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提交 d3f8c0ab 编写于 作者: R Rex Zhu 提交者： Alex Deucher
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drm/amd/powerplay: refine interface in struct pp_smumgr_func 

unify to use struct hwmgr as function parameter in
smumgr.
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
上级 e9c7577c
隐藏空白更改
内联 并排
Showing with 1225 addition and 1248 deletion
drivers/gpu/drm/amd/powerplay/amd_powerplay.c
浏览文件 @ d3f8c0ab
...@@ -83,7 +83,7 @@ static int pp_sw_init(void *handle) ...@@ -83,7 +83,7 @@ static int pp_sw_init(void *handle)
if (smumgr->smumgr_funcs->smu_init == NULL) if (smumgr->smumgr_funcs->smu_init == NULL)
return -EINVAL; return -EINVAL;
ret = smumgr->smumgr_funcs->smu_init(smumgr); ret = smumgr->smumgr_funcs->smu_init(pp_handle->hwmgr);
pr_info("amdgpu: powerplay sw initialized\n"); pr_info("amdgpu: powerplay sw initialized\n");
} }
...@@ -103,7 +103,7 @@ static int pp_sw_fini(void *handle) ...@@ -103,7 +103,7 @@ static int pp_sw_fini(void *handle)
if (smumgr->smumgr_funcs->smu_fini == NULL) if (smumgr->smumgr_funcs->smu_fini == NULL)
return -EINVAL; return -EINVAL;
ret = smumgr->smumgr_funcs->smu_fini(smumgr); ret = smumgr->smumgr_funcs->smu_fini(pp_handle->hwmgr);
} }
return ret; return ret;
} }
...@@ -122,9 +122,9 @@ static int pp_hw_init(void *handle) ...@@ -122,9 +122,9 @@ static int pp_hw_init(void *handle)
if (smumgr->smumgr_funcs->start_smu == NULL) if (smumgr->smumgr_funcs->start_smu == NULL)
return -EINVAL; return -EINVAL;
if(smumgr->smumgr_funcs->start_smu(smumgr)) { if(smumgr->smumgr_funcs->start_smu(pp_handle->hwmgr)) {
pr_err("smc start failed\n"); pr_err("smc start failed\n");
smumgr->smumgr_funcs->smu_fini(smumgr); smumgr->smumgr_funcs->smu_fini(pp_handle->hwmgr);
return -EINVAL;; return -EINVAL;;
} }
if (ret == PP_DPM_DISABLED) if (ret == PP_DPM_DISABLED)
...@@ -246,10 +246,10 @@ static int pp_resume(void *handle) ...@@ -246,10 +246,10 @@ static int pp_resume(void *handle)
if (smumgr->smumgr_funcs->start_smu == NULL) if (smumgr->smumgr_funcs->start_smu == NULL)
return -EINVAL; return -EINVAL;
ret = smumgr->smumgr_funcs->start_smu(smumgr); ret = smumgr->smumgr_funcs->start_smu(pp_handle->hwmgr);
if (ret) { if (ret) {
pr_err("smc start failed\n"); pr_err("smc start failed\n");
smumgr->smumgr_funcs->smu_fini(smumgr); smumgr->smumgr_funcs->smu_fini(pp_handle->hwmgr);
return ret; return ret;
} }
......
drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c
浏览文件 @ d3f8c0ab
...@@ -113,12 +113,12 @@ int cz_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable) ...@@ -113,12 +113,12 @@ int cz_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
PHM_PlatformCaps_UVDDPM)) { PHM_PlatformCaps_UVDDPM)) {
cz_hwmgr->dpm_flags |= DPMFlags_UVD_Enabled; cz_hwmgr->dpm_flags |= DPMFlags_UVD_Enabled;
dpm_features |= UVD_DPM_MASK; dpm_features |= UVD_DPM_MASK;
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_EnableAllSmuFeatures, dpm_features); PPSMC_MSG_EnableAllSmuFeatures, dpm_features);
} else { } else {
dpm_features |= UVD_DPM_MASK; dpm_features |= UVD_DPM_MASK;
cz_hwmgr->dpm_flags &= ~DPMFlags_UVD_Enabled; cz_hwmgr->dpm_flags &= ~DPMFlags_UVD_Enabled;
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_DisableAllSmuFeatures, dpm_features); PPSMC_MSG_DisableAllSmuFeatures, dpm_features);
} }
return 0; return 0;
...@@ -134,12 +134,12 @@ int cz_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable) ...@@ -134,12 +134,12 @@ int cz_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
PHM_PlatformCaps_VCEDPM)) { PHM_PlatformCaps_VCEDPM)) {
cz_hwmgr->dpm_flags |= DPMFlags_VCE_Enabled; cz_hwmgr->dpm_flags |= DPMFlags_VCE_Enabled;
dpm_features |= VCE_DPM_MASK; dpm_features |= VCE_DPM_MASK;
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_EnableAllSmuFeatures, dpm_features); PPSMC_MSG_EnableAllSmuFeatures, dpm_features);
} else { } else {
dpm_features |= VCE_DPM_MASK; dpm_features |= VCE_DPM_MASK;
cz_hwmgr->dpm_flags &= ~DPMFlags_VCE_Enabled; cz_hwmgr->dpm_flags &= ~DPMFlags_VCE_Enabled;
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_DisableAllSmuFeatures, dpm_features); PPSMC_MSG_DisableAllSmuFeatures, dpm_features);
} }
......
drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
浏览文件 @ d3f8c0ab
...@@ -162,8 +162,8 @@ static uint32_t cz_get_max_sclk_level(struct pp_hwmgr *hwmgr) ...@@ -162,8 +162,8 @@ static uint32_t cz_get_max_sclk_level(struct pp_hwmgr *hwmgr)
struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
if (cz_hwmgr->max_sclk_level == 0) { if (cz_hwmgr->max_sclk_level == 0) {
smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxSclkLevel); smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxSclkLevel);
cz_hwmgr->max_sclk_level = smum_get_argument(hwmgr->smumgr) + 1; cz_hwmgr->max_sclk_level = smum_get_argument(hwmgr) + 1;
} }
return cz_hwmgr->max_sclk_level; return cz_hwmgr->max_sclk_level;
...@@ -462,7 +462,7 @@ static int cz_upload_pptable_to_smu(struct pp_hwmgr *hwmgr) ...@@ -462,7 +462,7 @@ static int cz_upload_pptable_to_smu(struct pp_hwmgr *hwmgr)
if (!hwmgr->need_pp_table_upload) if (!hwmgr->need_pp_table_upload)
return 0; return 0;
ret = smum_download_powerplay_table(hwmgr->smumgr, &table); ret = smum_download_powerplay_table(hwmgr, &table);
PP_ASSERT_WITH_CODE((0 == ret && NULL != table), PP_ASSERT_WITH_CODE((0 == ret && NULL != table),
"Fail to get clock table from SMU!", return -EINVAL;); "Fail to get clock table from SMU!", return -EINVAL;);
...@@ -554,7 +554,7 @@ static int cz_upload_pptable_to_smu(struct pp_hwmgr *hwmgr) ...@@ -554,7 +554,7 @@ static int cz_upload_pptable_to_smu(struct pp_hwmgr *hwmgr)
(uint8_t)dividers.pll_post_divider; (uint8_t)dividers.pll_post_divider;
} }
ret = smum_upload_powerplay_table(hwmgr->smumgr); ret = smum_upload_powerplay_table(hwmgr);
return ret; return ret;
} }
...@@ -598,8 +598,8 @@ static int cz_init_uvd_limit(struct pp_hwmgr *hwmgr) ...@@ -598,8 +598,8 @@ static int cz_init_uvd_limit(struct pp_hwmgr *hwmgr)
cz_hwmgr->uvd_dpm.soft_min_clk = 0; cz_hwmgr->uvd_dpm.soft_min_clk = 0;
cz_hwmgr->uvd_dpm.hard_min_clk = 0; cz_hwmgr->uvd_dpm.hard_min_clk = 0;
smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxUvdLevel); smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxUvdLevel);
level = smum_get_argument(hwmgr->smumgr); level = smum_get_argument(hwmgr);
if (level < table->count) if (level < table->count)
clock = table->entries[level].vclk; clock = table->entries[level].vclk;
...@@ -625,8 +625,8 @@ static int cz_init_vce_limit(struct pp_hwmgr *hwmgr) ...@@ -625,8 +625,8 @@ static int cz_init_vce_limit(struct pp_hwmgr *hwmgr)
cz_hwmgr->vce_dpm.soft_min_clk = 0; cz_hwmgr->vce_dpm.soft_min_clk = 0;
cz_hwmgr->vce_dpm.hard_min_clk = 0; cz_hwmgr->vce_dpm.hard_min_clk = 0;
smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxEclkLevel); smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxEclkLevel);
level = smum_get_argument(hwmgr->smumgr); level = smum_get_argument(hwmgr);
if (level < table->count) if (level < table->count)
clock = table->entries[level].ecclk; clock = table->entries[level].ecclk;
...@@ -652,8 +652,8 @@ static int cz_init_acp_limit(struct pp_hwmgr *hwmgr) ...@@ -652,8 +652,8 @@ static int cz_init_acp_limit(struct pp_hwmgr *hwmgr)
cz_hwmgr->acp_dpm.soft_min_clk = 0; cz_hwmgr->acp_dpm.soft_min_clk = 0;
cz_hwmgr->acp_dpm.hard_min_clk = 0; cz_hwmgr->acp_dpm.hard_min_clk = 0;
smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxAclkLevel); smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxAclkLevel);
level = smum_get_argument(hwmgr->smumgr); level = smum_get_argument(hwmgr);
if (level < table->count) if (level < table->count)
clock = table->entries[level].acpclk; clock = table->entries[level].acpclk;
...@@ -709,7 +709,7 @@ static int cz_update_sclk_limit(struct pp_hwmgr *hwmgr) ...@@ -709,7 +709,7 @@ static int cz_update_sclk_limit(struct pp_hwmgr *hwmgr)
if (cz_hwmgr->sclk_dpm.hard_min_clk != clock) { if (cz_hwmgr->sclk_dpm.hard_min_clk != clock) {
cz_hwmgr->sclk_dpm.hard_min_clk = clock; cz_hwmgr->sclk_dpm.hard_min_clk = clock;
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSclkHardMin, PPSMC_MSG_SetSclkHardMin,
cz_get_sclk_level(hwmgr, cz_get_sclk_level(hwmgr,
cz_hwmgr->sclk_dpm.hard_min_clk, cz_hwmgr->sclk_dpm.hard_min_clk,
...@@ -735,7 +735,7 @@ static int cz_update_sclk_limit(struct pp_hwmgr *hwmgr) ...@@ -735,7 +735,7 @@ static int cz_update_sclk_limit(struct pp_hwmgr *hwmgr)
if (cz_hwmgr->sclk_dpm.soft_min_clk != clock) { if (cz_hwmgr->sclk_dpm.soft_min_clk != clock) {
cz_hwmgr->sclk_dpm.soft_min_clk = clock; cz_hwmgr->sclk_dpm.soft_min_clk = clock;
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSclkSoftMin, PPSMC_MSG_SetSclkSoftMin,
cz_get_sclk_level(hwmgr, cz_get_sclk_level(hwmgr,
cz_hwmgr->sclk_dpm.soft_min_clk, cz_hwmgr->sclk_dpm.soft_min_clk,
...@@ -746,7 +746,7 @@ static int cz_update_sclk_limit(struct pp_hwmgr *hwmgr) ...@@ -746,7 +746,7 @@ static int cz_update_sclk_limit(struct pp_hwmgr *hwmgr)
PHM_PlatformCaps_StablePState) && PHM_PlatformCaps_StablePState) &&
cz_hwmgr->sclk_dpm.soft_max_clk != clock) { cz_hwmgr->sclk_dpm.soft_max_clk != clock) {
cz_hwmgr->sclk_dpm.soft_max_clk = clock; cz_hwmgr->sclk_dpm.soft_max_clk = clock;
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSclkSoftMax, PPSMC_MSG_SetSclkSoftMax,
cz_get_sclk_level(hwmgr, cz_get_sclk_level(hwmgr,
cz_hwmgr->sclk_dpm.soft_max_clk, cz_hwmgr->sclk_dpm.soft_max_clk,
...@@ -766,7 +766,7 @@ static int cz_set_deep_sleep_sclk_threshold(struct pp_hwmgr *hwmgr) ...@@ -766,7 +766,7 @@ static int cz_set_deep_sleep_sclk_threshold(struct pp_hwmgr *hwmgr)
PP_DBG_LOG("Setting Deep Sleep Clock: %d\n", clks); PP_DBG_LOG("Setting Deep Sleep Clock: %d\n", clks);
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetMinDeepSleepSclk, PPSMC_MSG_SetMinDeepSleepSclk,
clks); clks);
} }
...@@ -779,7 +779,7 @@ static int cz_set_watermark_threshold(struct pp_hwmgr *hwmgr) ...@@ -779,7 +779,7 @@ static int cz_set_watermark_threshold(struct pp_hwmgr *hwmgr)
struct cz_hwmgr *cz_hwmgr = struct cz_hwmgr *cz_hwmgr =
(struct cz_hwmgr *)(hwmgr->backend); (struct cz_hwmgr *)(hwmgr->backend);
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetWatermarkFrequency, PPSMC_MSG_SetWatermarkFrequency,
cz_hwmgr->sclk_dpm.soft_max_clk); cz_hwmgr->sclk_dpm.soft_max_clk);
...@@ -794,13 +794,13 @@ static int cz_nbdpm_pstate_enable_disable(struct pp_hwmgr *hwmgr, bool enable, b ...@@ -794,13 +794,13 @@ static int cz_nbdpm_pstate_enable_disable(struct pp_hwmgr *hwmgr, bool enable, b
if (enable) { if (enable) {
PP_DBG_LOG("enable Low Memory PState.\n"); PP_DBG_LOG("enable Low Memory PState.\n");
return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, return smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_EnableLowMemoryPstate, PPSMC_MSG_EnableLowMemoryPstate,
(lock ? 1 : 0)); (lock ? 1 : 0));
} else { } else {
PP_DBG_LOG("disable Low Memory PState.\n"); PP_DBG_LOG("disable Low Memory PState.\n");
return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, return smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_DisableLowMemoryPstate, PPSMC_MSG_DisableLowMemoryPstate,
(lock ? 1 : 0)); (lock ? 1 : 0));
} }
...@@ -820,7 +820,7 @@ static int cz_disable_nb_dpm(struct pp_hwmgr *hwmgr) ...@@ -820,7 +820,7 @@ static int cz_disable_nb_dpm(struct pp_hwmgr *hwmgr)
cz_nbdpm_pstate_enable_disable(hwmgr, true, true); cz_nbdpm_pstate_enable_disable(hwmgr, true, true);
dpm_features |= NB_DPM_MASK; dpm_features |= NB_DPM_MASK;
ret = smum_send_msg_to_smc_with_parameter( ret = smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr, hwmgr,
PPSMC_MSG_DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures,
dpm_features); dpm_features);
if (ret == 0) if (ret == 0)
...@@ -841,7 +841,7 @@ static int cz_enable_nb_dpm(struct pp_hwmgr *hwmgr) ...@@ -841,7 +841,7 @@ static int cz_enable_nb_dpm(struct pp_hwmgr *hwmgr)
PP_DBG_LOG("enabling ALL SMU features.\n"); PP_DBG_LOG("enabling ALL SMU features.\n");
dpm_features |= NB_DPM_MASK; dpm_features |= NB_DPM_MASK;
ret = smum_send_msg_to_smc_with_parameter( ret = smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr, hwmgr,
PPSMC_MSG_EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures,
dpm_features); dpm_features);
if (ret == 0) if (ret == 0)
...@@ -968,7 +968,7 @@ static int cz_start_dpm(struct pp_hwmgr *hwmgr) ...@@ -968,7 +968,7 @@ static int cz_start_dpm(struct pp_hwmgr *hwmgr)
cz_hwmgr->dpm_flags |= DPMFlags_SCLK_Enabled; cz_hwmgr->dpm_flags |= DPMFlags_SCLK_Enabled;
dpm_features |= SCLK_DPM_MASK; dpm_features |= SCLK_DPM_MASK;
ret = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, ret = smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures,
dpm_features); dpm_features);
...@@ -984,7 +984,7 @@ static int cz_stop_dpm(struct pp_hwmgr *hwmgr) ...@@ -984,7 +984,7 @@ static int cz_stop_dpm(struct pp_hwmgr *hwmgr)
if (cz_hwmgr->dpm_flags & DPMFlags_SCLK_Enabled) { if (cz_hwmgr->dpm_flags & DPMFlags_SCLK_Enabled) {
dpm_features |= SCLK_DPM_MASK; dpm_features |= SCLK_DPM_MASK;
cz_hwmgr->dpm_flags &= ~DPMFlags_SCLK_Enabled; cz_hwmgr->dpm_flags &= ~DPMFlags_SCLK_Enabled;
ret = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, ret = smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures,
dpm_features); dpm_features);
} }
...@@ -998,13 +998,13 @@ static int cz_program_bootup_state(struct pp_hwmgr *hwmgr) ...@@ -998,13 +998,13 @@ static int cz_program_bootup_state(struct pp_hwmgr *hwmgr)
cz_hwmgr->sclk_dpm.soft_min_clk = cz_hwmgr->sys_info.bootup_engine_clock; cz_hwmgr->sclk_dpm.soft_min_clk = cz_hwmgr->sys_info.bootup_engine_clock;
cz_hwmgr->sclk_dpm.soft_max_clk = cz_hwmgr->sys_info.bootup_engine_clock; cz_hwmgr->sclk_dpm.soft_max_clk = cz_hwmgr->sys_info.bootup_engine_clock;
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSclkSoftMin, PPSMC_MSG_SetSclkSoftMin,
cz_get_sclk_level(hwmgr, cz_get_sclk_level(hwmgr,
cz_hwmgr->sclk_dpm.soft_min_clk, cz_hwmgr->sclk_dpm.soft_min_clk,
PPSMC_MSG_SetSclkSoftMin)); PPSMC_MSG_SetSclkSoftMin));
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSclkSoftMax, PPSMC_MSG_SetSclkSoftMax,
cz_get_sclk_level(hwmgr, cz_get_sclk_level(hwmgr,
cz_hwmgr->sclk_dpm.soft_max_clk, cz_hwmgr->sclk_dpm.soft_max_clk,
...@@ -1026,9 +1026,9 @@ static bool cz_dpm_check_smu_features(struct pp_hwmgr *hwmgr, ...@@ -1026,9 +1026,9 @@ static bool cz_dpm_check_smu_features(struct pp_hwmgr *hwmgr,
int result; int result;
unsigned long features; unsigned long features;
result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_GetFeatureStatus, 0); result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetFeatureStatus, 0);
if (result == 0) { if (result == 0) {
features = smum_get_argument(hwmgr->smumgr); features = smum_get_argument(hwmgr);
if (features & check_feature) if (features & check_feature)
return true; return true;
} }
...@@ -1178,13 +1178,13 @@ static int cz_phm_force_dpm_highest(struct pp_hwmgr *hwmgr) ...@@ -1178,13 +1178,13 @@ static int cz_phm_force_dpm_highest(struct pp_hwmgr *hwmgr)
{ {
struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSclkSoftMin, PPSMC_MSG_SetSclkSoftMin,
cz_get_sclk_level(hwmgr, cz_get_sclk_level(hwmgr,
cz_hwmgr->sclk_dpm.soft_max_clk, cz_hwmgr->sclk_dpm.soft_max_clk,
PPSMC_MSG_SetSclkSoftMin)); PPSMC_MSG_SetSclkSoftMin));
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSclkSoftMax, PPSMC_MSG_SetSclkSoftMax,
cz_get_sclk_level(hwmgr, cz_get_sclk_level(hwmgr,
cz_hwmgr->sclk_dpm.soft_max_clk, cz_hwmgr->sclk_dpm.soft_max_clk,
...@@ -1216,13 +1216,13 @@ static int cz_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr) ...@@ -1216,13 +1216,13 @@ static int cz_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
cz_hwmgr->sclk_dpm.soft_max_clk = clock; cz_hwmgr->sclk_dpm.soft_max_clk = clock;
cz_hwmgr->sclk_dpm.hard_max_clk = clock; cz_hwmgr->sclk_dpm.hard_max_clk = clock;
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSclkSoftMin, PPSMC_MSG_SetSclkSoftMin,
cz_get_sclk_level(hwmgr, cz_get_sclk_level(hwmgr,
cz_hwmgr->sclk_dpm.soft_min_clk, cz_hwmgr->sclk_dpm.soft_min_clk,
PPSMC_MSG_SetSclkSoftMin)); PPSMC_MSG_SetSclkSoftMin));
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSclkSoftMax, PPSMC_MSG_SetSclkSoftMax,
cz_get_sclk_level(hwmgr, cz_get_sclk_level(hwmgr,
cz_hwmgr->sclk_dpm.soft_max_clk, cz_hwmgr->sclk_dpm.soft_max_clk,
...@@ -1235,13 +1235,13 @@ static int cz_phm_force_dpm_lowest(struct pp_hwmgr *hwmgr) ...@@ -1235,13 +1235,13 @@ static int cz_phm_force_dpm_lowest(struct pp_hwmgr *hwmgr)
{ {
struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSclkSoftMax, PPSMC_MSG_SetSclkSoftMax,
cz_get_sclk_level(hwmgr, cz_get_sclk_level(hwmgr,
cz_hwmgr->sclk_dpm.soft_min_clk, cz_hwmgr->sclk_dpm.soft_min_clk,
PPSMC_MSG_SetSclkSoftMax)); PPSMC_MSG_SetSclkSoftMax));
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSclkSoftMin, PPSMC_MSG_SetSclkSoftMin,
cz_get_sclk_level(hwmgr, cz_get_sclk_level(hwmgr,
cz_hwmgr->sclk_dpm.soft_min_clk, cz_hwmgr->sclk_dpm.soft_min_clk,
...@@ -1281,7 +1281,7 @@ int cz_dpm_powerdown_uvd(struct pp_hwmgr *hwmgr) ...@@ -1281,7 +1281,7 @@ int cz_dpm_powerdown_uvd(struct pp_hwmgr *hwmgr)
{ {
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_UVDPowerGating)) PHM_PlatformCaps_UVDPowerGating))
return smum_send_msg_to_smc(hwmgr->smumgr, return smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_UVDPowerOFF); PPSMC_MSG_UVDPowerOFF);
return 0; return 0;
} }
...@@ -1293,11 +1293,11 @@ int cz_dpm_powerup_uvd(struct pp_hwmgr *hwmgr) ...@@ -1293,11 +1293,11 @@ int cz_dpm_powerup_uvd(struct pp_hwmgr *hwmgr)
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_UVDDynamicPowerGating)) { PHM_PlatformCaps_UVDDynamicPowerGating)) {
return smum_send_msg_to_smc_with_parameter( return smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr, hwmgr,
PPSMC_MSG_UVDPowerON, 1); PPSMC_MSG_UVDPowerON, 1);
} else { } else {
return smum_send_msg_to_smc_with_parameter( return smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr, hwmgr,
PPSMC_MSG_UVDPowerON, 0); PPSMC_MSG_UVDPowerON, 0);
} }
} }
...@@ -1319,7 +1319,7 @@ int cz_dpm_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate) ...@@ -1319,7 +1319,7 @@ int cz_dpm_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
cz_hwmgr->uvd_dpm.hard_min_clk = cz_hwmgr->uvd_dpm.hard_min_clk =
ptable->entries[ptable->count - 1].vclk; ptable->entries[ptable->count - 1].vclk;
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetUvdHardMin, PPSMC_MSG_SetUvdHardMin,
cz_get_uvd_level(hwmgr, cz_get_uvd_level(hwmgr,
cz_hwmgr->uvd_dpm.hard_min_clk, cz_hwmgr->uvd_dpm.hard_min_clk,
...@@ -1349,7 +1349,7 @@ int cz_dpm_update_vce_dpm(struct pp_hwmgr *hwmgr) ...@@ -1349,7 +1349,7 @@ int cz_dpm_update_vce_dpm(struct pp_hwmgr *hwmgr)
cz_hwmgr->vce_dpm.hard_min_clk = cz_hwmgr->vce_dpm.hard_min_clk =
ptable->entries[ptable->count - 1].ecclk; ptable->entries[ptable->count - 1].ecclk;
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetEclkHardMin, PPSMC_MSG_SetEclkHardMin,
cz_get_eclk_level(hwmgr, cz_get_eclk_level(hwmgr,
cz_hwmgr->vce_dpm.hard_min_clk, cz_hwmgr->vce_dpm.hard_min_clk,
...@@ -1357,15 +1357,15 @@ int cz_dpm_update_vce_dpm(struct pp_hwmgr *hwmgr) ...@@ -1357,15 +1357,15 @@ int cz_dpm_update_vce_dpm(struct pp_hwmgr *hwmgr)
} else { } else {
/*Program HardMin based on the vce_arbiter.ecclk */ /*Program HardMin based on the vce_arbiter.ecclk */
if (hwmgr->vce_arbiter.ecclk == 0) { if (hwmgr->vce_arbiter.ecclk == 0) {
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetEclkHardMin, 0); PPSMC_MSG_SetEclkHardMin, 0);
/* disable ECLK DPM 0. Otherwise VCE could hang if /* disable ECLK DPM 0. Otherwise VCE could hang if
* switching SCLK from DPM 0 to 6/7 */ * switching SCLK from DPM 0 to 6/7 */
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetEclkSoftMin, 1); PPSMC_MSG_SetEclkSoftMin, 1);
} else { } else {
cz_hwmgr->vce_dpm.hard_min_clk = hwmgr->vce_arbiter.ecclk; cz_hwmgr->vce_dpm.hard_min_clk = hwmgr->vce_arbiter.ecclk;
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetEclkHardMin, PPSMC_MSG_SetEclkHardMin,
cz_get_eclk_level(hwmgr, cz_get_eclk_level(hwmgr,
cz_hwmgr->vce_dpm.hard_min_clk, cz_hwmgr->vce_dpm.hard_min_clk,
...@@ -1379,7 +1379,7 @@ int cz_dpm_powerdown_vce(struct pp_hwmgr *hwmgr) ...@@ -1379,7 +1379,7 @@ int cz_dpm_powerdown_vce(struct pp_hwmgr *hwmgr)
{ {
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_VCEPowerGating)) PHM_PlatformCaps_VCEPowerGating))
return smum_send_msg_to_smc(hwmgr->smumgr, return smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_VCEPowerOFF); PPSMC_MSG_VCEPowerOFF);
return 0; return 0;
} }
...@@ -1388,7 +1388,7 @@ int cz_dpm_powerup_vce(struct pp_hwmgr *hwmgr) ...@@ -1388,7 +1388,7 @@ int cz_dpm_powerup_vce(struct pp_hwmgr *hwmgr)
{ {
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_VCEPowerGating)) PHM_PlatformCaps_VCEPowerGating))
return smum_send_msg_to_smc(hwmgr->smumgr, return smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_VCEPowerON); PPSMC_MSG_VCEPowerON);
return 0; return 0;
} }
...@@ -1538,7 +1538,7 @@ static void cz_hw_print_display_cfg( ...@@ -1538,7 +1538,7 @@ static void cz_hw_print_display_cfg(
PP_DBG_LOG("SetDisplaySizePowerParams data: 0x%X\n", PP_DBG_LOG("SetDisplaySizePowerParams data: 0x%X\n",
data); data);
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetDisplaySizePowerParams, PPSMC_MSG_SetDisplaySizePowerParams,
data); data);
} }
...@@ -1603,10 +1603,10 @@ static int cz_force_clock_level(struct pp_hwmgr *hwmgr, ...@@ -1603,10 +1603,10 @@ static int cz_force_clock_level(struct pp_hwmgr *hwmgr,
switch (type) { switch (type) {
case PP_SCLK: case PP_SCLK:
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSclkSoftMin, PPSMC_MSG_SetSclkSoftMin,
mask); mask);
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSclkSoftMax, PPSMC_MSG_SetSclkSoftMax,
mask); mask);
break; break;
...@@ -1848,7 +1848,7 @@ static int cz_read_sensor(struct pp_hwmgr *hwmgr, int idx, ...@@ -1848,7 +1848,7 @@ static int cz_read_sensor(struct pp_hwmgr *hwmgr, int idx,
*((uint32_t *)value) = 0; *((uint32_t *)value) = 0;
return 0; return 0;
case AMDGPU_PP_SENSOR_GPU_LOAD: case AMDGPU_PP_SENSOR_GPU_LOAD:
result = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetAverageGraphicsActivity); result = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetAverageGraphicsActivity);
if (0 == result) { if (0 == result) {
activity_percent = cgs_read_register(hwmgr->device, mmSMU_MP1_SRBM2P_ARG_0); activity_percent = cgs_read_register(hwmgr->device, mmSMU_MP1_SRBM2P_ARG_0);
activity_percent = activity_percent > 100 ? 100 : activity_percent; activity_percent = activity_percent > 100 ? 100 : activity_percent;
......
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
浏览文件 @ d3f8c0ab
...@@ -818,7 +818,7 @@ void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr) ...@@ -818,7 +818,7 @@ void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr)
for (i = 0; i < vddc_table->count; i++) { for (i = 0; i < vddc_table->count; i++) {
if (req_vddc <= vddc_table->entries[i].vddc) { if (req_vddc <= vddc_table->entries[i].vddc) {
req_volt = (((uint32_t)vddc_table->entries[i].vddc) * VOLTAGE_SCALE); req_volt = (((uint32_t)vddc_table->entries[i].vddc) * VOLTAGE_SCALE);
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_VddC_Request, req_volt); PPSMC_MSG_VddC_Request, req_volt);
return; return;
} }
......
drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
浏览文件 @ d3f8c0ab
...@@ -174,33 +174,33 @@ static int rv_set_clock_limit(struct pp_hwmgr *hwmgr, const void *input) ...@@ -174,33 +174,33 @@ static int rv_set_clock_limit(struct pp_hwmgr *hwmgr, const void *input)
((hwmgr->uvd_arbiter.dclk_soft_min / 100) != rv_data->dclk_soft_min)) { ((hwmgr->uvd_arbiter.dclk_soft_min / 100) != rv_data->dclk_soft_min)) {
rv_data->vclk_soft_min = hwmgr->uvd_arbiter.vclk_soft_min / 100; rv_data->vclk_soft_min = hwmgr->uvd_arbiter.vclk_soft_min / 100;
rv_data->dclk_soft_min = hwmgr->uvd_arbiter.dclk_soft_min / 100; rv_data->dclk_soft_min = hwmgr->uvd_arbiter.dclk_soft_min / 100;
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn,
(rv_data->vclk_soft_min << 16) | rv_data->vclk_soft_min); (rv_data->vclk_soft_min << 16) | rv_data->vclk_soft_min);
} }
if((hwmgr->gfx_arbiter.sclk_hard_min != 0) && if((hwmgr->gfx_arbiter.sclk_hard_min != 0) &&
((hwmgr->gfx_arbiter.sclk_hard_min / 100) != rv_data->soc_actual_hard_min_freq)) { ((hwmgr->gfx_arbiter.sclk_hard_min / 100) != rv_data->soc_actual_hard_min_freq)) {
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetHardMinSocclkByFreq, PPSMC_MSG_SetHardMinSocclkByFreq,
hwmgr->gfx_arbiter.sclk_hard_min / 100); hwmgr->gfx_arbiter.sclk_hard_min / 100);
rv_read_arg_from_smc(hwmgr->smumgr, &rv_data->soc_actual_hard_min_freq); rv_read_arg_from_smc(hwmgr, &rv_data->soc_actual_hard_min_freq);
} }
if ((hwmgr->gfx_arbiter.gfxclk != 0) && if ((hwmgr->gfx_arbiter.gfxclk != 0) &&
(rv_data->gfx_actual_soft_min_freq != (hwmgr->gfx_arbiter.gfxclk))) { (rv_data->gfx_actual_soft_min_freq != (hwmgr->gfx_arbiter.gfxclk))) {
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetMinVideoGfxclkFreq, PPSMC_MSG_SetMinVideoGfxclkFreq,
hwmgr->gfx_arbiter.gfxclk / 100); hwmgr->gfx_arbiter.gfxclk / 100);
rv_read_arg_from_smc(hwmgr->smumgr, &rv_data->gfx_actual_soft_min_freq); rv_read_arg_from_smc(hwmgr, &rv_data->gfx_actual_soft_min_freq);
} }
if ((hwmgr->gfx_arbiter.fclk != 0) && if ((hwmgr->gfx_arbiter.fclk != 0) &&
(rv_data->fabric_actual_soft_min_freq != (hwmgr->gfx_arbiter.fclk / 100))) { (rv_data->fabric_actual_soft_min_freq != (hwmgr->gfx_arbiter.fclk / 100))) {
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetMinVideoFclkFreq, PPSMC_MSG_SetMinVideoFclkFreq,
hwmgr->gfx_arbiter.fclk / 100); hwmgr->gfx_arbiter.fclk / 100);
rv_read_arg_from_smc(hwmgr->smumgr, &rv_data->fabric_actual_soft_min_freq); rv_read_arg_from_smc(hwmgr, &rv_data->fabric_actual_soft_min_freq);
} }
return 0; return 0;
...@@ -212,7 +212,7 @@ static int rv_set_deep_sleep_dcefclk(struct pp_hwmgr *hwmgr, uint32_t clock) ...@@ -212,7 +212,7 @@ static int rv_set_deep_sleep_dcefclk(struct pp_hwmgr *hwmgr, uint32_t clock)
if (rv_data->need_min_deep_sleep_dcefclk && rv_data->deep_sleep_dcefclk != clock/100) { if (rv_data->need_min_deep_sleep_dcefclk && rv_data->deep_sleep_dcefclk != clock/100) {
rv_data->deep_sleep_dcefclk = clock/100; rv_data->deep_sleep_dcefclk = clock/100;
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetMinDeepSleepDcefclk, PPSMC_MSG_SetMinDeepSleepDcefclk,
rv_data->deep_sleep_dcefclk); rv_data->deep_sleep_dcefclk);
} }
...@@ -225,7 +225,7 @@ static int rv_set_active_display_count(struct pp_hwmgr *hwmgr, uint32_t count) ...@@ -225,7 +225,7 @@ static int rv_set_active_display_count(struct pp_hwmgr *hwmgr, uint32_t count)
if (rv_data->num_active_display != count) { if (rv_data->num_active_display != count) {
rv_data->num_active_display = count; rv_data->num_active_display = count;
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetDisplayCount, PPSMC_MSG_SetDisplayCount,
rv_data->num_active_display); rv_data->num_active_display);
} }
...@@ -277,7 +277,7 @@ static int rv_disable_gfx_off(struct pp_hwmgr *hwmgr) ...@@ -277,7 +277,7 @@ static int rv_disable_gfx_off(struct pp_hwmgr *hwmgr)
struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend); struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
if (rv_data->gfx_off_controled_by_driver) if (rv_data->gfx_off_controled_by_driver)
smum_send_msg_to_smc(hwmgr->smumgr, smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_DisableGfxOff); PPSMC_MSG_DisableGfxOff);
return 0; return 0;
...@@ -293,7 +293,7 @@ static int rv_enable_gfx_off(struct pp_hwmgr *hwmgr) ...@@ -293,7 +293,7 @@ static int rv_enable_gfx_off(struct pp_hwmgr *hwmgr)
struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend); struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
if (rv_data->gfx_off_controled_by_driver) if (rv_data->gfx_off_controled_by_driver)
smum_send_msg_to_smc(hwmgr->smumgr, smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_EnableGfxOff); PPSMC_MSG_EnableGfxOff);
return 0; return 0;
...@@ -383,7 +383,7 @@ static int rv_populate_clock_table(struct pp_hwmgr *hwmgr) ...@@ -383,7 +383,7 @@ static int rv_populate_clock_table(struct pp_hwmgr *hwmgr)
DpmClocks_t *table = &(rv_data->clock_table); DpmClocks_t *table = &(rv_data->clock_table);
struct rv_clock_voltage_information *pinfo = &(rv_data->clock_vol_info); struct rv_clock_voltage_information *pinfo = &(rv_data->clock_vol_info);
result = rv_copy_table_from_smc(hwmgr->smumgr, (uint8_t *)table, CLOCKTABLE); result = rv_copy_table_from_smc(hwmgr, (uint8_t *)table, CLOCKTABLE);
PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE((0 == result),
"Attempt to copy clock table from smc failed", "Attempt to copy clock table from smc failed",
...@@ -799,7 +799,7 @@ int rv_display_clock_voltage_request(struct pp_hwmgr *hwmgr, ...@@ -799,7 +799,7 @@ int rv_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
return -EINVAL; return -EINVAL;
} }
result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, msg, result = smum_send_msg_to_smc_with_parameter(hwmgr, msg,
clk_freq); clk_freq);
return result; return result;
......
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
浏览文件 @ d3f8c0ab
...@@ -27,21 +27,21 @@ ...@@ -27,21 +27,21 @@
static int smu7_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable) static int smu7_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
{ {
return smum_send_msg_to_smc(hwmgr->smumgr, enable ? return smum_send_msg_to_smc(hwmgr, enable ?
PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Enable :
PPSMC_MSG_UVDDPM_Disable); PPSMC_MSG_UVDDPM_Disable);
} }
static int smu7_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable) static int smu7_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
{ {
return smum_send_msg_to_smc(hwmgr->smumgr, enable ? return smum_send_msg_to_smc(hwmgr, enable ?
PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Enable :
PPSMC_MSG_VCEDPM_Disable); PPSMC_MSG_VCEDPM_Disable);
} }
static int smu7_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable) static int smu7_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable)
{ {
return smum_send_msg_to_smc(hwmgr->smumgr, enable ? return smum_send_msg_to_smc(hwmgr, enable ?
PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Enable :
PPSMC_MSG_SAMUDPM_Disable); PPSMC_MSG_SAMUDPM_Disable);
} }
...@@ -70,7 +70,7 @@ static int smu7_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate) ...@@ -70,7 +70,7 @@ static int smu7_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate)
int smu7_powerdown_uvd(struct pp_hwmgr *hwmgr) int smu7_powerdown_uvd(struct pp_hwmgr *hwmgr)
{ {
if (phm_cf_want_uvd_power_gating(hwmgr)) if (phm_cf_want_uvd_power_gating(hwmgr))
return smum_send_msg_to_smc(hwmgr->smumgr, return smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_UVDPowerOFF); PPSMC_MSG_UVDPowerOFF);
return 0; return 0;
} }
...@@ -80,10 +80,10 @@ static int smu7_powerup_uvd(struct pp_hwmgr *hwmgr) ...@@ -80,10 +80,10 @@ static int smu7_powerup_uvd(struct pp_hwmgr *hwmgr)
if (phm_cf_want_uvd_power_gating(hwmgr)) { if (phm_cf_want_uvd_power_gating(hwmgr)) {
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_UVDDynamicPowerGating)) { PHM_PlatformCaps_UVDDynamicPowerGating)) {
return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, return smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_UVDPowerON, 1); PPSMC_MSG_UVDPowerON, 1);
} else { } else {
return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, return smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_UVDPowerON, 0); PPSMC_MSG_UVDPowerON, 0);
} }
} }
...@@ -94,7 +94,7 @@ static int smu7_powerup_uvd(struct pp_hwmgr *hwmgr) ...@@ -94,7 +94,7 @@ static int smu7_powerup_uvd(struct pp_hwmgr *hwmgr)
static int smu7_powerdown_vce(struct pp_hwmgr *hwmgr) static int smu7_powerdown_vce(struct pp_hwmgr *hwmgr)
{ {
if (phm_cf_want_vce_power_gating(hwmgr)) if (phm_cf_want_vce_power_gating(hwmgr))
return smum_send_msg_to_smc(hwmgr->smumgr, return smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_VCEPowerOFF); PPSMC_MSG_VCEPowerOFF);
return 0; return 0;
} }
...@@ -102,7 +102,7 @@ static int smu7_powerdown_vce(struct pp_hwmgr *hwmgr) ...@@ -102,7 +102,7 @@ static int smu7_powerdown_vce(struct pp_hwmgr *hwmgr)
static int smu7_powerup_vce(struct pp_hwmgr *hwmgr) static int smu7_powerup_vce(struct pp_hwmgr *hwmgr)
{ {
if (phm_cf_want_vce_power_gating(hwmgr)) if (phm_cf_want_vce_power_gating(hwmgr))
return smum_send_msg_to_smc(hwmgr->smumgr, return smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_VCEPowerON); PPSMC_MSG_VCEPowerON);
return 0; return 0;
} }
...@@ -111,7 +111,7 @@ static int smu7_powerdown_samu(struct pp_hwmgr *hwmgr) ...@@ -111,7 +111,7 @@ static int smu7_powerdown_samu(struct pp_hwmgr *hwmgr)
{ {
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SamuPowerGating)) PHM_PlatformCaps_SamuPowerGating))
return smum_send_msg_to_smc(hwmgr->smumgr, return smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_SAMPowerOFF); PPSMC_MSG_SAMPowerOFF);
return 0; return 0;
} }
...@@ -120,7 +120,7 @@ static int smu7_powerup_samu(struct pp_hwmgr *hwmgr) ...@@ -120,7 +120,7 @@ static int smu7_powerup_samu(struct pp_hwmgr *hwmgr)
{ {
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SamuPowerGating)) PHM_PlatformCaps_SamuPowerGating))
return smum_send_msg_to_smc(hwmgr->smumgr, return smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_SAMPowerON); PPSMC_MSG_SAMPowerON);
return 0; return 0;
} }
...@@ -235,7 +235,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, ...@@ -235,7 +235,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
value = CG_GFX_CGCG_MASK; value = CG_GFX_CGCG_MASK;
if (smum_send_msg_to_smc_with_parameter( if (smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr, msg, value)) hwmgr, msg, value))
return -EINVAL; return -EINVAL;
} }
if (PP_STATE_SUPPORT_LS & *msg_id) { if (PP_STATE_SUPPORT_LS & *msg_id) {
...@@ -245,7 +245,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, ...@@ -245,7 +245,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
value = CG_GFX_CGLS_MASK; value = CG_GFX_CGLS_MASK;
if (smum_send_msg_to_smc_with_parameter( if (smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr, msg, value)) hwmgr, msg, value))
return -EINVAL; return -EINVAL;
} }
break; break;
...@@ -258,7 +258,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, ...@@ -258,7 +258,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
value = CG_GFX_3DCG_MASK; value = CG_GFX_3DCG_MASK;
if (smum_send_msg_to_smc_with_parameter( if (smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr, msg, value)) hwmgr, msg, value))
return -EINVAL; return -EINVAL;
} }
...@@ -269,7 +269,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, ...@@ -269,7 +269,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
value = CG_GFX_3DLS_MASK; value = CG_GFX_3DLS_MASK;
if (smum_send_msg_to_smc_with_parameter( if (smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr, msg, value)) hwmgr, msg, value))
return -EINVAL; return -EINVAL;
} }
break; break;
...@@ -282,7 +282,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, ...@@ -282,7 +282,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
value = CG_GFX_RLC_LS_MASK; value = CG_GFX_RLC_LS_MASK;
if (smum_send_msg_to_smc_with_parameter( if (smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr, msg, value)) hwmgr, msg, value))
return -EINVAL; return -EINVAL;
} }
break; break;
...@@ -295,7 +295,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, ...@@ -295,7 +295,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
value = CG_GFX_CP_LS_MASK; value = CG_GFX_CP_LS_MASK;
if (smum_send_msg_to_smc_with_parameter( if (smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr, msg, value)) hwmgr, msg, value))
return -EINVAL; return -EINVAL;
} }
break; break;
...@@ -309,7 +309,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, ...@@ -309,7 +309,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
CG_GFX_OTHERS_MGCG_MASK); CG_GFX_OTHERS_MGCG_MASK);
if (smum_send_msg_to_smc_with_parameter( if (smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr, msg, value)) hwmgr, msg, value))
return -EINVAL; return -EINVAL;
} }
break; break;
...@@ -329,7 +329,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, ...@@ -329,7 +329,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
value = CG_SYS_BIF_MGCG_MASK; value = CG_SYS_BIF_MGCG_MASK;
if (smum_send_msg_to_smc_with_parameter( if (smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr, msg, value)) hwmgr, msg, value))
return -EINVAL; return -EINVAL;
} }
if (PP_STATE_SUPPORT_LS & *msg_id) { if (PP_STATE_SUPPORT_LS & *msg_id) {
...@@ -339,7 +339,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, ...@@ -339,7 +339,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
value = CG_SYS_BIF_MGLS_MASK; value = CG_SYS_BIF_MGLS_MASK;
if (smum_send_msg_to_smc_with_parameter( if (smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr, msg, value)) hwmgr, msg, value))
return -EINVAL; return -EINVAL;
} }
break; break;
...@@ -352,7 +352,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, ...@@ -352,7 +352,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
value = CG_SYS_MC_MGCG_MASK; value = CG_SYS_MC_MGCG_MASK;
if (smum_send_msg_to_smc_with_parameter( if (smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr, msg, value)) hwmgr, msg, value))
return -EINVAL; return -EINVAL;
} }
...@@ -363,7 +363,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, ...@@ -363,7 +363,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
value = CG_SYS_MC_MGLS_MASK; value = CG_SYS_MC_MGLS_MASK;
if (smum_send_msg_to_smc_with_parameter( if (smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr, msg, value)) hwmgr, msg, value))
return -EINVAL; return -EINVAL;
} }
break; break;
...@@ -376,7 +376,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, ...@@ -376,7 +376,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
value = CG_SYS_DRM_MGCG_MASK; value = CG_SYS_DRM_MGCG_MASK;
if (smum_send_msg_to_smc_with_parameter( if (smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr, msg, value)) hwmgr, msg, value))
return -EINVAL; return -EINVAL;
} }
if (PP_STATE_SUPPORT_LS & *msg_id) { if (PP_STATE_SUPPORT_LS & *msg_id) {
...@@ -386,7 +386,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, ...@@ -386,7 +386,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
value = CG_SYS_DRM_MGLS_MASK; value = CG_SYS_DRM_MGLS_MASK;
if (smum_send_msg_to_smc_with_parameter( if (smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr, msg, value)) hwmgr, msg, value))
return -EINVAL; return -EINVAL;
} }
break; break;
...@@ -399,7 +399,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, ...@@ -399,7 +399,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
value = CG_SYS_HDP_MGCG_MASK; value = CG_SYS_HDP_MGCG_MASK;
if (smum_send_msg_to_smc_with_parameter( if (smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr, msg, value)) hwmgr, msg, value))
return -EINVAL; return -EINVAL;
} }
...@@ -410,7 +410,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, ...@@ -410,7 +410,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
value = CG_SYS_HDP_MGLS_MASK; value = CG_SYS_HDP_MGLS_MASK;
if (smum_send_msg_to_smc_with_parameter( if (smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr, msg, value)) hwmgr, msg, value))
return -EINVAL; return -EINVAL;
} }
break; break;
...@@ -423,7 +423,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, ...@@ -423,7 +423,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
value = CG_SYS_SDMA_MGCG_MASK; value = CG_SYS_SDMA_MGCG_MASK;
if (smum_send_msg_to_smc_with_parameter( if (smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr, msg, value)) hwmgr, msg, value))
return -EINVAL; return -EINVAL;
} }
...@@ -434,7 +434,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, ...@@ -434,7 +434,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
value = CG_SYS_SDMA_MGLS_MASK; value = CG_SYS_SDMA_MGLS_MASK;
if (smum_send_msg_to_smc_with_parameter( if (smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr, msg, value)) hwmgr, msg, value))
return -EINVAL; return -EINVAL;
} }
break; break;
...@@ -447,7 +447,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, ...@@ -447,7 +447,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
value = CG_SYS_ROM_MASK; value = CG_SYS_ROM_MASK;
if (smum_send_msg_to_smc_with_parameter( if (smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr, msg, value)) hwmgr, msg, value))
return -EINVAL; return -EINVAL;
} }
break; break;
...@@ -487,9 +487,9 @@ int smu7_enable_per_cu_power_gating(struct pp_hwmgr *hwmgr, bool enable) ...@@ -487,9 +487,9 @@ int smu7_enable_per_cu_power_gating(struct pp_hwmgr *hwmgr, bool enable)
active_cus = sys_info.value; active_cus = sys_info.value;
if (enable) if (enable)
return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, return smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_GFX_CU_PG_ENABLE, active_cus); PPSMC_MSG_GFX_CU_PG_ENABLE, active_cus);
else else
return smum_send_msg_to_smc(hwmgr->smumgr, return smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_GFX_CU_PG_DISABLE); PPSMC_MSG_GFX_CU_PG_DISABLE);
} }
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
浏览文件 @ d3f8c0ab
...@@ -164,7 +164,7 @@ static int smu7_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr) ...@@ -164,7 +164,7 @@ static int smu7_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
static int smu7_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr) static int smu7_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr)
{ {
if (hwmgr->feature_mask & PP_SMC_VOLTAGE_CONTROL_MASK) if (hwmgr->feature_mask & PP_SMC_VOLTAGE_CONTROL_MASK)
smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Voltage_Cntl_Enable); smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Voltage_Cntl_Enable);
return 0; return 0;
} }
...@@ -301,28 +301,28 @@ static int smu7_construct_voltage_tables(struct pp_hwmgr *hwmgr) ...@@ -301,28 +301,28 @@ static int smu7_construct_voltage_tables(struct pp_hwmgr *hwmgr)
"Failed to retrieve SVI2 VDDC table from dependancy table.", return result;); "Failed to retrieve SVI2 VDDC table from dependancy table.", return result;);
} }
tmp = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_VDDC); tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDC);
PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE(
(data->vddc_voltage_table.count <= tmp), (data->vddc_voltage_table.count <= tmp),
"Too many voltage values for VDDC. Trimming to fit state table.", "Too many voltage values for VDDC. Trimming to fit state table.",
phm_trim_voltage_table_to_fit_state_table(tmp, phm_trim_voltage_table_to_fit_state_table(tmp,
&(data->vddc_voltage_table))); &(data->vddc_voltage_table)));
tmp = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_VDDGFX); tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDGFX);
PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE(
(data->vddgfx_voltage_table.count <= tmp), (data->vddgfx_voltage_table.count <= tmp),
"Too many voltage values for VDDC. Trimming to fit state table.", "Too many voltage values for VDDC. Trimming to fit state table.",
phm_trim_voltage_table_to_fit_state_table(tmp, phm_trim_voltage_table_to_fit_state_table(tmp,
&(data->vddgfx_voltage_table))); &(data->vddgfx_voltage_table)));
tmp = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_VDDCI); tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDCI);
PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE(
(data->vddci_voltage_table.count <= tmp), (data->vddci_voltage_table.count <= tmp),
"Too many voltage values for VDDCI. Trimming to fit state table.", "Too many voltage values for VDDCI. Trimming to fit state table.",
phm_trim_voltage_table_to_fit_state_table(tmp, phm_trim_voltage_table_to_fit_state_table(tmp,
&(data->vddci_voltage_table))); &(data->vddci_voltage_table)));
tmp = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_MVDD); tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_MVDD);
PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE(
(data->mvdd_voltage_table.count <= tmp), (data->mvdd_voltage_table.count <= tmp),
"Too many voltage values for MVDD. Trimming to fit state table.", "Too many voltage values for MVDD. Trimming to fit state table.",
...@@ -471,7 +471,7 @@ static int smu7_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr, ...@@ -471,7 +471,7 @@ static int smu7_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
static int smu7_reset_to_default(struct pp_hwmgr *hwmgr) static int smu7_reset_to_default(struct pp_hwmgr *hwmgr)
{ {
return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_ResetToDefaults); return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ResetToDefaults);
} }
/** /**
...@@ -529,7 +529,7 @@ static int smu7_setup_default_pcie_table(struct pp_hwmgr *hwmgr) ...@@ -529,7 +529,7 @@ static int smu7_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
data->pcie_gen_performance = data->pcie_gen_power_saving; data->pcie_gen_performance = data->pcie_gen_power_saving;
data->pcie_lane_performance = data->pcie_lane_power_saving; data->pcie_lane_performance = data->pcie_lane_power_saving;
} }
tmp = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_LINK); tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_LINK);
phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table, phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table,
tmp, tmp,
MAX_REGULAR_DPM_NUMBER); MAX_REGULAR_DPM_NUMBER);
...@@ -610,27 +610,27 @@ static int smu7_reset_dpm_tables(struct pp_hwmgr *hwmgr) ...@@ -610,27 +610,27 @@ static int smu7_reset_dpm_tables(struct pp_hwmgr *hwmgr)
phm_reset_single_dpm_table( phm_reset_single_dpm_table(
&data->dpm_table.sclk_table, &data->dpm_table.sclk_table,
smum_get_mac_definition(hwmgr->smumgr, smum_get_mac_definition(hwmgr,
SMU_MAX_LEVELS_GRAPHICS), SMU_MAX_LEVELS_GRAPHICS),
MAX_REGULAR_DPM_NUMBER); MAX_REGULAR_DPM_NUMBER);
phm_reset_single_dpm_table( phm_reset_single_dpm_table(
&data->dpm_table.mclk_table, &data->dpm_table.mclk_table,
smum_get_mac_definition(hwmgr->smumgr, smum_get_mac_definition(hwmgr,
SMU_MAX_LEVELS_MEMORY), MAX_REGULAR_DPM_NUMBER); SMU_MAX_LEVELS_MEMORY), MAX_REGULAR_DPM_NUMBER);
phm_reset_single_dpm_table( phm_reset_single_dpm_table(
&data->dpm_table.vddc_table, &data->dpm_table.vddc_table,
smum_get_mac_definition(hwmgr->smumgr, smum_get_mac_definition(hwmgr,
SMU_MAX_LEVELS_VDDC), SMU_MAX_LEVELS_VDDC),
MAX_REGULAR_DPM_NUMBER); MAX_REGULAR_DPM_NUMBER);
phm_reset_single_dpm_table( phm_reset_single_dpm_table(
&data->dpm_table.vddci_table, &data->dpm_table.vddci_table,
smum_get_mac_definition(hwmgr->smumgr, smum_get_mac_definition(hwmgr,
SMU_MAX_LEVELS_VDDCI), MAX_REGULAR_DPM_NUMBER); SMU_MAX_LEVELS_VDDCI), MAX_REGULAR_DPM_NUMBER);
phm_reset_single_dpm_table( phm_reset_single_dpm_table(
&data->dpm_table.mvdd_table, &data->dpm_table.mvdd_table,
smum_get_mac_definition(hwmgr->smumgr, smum_get_mac_definition(hwmgr,
SMU_MAX_LEVELS_MVDD), SMU_MAX_LEVELS_MVDD),
MAX_REGULAR_DPM_NUMBER); MAX_REGULAR_DPM_NUMBER);
return 0; return 0;
...@@ -840,7 +840,7 @@ static int smu7_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr) ...@@ -840,7 +840,7 @@ static int smu7_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr)
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_RegulatorHot)) PHM_PlatformCaps_RegulatorHot))
return smum_send_msg_to_smc(hwmgr->smumgr, return smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_EnableVRHotGPIOInterrupt); PPSMC_MSG_EnableVRHotGPIOInterrupt);
return 0; return 0;
...@@ -858,7 +858,7 @@ static int smu7_enable_ulv(struct pp_hwmgr *hwmgr) ...@@ -858,7 +858,7 @@ static int smu7_enable_ulv(struct pp_hwmgr *hwmgr)
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
if (data->ulv_supported) if (data->ulv_supported)
return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_EnableULV); return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableULV);
return 0; return 0;
} }
...@@ -868,7 +868,7 @@ static int smu7_disable_ulv(struct pp_hwmgr *hwmgr) ...@@ -868,7 +868,7 @@ static int smu7_disable_ulv(struct pp_hwmgr *hwmgr)
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
if (data->ulv_supported) if (data->ulv_supported)
return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DisableULV); return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableULV);
return 0; return 0;
} }
...@@ -877,12 +877,12 @@ static int smu7_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) ...@@ -877,12 +877,12 @@ static int smu7_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
{ {
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SclkDeepSleep)) { PHM_PlatformCaps_SclkDeepSleep)) {
if (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_MASTER_DeepSleep_ON)) if (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MASTER_DeepSleep_ON))
PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE(false,
"Attempt to enable Master Deep Sleep switch failed!", "Attempt to enable Master Deep Sleep switch failed!",
return -EINVAL); return -EINVAL);
} else { } else {
if (smum_send_msg_to_smc(hwmgr->smumgr, if (smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_MASTER_DeepSleep_OFF)) { PPSMC_MSG_MASTER_DeepSleep_OFF)) {
PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE(false,
"Attempt to disable Master Deep Sleep switch failed!", "Attempt to disable Master Deep Sleep switch failed!",
...@@ -897,7 +897,7 @@ static int smu7_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) ...@@ -897,7 +897,7 @@ static int smu7_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
{ {
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SclkDeepSleep)) { PHM_PlatformCaps_SclkDeepSleep)) {
if (smum_send_msg_to_smc(hwmgr->smumgr, if (smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_MASTER_DeepSleep_OFF)) { PPSMC_MSG_MASTER_DeepSleep_OFF)) {
PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE(false,
"Attempt to disable Master Deep Sleep switch failed!", "Attempt to disable Master Deep Sleep switch failed!",
...@@ -913,12 +913,12 @@ static int smu7_disable_handshake_uvd(struct pp_hwmgr *hwmgr) ...@@ -913,12 +913,12 @@ static int smu7_disable_handshake_uvd(struct pp_hwmgr *hwmgr)
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
uint32_t soft_register_value = 0; uint32_t soft_register_value = 0;
uint32_t handshake_disables_offset = data->soft_regs_start uint32_t handshake_disables_offset = data->soft_regs_start
+ smum_get_offsetof(hwmgr->smumgr, + smum_get_offsetof(hwmgr,
SMU_SoftRegisters, HandshakeDisables); SMU_SoftRegisters, HandshakeDisables);
soft_register_value = cgs_read_ind_register(hwmgr->device, soft_register_value = cgs_read_ind_register(hwmgr->device,
CGS_IND_REG__SMC, handshake_disables_offset); CGS_IND_REG__SMC, handshake_disables_offset);
soft_register_value |= smum_get_mac_definition(hwmgr->smumgr, soft_register_value |= smum_get_mac_definition(hwmgr,
SMU_UVD_MCLK_HANDSHAKE_DISABLE); SMU_UVD_MCLK_HANDSHAKE_DISABLE);
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
handshake_disables_offset, soft_register_value); handshake_disables_offset, soft_register_value);
...@@ -932,7 +932,7 @@ static int smu7_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) ...@@ -932,7 +932,7 @@ static int smu7_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
/* enable SCLK dpm */ /* enable SCLK dpm */
if (!data->sclk_dpm_key_disabled) if (!data->sclk_dpm_key_disabled)
PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE(
(0 == smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Enable)), (0 == smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DPM_Enable)),
"Failed to enable SCLK DPM during DPM Start Function!", "Failed to enable SCLK DPM during DPM Start Function!",
return -EINVAL); return -EINVAL);
...@@ -941,7 +941,7 @@ static int smu7_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) ...@@ -941,7 +941,7 @@ static int smu7_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
if (!(hwmgr->feature_mask & PP_UVD_HANDSHAKE_MASK)) if (!(hwmgr->feature_mask & PP_UVD_HANDSHAKE_MASK))
smu7_disable_handshake_uvd(hwmgr); smu7_disable_handshake_uvd(hwmgr);
PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE(
(0 == smum_send_msg_to_smc(hwmgr->smumgr, (0 == smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_MCLKDPM_Enable)), PPSMC_MSG_MCLKDPM_Enable)),
"Failed to enable MCLK DPM during DPM Start Function!", "Failed to enable MCLK DPM during DPM Start Function!",
return -EINVAL); return -EINVAL);
...@@ -989,7 +989,7 @@ static int smu7_start_dpm(struct pp_hwmgr *hwmgr) ...@@ -989,7 +989,7 @@ static int smu7_start_dpm(struct pp_hwmgr *hwmgr)
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
data->soft_regs_start + data->soft_regs_start +
smum_get_offsetof(hwmgr->smumgr, SMU_SoftRegisters, smum_get_offsetof(hwmgr, SMU_SoftRegisters,
VoltageChangeTimeout), 0x1000); VoltageChangeTimeout), 0x1000);
PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE, PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
SWRST_COMMAND_1, RESETLC, 0x0); SWRST_COMMAND_1, RESETLC, 0x0);
...@@ -1006,7 +1006,7 @@ static int smu7_start_dpm(struct pp_hwmgr *hwmgr) ...@@ -1006,7 +1006,7 @@ static int smu7_start_dpm(struct pp_hwmgr *hwmgr)
/* enable PCIE dpm */ /* enable PCIE dpm */
if (0 == data->pcie_dpm_key_disabled) { if (0 == data->pcie_dpm_key_disabled) {
PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE(
(0 == smum_send_msg_to_smc(hwmgr->smumgr, (0 == smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_PCIeDPM_Enable)), PPSMC_MSG_PCIeDPM_Enable)),
"Failed to enable pcie DPM during DPM Start Function!", "Failed to enable pcie DPM during DPM Start Function!",
return -EINVAL); return -EINVAL);
...@@ -1014,7 +1014,7 @@ static int smu7_start_dpm(struct pp_hwmgr *hwmgr) ...@@ -1014,7 +1014,7 @@ static int smu7_start_dpm(struct pp_hwmgr *hwmgr)
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_Falcon_QuickTransition)) { PHM_PlatformCaps_Falcon_QuickTransition)) {
PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr->smumgr, PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_EnableACDCGPIOInterrupt)), PPSMC_MSG_EnableACDCGPIOInterrupt)),
"Failed to enable AC DC GPIO Interrupt!", "Failed to enable AC DC GPIO Interrupt!",
); );
...@@ -1032,7 +1032,7 @@ static int smu7_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) ...@@ -1032,7 +1032,7 @@ static int smu7_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
"Trying to disable SCLK DPM when DPM is disabled", "Trying to disable SCLK DPM when DPM is disabled",
return 0); return 0);
smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Disable); smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DPM_Disable);
} }
/* disable MCLK dpm */ /* disable MCLK dpm */
...@@ -1040,7 +1040,7 @@ static int smu7_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) ...@@ -1040,7 +1040,7 @@ static int smu7_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
"Trying to disable MCLK DPM when DPM is disabled", "Trying to disable MCLK DPM when DPM is disabled",
return 0); return 0);
smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_MCLKDPM_Disable); smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_Disable);
} }
return 0; return 0;
...@@ -1060,7 +1060,7 @@ static int smu7_stop_dpm(struct pp_hwmgr *hwmgr) ...@@ -1060,7 +1060,7 @@ static int smu7_stop_dpm(struct pp_hwmgr *hwmgr)
/* disable PCIE dpm */ /* disable PCIE dpm */
if (!data->pcie_dpm_key_disabled) { if (!data->pcie_dpm_key_disabled) {
PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE(
(smum_send_msg_to_smc(hwmgr->smumgr, (smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_PCIeDPM_Disable) == 0), PPSMC_MSG_PCIeDPM_Disable) == 0),
"Failed to disable pcie DPM during DPM Stop Function!", "Failed to disable pcie DPM during DPM Stop Function!",
return -EINVAL); return -EINVAL);
...@@ -1072,7 +1072,7 @@ static int smu7_stop_dpm(struct pp_hwmgr *hwmgr) ...@@ -1072,7 +1072,7 @@ static int smu7_stop_dpm(struct pp_hwmgr *hwmgr)
"Trying to disable voltage DPM when DPM is disabled", "Trying to disable voltage DPM when DPM is disabled",
return 0); return 0);
smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Voltage_Cntl_Disable); smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Voltage_Cntl_Disable);
return 0; return 0;
} }
...@@ -1226,7 +1226,7 @@ static int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr) ...@@ -1226,7 +1226,7 @@ static int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
PP_ASSERT_WITH_CODE((0 == tmp_result), PP_ASSERT_WITH_CODE((0 == tmp_result),
"Failed to enable VR hot GPIO interrupt!", result = tmp_result); "Failed to enable VR hot GPIO interrupt!", result = tmp_result);
smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)PPSMC_NoDisplay); smum_send_msg_to_smc(hwmgr, (PPSMC_Msg)PPSMC_NoDisplay);
tmp_result = smu7_enable_sclk_control(hwmgr); tmp_result = smu7_enable_sclk_control(hwmgr);
PP_ASSERT_WITH_CODE((0 == tmp_result), PP_ASSERT_WITH_CODE((0 == tmp_result),
...@@ -1692,7 +1692,7 @@ static int phm_add_voltage(struct pp_hwmgr *hwmgr, ...@@ -1692,7 +1692,7 @@ static int phm_add_voltage(struct pp_hwmgr *hwmgr,
PP_ASSERT_WITH_CODE((0 != look_up_table->count), PP_ASSERT_WITH_CODE((0 != look_up_table->count),
"Lookup Table empty.", return -EINVAL); "Lookup Table empty.", return -EINVAL);
i = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_VDDGFX); i = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDGFX);
PP_ASSERT_WITH_CODE((i >= look_up_table->count), PP_ASSERT_WITH_CODE((i >= look_up_table->count),
"Lookup Table is full.", return -EINVAL); "Lookup Table is full.", return -EINVAL);
...@@ -2423,7 +2423,7 @@ static int smu7_force_dpm_highest(struct pp_hwmgr *hwmgr) ...@@ -2423,7 +2423,7 @@ static int smu7_force_dpm_highest(struct pp_hwmgr *hwmgr)
level++; level++;
if (level) if (level)
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_PCIeDPM_ForceLevel, level); PPSMC_MSG_PCIeDPM_ForceLevel, level);
} }
} }
...@@ -2436,7 +2436,7 @@ static int smu7_force_dpm_highest(struct pp_hwmgr *hwmgr) ...@@ -2436,7 +2436,7 @@ static int smu7_force_dpm_highest(struct pp_hwmgr *hwmgr)
level++; level++;
if (level) if (level)
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SCLKDPM_SetEnabledMask, PPSMC_MSG_SCLKDPM_SetEnabledMask,
(1 << level)); (1 << level));
} }
...@@ -2450,7 +2450,7 @@ static int smu7_force_dpm_highest(struct pp_hwmgr *hwmgr) ...@@ -2450,7 +2450,7 @@ static int smu7_force_dpm_highest(struct pp_hwmgr *hwmgr)
level++; level++;
if (level) if (level)
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_MCLKDPM_SetEnabledMask, PPSMC_MSG_MCLKDPM_SetEnabledMask,
(1 << level)); (1 << level));
} }
...@@ -2469,14 +2469,14 @@ static int smu7_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr) ...@@ -2469,14 +2469,14 @@ static int smu7_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
if (!data->sclk_dpm_key_disabled) { if (!data->sclk_dpm_key_disabled) {
if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SCLKDPM_SetEnabledMask, PPSMC_MSG_SCLKDPM_SetEnabledMask,
data->dpm_level_enable_mask.sclk_dpm_enable_mask); data->dpm_level_enable_mask.sclk_dpm_enable_mask);
} }
if (!data->mclk_dpm_key_disabled) { if (!data->mclk_dpm_key_disabled) {
if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) if (data->dpm_level_enable_mask.mclk_dpm_enable_mask)
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_MCLKDPM_SetEnabledMask, PPSMC_MSG_MCLKDPM_SetEnabledMask,
data->dpm_level_enable_mask.mclk_dpm_enable_mask); data->dpm_level_enable_mask.mclk_dpm_enable_mask);
} }
...@@ -2492,7 +2492,7 @@ static int smu7_unforce_dpm_levels(struct pp_hwmgr *hwmgr) ...@@ -2492,7 +2492,7 @@ static int smu7_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
return -EINVAL; return -EINVAL;
if (!data->pcie_dpm_key_disabled) { if (!data->pcie_dpm_key_disabled) {
smum_send_msg_to_smc(hwmgr->smumgr, smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_PCIeDPM_UnForceLevel); PPSMC_MSG_PCIeDPM_UnForceLevel);
} }
...@@ -2509,7 +2509,7 @@ static int smu7_force_dpm_lowest(struct pp_hwmgr *hwmgr) ...@@ -2509,7 +2509,7 @@ static int smu7_force_dpm_lowest(struct pp_hwmgr *hwmgr)
if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) { if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
level = phm_get_lowest_enabled_level(hwmgr, level = phm_get_lowest_enabled_level(hwmgr,
data->dpm_level_enable_mask.sclk_dpm_enable_mask); data->dpm_level_enable_mask.sclk_dpm_enable_mask);
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SCLKDPM_SetEnabledMask, PPSMC_MSG_SCLKDPM_SetEnabledMask,
(1 << level)); (1 << level));
...@@ -2519,7 +2519,7 @@ static int smu7_force_dpm_lowest(struct pp_hwmgr *hwmgr) ...@@ -2519,7 +2519,7 @@ static int smu7_force_dpm_lowest(struct pp_hwmgr *hwmgr)
if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) { if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
level = phm_get_lowest_enabled_level(hwmgr, level = phm_get_lowest_enabled_level(hwmgr,
data->dpm_level_enable_mask.mclk_dpm_enable_mask); data->dpm_level_enable_mask.mclk_dpm_enable_mask);
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_MCLKDPM_SetEnabledMask, PPSMC_MSG_MCLKDPM_SetEnabledMask,
(1 << level)); (1 << level));
} }
...@@ -2529,7 +2529,7 @@ static int smu7_force_dpm_lowest(struct pp_hwmgr *hwmgr) ...@@ -2529,7 +2529,7 @@ static int smu7_force_dpm_lowest(struct pp_hwmgr *hwmgr)
if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) { if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
level = phm_get_lowest_enabled_level(hwmgr, level = phm_get_lowest_enabled_level(hwmgr,
data->dpm_level_enable_mask.pcie_dpm_enable_mask); data->dpm_level_enable_mask.pcie_dpm_enable_mask);
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_PCIeDPM_ForceLevel, PPSMC_MSG_PCIeDPM_ForceLevel,
(level)); (level));
} }
...@@ -3005,7 +3005,7 @@ static int smu7_get_pp_table_entry_callback_func_v1(struct pp_hwmgr *hwmgr, ...@@ -3005,7 +3005,7 @@ static int smu7_get_pp_table_entry_callback_func_v1(struct pp_hwmgr *hwmgr,
[smu7_power_state->performance_level_count++]); [smu7_power_state->performance_level_count++]);
PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE(
(smu7_power_state->performance_level_count < smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_GRAPHICS)), (smu7_power_state->performance_level_count < smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_GRAPHICS)),
"Performance levels exceeds SMC limit!", "Performance levels exceeds SMC limit!",
return -EINVAL); return -EINVAL);
...@@ -3169,7 +3169,7 @@ static int smu7_get_pp_table_entry_callback_func_v0(struct pp_hwmgr *hwmgr, ...@@ -3169,7 +3169,7 @@ static int smu7_get_pp_table_entry_callback_func_v0(struct pp_hwmgr *hwmgr,
data->highest_mclk = memory_clock; data->highest_mclk = memory_clock;
PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE(
(ps->performance_level_count < smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_GRAPHICS)), (ps->performance_level_count < smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_GRAPHICS)),
"Performance levels exceeds SMC limit!", "Performance levels exceeds SMC limit!",
return -EINVAL); return -EINVAL);
...@@ -3315,14 +3315,14 @@ static int smu7_get_pp_table_entry(struct pp_hwmgr *hwmgr, ...@@ -3315,14 +3315,14 @@ static int smu7_get_pp_table_entry(struct pp_hwmgr *hwmgr,
static int smu7_get_gpu_power(struct pp_hwmgr *hwmgr, static int smu7_get_gpu_power(struct pp_hwmgr *hwmgr,
struct pp_gpu_power *query) struct pp_gpu_power *query)
{ {
PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr, PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_PmStatusLogStart), PPSMC_MSG_PmStatusLogStart),
"Failed to start pm status log!", "Failed to start pm status log!",
return -1); return -1);
msleep_interruptible(20); msleep_interruptible(20);
PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr, PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_PmStatusLogSample), PPSMC_MSG_PmStatusLogSample),
"Failed to sample pm status log!", "Failed to sample pm status log!",
return -1); return -1);
...@@ -3356,19 +3356,19 @@ static int smu7_read_sensor(struct pp_hwmgr *hwmgr, int idx, ...@@ -3356,19 +3356,19 @@ static int smu7_read_sensor(struct pp_hwmgr *hwmgr, int idx,
switch (idx) { switch (idx) {
case AMDGPU_PP_SENSOR_GFX_SCLK: case AMDGPU_PP_SENSOR_GFX_SCLK:
smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency); smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetSclkFrequency);
sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
*((uint32_t *)value) = sclk; *((uint32_t *)value) = sclk;
*size = 4; *size = 4;
return 0; return 0;
case AMDGPU_PP_SENSOR_GFX_MCLK: case AMDGPU_PP_SENSOR_GFX_MCLK:
smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency); smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetMclkFrequency);
mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
*((uint32_t *)value) = mclk; *((uint32_t *)value) = mclk;
*size = 4; *size = 4;
return 0; return 0;
case AMDGPU_PP_SENSOR_GPU_LOAD: case AMDGPU_PP_SENSOR_GPU_LOAD:
offset = data->soft_regs_start + smum_get_offsetof(hwmgr->smumgr, offset = data->soft_regs_start + smum_get_offsetof(hwmgr,
SMU_SoftRegisters, SMU_SoftRegisters,
AverageGraphicsActivity); AverageGraphicsActivity);
...@@ -3535,7 +3535,7 @@ static int smu7_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) ...@@ -3535,7 +3535,7 @@ static int smu7_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
"Trying to freeze SCLK DPM when DPM is disabled", "Trying to freeze SCLK DPM when DPM is disabled",
); );
PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr, PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_SCLKDPM_FreezeLevel), PPSMC_MSG_SCLKDPM_FreezeLevel),
"Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!", "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
return -EINVAL); return -EINVAL);
...@@ -3547,7 +3547,7 @@ static int smu7_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) ...@@ -3547,7 +3547,7 @@ static int smu7_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
"Trying to freeze MCLK DPM when DPM is disabled", "Trying to freeze MCLK DPM when DPM is disabled",
); );
PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr, PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_MCLKDPM_FreezeLevel), PPSMC_MSG_MCLKDPM_FreezeLevel),
"Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!", "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
return -EINVAL); return -EINVAL);
...@@ -3765,7 +3765,7 @@ static int smu7_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) ...@@ -3765,7 +3765,7 @@ static int smu7_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
"Trying to Unfreeze SCLK DPM when DPM is disabled", "Trying to Unfreeze SCLK DPM when DPM is disabled",
); );
PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr, PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_SCLKDPM_UnfreezeLevel), PPSMC_MSG_SCLKDPM_UnfreezeLevel),
"Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!", "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
return -EINVAL); return -EINVAL);
...@@ -3777,7 +3777,7 @@ static int smu7_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) ...@@ -3777,7 +3777,7 @@ static int smu7_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
"Trying to Unfreeze MCLK DPM when DPM is disabled", "Trying to Unfreeze MCLK DPM when DPM is disabled",
); );
PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr, PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_SCLKDPM_UnfreezeLevel), PPSMC_MSG_SCLKDPM_UnfreezeLevel),
"Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!", "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
return -EINVAL); return -EINVAL);
...@@ -3828,9 +3828,9 @@ static int smu7_notify_smc_display(struct pp_hwmgr *hwmgr) ...@@ -3828,9 +3828,9 @@ static int smu7_notify_smc_display(struct pp_hwmgr *hwmgr)
int ret = 0; int ret = 0;
if (hwmgr->feature_mask & PP_VBI_TIME_SUPPORT_MASK) { if (hwmgr->feature_mask & PP_VBI_TIME_SUPPORT_MASK) {
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
(PPSMC_Msg)PPSMC_MSG_SetVBITimeout, data->frame_time_x2); (PPSMC_Msg)PPSMC_MSG_SetVBITimeout, data->frame_time_x2);
ret = (smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)PPSMC_HasDisplay) == 0) ? 0 : -EINVAL; ret = (smum_send_msg_to_smc(hwmgr, (PPSMC_Msg)PPSMC_HasDisplay) == 0) ? 0 : -EINVAL;
} }
return ret; return ret;
} }
...@@ -3905,7 +3905,7 @@ static int smu7_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_f ...@@ -3905,7 +3905,7 @@ static int smu7_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_f
hwmgr->thermal_controller. hwmgr->thermal_controller.
advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm; advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, return smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm); PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm);
} }
...@@ -3914,7 +3914,7 @@ smu7_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display) ...@@ -3914,7 +3914,7 @@ smu7_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
{ {
PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay; PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay;
return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ? 0 : -1; return (smum_send_msg_to_smc(hwmgr, msg) == 0) ? 0 : -1;
} }
static int static int
...@@ -3977,12 +3977,12 @@ static int smu7_program_display_gap(struct pp_hwmgr *hwmgr) ...@@ -3977,12 +3977,12 @@ static int smu7_program_display_gap(struct pp_hwmgr *hwmgr)
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2); cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2);
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
data->soft_regs_start + smum_get_offsetof(hwmgr->smumgr, data->soft_regs_start + smum_get_offsetof(hwmgr,
SMU_SoftRegisters, SMU_SoftRegisters,
PreVBlankGap), 0x64); PreVBlankGap), 0x64);
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
data->soft_regs_start + smum_get_offsetof(hwmgr->smumgr, data->soft_regs_start + smum_get_offsetof(hwmgr,
SMU_SoftRegisters, SMU_SoftRegisters,
VBlankTimeout), VBlankTimeout),
(frame_time_in_us - pre_vbi_time_in_us)); (frame_time_in_us - pre_vbi_time_in_us));
...@@ -4007,7 +4007,7 @@ static int smu7_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_f ...@@ -4007,7 +4007,7 @@ static int smu7_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_f
hwmgr->thermal_controller. hwmgr->thermal_controller.
advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm; advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm;
return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, return smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm); PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
} }
...@@ -4257,13 +4257,13 @@ static int smu7_force_clock_level(struct pp_hwmgr *hwmgr, ...@@ -4257,13 +4257,13 @@ static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
switch (type) { switch (type) {
case PP_SCLK: case PP_SCLK:
if (!data->sclk_dpm_key_disabled) if (!data->sclk_dpm_key_disabled)
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SCLKDPM_SetEnabledMask, PPSMC_MSG_SCLKDPM_SetEnabledMask,
data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask); data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
break; break;
case PP_MCLK: case PP_MCLK:
if (!data->mclk_dpm_key_disabled) if (!data->mclk_dpm_key_disabled)
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_MCLKDPM_SetEnabledMask, PPSMC_MSG_MCLKDPM_SetEnabledMask,
data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask); data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);
break; break;
...@@ -4276,7 +4276,7 @@ static int smu7_force_clock_level(struct pp_hwmgr *hwmgr, ...@@ -4276,7 +4276,7 @@ static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
level++; level++;
if (!data->pcie_dpm_key_disabled) if (!data->pcie_dpm_key_disabled)
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_PCIeDPM_ForceLevel, PPSMC_MSG_PCIeDPM_ForceLevel,
level); level);
break; break;
...@@ -4300,7 +4300,7 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr, ...@@ -4300,7 +4300,7 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
switch (type) { switch (type) {
case PP_SCLK: case PP_SCLK:
smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency); smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetSclkFrequency);
clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
for (i = 0; i < sclk_table->count; i++) { for (i = 0; i < sclk_table->count; i++) {
...@@ -4316,7 +4316,7 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr, ...@@ -4316,7 +4316,7 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
(i == now) ? "*" : ""); (i == now) ? "*" : "");
break; break;
case PP_MCLK: case PP_MCLK:
smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency); smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetMclkFrequency);
clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
for (i = 0; i < mclk_table->count; i++) { for (i = 0; i < mclk_table->count; i++) {
...@@ -4602,7 +4602,7 @@ static int smu7_set_power_profile_state(struct pp_hwmgr *hwmgr, ...@@ -4602,7 +4602,7 @@ static int smu7_set_power_profile_state(struct pp_hwmgr *hwmgr,
if (sclk_mask) { if (sclk_mask) {
if (!data->sclk_dpm_key_disabled) if (!data->sclk_dpm_key_disabled)
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SCLKDPM_SetEnabledMask, PPSMC_MSG_SCLKDPM_SetEnabledMask,
data->dpm_level_enable_mask. data->dpm_level_enable_mask.
sclk_dpm_enable_mask & sclk_dpm_enable_mask &
...@@ -4611,7 +4611,7 @@ static int smu7_set_power_profile_state(struct pp_hwmgr *hwmgr, ...@@ -4611,7 +4611,7 @@ static int smu7_set_power_profile_state(struct pp_hwmgr *hwmgr,
if (mclk_mask) { if (mclk_mask) {
if (!data->mclk_dpm_key_disabled) if (!data->mclk_dpm_key_disabled)
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_MCLKDPM_SetEnabledMask, PPSMC_MSG_MCLKDPM_SetEnabledMask,
data->dpm_level_enable_mask. data->dpm_level_enable_mask.
mclk_dpm_enable_mask & mclk_dpm_enable_mask &
...@@ -4623,8 +4623,7 @@ static int smu7_set_power_profile_state(struct pp_hwmgr *hwmgr, ...@@ -4623,8 +4623,7 @@ static int smu7_set_power_profile_state(struct pp_hwmgr *hwmgr,
static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable) static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable)
{ {
struct pp_smumgr *smumgr = (struct pp_smumgr *)(hwmgr->smumgr); struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend);
struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend);
if (smu_data == NULL) if (smu_data == NULL)
return -EINVAL; return -EINVAL;
...@@ -4636,13 +4635,13 @@ static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable) ...@@ -4636,13 +4635,13 @@ static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable)
if (!PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, if (!PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON))
PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc( PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
hwmgr->smumgr, PPSMC_MSG_EnableAvfs), hwmgr, PPSMC_MSG_EnableAvfs),
"Failed to enable AVFS!", "Failed to enable AVFS!",
return -EINVAL); return -EINVAL);
} else if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, } else if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON))
PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc( PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
hwmgr->smumgr, PPSMC_MSG_DisableAvfs), hwmgr, PPSMC_MSG_DisableAvfs),
"Failed to disable AVFS!", "Failed to disable AVFS!",
return -EINVAL); return -EINVAL);
......
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
浏览文件 @ d3f8c0ab
...@@ -660,7 +660,7 @@ static int smu7_enable_didt(struct pp_hwmgr *hwmgr, const bool enable) ...@@ -660,7 +660,7 @@ static int smu7_enable_didt(struct pp_hwmgr *hwmgr, const bool enable)
didt_block |= block_en << TCP_Enable_SHIFT; didt_block |= block_en << TCP_Enable_SHIFT;
if (enable) if (enable)
result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_Didt_Block_Function, didt_block); result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_Didt_Block_Function, didt_block);
return result; return result;
} }
...@@ -781,7 +781,7 @@ int smu7_enable_didt_config(struct pp_hwmgr *hwmgr) ...@@ -781,7 +781,7 @@ int smu7_enable_didt_config(struct pp_hwmgr *hwmgr)
PP_ASSERT_WITH_CODE((result == 0), "EnableDiDt failed.", return result); PP_ASSERT_WITH_CODE((result == 0), "EnableDiDt failed.", return result);
if (hwmgr->chip_id == CHIP_POLARIS11) { if (hwmgr->chip_id == CHIP_POLARIS11) {
result = smum_send_msg_to_smc(hwmgr->smumgr, result = smum_send_msg_to_smc(hwmgr,
(uint16_t)(PPSMC_MSG_EnableDpmDidt)); (uint16_t)(PPSMC_MSG_EnableDpmDidt));
PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE((0 == result),
"Failed to enable DPM DIDT.", return result); "Failed to enable DPM DIDT.", return result);
...@@ -809,7 +809,7 @@ int smu7_disable_didt_config(struct pp_hwmgr *hwmgr) ...@@ -809,7 +809,7 @@ int smu7_disable_didt_config(struct pp_hwmgr *hwmgr)
"Post DIDT enable clock gating failed.", "Post DIDT enable clock gating failed.",
return result); return result);
if (hwmgr->chip_id == CHIP_POLARIS11) { if (hwmgr->chip_id == CHIP_POLARIS11) {
result = smum_send_msg_to_smc(hwmgr->smumgr, result = smum_send_msg_to_smc(hwmgr,
(uint16_t)(PPSMC_MSG_DisableDpmDidt)); (uint16_t)(PPSMC_MSG_DisableDpmDidt));
PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE((0 == result),
"Failed to disable DPM DIDT.", return result); "Failed to disable DPM DIDT.", return result);
...@@ -827,7 +827,7 @@ int smu7_enable_smc_cac(struct pp_hwmgr *hwmgr) ...@@ -827,7 +827,7 @@ int smu7_enable_smc_cac(struct pp_hwmgr *hwmgr)
if (PP_CAP(PHM_PlatformCaps_CAC)) { if (PP_CAP(PHM_PlatformCaps_CAC)) {
int smc_result; int smc_result;
smc_result = smum_send_msg_to_smc(hwmgr->smumgr, smc_result = smum_send_msg_to_smc(hwmgr,
(uint16_t)(PPSMC_MSG_EnableCac)); (uint16_t)(PPSMC_MSG_EnableCac));
PP_ASSERT_WITH_CODE((0 == smc_result), PP_ASSERT_WITH_CODE((0 == smc_result),
"Failed to enable CAC in SMC.", result = -1); "Failed to enable CAC in SMC.", result = -1);
...@@ -843,7 +843,7 @@ int smu7_disable_smc_cac(struct pp_hwmgr *hwmgr) ...@@ -843,7 +843,7 @@ int smu7_disable_smc_cac(struct pp_hwmgr *hwmgr)
int result = 0; int result = 0;
if (PP_CAP(PHM_PlatformCaps_CAC) && data->cac_enabled) { if (PP_CAP(PHM_PlatformCaps_CAC) && data->cac_enabled) {
int smc_result = smum_send_msg_to_smc(hwmgr->smumgr, int smc_result = smum_send_msg_to_smc(hwmgr,
(uint16_t)(PPSMC_MSG_DisableCac)); (uint16_t)(PPSMC_MSG_DisableCac));
PP_ASSERT_WITH_CODE((smc_result == 0), PP_ASSERT_WITH_CODE((smc_result == 0),
"Failed to disable CAC in SMC.", result = -1); "Failed to disable CAC in SMC.", result = -1);
...@@ -859,7 +859,7 @@ int smu7_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n) ...@@ -859,7 +859,7 @@ int smu7_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)
if (data->power_containment_features & if (data->power_containment_features &
POWERCONTAINMENT_FEATURE_PkgPwrLimit) POWERCONTAINMENT_FEATURE_PkgPwrLimit)
return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, return smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_PkgPwrSetLimit, n); PPSMC_MSG_PkgPwrSetLimit, n);
return 0; return 0;
} }
...@@ -867,7 +867,7 @@ int smu7_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n) ...@@ -867,7 +867,7 @@ int smu7_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)
static int smu7_set_overdriver_target_tdp(struct pp_hwmgr *hwmgr, static int smu7_set_overdriver_target_tdp(struct pp_hwmgr *hwmgr,
uint32_t target_tdp) uint32_t target_tdp)
{ {
return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, return smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_OverDriveSetTargetTdp, target_tdp); PPSMC_MSG_OverDriveSetTargetTdp, target_tdp);
} }
...@@ -888,7 +888,7 @@ int smu7_enable_power_containment(struct pp_hwmgr *hwmgr) ...@@ -888,7 +888,7 @@ int smu7_enable_power_containment(struct pp_hwmgr *hwmgr)
if (PP_CAP(PHM_PlatformCaps_PowerContainment)) { if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
if (data->enable_tdc_limit_feature) { if (data->enable_tdc_limit_feature) {
smc_result = smum_send_msg_to_smc(hwmgr->smumgr, smc_result = smum_send_msg_to_smc(hwmgr,
(uint16_t)(PPSMC_MSG_TDCLimitEnable)); (uint16_t)(PPSMC_MSG_TDCLimitEnable));
PP_ASSERT_WITH_CODE((0 == smc_result), PP_ASSERT_WITH_CODE((0 == smc_result),
"Failed to enable TDCLimit in SMC.", result = -1;); "Failed to enable TDCLimit in SMC.", result = -1;);
...@@ -898,7 +898,7 @@ int smu7_enable_power_containment(struct pp_hwmgr *hwmgr) ...@@ -898,7 +898,7 @@ int smu7_enable_power_containment(struct pp_hwmgr *hwmgr)
} }
if (data->enable_pkg_pwr_tracking_feature) { if (data->enable_pkg_pwr_tracking_feature) {
smc_result = smum_send_msg_to_smc(hwmgr->smumgr, smc_result = smum_send_msg_to_smc(hwmgr,
(uint16_t)(PPSMC_MSG_PkgPwrLimitEnable)); (uint16_t)(PPSMC_MSG_PkgPwrLimitEnable));
PP_ASSERT_WITH_CODE((0 == smc_result), PP_ASSERT_WITH_CODE((0 == smc_result),
"Failed to enable PkgPwrTracking in SMC.", result = -1;); "Failed to enable PkgPwrTracking in SMC.", result = -1;);
...@@ -927,7 +927,7 @@ int smu7_disable_power_containment(struct pp_hwmgr *hwmgr) ...@@ -927,7 +927,7 @@ int smu7_disable_power_containment(struct pp_hwmgr *hwmgr)
if (data->power_containment_features & if (data->power_containment_features &
POWERCONTAINMENT_FEATURE_TDCLimit) { POWERCONTAINMENT_FEATURE_TDCLimit) {
smc_result = smum_send_msg_to_smc(hwmgr->smumgr, smc_result = smum_send_msg_to_smc(hwmgr,
(uint16_t)(PPSMC_MSG_TDCLimitDisable)); (uint16_t)(PPSMC_MSG_TDCLimitDisable));
PP_ASSERT_WITH_CODE((smc_result == 0), PP_ASSERT_WITH_CODE((smc_result == 0),
"Failed to disable TDCLimit in SMC.", "Failed to disable TDCLimit in SMC.",
...@@ -936,7 +936,7 @@ int smu7_disable_power_containment(struct pp_hwmgr *hwmgr) ...@@ -936,7 +936,7 @@ int smu7_disable_power_containment(struct pp_hwmgr *hwmgr)
if (data->power_containment_features & if (data->power_containment_features &
POWERCONTAINMENT_FEATURE_DTE) { POWERCONTAINMENT_FEATURE_DTE) {
smc_result = smum_send_msg_to_smc(hwmgr->smumgr, smc_result = smum_send_msg_to_smc(hwmgr,
(uint16_t)(PPSMC_MSG_DisableDTE)); (uint16_t)(PPSMC_MSG_DisableDTE));
PP_ASSERT_WITH_CODE((smc_result == 0), PP_ASSERT_WITH_CODE((smc_result == 0),
"Failed to disable DTE in SMC.", "Failed to disable DTE in SMC.",
...@@ -945,7 +945,7 @@ int smu7_disable_power_containment(struct pp_hwmgr *hwmgr) ...@@ -945,7 +945,7 @@ int smu7_disable_power_containment(struct pp_hwmgr *hwmgr)
if (data->power_containment_features & if (data->power_containment_features &
POWERCONTAINMENT_FEATURE_PkgPwrLimit) { POWERCONTAINMENT_FEATURE_PkgPwrLimit) {
smc_result = smum_send_msg_to_smc(hwmgr->smumgr, smc_result = smum_send_msg_to_smc(hwmgr,
(uint16_t)(PPSMC_MSG_PkgPwrLimitDisable)); (uint16_t)(PPSMC_MSG_PkgPwrLimitDisable));
PP_ASSERT_WITH_CODE((smc_result == 0), PP_ASSERT_WITH_CODE((smc_result == 0),
"Failed to disable PkgPwrTracking in SMC.", "Failed to disable PkgPwrTracking in SMC.",
......
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c
浏览文件 @ d3f8c0ab
...@@ -152,7 +152,7 @@ int smu7_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr) ...@@ -152,7 +152,7 @@ int smu7_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr)
if (PP_CAP(PHM_PlatformCaps_ODFuzzyFanControlSupport)) { if (PP_CAP(PHM_PlatformCaps_ODFuzzyFanControlSupport)) {
cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, FAN_CONTROL_FUZZY); cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, FAN_CONTROL_FUZZY);
result = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StartFanControl); result = smum_send_msg_to_smc(hwmgr, PPSMC_StartFanControl);
if (PP_CAP(PHM_PlatformCaps_FanSpeedInTableIsRPM)) if (PP_CAP(PHM_PlatformCaps_FanSpeedInTableIsRPM))
hwmgr->hwmgr_func->set_max_fan_rpm_output(hwmgr, hwmgr->hwmgr_func->set_max_fan_rpm_output(hwmgr,
...@@ -165,12 +165,12 @@ int smu7_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr) ...@@ -165,12 +165,12 @@ int smu7_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr)
} else { } else {
cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, FAN_CONTROL_TABLE); cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, FAN_CONTROL_TABLE);
result = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StartFanControl); result = smum_send_msg_to_smc(hwmgr, PPSMC_StartFanControl);
} }
if (!result && hwmgr->thermal_controller. if (!result && hwmgr->thermal_controller.
advanceFanControlParameters.ucTargetTemperature) advanceFanControlParameters.ucTargetTemperature)
result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, result = smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetFanTemperatureTarget, PPSMC_MSG_SetFanTemperatureTarget,
hwmgr->thermal_controller. hwmgr->thermal_controller.
advanceFanControlParameters.ucTargetTemperature); advanceFanControlParameters.ucTargetTemperature);
...@@ -183,7 +183,7 @@ int smu7_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr) ...@@ -183,7 +183,7 @@ int smu7_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr)
int smu7_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr) int smu7_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr)
{ {
hwmgr->fan_ctrl_enabled = false; hwmgr->fan_ctrl_enabled = false;
return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StopFanControl); return smum_send_msg_to_smc(hwmgr, PPSMC_StopFanControl);
} }
/** /**
...@@ -371,7 +371,7 @@ static void smu7_thermal_enable_alert(struct pp_hwmgr *hwmgr) ...@@ -371,7 +371,7 @@ static void smu7_thermal_enable_alert(struct pp_hwmgr *hwmgr)
CG_THERMAL_INT, THERM_INT_MASK, alert); CG_THERMAL_INT, THERM_INT_MASK, alert);
/* send message to SMU to enable internal thermal interrupts */ /* send message to SMU to enable internal thermal interrupts */
smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Thermal_Cntl_Enable); smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Thermal_Cntl_Enable);
} }
/** /**
...@@ -389,7 +389,7 @@ int smu7_thermal_disable_alert(struct pp_hwmgr *hwmgr) ...@@ -389,7 +389,7 @@ int smu7_thermal_disable_alert(struct pp_hwmgr *hwmgr)
CG_THERMAL_INT, THERM_INT_MASK, alert); CG_THERMAL_INT, THERM_INT_MASK, alert);
/* send message to SMU to disable internal thermal interrupts */ /* send message to SMU to disable internal thermal interrupts */
return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Thermal_Cntl_Disable); return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Thermal_Cntl_Disable);
} }
/** /**
......
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
浏览文件 @ d3f8c0ab
...@@ -425,8 +425,8 @@ static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr) ...@@ -425,8 +425,8 @@ static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
if (data->registry_data.vr0hot_enabled) if (data->registry_data.vr0hot_enabled)
data->smu_features[GNLD_VR0HOT].supported = true; data->smu_features[GNLD_VR0HOT].supported = true;
smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetSmuVersion); smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion);
vega10_read_arg_from_smc(hwmgr->smumgr, &(data->smu_version)); vega10_read_arg_from_smc(hwmgr, &(data->smu_version));
/* ACG firmware has major version 5 */ /* ACG firmware has major version 5 */
if ((data->smu_version & 0xff000000) == 0x5000000) if ((data->smu_version & 0xff000000) == 0x5000000)
data->smu_features[GNLD_ACG].supported = true; data->smu_features[GNLD_ACG].supported = true;
...@@ -922,7 +922,7 @@ static bool vega10_is_dpm_running(struct pp_hwmgr *hwmgr) ...@@ -922,7 +922,7 @@ static bool vega10_is_dpm_running(struct pp_hwmgr *hwmgr)
{ {
uint32_t features_enabled; uint32_t features_enabled;
if (!vega10_get_smc_features(hwmgr->smumgr, &features_enabled)) { if (!vega10_get_smc_features(hwmgr, &features_enabled)) {
if (features_enabled & SMC_DPM_FEATURES) if (features_enabled & SMC_DPM_FEATURES)
return true; return true;
} }
...@@ -2272,21 +2272,21 @@ static int vega10_acg_enable(struct pp_hwmgr *hwmgr) ...@@ -2272,21 +2272,21 @@ static int vega10_acg_enable(struct pp_hwmgr *hwmgr)
uint32_t agc_btc_response; uint32_t agc_btc_response;
if (data->smu_features[GNLD_ACG].supported) { if (data->smu_features[GNLD_ACG].supported) {
if (0 == vega10_enable_smc_features(hwmgr->smumgr, true, if (0 == vega10_enable_smc_features(hwmgr, true,
data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_bitmap)) data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_bitmap))
data->smu_features[GNLD_DPM_PREFETCHER].enabled = true; data->smu_features[GNLD_DPM_PREFETCHER].enabled = true;
smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_InitializeAcg); smum_send_msg_to_smc(hwmgr, PPSMC_MSG_InitializeAcg);
smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_RunAcgBtc); smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgBtc);
vega10_read_arg_from_smc(hwmgr->smumgr, &agc_btc_response); vega10_read_arg_from_smc(hwmgr, &agc_btc_response);
if (1 == agc_btc_response) { if (1 == agc_btc_response) {
if (1 == data->acg_loop_state) if (1 == data->acg_loop_state)
smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_RunAcgInClosedLoop); smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgInClosedLoop);
else if (2 == data->acg_loop_state) else if (2 == data->acg_loop_state)
smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_RunAcgInOpenLoop); smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgInOpenLoop);
if (0 == vega10_enable_smc_features(hwmgr->smumgr, true, if (0 == vega10_enable_smc_features(hwmgr, true,
data->smu_features[GNLD_ACG].smu_feature_bitmap)) data->smu_features[GNLD_ACG].smu_feature_bitmap))
data->smu_features[GNLD_ACG].enabled = true; data->smu_features[GNLD_ACG].enabled = true;
} else { } else {
...@@ -2305,7 +2305,7 @@ static int vega10_acg_disable(struct pp_hwmgr *hwmgr) ...@@ -2305,7 +2305,7 @@ static int vega10_acg_disable(struct pp_hwmgr *hwmgr)
if (data->smu_features[GNLD_ACG].supported && if (data->smu_features[GNLD_ACG].supported &&
data->smu_features[GNLD_ACG].enabled) data->smu_features[GNLD_ACG].enabled)
if (!vega10_enable_smc_features(hwmgr->smumgr, false, if (!vega10_enable_smc_features(hwmgr, false,
data->smu_features[GNLD_ACG].smu_feature_bitmap)) data->smu_features[GNLD_ACG].smu_feature_bitmap))
data->smu_features[GNLD_ACG].enabled = false; data->smu_features[GNLD_ACG].enabled = false;
...@@ -2355,14 +2355,14 @@ static int vega10_avfs_enable(struct pp_hwmgr *hwmgr, bool enable) ...@@ -2355,14 +2355,14 @@ static int vega10_avfs_enable(struct pp_hwmgr *hwmgr, bool enable)
if (data->smu_features[GNLD_AVFS].supported) { if (data->smu_features[GNLD_AVFS].supported) {
if (enable) { if (enable) {
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
true, true,
data->smu_features[GNLD_AVFS].smu_feature_bitmap), data->smu_features[GNLD_AVFS].smu_feature_bitmap),
"[avfs_control] Attempt to Enable AVFS feature Failed!", "[avfs_control] Attempt to Enable AVFS feature Failed!",
return -1); return -1);
data->smu_features[GNLD_AVFS].enabled = true; data->smu_features[GNLD_AVFS].enabled = true;
} else { } else {
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
false, false,
data->smu_features[GNLD_AVFS].smu_feature_id), data->smu_features[GNLD_AVFS].smu_feature_id),
"[avfs_control] Attempt to Disable AVFS feature Failed!", "[avfs_control] Attempt to Disable AVFS feature Failed!",
...@@ -2385,11 +2385,11 @@ static int vega10_populate_and_upload_avfs_fuse_override(struct pp_hwmgr *hwmgr) ...@@ -2385,11 +2385,11 @@ static int vega10_populate_and_upload_avfs_fuse_override(struct pp_hwmgr *hwmgr)
struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend); struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
AvfsFuseOverride_t *avfs_fuse_table = &(data->smc_state_table.avfs_fuse_override_table); AvfsFuseOverride_t *avfs_fuse_table = &(data->smc_state_table.avfs_fuse_override_table);
smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_ReadSerialNumTop32); smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32);
vega10_read_arg_from_smc(hwmgr->smumgr, &top32); vega10_read_arg_from_smc(hwmgr, &top32);
smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_ReadSerialNumBottom32); smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32);
vega10_read_arg_from_smc(hwmgr->smumgr, &bottom32); vega10_read_arg_from_smc(hwmgr, &bottom32);
serial_number = ((uint64_t)bottom32 << 32) | top32; serial_number = ((uint64_t)bottom32 << 32) | top32;
...@@ -2403,7 +2403,7 @@ static int vega10_populate_and_upload_avfs_fuse_override(struct pp_hwmgr *hwmgr) ...@@ -2403,7 +2403,7 @@ static int vega10_populate_and_upload_avfs_fuse_override(struct pp_hwmgr *hwmgr)
avfs_fuse_table->VFT2_b = fuse.VFT2_b; avfs_fuse_table->VFT2_b = fuse.VFT2_b;
avfs_fuse_table->VFT2_m1 = fuse.VFT2_m1; avfs_fuse_table->VFT2_m1 = fuse.VFT2_m1;
avfs_fuse_table->VFT2_m2 = fuse.VFT2_m2; avfs_fuse_table->VFT2_m2 = fuse.VFT2_m2;
result = vega10_copy_table_to_smc(hwmgr->smumgr, result = vega10_copy_table_to_smc(hwmgr,
(uint8_t *)avfs_fuse_table, AVFSFUSETABLE); (uint8_t *)avfs_fuse_table, AVFSFUSETABLE);
PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE(!result,
"Failed to upload FuseOVerride!", "Failed to upload FuseOVerride!",
...@@ -2542,14 +2542,14 @@ static int vega10_init_smc_table(struct pp_hwmgr *hwmgr) ...@@ -2542,14 +2542,14 @@ static int vega10_init_smc_table(struct pp_hwmgr *hwmgr)
data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk; data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk;
data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk; data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk;
if (0 != boot_up_values.usVddc) { if (0 != boot_up_values.usVddc) {
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetFloorSocVoltage, PPSMC_MSG_SetFloorSocVoltage,
(boot_up_values.usVddc * 4)); (boot_up_values.usVddc * 4));
data->vbios_boot_state.bsoc_vddc_lock = true; data->vbios_boot_state.bsoc_vddc_lock = true;
} else { } else {
data->vbios_boot_state.bsoc_vddc_lock = false; data->vbios_boot_state.bsoc_vddc_lock = false;
} }
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetMinDeepSleepDcefclk, PPSMC_MSG_SetMinDeepSleepDcefclk,
(uint32_t)(data->vbios_boot_state.dcef_clock / 100)); (uint32_t)(data->vbios_boot_state.dcef_clock / 100));
} }
...@@ -2575,7 +2575,7 @@ static int vega10_init_smc_table(struct pp_hwmgr *hwmgr) ...@@ -2575,7 +2575,7 @@ static int vega10_init_smc_table(struct pp_hwmgr *hwmgr)
vega10_populate_and_upload_avfs_fuse_override(hwmgr); vega10_populate_and_upload_avfs_fuse_override(hwmgr);
result = vega10_copy_table_to_smc(hwmgr->smumgr, result = vega10_copy_table_to_smc(hwmgr,
(uint8_t *)pp_table, PPTABLE); (uint8_t *)pp_table, PPTABLE);
PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE(!result,
"Failed to upload PPtable!", return result); "Failed to upload PPtable!", return result);
...@@ -2598,7 +2598,7 @@ static int vega10_enable_thermal_protection(struct pp_hwmgr *hwmgr) ...@@ -2598,7 +2598,7 @@ static int vega10_enable_thermal_protection(struct pp_hwmgr *hwmgr)
pr_info("THERMAL Feature Already enabled!"); pr_info("THERMAL Feature Already enabled!");
PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE(
!vega10_enable_smc_features(hwmgr->smumgr, !vega10_enable_smc_features(hwmgr,
true, true,
data->smu_features[GNLD_THERMAL].smu_feature_bitmap), data->smu_features[GNLD_THERMAL].smu_feature_bitmap),
"Enable THERMAL Feature Failed!", "Enable THERMAL Feature Failed!",
...@@ -2618,7 +2618,7 @@ static int vega10_disable_thermal_protection(struct pp_hwmgr *hwmgr) ...@@ -2618,7 +2618,7 @@ static int vega10_disable_thermal_protection(struct pp_hwmgr *hwmgr)
pr_info("THERMAL Feature Already disabled!"); pr_info("THERMAL Feature Already disabled!");
PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE(
!vega10_enable_smc_features(hwmgr->smumgr, !vega10_enable_smc_features(hwmgr,
false, false,
data->smu_features[GNLD_THERMAL].smu_feature_bitmap), data->smu_features[GNLD_THERMAL].smu_feature_bitmap),
"disable THERMAL Feature Failed!", "disable THERMAL Feature Failed!",
...@@ -2637,7 +2637,7 @@ static int vega10_enable_vrhot_feature(struct pp_hwmgr *hwmgr) ...@@ -2637,7 +2637,7 @@ static int vega10_enable_vrhot_feature(struct pp_hwmgr *hwmgr)
if (PP_CAP(PHM_PlatformCaps_RegulatorHot)) { if (PP_CAP(PHM_PlatformCaps_RegulatorHot)) {
if (data->smu_features[GNLD_VR0HOT].supported) { if (data->smu_features[GNLD_VR0HOT].supported) {
PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE(
!vega10_enable_smc_features(hwmgr->smumgr, !vega10_enable_smc_features(hwmgr,
true, true,
data->smu_features[GNLD_VR0HOT].smu_feature_bitmap), data->smu_features[GNLD_VR0HOT].smu_feature_bitmap),
"Attempt to Enable VR0 Hot feature Failed!", "Attempt to Enable VR0 Hot feature Failed!",
...@@ -2646,7 +2646,7 @@ static int vega10_enable_vrhot_feature(struct pp_hwmgr *hwmgr) ...@@ -2646,7 +2646,7 @@ static int vega10_enable_vrhot_feature(struct pp_hwmgr *hwmgr)
} else { } else {
if (data->smu_features[GNLD_VR1HOT].supported) { if (data->smu_features[GNLD_VR1HOT].supported) {
PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE(
!vega10_enable_smc_features(hwmgr->smumgr, !vega10_enable_smc_features(hwmgr,
true, true,
data->smu_features[GNLD_VR1HOT].smu_feature_bitmap), data->smu_features[GNLD_VR1HOT].smu_feature_bitmap),
"Attempt to Enable VR0 Hot feature Failed!", "Attempt to Enable VR0 Hot feature Failed!",
...@@ -2664,7 +2664,7 @@ static int vega10_enable_ulv(struct pp_hwmgr *hwmgr) ...@@ -2664,7 +2664,7 @@ static int vega10_enable_ulv(struct pp_hwmgr *hwmgr)
(struct vega10_hwmgr *)(hwmgr->backend); (struct vega10_hwmgr *)(hwmgr->backend);
if (data->registry_data.ulv_support) { if (data->registry_data.ulv_support) {
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
true, data->smu_features[GNLD_ULV].smu_feature_bitmap), true, data->smu_features[GNLD_ULV].smu_feature_bitmap),
"Enable ULV Feature Failed!", "Enable ULV Feature Failed!",
return -1); return -1);
...@@ -2680,7 +2680,7 @@ static int vega10_disable_ulv(struct pp_hwmgr *hwmgr) ...@@ -2680,7 +2680,7 @@ static int vega10_disable_ulv(struct pp_hwmgr *hwmgr)
(struct vega10_hwmgr *)(hwmgr->backend); (struct vega10_hwmgr *)(hwmgr->backend);
if (data->registry_data.ulv_support) { if (data->registry_data.ulv_support) {
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
false, data->smu_features[GNLD_ULV].smu_feature_bitmap), false, data->smu_features[GNLD_ULV].smu_feature_bitmap),
"disable ULV Feature Failed!", "disable ULV Feature Failed!",
return -EINVAL); return -EINVAL);
...@@ -2696,7 +2696,7 @@ static int vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) ...@@ -2696,7 +2696,7 @@ static int vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
(struct vega10_hwmgr *)(hwmgr->backend); (struct vega10_hwmgr *)(hwmgr->backend);
if (data->smu_features[GNLD_DS_GFXCLK].supported) { if (data->smu_features[GNLD_DS_GFXCLK].supported) {
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
true, data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap), true, data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap),
"Attempt to Enable DS_GFXCLK Feature Failed!", "Attempt to Enable DS_GFXCLK Feature Failed!",
return -EINVAL); return -EINVAL);
...@@ -2704,7 +2704,7 @@ static int vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) ...@@ -2704,7 +2704,7 @@ static int vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
} }
if (data->smu_features[GNLD_DS_SOCCLK].supported) { if (data->smu_features[GNLD_DS_SOCCLK].supported) {
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
true, data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap), true, data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap),
"Attempt to Enable DS_SOCCLK Feature Failed!", "Attempt to Enable DS_SOCCLK Feature Failed!",
return -EINVAL); return -EINVAL);
...@@ -2712,7 +2712,7 @@ static int vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) ...@@ -2712,7 +2712,7 @@ static int vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
} }
if (data->smu_features[GNLD_DS_LCLK].supported) { if (data->smu_features[GNLD_DS_LCLK].supported) {
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
true, data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap), true, data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap),
"Attempt to Enable DS_LCLK Feature Failed!", "Attempt to Enable DS_LCLK Feature Failed!",
return -EINVAL); return -EINVAL);
...@@ -2720,7 +2720,7 @@ static int vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) ...@@ -2720,7 +2720,7 @@ static int vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
} }
if (data->smu_features[GNLD_DS_DCEFCLK].supported) { if (data->smu_features[GNLD_DS_DCEFCLK].supported) {
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
true, data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap), true, data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap),
"Attempt to Enable DS_DCEFCLK Feature Failed!", "Attempt to Enable DS_DCEFCLK Feature Failed!",
return -EINVAL); return -EINVAL);
...@@ -2736,7 +2736,7 @@ static int vega10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) ...@@ -2736,7 +2736,7 @@ static int vega10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
(struct vega10_hwmgr *)(hwmgr->backend); (struct vega10_hwmgr *)(hwmgr->backend);
if (data->smu_features[GNLD_DS_GFXCLK].supported) { if (data->smu_features[GNLD_DS_GFXCLK].supported) {
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
false, data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap), false, data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap),
"Attempt to disable DS_GFXCLK Feature Failed!", "Attempt to disable DS_GFXCLK Feature Failed!",
return -EINVAL); return -EINVAL);
...@@ -2744,7 +2744,7 @@ static int vega10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) ...@@ -2744,7 +2744,7 @@ static int vega10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
} }
if (data->smu_features[GNLD_DS_SOCCLK].supported) { if (data->smu_features[GNLD_DS_SOCCLK].supported) {
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
false, data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap), false, data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap),
"Attempt to disable DS_ Feature Failed!", "Attempt to disable DS_ Feature Failed!",
return -EINVAL); return -EINVAL);
...@@ -2752,7 +2752,7 @@ static int vega10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) ...@@ -2752,7 +2752,7 @@ static int vega10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
} }
if (data->smu_features[GNLD_DS_LCLK].supported) { if (data->smu_features[GNLD_DS_LCLK].supported) {
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
false, data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap), false, data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap),
"Attempt to disable DS_LCLK Feature Failed!", "Attempt to disable DS_LCLK Feature Failed!",
return -EINVAL); return -EINVAL);
...@@ -2760,7 +2760,7 @@ static int vega10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) ...@@ -2760,7 +2760,7 @@ static int vega10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
} }
if (data->smu_features[GNLD_DS_DCEFCLK].supported) { if (data->smu_features[GNLD_DS_DCEFCLK].supported) {
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
false, data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap), false, data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap),
"Attempt to disable DS_DCEFCLK Feature Failed!", "Attempt to disable DS_DCEFCLK Feature Failed!",
return -EINVAL); return -EINVAL);
...@@ -2778,7 +2778,7 @@ static int vega10_stop_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap) ...@@ -2778,7 +2778,7 @@ static int vega10_stop_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)
if(data->smu_features[GNLD_LED_DISPLAY].supported == true){ if(data->smu_features[GNLD_LED_DISPLAY].supported == true){
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
false, data->smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap), false, data->smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap),
"Attempt to disable LED DPM feature failed!", return -EINVAL); "Attempt to disable LED DPM feature failed!", return -EINVAL);
data->smu_features[GNLD_LED_DISPLAY].enabled = false; data->smu_features[GNLD_LED_DISPLAY].enabled = false;
...@@ -2796,7 +2796,7 @@ static int vega10_stop_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap) ...@@ -2796,7 +2796,7 @@ static int vega10_stop_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)
} }
} }
vega10_enable_smc_features(hwmgr->smumgr, false, feature_mask); vega10_enable_smc_features(hwmgr, false, feature_mask);
return 0; return 0;
} }
...@@ -2826,7 +2826,7 @@ static int vega10_start_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap) ...@@ -2826,7 +2826,7 @@ static int vega10_start_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)
} }
} }
if (vega10_enable_smc_features(hwmgr->smumgr, if (vega10_enable_smc_features(hwmgr,
true, feature_mask)) { true, feature_mask)) {
for (i = 0; i < GNLD_DPM_MAX; i++) { for (i = 0; i < GNLD_DPM_MAX; i++) {
if (data->smu_features[i].smu_feature_bitmap & if (data->smu_features[i].smu_feature_bitmap &
...@@ -2836,21 +2836,21 @@ static int vega10_start_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap) ...@@ -2836,21 +2836,21 @@ static int vega10_start_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)
} }
if(data->smu_features[GNLD_LED_DISPLAY].supported == true){ if(data->smu_features[GNLD_LED_DISPLAY].supported == true){
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
true, data->smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap), true, data->smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap),
"Attempt to Enable LED DPM feature Failed!", return -EINVAL); "Attempt to Enable LED DPM feature Failed!", return -EINVAL);
data->smu_features[GNLD_LED_DISPLAY].enabled = true; data->smu_features[GNLD_LED_DISPLAY].enabled = true;
} }
if (data->vbios_boot_state.bsoc_vddc_lock) { if (data->vbios_boot_state.bsoc_vddc_lock) {
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetFloorSocVoltage, 0); PPSMC_MSG_SetFloorSocVoltage, 0);
data->vbios_boot_state.bsoc_vddc_lock = false; data->vbios_boot_state.bsoc_vddc_lock = false;
} }
if (PP_CAP(PHM_PlatformCaps_Falcon_QuickTransition)) { if (PP_CAP(PHM_PlatformCaps_Falcon_QuickTransition)) {
if (data->smu_features[GNLD_ACDC].supported) { if (data->smu_features[GNLD_ACDC].supported) {
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
true, data->smu_features[GNLD_ACDC].smu_feature_bitmap), true, data->smu_features[GNLD_ACDC].smu_feature_bitmap),
"Attempt to Enable DS_GFXCLK Feature Failed!", "Attempt to Enable DS_GFXCLK Feature Failed!",
return -1); return -1);
...@@ -2867,13 +2867,13 @@ static int vega10_enable_dpm_tasks(struct pp_hwmgr *hwmgr) ...@@ -2867,13 +2867,13 @@ static int vega10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
(struct vega10_hwmgr *)(hwmgr->backend); (struct vega10_hwmgr *)(hwmgr->backend);
int tmp_result, result = 0; int tmp_result, result = 0;
tmp_result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, tmp_result = smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_ConfigureTelemetry, data->config_telemetry); PPSMC_MSG_ConfigureTelemetry, data->config_telemetry);
PP_ASSERT_WITH_CODE(!tmp_result, PP_ASSERT_WITH_CODE(!tmp_result,
"Failed to configure telemetry!", "Failed to configure telemetry!",
return tmp_result); return tmp_result);
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_NumOfDisplays, 0); PPSMC_MSG_NumOfDisplays, 0);
tmp_result = (!vega10_is_dpm_running(hwmgr)) ? 0 : -1; tmp_result = (!vega10_is_dpm_running(hwmgr)) ? 0 : -1;
...@@ -3674,7 +3674,7 @@ static int vega10_upload_dpm_bootup_level(struct pp_hwmgr *hwmgr) ...@@ -3674,7 +3674,7 @@ static int vega10_upload_dpm_bootup_level(struct pp_hwmgr *hwmgr)
if (data->smc_state_table.gfx_boot_level != if (data->smc_state_table.gfx_boot_level !=
data->dpm_table.gfx_table.dpm_state.soft_min_level) { data->dpm_table.gfx_table.dpm_state.soft_min_level) {
PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter( PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr, hwmgr,
PPSMC_MSG_SetSoftMinGfxclkByIndex, PPSMC_MSG_SetSoftMinGfxclkByIndex,
data->smc_state_table.gfx_boot_level), data->smc_state_table.gfx_boot_level),
"Failed to set soft min sclk index!", "Failed to set soft min sclk index!",
...@@ -3690,14 +3690,14 @@ static int vega10_upload_dpm_bootup_level(struct pp_hwmgr *hwmgr) ...@@ -3690,14 +3690,14 @@ static int vega10_upload_dpm_bootup_level(struct pp_hwmgr *hwmgr)
if (data->smc_state_table.mem_boot_level == NUM_UCLK_DPM_LEVELS - 1) { if (data->smc_state_table.mem_boot_level == NUM_UCLK_DPM_LEVELS - 1) {
socclk_idx = vega10_get_soc_index_for_max_uclk(hwmgr); socclk_idx = vega10_get_soc_index_for_max_uclk(hwmgr);
PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter( PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr, hwmgr,
PPSMC_MSG_SetSoftMinSocclkByIndex, PPSMC_MSG_SetSoftMinSocclkByIndex,
socclk_idx), socclk_idx),
"Failed to set soft min uclk index!", "Failed to set soft min uclk index!",
return -EINVAL); return -EINVAL);
} else { } else {
PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter( PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr, hwmgr,
PPSMC_MSG_SetSoftMinUclkByIndex, PPSMC_MSG_SetSoftMinUclkByIndex,
data->smc_state_table.mem_boot_level), data->smc_state_table.mem_boot_level),
"Failed to set soft min uclk index!", "Failed to set soft min uclk index!",
...@@ -3722,7 +3722,7 @@ static int vega10_upload_dpm_max_level(struct pp_hwmgr *hwmgr) ...@@ -3722,7 +3722,7 @@ static int vega10_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
if (data->smc_state_table.gfx_max_level != if (data->smc_state_table.gfx_max_level !=
data->dpm_table.gfx_table.dpm_state.soft_max_level) { data->dpm_table.gfx_table.dpm_state.soft_max_level) {
PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter( PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr, hwmgr,
PPSMC_MSG_SetSoftMaxGfxclkByIndex, PPSMC_MSG_SetSoftMaxGfxclkByIndex,
data->smc_state_table.gfx_max_level), data->smc_state_table.gfx_max_level),
"Failed to set soft max sclk index!", "Failed to set soft max sclk index!",
...@@ -3736,7 +3736,7 @@ static int vega10_upload_dpm_max_level(struct pp_hwmgr *hwmgr) ...@@ -3736,7 +3736,7 @@ static int vega10_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
if (data->smc_state_table.mem_max_level != if (data->smc_state_table.mem_max_level !=
data->dpm_table.mem_table.dpm_state.soft_max_level) { data->dpm_table.mem_table.dpm_state.soft_max_level) {
PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter( PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr, hwmgr,
PPSMC_MSG_SetSoftMaxUclkByIndex, PPSMC_MSG_SetSoftMaxUclkByIndex,
data->smc_state_table.mem_max_level), data->smc_state_table.mem_max_level),
"Failed to set soft max mclk index!", "Failed to set soft max mclk index!",
...@@ -3795,7 +3795,7 @@ int vega10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable) ...@@ -3795,7 +3795,7 @@ int vega10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
(struct vega10_hwmgr *)(hwmgr->backend); (struct vega10_hwmgr *)(hwmgr->backend);
if (data->smu_features[GNLD_DPM_VCE].supported) { if (data->smu_features[GNLD_DPM_VCE].supported) {
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
enable, enable,
data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap), data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap),
"Attempt to Enable/Disable DPM VCE Failed!", "Attempt to Enable/Disable DPM VCE Failed!",
...@@ -3825,7 +3825,7 @@ static int vega10_update_sclk_threshold(struct pp_hwmgr *hwmgr) ...@@ -3825,7 +3825,7 @@ static int vega10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
cpu_to_le32(low_sclk_interrupt_threshold); cpu_to_le32(low_sclk_interrupt_threshold);
/* This message will also enable SmcToHost Interrupt */ /* This message will also enable SmcToHost Interrupt */
result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, result = smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetLowGfxclkInterruptThreshold, PPSMC_MSG_SetLowGfxclkInterruptThreshold,
(uint32_t)low_sclk_interrupt_threshold); (uint32_t)low_sclk_interrupt_threshold);
} }
...@@ -3861,7 +3861,7 @@ static int vega10_set_power_state_tasks(struct pp_hwmgr *hwmgr, ...@@ -3861,7 +3861,7 @@ static int vega10_set_power_state_tasks(struct pp_hwmgr *hwmgr,
"Failed to update SCLK threshold!", "Failed to update SCLK threshold!",
result = tmp_result); result = tmp_result);
result = vega10_copy_table_to_smc(hwmgr->smumgr, result = vega10_copy_table_to_smc(hwmgr,
(uint8_t *)pp_table, PPTABLE); (uint8_t *)pp_table, PPTABLE);
PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE(!result,
"Failed to upload PPtable!", return result); "Failed to upload PPtable!", return result);
...@@ -3921,12 +3921,12 @@ static int vega10_get_gpu_power(struct pp_hwmgr *hwmgr, ...@@ -3921,12 +3921,12 @@ static int vega10_get_gpu_power(struct pp_hwmgr *hwmgr,
{ {
uint32_t value; uint32_t value;
PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr, PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_GetCurrPkgPwr), PPSMC_MSG_GetCurrPkgPwr),
"Failed to get current package power!", "Failed to get current package power!",
return -EINVAL); return -EINVAL);
vega10_read_arg_from_smc(hwmgr->smumgr, &value); vega10_read_arg_from_smc(hwmgr, &value);
/* power value is an integer */ /* power value is an integer */
query->average_gpu_power = value << 8; query->average_gpu_power = value << 8;
...@@ -3943,25 +3943,25 @@ static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx, ...@@ -3943,25 +3943,25 @@ static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
switch (idx) { switch (idx) {
case AMDGPU_PP_SENSOR_GFX_SCLK: case AMDGPU_PP_SENSOR_GFX_SCLK:
ret = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetCurrentGfxclkIndex); ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentGfxclkIndex);
if (!ret) { if (!ret) {
vega10_read_arg_from_smc(hwmgr->smumgr, &sclk_idx); vega10_read_arg_from_smc(hwmgr, &sclk_idx);
*((uint32_t *)value) = dpm_table->gfx_table.dpm_levels[sclk_idx].value; *((uint32_t *)value) = dpm_table->gfx_table.dpm_levels[sclk_idx].value;
*size = 4; *size = 4;
} }
break; break;
case AMDGPU_PP_SENSOR_GFX_MCLK: case AMDGPU_PP_SENSOR_GFX_MCLK:
ret = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetCurrentUclkIndex); ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex);
if (!ret) { if (!ret) {
vega10_read_arg_from_smc(hwmgr->smumgr, &mclk_idx); vega10_read_arg_from_smc(hwmgr, &mclk_idx);
*((uint32_t *)value) = dpm_table->mem_table.dpm_levels[mclk_idx].value; *((uint32_t *)value) = dpm_table->mem_table.dpm_levels[mclk_idx].value;
*size = 4; *size = 4;
} }
break; break;
case AMDGPU_PP_SENSOR_GPU_LOAD: case AMDGPU_PP_SENSOR_GPU_LOAD:
ret = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_GetAverageGfxActivity, 0); ret = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetAverageGfxActivity, 0);
if (!ret) { if (!ret) {
vega10_read_arg_from_smc(hwmgr->smumgr, &activity_percent); vega10_read_arg_from_smc(hwmgr, &activity_percent);
*((uint32_t *)value) = activity_percent > 100 ? 100 : activity_percent; *((uint32_t *)value) = activity_percent > 100 ? 100 : activity_percent;
*size = 4; *size = 4;
} }
...@@ -3996,7 +3996,7 @@ static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx, ...@@ -3996,7 +3996,7 @@ static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
static int vega10_notify_smc_display_change(struct pp_hwmgr *hwmgr, static int vega10_notify_smc_display_change(struct pp_hwmgr *hwmgr,
bool has_disp) bool has_disp)
{ {
return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, return smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch,
has_disp ? 0 : 1); has_disp ? 0 : 1);
} }
...@@ -4031,7 +4031,7 @@ int vega10_display_clock_voltage_request(struct pp_hwmgr *hwmgr, ...@@ -4031,7 +4031,7 @@ int vega10_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
if (!result) { if (!result) {
clk_request = (clk_freq << 16) | clk_select; clk_request = (clk_freq << 16) | clk_select;
result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, result = smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_RequestDisplayClockByFreq, PPSMC_MSG_RequestDisplayClockByFreq,
clk_request); clk_request);
} }
...@@ -4101,7 +4101,7 @@ static int vega10_notify_smc_display_config_after_ps_adjustment( ...@@ -4101,7 +4101,7 @@ static int vega10_notify_smc_display_config_after_ps_adjustment(
clock_req.clock_freq_in_khz = dpm_table->dpm_levels[i].value; clock_req.clock_freq_in_khz = dpm_table->dpm_levels[i].value;
if (!vega10_display_clock_voltage_request(hwmgr, &clock_req)) { if (!vega10_display_clock_voltage_request(hwmgr, &clock_req)) {
PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter( PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr, PPSMC_MSG_SetMinDeepSleepDcefclk, hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk,
min_clocks.dcefClockInSR /100), min_clocks.dcefClockInSR /100),
"Attempt to set divider for DCEFCLK Failed!",); "Attempt to set divider for DCEFCLK Failed!",);
} else { } else {
...@@ -4113,7 +4113,7 @@ static int vega10_notify_smc_display_config_after_ps_adjustment( ...@@ -4113,7 +4113,7 @@ static int vega10_notify_smc_display_config_after_ps_adjustment(
if (min_clocks.memoryClock != 0) { if (min_clocks.memoryClock != 0) {
idx = vega10_get_uclk_index(hwmgr, mclk_table, min_clocks.memoryClock); idx = vega10_get_uclk_index(hwmgr, mclk_table, min_clocks.memoryClock);
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetSoftMinUclkByIndex, idx); smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetSoftMinUclkByIndex, idx);
data->dpm_table.mem_table.dpm_state.soft_min_level= idx; data->dpm_table.mem_table.dpm_state.soft_min_level= idx;
} }
...@@ -4596,11 +4596,11 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr, ...@@ -4596,11 +4596,11 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
if (data->registry_data.sclk_dpm_key_disabled) if (data->registry_data.sclk_dpm_key_disabled)
break; break;
PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr, PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_GetCurrentGfxclkIndex), PPSMC_MSG_GetCurrentGfxclkIndex),
"Attempt to get current sclk index Failed!", "Attempt to get current sclk index Failed!",
return -1); return -1);
PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr->smumgr, PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr,
&now), &now),
"Attempt to read sclk index Failed!", "Attempt to read sclk index Failed!",
return -1); return -1);
...@@ -4614,11 +4614,11 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr, ...@@ -4614,11 +4614,11 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
if (data->registry_data.mclk_dpm_key_disabled) if (data->registry_data.mclk_dpm_key_disabled)
break; break;
PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr, PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_GetCurrentUclkIndex), PPSMC_MSG_GetCurrentUclkIndex),
"Attempt to get current mclk index Failed!", "Attempt to get current mclk index Failed!",
return -1); return -1);
PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr->smumgr, PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr,
&now), &now),
"Attempt to read mclk index Failed!", "Attempt to read mclk index Failed!",
return -1); return -1);
...@@ -4629,11 +4629,11 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr, ...@@ -4629,11 +4629,11 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
(i == now) ? "*" : ""); (i == now) ? "*" : "");
break; break;
case PP_PCIE: case PP_PCIE:
PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr, PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_GetCurrentLinkIndex), PPSMC_MSG_GetCurrentLinkIndex),
"Attempt to get current mclk index Failed!", "Attempt to get current mclk index Failed!",
return -1); return -1);
PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr->smumgr, PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr,
&now), &now),
"Attempt to read mclk index Failed!", "Attempt to read mclk index Failed!",
return -1); return -1);
...@@ -4661,7 +4661,7 @@ static int vega10_display_configuration_changed_task(struct pp_hwmgr *hwmgr) ...@@ -4661,7 +4661,7 @@ static int vega10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
if ((data->water_marks_bitmap & WaterMarksExist) && if ((data->water_marks_bitmap & WaterMarksExist) &&
!(data->water_marks_bitmap & WaterMarksLoaded)) { !(data->water_marks_bitmap & WaterMarksLoaded)) {
result = vega10_copy_table_to_smc(hwmgr->smumgr, result = vega10_copy_table_to_smc(hwmgr,
(uint8_t *)wm_table, WMTABLE); (uint8_t *)wm_table, WMTABLE);
PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return EINVAL); PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return EINVAL);
data->water_marks_bitmap |= WaterMarksLoaded; data->water_marks_bitmap |= WaterMarksLoaded;
...@@ -4670,7 +4670,7 @@ static int vega10_display_configuration_changed_task(struct pp_hwmgr *hwmgr) ...@@ -4670,7 +4670,7 @@ static int vega10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
if (data->water_marks_bitmap & WaterMarksLoaded) { if (data->water_marks_bitmap & WaterMarksLoaded) {
cgs_get_active_displays_info(hwmgr->device, &info); cgs_get_active_displays_info(hwmgr->device, &info);
num_turned_on_displays = info.display_count; num_turned_on_displays = info.display_count;
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_NumOfDisplays, num_turned_on_displays); PPSMC_MSG_NumOfDisplays, num_turned_on_displays);
} }
...@@ -4683,7 +4683,7 @@ int vega10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable) ...@@ -4683,7 +4683,7 @@ int vega10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
(struct vega10_hwmgr *)(hwmgr->backend); (struct vega10_hwmgr *)(hwmgr->backend);
if (data->smu_features[GNLD_DPM_UVD].supported) { if (data->smu_features[GNLD_DPM_UVD].supported) {
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
enable, enable,
data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap), data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap),
"Attempt to Enable/Disable DPM UVD Failed!", "Attempt to Enable/Disable DPM UVD Failed!",
...@@ -4870,7 +4870,7 @@ static int vega10_set_power_profile_state(struct pp_hwmgr *hwmgr, ...@@ -4870,7 +4870,7 @@ static int vega10_set_power_profile_state(struct pp_hwmgr *hwmgr,
if (!data->registry_data.sclk_dpm_key_disabled) if (!data->registry_data.sclk_dpm_key_disabled)
PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE(
!smum_send_msg_to_smc_with_parameter( !smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr, hwmgr,
PPSMC_MSG_SetSoftMinGfxclkByIndex, PPSMC_MSG_SetSoftMinGfxclkByIndex,
sclk_idx), sclk_idx),
"Failed to set soft min sclk index!", "Failed to set soft min sclk index!",
...@@ -4881,7 +4881,7 @@ static int vega10_set_power_profile_state(struct pp_hwmgr *hwmgr, ...@@ -4881,7 +4881,7 @@ static int vega10_set_power_profile_state(struct pp_hwmgr *hwmgr,
if (!data->registry_data.mclk_dpm_key_disabled) if (!data->registry_data.mclk_dpm_key_disabled)
PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE(
!smum_send_msg_to_smc_with_parameter( !smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr, hwmgr,
PPSMC_MSG_SetSoftMinUclkByIndex, PPSMC_MSG_SetSoftMinUclkByIndex,
mclk_idx), mclk_idx),
"Failed to set soft min mclk index!", "Failed to set soft min mclk index!",
......
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
浏览文件 @ d3f8c0ab
...@@ -926,7 +926,7 @@ static void vega10_didt_set_mask(struct pp_hwmgr *hwmgr, const bool enable) ...@@ -926,7 +926,7 @@ static void vega10_didt_set_mask(struct pp_hwmgr *hwmgr, const bool enable)
if (enable) { if (enable) {
/* For Vega10, SMC does not support any mask yet. */ /* For Vega10, SMC does not support any mask yet. */
result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_ConfigureGfxDidt, didt_block_info); result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ConfigureGfxDidt, didt_block_info);
PP_ASSERT((0 == result), "[EnableDiDtConfig] SMC Configure Gfx Didt Failed!"); PP_ASSERT((0 == result), "[EnableDiDtConfig] SMC Configure Gfx Didt Failed!");
} }
} }
...@@ -1243,7 +1243,7 @@ int vega10_enable_didt_config(struct pp_hwmgr *hwmgr) ...@@ -1243,7 +1243,7 @@ int vega10_enable_didt_config(struct pp_hwmgr *hwmgr)
} }
if (0 == result) { if (0 == result) {
PP_ASSERT_WITH_CODE((!vega10_enable_smc_features(hwmgr->smumgr, true, data->smu_features[GNLD_DIDT].smu_feature_bitmap)), PP_ASSERT_WITH_CODE((!vega10_enable_smc_features(hwmgr, true, data->smu_features[GNLD_DIDT].smu_feature_bitmap)),
"[EnableDiDtConfig] Attempt to Enable DiDt feature Failed!", return result); "[EnableDiDtConfig] Attempt to Enable DiDt feature Failed!", return result);
data->smu_features[GNLD_DIDT].enabled = true; data->smu_features[GNLD_DIDT].enabled = true;
} }
...@@ -1290,7 +1290,7 @@ int vega10_disable_didt_config(struct pp_hwmgr *hwmgr) ...@@ -1290,7 +1290,7 @@ int vega10_disable_didt_config(struct pp_hwmgr *hwmgr)
} }
if (0 == result) { if (0 == result) {
PP_ASSERT_WITH_CODE((0 != vega10_enable_smc_features(hwmgr->smumgr, false, data->smu_features[GNLD_DIDT].smu_feature_bitmap)), PP_ASSERT_WITH_CODE((0 != vega10_enable_smc_features(hwmgr, false, data->smu_features[GNLD_DIDT].smu_feature_bitmap)),
"[DisableDiDtConfig] Attempt to Disable DiDt feature Failed!", return result); "[DisableDiDtConfig] Attempt to Disable DiDt feature Failed!", return result);
data->smu_features[GNLD_DIDT].enabled = false; data->smu_features[GNLD_DIDT].enabled = false;
} }
...@@ -1344,7 +1344,7 @@ int vega10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n) ...@@ -1344,7 +1344,7 @@ int vega10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)
(struct vega10_hwmgr *)(hwmgr->backend); (struct vega10_hwmgr *)(hwmgr->backend);
if (data->registry_data.enable_pkg_pwr_tracking_feature) if (data->registry_data.enable_pkg_pwr_tracking_feature)
return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, return smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetPptLimit, n); PPSMC_MSG_SetPptLimit, n);
return 0; return 0;
...@@ -1363,13 +1363,13 @@ int vega10_enable_power_containment(struct pp_hwmgr *hwmgr) ...@@ -1363,13 +1363,13 @@ int vega10_enable_power_containment(struct pp_hwmgr *hwmgr)
if (PP_CAP(PHM_PlatformCaps_PowerContainment)) { if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
if (data->smu_features[GNLD_PPT].supported) if (data->smu_features[GNLD_PPT].supported)
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
true, data->smu_features[GNLD_PPT].smu_feature_bitmap), true, data->smu_features[GNLD_PPT].smu_feature_bitmap),
"Attempt to enable PPT feature Failed!", "Attempt to enable PPT feature Failed!",
data->smu_features[GNLD_PPT].supported = false); data->smu_features[GNLD_PPT].supported = false);
if (data->smu_features[GNLD_TDC].supported) if (data->smu_features[GNLD_TDC].supported)
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
true, data->smu_features[GNLD_TDC].smu_feature_bitmap), true, data->smu_features[GNLD_TDC].smu_feature_bitmap),
"Attempt to enable PPT feature Failed!", "Attempt to enable PPT feature Failed!",
data->smu_features[GNLD_TDC].supported = false); data->smu_features[GNLD_TDC].supported = false);
...@@ -1390,13 +1390,13 @@ int vega10_disable_power_containment(struct pp_hwmgr *hwmgr) ...@@ -1390,13 +1390,13 @@ int vega10_disable_power_containment(struct pp_hwmgr *hwmgr)
if (PP_CAP(PHM_PlatformCaps_PowerContainment)) { if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
if (data->smu_features[GNLD_PPT].supported) if (data->smu_features[GNLD_PPT].supported)
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
false, data->smu_features[GNLD_PPT].smu_feature_bitmap), false, data->smu_features[GNLD_PPT].smu_feature_bitmap),
"Attempt to disable PPT feature Failed!", "Attempt to disable PPT feature Failed!",
data->smu_features[GNLD_PPT].supported = false); data->smu_features[GNLD_PPT].supported = false);
if (data->smu_features[GNLD_TDC].supported) if (data->smu_features[GNLD_TDC].supported)
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
false, data->smu_features[GNLD_TDC].smu_feature_bitmap), false, data->smu_features[GNLD_TDC].smu_feature_bitmap),
"Attempt to disable PPT feature Failed!", "Attempt to disable PPT feature Failed!",
data->smu_features[GNLD_TDC].supported = false); data->smu_features[GNLD_TDC].supported = false);
...@@ -1408,7 +1408,7 @@ int vega10_disable_power_containment(struct pp_hwmgr *hwmgr) ...@@ -1408,7 +1408,7 @@ int vega10_disable_power_containment(struct pp_hwmgr *hwmgr)
static int vega10_set_overdrive_target_percentage(struct pp_hwmgr *hwmgr, static int vega10_set_overdrive_target_percentage(struct pp_hwmgr *hwmgr,
uint32_t adjust_percent) uint32_t adjust_percent)
{ {
return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, return smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_OverDriveSetPercentage, adjust_percent); PPSMC_MSG_OverDriveSetPercentage, adjust_percent);
} }
......
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
浏览文件 @ d3f8c0ab
...@@ -31,11 +31,11 @@ ...@@ -31,11 +31,11 @@
static int vega10_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm) static int vega10_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm)
{ {
PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr, PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_GetCurrentRpm), PPSMC_MSG_GetCurrentRpm),
"Attempt to get current RPM from SMC Failed!", "Attempt to get current RPM from SMC Failed!",
return -1); return -1);
PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr->smumgr, PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr,
current_rpm), current_rpm),
"Attempt to read current RPM from SMC Failed!", "Attempt to read current RPM from SMC Failed!",
return -1); return -1);
...@@ -199,7 +199,7 @@ static int vega10_enable_fan_control_feature(struct pp_hwmgr *hwmgr) ...@@ -199,7 +199,7 @@ static int vega10_enable_fan_control_feature(struct pp_hwmgr *hwmgr)
if (data->smu_features[GNLD_FAN_CONTROL].supported) { if (data->smu_features[GNLD_FAN_CONTROL].supported) {
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features( PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(
hwmgr->smumgr, true, hwmgr, true,
data->smu_features[GNLD_FAN_CONTROL]. data->smu_features[GNLD_FAN_CONTROL].
smu_feature_bitmap), smu_feature_bitmap),
"Attempt to Enable FAN CONTROL feature Failed!", "Attempt to Enable FAN CONTROL feature Failed!",
...@@ -216,7 +216,7 @@ static int vega10_disable_fan_control_feature(struct pp_hwmgr *hwmgr) ...@@ -216,7 +216,7 @@ static int vega10_disable_fan_control_feature(struct pp_hwmgr *hwmgr)
if (data->smu_features[GNLD_FAN_CONTROL].supported) { if (data->smu_features[GNLD_FAN_CONTROL].supported) {
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features( PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(
hwmgr->smumgr, false, hwmgr, false,
data->smu_features[GNLD_FAN_CONTROL]. data->smu_features[GNLD_FAN_CONTROL].
smu_feature_bitmap), smu_feature_bitmap),
"Attempt to Enable FAN CONTROL feature Failed!", "Attempt to Enable FAN CONTROL feature Failed!",
...@@ -458,7 +458,7 @@ static int vega10_thermal_enable_alert(struct pp_hwmgr *hwmgr) ...@@ -458,7 +458,7 @@ static int vega10_thermal_enable_alert(struct pp_hwmgr *hwmgr)
if (data->smu_features[GNLD_FW_CTF].enabled) if (data->smu_features[GNLD_FW_CTF].enabled)
printk("[Thermal_EnableAlert] FW CTF Already Enabled!\n"); printk("[Thermal_EnableAlert] FW CTF Already Enabled!\n");
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
true, true,
data->smu_features[GNLD_FW_CTF].smu_feature_bitmap), data->smu_features[GNLD_FW_CTF].smu_feature_bitmap),
"Attempt to Enable FW CTF feature Failed!", "Attempt to Enable FW CTF feature Failed!",
...@@ -490,7 +490,7 @@ int vega10_thermal_disable_alert(struct pp_hwmgr *hwmgr) ...@@ -490,7 +490,7 @@ int vega10_thermal_disable_alert(struct pp_hwmgr *hwmgr)
printk("[Thermal_EnableAlert] FW CTF Already disabled!\n"); printk("[Thermal_EnableAlert] FW CTF Already disabled!\n");
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
false, false,
data->smu_features[GNLD_FW_CTF].smu_feature_bitmap), data->smu_features[GNLD_FW_CTF].smu_feature_bitmap),
"Attempt to disable FW CTF feature Failed!", "Attempt to disable FW CTF feature Failed!",
...@@ -546,7 +546,7 @@ int vega10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) ...@@ -546,7 +546,7 @@ int vega10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
table->FanTargetTemperature = hwmgr->thermal_controller. table->FanTargetTemperature = hwmgr->thermal_controller.
advanceFanControlParameters.usTMax; advanceFanControlParameters.usTMax;
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetFanTemperatureTarget, PPSMC_MSG_SetFanTemperatureTarget,
(uint32_t)table->FanTargetTemperature); (uint32_t)table->FanTargetTemperature);
...@@ -575,7 +575,7 @@ int vega10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) ...@@ -575,7 +575,7 @@ int vega10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
table->FanStartTemp = hwmgr->thermal_controller. table->FanStartTemp = hwmgr->thermal_controller.
advanceFanControlParameters.usZeroRPMStartTemperature; advanceFanControlParameters.usZeroRPMStartTemperature;
ret = vega10_copy_table_to_smc(hwmgr->smumgr, ret = vega10_copy_table_to_smc(hwmgr,
(uint8_t *)(&(data->smc_state_table.pp_table)), PPTABLE); (uint8_t *)(&(data->smc_state_table.pp_table)), PPTABLE);
if (ret) if (ret)
pr_info("Failed to update Fan Control Table in PPTable!"); pr_info("Failed to update Fan Control Table in PPTable!");
......
drivers/gpu/drm/amd/powerplay/inc/smumgr.h
浏览文件 @ d3f8c0ab
...@@ -103,21 +103,21 @@ enum SMU_MAC_DEFINITION { ...@@ -103,21 +103,21 @@ enum SMU_MAC_DEFINITION {
struct pp_smumgr_func { struct pp_smumgr_func {
int (*smu_init)(struct pp_smumgr *smumgr); int (*smu_init)(struct pp_hwmgr *hwmgr);
int (*smu_fini)(struct pp_smumgr *smumgr); int (*smu_fini)(struct pp_hwmgr *hwmgr);
int (*start_smu)(struct pp_smumgr *smumgr); int (*start_smu)(struct pp_hwmgr *hwmgr);
int (*check_fw_load_finish)(struct pp_smumgr *smumgr, int (*check_fw_load_finish)(struct pp_hwmgr *hwmgr,
uint32_t firmware); uint32_t firmware);
int (*request_smu_load_fw)(struct pp_smumgr *smumgr); int (*request_smu_load_fw)(struct pp_hwmgr *hwmgr);
int (*request_smu_load_specific_fw)(struct pp_smumgr *smumgr, int (*request_smu_load_specific_fw)(struct pp_hwmgr *hwmgr,
uint32_t firmware); uint32_t firmware);
int (*get_argument)(struct pp_smumgr *smumgr); int (*get_argument)(struct pp_hwmgr *hwmgr);
int (*send_msg_to_smc)(struct pp_smumgr *smumgr, uint16_t msg); int (*send_msg_to_smc)(struct pp_hwmgr *hwmgr, uint16_t msg);
int (*send_msg_to_smc_with_parameter)(struct pp_smumgr *smumgr, int (*send_msg_to_smc_with_parameter)(struct pp_hwmgr *hwmgr,
uint16_t msg, uint32_t parameter); uint16_t msg, uint32_t parameter);
int (*download_pptable_settings)(struct pp_smumgr *smumgr, int (*download_pptable_settings)(struct pp_hwmgr *hwmgr,
void **table); void **table);
int (*upload_pptable_settings)(struct pp_smumgr *smumgr); int (*upload_pptable_settings)(struct pp_hwmgr *hwmgr);
int (*update_smc_table)(struct pp_hwmgr *hwmgr, uint32_t type); int (*update_smc_table)(struct pp_hwmgr *hwmgr, uint32_t type);
int (*process_firmware_header)(struct pp_hwmgr *hwmgr); int (*process_firmware_header)(struct pp_hwmgr *hwmgr);
int (*update_sclk_threshold)(struct pp_hwmgr *hwmgr); int (*update_sclk_threshold)(struct pp_hwmgr *hwmgr);
...@@ -132,7 +132,7 @@ struct pp_smumgr_func { ...@@ -132,7 +132,7 @@ struct pp_smumgr_func {
bool (*is_dpm_running)(struct pp_hwmgr *hwmgr); bool (*is_dpm_running)(struct pp_hwmgr *hwmgr);
int (*populate_requested_graphic_levels)(struct pp_hwmgr *hwmgr, int (*populate_requested_graphic_levels)(struct pp_hwmgr *hwmgr,
struct amd_pp_profile *request); struct amd_pp_profile *request);
bool (*is_hw_avfs_present)(struct pp_smumgr *smumgr); bool (*is_hw_avfs_present)(struct pp_hwmgr *hwmgr);
}; };
struct pp_smumgr { struct pp_smumgr {
...@@ -148,30 +148,30 @@ struct pp_smumgr { ...@@ -148,30 +148,30 @@ struct pp_smumgr {
extern int smum_early_init(struct pp_instance *handle); extern int smum_early_init(struct pp_instance *handle);
extern int smum_get_argument(struct pp_smumgr *smumgr); extern int smum_get_argument(struct pp_hwmgr *hwmgr);
extern int smum_download_powerplay_table(struct pp_smumgr *smumgr, void **table); extern int smum_download_powerplay_table(struct pp_hwmgr *hwmgr, void **table);
extern int smum_upload_powerplay_table(struct pp_smumgr *smumgr); extern int smum_upload_powerplay_table(struct pp_hwmgr *hwmgr);
extern int smum_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg); extern int smum_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg);
extern int smum_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, extern int smum_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
uint16_t msg, uint32_t parameter); uint16_t msg, uint32_t parameter);
extern int smum_wait_on_register(struct pp_smumgr *smumgr, extern int smum_wait_on_register(struct pp_hwmgr *hwmgr,
uint32_t index, uint32_t value, uint32_t mask); uint32_t index, uint32_t value, uint32_t mask);
extern int smum_wait_for_register_unequal(struct pp_smumgr *smumgr, extern int smum_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
uint32_t index, uint32_t value, uint32_t mask); uint32_t index, uint32_t value, uint32_t mask);
extern int smum_wait_on_indirect_register(struct pp_smumgr *smumgr, extern int smum_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
uint32_t indirect_port, uint32_t index, uint32_t indirect_port, uint32_t index,
uint32_t value, uint32_t mask); uint32_t value, uint32_t mask);
extern void smum_wait_for_indirect_register_unequal( extern void smum_wait_for_indirect_register_unequal(
struct pp_smumgr *smumgr, struct pp_hwmgr *hwmgr,
uint32_t indirect_port, uint32_t index, uint32_t indirect_port, uint32_t index,
uint32_t value, uint32_t mask); uint32_t value, uint32_t mask);
...@@ -181,7 +181,7 @@ extern int smu_allocate_memory(void *device, uint32_t size, ...@@ -181,7 +181,7 @@ extern int smu_allocate_memory(void *device, uint32_t size,
void **kptr, void *handle); void **kptr, void *handle);
extern int smu_free_memory(void *device, void *handle); extern int smu_free_memory(void *device, void *handle);
extern int vega10_smum_init(struct pp_smumgr *smumgr); extern int vega10_smum_init(struct pp_hwmgr *hwmgr);
extern int smum_update_sclk_threshold(struct pp_hwmgr *hwmgr); extern int smum_update_sclk_threshold(struct pp_hwmgr *hwmgr);
...@@ -193,44 +193,44 @@ extern int smum_init_smc_table(struct pp_hwmgr *hwmgr); ...@@ -193,44 +193,44 @@ extern int smum_init_smc_table(struct pp_hwmgr *hwmgr);
extern int smum_populate_all_graphic_levels(struct pp_hwmgr *hwmgr); extern int smum_populate_all_graphic_levels(struct pp_hwmgr *hwmgr);
extern int smum_populate_all_memory_levels(struct pp_hwmgr *hwmgr); extern int smum_populate_all_memory_levels(struct pp_hwmgr *hwmgr);
extern int smum_initialize_mc_reg_table(struct pp_hwmgr *hwmgr); extern int smum_initialize_mc_reg_table(struct pp_hwmgr *hwmgr);
extern uint32_t smum_get_offsetof(struct pp_smumgr *smumgr, extern uint32_t smum_get_offsetof(struct pp_hwmgr *hwmgr,
uint32_t type, uint32_t member); uint32_t type, uint32_t member);
extern uint32_t smum_get_mac_definition(struct pp_smumgr *smumgr, uint32_t value); extern uint32_t smum_get_mac_definition(struct pp_hwmgr *hwmgr, uint32_t value);
extern bool smum_is_dpm_running(struct pp_hwmgr *hwmgr); extern bool smum_is_dpm_running(struct pp_hwmgr *hwmgr);
extern int smum_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr, extern int smum_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
struct amd_pp_profile *request); struct amd_pp_profile *request);
extern bool smum_is_hw_avfs_present(struct pp_smumgr *smumgr); extern bool smum_is_hw_avfs_present(struct pp_hwmgr *hwmgr);
#define SMUM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT #define SMUM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
#define SMUM_FIELD_MASK(reg, field) reg##__##field##_MASK #define SMUM_FIELD_MASK(reg, field) reg##__##field##_MASK
#define SMUM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(smumgr, \ #define SMUM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, \
port, index, value, mask) \ port, index, value, mask) \
smum_wait_on_indirect_register(smumgr, \ smum_wait_on_indirect_register(hwmgr, \
mm##port##_INDEX, index, value, mask) mm##port##_INDEX, index, value, mask)
#define SMUM_WAIT_INDIRECT_REGISTER(smumgr, port, reg, value, mask) \ #define SMUM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \
SMUM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(smumgr, port, ix##reg, value, mask) SMUM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
#define SMUM_WAIT_INDIRECT_FIELD(smumgr, port, reg, field, fieldval) \ #define SMUM_WAIT_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \
SMUM_WAIT_INDIRECT_REGISTER(smumgr, port, reg, (fieldval) << SMUM_FIELD_SHIFT(reg, field), \ SMUM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) << SMUM_FIELD_SHIFT(reg, field), \
SMUM_FIELD_MASK(reg, field) ) SMUM_FIELD_MASK(reg, field) )
#define SMUM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, \ #define SMUM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, \
index, value, mask) \ index, value, mask) \
smum_wait_for_register_unequal(smumgr, \ smum_wait_for_register_unequal(hwmgr, \
index, value, mask) index, value, mask)
#define SMUM_WAIT_REGISTER_UNEQUAL(smumgr, reg, value, mask) \ #define SMUM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, value, mask) \
SMUM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, \ SMUM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, \
mm##reg, value, mask) mm##reg, value, mask)
#define SMUM_WAIT_FIELD_UNEQUAL(smumgr, reg, field, fieldval) \ #define SMUM_WAIT_FIELD_UNEQUAL(hwmgr, reg, field, fieldval) \
SMUM_WAIT_REGISTER_UNEQUAL(smumgr, reg, \ SMUM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, \
(fieldval) << SMUM_FIELD_SHIFT(reg, field), \ (fieldval) << SMUM_FIELD_SHIFT(reg, field), \
SMUM_FIELD_MASK(reg, field)) SMUM_FIELD_MASK(reg, field))
...@@ -250,22 +250,22 @@ extern bool smum_is_hw_avfs_present(struct pp_smumgr *smumgr); ...@@ -250,22 +250,22 @@ extern bool smum_is_hw_avfs_present(struct pp_smumgr *smumgr);
SMUM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \ SMUM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
reg, field) reg, field)
#define SMUM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(smumgr, \ #define SMUM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, \
port, index, value, mask) \ port, index, value, mask) \
smum_wait_on_indirect_register(smumgr, \ smum_wait_on_indirect_register(hwmgr, \
mm##port##_INDEX_0, index, value, mask) mm##port##_INDEX_0, index, value, mask)
#define SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, \ #define SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, \
port, index, value, mask) \ port, index, value, mask) \
smum_wait_for_indirect_register_unequal(smumgr, \ smum_wait_for_indirect_register_unequal(hwmgr, \
mm##port##_INDEX_0, index, value, mask) mm##port##_INDEX_0, index, value, mask)
#define SMUM_WAIT_VFPF_INDIRECT_REGISTER(smumgr, port, reg, value, mask) \ #define SMUM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \
SMUM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(smumgr, port, ix##reg, value, mask) SMUM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
#define SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(smumgr, port, reg, value, mask) \ #define SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \
SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, port, ix##reg, value, mask) SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
/*Operations on named fields.*/ /*Operations on named fields.*/
...@@ -290,25 +290,25 @@ extern bool smum_is_hw_avfs_present(struct pp_smumgr *smumgr); ...@@ -290,25 +290,25 @@ extern bool smum_is_hw_avfs_present(struct pp_smumgr *smumgr);
reg, field, fieldval)) reg, field, fieldval))
#define SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, port, reg, field, fieldval) \ #define SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \
SMUM_WAIT_VFPF_INDIRECT_REGISTER(smumgr, port, reg, \ SMUM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, \
(fieldval) << SMUM_FIELD_SHIFT(reg, field), \ (fieldval) << SMUM_FIELD_SHIFT(reg, field), \
SMUM_FIELD_MASK(reg, field)) SMUM_FIELD_MASK(reg, field))
#define SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, port, reg, field, fieldval) \ #define SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \
SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(smumgr, port, reg, \ SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, \
(fieldval) << SMUM_FIELD_SHIFT(reg, field), \ (fieldval) << SMUM_FIELD_SHIFT(reg, field), \
SMUM_FIELD_MASK(reg, field)) SMUM_FIELD_MASK(reg, field))
#define SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, port, index, value, mask) \ #define SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, index, value, mask) \
smum_wait_for_indirect_register_unequal(smumgr, \ smum_wait_for_indirect_register_unequal(hwmgr, \
mm##port##_INDEX, index, value, mask) mm##port##_INDEX, index, value, mask)
#define SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL(smumgr, port, reg, value, mask) \ #define SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \
SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, port, ix##reg, value, mask) SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
#define SMUM_WAIT_INDIRECT_FIELD_UNEQUAL(smumgr, port, reg, field, fieldval) \ #define SMUM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \
SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL(smumgr, port, reg, (fieldval) << SMUM_FIELD_SHIFT(reg, field), \ SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, (fieldval) << SMUM_FIELD_SHIFT(reg, field), \
SMUM_FIELD_MASK(reg, field) ) SMUM_FIELD_MASK(reg, field) )
#endif #endif
drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c
浏览文件 @ d3f8c0ab
...@@ -94,7 +94,7 @@ static const struct ci_pt_defaults defaults_saturn_xt = { ...@@ -94,7 +94,7 @@ static const struct ci_pt_defaults defaults_saturn_xt = {
}; };
static int ci_set_smc_sram_address(struct pp_smumgr *smumgr, static int ci_set_smc_sram_address(struct pp_hwmgr *hwmgr,
uint32_t smc_addr, uint32_t limit) uint32_t smc_addr, uint32_t limit)
{ {
if ((0 != (3 & smc_addr)) if ((0 != (3 & smc_addr))
...@@ -103,12 +103,12 @@ static int ci_set_smc_sram_address(struct pp_smumgr *smumgr, ...@@ -103,12 +103,12 @@ static int ci_set_smc_sram_address(struct pp_smumgr *smumgr,
return -EINVAL; return -EINVAL;
} }
cgs_write_register(smumgr->device, mmSMC_IND_INDEX_0, smc_addr); cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_0, smc_addr);
SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0); SMUM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0);
return 0; return 0;
} }
static int ci_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address, static int ci_copy_bytes_to_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address,
const uint8_t *src, uint32_t byte_count, uint32_t limit) const uint8_t *src, uint32_t byte_count, uint32_t limit)
{ {
int result; int result;
...@@ -129,12 +129,12 @@ static int ci_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_add ...@@ -129,12 +129,12 @@ static int ci_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_add
/* Bytes are written into the SMC address space with the MSB first. */ /* Bytes are written into the SMC address space with the MSB first. */
data = src[0] * 0x1000000 + src[1] * 0x10000 + src[2] * 0x100 + src[3]; data = src[0] * 0x1000000 + src[1] * 0x10000 + src[2] * 0x100 + src[3];
result = ci_set_smc_sram_address(smumgr, addr, limit); result = ci_set_smc_sram_address(hwmgr, addr, limit);
if (0 != result) if (0 != result)
return result; return result;
cgs_write_register(smumgr->device, mmSMC_IND_DATA_0, data); cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data);
src += 4; src += 4;
byte_count -= 4; byte_count -= 4;
...@@ -145,13 +145,13 @@ static int ci_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_add ...@@ -145,13 +145,13 @@ static int ci_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_add
data = 0; data = 0;
result = ci_set_smc_sram_address(smumgr, addr, limit); result = ci_set_smc_sram_address(hwmgr, addr, limit);
if (0 != result) if (0 != result)
return result; return result;
original_data = cgs_read_register(smumgr->device, mmSMC_IND_DATA_0); original_data = cgs_read_register(hwmgr->device, mmSMC_IND_DATA_0);
extra_shift = 8 * (4 - byte_count); extra_shift = 8 * (4 - byte_count);
...@@ -165,61 +165,61 @@ static int ci_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_add ...@@ -165,61 +165,61 @@ static int ci_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_add
data |= (original_data & ~((~0UL) << extra_shift)); data |= (original_data & ~((~0UL) << extra_shift));
result = ci_set_smc_sram_address(smumgr, addr, limit); result = ci_set_smc_sram_address(hwmgr, addr, limit);
if (0 != result) if (0 != result)
return result; return result;
cgs_write_register(smumgr->device, mmSMC_IND_DATA_0, data); cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data);
} }
return 0; return 0;
} }
static int ci_program_jump_on_start(struct pp_smumgr *smumgr) static int ci_program_jump_on_start(struct pp_hwmgr *hwmgr)
{ {
static const unsigned char data[4] = { 0xE0, 0x00, 0x80, 0x40 }; static const unsigned char data[4] = { 0xE0, 0x00, 0x80, 0x40 };
ci_copy_bytes_to_smc(smumgr, 0x0, data, 4, sizeof(data)+1); ci_copy_bytes_to_smc(hwmgr, 0x0, data, 4, sizeof(data)+1);
return 0; return 0;
} }
bool ci_is_smc_ram_running(struct pp_smumgr *smumgr) bool ci_is_smc_ram_running(struct pp_hwmgr *hwmgr)
{ {
return ((0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, return ((0 == SMUM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable)) CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable))
&& (0x20100 <= cgs_read_ind_register(smumgr->device, && (0x20100 <= cgs_read_ind_register(hwmgr->device,
CGS_IND_REG__SMC, ixSMC_PC_C))); CGS_IND_REG__SMC, ixSMC_PC_C)));
} }
static int ci_read_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, static int ci_read_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr,
uint32_t *value, uint32_t limit) uint32_t *value, uint32_t limit)
{ {
int result; int result;
result = ci_set_smc_sram_address(smumgr, smc_addr, limit); result = ci_set_smc_sram_address(hwmgr, smc_addr, limit);
if (result) if (result)
return result; return result;
*value = cgs_read_register(smumgr->device, mmSMC_IND_DATA_0); *value = cgs_read_register(hwmgr->device, mmSMC_IND_DATA_0);
return 0; return 0;
} }
int ci_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg) int ci_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
{ {
int ret; int ret;
if (!ci_is_smc_ram_running(smumgr)) if (!ci_is_smc_ram_running(hwmgr))
return -EINVAL; return -EINVAL;
cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg); cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, msg);
SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0); SMUM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);
ret = SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP); ret = SMUM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP);
if (ret != 1) if (ret != 1)
pr_info("\n failed to send message %x ret is %d\n", msg, ret); pr_info("\n failed to send message %x ret is %d\n", msg, ret);
...@@ -227,11 +227,11 @@ int ci_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg) ...@@ -227,11 +227,11 @@ int ci_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
return 0; return 0;
} }
int ci_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, int ci_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
uint16_t msg, uint32_t parameter) uint16_t msg, uint32_t parameter)
{ {
cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, parameter); cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, parameter);
return ci_send_msg_to_smc(smumgr, msg); return ci_send_msg_to_smc(hwmgr, msg);
} }
static void ci_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr) static void ci_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
...@@ -510,7 +510,7 @@ int ci_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) ...@@ -510,7 +510,7 @@ int ci_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
data->dpm_level_enable_mask.sclk_dpm_enable_mask = data->dpm_level_enable_mask.sclk_dpm_enable_mask =
phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
result = ci_copy_bytes_to_smc(hwmgr->smumgr, array, result = ci_copy_bytes_to_smc(hwmgr, array,
(u8 *)levels, array_size, (u8 *)levels, array_size,
SMC_RAM_END); SMC_RAM_END);
...@@ -553,7 +553,7 @@ static int ci_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset) ...@@ -553,7 +553,7 @@ static int ci_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
const struct ci_pt_defaults *defaults = smu_data->power_tune_defaults; const struct ci_pt_defaults *defaults = smu_data->power_tune_defaults;
uint32_t temp; uint32_t temp;
if (ci_read_smc_sram_dword(hwmgr->smumgr, if (ci_read_smc_sram_dword(hwmgr,
fuse_table_offset + fuse_table_offset +
offsetof(SMU7_Discrete_PmFuses, TdcWaterfallCtl), offsetof(SMU7_Discrete_PmFuses, TdcWaterfallCtl),
(uint32_t *)&temp, SMC_RAM_END)) (uint32_t *)&temp, SMC_RAM_END))
...@@ -686,7 +686,7 @@ static int ci_populate_pm_fuses(struct pp_hwmgr *hwmgr) ...@@ -686,7 +686,7 @@ static int ci_populate_pm_fuses(struct pp_hwmgr *hwmgr)
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_PowerContainment)) { PHM_PlatformCaps_PowerContainment)) {
if (ci_read_smc_sram_dword(hwmgr->smumgr, if (ci_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION + SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU7_Firmware_Header, PmFuseTable), offsetof(SMU7_Firmware_Header, PmFuseTable),
&pm_fuse_table_offset, SMC_RAM_END)) { &pm_fuse_table_offset, SMC_RAM_END)) {
...@@ -713,7 +713,7 @@ static int ci_populate_pm_fuses(struct pp_hwmgr *hwmgr) ...@@ -713,7 +713,7 @@ static int ci_populate_pm_fuses(struct pp_hwmgr *hwmgr)
if (ret) if (ret)
return ret; return ret;
ret = ci_copy_bytes_to_smc(hwmgr->smumgr, pm_fuse_table_offset, ret = ci_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
(uint8_t *)&smu_data->power_tune_table, (uint8_t *)&smu_data->power_tune_table,
sizeof(struct SMU7_Discrete_PmFuses), SMC_RAM_END); sizeof(struct SMU7_Discrete_PmFuses), SMC_RAM_END);
} }
...@@ -1343,7 +1343,7 @@ int ci_populate_all_memory_levels(struct pp_hwmgr *hwmgr) ...@@ -1343,7 +1343,7 @@ int ci_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH; smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
result = ci_copy_bytes_to_smc(hwmgr->smumgr, result = ci_copy_bytes_to_smc(hwmgr,
level_array_address, (uint8_t *)levels, (uint32_t)level_array_size, level_array_address, (uint8_t *)levels, (uint32_t)level_array_size,
SMC_RAM_END); SMC_RAM_END);
...@@ -1705,7 +1705,7 @@ static int ci_program_memory_timing_parameters(struct pp_hwmgr *hwmgr) ...@@ -1705,7 +1705,7 @@ static int ci_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
if (0 == result) { if (0 == result) {
result = ci_copy_bytes_to_smc( result = ci_copy_bytes_to_smc(
hwmgr->smumgr, hwmgr,
smu_data->arb_table_start, smu_data->arb_table_start,
(uint8_t *)&arb_regs, (uint8_t *)&arb_regs,
sizeof(SMU7_Discrete_MCArbDramTimingTable), sizeof(SMU7_Discrete_MCArbDramTimingTable),
...@@ -1756,10 +1756,10 @@ static int ci_populate_smc_boot_level(struct pp_hwmgr *hwmgr, ...@@ -1756,10 +1756,10 @@ static int ci_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
return result; return result;
} }
static int ci_populate_mc_reg_address(struct pp_smumgr *smumgr, static int ci_populate_mc_reg_address(struct pp_hwmgr *hwmgr,
SMU7_Discrete_MCRegisters *mc_reg_table) SMU7_Discrete_MCRegisters *mc_reg_table)
{ {
const struct ci_smumgr *smu_data = (struct ci_smumgr *)smumgr->backend; const struct ci_smumgr *smu_data = (struct ci_smumgr *)hwmgr->smumgr->backend;
uint32_t i, j; uint32_t i, j;
...@@ -1796,12 +1796,12 @@ static void ci_convert_mc_registers( ...@@ -1796,12 +1796,12 @@ static void ci_convert_mc_registers(
} }
static int ci_convert_mc_reg_table_entry_to_smc( static int ci_convert_mc_reg_table_entry_to_smc(
struct pp_smumgr *smumgr, struct pp_hwmgr *hwmgr,
const uint32_t memory_clock, const uint32_t memory_clock,
SMU7_Discrete_MCRegisterSet *mc_reg_table_data SMU7_Discrete_MCRegisterSet *mc_reg_table_data
) )
{ {
struct ci_smumgr *smu_data = (struct ci_smumgr *)(smumgr->backend); struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend);
uint32_t i = 0; uint32_t i = 0;
for (i = 0; i < smu_data->mc_reg_table.num_entries; i++) { for (i = 0; i < smu_data->mc_reg_table.num_entries; i++) {
...@@ -1831,7 +1831,7 @@ static int ci_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr, ...@@ -1831,7 +1831,7 @@ static int ci_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
for (i = 0; i < data->dpm_table.mclk_table.count; i++) { for (i = 0; i < data->dpm_table.mclk_table.count; i++) {
res = ci_convert_mc_reg_table_entry_to_smc( res = ci_convert_mc_reg_table_entry_to_smc(
hwmgr->smumgr, hwmgr,
data->dpm_table.mclk_table.dpm_levels[i].value, data->dpm_table.mclk_table.dpm_levels[i].value,
&mc_regs->data[i] &mc_regs->data[i]
); );
...@@ -1845,8 +1845,7 @@ static int ci_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr, ...@@ -1845,8 +1845,7 @@ static int ci_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
static int ci_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr) static int ci_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
{ {
struct pp_smumgr *smumgr = hwmgr->smumgr; struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend);
struct ci_smumgr *smu_data = (struct ci_smumgr *)(smumgr->backend);
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
uint32_t address; uint32_t address;
int32_t result; int32_t result;
...@@ -1864,7 +1863,7 @@ static int ci_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr) ...@@ -1864,7 +1863,7 @@ static int ci_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
address = smu_data->mc_reg_table_start + (uint32_t)offsetof(SMU7_Discrete_MCRegisters, data[0]); address = smu_data->mc_reg_table_start + (uint32_t)offsetof(SMU7_Discrete_MCRegisters, data[0]);
return ci_copy_bytes_to_smc(hwmgr->smumgr, address, return ci_copy_bytes_to_smc(hwmgr, address,
(uint8_t *)&smu_data->mc_regs.data[0], (uint8_t *)&smu_data->mc_regs.data[0],
sizeof(SMU7_Discrete_MCRegisterSet) * data->dpm_table.mclk_table.count, sizeof(SMU7_Discrete_MCRegisterSet) * data->dpm_table.mclk_table.count,
SMC_RAM_END); SMC_RAM_END);
...@@ -1873,11 +1872,10 @@ static int ci_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr) ...@@ -1873,11 +1872,10 @@ static int ci_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
static int ci_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr) static int ci_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
{ {
int result; int result;
struct pp_smumgr *smumgr = hwmgr->smumgr; struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend);
struct ci_smumgr *smu_data = (struct ci_smumgr *)(smumgr->backend);
memset(&smu_data->mc_regs, 0x00, sizeof(SMU7_Discrete_MCRegisters)); memset(&smu_data->mc_regs, 0x00, sizeof(SMU7_Discrete_MCRegisters));
result = ci_populate_mc_reg_address(smumgr, &(smu_data->mc_regs)); result = ci_populate_mc_reg_address(hwmgr, &(smu_data->mc_regs));
PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE(0 == result,
"Failed to initialize MCRegTable for the MC register addresses!", return result;); "Failed to initialize MCRegTable for the MC register addresses!", return result;);
...@@ -1885,7 +1883,7 @@ static int ci_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr) ...@@ -1885,7 +1883,7 @@ static int ci_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE(0 == result,
"Failed to initialize MCRegTable for driver state!", return result;); "Failed to initialize MCRegTable for driver state!", return result;);
return ci_copy_bytes_to_smc(smumgr, smu_data->mc_reg_table_start, return ci_copy_bytes_to_smc(hwmgr, smu_data->mc_reg_table_start,
(uint8_t *)&smu_data->mc_regs, sizeof(SMU7_Discrete_MCRegisters), SMC_RAM_END); (uint8_t *)&smu_data->mc_regs, sizeof(SMU7_Discrete_MCRegisters), SMC_RAM_END);
} }
...@@ -1930,17 +1928,17 @@ static int ci_populate_smc_svi2_config(struct pp_hwmgr *hwmgr, ...@@ -1930,17 +1928,17 @@ static int ci_populate_smc_svi2_config(struct pp_hwmgr *hwmgr,
return 0; return 0;
} }
static int ci_start_smc(struct pp_smumgr *smumgr) static int ci_start_smc(struct pp_hwmgr *hwmgr)
{ {
/* set smc instruct start point at 0x0 */ /* set smc instruct start point at 0x0 */
ci_program_jump_on_start(smumgr); ci_program_jump_on_start(hwmgr);
/* enable smc clock */ /* enable smc clock */
SMUM_WRITE_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); SMUM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
SMUM_WRITE_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 0); SMUM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 0);
SMUM_WAIT_INDIRECT_FIELD(smumgr, SMC_IND, FIRMWARE_FLAGS, SMUM_WAIT_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS,
INTERRUPTS_ENABLED, 1); INTERRUPTS_ENABLED, 1);
return 0; return 0;
...@@ -2105,7 +2103,7 @@ int ci_init_smc_table(struct pp_hwmgr *hwmgr) ...@@ -2105,7 +2103,7 @@ int ci_init_smc_table(struct pp_hwmgr *hwmgr)
table->BootMVdd = PP_HOST_TO_SMC_US(table->BootMVdd * VOLTAGE_SCALE); table->BootMVdd = PP_HOST_TO_SMC_US(table->BootMVdd * VOLTAGE_SCALE);
/* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */ /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
result = ci_copy_bytes_to_smc(hwmgr->smumgr, smu_data->dpm_table_start + result = ci_copy_bytes_to_smc(hwmgr, smu_data->dpm_table_start +
offsetof(SMU7_Discrete_DpmTable, SystemFlags), offsetof(SMU7_Discrete_DpmTable, SystemFlags),
(uint8_t *)&(table->SystemFlags), (uint8_t *)&(table->SystemFlags),
sizeof(SMU7_Discrete_DpmTable)-3 * sizeof(SMU7_PIDController), sizeof(SMU7_Discrete_DpmTable)-3 * sizeof(SMU7_PIDController),
...@@ -2122,7 +2120,7 @@ int ci_init_smc_table(struct pp_hwmgr *hwmgr) ...@@ -2122,7 +2120,7 @@ int ci_init_smc_table(struct pp_hwmgr *hwmgr)
PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE(0 == result,
"Failed to populate PM fuses to SMC memory!", return result); "Failed to populate PM fuses to SMC memory!", return result);
ci_start_smc(hwmgr->smumgr); ci_start_smc(hwmgr);
return 0; return 0;
} }
...@@ -2197,7 +2195,7 @@ int ci_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) ...@@ -2197,7 +2195,7 @@ int ci_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_MULT_THERMAL_CTRL, TEMP_SEL); fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_MULT_THERMAL_CTRL, TEMP_SEL);
res = ci_copy_bytes_to_smc(hwmgr->smumgr, ci_data->fan_table_start, (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table), SMC_RAM_END); res = ci_copy_bytes_to_smc(hwmgr, ci_data->fan_table_start, (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table), SMC_RAM_END);
return 0; return 0;
} }
...@@ -2233,7 +2231,7 @@ int ci_update_sclk_threshold(struct pp_hwmgr *hwmgr) ...@@ -2233,7 +2231,7 @@ int ci_update_sclk_threshold(struct pp_hwmgr *hwmgr)
CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold); CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
result = ci_copy_bytes_to_smc( result = ci_copy_bytes_to_smc(
hwmgr->smumgr, hwmgr,
smu_data->dpm_table_start + smu_data->dpm_table_start +
offsetof(SMU7_Discrete_DpmTable, offsetof(SMU7_Discrete_DpmTable,
LowSclkInterruptT), LowSclkInterruptT),
...@@ -2303,7 +2301,7 @@ uint32_t ci_get_mac_definition(uint32_t value) ...@@ -2303,7 +2301,7 @@ uint32_t ci_get_mac_definition(uint32_t value)
return 0; return 0;
} }
static int ci_load_smc_ucode(struct pp_smumgr *smumgr) static int ci_load_smc_ucode(struct pp_hwmgr *hwmgr)
{ {
uint32_t byte_count, start_addr; uint32_t byte_count, start_addr;
uint8_t *src; uint8_t *src;
...@@ -2311,9 +2309,9 @@ static int ci_load_smc_ucode(struct pp_smumgr *smumgr) ...@@ -2311,9 +2309,9 @@ static int ci_load_smc_ucode(struct pp_smumgr *smumgr)
struct cgs_firmware_info info = {0}; struct cgs_firmware_info info = {0};
cgs_get_firmware_info(smumgr->device, CGS_UCODE_ID_SMU, &info); cgs_get_firmware_info(hwmgr->device, CGS_UCODE_ID_SMU, &info);
smumgr->is_kicker = info.is_kicker; hwmgr->smumgr->is_kicker = info.is_kicker;
byte_count = info.image_size; byte_count = info.image_size;
src = (uint8_t *)info.kptr; src = (uint8_t *)info.kptr;
start_addr = info.ucode_start_address; start_addr = info.ucode_start_address;
...@@ -2323,15 +2321,15 @@ static int ci_load_smc_ucode(struct pp_smumgr *smumgr) ...@@ -2323,15 +2321,15 @@ static int ci_load_smc_ucode(struct pp_smumgr *smumgr)
return -EINVAL; return -EINVAL;
} }
cgs_write_register(smumgr->device, mmSMC_IND_INDEX_0, start_addr); cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_0, start_addr);
SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 1); SMUM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 1);
for (; byte_count >= 4; byte_count -= 4) { for (; byte_count >= 4; byte_count -= 4) {
data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3]; data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3];
cgs_write_register(smumgr->device, mmSMC_IND_DATA_0, data); cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data);
src += 4; src += 4;
} }
SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0); SMUM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0);
if (0 != byte_count) { if (0 != byte_count) {
pr_err("SMC size must be dividable by 4\n"); pr_err("SMC size must be dividable by 4\n");
...@@ -2343,18 +2341,18 @@ static int ci_load_smc_ucode(struct pp_smumgr *smumgr) ...@@ -2343,18 +2341,18 @@ static int ci_load_smc_ucode(struct pp_smumgr *smumgr)
static int ci_upload_firmware(struct pp_hwmgr *hwmgr) static int ci_upload_firmware(struct pp_hwmgr *hwmgr)
{ {
if (ci_is_smc_ram_running(hwmgr->smumgr)) { if (ci_is_smc_ram_running(hwmgr)) {
pr_info("smc is running, no need to load smc firmware\n"); pr_info("smc is running, no need to load smc firmware\n");
return 0; return 0;
} }
SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr->smumgr, SMC_IND, RCU_UC_EVENTS, SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS,
boot_seq_done, 1); boot_seq_done, 1);
PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_MISC_CNTL, PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_MISC_CNTL,
pre_fetcher_en, 1); pre_fetcher_en, 1);
PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 1); PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 1);
PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 1); PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 1);
return ci_load_smc_ucode(hwmgr->smumgr); return ci_load_smc_ucode(hwmgr);
} }
int ci_process_firmware_header(struct pp_hwmgr *hwmgr) int ci_process_firmware_header(struct pp_hwmgr *hwmgr)
...@@ -2369,7 +2367,7 @@ int ci_process_firmware_header(struct pp_hwmgr *hwmgr) ...@@ -2369,7 +2367,7 @@ int ci_process_firmware_header(struct pp_hwmgr *hwmgr)
if (ci_upload_firmware(hwmgr)) if (ci_upload_firmware(hwmgr))
return -EINVAL; return -EINVAL;
result = ci_read_smc_sram_dword(hwmgr->smumgr, result = ci_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION + SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU7_Firmware_Header, DpmTable), offsetof(SMU7_Firmware_Header, DpmTable),
&tmp, SMC_RAM_END); &tmp, SMC_RAM_END);
...@@ -2379,7 +2377,7 @@ int ci_process_firmware_header(struct pp_hwmgr *hwmgr) ...@@ -2379,7 +2377,7 @@ int ci_process_firmware_header(struct pp_hwmgr *hwmgr)
error |= (0 != result); error |= (0 != result);
result = ci_read_smc_sram_dword(hwmgr->smumgr, result = ci_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION + SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU7_Firmware_Header, SoftRegisters), offsetof(SMU7_Firmware_Header, SoftRegisters),
&tmp, SMC_RAM_END); &tmp, SMC_RAM_END);
...@@ -2391,7 +2389,7 @@ int ci_process_firmware_header(struct pp_hwmgr *hwmgr) ...@@ -2391,7 +2389,7 @@ int ci_process_firmware_header(struct pp_hwmgr *hwmgr)
error |= (0 != result); error |= (0 != result);
result = ci_read_smc_sram_dword(hwmgr->smumgr, result = ci_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION + SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU7_Firmware_Header, mcRegisterTable), offsetof(SMU7_Firmware_Header, mcRegisterTable),
&tmp, SMC_RAM_END); &tmp, SMC_RAM_END);
...@@ -2399,7 +2397,7 @@ int ci_process_firmware_header(struct pp_hwmgr *hwmgr) ...@@ -2399,7 +2397,7 @@ int ci_process_firmware_header(struct pp_hwmgr *hwmgr)
if (0 == result) if (0 == result)
ci_data->mc_reg_table_start = tmp; ci_data->mc_reg_table_start = tmp;
result = ci_read_smc_sram_dword(hwmgr->smumgr, result = ci_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION + SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU7_Firmware_Header, FanTable), offsetof(SMU7_Firmware_Header, FanTable),
&tmp, SMC_RAM_END); &tmp, SMC_RAM_END);
...@@ -2409,7 +2407,7 @@ int ci_process_firmware_header(struct pp_hwmgr *hwmgr) ...@@ -2409,7 +2407,7 @@ int ci_process_firmware_header(struct pp_hwmgr *hwmgr)
error |= (0 != result); error |= (0 != result);
result = ci_read_smc_sram_dword(hwmgr->smumgr, result = ci_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION + SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU7_Firmware_Header, mcArbDramTimingTable), offsetof(SMU7_Firmware_Header, mcArbDramTimingTable),
&tmp, SMC_RAM_END); &tmp, SMC_RAM_END);
...@@ -2419,7 +2417,7 @@ int ci_process_firmware_header(struct pp_hwmgr *hwmgr) ...@@ -2419,7 +2417,7 @@ int ci_process_firmware_header(struct pp_hwmgr *hwmgr)
error |= (0 != result); error |= (0 != result);
result = ci_read_smc_sram_dword(hwmgr->smumgr, result = ci_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION + SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU7_Firmware_Header, Version), offsetof(SMU7_Firmware_Header, Version),
&tmp, SMC_RAM_END); &tmp, SMC_RAM_END);
...@@ -2726,7 +2724,7 @@ int ci_initialize_mc_reg_table(struct pp_hwmgr *hwmgr) ...@@ -2726,7 +2724,7 @@ int ci_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
bool ci_is_dpm_running(struct pp_hwmgr *hwmgr) bool ci_is_dpm_running(struct pp_hwmgr *hwmgr)
{ {
return ci_is_smc_ram_running(hwmgr->smumgr); return ci_is_smc_ram_running(hwmgr);
} }
int ci_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr, int ci_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
...@@ -2750,6 +2748,6 @@ int ci_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr, ...@@ -2750,6 +2748,6 @@ int ci_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
levels[i].DownH = request->down_hyst; levels[i].DownH = request->down_hyst;
} }
return ci_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels, return ci_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
array_size, SMC_RAM_END); array_size, SMC_RAM_END);
} }
drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.h
浏览文件 @ d3f8c0ab
...@@ -30,9 +30,9 @@ struct pp_smumgr; ...@@ -30,9 +30,9 @@ struct pp_smumgr;
struct pp_hwmgr; struct pp_hwmgr;
struct amd_pp_profile; struct amd_pp_profile;
int ci_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, int ci_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
uint16_t msg, uint32_t parameter); uint16_t msg, uint32_t parameter);
int ci_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg); int ci_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg);
int ci_populate_all_graphic_levels(struct pp_hwmgr *hwmgr); int ci_populate_all_graphic_levels(struct pp_hwmgr *hwmgr);
int ci_populate_all_memory_levels(struct pp_hwmgr *hwmgr); int ci_populate_all_memory_levels(struct pp_hwmgr *hwmgr);
int ci_init_smc_table(struct pp_hwmgr *hwmgr); int ci_init_smc_table(struct pp_hwmgr *hwmgr);
......
drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
浏览文件 @ d3f8c0ab
...@@ -30,7 +30,7 @@ ...@@ -30,7 +30,7 @@
#include "cgs_common.h" #include "cgs_common.h"
#include "ci_smc.h" #include "ci_smc.h"
static int ci_smu_init(struct pp_smumgr *smumgr) static int ci_smu_init(struct pp_hwmgr *hwmgr)
{ {
int i; int i;
struct ci_smumgr *ci_priv = NULL; struct ci_smumgr *ci_priv = NULL;
...@@ -43,20 +43,20 @@ static int ci_smu_init(struct pp_smumgr *smumgr) ...@@ -43,20 +43,20 @@ static int ci_smu_init(struct pp_smumgr *smumgr)
for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++)
ci_priv->activity_target[i] = 30; ci_priv->activity_target[i] = 30;
smumgr->backend = ci_priv; hwmgr->smumgr->backend = ci_priv;
return 0; return 0;
} }
static int ci_smu_fini(struct pp_smumgr *smumgr) static int ci_smu_fini(struct pp_hwmgr *hwmgr)
{ {
kfree(smumgr->backend); kfree(hwmgr->smumgr->backend);
smumgr->backend = NULL; hwmgr->smumgr->backend = NULL;
cgs_rel_firmware(smumgr->device, CGS_UCODE_ID_SMU); cgs_rel_firmware(hwmgr->device, CGS_UCODE_ID_SMU);
return 0; return 0;
} }
static int ci_start_smu(struct pp_smumgr *smumgr) static int ci_start_smu(struct pp_hwmgr *hwmgr)
{ {
return 0; return 0;
} }
......
drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
浏览文件 @ d3f8c0ab
...@@ -52,53 +52,52 @@ static const enum cz_scratch_entry firmware_list[] = { ...@@ -52,53 +52,52 @@ static const enum cz_scratch_entry firmware_list[] = {
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G,
}; };
static int cz_smum_get_argument(struct pp_smumgr *smumgr) static int cz_smum_get_argument(struct pp_hwmgr *hwmgr)
{ {
if (smumgr == NULL || smumgr->device == NULL) if (hwmgr == NULL || hwmgr->device == NULL)
return -EINVAL; return -EINVAL;
return cgs_read_register(smumgr->device, return cgs_read_register(hwmgr->device,
mmSMU_MP1_SRBM2P_ARG_0); mmSMU_MP1_SRBM2P_ARG_0);
} }
static int cz_send_msg_to_smc_async(struct pp_smumgr *smumgr, static int cz_send_msg_to_smc_async(struct pp_hwmgr *hwmgr, uint16_t msg)
uint16_t msg)
{ {
int result = 0; int result = 0;
if (smumgr == NULL || smumgr->device == NULL) if (hwmgr == NULL || hwmgr->device == NULL)
return -EINVAL; return -EINVAL;
result = SMUM_WAIT_FIELD_UNEQUAL(smumgr, result = SMUM_WAIT_FIELD_UNEQUAL(hwmgr,
SMU_MP1_SRBM2P_RESP_0, CONTENT, 0); SMU_MP1_SRBM2P_RESP_0, CONTENT, 0);
if (result != 0) { if (result != 0) {
pr_err("cz_send_msg_to_smc_async (0x%04x) failed\n", msg); pr_err("cz_send_msg_to_smc_async (0x%04x) failed\n", msg);
return result; return result;
} }
cgs_write_register(smumgr->device, mmSMU_MP1_SRBM2P_RESP_0, 0); cgs_write_register(hwmgr->device, mmSMU_MP1_SRBM2P_RESP_0, 0);
cgs_write_register(smumgr->device, mmSMU_MP1_SRBM2P_MSG_0, msg); cgs_write_register(hwmgr->device, mmSMU_MP1_SRBM2P_MSG_0, msg);
return 0; return 0;
} }
/* Send a message to the SMC, and wait for its response.*/ /* Send a message to the SMC, and wait for its response.*/
static int cz_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg) static int cz_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
{ {
int result = 0; int result = 0;
result = cz_send_msg_to_smc_async(smumgr, msg); result = cz_send_msg_to_smc_async(hwmgr, msg);
if (result != 0) if (result != 0)
return result; return result;
return SMUM_WAIT_FIELD_UNEQUAL(smumgr, return SMUM_WAIT_FIELD_UNEQUAL(hwmgr,
SMU_MP1_SRBM2P_RESP_0, CONTENT, 0); SMU_MP1_SRBM2P_RESP_0, CONTENT, 0);
} }
static int cz_set_smc_sram_address(struct pp_smumgr *smumgr, static int cz_set_smc_sram_address(struct pp_hwmgr *hwmgr,
uint32_t smc_address, uint32_t limit) uint32_t smc_address, uint32_t limit)
{ {
if (smumgr == NULL || smumgr->device == NULL) if (hwmgr == NULL || hwmgr->device == NULL)
return -EINVAL; return -EINVAL;
if (0 != (3 & smc_address)) { if (0 != (3 & smc_address)) {
...@@ -111,39 +110,39 @@ static int cz_set_smc_sram_address(struct pp_smumgr *smumgr, ...@@ -111,39 +110,39 @@ static int cz_set_smc_sram_address(struct pp_smumgr *smumgr,
return -EINVAL; return -EINVAL;
} }
cgs_write_register(smumgr->device, mmMP0PUB_IND_INDEX_0, cgs_write_register(hwmgr->device, mmMP0PUB_IND_INDEX_0,
SMN_MP1_SRAM_START_ADDR + smc_address); SMN_MP1_SRAM_START_ADDR + smc_address);
return 0; return 0;
} }
static int cz_write_smc_sram_dword(struct pp_smumgr *smumgr, static int cz_write_smc_sram_dword(struct pp_hwmgr *hwmgr,
uint32_t smc_address, uint32_t value, uint32_t limit) uint32_t smc_address, uint32_t value, uint32_t limit)
{ {
int result; int result;
if (smumgr == NULL || smumgr->device == NULL) if (hwmgr == NULL || hwmgr->device == NULL)
return -EINVAL; return -EINVAL;
result = cz_set_smc_sram_address(smumgr, smc_address, limit); result = cz_set_smc_sram_address(hwmgr, smc_address, limit);
if (!result) if (!result)
cgs_write_register(smumgr->device, mmMP0PUB_IND_DATA_0, value); cgs_write_register(hwmgr->device, mmMP0PUB_IND_DATA_0, value);
return result; return result;
} }
static int cz_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, static int cz_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
uint16_t msg, uint32_t parameter) uint16_t msg, uint32_t parameter)
{ {
if (smumgr == NULL || smumgr->device == NULL) if (hwmgr == NULL || hwmgr->device == NULL)
return -EINVAL; return -EINVAL;
cgs_write_register(smumgr->device, mmSMU_MP1_SRBM2P_ARG_0, parameter); cgs_write_register(hwmgr->device, mmSMU_MP1_SRBM2P_ARG_0, parameter);
return cz_send_msg_to_smc(smumgr, msg); return cz_send_msg_to_smc(hwmgr, msg);
} }
static int cz_check_fw_load_finish(struct pp_smumgr *smumgr, static int cz_check_fw_load_finish(struct pp_hwmgr *hwmgr,
uint32_t firmware) uint32_t firmware)
{ {
int i; int i;
...@@ -151,19 +150,19 @@ static int cz_check_fw_load_finish(struct pp_smumgr *smumgr, ...@@ -151,19 +150,19 @@ static int cz_check_fw_load_finish(struct pp_smumgr *smumgr,
SMU8_FIRMWARE_HEADER_LOCATION + SMU8_FIRMWARE_HEADER_LOCATION +
offsetof(struct SMU8_Firmware_Header, UcodeLoadStatus); offsetof(struct SMU8_Firmware_Header, UcodeLoadStatus);
if (smumgr == NULL || smumgr->device == NULL) if (hwmgr == NULL || hwmgr->device == NULL)
return -EINVAL; return -EINVAL;
cgs_write_register(smumgr->device, mmMP0PUB_IND_INDEX, index); cgs_write_register(hwmgr->device, mmMP0PUB_IND_INDEX, index);
for (i = 0; i < smumgr->usec_timeout; i++) { for (i = 0; i < hwmgr->usec_timeout; i++) {
if (firmware == if (firmware ==
(cgs_read_register(smumgr->device, mmMP0PUB_IND_DATA) & firmware)) (cgs_read_register(hwmgr->device, mmMP0PUB_IND_DATA) & firmware))
break; break;
udelay(1); udelay(1);
} }
if (i >= smumgr->usec_timeout) { if (i >= hwmgr->usec_timeout) {
pr_err("SMU check loaded firmware failed.\n"); pr_err("SMU check loaded firmware failed.\n");
return -EINVAL; return -EINVAL;
} }
...@@ -171,7 +170,7 @@ static int cz_check_fw_load_finish(struct pp_smumgr *smumgr, ...@@ -171,7 +170,7 @@ static int cz_check_fw_load_finish(struct pp_smumgr *smumgr,
return 0; return 0;
} }
static int cz_load_mec_firmware(struct pp_smumgr *smumgr) static int cz_load_mec_firmware(struct pp_hwmgr *hwmgr)
{ {
uint32_t reg_data; uint32_t reg_data;
uint32_t tmp; uint32_t tmp;
...@@ -179,44 +178,44 @@ static int cz_load_mec_firmware(struct pp_smumgr *smumgr) ...@@ -179,44 +178,44 @@ static int cz_load_mec_firmware(struct pp_smumgr *smumgr)
struct cgs_firmware_info info = {0}; struct cgs_firmware_info info = {0};
struct cz_smumgr *cz_smu; struct cz_smumgr *cz_smu;
if (smumgr == NULL || smumgr->device == NULL) if (hwmgr == NULL || hwmgr->device == NULL)
return -EINVAL; return -EINVAL;
cz_smu = (struct cz_smumgr *)smumgr->backend; cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend;
ret = cgs_get_firmware_info(smumgr->device, ret = cgs_get_firmware_info(hwmgr->device,
CGS_UCODE_ID_CP_MEC, &info); CGS_UCODE_ID_CP_MEC, &info);
if (ret) if (ret)
return -EINVAL; return -EINVAL;
/* Disable MEC parsing/prefetching */ /* Disable MEC parsing/prefetching */
tmp = cgs_read_register(smumgr->device, tmp = cgs_read_register(hwmgr->device,
mmCP_MEC_CNTL); mmCP_MEC_CNTL);
tmp = SMUM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1); tmp = SMUM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1);
tmp = SMUM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1); tmp = SMUM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1);
cgs_write_register(smumgr->device, mmCP_MEC_CNTL, tmp); cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, tmp);
tmp = cgs_read_register(smumgr->device, tmp = cgs_read_register(hwmgr->device,
mmCP_CPC_IC_BASE_CNTL); mmCP_CPC_IC_BASE_CNTL);
tmp = SMUM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); tmp = SMUM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
tmp = SMUM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ATC, 0); tmp = SMUM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ATC, 0);
tmp = SMUM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); tmp = SMUM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
tmp = SMUM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, MTYPE, 1); tmp = SMUM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, MTYPE, 1);
cgs_write_register(smumgr->device, mmCP_CPC_IC_BASE_CNTL, tmp); cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_CNTL, tmp);
reg_data = smu_lower_32_bits(info.mc_addr) & reg_data = smu_lower_32_bits(info.mc_addr) &
SMUM_FIELD_MASK(CP_CPC_IC_BASE_LO, IC_BASE_LO); SMUM_FIELD_MASK(CP_CPC_IC_BASE_LO, IC_BASE_LO);
cgs_write_register(smumgr->device, mmCP_CPC_IC_BASE_LO, reg_data); cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_LO, reg_data);
reg_data = smu_upper_32_bits(info.mc_addr) & reg_data = smu_upper_32_bits(info.mc_addr) &
SMUM_FIELD_MASK(CP_CPC_IC_BASE_HI, IC_BASE_HI); SMUM_FIELD_MASK(CP_CPC_IC_BASE_HI, IC_BASE_HI);
cgs_write_register(smumgr->device, mmCP_CPC_IC_BASE_HI, reg_data); cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_HI, reg_data);
return 0; return 0;
} }
static uint8_t cz_translate_firmware_enum_to_arg(struct pp_smumgr *smumgr, static uint8_t cz_translate_firmware_enum_to_arg(struct pp_hwmgr *hwmgr,
enum cz_scratch_entry firmware_enum) enum cz_scratch_entry firmware_enum)
{ {
uint8_t ret = 0; uint8_t ret = 0;
...@@ -226,7 +225,7 @@ static uint8_t cz_translate_firmware_enum_to_arg(struct pp_smumgr *smumgr, ...@@ -226,7 +225,7 @@ static uint8_t cz_translate_firmware_enum_to_arg(struct pp_smumgr *smumgr,
ret = UCODE_ID_SDMA0; ret = UCODE_ID_SDMA0;
break; break;
case CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1: case CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1:
if (smumgr->chip_id == CHIP_STONEY) if (hwmgr->chip_id == CHIP_STONEY)
ret = UCODE_ID_SDMA0; ret = UCODE_ID_SDMA0;
else else
ret = UCODE_ID_SDMA1; ret = UCODE_ID_SDMA1;
...@@ -244,7 +243,7 @@ static uint8_t cz_translate_firmware_enum_to_arg(struct pp_smumgr *smumgr, ...@@ -244,7 +243,7 @@ static uint8_t cz_translate_firmware_enum_to_arg(struct pp_smumgr *smumgr,
ret = UCODE_ID_CP_MEC_JT1; ret = UCODE_ID_CP_MEC_JT1;
break; break;
case CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2: case CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2:
if (smumgr->chip_id == CHIP_STONEY) if (hwmgr->chip_id == CHIP_STONEY)
ret = UCODE_ID_CP_MEC_JT1; ret = UCODE_ID_CP_MEC_JT1;
else else
ret = UCODE_ID_CP_MEC_JT2; ret = UCODE_ID_CP_MEC_JT2;
...@@ -326,17 +325,17 @@ static enum cgs_ucode_id cz_convert_fw_type_to_cgs(uint32_t fw_type) ...@@ -326,17 +325,17 @@ static enum cgs_ucode_id cz_convert_fw_type_to_cgs(uint32_t fw_type)
} }
static int cz_smu_populate_single_scratch_task( static int cz_smu_populate_single_scratch_task(
struct pp_smumgr *smumgr, struct pp_hwmgr *hwmgr,
enum cz_scratch_entry fw_enum, enum cz_scratch_entry fw_enum,
uint8_t type, bool is_last) uint8_t type, bool is_last)
{ {
uint8_t i; uint8_t i;
struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend; struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend;
struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr; struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr;
struct SMU_Task *task = &toc->tasks[cz_smu->toc_entry_used_count++]; struct SMU_Task *task = &toc->tasks[cz_smu->toc_entry_used_count++];
task->type = type; task->type = type;
task->arg = cz_translate_firmware_enum_to_arg(smumgr, fw_enum); task->arg = cz_translate_firmware_enum_to_arg(hwmgr, fw_enum);
task->next = is_last ? END_OF_TASK_LIST : cz_smu->toc_entry_used_count; task->next = is_last ? END_OF_TASK_LIST : cz_smu->toc_entry_used_count;
for (i = 0; i < cz_smu->scratch_buffer_length; i++) for (i = 0; i < cz_smu->scratch_buffer_length; i++)
...@@ -363,17 +362,17 @@ static int cz_smu_populate_single_scratch_task( ...@@ -363,17 +362,17 @@ static int cz_smu_populate_single_scratch_task(
} }
static int cz_smu_populate_single_ucode_load_task( static int cz_smu_populate_single_ucode_load_task(
struct pp_smumgr *smumgr, struct pp_hwmgr *hwmgr,
enum cz_scratch_entry fw_enum, enum cz_scratch_entry fw_enum,
bool is_last) bool is_last)
{ {
uint8_t i; uint8_t i;
struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend; struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend;
struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr; struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr;
struct SMU_Task *task = &toc->tasks[cz_smu->toc_entry_used_count++]; struct SMU_Task *task = &toc->tasks[cz_smu->toc_entry_used_count++];
task->type = TASK_TYPE_UCODE_LOAD; task->type = TASK_TYPE_UCODE_LOAD;
task->arg = cz_translate_firmware_enum_to_arg(smumgr, fw_enum); task->arg = cz_translate_firmware_enum_to_arg(hwmgr, fw_enum);
task->next = is_last ? END_OF_TASK_LIST : cz_smu->toc_entry_used_count; task->next = is_last ? END_OF_TASK_LIST : cz_smu->toc_entry_used_count;
for (i = 0; i < cz_smu->driver_buffer_length; i++) for (i = 0; i < cz_smu->driver_buffer_length; i++)
...@@ -392,22 +391,22 @@ static int cz_smu_populate_single_ucode_load_task( ...@@ -392,22 +391,22 @@ static int cz_smu_populate_single_ucode_load_task(
return 0; return 0;
} }
static int cz_smu_construct_toc_for_rlc_aram_save(struct pp_smumgr *smumgr) static int cz_smu_construct_toc_for_rlc_aram_save(struct pp_hwmgr *hwmgr)
{ {
struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend; struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend;
cz_smu->toc_entry_aram = cz_smu->toc_entry_used_count; cz_smu->toc_entry_aram = cz_smu->toc_entry_used_count;
cz_smu_populate_single_scratch_task(smumgr, cz_smu_populate_single_scratch_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM, CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM,
TASK_TYPE_UCODE_SAVE, true); TASK_TYPE_UCODE_SAVE, true);
return 0; return 0;
} }
static int cz_smu_initialize_toc_empty_job_list(struct pp_smumgr *smumgr) static int cz_smu_initialize_toc_empty_job_list(struct pp_hwmgr *hwmgr)
{ {
int i; int i;
struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend; struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend;
struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr; struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr;
for (i = 0; i < NUM_JOBLIST_ENTRIES; i++) for (i = 0; i < NUM_JOBLIST_ENTRIES; i++)
...@@ -416,17 +415,17 @@ static int cz_smu_initialize_toc_empty_job_list(struct pp_smumgr *smumgr) ...@@ -416,17 +415,17 @@ static int cz_smu_initialize_toc_empty_job_list(struct pp_smumgr *smumgr)
return 0; return 0;
} }
static int cz_smu_construct_toc_for_vddgfx_enter(struct pp_smumgr *smumgr) static int cz_smu_construct_toc_for_vddgfx_enter(struct pp_hwmgr *hwmgr)
{ {
struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend; struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend;
struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr; struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr;
toc->JobList[JOB_GFX_SAVE] = (uint8_t)cz_smu->toc_entry_used_count; toc->JobList[JOB_GFX_SAVE] = (uint8_t)cz_smu->toc_entry_used_count;
cz_smu_populate_single_scratch_task(smumgr, cz_smu_populate_single_scratch_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH, CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH,
TASK_TYPE_UCODE_SAVE, false); TASK_TYPE_UCODE_SAVE, false);
cz_smu_populate_single_scratch_task(smumgr, cz_smu_populate_single_scratch_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM, CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM,
TASK_TYPE_UCODE_SAVE, true); TASK_TYPE_UCODE_SAVE, true);
...@@ -434,121 +433,120 @@ static int cz_smu_construct_toc_for_vddgfx_enter(struct pp_smumgr *smumgr) ...@@ -434,121 +433,120 @@ static int cz_smu_construct_toc_for_vddgfx_enter(struct pp_smumgr *smumgr)
} }
static int cz_smu_construct_toc_for_vddgfx_exit(struct pp_smumgr *smumgr) static int cz_smu_construct_toc_for_vddgfx_exit(struct pp_hwmgr *hwmgr)
{ {
struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend; struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend;
struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr; struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr;
toc->JobList[JOB_GFX_RESTORE] = (uint8_t)cz_smu->toc_entry_used_count; toc->JobList[JOB_GFX_RESTORE] = (uint8_t)cz_smu->toc_entry_used_count;
cz_smu_populate_single_ucode_load_task(smumgr, cz_smu_populate_single_ucode_load_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE, false); CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE, false);
cz_smu_populate_single_ucode_load_task(smumgr, cz_smu_populate_single_ucode_load_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_CP_PFP, false); CZ_SCRATCH_ENTRY_UCODE_ID_CP_PFP, false);
cz_smu_populate_single_ucode_load_task(smumgr, cz_smu_populate_single_ucode_load_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME, false); CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME, false);
cz_smu_populate_single_ucode_load_task(smumgr, cz_smu_populate_single_ucode_load_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false); CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
if (smumgr->chip_id == CHIP_STONEY) if (hwmgr->chip_id == CHIP_STONEY)
cz_smu_populate_single_ucode_load_task(smumgr, cz_smu_populate_single_ucode_load_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false); CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
else else
cz_smu_populate_single_ucode_load_task(smumgr, cz_smu_populate_single_ucode_load_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, false); CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, false);
cz_smu_populate_single_ucode_load_task(smumgr, cz_smu_populate_single_ucode_load_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, false); CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, false);
/* populate scratch */ /* populate scratch */
cz_smu_populate_single_scratch_task(smumgr, cz_smu_populate_single_scratch_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH, CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH,
TASK_TYPE_UCODE_LOAD, false); TASK_TYPE_UCODE_LOAD, false);
cz_smu_populate_single_scratch_task(smumgr, cz_smu_populate_single_scratch_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM, CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM,
TASK_TYPE_UCODE_LOAD, false); TASK_TYPE_UCODE_LOAD, false);
cz_smu_populate_single_scratch_task(smumgr, cz_smu_populate_single_scratch_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM, CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM,
TASK_TYPE_UCODE_LOAD, true); TASK_TYPE_UCODE_LOAD, true);
return 0; return 0;
} }
static int cz_smu_construct_toc_for_power_profiling( static int cz_smu_construct_toc_for_power_profiling(struct pp_hwmgr *hwmgr)
struct pp_smumgr *smumgr)
{ {
struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend; struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend;
cz_smu->toc_entry_power_profiling_index = cz_smu->toc_entry_used_count; cz_smu->toc_entry_power_profiling_index = cz_smu->toc_entry_used_count;
cz_smu_populate_single_scratch_task(smumgr, cz_smu_populate_single_scratch_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_POWER_PROFILING, CZ_SCRATCH_ENTRY_UCODE_ID_POWER_PROFILING,
TASK_TYPE_INITIALIZE, true); TASK_TYPE_INITIALIZE, true);
return 0; return 0;
} }
static int cz_smu_construct_toc_for_bootup(struct pp_smumgr *smumgr) static int cz_smu_construct_toc_for_bootup(struct pp_hwmgr *hwmgr)
{ {
struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend; struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend;
cz_smu->toc_entry_initialize_index = cz_smu->toc_entry_used_count; cz_smu->toc_entry_initialize_index = cz_smu->toc_entry_used_count;
cz_smu_populate_single_ucode_load_task(smumgr, cz_smu_populate_single_ucode_load_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0, false); CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0, false);
if (smumgr->chip_id != CHIP_STONEY) if (hwmgr->chip_id != CHIP_STONEY)
cz_smu_populate_single_ucode_load_task(smumgr, cz_smu_populate_single_ucode_load_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1, false); CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1, false);
cz_smu_populate_single_ucode_load_task(smumgr, cz_smu_populate_single_ucode_load_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE, false); CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE, false);
cz_smu_populate_single_ucode_load_task(smumgr, cz_smu_populate_single_ucode_load_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_CP_PFP, false); CZ_SCRATCH_ENTRY_UCODE_ID_CP_PFP, false);
cz_smu_populate_single_ucode_load_task(smumgr, cz_smu_populate_single_ucode_load_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME, false); CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME, false);
cz_smu_populate_single_ucode_load_task(smumgr, cz_smu_populate_single_ucode_load_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false); CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
if (smumgr->chip_id != CHIP_STONEY) if (hwmgr->chip_id != CHIP_STONEY)
cz_smu_populate_single_ucode_load_task(smumgr, cz_smu_populate_single_ucode_load_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, false); CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, false);
cz_smu_populate_single_ucode_load_task(smumgr, cz_smu_populate_single_ucode_load_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, true); CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, true);
return 0; return 0;
} }
static int cz_smu_construct_toc_for_clock_table(struct pp_smumgr *smumgr) static int cz_smu_construct_toc_for_clock_table(struct pp_hwmgr *hwmgr)
{ {
struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend; struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend;
cz_smu->toc_entry_clock_table = cz_smu->toc_entry_used_count; cz_smu->toc_entry_clock_table = cz_smu->toc_entry_used_count;
cz_smu_populate_single_scratch_task(smumgr, cz_smu_populate_single_scratch_task(hwmgr,
CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE, CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE,
TASK_TYPE_INITIALIZE, true); TASK_TYPE_INITIALIZE, true);
return 0; return 0;
} }
static int cz_smu_construct_toc(struct pp_smumgr *smumgr) static int cz_smu_construct_toc(struct pp_hwmgr *hwmgr)
{ {
struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend; struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend;
cz_smu->toc_entry_used_count = 0; cz_smu->toc_entry_used_count = 0;
cz_smu_initialize_toc_empty_job_list(smumgr); cz_smu_initialize_toc_empty_job_list(hwmgr);
cz_smu_construct_toc_for_rlc_aram_save(smumgr); cz_smu_construct_toc_for_rlc_aram_save(hwmgr);
cz_smu_construct_toc_for_vddgfx_enter(smumgr); cz_smu_construct_toc_for_vddgfx_enter(hwmgr);
cz_smu_construct_toc_for_vddgfx_exit(smumgr); cz_smu_construct_toc_for_vddgfx_exit(hwmgr);
cz_smu_construct_toc_for_power_profiling(smumgr); cz_smu_construct_toc_for_power_profiling(hwmgr);
cz_smu_construct_toc_for_bootup(smumgr); cz_smu_construct_toc_for_bootup(hwmgr);
cz_smu_construct_toc_for_clock_table(smumgr); cz_smu_construct_toc_for_clock_table(hwmgr);
return 0; return 0;
} }
static int cz_smu_populate_firmware_entries(struct pp_smumgr *smumgr) static int cz_smu_populate_firmware_entries(struct pp_hwmgr *hwmgr)
{ {
struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend; struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend;
uint32_t firmware_type; uint32_t firmware_type;
uint32_t i; uint32_t i;
int ret; int ret;
...@@ -559,12 +557,12 @@ static int cz_smu_populate_firmware_entries(struct pp_smumgr *smumgr) ...@@ -559,12 +557,12 @@ static int cz_smu_populate_firmware_entries(struct pp_smumgr *smumgr)
for (i = 0; i < ARRAY_SIZE(firmware_list); i++) { for (i = 0; i < ARRAY_SIZE(firmware_list); i++) {
firmware_type = cz_translate_firmware_enum_to_arg(smumgr, firmware_type = cz_translate_firmware_enum_to_arg(hwmgr,
firmware_list[i]); firmware_list[i]);
ucode_id = cz_convert_fw_type_to_cgs(firmware_type); ucode_id = cz_convert_fw_type_to_cgs(firmware_type);
ret = cgs_get_firmware_info(smumgr->device, ret = cgs_get_firmware_info(hwmgr->device,
ucode_id, &info); ucode_id, &info);
if (ret == 0) { if (ret == 0) {
...@@ -585,12 +583,12 @@ static int cz_smu_populate_firmware_entries(struct pp_smumgr *smumgr) ...@@ -585,12 +583,12 @@ static int cz_smu_populate_firmware_entries(struct pp_smumgr *smumgr)
} }
static int cz_smu_populate_single_scratch_entry( static int cz_smu_populate_single_scratch_entry(
struct pp_smumgr *smumgr, struct pp_hwmgr *hwmgr,
enum cz_scratch_entry scratch_type, enum cz_scratch_entry scratch_type,
uint32_t ulsize_byte, uint32_t ulsize_byte,
struct cz_buffer_entry *entry) struct cz_buffer_entry *entry)
{ {
struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend; struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend;
long long mc_addr = long long mc_addr =
((long long)(cz_smu->smu_buffer.mc_addr_high) << 32) ((long long)(cz_smu->smu_buffer.mc_addr_high) << 32)
| cz_smu->smu_buffer.mc_addr_low; | cz_smu->smu_buffer.mc_addr_low;
...@@ -611,9 +609,9 @@ static int cz_smu_populate_single_scratch_entry( ...@@ -611,9 +609,9 @@ static int cz_smu_populate_single_scratch_entry(
return 0; return 0;
} }
static int cz_download_pptable_settings(struct pp_smumgr *smumgr, void **table) static int cz_download_pptable_settings(struct pp_hwmgr *hwmgr, void **table)
{ {
struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend; struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend;
unsigned long i; unsigned long i;
for (i = 0; i < cz_smu->scratch_buffer_length; i++) { for (i = 0; i < cz_smu->scratch_buffer_length; i++) {
...@@ -624,25 +622,25 @@ static int cz_download_pptable_settings(struct pp_smumgr *smumgr, void **table) ...@@ -624,25 +622,25 @@ static int cz_download_pptable_settings(struct pp_smumgr *smumgr, void **table)
*table = (struct SMU8_Fusion_ClkTable *)cz_smu->scratch_buffer[i].kaddr; *table = (struct SMU8_Fusion_ClkTable *)cz_smu->scratch_buffer[i].kaddr;
cz_send_msg_to_smc_with_parameter(smumgr, cz_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetClkTableAddrHi, PPSMC_MSG_SetClkTableAddrHi,
cz_smu->scratch_buffer[i].mc_addr_high); cz_smu->scratch_buffer[i].mc_addr_high);
cz_send_msg_to_smc_with_parameter(smumgr, cz_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetClkTableAddrLo, PPSMC_MSG_SetClkTableAddrLo,
cz_smu->scratch_buffer[i].mc_addr_low); cz_smu->scratch_buffer[i].mc_addr_low);
cz_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_ExecuteJob, cz_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ExecuteJob,
cz_smu->toc_entry_clock_table); cz_smu->toc_entry_clock_table);
cz_send_msg_to_smc(smumgr, PPSMC_MSG_ClkTableXferToDram); cz_send_msg_to_smc(hwmgr, PPSMC_MSG_ClkTableXferToDram);
return 0; return 0;
} }
static int cz_upload_pptable_settings(struct pp_smumgr *smumgr) static int cz_upload_pptable_settings(struct pp_hwmgr *hwmgr)
{ {
struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend; struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend;
unsigned long i; unsigned long i;
for (i = 0; i < cz_smu->scratch_buffer_length; i++) { for (i = 0; i < cz_smu->scratch_buffer_length; i++) {
...@@ -651,63 +649,63 @@ static int cz_upload_pptable_settings(struct pp_smumgr *smumgr) ...@@ -651,63 +649,63 @@ static int cz_upload_pptable_settings(struct pp_smumgr *smumgr)
break; break;
} }
cz_send_msg_to_smc_with_parameter(smumgr, cz_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetClkTableAddrHi, PPSMC_MSG_SetClkTableAddrHi,
cz_smu->scratch_buffer[i].mc_addr_high); cz_smu->scratch_buffer[i].mc_addr_high);
cz_send_msg_to_smc_with_parameter(smumgr, cz_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetClkTableAddrLo, PPSMC_MSG_SetClkTableAddrLo,
cz_smu->scratch_buffer[i].mc_addr_low); cz_smu->scratch_buffer[i].mc_addr_low);
cz_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_ExecuteJob, cz_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ExecuteJob,
cz_smu->toc_entry_clock_table); cz_smu->toc_entry_clock_table);
cz_send_msg_to_smc(smumgr, PPSMC_MSG_ClkTableXferToSmu); cz_send_msg_to_smc(hwmgr, PPSMC_MSG_ClkTableXferToSmu);
return 0; return 0;
} }
static int cz_request_smu_load_fw(struct pp_smumgr *smumgr) static int cz_request_smu_load_fw(struct pp_hwmgr *hwmgr)
{ {
struct cz_smumgr *cz_smu = (struct cz_smumgr *)(smumgr->backend); struct cz_smumgr *cz_smu = (struct cz_smumgr *)(hwmgr->smumgr->backend);
uint32_t smc_address; uint32_t smc_address;
if (!smumgr->reload_fw) { if (!hwmgr->smumgr->reload_fw) {
pr_info("skip reloading...\n"); pr_info("skip reloading...\n");
return 0; return 0;
} }
cz_smu_populate_firmware_entries(smumgr); cz_smu_populate_firmware_entries(hwmgr);
cz_smu_construct_toc(smumgr); cz_smu_construct_toc(hwmgr);
smc_address = SMU8_FIRMWARE_HEADER_LOCATION + smc_address = SMU8_FIRMWARE_HEADER_LOCATION +
offsetof(struct SMU8_Firmware_Header, UcodeLoadStatus); offsetof(struct SMU8_Firmware_Header, UcodeLoadStatus);
cz_write_smc_sram_dword(smumgr, smc_address, 0, smc_address+4); cz_write_smc_sram_dword(hwmgr, smc_address, 0, smc_address+4);
cz_send_msg_to_smc_with_parameter(smumgr, cz_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_DriverDramAddrHi, PPSMC_MSG_DriverDramAddrHi,
cz_smu->toc_buffer.mc_addr_high); cz_smu->toc_buffer.mc_addr_high);
cz_send_msg_to_smc_with_parameter(smumgr, cz_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_DriverDramAddrLo, PPSMC_MSG_DriverDramAddrLo,
cz_smu->toc_buffer.mc_addr_low); cz_smu->toc_buffer.mc_addr_low);
cz_send_msg_to_smc(smumgr, PPSMC_MSG_InitJobs); cz_send_msg_to_smc(hwmgr, PPSMC_MSG_InitJobs);
cz_send_msg_to_smc_with_parameter(smumgr, cz_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_ExecuteJob, PPSMC_MSG_ExecuteJob,
cz_smu->toc_entry_aram); cz_smu->toc_entry_aram);
cz_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_ExecuteJob, cz_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ExecuteJob,
cz_smu->toc_entry_power_profiling_index); cz_smu->toc_entry_power_profiling_index);
return cz_send_msg_to_smc_with_parameter(smumgr, return cz_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_ExecuteJob, PPSMC_MSG_ExecuteJob,
cz_smu->toc_entry_initialize_index); cz_smu->toc_entry_initialize_index);
} }
static int cz_start_smu(struct pp_smumgr *smumgr) static int cz_start_smu(struct pp_hwmgr *hwmgr)
{ {
int ret = 0; int ret = 0;
uint32_t fw_to_check = 0; uint32_t fw_to_check = 0;
...@@ -721,23 +719,23 @@ static int cz_start_smu(struct pp_smumgr *smumgr) ...@@ -721,23 +719,23 @@ static int cz_start_smu(struct pp_smumgr *smumgr)
UCODE_ID_CP_MEC_JT1_MASK | UCODE_ID_CP_MEC_JT1_MASK |
UCODE_ID_CP_MEC_JT2_MASK; UCODE_ID_CP_MEC_JT2_MASK;
if (smumgr->chip_id == CHIP_STONEY) if (hwmgr->chip_id == CHIP_STONEY)
fw_to_check &= ~(UCODE_ID_SDMA1_MASK | UCODE_ID_CP_MEC_JT2_MASK); fw_to_check &= ~(UCODE_ID_SDMA1_MASK | UCODE_ID_CP_MEC_JT2_MASK);
ret = cz_request_smu_load_fw(smumgr); ret = cz_request_smu_load_fw(hwmgr);
if (ret) if (ret)
pr_err("SMU firmware load failed\n"); pr_err("SMU firmware load failed\n");
cz_check_fw_load_finish(smumgr, fw_to_check); cz_check_fw_load_finish(hwmgr, fw_to_check);
ret = cz_load_mec_firmware(smumgr); ret = cz_load_mec_firmware(hwmgr);
if (ret) if (ret)
pr_err("Mec Firmware load failed\n"); pr_err("Mec Firmware load failed\n");
return ret; return ret;
} }
static int cz_smu_init(struct pp_smumgr *smumgr) static int cz_smu_init(struct pp_hwmgr *hwmgr)
{ {
uint64_t mc_addr = 0; uint64_t mc_addr = 0;
int ret = 0; int ret = 0;
...@@ -747,7 +745,7 @@ static int cz_smu_init(struct pp_smumgr *smumgr) ...@@ -747,7 +745,7 @@ static int cz_smu_init(struct pp_smumgr *smumgr)
if (cz_smu == NULL) if (cz_smu == NULL)
return -ENOMEM; return -ENOMEM;
smumgr->backend = cz_smu; hwmgr->smumgr->backend = cz_smu;
cz_smu->toc_buffer.data_size = 4096; cz_smu->toc_buffer.data_size = 4096;
cz_smu->smu_buffer.data_size = cz_smu->smu_buffer.data_size =
...@@ -757,7 +755,7 @@ static int cz_smu_init(struct pp_smumgr *smumgr) ...@@ -757,7 +755,7 @@ static int cz_smu_init(struct pp_smumgr *smumgr)
ALIGN(sizeof(struct SMU8_MultimediaPowerLogData), 32) + ALIGN(sizeof(struct SMU8_MultimediaPowerLogData), 32) +
ALIGN(sizeof(struct SMU8_Fusion_ClkTable), 32); ALIGN(sizeof(struct SMU8_Fusion_ClkTable), 32);
ret = smu_allocate_memory(smumgr->device, ret = smu_allocate_memory(hwmgr->device,
cz_smu->toc_buffer.data_size, cz_smu->toc_buffer.data_size,
CGS_GPU_MEM_TYPE__GART_CACHEABLE, CGS_GPU_MEM_TYPE__GART_CACHEABLE,
PAGE_SIZE, PAGE_SIZE,
...@@ -770,7 +768,7 @@ static int cz_smu_init(struct pp_smumgr *smumgr) ...@@ -770,7 +768,7 @@ static int cz_smu_init(struct pp_smumgr *smumgr)
cz_smu->toc_buffer.mc_addr_high = smu_upper_32_bits(mc_addr); cz_smu->toc_buffer.mc_addr_high = smu_upper_32_bits(mc_addr);
cz_smu->toc_buffer.mc_addr_low = smu_lower_32_bits(mc_addr); cz_smu->toc_buffer.mc_addr_low = smu_lower_32_bits(mc_addr);
ret = smu_allocate_memory(smumgr->device, ret = smu_allocate_memory(hwmgr->device,
cz_smu->smu_buffer.data_size, cz_smu->smu_buffer.data_size,
CGS_GPU_MEM_TYPE__GART_CACHEABLE, CGS_GPU_MEM_TYPE__GART_CACHEABLE,
PAGE_SIZE, PAGE_SIZE,
...@@ -783,7 +781,7 @@ static int cz_smu_init(struct pp_smumgr *smumgr) ...@@ -783,7 +781,7 @@ static int cz_smu_init(struct pp_smumgr *smumgr)
cz_smu->smu_buffer.mc_addr_high = smu_upper_32_bits(mc_addr); cz_smu->smu_buffer.mc_addr_high = smu_upper_32_bits(mc_addr);
cz_smu->smu_buffer.mc_addr_low = smu_lower_32_bits(mc_addr); cz_smu->smu_buffer.mc_addr_low = smu_lower_32_bits(mc_addr);
if (0 != cz_smu_populate_single_scratch_entry(smumgr, if (0 != cz_smu_populate_single_scratch_entry(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH, CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH,
UCODE_ID_RLC_SCRATCH_SIZE_BYTE, UCODE_ID_RLC_SCRATCH_SIZE_BYTE,
&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) { &cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
...@@ -791,14 +789,14 @@ static int cz_smu_init(struct pp_smumgr *smumgr) ...@@ -791,14 +789,14 @@ static int cz_smu_init(struct pp_smumgr *smumgr)
return -1; return -1;
} }
if (0 != cz_smu_populate_single_scratch_entry(smumgr, if (0 != cz_smu_populate_single_scratch_entry(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM, CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM,
UCODE_ID_RLC_SRM_ARAM_SIZE_BYTE, UCODE_ID_RLC_SRM_ARAM_SIZE_BYTE,
&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) { &cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
pr_err("Error when Populate Firmware Entry.\n"); pr_err("Error when Populate Firmware Entry.\n");
return -1; return -1;
} }
if (0 != cz_smu_populate_single_scratch_entry(smumgr, if (0 != cz_smu_populate_single_scratch_entry(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM, CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM,
UCODE_ID_RLC_SRM_DRAM_SIZE_BYTE, UCODE_ID_RLC_SRM_DRAM_SIZE_BYTE,
&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) { &cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
...@@ -806,7 +804,7 @@ static int cz_smu_init(struct pp_smumgr *smumgr) ...@@ -806,7 +804,7 @@ static int cz_smu_init(struct pp_smumgr *smumgr)
return -1; return -1;
} }
if (0 != cz_smu_populate_single_scratch_entry(smumgr, if (0 != cz_smu_populate_single_scratch_entry(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_POWER_PROFILING, CZ_SCRATCH_ENTRY_UCODE_ID_POWER_PROFILING,
sizeof(struct SMU8_MultimediaPowerLogData), sizeof(struct SMU8_MultimediaPowerLogData),
&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) { &cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
...@@ -814,7 +812,7 @@ static int cz_smu_init(struct pp_smumgr *smumgr) ...@@ -814,7 +812,7 @@ static int cz_smu_init(struct pp_smumgr *smumgr)
return -1; return -1;
} }
if (0 != cz_smu_populate_single_scratch_entry(smumgr, if (0 != cz_smu_populate_single_scratch_entry(hwmgr,
CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE, CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE,
sizeof(struct SMU8_Fusion_ClkTable), sizeof(struct SMU8_Fusion_ClkTable),
&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) { &cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
...@@ -825,18 +823,18 @@ static int cz_smu_init(struct pp_smumgr *smumgr) ...@@ -825,18 +823,18 @@ static int cz_smu_init(struct pp_smumgr *smumgr)
return 0; return 0;
} }
static int cz_smu_fini(struct pp_smumgr *smumgr) static int cz_smu_fini(struct pp_hwmgr *hwmgr)
{ {
struct cz_smumgr *cz_smu; struct cz_smumgr *cz_smu;
if (smumgr == NULL || smumgr->device == NULL) if (hwmgr == NULL || hwmgr->device == NULL)
return -EINVAL; return -EINVAL;
cz_smu = (struct cz_smumgr *)smumgr->backend; cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend;
if (cz_smu) { if (cz_smu) {
cgs_free_gpu_mem(smumgr->device, cgs_free_gpu_mem(hwmgr->device,
cz_smu->toc_buffer.handle); cz_smu->toc_buffer.handle);
cgs_free_gpu_mem(smumgr->device, cgs_free_gpu_mem(hwmgr->device,
cz_smu->smu_buffer.handle); cz_smu->smu_buffer.handle);
kfree(cz_smu); kfree(cz_smu);
} }
......
drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
浏览文件 @ d3f8c0ab
...@@ -338,7 +338,7 @@ static int fiji_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset) ...@@ -338,7 +338,7 @@ static int fiji_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
const struct fiji_pt_defaults *defaults = smu_data->power_tune_defaults; const struct fiji_pt_defaults *defaults = smu_data->power_tune_defaults;
uint32_t temp; uint32_t temp;
if (smu7_read_smc_sram_dword(hwmgr->smumgr, if (smu7_read_smc_sram_dword(hwmgr,
fuse_table_offset + fuse_table_offset +
offsetof(SMU73_Discrete_PmFuses, TdcWaterfallCtl), offsetof(SMU73_Discrete_PmFuses, TdcWaterfallCtl),
(uint32_t *)&temp, SMC_RAM_END)) (uint32_t *)&temp, SMC_RAM_END))
...@@ -425,7 +425,7 @@ static int fiji_populate_pm_fuses(struct pp_hwmgr *hwmgr) ...@@ -425,7 +425,7 @@ static int fiji_populate_pm_fuses(struct pp_hwmgr *hwmgr)
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_PowerContainment)) { PHM_PlatformCaps_PowerContainment)) {
if (smu7_read_smc_sram_dword(hwmgr->smumgr, if (smu7_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION + SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU73_Firmware_Header, PmFuseTable), offsetof(SMU73_Firmware_Header, PmFuseTable),
&pm_fuse_table_offset, SMC_RAM_END)) &pm_fuse_table_offset, SMC_RAM_END))
...@@ -473,7 +473,7 @@ static int fiji_populate_pm_fuses(struct pp_hwmgr *hwmgr) ...@@ -473,7 +473,7 @@ static int fiji_populate_pm_fuses(struct pp_hwmgr *hwmgr)
"Attempt to populate BapmVddCBaseLeakage Hi and Lo " "Attempt to populate BapmVddCBaseLeakage Hi and Lo "
"Sidd Failed!", return -EINVAL); "Sidd Failed!", return -EINVAL);
if (smu7_copy_bytes_to_smc(hwmgr->smumgr, pm_fuse_table_offset, if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
(uint8_t *)&smu_data->power_tune_table, (uint8_t *)&smu_data->power_tune_table,
sizeof(struct SMU73_Discrete_PmFuses), SMC_RAM_END)) sizeof(struct SMU73_Discrete_PmFuses), SMC_RAM_END))
PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE(false,
...@@ -848,7 +848,7 @@ int fiji_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) ...@@ -848,7 +848,7 @@ int fiji_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
levels[1].pcieDpmLevel = mid_pcie_level_enabled; levels[1].pcieDpmLevel = mid_pcie_level_enabled;
} }
/* level count will send to smc once at init smc table and never change */ /* level count will send to smc once at init smc table and never change */
result = smu7_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels, result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
(uint32_t)array_size, SMC_RAM_END); (uint32_t)array_size, SMC_RAM_END);
return result; return result;
...@@ -1032,7 +1032,7 @@ int fiji_populate_all_memory_levels(struct pp_hwmgr *hwmgr) ...@@ -1032,7 +1032,7 @@ int fiji_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
PPSMC_DISPLAY_WATERMARK_HIGH; PPSMC_DISPLAY_WATERMARK_HIGH;
/* level count will send to smc once at init smc table and never change */ /* level count will send to smc once at init smc table and never change */
result = smu7_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels, result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
(uint32_t)array_size, SMC_RAM_END); (uint32_t)array_size, SMC_RAM_END);
return result; return result;
...@@ -1359,7 +1359,7 @@ static int fiji_program_memory_timing_parameters(struct pp_hwmgr *hwmgr) ...@@ -1359,7 +1359,7 @@ static int fiji_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
if (!result) if (!result)
result = smu7_copy_bytes_to_smc( result = smu7_copy_bytes_to_smc(
hwmgr->smumgr, hwmgr,
smu_data->smu7_data.arb_table_start, smu_data->smu7_data.arb_table_start,
(uint8_t *)&arb_regs, (uint8_t *)&arb_regs,
sizeof(SMU73_Discrete_MCArbDramTimingTable), sizeof(SMU73_Discrete_MCArbDramTimingTable),
...@@ -1683,9 +1683,9 @@ static int fiji_populate_vr_config(struct pp_hwmgr *hwmgr, ...@@ -1683,9 +1683,9 @@ static int fiji_populate_vr_config(struct pp_hwmgr *hwmgr,
return 0; return 0;
} }
static int fiji_init_arb_table_index(struct pp_smumgr *smumgr) static int fiji_init_arb_table_index(struct pp_hwmgr *hwmgr)
{ {
struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(smumgr->backend); struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend);
uint32_t tmp; uint32_t tmp;
int result; int result;
...@@ -1697,7 +1697,7 @@ static int fiji_init_arb_table_index(struct pp_smumgr *smumgr) ...@@ -1697,7 +1697,7 @@ static int fiji_init_arb_table_index(struct pp_smumgr *smumgr)
* In reality this field should not be in that structure * In reality this field should not be in that structure
* but in a soft register. * but in a soft register.
*/ */
result = smu7_read_smc_sram_dword(smumgr, result = smu7_read_smc_sram_dword(hwmgr,
smu_data->smu7_data.arb_table_start, &tmp, SMC_RAM_END); smu_data->smu7_data.arb_table_start, &tmp, SMC_RAM_END);
if (result) if (result)
...@@ -1706,7 +1706,7 @@ static int fiji_init_arb_table_index(struct pp_smumgr *smumgr) ...@@ -1706,7 +1706,7 @@ static int fiji_init_arb_table_index(struct pp_smumgr *smumgr)
tmp &= 0x00FFFFFF; tmp &= 0x00FFFFFF;
tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24; tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
return smu7_write_smc_sram_dword(smumgr, return smu7_write_smc_sram_dword(hwmgr,
smu_data->smu7_data.arb_table_start, tmp, SMC_RAM_END); smu_data->smu7_data.arb_table_start, tmp, SMC_RAM_END);
} }
...@@ -1771,7 +1771,7 @@ static int fiji_setup_dpm_led_config(struct pp_hwmgr *hwmgr) ...@@ -1771,7 +1771,7 @@ static int fiji_setup_dpm_led_config(struct pp_hwmgr *hwmgr)
} }
} }
if (mask) if (mask)
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_LedConfig, PPSMC_MSG_LedConfig,
mask); mask);
return 0; return 0;
...@@ -1974,7 +1974,7 @@ int fiji_init_smc_table(struct pp_hwmgr *hwmgr) ...@@ -1974,7 +1974,7 @@ int fiji_init_smc_table(struct pp_hwmgr *hwmgr)
CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime); CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
/* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */ /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
result = smu7_copy_bytes_to_smc(hwmgr->smumgr, result = smu7_copy_bytes_to_smc(hwmgr,
smu_data->smu7_data.dpm_table_start + smu_data->smu7_data.dpm_table_start +
offsetof(SMU73_Discrete_DpmTable, SystemFlags), offsetof(SMU73_Discrete_DpmTable, SystemFlags),
(uint8_t *)&(table->SystemFlags), (uint8_t *)&(table->SystemFlags),
...@@ -1983,7 +1983,7 @@ int fiji_init_smc_table(struct pp_hwmgr *hwmgr) ...@@ -1983,7 +1983,7 @@ int fiji_init_smc_table(struct pp_hwmgr *hwmgr)
PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE(0 == result,
"Failed to upload dpm data to SMC memory!", return result); "Failed to upload dpm data to SMC memory!", return result);
result = fiji_init_arb_table_index(hwmgr->smumgr); result = fiji_init_arb_table_index(hwmgr);
PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE(0 == result,
"Failed to upload arb data to SMC memory!", return result); "Failed to upload arb data to SMC memory!", return result);
...@@ -2093,20 +2093,20 @@ int fiji_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) ...@@ -2093,20 +2093,20 @@ int fiji_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
hwmgr->device, CGS_IND_REG__SMC, hwmgr->device, CGS_IND_REG__SMC,
CG_MULT_THERMAL_CTRL, TEMP_SEL); CG_MULT_THERMAL_CTRL, TEMP_SEL);
res = smu7_copy_bytes_to_smc(hwmgr->smumgr, smu_data->smu7_data.fan_table_start, res = smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.fan_table_start,
(uint8_t *)&fan_table, (uint32_t)sizeof(fan_table), (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table),
SMC_RAM_END); SMC_RAM_END);
if (!res && hwmgr->thermal_controller. if (!res && hwmgr->thermal_controller.
advanceFanControlParameters.ucMinimumPWMLimit) advanceFanControlParameters.ucMinimumPWMLimit)
res = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, res = smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetFanMinPwm, PPSMC_MSG_SetFanMinPwm,
hwmgr->thermal_controller. hwmgr->thermal_controller.
advanceFanControlParameters.ucMinimumPWMLimit); advanceFanControlParameters.ucMinimumPWMLimit);
if (!res && hwmgr->thermal_controller. if (!res && hwmgr->thermal_controller.
advanceFanControlParameters.ulMinFanSCLKAcousticLimit) advanceFanControlParameters.ulMinFanSCLKAcousticLimit)
res = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, res = smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetFanSclkTarget, PPSMC_MSG_SetFanSclkTarget,
hwmgr->thermal_controller. hwmgr->thermal_controller.
advanceFanControlParameters.ulMinFanSCLKAcousticLimit); advanceFanControlParameters.ulMinFanSCLKAcousticLimit);
...@@ -2122,13 +2122,12 @@ int fiji_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) ...@@ -2122,13 +2122,12 @@ int fiji_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
int fiji_thermal_avfs_enable(struct pp_hwmgr *hwmgr) int fiji_thermal_avfs_enable(struct pp_hwmgr *hwmgr)
{ {
int ret; int ret;
struct pp_smumgr *smumgr = (struct pp_smumgr *)(hwmgr->smumgr); struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend);
struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend);
if (smu_data->avfs.avfs_btc_status != AVFS_BTC_ENABLEAVFS) if (smu_data->avfs.avfs_btc_status != AVFS_BTC_ENABLEAVFS)
return 0; return 0;
ret = smum_send_msg_to_smc(smumgr, PPSMC_MSG_EnableAvfs); ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAvfs);
if (!ret) if (!ret)
/* If this param is not changed, this function could fire unnecessarily */ /* If this param is not changed, this function could fire unnecessarily */
...@@ -2168,7 +2167,7 @@ int fiji_update_sclk_threshold(struct pp_hwmgr *hwmgr) ...@@ -2168,7 +2167,7 @@ int fiji_update_sclk_threshold(struct pp_hwmgr *hwmgr)
CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold); CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
result = smu7_copy_bytes_to_smc( result = smu7_copy_bytes_to_smc(
hwmgr->smumgr, hwmgr,
smu_data->smu7_data.dpm_table_start + smu_data->smu7_data.dpm_table_start +
offsetof(SMU73_Discrete_DpmTable, offsetof(SMU73_Discrete_DpmTable,
LowSclkInterruptThreshold), LowSclkInterruptThreshold),
...@@ -2269,7 +2268,7 @@ static int fiji_update_uvd_smc_table(struct pp_hwmgr *hwmgr) ...@@ -2269,7 +2268,7 @@ static int fiji_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
PHM_PlatformCaps_UVDDPM) || PHM_PlatformCaps_UVDDPM) ||
phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_StablePState)) PHM_PlatformCaps_StablePState))
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_UVDDPM_SetEnabledMask, PPSMC_MSG_UVDDPM_SetEnabledMask,
(uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel)); (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel));
return 0; return 0;
...@@ -2301,7 +2300,7 @@ static int fiji_update_vce_smc_table(struct pp_hwmgr *hwmgr) ...@@ -2301,7 +2300,7 @@ static int fiji_update_vce_smc_table(struct pp_hwmgr *hwmgr)
CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value); CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_VCEDPM_SetEnabledMask, PPSMC_MSG_VCEDPM_SetEnabledMask,
(uint32_t)1 << smu_data->smc_state_table.VceBootLevel); (uint32_t)1 << smu_data->smc_state_table.VceBootLevel);
return 0; return 0;
...@@ -2328,7 +2327,7 @@ static int fiji_update_samu_smc_table(struct pp_hwmgr *hwmgr) ...@@ -2328,7 +2327,7 @@ static int fiji_update_samu_smc_table(struct pp_hwmgr *hwmgr)
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_StablePState)) PHM_PlatformCaps_StablePState))
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SAMUDPM_SetEnabledMask, PPSMC_MSG_SAMUDPM_SetEnabledMask,
(uint32_t)(1 << smu_data->smc_state_table.SamuBootLevel)); (uint32_t)(1 << smu_data->smc_state_table.SamuBootLevel));
return 0; return 0;
...@@ -2367,7 +2366,7 @@ int fiji_process_firmware_header(struct pp_hwmgr *hwmgr) ...@@ -2367,7 +2366,7 @@ int fiji_process_firmware_header(struct pp_hwmgr *hwmgr)
int result; int result;
bool error = false; bool error = false;
result = smu7_read_smc_sram_dword(hwmgr->smumgr, result = smu7_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION + SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU73_Firmware_Header, DpmTable), offsetof(SMU73_Firmware_Header, DpmTable),
&tmp, SMC_RAM_END); &tmp, SMC_RAM_END);
...@@ -2377,7 +2376,7 @@ int fiji_process_firmware_header(struct pp_hwmgr *hwmgr) ...@@ -2377,7 +2376,7 @@ int fiji_process_firmware_header(struct pp_hwmgr *hwmgr)
error |= (0 != result); error |= (0 != result);
result = smu7_read_smc_sram_dword(hwmgr->smumgr, result = smu7_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION + SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU73_Firmware_Header, SoftRegisters), offsetof(SMU73_Firmware_Header, SoftRegisters),
&tmp, SMC_RAM_END); &tmp, SMC_RAM_END);
...@@ -2389,7 +2388,7 @@ int fiji_process_firmware_header(struct pp_hwmgr *hwmgr) ...@@ -2389,7 +2388,7 @@ int fiji_process_firmware_header(struct pp_hwmgr *hwmgr)
error |= (0 != result); error |= (0 != result);
result = smu7_read_smc_sram_dword(hwmgr->smumgr, result = smu7_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION + SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU73_Firmware_Header, mcRegisterTable), offsetof(SMU73_Firmware_Header, mcRegisterTable),
&tmp, SMC_RAM_END); &tmp, SMC_RAM_END);
...@@ -2397,7 +2396,7 @@ int fiji_process_firmware_header(struct pp_hwmgr *hwmgr) ...@@ -2397,7 +2396,7 @@ int fiji_process_firmware_header(struct pp_hwmgr *hwmgr)
if (!result) if (!result)
smu_data->smu7_data.mc_reg_table_start = tmp; smu_data->smu7_data.mc_reg_table_start = tmp;
result = smu7_read_smc_sram_dword(hwmgr->smumgr, result = smu7_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION + SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU73_Firmware_Header, FanTable), offsetof(SMU73_Firmware_Header, FanTable),
&tmp, SMC_RAM_END); &tmp, SMC_RAM_END);
...@@ -2407,7 +2406,7 @@ int fiji_process_firmware_header(struct pp_hwmgr *hwmgr) ...@@ -2407,7 +2406,7 @@ int fiji_process_firmware_header(struct pp_hwmgr *hwmgr)
error |= (0 != result); error |= (0 != result);
result = smu7_read_smc_sram_dword(hwmgr->smumgr, result = smu7_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION + SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU73_Firmware_Header, mcArbDramTimingTable), offsetof(SMU73_Firmware_Header, mcArbDramTimingTable),
&tmp, SMC_RAM_END); &tmp, SMC_RAM_END);
...@@ -2417,7 +2416,7 @@ int fiji_process_firmware_header(struct pp_hwmgr *hwmgr) ...@@ -2417,7 +2416,7 @@ int fiji_process_firmware_header(struct pp_hwmgr *hwmgr)
error |= (0 != result); error |= (0 != result);
result = smu7_read_smc_sram_dword(hwmgr->smumgr, result = smu7_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION + SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU73_Firmware_Header, Version), offsetof(SMU73_Firmware_Header, Version),
&tmp, SMC_RAM_END); &tmp, SMC_RAM_END);
...@@ -2482,6 +2481,6 @@ int fiji_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr, ...@@ -2482,6 +2481,6 @@ int fiji_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
levels[i].DownHyst = request->down_hyst; levels[i].DownHyst = request->down_hyst;
} }
return smu7_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels, return smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
array_size, SMC_RAM_END); array_size, SMC_RAM_END);
} }
drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
浏览文件 @ d3f8c0ab
...@@ -58,122 +58,122 @@ static const struct SMU73_Discrete_GraphicsLevel avfs_graphics_level[8] = { ...@@ -58,122 +58,122 @@ static const struct SMU73_Discrete_GraphicsLevel avfs_graphics_level[8] = {
{ 0xf811d047, 0x80380100, 0x01, 0x00, 0x1e00, 0x00000610, 0x87020000, 0x21680000, 0x12000000, 0, 0, 0x0c, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00 } { 0xf811d047, 0x80380100, 0x01, 0x00, 0x1e00, 0x00000610, 0x87020000, 0x21680000, 0x12000000, 0, 0, 0x0c, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00 }
}; };
static int fiji_start_smu_in_protection_mode(struct pp_smumgr *smumgr) static int fiji_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr)
{ {
int result = 0; int result = 0;
/* Wait for smc boot up */ /* Wait for smc boot up */
/* SMUM_WAIT_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, /* SMUM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
RCU_UC_EVENTS, boot_seq_done, 0); */ RCU_UC_EVENTS, boot_seq_done, 0); */
SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_RESET_CNTL, rst_reg, 1); SMC_SYSCON_RESET_CNTL, rst_reg, 1);
result = smu7_upload_smu_firmware_image(smumgr); result = smu7_upload_smu_firmware_image(hwmgr);
if (result) if (result)
return result; return result;
/* Clear status */ /* Clear status */
cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
ixSMU_STATUS, 0); ixSMU_STATUS, 0);
SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
/* De-assert reset */ /* De-assert reset */
SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_RESET_CNTL, rst_reg, 0); SMC_SYSCON_RESET_CNTL, rst_reg, 0);
/* Wait for ROM firmware to initialize interrupt hendler */ /* Wait for ROM firmware to initialize interrupt hendler */
/*SMUM_WAIT_VFPF_INDIRECT_REGISTER(smumgr, SMC_IND, /*SMUM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, SMC_IND,
SMC_INTR_CNTL_MASK_0, 0x10040, 0xFFFFFFFF); */ SMC_INTR_CNTL_MASK_0, 0x10040, 0xFFFFFFFF); */
/* Set SMU Auto Start */ /* Set SMU Auto Start */
SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMU_INPUT_DATA, AUTO_START, 1); SMU_INPUT_DATA, AUTO_START, 1);
/* Clear firmware interrupt enable flag */ /* Clear firmware interrupt enable flag */
cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
ixFIRMWARE_FLAGS, 0); ixFIRMWARE_FLAGS, 0);
SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, RCU_UC_EVENTS, SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS,
INTERRUPTS_ENABLED, 1); INTERRUPTS_ENABLED, 1);
cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, 0x20000); cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, 0x20000);
cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, PPSMC_MSG_Test); cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, PPSMC_MSG_Test);
SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0); SMUM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);
/* Wait for done bit to be set */ /* Wait for done bit to be set */
SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
SMU_STATUS, SMU_DONE, 0); SMU_STATUS, SMU_DONE, 0);
/* Check pass/failed indicator */ /* Check pass/failed indicator */
if (SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, if (SMUM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMU_STATUS, SMU_PASS) != 1) { SMU_STATUS, SMU_PASS) != 1) {
PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE(false,
"SMU Firmware start failed!", return -1); "SMU Firmware start failed!", return -1);
} }
/* Wait for firmware to initialize */ /* Wait for firmware to initialize */
SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1); FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
return result; return result;
} }
static int fiji_start_smu_in_non_protection_mode(struct pp_smumgr *smumgr) static int fiji_start_smu_in_non_protection_mode(struct pp_hwmgr *hwmgr)
{ {
int result = 0; int result = 0;
/* wait for smc boot up */ /* wait for smc boot up */
SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
RCU_UC_EVENTS, boot_seq_done, 0); RCU_UC_EVENTS, boot_seq_done, 0);
/* Clear firmware interrupt enable flag */ /* Clear firmware interrupt enable flag */
cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
ixFIRMWARE_FLAGS, 0); ixFIRMWARE_FLAGS, 0);
/* Assert reset */ /* Assert reset */
SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_RESET_CNTL, rst_reg, 1); SMC_SYSCON_RESET_CNTL, rst_reg, 1);
result = smu7_upload_smu_firmware_image(smumgr); result = smu7_upload_smu_firmware_image(hwmgr);
if (result) if (result)
return result; return result;
/* Set smc instruct start point at 0x0 */ /* Set smc instruct start point at 0x0 */
smu7_program_jump_on_start(smumgr); smu7_program_jump_on_start(hwmgr);
/* Enable clock */ /* Enable clock */
SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
/* De-assert reset */ /* De-assert reset */
SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_RESET_CNTL, rst_reg, 0); SMC_SYSCON_RESET_CNTL, rst_reg, 0);
/* Wait for firmware to initialize */ /* Wait for firmware to initialize */
SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1); FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
return result; return result;
} }
static int fiji_setup_pwr_virus(struct pp_smumgr *smumgr) static int fiji_setup_pwr_virus(struct pp_hwmgr *hwmgr)
{ {
int i; int i;
int result = -EINVAL; int result = -EINVAL;
uint32_t reg, data; uint32_t reg, data;
const PWR_Command_Table *pvirus = PwrVirusTable; const PWR_Command_Table *pvirus = PwrVirusTable;
struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend); struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend);
for (i = 0; i < PWR_VIRUS_TABLE_SIZE; i++) { for (i = 0; i < PWR_VIRUS_TABLE_SIZE; i++) {
switch (pvirus->command) { switch (pvirus->command) {
case PwrCmdWrite: case PwrCmdWrite:
reg = pvirus->reg; reg = pvirus->reg;
data = pvirus->data; data = pvirus->data;
cgs_write_register(smumgr->device, reg, data); cgs_write_register(hwmgr->device, reg, data);
break; break;
case PwrCmdEnd: case PwrCmdEnd:
...@@ -192,13 +192,13 @@ static int fiji_setup_pwr_virus(struct pp_smumgr *smumgr) ...@@ -192,13 +192,13 @@ static int fiji_setup_pwr_virus(struct pp_smumgr *smumgr)
return result; return result;
} }
static int fiji_start_avfs_btc(struct pp_smumgr *smumgr) static int fiji_start_avfs_btc(struct pp_hwmgr *hwmgr)
{ {
int result = 0; int result = 0;
struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend); struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend);
if (0 != smu_data->avfs.avfs_btc_param) { if (0 != smu_data->avfs.avfs_btc_param) {
if (0 != smu7_send_msg_to_smc_with_parameter(smumgr, if (0 != smu7_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_PerformBtc, smu_data->avfs.avfs_btc_param)) { PPSMC_MSG_PerformBtc, smu_data->avfs.avfs_btc_param)) {
pr_info("[AVFS][Fiji_PerformBtc] PerformBTC SMU msg failed"); pr_info("[AVFS][Fiji_PerformBtc] PerformBTC SMU msg failed");
result = -EINVAL; result = -EINVAL;
...@@ -206,23 +206,23 @@ static int fiji_start_avfs_btc(struct pp_smumgr *smumgr) ...@@ -206,23 +206,23 @@ static int fiji_start_avfs_btc(struct pp_smumgr *smumgr)
} }
/* Soft-Reset to reset the engine before loading uCode */ /* Soft-Reset to reset the engine before loading uCode */
/* halt */ /* halt */
cgs_write_register(smumgr->device, mmCP_MEC_CNTL, 0x50000000); cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, 0x50000000);
/* reset everything */ /* reset everything */
cgs_write_register(smumgr->device, mmGRBM_SOFT_RESET, 0xffffffff); cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0xffffffff);
/* clear reset */ /* clear reset */
cgs_write_register(smumgr->device, mmGRBM_SOFT_RESET, 0); cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0);
return result; return result;
} }
static int fiji_setup_graphics_level_structure(struct pp_smumgr *smumgr) static int fiji_setup_graphics_level_structure(struct pp_hwmgr *hwmgr)
{ {
int32_t vr_config; int32_t vr_config;
uint32_t table_start; uint32_t table_start;
uint32_t level_addr, vr_config_addr; uint32_t level_addr, vr_config_addr;
uint32_t level_size = sizeof(avfs_graphics_level); uint32_t level_size = sizeof(avfs_graphics_level);
PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(smumgr, PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION + SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU73_Firmware_Header, DpmTable), offsetof(SMU73_Firmware_Header, DpmTable),
&table_start, 0x40000), &table_start, 0x40000),
...@@ -237,7 +237,7 @@ static int fiji_setup_graphics_level_structure(struct pp_smumgr *smumgr) ...@@ -237,7 +237,7 @@ static int fiji_setup_graphics_level_structure(struct pp_smumgr *smumgr)
vr_config_addr = table_start + vr_config_addr = table_start +
offsetof(SMU73_Discrete_DpmTable, VRConfig); offsetof(SMU73_Discrete_DpmTable, VRConfig);
PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, vr_config_addr, PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, vr_config_addr,
(uint8_t *)&vr_config, sizeof(int32_t), 0x40000), (uint8_t *)&vr_config, sizeof(int32_t), 0x40000),
"[AVFS][Fiji_SetupGfxLvlStruct] Problems copying " "[AVFS][Fiji_SetupGfxLvlStruct] Problems copying "
"vr_config value over to SMC", "vr_config value over to SMC",
...@@ -245,7 +245,7 @@ static int fiji_setup_graphics_level_structure(struct pp_smumgr *smumgr) ...@@ -245,7 +245,7 @@ static int fiji_setup_graphics_level_structure(struct pp_smumgr *smumgr)
level_addr = table_start + offsetof(SMU73_Discrete_DpmTable, GraphicsLevel); level_addr = table_start + offsetof(SMU73_Discrete_DpmTable, GraphicsLevel);
PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, level_addr, PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, level_addr,
(uint8_t *)(&avfs_graphics_level), level_size, 0x40000), (uint8_t *)(&avfs_graphics_level), level_size, 0x40000),
"[AVFS][Fiji_SetupGfxLvlStruct] Copying of DPM table failed!", "[AVFS][Fiji_SetupGfxLvlStruct] Copying of DPM table failed!",
return -1;); return -1;);
...@@ -253,9 +253,9 @@ static int fiji_setup_graphics_level_structure(struct pp_smumgr *smumgr) ...@@ -253,9 +253,9 @@ static int fiji_setup_graphics_level_structure(struct pp_smumgr *smumgr)
return 0; return 0;
} }
static int fiji_avfs_event_mgr(struct pp_smumgr *smumgr, bool smu_started) static int fiji_avfs_event_mgr(struct pp_hwmgr *hwmgr, bool smu_started)
{ {
struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend); struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend);
switch (smu_data->avfs.avfs_btc_status) { switch (smu_data->avfs.avfs_btc_status) {
case AVFS_BTC_COMPLETED_PREVIOUSLY: case AVFS_BTC_COMPLETED_PREVIOUSLY:
...@@ -265,17 +265,17 @@ static int fiji_avfs_event_mgr(struct pp_smumgr *smumgr, bool smu_started) ...@@ -265,17 +265,17 @@ static int fiji_avfs_event_mgr(struct pp_smumgr *smumgr, bool smu_started)
if (!smu_started) if (!smu_started)
break; break;
smu_data->avfs.avfs_btc_status = AVFS_BTC_FAILED; smu_data->avfs.avfs_btc_status = AVFS_BTC_FAILED;
PP_ASSERT_WITH_CODE(0 == fiji_setup_graphics_level_structure(smumgr), PP_ASSERT_WITH_CODE(0 == fiji_setup_graphics_level_structure(hwmgr),
"[AVFS][fiji_avfs_event_mgr] Could not Copy Graphics Level" "[AVFS][fiji_avfs_event_mgr] Could not Copy Graphics Level"
" table over to SMU", " table over to SMU",
return -EINVAL;); return -EINVAL;);
smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL; smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL;
PP_ASSERT_WITH_CODE(0 == fiji_setup_pwr_virus(smumgr), PP_ASSERT_WITH_CODE(0 == fiji_setup_pwr_virus(hwmgr),
"[AVFS][fiji_avfs_event_mgr] Could not setup " "[AVFS][fiji_avfs_event_mgr] Could not setup "
"Pwr Virus for AVFS ", "Pwr Virus for AVFS ",
return -EINVAL;); return -EINVAL;);
smu_data->avfs.avfs_btc_status = AVFS_BTC_FAILED; smu_data->avfs.avfs_btc_status = AVFS_BTC_FAILED;
PP_ASSERT_WITH_CODE(0 == fiji_start_avfs_btc(smumgr), PP_ASSERT_WITH_CODE(0 == fiji_start_avfs_btc(hwmgr),
"[AVFS][fiji_avfs_event_mgr] Failure at " "[AVFS][fiji_avfs_event_mgr] Failure at "
"fiji_start_avfs_btc. AVFS Disabled", "fiji_start_avfs_btc. AVFS Disabled",
return -EINVAL;); return -EINVAL;);
...@@ -293,64 +293,64 @@ static int fiji_avfs_event_mgr(struct pp_smumgr *smumgr, bool smu_started) ...@@ -293,64 +293,64 @@ static int fiji_avfs_event_mgr(struct pp_smumgr *smumgr, bool smu_started)
return 0; return 0;
} }
static int fiji_start_smu(struct pp_smumgr *smumgr) static int fiji_start_smu(struct pp_hwmgr *hwmgr)
{ {
int result = 0; int result = 0;
struct fiji_smumgr *priv = (struct fiji_smumgr *)(smumgr->backend); struct fiji_smumgr *priv = (struct fiji_smumgr *)(hwmgr->smumgr->backend);
/* Only start SMC if SMC RAM is not running */ /* Only start SMC if SMC RAM is not running */
if (!(smu7_is_smc_ram_running(smumgr) if (!(smu7_is_smc_ram_running(hwmgr)
|| cgs_is_virtualization_enabled(smumgr->device))) { || cgs_is_virtualization_enabled(hwmgr->device))) {
fiji_avfs_event_mgr(smumgr, false); fiji_avfs_event_mgr(hwmgr, false);
/* Check if SMU is running in protected mode */ /* Check if SMU is running in protected mode */
if (0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, if (0 == SMUM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
CGS_IND_REG__SMC, CGS_IND_REG__SMC,
SMU_FIRMWARE, SMU_MODE)) { SMU_FIRMWARE, SMU_MODE)) {
result = fiji_start_smu_in_non_protection_mode(smumgr); result = fiji_start_smu_in_non_protection_mode(hwmgr);
if (result) if (result)
return result; return result;
} else { } else {
result = fiji_start_smu_in_protection_mode(smumgr); result = fiji_start_smu_in_protection_mode(hwmgr);
if (result) if (result)
return result; return result;
} }
fiji_avfs_event_mgr(smumgr, true); fiji_avfs_event_mgr(hwmgr, true);
} }
/* To initialize all clock gating before RLC loaded and running.*/ /* To initialize all clock gating before RLC loaded and running.*/
cgs_set_clockgating_state(smumgr->device, cgs_set_clockgating_state(hwmgr->device,
AMD_IP_BLOCK_TYPE_GFX, AMD_CG_STATE_GATE); AMD_IP_BLOCK_TYPE_GFX, AMD_CG_STATE_GATE);
cgs_set_clockgating_state(smumgr->device, cgs_set_clockgating_state(hwmgr->device,
AMD_IP_BLOCK_TYPE_GMC, AMD_CG_STATE_GATE); AMD_IP_BLOCK_TYPE_GMC, AMD_CG_STATE_GATE);
cgs_set_clockgating_state(smumgr->device, cgs_set_clockgating_state(hwmgr->device,
AMD_IP_BLOCK_TYPE_SDMA, AMD_CG_STATE_GATE); AMD_IP_BLOCK_TYPE_SDMA, AMD_CG_STATE_GATE);
cgs_set_clockgating_state(smumgr->device, cgs_set_clockgating_state(hwmgr->device,
AMD_IP_BLOCK_TYPE_COMMON, AMD_CG_STATE_GATE); AMD_IP_BLOCK_TYPE_COMMON, AMD_CG_STATE_GATE);
/* Setup SoftRegsStart here for register lookup in case /* Setup SoftRegsStart here for register lookup in case
* DummyBackEnd is used and ProcessFirmwareHeader is not executed * DummyBackEnd is used and ProcessFirmwareHeader is not executed
*/ */
smu7_read_smc_sram_dword(smumgr, smu7_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION + SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU73_Firmware_Header, SoftRegisters), offsetof(SMU73_Firmware_Header, SoftRegisters),
&(priv->smu7_data.soft_regs_start), 0x40000); &(priv->smu7_data.soft_regs_start), 0x40000);
result = smu7_request_smu_load_fw(smumgr); result = smu7_request_smu_load_fw(hwmgr);
return result; return result;
} }
static bool fiji_is_hw_avfs_present(struct pp_smumgr *smumgr) static bool fiji_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
{ {
uint32_t efuse = 0; uint32_t efuse = 0;
uint32_t mask = (1 << ((AVFS_EN_MSB - AVFS_EN_LSB) + 1)) - 1; uint32_t mask = (1 << ((AVFS_EN_MSB - AVFS_EN_LSB) + 1)) - 1;
if (cgs_is_virtualization_enabled(smumgr->device)) if (cgs_is_virtualization_enabled(hwmgr->device))
return 0; return 0;
if (!atomctrl_read_efuse(smumgr->device, AVFS_EN_LSB, AVFS_EN_MSB, if (!atomctrl_read_efuse(hwmgr->device, AVFS_EN_LSB, AVFS_EN_MSB,
mask, &efuse)) { mask, &efuse)) {
if (efuse) if (efuse)
return true; return true;
...@@ -365,7 +365,7 @@ static bool fiji_is_hw_avfs_present(struct pp_smumgr *smumgr) ...@@ -365,7 +365,7 @@ static bool fiji_is_hw_avfs_present(struct pp_smumgr *smumgr)
* @param smc_addr the address in the SMC RAM to access. * @param smc_addr the address in the SMC RAM to access.
* @param value to write to the SMC SRAM. * @param value to write to the SMC SRAM.
*/ */
static int fiji_smu_init(struct pp_smumgr *smumgr) static int fiji_smu_init(struct pp_hwmgr *hwmgr)
{ {
int i; int i;
struct fiji_smumgr *fiji_priv = NULL; struct fiji_smumgr *fiji_priv = NULL;
...@@ -375,9 +375,9 @@ static int fiji_smu_init(struct pp_smumgr *smumgr) ...@@ -375,9 +375,9 @@ static int fiji_smu_init(struct pp_smumgr *smumgr)
if (fiji_priv == NULL) if (fiji_priv == NULL)
return -ENOMEM; return -ENOMEM;
smumgr->backend = fiji_priv; hwmgr->smumgr->backend = fiji_priv;
if (smu7_init(smumgr)) if (smu7_init(hwmgr))
return -EINVAL; return -EINVAL;
for (i = 0; i < SMU73_MAX_LEVELS_GRAPHICS; i++) for (i = 0; i < SMU73_MAX_LEVELS_GRAPHICS; i++)
......
drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c
浏览文件 @ d3f8c0ab
...@@ -163,7 +163,7 @@ static int iceland_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offs ...@@ -163,7 +163,7 @@ static int iceland_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offs
const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults; const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults;
uint32_t temp; uint32_t temp;
if (smu7_read_smc_sram_dword(hwmgr->smumgr, if (smu7_read_smc_sram_dword(hwmgr,
fuse_table_offset + fuse_table_offset +
offsetof(SMU71_Discrete_PmFuses, TdcWaterfallCtl), offsetof(SMU71_Discrete_PmFuses, TdcWaterfallCtl),
(uint32_t *)&temp, SMC_RAM_END)) (uint32_t *)&temp, SMC_RAM_END))
...@@ -264,7 +264,7 @@ static int iceland_populate_pm_fuses(struct pp_hwmgr *hwmgr) ...@@ -264,7 +264,7 @@ static int iceland_populate_pm_fuses(struct pp_hwmgr *hwmgr)
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_PowerContainment)) { PHM_PlatformCaps_PowerContainment)) {
if (smu7_read_smc_sram_dword(hwmgr->smumgr, if (smu7_read_smc_sram_dword(hwmgr,
SMU71_FIRMWARE_HEADER_LOCATION + SMU71_FIRMWARE_HEADER_LOCATION +
offsetof(SMU71_Firmware_Header, PmFuseTable), offsetof(SMU71_Firmware_Header, PmFuseTable),
&pm_fuse_table_offset, SMC_RAM_END)) &pm_fuse_table_offset, SMC_RAM_END))
...@@ -318,7 +318,7 @@ static int iceland_populate_pm_fuses(struct pp_hwmgr *hwmgr) ...@@ -318,7 +318,7 @@ static int iceland_populate_pm_fuses(struct pp_hwmgr *hwmgr)
"Attempt to populate BapmVddCBaseLeakage Hi and Lo Sidd Failed!", "Attempt to populate BapmVddCBaseLeakage Hi and Lo Sidd Failed!",
return -EINVAL); return -EINVAL);
if (smu7_copy_bytes_to_smc(hwmgr->smumgr, pm_fuse_table_offset, if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
(uint8_t *)&smu_data->power_tune_table, (uint8_t *)&smu_data->power_tune_table,
sizeof(struct SMU71_Discrete_PmFuses), SMC_RAM_END)) sizeof(struct SMU71_Discrete_PmFuses), SMC_RAM_END))
PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE(false,
...@@ -881,7 +881,7 @@ int iceland_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) ...@@ -881,7 +881,7 @@ int iceland_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
smu_data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled; smu_data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled;
/* level count will send to smc once at init smc table and never change*/ /* level count will send to smc once at init smc table and never change*/
result = smu7_copy_bytes_to_smc(hwmgr->smumgr, level_array_adress, result = smu7_copy_bytes_to_smc(hwmgr, level_array_adress,
(uint8_t *)levels, (uint32_t)level_array_size, (uint8_t *)levels, (uint32_t)level_array_size,
SMC_RAM_END); SMC_RAM_END);
...@@ -1246,7 +1246,7 @@ int iceland_populate_all_memory_levels(struct pp_hwmgr *hwmgr) ...@@ -1246,7 +1246,7 @@ int iceland_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH; smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
/* level count will send to smc once at init smc table and never change*/ /* level count will send to smc once at init smc table and never change*/
result = smu7_copy_bytes_to_smc(hwmgr->smumgr, result = smu7_copy_bytes_to_smc(hwmgr,
level_array_adress, (uint8_t *)levels, (uint32_t)level_array_size, level_array_adress, (uint8_t *)levels, (uint32_t)level_array_size,
SMC_RAM_END); SMC_RAM_END);
...@@ -1507,7 +1507,7 @@ static int iceland_program_memory_timing_parameters(struct pp_hwmgr *hwmgr) ...@@ -1507,7 +1507,7 @@ static int iceland_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
if (0 == result) { if (0 == result) {
result = smu7_copy_bytes_to_smc( result = smu7_copy_bytes_to_smc(
hwmgr->smumgr, hwmgr,
smu_data->smu7_data.arb_table_start, smu_data->smu7_data.arb_table_start,
(uint8_t *)&arb_regs, (uint8_t *)&arb_regs,
sizeof(SMU71_Discrete_MCArbDramTimingTable), sizeof(SMU71_Discrete_MCArbDramTimingTable),
...@@ -1561,10 +1561,10 @@ static int iceland_populate_smc_boot_level(struct pp_hwmgr *hwmgr, ...@@ -1561,10 +1561,10 @@ static int iceland_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
return result; return result;
} }
static int iceland_populate_mc_reg_address(struct pp_smumgr *smumgr, static int iceland_populate_mc_reg_address(struct pp_hwmgr *hwmgr,
SMU71_Discrete_MCRegisters *mc_reg_table) SMU71_Discrete_MCRegisters *mc_reg_table)
{ {
const struct iceland_smumgr *smu_data = (struct iceland_smumgr *)smumgr->backend; const struct iceland_smumgr *smu_data = (struct iceland_smumgr *)hwmgr->smumgr->backend;
uint32_t i, j; uint32_t i, j;
...@@ -1601,13 +1601,12 @@ static void iceland_convert_mc_registers( ...@@ -1601,13 +1601,12 @@ static void iceland_convert_mc_registers(
} }
} }
static int iceland_convert_mc_reg_table_entry_to_smc( static int iceland_convert_mc_reg_table_entry_to_smc(struct pp_hwmgr *hwmgr,
struct pp_smumgr *smumgr,
const uint32_t memory_clock, const uint32_t memory_clock,
SMU71_Discrete_MCRegisterSet *mc_reg_table_data SMU71_Discrete_MCRegisterSet *mc_reg_table_data
) )
{ {
struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(smumgr->backend); struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend);
uint32_t i = 0; uint32_t i = 0;
for (i = 0; i < smu_data->mc_reg_table.num_entries; i++) { for (i = 0; i < smu_data->mc_reg_table.num_entries; i++) {
...@@ -1637,7 +1636,7 @@ static int iceland_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr, ...@@ -1637,7 +1636,7 @@ static int iceland_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
for (i = 0; i < data->dpm_table.mclk_table.count; i++) { for (i = 0; i < data->dpm_table.mclk_table.count; i++) {
res = iceland_convert_mc_reg_table_entry_to_smc( res = iceland_convert_mc_reg_table_entry_to_smc(
hwmgr->smumgr, hwmgr,
data->dpm_table.mclk_table.dpm_levels[i].value, data->dpm_table.mclk_table.dpm_levels[i].value,
&mc_regs->data[i] &mc_regs->data[i]
); );
...@@ -1651,8 +1650,7 @@ static int iceland_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr, ...@@ -1651,8 +1650,7 @@ static int iceland_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
static int iceland_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr) static int iceland_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
{ {
struct pp_smumgr *smumgr = hwmgr->smumgr; struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend);
struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(smumgr->backend);
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
uint32_t address; uint32_t address;
int32_t result; int32_t result;
...@@ -1671,7 +1669,7 @@ static int iceland_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr) ...@@ -1671,7 +1669,7 @@ static int iceland_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
address = smu_data->smu7_data.mc_reg_table_start + (uint32_t)offsetof(SMU71_Discrete_MCRegisters, data[0]); address = smu_data->smu7_data.mc_reg_table_start + (uint32_t)offsetof(SMU71_Discrete_MCRegisters, data[0]);
return smu7_copy_bytes_to_smc(hwmgr->smumgr, address, return smu7_copy_bytes_to_smc(hwmgr, address,
(uint8_t *)&smu_data->mc_regs.data[0], (uint8_t *)&smu_data->mc_regs.data[0],
sizeof(SMU71_Discrete_MCRegisterSet) * data->dpm_table.mclk_table.count, sizeof(SMU71_Discrete_MCRegisterSet) * data->dpm_table.mclk_table.count,
SMC_RAM_END); SMC_RAM_END);
...@@ -1680,11 +1678,10 @@ static int iceland_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr) ...@@ -1680,11 +1678,10 @@ static int iceland_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
static int iceland_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr) static int iceland_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
{ {
int result; int result;
struct pp_smumgr *smumgr = hwmgr->smumgr; struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend);
struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(smumgr->backend);
memset(&smu_data->mc_regs, 0x00, sizeof(SMU71_Discrete_MCRegisters)); memset(&smu_data->mc_regs, 0x00, sizeof(SMU71_Discrete_MCRegisters));
result = iceland_populate_mc_reg_address(smumgr, &(smu_data->mc_regs)); result = iceland_populate_mc_reg_address(hwmgr, &(smu_data->mc_regs));
PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE(0 == result,
"Failed to initialize MCRegTable for the MC register addresses!", return result;); "Failed to initialize MCRegTable for the MC register addresses!", return result;);
...@@ -1692,7 +1689,7 @@ static int iceland_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr) ...@@ -1692,7 +1689,7 @@ static int iceland_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE(0 == result,
"Failed to initialize MCRegTable for driver state!", return result;); "Failed to initialize MCRegTable for driver state!", return result;);
return smu7_copy_bytes_to_smc(smumgr, smu_data->smu7_data.mc_reg_table_start, return smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.mc_reg_table_start,
(uint8_t *)&smu_data->mc_regs, sizeof(SMU71_Discrete_MCRegisters), SMC_RAM_END); (uint8_t *)&smu_data->mc_regs, sizeof(SMU71_Discrete_MCRegisters), SMC_RAM_END);
} }
...@@ -1944,7 +1941,7 @@ int iceland_init_smc_table(struct pp_hwmgr *hwmgr) ...@@ -1944,7 +1941,7 @@ int iceland_init_smc_table(struct pp_hwmgr *hwmgr)
table->BootMVdd = PP_HOST_TO_SMC_US(table->BootMVdd * VOLTAGE_SCALE); table->BootMVdd = PP_HOST_TO_SMC_US(table->BootMVdd * VOLTAGE_SCALE);
/* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */ /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
result = smu7_copy_bytes_to_smc(hwmgr->smumgr, smu_data->smu7_data.dpm_table_start + result = smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.dpm_table_start +
offsetof(SMU71_Discrete_DpmTable, SystemFlags), offsetof(SMU71_Discrete_DpmTable, SystemFlags),
(uint8_t *)&(table->SystemFlags), (uint8_t *)&(table->SystemFlags),
sizeof(SMU71_Discrete_DpmTable)-3 * sizeof(SMU71_PIDController), sizeof(SMU71_Discrete_DpmTable)-3 * sizeof(SMU71_PIDController),
...@@ -1954,7 +1951,7 @@ int iceland_init_smc_table(struct pp_hwmgr *hwmgr) ...@@ -1954,7 +1951,7 @@ int iceland_init_smc_table(struct pp_hwmgr *hwmgr)
"Failed to upload dpm data to SMC memory!", return result;); "Failed to upload dpm data to SMC memory!", return result;);
/* Upload all ulv setting to SMC memory.(dpm level, dpm level count etc) */ /* Upload all ulv setting to SMC memory.(dpm level, dpm level count etc) */
result = smu7_copy_bytes_to_smc(hwmgr->smumgr, result = smu7_copy_bytes_to_smc(hwmgr,
smu_data->smu7_data.ulv_setting_starts, smu_data->smu7_data.ulv_setting_starts,
(uint8_t *)&(smu_data->ulv_setting), (uint8_t *)&(smu_data->ulv_setting),
sizeof(SMU71_Discrete_Ulv), sizeof(SMU71_Discrete_Ulv),
...@@ -2053,7 +2050,7 @@ int iceland_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) ...@@ -2053,7 +2050,7 @@ int iceland_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
/* fan_table.FanControl_GL_Flag = 1; */ /* fan_table.FanControl_GL_Flag = 1; */
res = smu7_copy_bytes_to_smc(hwmgr->smumgr, smu7_data->fan_table_start, (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table), SMC_RAM_END); res = smu7_copy_bytes_to_smc(hwmgr, smu7_data->fan_table_start, (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table), SMC_RAM_END);
return 0; return 0;
} }
...@@ -2090,7 +2087,7 @@ int iceland_update_sclk_threshold(struct pp_hwmgr *hwmgr) ...@@ -2090,7 +2087,7 @@ int iceland_update_sclk_threshold(struct pp_hwmgr *hwmgr)
CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold); CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
result = smu7_copy_bytes_to_smc( result = smu7_copy_bytes_to_smc(
hwmgr->smumgr, hwmgr,
smu_data->smu7_data.dpm_table_start + smu_data->smu7_data.dpm_table_start +
offsetof(SMU71_Discrete_DpmTable, offsetof(SMU71_Discrete_DpmTable,
LowSclkInterruptThreshold), LowSclkInterruptThreshold),
...@@ -2177,7 +2174,7 @@ int iceland_process_firmware_header(struct pp_hwmgr *hwmgr) ...@@ -2177,7 +2174,7 @@ int iceland_process_firmware_header(struct pp_hwmgr *hwmgr)
int result; int result;
bool error = false; bool error = false;
result = smu7_read_smc_sram_dword(hwmgr->smumgr, result = smu7_read_smc_sram_dword(hwmgr,
SMU71_FIRMWARE_HEADER_LOCATION + SMU71_FIRMWARE_HEADER_LOCATION +
offsetof(SMU71_Firmware_Header, DpmTable), offsetof(SMU71_Firmware_Header, DpmTable),
&tmp, SMC_RAM_END); &tmp, SMC_RAM_END);
...@@ -2188,7 +2185,7 @@ int iceland_process_firmware_header(struct pp_hwmgr *hwmgr) ...@@ -2188,7 +2185,7 @@ int iceland_process_firmware_header(struct pp_hwmgr *hwmgr)
error |= (0 != result); error |= (0 != result);
result = smu7_read_smc_sram_dword(hwmgr->smumgr, result = smu7_read_smc_sram_dword(hwmgr,
SMU71_FIRMWARE_HEADER_LOCATION + SMU71_FIRMWARE_HEADER_LOCATION +
offsetof(SMU71_Firmware_Header, SoftRegisters), offsetof(SMU71_Firmware_Header, SoftRegisters),
&tmp, SMC_RAM_END); &tmp, SMC_RAM_END);
...@@ -2201,7 +2198,7 @@ int iceland_process_firmware_header(struct pp_hwmgr *hwmgr) ...@@ -2201,7 +2198,7 @@ int iceland_process_firmware_header(struct pp_hwmgr *hwmgr)
error |= (0 != result); error |= (0 != result);
result = smu7_read_smc_sram_dword(hwmgr->smumgr, result = smu7_read_smc_sram_dword(hwmgr,
SMU71_FIRMWARE_HEADER_LOCATION + SMU71_FIRMWARE_HEADER_LOCATION +
offsetof(SMU71_Firmware_Header, mcRegisterTable), offsetof(SMU71_Firmware_Header, mcRegisterTable),
&tmp, SMC_RAM_END); &tmp, SMC_RAM_END);
...@@ -2210,7 +2207,7 @@ int iceland_process_firmware_header(struct pp_hwmgr *hwmgr) ...@@ -2210,7 +2207,7 @@ int iceland_process_firmware_header(struct pp_hwmgr *hwmgr)
smu7_data->mc_reg_table_start = tmp; smu7_data->mc_reg_table_start = tmp;
} }
result = smu7_read_smc_sram_dword(hwmgr->smumgr, result = smu7_read_smc_sram_dword(hwmgr,
SMU71_FIRMWARE_HEADER_LOCATION + SMU71_FIRMWARE_HEADER_LOCATION +
offsetof(SMU71_Firmware_Header, FanTable), offsetof(SMU71_Firmware_Header, FanTable),
&tmp, SMC_RAM_END); &tmp, SMC_RAM_END);
...@@ -2221,7 +2218,7 @@ int iceland_process_firmware_header(struct pp_hwmgr *hwmgr) ...@@ -2221,7 +2218,7 @@ int iceland_process_firmware_header(struct pp_hwmgr *hwmgr)
error |= (0 != result); error |= (0 != result);
result = smu7_read_smc_sram_dword(hwmgr->smumgr, result = smu7_read_smc_sram_dword(hwmgr,
SMU71_FIRMWARE_HEADER_LOCATION + SMU71_FIRMWARE_HEADER_LOCATION +
offsetof(SMU71_Firmware_Header, mcArbDramTimingTable), offsetof(SMU71_Firmware_Header, mcArbDramTimingTable),
&tmp, SMC_RAM_END); &tmp, SMC_RAM_END);
...@@ -2233,7 +2230,7 @@ int iceland_process_firmware_header(struct pp_hwmgr *hwmgr) ...@@ -2233,7 +2230,7 @@ int iceland_process_firmware_header(struct pp_hwmgr *hwmgr)
error |= (0 != result); error |= (0 != result);
result = smu7_read_smc_sram_dword(hwmgr->smumgr, result = smu7_read_smc_sram_dword(hwmgr,
SMU71_FIRMWARE_HEADER_LOCATION + SMU71_FIRMWARE_HEADER_LOCATION +
offsetof(SMU71_Firmware_Header, Version), offsetof(SMU71_Firmware_Header, Version),
&tmp, SMC_RAM_END); &tmp, SMC_RAM_END);
...@@ -2244,7 +2241,7 @@ int iceland_process_firmware_header(struct pp_hwmgr *hwmgr) ...@@ -2244,7 +2241,7 @@ int iceland_process_firmware_header(struct pp_hwmgr *hwmgr)
error |= (0 != result); error |= (0 != result);
result = smu7_read_smc_sram_dword(hwmgr->smumgr, result = smu7_read_smc_sram_dword(hwmgr,
SMU71_FIRMWARE_HEADER_LOCATION + SMU71_FIRMWARE_HEADER_LOCATION +
offsetof(SMU71_Firmware_Header, UlvSettings), offsetof(SMU71_Firmware_Header, UlvSettings),
&tmp, SMC_RAM_END); &tmp, SMC_RAM_END);
......
drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
浏览文件 @ d3f8c0ab
...@@ -39,55 +39,55 @@ ...@@ -39,55 +39,55 @@
#define ICELAND_SMC_SIZE 0x20000 #define ICELAND_SMC_SIZE 0x20000
static int iceland_start_smc(struct pp_smumgr *smumgr) static int iceland_start_smc(struct pp_hwmgr *hwmgr)
{ {
SMUM_WRITE_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMUM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_RESET_CNTL, rst_reg, 0); SMC_SYSCON_RESET_CNTL, rst_reg, 0);
return 0; return 0;
} }
static void iceland_reset_smc(struct pp_smumgr *smumgr) static void iceland_reset_smc(struct pp_hwmgr *hwmgr)
{ {
SMUM_WRITE_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMUM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_RESET_CNTL, SMC_SYSCON_RESET_CNTL,
rst_reg, 1); rst_reg, 1);
} }
static void iceland_stop_smc_clock(struct pp_smumgr *smumgr) static void iceland_stop_smc_clock(struct pp_hwmgr *hwmgr)
{ {
SMUM_WRITE_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMUM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_CLOCK_CNTL_0, SMC_SYSCON_CLOCK_CNTL_0,
ck_disable, 1); ck_disable, 1);
} }
static void iceland_start_smc_clock(struct pp_smumgr *smumgr) static void iceland_start_smc_clock(struct pp_hwmgr *hwmgr)
{ {
SMUM_WRITE_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMUM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_CLOCK_CNTL_0, SMC_SYSCON_CLOCK_CNTL_0,
ck_disable, 0); ck_disable, 0);
} }
static int iceland_smu_start_smc(struct pp_smumgr *smumgr) static int iceland_smu_start_smc(struct pp_hwmgr *hwmgr)
{ {
/* set smc instruct start point at 0x0 */ /* set smc instruct start point at 0x0 */
smu7_program_jump_on_start(smumgr); smu7_program_jump_on_start(hwmgr);
/* enable smc clock */ /* enable smc clock */
iceland_start_smc_clock(smumgr); iceland_start_smc_clock(hwmgr);
/* de-assert reset */ /* de-assert reset */
iceland_start_smc(smumgr); iceland_start_smc(hwmgr);
SMUM_WAIT_INDIRECT_FIELD(smumgr, SMC_IND, FIRMWARE_FLAGS, SMUM_WAIT_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS,
INTERRUPTS_ENABLED, 1); INTERRUPTS_ENABLED, 1);
return 0; return 0;
} }
static int iceland_upload_smc_firmware_data(struct pp_smumgr *smumgr, static int iceland_upload_smc_firmware_data(struct pp_hwmgr *hwmgr,
uint32_t length, const uint8_t *src, uint32_t length, const uint8_t *src,
uint32_t limit, uint32_t start_addr) uint32_t limit, uint32_t start_addr)
{ {
...@@ -96,17 +96,17 @@ static int iceland_upload_smc_firmware_data(struct pp_smumgr *smumgr, ...@@ -96,17 +96,17 @@ static int iceland_upload_smc_firmware_data(struct pp_smumgr *smumgr,
PP_ASSERT_WITH_CODE((limit >= byte_count), "SMC address is beyond the SMC RAM area.", return -EINVAL); PP_ASSERT_WITH_CODE((limit >= byte_count), "SMC address is beyond the SMC RAM area.", return -EINVAL);
cgs_write_register(smumgr->device, mmSMC_IND_INDEX_0, start_addr); cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_0, start_addr);
SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 1); SMUM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 1);
while (byte_count >= 4) { while (byte_count >= 4) {
data = src[0] * 0x1000000 + src[1] * 0x10000 + src[2] * 0x100 + src[3]; data = src[0] * 0x1000000 + src[1] * 0x10000 + src[2] * 0x100 + src[3];
cgs_write_register(smumgr->device, mmSMC_IND_DATA_0, data); cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data);
src += 4; src += 4;
byte_count -= 4; byte_count -= 4;
} }
SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0); SMUM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0);
PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be dividable by 4.", return -EINVAL); PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be dividable by 4.", return -EINVAL);
...@@ -114,16 +114,16 @@ static int iceland_upload_smc_firmware_data(struct pp_smumgr *smumgr, ...@@ -114,16 +114,16 @@ static int iceland_upload_smc_firmware_data(struct pp_smumgr *smumgr,
} }
static int iceland_smu_upload_firmware_image(struct pp_smumgr *smumgr) static int iceland_smu_upload_firmware_image(struct pp_hwmgr *hwmgr)
{ {
uint32_t val; uint32_t val;
struct cgs_firmware_info info = {0}; struct cgs_firmware_info info = {0};
if (smumgr == NULL || smumgr->device == NULL) if (hwmgr == NULL || hwmgr->device == NULL)
return -EINVAL; return -EINVAL;
/* load SMC firmware */ /* load SMC firmware */
cgs_get_firmware_info(smumgr->device, cgs_get_firmware_info(hwmgr->device,
smu7_convert_fw_type_to_cgs(UCODE_ID_SMU), &info); smu7_convert_fw_type_to_cgs(UCODE_ID_SMU), &info);
if (info.image_size & 3) { if (info.image_size & 3) {
...@@ -137,56 +137,56 @@ static int iceland_smu_upload_firmware_image(struct pp_smumgr *smumgr) ...@@ -137,56 +137,56 @@ static int iceland_smu_upload_firmware_image(struct pp_smumgr *smumgr)
} }
/* wait for smc boot up */ /* wait for smc boot up */
SMUM_WAIT_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, SMUM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
RCU_UC_EVENTS, boot_seq_done, 0); RCU_UC_EVENTS, boot_seq_done, 0);
/* clear firmware interrupt enable flag */ /* clear firmware interrupt enable flag */
val = cgs_read_ind_register(smumgr->device, CGS_IND_REG__SMC, val = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
ixSMC_SYSCON_MISC_CNTL); ixSMC_SYSCON_MISC_CNTL);
cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
ixSMC_SYSCON_MISC_CNTL, val | 1); ixSMC_SYSCON_MISC_CNTL, val | 1);
/* stop smc clock */ /* stop smc clock */
iceland_stop_smc_clock(smumgr); iceland_stop_smc_clock(hwmgr);
/* reset smc */ /* reset smc */
iceland_reset_smc(smumgr); iceland_reset_smc(hwmgr);
iceland_upload_smc_firmware_data(smumgr, info.image_size, iceland_upload_smc_firmware_data(hwmgr, info.image_size,
(uint8_t *)info.kptr, ICELAND_SMC_SIZE, (uint8_t *)info.kptr, ICELAND_SMC_SIZE,
info.ucode_start_address); info.ucode_start_address);
return 0; return 0;
} }
static int iceland_request_smu_load_specific_fw(struct pp_smumgr *smumgr, static int iceland_request_smu_load_specific_fw(struct pp_hwmgr *hwmgr,
uint32_t firmwareType) uint32_t firmwareType)
{ {
return 0; return 0;
} }
static int iceland_start_smu(struct pp_smumgr *smumgr) static int iceland_start_smu(struct pp_hwmgr *hwmgr)
{ {
int result; int result;
result = iceland_smu_upload_firmware_image(smumgr); result = iceland_smu_upload_firmware_image(hwmgr);
if (result) if (result)
return result; return result;
result = iceland_smu_start_smc(smumgr); result = iceland_smu_start_smc(hwmgr);
if (result) if (result)
return result; return result;
if (!smu7_is_smc_ram_running(smumgr)) { if (!smu7_is_smc_ram_running(hwmgr)) {
pr_info("smu not running, upload firmware again \n"); pr_info("smu not running, upload firmware again \n");
result = iceland_smu_upload_firmware_image(smumgr); result = iceland_smu_upload_firmware_image(hwmgr);
if (result) if (result)
return result; return result;
result = iceland_smu_start_smc(smumgr); result = iceland_smu_start_smc(hwmgr);
if (result) if (result)
return result; return result;
} }
result = smu7_request_smu_load_fw(smumgr); result = smu7_request_smu_load_fw(hwmgr);
return result; return result;
} }
...@@ -198,7 +198,7 @@ static int iceland_start_smu(struct pp_smumgr *smumgr) ...@@ -198,7 +198,7 @@ static int iceland_start_smu(struct pp_smumgr *smumgr)
* @param smcAddress the address in the SMC RAM to access. * @param smcAddress the address in the SMC RAM to access.
* @param value to write to the SMC SRAM. * @param value to write to the SMC SRAM.
*/ */
static int iceland_smu_init(struct pp_smumgr *smumgr) static int iceland_smu_init(struct pp_hwmgr *hwmgr)
{ {
int i; int i;
struct iceland_smumgr *iceland_priv = NULL; struct iceland_smumgr *iceland_priv = NULL;
...@@ -208,9 +208,9 @@ static int iceland_smu_init(struct pp_smumgr *smumgr) ...@@ -208,9 +208,9 @@ static int iceland_smu_init(struct pp_smumgr *smumgr)
if (iceland_priv == NULL) if (iceland_priv == NULL)
return -ENOMEM; return -ENOMEM;
smumgr->backend = iceland_priv; hwmgr->smumgr->backend = iceland_priv;
if (smu7_init(smumgr)) if (smu7_init(hwmgr))
return -EINVAL; return -EINVAL;
for (i = 0; i < SMU71_MAX_LEVELS_GRAPHICS; i++) for (i = 0; i < SMU71_MAX_LEVELS_GRAPHICS; i++)
......
drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c
浏览文件 @ d3f8c0ab
...@@ -231,7 +231,7 @@ static int polaris10_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_of ...@@ -231,7 +231,7 @@ static int polaris10_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_of
const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults; const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
uint32_t temp; uint32_t temp;
if (smu7_read_smc_sram_dword(hwmgr->smumgr, if (smu7_read_smc_sram_dword(hwmgr,
fuse_table_offset + fuse_table_offset +
offsetof(SMU74_Discrete_PmFuses, TdcWaterfallCtl), offsetof(SMU74_Discrete_PmFuses, TdcWaterfallCtl),
(uint32_t *)&temp, SMC_RAM_END)) (uint32_t *)&temp, SMC_RAM_END))
...@@ -315,7 +315,7 @@ static int polaris10_populate_pm_fuses(struct pp_hwmgr *hwmgr) ...@@ -315,7 +315,7 @@ static int polaris10_populate_pm_fuses(struct pp_hwmgr *hwmgr)
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_PowerContainment)) { PHM_PlatformCaps_PowerContainment)) {
if (smu7_read_smc_sram_dword(hwmgr->smumgr, if (smu7_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION + SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU74_Firmware_Header, PmFuseTable), offsetof(SMU74_Firmware_Header, PmFuseTable),
&pm_fuse_table_offset, SMC_RAM_END)) &pm_fuse_table_offset, SMC_RAM_END))
...@@ -358,7 +358,7 @@ static int polaris10_populate_pm_fuses(struct pp_hwmgr *hwmgr) ...@@ -358,7 +358,7 @@ static int polaris10_populate_pm_fuses(struct pp_hwmgr *hwmgr)
"Attempt to populate BapmVddCBaseLeakage Hi and Lo " "Attempt to populate BapmVddCBaseLeakage Hi and Lo "
"Sidd Failed!", return -EINVAL); "Sidd Failed!", return -EINVAL);
if (smu7_copy_bytes_to_smc(hwmgr->smumgr, pm_fuse_table_offset, if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
(uint8_t *)&smu_data->power_tune_table, (uint8_t *)&smu_data->power_tune_table,
(sizeof(struct SMU74_Discrete_PmFuses) - 92), SMC_RAM_END)) (sizeof(struct SMU74_Discrete_PmFuses) - 92), SMC_RAM_END))
PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE(false,
...@@ -484,7 +484,6 @@ static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr, ...@@ -484,7 +484,6 @@ static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr,
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
struct phm_ppt_v1_information *table_info = struct phm_ppt_v1_information *table_info =
(struct phm_ppt_v1_information *)(hwmgr->pptable); (struct phm_ppt_v1_information *)(hwmgr->pptable);
struct pp_smumgr *smumgr = hwmgr->smumgr;
state->CcPwrDynRm = 0; state->CcPwrDynRm = 0;
state->CcPwrDynRm1 = 0; state->CcPwrDynRm1 = 0;
...@@ -493,7 +492,7 @@ static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr, ...@@ -493,7 +492,7 @@ static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr,
state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset * state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1); VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
if (smumgr->chip_id == CHIP_POLARIS12 || smumgr->is_kicker) if (hwmgr->chip_id == CHIP_POLARIS12 || hwmgr->smumgr->is_kicker)
state->VddcPhase = data->vddc_phase_shed_control ^ 0x3; state->VddcPhase = data->vddc_phase_shed_control ^ 0x3;
else else
state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1; state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;
...@@ -546,8 +545,7 @@ static int polaris10_populate_smc_link_level(struct pp_hwmgr *hwmgr, ...@@ -546,8 +545,7 @@ static int polaris10_populate_smc_link_level(struct pp_hwmgr *hwmgr,
static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr, static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr,
SMU74_Discrete_DpmTable *table) SMU74_Discrete_DpmTable *table)
{ {
struct pp_smumgr *smumgr = hwmgr->smumgr; struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
uint32_t i, ref_clk; uint32_t i, ref_clk;
struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } }; struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } };
...@@ -597,8 +595,7 @@ static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr, ...@@ -597,8 +595,7 @@ static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr,
static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr, static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr,
uint32_t clock, SMU_SclkSetting *sclk_setting) uint32_t clock, SMU_SclkSetting *sclk_setting)
{ {
struct pp_smumgr *smumgr = hwmgr->smumgr; struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
const SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table); const SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
struct pp_atomctrl_clock_dividers_ai dividers; struct pp_atomctrl_clock_dividers_ai dividers;
uint32_t ref_clock; uint32_t ref_clock;
...@@ -741,9 +738,8 @@ static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr, ...@@ -741,9 +738,8 @@ static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
*/ */
int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
{ {
struct pp_smumgr *smumgr = hwmgr->smumgr;
struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend); struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
struct smu7_dpm_table *dpm_table = &hw_data->dpm_table; struct smu7_dpm_table *dpm_table = &hw_data->dpm_table;
struct phm_ppt_v1_information *table_info = struct phm_ppt_v1_information *table_info =
(struct phm_ppt_v1_information *)(hwmgr->pptable); (struct phm_ppt_v1_information *)(hwmgr->pptable);
...@@ -828,7 +824,7 @@ int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) ...@@ -828,7 +824,7 @@ int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
levels[1].pcieDpmLevel = mid_pcie_level_enabled; levels[1].pcieDpmLevel = mid_pcie_level_enabled;
} }
/* level count will send to smc once at init smc table and never change */ /* level count will send to smc once at init smc table and never change */
result = smu7_copy_bytes_to_smc(smumgr, array, (uint8_t *)levels, result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
(uint32_t)array_size, SMC_RAM_END); (uint32_t)array_size, SMC_RAM_END);
return result; return result;
...@@ -890,9 +886,8 @@ static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr, ...@@ -890,9 +886,8 @@ static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
*/ */
int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr) int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
{ {
struct pp_smumgr *smumgr = hwmgr->smumgr;
struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend); struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
struct smu7_dpm_table *dpm_table = &hw_data->dpm_table; struct smu7_dpm_table *dpm_table = &hw_data->dpm_table;
int result; int result;
/* populate MCLK dpm table to SMU7 */ /* populate MCLK dpm table to SMU7 */
...@@ -933,7 +928,7 @@ int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr) ...@@ -933,7 +928,7 @@ int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
/* level count will send to smc once at init smc table and never change */ /* level count will send to smc once at init smc table and never change */
result = smu7_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels, result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
(uint32_t)array_size, SMC_RAM_END); (uint32_t)array_size, SMC_RAM_END);
return result; return result;
...@@ -1191,9 +1186,8 @@ static int polaris10_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr, ...@@ -1191,9 +1186,8 @@ static int polaris10_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr) static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
{ {
struct pp_smumgr *smumgr = hwmgr->smumgr;
struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend); struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
struct SMU74_Discrete_MCArbDramTimingTable arb_regs; struct SMU74_Discrete_MCArbDramTimingTable arb_regs;
uint32_t i, j; uint32_t i, j;
int result = 0; int result = 0;
...@@ -1212,7 +1206,7 @@ static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr) ...@@ -1212,7 +1206,7 @@ static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
} }
result = smu7_copy_bytes_to_smc( result = smu7_copy_bytes_to_smc(
hwmgr->smumgr, hwmgr,
smu_data->smu7_data.arb_table_start, smu_data->smu7_data.arb_table_start,
(uint8_t *)&arb_regs, (uint8_t *)&arb_regs,
sizeof(SMU74_Discrete_MCArbDramTimingTable), sizeof(SMU74_Discrete_MCArbDramTimingTable),
...@@ -1311,9 +1305,8 @@ static int polaris10_populate_smc_boot_level(struct pp_hwmgr *hwmgr, ...@@ -1311,9 +1305,8 @@ static int polaris10_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr) static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
{ {
struct pp_smumgr *smumgr = hwmgr->smumgr;
struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend); struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
struct phm_ppt_v1_information *table_info = struct phm_ppt_v1_information *table_info =
(struct phm_ppt_v1_information *)(hwmgr->pptable); (struct phm_ppt_v1_information *)(hwmgr->pptable);
uint8_t count, level; uint8_t count, level;
...@@ -1344,8 +1337,7 @@ static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr) ...@@ -1344,8 +1337,7 @@ static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr) static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
{ {
uint32_t ro, efuse, volt_without_cks, volt_with_cks, value, max, min; uint32_t ro, efuse, volt_without_cks, volt_with_cks, value, max, min;
struct pp_smumgr *smumgr = hwmgr->smumgr; struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
uint8_t i, stretch_amount, stretch_amount2, volt_offset = 0; uint8_t i, stretch_amount, stretch_amount2, volt_offset = 0;
struct phm_ppt_v1_information *table_info = struct phm_ppt_v1_information *table_info =
...@@ -1472,8 +1464,7 @@ static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr, ...@@ -1472,8 +1464,7 @@ static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr,
static int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr) static int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
{ {
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
struct pp_smumgr *smumgr = hwmgr->smumgr; struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table); SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
int result = 0; int result = 0;
...@@ -1524,20 +1515,20 @@ static int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr) ...@@ -1524,20 +1515,20 @@ static int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
AVFS_SclkOffset.Sclk_Offset[i] = PP_HOST_TO_SMC_US((uint16_t)(sclk_table->entries[i].sclk_offset) / 100); AVFS_SclkOffset.Sclk_Offset[i] = PP_HOST_TO_SMC_US((uint16_t)(sclk_table->entries[i].sclk_offset) / 100);
} }
result = smu7_read_smc_sram_dword(smumgr, result = smu7_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsMeanNSigma), SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsMeanNSigma),
&tmp, SMC_RAM_END); &tmp, SMC_RAM_END);
smu7_copy_bytes_to_smc(smumgr, smu7_copy_bytes_to_smc(hwmgr,
tmp, tmp,
(uint8_t *)&AVFS_meanNsigma, (uint8_t *)&AVFS_meanNsigma,
sizeof(AVFS_meanNsigma_t), sizeof(AVFS_meanNsigma_t),
SMC_RAM_END); SMC_RAM_END);
result = smu7_read_smc_sram_dword(smumgr, result = smu7_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsSclkOffsetTable), SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsSclkOffsetTable),
&tmp, SMC_RAM_END); &tmp, SMC_RAM_END);
smu7_copy_bytes_to_smc(smumgr, smu7_copy_bytes_to_smc(hwmgr,
tmp, tmp,
(uint8_t *)&AVFS_SclkOffset, (uint8_t *)&AVFS_SclkOffset,
sizeof(AVFS_Sclk_Offset_t), sizeof(AVFS_Sclk_Offset_t),
...@@ -1559,9 +1550,9 @@ static int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr) ...@@ -1559,9 +1550,9 @@ static int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
* @param hwmgr the address of the powerplay hardware manager. * @param hwmgr the address of the powerplay hardware manager.
* @return always 0 * @return always 0
*/ */
static int polaris10_init_arb_table_index(struct pp_smumgr *smumgr) static int polaris10_init_arb_table_index(struct pp_hwmgr *hwmgr)
{ {
struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
uint32_t tmp; uint32_t tmp;
int result; int result;
...@@ -1573,7 +1564,7 @@ static int polaris10_init_arb_table_index(struct pp_smumgr *smumgr) ...@@ -1573,7 +1564,7 @@ static int polaris10_init_arb_table_index(struct pp_smumgr *smumgr)
* In reality this field should not be in that structure * In reality this field should not be in that structure
* but in a soft register. * but in a soft register.
*/ */
result = smu7_read_smc_sram_dword(smumgr, result = smu7_read_smc_sram_dword(hwmgr,
smu_data->smu7_data.arb_table_start, &tmp, SMC_RAM_END); smu_data->smu7_data.arb_table_start, &tmp, SMC_RAM_END);
if (result) if (result)
...@@ -1582,7 +1573,7 @@ static int polaris10_init_arb_table_index(struct pp_smumgr *smumgr) ...@@ -1582,7 +1573,7 @@ static int polaris10_init_arb_table_index(struct pp_smumgr *smumgr)
tmp &= 0x00FFFFFF; tmp &= 0x00FFFFFF;
tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24; tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
return smu7_write_smc_sram_dword(smumgr, return smu7_write_smc_sram_dword(hwmgr,
smu_data->smu7_data.arb_table_start, tmp, SMC_RAM_END); smu_data->smu7_data.arb_table_start, tmp, SMC_RAM_END);
} }
...@@ -1648,9 +1639,8 @@ static void polaris10_save_default_power_profile(struct pp_hwmgr *hwmgr) ...@@ -1648,9 +1639,8 @@ static void polaris10_save_default_power_profile(struct pp_hwmgr *hwmgr)
int polaris10_init_smc_table(struct pp_hwmgr *hwmgr) int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
{ {
int result; int result;
struct pp_smumgr *smumgr = hwmgr->smumgr;
struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend); struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
struct phm_ppt_v1_information *table_info = struct phm_ppt_v1_information *table_info =
(struct phm_ppt_v1_information *)(hwmgr->pptable); (struct phm_ppt_v1_information *)(hwmgr->pptable);
struct SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table); struct SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
...@@ -1842,7 +1832,7 @@ int polaris10_init_smc_table(struct pp_hwmgr *hwmgr) ...@@ -1842,7 +1832,7 @@ int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime); CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
/* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */ /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
result = smu7_copy_bytes_to_smc(hwmgr->smumgr, result = smu7_copy_bytes_to_smc(hwmgr,
smu_data->smu7_data.dpm_table_start + smu_data->smu7_data.dpm_table_start +
offsetof(SMU74_Discrete_DpmTable, SystemFlags), offsetof(SMU74_Discrete_DpmTable, SystemFlags),
(uint8_t *)&(table->SystemFlags), (uint8_t *)&(table->SystemFlags),
...@@ -1851,7 +1841,7 @@ int polaris10_init_smc_table(struct pp_hwmgr *hwmgr) ...@@ -1851,7 +1841,7 @@ int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE(0 == result,
"Failed to upload dpm data to SMC memory!", return result); "Failed to upload dpm data to SMC memory!", return result);
result = polaris10_init_arb_table_index(hwmgr->smumgr); result = polaris10_init_arb_table_index(hwmgr);
PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE(0 == result,
"Failed to upload arb data to SMC memory!", return result); "Failed to upload arb data to SMC memory!", return result);
...@@ -1878,17 +1868,16 @@ static int polaris10_program_mem_timing_parameters(struct pp_hwmgr *hwmgr) ...@@ -1878,17 +1868,16 @@ static int polaris10_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
int polaris10_thermal_avfs_enable(struct pp_hwmgr *hwmgr) int polaris10_thermal_avfs_enable(struct pp_hwmgr *hwmgr)
{ {
int ret; int ret;
struct pp_smumgr *smumgr = (struct pp_smumgr *)(hwmgr->smumgr); struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend);
struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend);
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED) if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
return 0; return 0;
ret = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, ret = smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetGBDroopSettings, data->avfs_vdroop_override_setting); PPSMC_MSG_SetGBDroopSettings, data->avfs_vdroop_override_setting);
ret = (smum_send_msg_to_smc(smumgr, PPSMC_MSG_EnableAvfs) == 0) ? ret = (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAvfs) == 0) ?
0 : -1; 0 : -1;
if (!ret) if (!ret)
...@@ -1990,20 +1979,20 @@ int polaris10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) ...@@ -1990,20 +1979,20 @@ int polaris10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
hwmgr->device, CGS_IND_REG__SMC, hwmgr->device, CGS_IND_REG__SMC,
CG_MULT_THERMAL_CTRL, TEMP_SEL); CG_MULT_THERMAL_CTRL, TEMP_SEL);
res = smu7_copy_bytes_to_smc(hwmgr->smumgr, smu_data->smu7_data.fan_table_start, res = smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.fan_table_start,
(uint8_t *)&fan_table, (uint32_t)sizeof(fan_table), (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table),
SMC_RAM_END); SMC_RAM_END);
if (!res && hwmgr->thermal_controller. if (!res && hwmgr->thermal_controller.
advanceFanControlParameters.ucMinimumPWMLimit) advanceFanControlParameters.ucMinimumPWMLimit)
res = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, res = smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetFanMinPwm, PPSMC_MSG_SetFanMinPwm,
hwmgr->thermal_controller. hwmgr->thermal_controller.
advanceFanControlParameters.ucMinimumPWMLimit); advanceFanControlParameters.ucMinimumPWMLimit);
if (!res && hwmgr->thermal_controller. if (!res && hwmgr->thermal_controller.
advanceFanControlParameters.ulMinFanSCLKAcousticLimit) advanceFanControlParameters.ulMinFanSCLKAcousticLimit)
res = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, res = smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetFanSclkTarget, PPSMC_MSG_SetFanSclkTarget,
hwmgr->thermal_controller. hwmgr->thermal_controller.
advanceFanControlParameters.ulMinFanSCLKAcousticLimit); advanceFanControlParameters.ulMinFanSCLKAcousticLimit);
...@@ -2041,7 +2030,7 @@ static int polaris10_update_uvd_smc_table(struct pp_hwmgr *hwmgr) ...@@ -2041,7 +2030,7 @@ static int polaris10_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
PHM_PlatformCaps_UVDDPM) || PHM_PlatformCaps_UVDDPM) ||
phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_StablePState)) PHM_PlatformCaps_StablePState))
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_UVDDPM_SetEnabledMask, PPSMC_MSG_UVDDPM_SetEnabledMask,
(uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel)); (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel));
return 0; return 0;
...@@ -2073,7 +2062,7 @@ static int polaris10_update_vce_smc_table(struct pp_hwmgr *hwmgr) ...@@ -2073,7 +2062,7 @@ static int polaris10_update_vce_smc_table(struct pp_hwmgr *hwmgr)
CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value); CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_VCEDPM_SetEnabledMask, PPSMC_MSG_VCEDPM_SetEnabledMask,
(uint32_t)1 << smu_data->smc_state_table.VceBootLevel); (uint32_t)1 << smu_data->smc_state_table.VceBootLevel);
return 0; return 0;
...@@ -2100,7 +2089,7 @@ static int polaris10_update_samu_smc_table(struct pp_hwmgr *hwmgr) ...@@ -2100,7 +2089,7 @@ static int polaris10_update_samu_smc_table(struct pp_hwmgr *hwmgr)
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_StablePState)) PHM_PlatformCaps_StablePState))
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SAMUDPM_SetEnabledMask, PPSMC_MSG_SAMUDPM_SetEnabledMask,
(uint32_t)(1 << smu_data->smc_state_table.SamuBootLevel)); (uint32_t)(1 << smu_data->smc_state_table.SamuBootLevel));
return 0; return 0;
...@@ -2164,7 +2153,7 @@ int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr) ...@@ -2164,7 +2153,7 @@ int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold); CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
result = smu7_copy_bytes_to_smc( result = smu7_copy_bytes_to_smc(
hwmgr->smumgr, hwmgr,
smu_data->smu7_data.dpm_table_start + smu_data->smu7_data.dpm_table_start +
offsetof(SMU74_Discrete_DpmTable, offsetof(SMU74_Discrete_DpmTable,
LowSclkInterruptThreshold), LowSclkInterruptThreshold),
...@@ -2258,7 +2247,7 @@ int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr) ...@@ -2258,7 +2247,7 @@ int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
int result; int result;
bool error = false; bool error = false;
result = smu7_read_smc_sram_dword(hwmgr->smumgr, result = smu7_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION + SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU74_Firmware_Header, DpmTable), offsetof(SMU74_Firmware_Header, DpmTable),
&tmp, SMC_RAM_END); &tmp, SMC_RAM_END);
...@@ -2268,7 +2257,7 @@ int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr) ...@@ -2268,7 +2257,7 @@ int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
error |= (0 != result); error |= (0 != result);
result = smu7_read_smc_sram_dword(hwmgr->smumgr, result = smu7_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION + SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU74_Firmware_Header, SoftRegisters), offsetof(SMU74_Firmware_Header, SoftRegisters),
&tmp, SMC_RAM_END); &tmp, SMC_RAM_END);
...@@ -2280,7 +2269,7 @@ int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr) ...@@ -2280,7 +2269,7 @@ int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
error |= (0 != result); error |= (0 != result);
result = smu7_read_smc_sram_dword(hwmgr->smumgr, result = smu7_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION + SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU74_Firmware_Header, mcRegisterTable), offsetof(SMU74_Firmware_Header, mcRegisterTable),
&tmp, SMC_RAM_END); &tmp, SMC_RAM_END);
...@@ -2288,7 +2277,7 @@ int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr) ...@@ -2288,7 +2277,7 @@ int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
if (!result) if (!result)
smu_data->smu7_data.mc_reg_table_start = tmp; smu_data->smu7_data.mc_reg_table_start = tmp;
result = smu7_read_smc_sram_dword(hwmgr->smumgr, result = smu7_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION + SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU74_Firmware_Header, FanTable), offsetof(SMU74_Firmware_Header, FanTable),
&tmp, SMC_RAM_END); &tmp, SMC_RAM_END);
...@@ -2298,7 +2287,7 @@ int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr) ...@@ -2298,7 +2287,7 @@ int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
error |= (0 != result); error |= (0 != result);
result = smu7_read_smc_sram_dword(hwmgr->smumgr, result = smu7_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION + SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU74_Firmware_Header, mcArbDramTimingTable), offsetof(SMU74_Firmware_Header, mcArbDramTimingTable),
&tmp, SMC_RAM_END); &tmp, SMC_RAM_END);
...@@ -2308,7 +2297,7 @@ int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr) ...@@ -2308,7 +2297,7 @@ int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
error |= (0 != result); error |= (0 != result);
result = smu7_read_smc_sram_dword(hwmgr->smumgr, result = smu7_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION + SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU74_Firmware_Header, Version), offsetof(SMU74_Firmware_Header, Version),
&tmp, SMC_RAM_END); &tmp, SMC_RAM_END);
...@@ -2349,6 +2338,6 @@ int polaris10_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr, ...@@ -2349,6 +2338,6 @@ int polaris10_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
levels[i].DownHyst = request->down_hyst; levels[i].DownHyst = request->down_hyst;
} }
return smu7_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels, return smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
array_size, SMC_RAM_END); array_size, SMC_RAM_END);
} }
drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
浏览文件 @ d3f8c0ab
...@@ -60,21 +60,21 @@ static const SMU74_Discrete_GraphicsLevel avfs_graphics_level_polaris10[8] = { ...@@ -60,21 +60,21 @@ static const SMU74_Discrete_GraphicsLevel avfs_graphics_level_polaris10[8] = {
static const SMU74_Discrete_MemoryLevel avfs_memory_level_polaris10 = { static const SMU74_Discrete_MemoryLevel avfs_memory_level_polaris10 = {
0x100ea446, 0, 0x30750000, 0x01, 0x01, 0x01, 0x00, 0x00, 0x64, 0x00, 0x00, 0x1f00, 0x00, 0x00}; 0x100ea446, 0, 0x30750000, 0x01, 0x01, 0x01, 0x00, 0x00, 0x64, 0x00, 0x00, 0x1f00, 0x00, 0x00};
static int polaris10_setup_pwr_virus(struct pp_smumgr *smumgr) static int polaris10_setup_pwr_virus(struct pp_hwmgr *hwmgr)
{ {
int i; int i;
int result = -EINVAL; int result = -EINVAL;
uint32_t reg, data; uint32_t reg, data;
const PWR_Command_Table *pvirus = pwr_virus_table; const PWR_Command_Table *pvirus = pwr_virus_table;
struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend); struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend);
for (i = 0; i < PWR_VIRUS_TABLE_SIZE; i++) { for (i = 0; i < PWR_VIRUS_TABLE_SIZE; i++) {
switch (pvirus->command) { switch (pvirus->command) {
case PwrCmdWrite: case PwrCmdWrite:
reg = pvirus->reg; reg = pvirus->reg;
data = pvirus->data; data = pvirus->data;
cgs_write_register(smumgr->device, reg, data); cgs_write_register(hwmgr->device, reg, data);
break; break;
case PwrCmdEnd: case PwrCmdEnd:
...@@ -93,13 +93,13 @@ static int polaris10_setup_pwr_virus(struct pp_smumgr *smumgr) ...@@ -93,13 +93,13 @@ static int polaris10_setup_pwr_virus(struct pp_smumgr *smumgr)
return result; return result;
} }
static int polaris10_perform_btc(struct pp_smumgr *smumgr) static int polaris10_perform_btc(struct pp_hwmgr *hwmgr)
{ {
int result = 0; int result = 0;
struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend); struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend);
if (0 != smu_data->avfs.avfs_btc_param) { if (0 != smu_data->avfs.avfs_btc_param) {
if (0 != smu7_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_PerformBtc, smu_data->avfs.avfs_btc_param)) { if (0 != smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_PerformBtc, smu_data->avfs.avfs_btc_param)) {
pr_info("[AVFS][SmuPolaris10_PerformBtc] PerformBTC SMU msg failed"); pr_info("[AVFS][SmuPolaris10_PerformBtc] PerformBTC SMU msg failed");
result = -1; result = -1;
} }
...@@ -107,16 +107,16 @@ static int polaris10_perform_btc(struct pp_smumgr *smumgr) ...@@ -107,16 +107,16 @@ static int polaris10_perform_btc(struct pp_smumgr *smumgr)
if (smu_data->avfs.avfs_btc_param > 1) { if (smu_data->avfs.avfs_btc_param > 1) {
/* Soft-Reset to reset the engine before loading uCode */ /* Soft-Reset to reset the engine before loading uCode */
/* halt */ /* halt */
cgs_write_register(smumgr->device, mmCP_MEC_CNTL, 0x50000000); cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, 0x50000000);
/* reset everything */ /* reset everything */
cgs_write_register(smumgr->device, mmGRBM_SOFT_RESET, 0xffffffff); cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0xffffffff);
cgs_write_register(smumgr->device, mmGRBM_SOFT_RESET, 0); cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0);
} }
return result; return result;
} }
static int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr) static int polaris10_setup_graphics_level_structure(struct pp_hwmgr *hwmgr)
{ {
uint32_t vr_config; uint32_t vr_config;
uint32_t dpm_table_start; uint32_t dpm_table_start;
...@@ -127,7 +127,7 @@ static int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr) ...@@ -127,7 +127,7 @@ static int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr)
graphics_level_size = sizeof(avfs_graphics_level_polaris10); graphics_level_size = sizeof(avfs_graphics_level_polaris10);
u16_boot_mvdd = PP_HOST_TO_SMC_US(1300 * VOLTAGE_SCALE); u16_boot_mvdd = PP_HOST_TO_SMC_US(1300 * VOLTAGE_SCALE);
PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(smumgr, PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, DpmTable), SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, DpmTable),
&dpm_table_start, 0x40000), &dpm_table_start, 0x40000),
"[AVFS][Polaris10_SetupGfxLvlStruct] SMU could not communicate starting address of DPM table", "[AVFS][Polaris10_SetupGfxLvlStruct] SMU could not communicate starting address of DPM table",
...@@ -138,14 +138,14 @@ static int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr) ...@@ -138,14 +138,14 @@ static int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr)
vr_config_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, VRConfig); vr_config_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, VRConfig);
PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, vr_config_address, PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, vr_config_address,
(uint8_t *)&vr_config, sizeof(uint32_t), 0x40000), (uint8_t *)&vr_config, sizeof(uint32_t), 0x40000),
"[AVFS][Polaris10_SetupGfxLvlStruct] Problems copying VRConfig value over to SMC", "[AVFS][Polaris10_SetupGfxLvlStruct] Problems copying VRConfig value over to SMC",
return -1); return -1);
graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, GraphicsLevel); graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, graphics_level_address, PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,
(uint8_t *)(&avfs_graphics_level_polaris10), (uint8_t *)(&avfs_graphics_level_polaris10),
graphics_level_size, 0x40000), graphics_level_size, 0x40000),
"[AVFS][Polaris10_SetupGfxLvlStruct] Copying of SCLK DPM table failed!", "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of SCLK DPM table failed!",
...@@ -153,7 +153,7 @@ static int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr) ...@@ -153,7 +153,7 @@ static int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr)
graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, MemoryLevel); graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, graphics_level_address, PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,
(uint8_t *)(&avfs_memory_level_polaris10), sizeof(avfs_memory_level_polaris10), 0x40000), (uint8_t *)(&avfs_memory_level_polaris10), sizeof(avfs_memory_level_polaris10), 0x40000),
"[AVFS][Polaris10_SetupGfxLvlStruct] Copying of MCLK DPM table failed!", "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of MCLK DPM table failed!",
return -1); return -1);
...@@ -162,7 +162,7 @@ static int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr) ...@@ -162,7 +162,7 @@ static int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr)
graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, BootMVdd); graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, BootMVdd);
PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, graphics_level_address, PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,
(uint8_t *)(&u16_boot_mvdd), sizeof(u16_boot_mvdd), 0x40000), (uint8_t *)(&u16_boot_mvdd), sizeof(u16_boot_mvdd), 0x40000),
"[AVFS][Polaris10_SetupGfxLvlStruct] Copying of DPM table failed!", "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of DPM table failed!",
return -1); return -1);
...@@ -172,9 +172,9 @@ static int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr) ...@@ -172,9 +172,9 @@ static int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr)
static int static int
polaris10_avfs_event_mgr(struct pp_smumgr *smumgr, bool SMU_VFT_INTACT) polaris10_avfs_event_mgr(struct pp_hwmgr *hwmgr, bool SMU_VFT_INTACT)
{ {
struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend); struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend);
switch (smu_data->avfs.avfs_btc_status) { switch (smu_data->avfs.avfs_btc_status) {
case AVFS_BTC_COMPLETED_PREVIOUSLY: case AVFS_BTC_COMPLETED_PREVIOUSLY:
...@@ -183,20 +183,20 @@ polaris10_avfs_event_mgr(struct pp_smumgr *smumgr, bool SMU_VFT_INTACT) ...@@ -183,20 +183,20 @@ polaris10_avfs_event_mgr(struct pp_smumgr *smumgr, bool SMU_VFT_INTACT)
case AVFS_BTC_BOOT: /* Cold Boot State - Post SMU Start */ case AVFS_BTC_BOOT: /* Cold Boot State - Post SMU Start */
smu_data->avfs.avfs_btc_status = AVFS_BTC_DPMTABLESETUP_FAILED; smu_data->avfs.avfs_btc_status = AVFS_BTC_DPMTABLESETUP_FAILED;
PP_ASSERT_WITH_CODE(0 == polaris10_setup_graphics_level_structure(smumgr), PP_ASSERT_WITH_CODE(0 == polaris10_setup_graphics_level_structure(hwmgr),
"[AVFS][Polaris10_AVFSEventMgr] Could not Copy Graphics Level table over to SMU", "[AVFS][Polaris10_AVFSEventMgr] Could not Copy Graphics Level table over to SMU",
return -EINVAL); return -EINVAL);
if (smu_data->avfs.avfs_btc_param > 1) { if (smu_data->avfs.avfs_btc_param > 1) {
pr_info("[AVFS][Polaris10_AVFSEventMgr] AC BTC has not been successfully verified on Fiji. There may be in this setting."); pr_info("[AVFS][Polaris10_AVFSEventMgr] AC BTC has not been successfully verified on Fiji. There may be in this setting.");
smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL; smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL;
PP_ASSERT_WITH_CODE(0 == polaris10_setup_pwr_virus(smumgr), PP_ASSERT_WITH_CODE(0 == polaris10_setup_pwr_virus(hwmgr),
"[AVFS][Polaris10_AVFSEventMgr] Could not setup Pwr Virus for AVFS ", "[AVFS][Polaris10_AVFSEventMgr] Could not setup Pwr Virus for AVFS ",
return -EINVAL); return -EINVAL);
} }
smu_data->avfs.avfs_btc_status = AVFS_BTC_FAILED; smu_data->avfs.avfs_btc_status = AVFS_BTC_FAILED;
PP_ASSERT_WITH_CODE(0 == polaris10_perform_btc(smumgr), PP_ASSERT_WITH_CODE(0 == polaris10_perform_btc(hwmgr),
"[AVFS][Polaris10_AVFSEventMgr] Failure at SmuPolaris10_PerformBTC. AVFS Disabled", "[AVFS][Polaris10_AVFSEventMgr] Failure at SmuPolaris10_PerformBTC. AVFS Disabled",
return -EINVAL); return -EINVAL);
smu_data->avfs.avfs_btc_status = AVFS_BTC_ENABLEAVFS; smu_data->avfs.avfs_btc_status = AVFS_BTC_ENABLEAVFS;
...@@ -215,7 +215,7 @@ polaris10_avfs_event_mgr(struct pp_smumgr *smumgr, bool SMU_VFT_INTACT) ...@@ -215,7 +215,7 @@ polaris10_avfs_event_mgr(struct pp_smumgr *smumgr, bool SMU_VFT_INTACT)
return 0; return 0;
} }
static int polaris10_start_smu_in_protection_mode(struct pp_smumgr *smumgr) static int polaris10_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr)
{ {
int result = 0; int result = 0;
...@@ -223,138 +223,138 @@ static int polaris10_start_smu_in_protection_mode(struct pp_smumgr *smumgr) ...@@ -223,138 +223,138 @@ static int polaris10_start_smu_in_protection_mode(struct pp_smumgr *smumgr)
/* SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0) */ /* SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0) */
/* Assert reset */ /* Assert reset */
SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_RESET_CNTL, rst_reg, 1); SMC_SYSCON_RESET_CNTL, rst_reg, 1);
result = smu7_upload_smu_firmware_image(smumgr); result = smu7_upload_smu_firmware_image(hwmgr);
if (result != 0) if (result != 0)
return result; return result;
/* Clear status */ /* Clear status */
cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0); cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0);
SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
/* De-assert reset */ /* De-assert reset */
SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_RESET_CNTL, rst_reg, 0); SMC_SYSCON_RESET_CNTL, rst_reg, 0);
SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1); SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1);
/* Call Test SMU message with 0x20000 offset to trigger SMU start */ /* Call Test SMU message with 0x20000 offset to trigger SMU start */
smu7_send_msg_to_smc_offset(smumgr); smu7_send_msg_to_smc_offset(hwmgr);
/* Wait done bit to be set */ /* Wait done bit to be set */
/* Check pass/failed indicator */ /* Check pass/failed indicator */
SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, SMU_STATUS, SMU_DONE, 0); SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, SMU_STATUS, SMU_DONE, 0);
if (1 != SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, if (1 != SMUM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMU_STATUS, SMU_PASS)) SMU_STATUS, SMU_PASS))
PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return -1); PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return -1);
cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0); cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0);
SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_RESET_CNTL, rst_reg, 1); SMC_SYSCON_RESET_CNTL, rst_reg, 1);
SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_RESET_CNTL, rst_reg, 0); SMC_SYSCON_RESET_CNTL, rst_reg, 0);
/* Wait for firmware to initialize */ /* Wait for firmware to initialize */
SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1); SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
return result; return result;
} }
static int polaris10_start_smu_in_non_protection_mode(struct pp_smumgr *smumgr) static int polaris10_start_smu_in_non_protection_mode(struct pp_hwmgr *hwmgr)
{ {
int result = 0; int result = 0;
/* wait for smc boot up */ /* wait for smc boot up */
SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0); SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0);
/* Clear firmware interrupt enable flag */ /* Clear firmware interrupt enable flag */
/* SMUM_WRITE_VFPF_INDIRECT_FIELD(pSmuMgr, SMC_IND, SMC_SYSCON_MISC_CNTL, pre_fetcher_en, 1); */ /* SMUM_WRITE_VFPF_INDIRECT_FIELD(pSmuMgr, SMC_IND, SMC_SYSCON_MISC_CNTL, pre_fetcher_en, 1); */
cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
ixFIRMWARE_FLAGS, 0); ixFIRMWARE_FLAGS, 0);
SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_RESET_CNTL, SMC_SYSCON_RESET_CNTL,
rst_reg, 1); rst_reg, 1);
result = smu7_upload_smu_firmware_image(smumgr); result = smu7_upload_smu_firmware_image(hwmgr);
if (result != 0) if (result != 0)
return result; return result;
/* Set smc instruct start point at 0x0 */ /* Set smc instruct start point at 0x0 */
smu7_program_jump_on_start(smumgr); smu7_program_jump_on_start(hwmgr);
SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_RESET_CNTL, rst_reg, 0); SMC_SYSCON_RESET_CNTL, rst_reg, 0);
/* Wait for firmware to initialize */ /* Wait for firmware to initialize */
SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1); FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
return result; return result;
} }
static int polaris10_start_smu(struct pp_smumgr *smumgr) static int polaris10_start_smu(struct pp_hwmgr *hwmgr)
{ {
int result = 0; int result = 0;
struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
bool SMU_VFT_INTACT; bool SMU_VFT_INTACT;
/* Only start SMC if SMC RAM is not running */ /* Only start SMC if SMC RAM is not running */
if (!smu7_is_smc_ram_running(smumgr)) { if (!smu7_is_smc_ram_running(hwmgr)) {
SMU_VFT_INTACT = false; SMU_VFT_INTACT = false;
smu_data->protected_mode = (uint8_t) (SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE)); smu_data->protected_mode = (uint8_t) (SMUM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE));
smu_data->smu7_data.security_hard_key = (uint8_t) (SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL)); smu_data->smu7_data.security_hard_key = (uint8_t) (SMUM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL));
/* Check if SMU is running in protected mode */ /* Check if SMU is running in protected mode */
if (smu_data->protected_mode == 0) { if (smu_data->protected_mode == 0) {
result = polaris10_start_smu_in_non_protection_mode(smumgr); result = polaris10_start_smu_in_non_protection_mode(hwmgr);
} else { } else {
result = polaris10_start_smu_in_protection_mode(smumgr); result = polaris10_start_smu_in_protection_mode(hwmgr);
/* If failed, try with different security Key. */ /* If failed, try with different security Key. */
if (result != 0) { if (result != 0) {
smu_data->smu7_data.security_hard_key ^= 1; smu_data->smu7_data.security_hard_key ^= 1;
cgs_rel_firmware(smumgr->device, CGS_UCODE_ID_SMU); cgs_rel_firmware(hwmgr->device, CGS_UCODE_ID_SMU);
result = polaris10_start_smu_in_protection_mode(smumgr); result = polaris10_start_smu_in_protection_mode(hwmgr);
} }
} }
if (result != 0) if (result != 0)
PP_ASSERT_WITH_CODE(0, "Failed to load SMU ucode.", return result); PP_ASSERT_WITH_CODE(0, "Failed to load SMU ucode.", return result);
polaris10_avfs_event_mgr(smumgr, true); polaris10_avfs_event_mgr(hwmgr, true);
} else } else
SMU_VFT_INTACT = true; /*Driver went offline but SMU was still alive and contains the VFT table */ SMU_VFT_INTACT = true; /*Driver went offline but SMU was still alive and contains the VFT table */
polaris10_avfs_event_mgr(smumgr, SMU_VFT_INTACT); polaris10_avfs_event_mgr(hwmgr, SMU_VFT_INTACT);
/* Setup SoftRegsStart here for register lookup in case DummyBackEnd is used and ProcessFirmwareHeader is not executed */ /* Setup SoftRegsStart here for register lookup in case DummyBackEnd is used and ProcessFirmwareHeader is not executed */
smu7_read_smc_sram_dword(smumgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, SoftRegisters), smu7_read_smc_sram_dword(hwmgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, SoftRegisters),
&(smu_data->smu7_data.soft_regs_start), 0x40000); &(smu_data->smu7_data.soft_regs_start), 0x40000);
result = smu7_request_smu_load_fw(smumgr); result = smu7_request_smu_load_fw(hwmgr);
return result; return result;
} }
static bool polaris10_is_hw_avfs_present(struct pp_smumgr *smumgr) static bool polaris10_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
{ {
uint32_t efuse; uint32_t efuse;
efuse = cgs_read_ind_register(smumgr->device, CGS_IND_REG__SMC, ixSMU_EFUSE_0 + (49*4)); efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_EFUSE_0 + (49*4));
efuse &= 0x00000001; efuse &= 0x00000001;
if (efuse) if (efuse)
return true; return true;
...@@ -362,7 +362,7 @@ static bool polaris10_is_hw_avfs_present(struct pp_smumgr *smumgr) ...@@ -362,7 +362,7 @@ static bool polaris10_is_hw_avfs_present(struct pp_smumgr *smumgr)
return false; return false;
} }
static int polaris10_smu_init(struct pp_smumgr *smumgr) static int polaris10_smu_init(struct pp_hwmgr *hwmgr)
{ {
struct polaris10_smumgr *smu_data; struct polaris10_smumgr *smu_data;
int i; int i;
...@@ -371,9 +371,9 @@ static int polaris10_smu_init(struct pp_smumgr *smumgr) ...@@ -371,9 +371,9 @@ static int polaris10_smu_init(struct pp_smumgr *smumgr)
if (smu_data == NULL) if (smu_data == NULL)
return -ENOMEM; return -ENOMEM;
smumgr->backend = smu_data; hwmgr->smumgr->backend = smu_data;
if (smu7_init(smumgr)) if (smu7_init(hwmgr))
return -EINVAL; return -EINVAL;
for (i = 0; i < SMU74_MAX_LEVELS_GRAPHICS; i++) for (i = 0; i < SMU74_MAX_LEVELS_GRAPHICS; i++)
......
drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
浏览文件 @ d3f8c0ab
...@@ -48,20 +48,20 @@ ...@@ -48,20 +48,20 @@
#define smnMP1_FIRMWARE_FLAGS 0x3010028 #define smnMP1_FIRMWARE_FLAGS 0x3010028
bool rv_is_smc_ram_running(struct pp_smumgr *smumgr) bool rv_is_smc_ram_running(struct pp_hwmgr *hwmgr)
{ {
uint32_t mp1_fw_flags, reg; uint32_t mp1_fw_flags, reg;
reg = soc15_get_register_offset(NBIF_HWID, 0, reg = soc15_get_register_offset(NBIF_HWID, 0,
mmPCIE_INDEX2_BASE_IDX, mmPCIE_INDEX2); mmPCIE_INDEX2_BASE_IDX, mmPCIE_INDEX2);
cgs_write_register(smumgr->device, reg, cgs_write_register(hwmgr->device, reg,
(MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff))); (MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff)));
reg = soc15_get_register_offset(NBIF_HWID, 0, reg = soc15_get_register_offset(NBIF_HWID, 0,
mmPCIE_DATA2_BASE_IDX, mmPCIE_DATA2); mmPCIE_DATA2_BASE_IDX, mmPCIE_DATA2);
mp1_fw_flags = cgs_read_register(smumgr->device, reg); mp1_fw_flags = cgs_read_register(hwmgr->device, reg);
if (mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) if (mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK)
return true; return true;
...@@ -69,97 +69,97 @@ bool rv_is_smc_ram_running(struct pp_smumgr *smumgr) ...@@ -69,97 +69,97 @@ bool rv_is_smc_ram_running(struct pp_smumgr *smumgr)
return false; return false;
} }
static uint32_t rv_wait_for_response(struct pp_smumgr *smumgr) static uint32_t rv_wait_for_response(struct pp_hwmgr *hwmgr)
{ {
uint32_t reg; uint32_t reg;
if (!rv_is_smc_ram_running(smumgr)) if (!rv_is_smc_ram_running(hwmgr))
return -EINVAL; return -EINVAL;
reg = soc15_get_register_offset(MP1_HWID, 0, reg = soc15_get_register_offset(MP1_HWID, 0,
mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90); mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
smum_wait_for_register_unequal(smumgr, reg, smum_wait_for_register_unequal(hwmgr, reg,
0, MP1_C2PMSG_90__CONTENT_MASK); 0, MP1_C2PMSG_90__CONTENT_MASK);
return cgs_read_register(smumgr->device, reg); return cgs_read_register(hwmgr->device, reg);
} }
int rv_send_msg_to_smc_without_waiting(struct pp_smumgr *smumgr, int rv_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr,
uint16_t msg) uint16_t msg)
{ {
uint32_t reg; uint32_t reg;
if (!rv_is_smc_ram_running(smumgr)) if (!rv_is_smc_ram_running(hwmgr))
return -EINVAL; return -EINVAL;
reg = soc15_get_register_offset(MP1_HWID, 0, reg = soc15_get_register_offset(MP1_HWID, 0,
mmMP1_SMN_C2PMSG_66_BASE_IDX, mmMP1_SMN_C2PMSG_66); mmMP1_SMN_C2PMSG_66_BASE_IDX, mmMP1_SMN_C2PMSG_66);
cgs_write_register(smumgr->device, reg, msg); cgs_write_register(hwmgr->device, reg, msg);
return 0; return 0;
} }
int rv_read_arg_from_smc(struct pp_smumgr *smumgr, uint32_t *arg) int rv_read_arg_from_smc(struct pp_hwmgr *hwmgr, uint32_t *arg)
{ {
uint32_t reg; uint32_t reg;
reg = soc15_get_register_offset(MP1_HWID, 0, reg = soc15_get_register_offset(MP1_HWID, 0,
mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82); mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82);
*arg = cgs_read_register(smumgr->device, reg); *arg = cgs_read_register(hwmgr->device, reg);
return 0; return 0;
} }
int rv_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg) int rv_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
{ {
uint32_t reg; uint32_t reg;
rv_wait_for_response(smumgr); rv_wait_for_response(hwmgr);
reg = soc15_get_register_offset(MP1_HWID, 0, reg = soc15_get_register_offset(MP1_HWID, 0,
mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90); mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
cgs_write_register(smumgr->device, reg, 0); cgs_write_register(hwmgr->device, reg, 0);
rv_send_msg_to_smc_without_waiting(smumgr, msg); rv_send_msg_to_smc_without_waiting(hwmgr, msg);
if (rv_wait_for_response(smumgr) == 0) if (rv_wait_for_response(hwmgr) == 0)
printk("Failed to send Message %x.\n", msg); printk("Failed to send Message %x.\n", msg);
return 0; return 0;
} }
int rv_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, int rv_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
uint16_t msg, uint32_t parameter) uint16_t msg, uint32_t parameter)
{ {
uint32_t reg; uint32_t reg;
rv_wait_for_response(smumgr); rv_wait_for_response(hwmgr);
reg = soc15_get_register_offset(MP1_HWID, 0, reg = soc15_get_register_offset(MP1_HWID, 0,
mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90); mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
cgs_write_register(smumgr->device, reg, 0); cgs_write_register(hwmgr->device, reg, 0);
reg = soc15_get_register_offset(MP1_HWID, 0, reg = soc15_get_register_offset(MP1_HWID, 0,
mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82); mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82);
cgs_write_register(smumgr->device, reg, parameter); cgs_write_register(hwmgr->device, reg, parameter);
rv_send_msg_to_smc_without_waiting(smumgr, msg); rv_send_msg_to_smc_without_waiting(hwmgr, msg);
if (rv_wait_for_response(smumgr) == 0) if (rv_wait_for_response(hwmgr) == 0)
printk("Failed to send Message %x.\n", msg); printk("Failed to send Message %x.\n", msg);
return 0; return 0;
} }
int rv_copy_table_from_smc(struct pp_smumgr *smumgr, int rv_copy_table_from_smc(struct pp_hwmgr *hwmgr,
uint8_t *table, int16_t table_id) uint8_t *table, int16_t table_id)
{ {
struct rv_smumgr *priv = struct rv_smumgr *priv =
(struct rv_smumgr *)(smumgr->backend); (struct rv_smumgr *)(hwmgr->smumgr->backend);
PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE, PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
"Invalid SMU Table ID!", return -EINVAL;); "Invalid SMU Table ID!", return -EINVAL;);
...@@ -167,16 +167,16 @@ int rv_copy_table_from_smc(struct pp_smumgr *smumgr, ...@@ -167,16 +167,16 @@ int rv_copy_table_from_smc(struct pp_smumgr *smumgr,
"Invalid SMU Table version!", return -EINVAL;); "Invalid SMU Table version!", return -EINVAL;);
PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0, PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
"Invalid SMU Table Length!", return -EINVAL;); "Invalid SMU Table Length!", return -EINVAL;);
PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr, PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh,
priv->smu_tables.entry[table_id].table_addr_high) == 0, priv->smu_tables.entry[table_id].table_addr_high) == 0,
"[CopyTableFromSMC] Attempt to Set Dram Addr High Failed!", return -EINVAL;); "[CopyTableFromSMC] Attempt to Set Dram Addr High Failed!", return -EINVAL;);
PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr, PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow,
priv->smu_tables.entry[table_id].table_addr_low) == 0, priv->smu_tables.entry[table_id].table_addr_low) == 0,
"[CopyTableFromSMC] Attempt to Set Dram Addr Low Failed!", "[CopyTableFromSMC] Attempt to Set Dram Addr Low Failed!",
return -EINVAL;); return -EINVAL;);
PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr, PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram,
priv->smu_tables.entry[table_id].table_id) == 0, priv->smu_tables.entry[table_id].table_id) == 0,
"[CopyTableFromSMC] Attempt to Transfer Table From SMU Failed!", "[CopyTableFromSMC] Attempt to Transfer Table From SMU Failed!",
...@@ -188,11 +188,11 @@ int rv_copy_table_from_smc(struct pp_smumgr *smumgr, ...@@ -188,11 +188,11 @@ int rv_copy_table_from_smc(struct pp_smumgr *smumgr,
return 0; return 0;
} }
int rv_copy_table_to_smc(struct pp_smumgr *smumgr, int rv_copy_table_to_smc(struct pp_hwmgr *hwmgr,
uint8_t *table, int16_t table_id) uint8_t *table, int16_t table_id)
{ {
struct rv_smumgr *priv = struct rv_smumgr *priv =
(struct rv_smumgr *)(smumgr->backend); (struct rv_smumgr *)(hwmgr->smumgr->backend);
PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE, PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
"Invalid SMU Table ID!", return -EINVAL;); "Invalid SMU Table ID!", return -EINVAL;);
...@@ -204,17 +204,17 @@ int rv_copy_table_to_smc(struct pp_smumgr *smumgr, ...@@ -204,17 +204,17 @@ int rv_copy_table_to_smc(struct pp_smumgr *smumgr,
memcpy(priv->smu_tables.entry[table_id].table, table, memcpy(priv->smu_tables.entry[table_id].table, table,
priv->smu_tables.entry[table_id].size); priv->smu_tables.entry[table_id].size);
PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr, PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh,
priv->smu_tables.entry[table_id].table_addr_high) == 0, priv->smu_tables.entry[table_id].table_addr_high) == 0,
"[CopyTableToSMC] Attempt to Set Dram Addr High Failed!", "[CopyTableToSMC] Attempt to Set Dram Addr High Failed!",
return -EINVAL;); return -EINVAL;);
PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr, PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow,
priv->smu_tables.entry[table_id].table_addr_low) == 0, priv->smu_tables.entry[table_id].table_addr_low) == 0,
"[CopyTableToSMC] Attempt to Set Dram Addr Low Failed!", "[CopyTableToSMC] Attempt to Set Dram Addr Low Failed!",
return -EINVAL;); return -EINVAL;);
PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr, PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu,
priv->smu_tables.entry[table_id].table_id) == 0, priv->smu_tables.entry[table_id].table_id) == 0,
"[CopyTableToSMC] Attempt to Transfer Table To SMU Failed!", "[CopyTableToSMC] Attempt to Transfer Table To SMU Failed!",
...@@ -223,15 +223,15 @@ int rv_copy_table_to_smc(struct pp_smumgr *smumgr, ...@@ -223,15 +223,15 @@ int rv_copy_table_to_smc(struct pp_smumgr *smumgr,
return 0; return 0;
} }
static int rv_verify_smc_interface(struct pp_smumgr *smumgr) static int rv_verify_smc_interface(struct pp_hwmgr *hwmgr)
{ {
uint32_t smc_driver_if_version; uint32_t smc_driver_if_version;
PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc(smumgr, PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc(hwmgr,
PPSMC_MSG_GetDriverIfVersion), PPSMC_MSG_GetDriverIfVersion),
"Attempt to get SMC IF Version Number Failed!", "Attempt to get SMC IF Version Number Failed!",
return -EINVAL); return -EINVAL);
PP_ASSERT_WITH_CODE(!rv_read_arg_from_smc(smumgr, PP_ASSERT_WITH_CODE(!rv_read_arg_from_smc(hwmgr,
&smc_driver_if_version), &smc_driver_if_version),
"Attempt to read SMC IF Version Number Failed!", "Attempt to read SMC IF Version Number Failed!",
return -EINVAL); return -EINVAL);
...@@ -243,9 +243,9 @@ static int rv_verify_smc_interface(struct pp_smumgr *smumgr) ...@@ -243,9 +243,9 @@ static int rv_verify_smc_interface(struct pp_smumgr *smumgr)
} }
/* sdma is disabled by default in vbios, need to re-enable in driver */ /* sdma is disabled by default in vbios, need to re-enable in driver */
static int rv_smc_enable_sdma(struct pp_smumgr *smumgr) static int rv_smc_enable_sdma(struct pp_hwmgr *hwmgr)
{ {
PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc(smumgr, PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc(hwmgr,
PPSMC_MSG_PowerUpSdma), PPSMC_MSG_PowerUpSdma),
"Attempt to power up sdma Failed!", "Attempt to power up sdma Failed!",
return -EINVAL); return -EINVAL);
...@@ -253,9 +253,9 @@ static int rv_smc_enable_sdma(struct pp_smumgr *smumgr) ...@@ -253,9 +253,9 @@ static int rv_smc_enable_sdma(struct pp_smumgr *smumgr)
return 0; return 0;
} }
static int rv_smc_disable_sdma(struct pp_smumgr *smumgr) static int rv_smc_disable_sdma(struct pp_hwmgr *hwmgr)
{ {
PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc(smumgr, PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc(hwmgr,
PPSMC_MSG_PowerDownSdma), PPSMC_MSG_PowerDownSdma),
"Attempt to power down sdma Failed!", "Attempt to power down sdma Failed!",
return -EINVAL); return -EINVAL);
...@@ -264,9 +264,9 @@ static int rv_smc_disable_sdma(struct pp_smumgr *smumgr) ...@@ -264,9 +264,9 @@ static int rv_smc_disable_sdma(struct pp_smumgr *smumgr)
} }
/* vcn is disabled by default in vbios, need to re-enable in driver */ /* vcn is disabled by default in vbios, need to re-enable in driver */
static int rv_smc_enable_vcn(struct pp_smumgr *smumgr) static int rv_smc_enable_vcn(struct pp_hwmgr *hwmgr)
{ {
PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc_with_parameter(smumgr, PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_PowerUpVcn, 0), PPSMC_MSG_PowerUpVcn, 0),
"Attempt to power up vcn Failed!", "Attempt to power up vcn Failed!",
return -EINVAL); return -EINVAL);
...@@ -274,9 +274,9 @@ static int rv_smc_enable_vcn(struct pp_smumgr *smumgr) ...@@ -274,9 +274,9 @@ static int rv_smc_enable_vcn(struct pp_smumgr *smumgr)
return 0; return 0;
} }
static int rv_smc_disable_vcn(struct pp_smumgr *smumgr) static int rv_smc_disable_vcn(struct pp_hwmgr *hwmgr)
{ {
PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc_with_parameter(smumgr, PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_PowerDownVcn, 0), PPSMC_MSG_PowerDownVcn, 0),
"Attempt to power down vcn Failed!", "Attempt to power down vcn Failed!",
return -EINVAL); return -EINVAL);
...@@ -284,38 +284,38 @@ static int rv_smc_disable_vcn(struct pp_smumgr *smumgr) ...@@ -284,38 +284,38 @@ static int rv_smc_disable_vcn(struct pp_smumgr *smumgr)
return 0; return 0;
} }
static int rv_smu_fini(struct pp_smumgr *smumgr) static int rv_smu_fini(struct pp_hwmgr *hwmgr)
{ {
struct rv_smumgr *priv = struct rv_smumgr *priv =
(struct rv_smumgr *)(smumgr->backend); (struct rv_smumgr *)(hwmgr->smumgr->backend);
if (priv) { if (priv) {
rv_smc_disable_sdma(smumgr); rv_smc_disable_sdma(hwmgr);
rv_smc_disable_vcn(smumgr); rv_smc_disable_vcn(hwmgr);
cgs_free_gpu_mem(smumgr->device, cgs_free_gpu_mem(hwmgr->device,
priv->smu_tables.entry[WMTABLE].handle); priv->smu_tables.entry[WMTABLE].handle);
cgs_free_gpu_mem(smumgr->device, cgs_free_gpu_mem(hwmgr->device,
priv->smu_tables.entry[CLOCKTABLE].handle); priv->smu_tables.entry[CLOCKTABLE].handle);
kfree(smumgr->backend); kfree(hwmgr->smumgr->backend);
smumgr->backend = NULL; hwmgr->smumgr->backend = NULL;
} }
return 0; return 0;
} }
static int rv_start_smu(struct pp_smumgr *smumgr) static int rv_start_smu(struct pp_hwmgr *hwmgr)
{ {
if (rv_verify_smc_interface(smumgr)) if (rv_verify_smc_interface(hwmgr))
return -EINVAL; return -EINVAL;
if (rv_smc_enable_sdma(smumgr)) if (rv_smc_enable_sdma(hwmgr))
return -EINVAL; return -EINVAL;
if (rv_smc_enable_vcn(smumgr)) if (rv_smc_enable_vcn(hwmgr))
return -EINVAL; return -EINVAL;
return 0; return 0;
} }
static int rv_smu_init(struct pp_smumgr *smumgr) static int rv_smu_init(struct pp_hwmgr *hwmgr)
{ {
struct rv_smumgr *priv; struct rv_smumgr *priv;
uint64_t mc_addr; uint64_t mc_addr;
...@@ -327,10 +327,10 @@ static int rv_smu_init(struct pp_smumgr *smumgr) ...@@ -327,10 +327,10 @@ static int rv_smu_init(struct pp_smumgr *smumgr)
if (!priv) if (!priv)
return -ENOMEM; return -ENOMEM;
smumgr->backend = priv; hwmgr->smumgr->backend = priv;
/* allocate space for watermarks table */ /* allocate space for watermarks table */
smu_allocate_memory(smumgr->device, smu_allocate_memory(hwmgr->device,
sizeof(Watermarks_t), sizeof(Watermarks_t),
CGS_GPU_MEM_TYPE__GART_CACHEABLE, CGS_GPU_MEM_TYPE__GART_CACHEABLE,
PAGE_SIZE, PAGE_SIZE,
...@@ -340,8 +340,8 @@ static int rv_smu_init(struct pp_smumgr *smumgr) ...@@ -340,8 +340,8 @@ static int rv_smu_init(struct pp_smumgr *smumgr)
PP_ASSERT_WITH_CODE(kaddr, PP_ASSERT_WITH_CODE(kaddr,
"[rv_smu_init] Out of memory for wmtable.", "[rv_smu_init] Out of memory for wmtable.",
kfree(smumgr->backend); kfree(hwmgr->smumgr->backend);
smumgr->backend = NULL; hwmgr->smumgr->backend = NULL;
return -EINVAL); return -EINVAL);
priv->smu_tables.entry[WMTABLE].version = 0x01; priv->smu_tables.entry[WMTABLE].version = 0x01;
...@@ -355,7 +355,7 @@ static int rv_smu_init(struct pp_smumgr *smumgr) ...@@ -355,7 +355,7 @@ static int rv_smu_init(struct pp_smumgr *smumgr)
priv->smu_tables.entry[WMTABLE].handle = handle; priv->smu_tables.entry[WMTABLE].handle = handle;
/* allocate space for watermarks table */ /* allocate space for watermarks table */
smu_allocate_memory(smumgr->device, smu_allocate_memory(hwmgr->device,
sizeof(DpmClocks_t), sizeof(DpmClocks_t),
CGS_GPU_MEM_TYPE__GART_CACHEABLE, CGS_GPU_MEM_TYPE__GART_CACHEABLE,
PAGE_SIZE, PAGE_SIZE,
...@@ -365,10 +365,10 @@ static int rv_smu_init(struct pp_smumgr *smumgr) ...@@ -365,10 +365,10 @@ static int rv_smu_init(struct pp_smumgr *smumgr)
PP_ASSERT_WITH_CODE(kaddr, PP_ASSERT_WITH_CODE(kaddr,
"[rv_smu_init] Out of memory for CLOCKTABLE.", "[rv_smu_init] Out of memory for CLOCKTABLE.",
cgs_free_gpu_mem(smumgr->device, cgs_free_gpu_mem(hwmgr->device,
(cgs_handle_t)priv->smu_tables.entry[WMTABLE].handle); (cgs_handle_t)priv->smu_tables.entry[WMTABLE].handle);
kfree(smumgr->backend); kfree(hwmgr->smumgr->backend);
smumgr->backend = NULL; hwmgr->smumgr->backend = NULL;
return -EINVAL); return -EINVAL);
priv->smu_tables.entry[CLOCKTABLE].version = 0x01; priv->smu_tables.entry[CLOCKTABLE].version = 0x01;
......
drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.h
浏览文件 @ d3f8c0ab
...@@ -51,11 +51,11 @@ struct rv_smumgr { ...@@ -51,11 +51,11 @@ struct rv_smumgr {
struct smu_table_array smu_tables; struct smu_table_array smu_tables;
}; };
int rv_read_arg_from_smc(struct pp_smumgr *smumgr, uint32_t *arg); int rv_read_arg_from_smc(struct pp_hwmgr *hwmgr, uint32_t *arg);
bool rv_is_smc_ram_running(struct pp_smumgr *smumgr); bool rv_is_smc_ram_running(struct pp_hwmgr *hwmgr);
int rv_copy_table_from_smc(struct pp_smumgr *smumgr, int rv_copy_table_from_smc(struct pp_hwmgr *hwmgr,
uint8_t *table, int16_t table_id); uint8_t *table, int16_t table_id);
int rv_copy_table_to_smc(struct pp_smumgr *smumgr, int rv_copy_table_to_smc(struct pp_hwmgr *hwmgr,
uint8_t *table, int16_t table_id); uint8_t *table, int16_t table_id);
......
drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
浏览文件 @ d3f8c0ab
...@@ -34,18 +34,18 @@ ...@@ -34,18 +34,18 @@
#define SMU7_SMC_SIZE 0x20000 #define SMU7_SMC_SIZE 0x20000
static int smu7_set_smc_sram_address(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t limit) static int smu7_set_smc_sram_address(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_t limit)
{ {
PP_ASSERT_WITH_CODE((0 == (3 & smc_addr)), "SMC address must be 4 byte aligned.", return -EINVAL); PP_ASSERT_WITH_CODE((0 == (3 & smc_addr)), "SMC address must be 4 byte aligned.", return -EINVAL);
PP_ASSERT_WITH_CODE((limit > (smc_addr + 3)), "SMC addr is beyond the SMC RAM area.", return -EINVAL); PP_ASSERT_WITH_CODE((limit > (smc_addr + 3)), "SMC addr is beyond the SMC RAM area.", return -EINVAL);
cgs_write_register(smumgr->device, mmSMC_IND_INDEX_11, smc_addr); cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_11, smc_addr);
SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0); /* on ci, SMC_IND_ACCESS_CNTL is different */ SMUM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0); /* on ci, SMC_IND_ACCESS_CNTL is different */
return 0; return 0;
} }
int smu7_copy_bytes_from_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address, uint32_t *dest, uint32_t byte_count, uint32_t limit) int smu7_copy_bytes_from_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address, uint32_t *dest, uint32_t byte_count, uint32_t limit)
{ {
uint32_t data; uint32_t data;
uint32_t addr; uint32_t addr;
...@@ -59,7 +59,7 @@ int smu7_copy_bytes_from_smc(struct pp_smumgr *smumgr, uint32_t smc_start_addres ...@@ -59,7 +59,7 @@ int smu7_copy_bytes_from_smc(struct pp_smumgr *smumgr, uint32_t smc_start_addres
addr = smc_start_address; addr = smc_start_address;
while (byte_count >= 4) { while (byte_count >= 4) {
smu7_read_smc_sram_dword(smumgr, addr, &data, limit); smu7_read_smc_sram_dword(hwmgr, addr, &data, limit);
*dest = PP_SMC_TO_HOST_UL(data); *dest = PP_SMC_TO_HOST_UL(data);
...@@ -69,7 +69,7 @@ int smu7_copy_bytes_from_smc(struct pp_smumgr *smumgr, uint32_t smc_start_addres ...@@ -69,7 +69,7 @@ int smu7_copy_bytes_from_smc(struct pp_smumgr *smumgr, uint32_t smc_start_addres
} }
if (byte_count) { if (byte_count) {
smu7_read_smc_sram_dword(smumgr, addr, &data, limit); smu7_read_smc_sram_dword(hwmgr, addr, &data, limit);
*pdata = PP_SMC_TO_HOST_UL(data); *pdata = PP_SMC_TO_HOST_UL(data);
/* Cast dest into byte type in dest_byte. This way, we don't overflow if the allocated memory is not 4-byte aligned. */ /* Cast dest into byte type in dest_byte. This way, we don't overflow if the allocated memory is not 4-byte aligned. */
dest_byte = (uint8_t *)dest; dest_byte = (uint8_t *)dest;
...@@ -81,7 +81,7 @@ int smu7_copy_bytes_from_smc(struct pp_smumgr *smumgr, uint32_t smc_start_addres ...@@ -81,7 +81,7 @@ int smu7_copy_bytes_from_smc(struct pp_smumgr *smumgr, uint32_t smc_start_addres
} }
int smu7_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address, int smu7_copy_bytes_to_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address,
const uint8_t *src, uint32_t byte_count, uint32_t limit) const uint8_t *src, uint32_t byte_count, uint32_t limit)
{ {
int result; int result;
...@@ -99,12 +99,12 @@ int smu7_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address, ...@@ -99,12 +99,12 @@ int smu7_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address,
/* Bytes are written into the SMC addres space with the MSB first. */ /* Bytes are written into the SMC addres space with the MSB first. */
data = src[0] * 0x1000000 + src[1] * 0x10000 + src[2] * 0x100 + src[3]; data = src[0] * 0x1000000 + src[1] * 0x10000 + src[2] * 0x100 + src[3];
result = smu7_set_smc_sram_address(smumgr, addr, limit); result = smu7_set_smc_sram_address(hwmgr, addr, limit);
if (0 != result) if (0 != result)
return result; return result;
cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, data); cgs_write_register(hwmgr->device, mmSMC_IND_DATA_11, data);
src += 4; src += 4;
byte_count -= 4; byte_count -= 4;
...@@ -115,13 +115,13 @@ int smu7_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address, ...@@ -115,13 +115,13 @@ int smu7_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address,
data = 0; data = 0;
result = smu7_set_smc_sram_address(smumgr, addr, limit); result = smu7_set_smc_sram_address(hwmgr, addr, limit);
if (0 != result) if (0 != result)
return result; return result;
original_data = cgs_read_register(smumgr->device, mmSMC_IND_DATA_11); original_data = cgs_read_register(hwmgr->device, mmSMC_IND_DATA_11);
extra_shift = 8 * (4 - byte_count); extra_shift = 8 * (4 - byte_count);
...@@ -135,53 +135,53 @@ int smu7_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address, ...@@ -135,53 +135,53 @@ int smu7_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address,
data |= (original_data & ~((~0UL) << extra_shift)); data |= (original_data & ~((~0UL) << extra_shift));
result = smu7_set_smc_sram_address(smumgr, addr, limit); result = smu7_set_smc_sram_address(hwmgr, addr, limit);
if (0 != result) if (0 != result)
return result; return result;
cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, data); cgs_write_register(hwmgr->device, mmSMC_IND_DATA_11, data);
} }
return 0; return 0;
} }
int smu7_program_jump_on_start(struct pp_smumgr *smumgr) int smu7_program_jump_on_start(struct pp_hwmgr *hwmgr)
{ {
static const unsigned char data[4] = { 0xE0, 0x00, 0x80, 0x40 }; static const unsigned char data[4] = { 0xE0, 0x00, 0x80, 0x40 };
smu7_copy_bytes_to_smc(smumgr, 0x0, data, 4, sizeof(data)+1); smu7_copy_bytes_to_smc(hwmgr, 0x0, data, 4, sizeof(data)+1);
return 0; return 0;
} }
bool smu7_is_smc_ram_running(struct pp_smumgr *smumgr) bool smu7_is_smc_ram_running(struct pp_hwmgr *hwmgr)
{ {
return ((0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable)) return ((0 == SMUM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable))
&& (0x20100 <= cgs_read_ind_register(smumgr->device, CGS_IND_REG__SMC, ixSMC_PC_C))); && (0x20100 <= cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMC_PC_C)));
} }
int smu7_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg) int smu7_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
{ {
int ret; int ret;
if (!smu7_is_smc_ram_running(smumgr)) if (!smu7_is_smc_ram_running(hwmgr))
return -EINVAL; return -EINVAL;
SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0); SMUM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);
ret = SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP); ret = SMUM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP);
if (ret != 1) if (ret != 1)
pr_info("\n failed to send pre message %x ret is %d \n", msg, ret); pr_info("\n failed to send pre message %x ret is %d \n", msg, ret);
cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg); cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, msg);
SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0); SMUM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);
ret = SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP); ret = SMUM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP);
if (ret != 1) if (ret != 1)
pr_info("\n failed to send message %x ret is %d \n", msg, ret); pr_info("\n failed to send message %x ret is %d \n", msg, ret);
...@@ -189,53 +189,53 @@ int smu7_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg) ...@@ -189,53 +189,53 @@ int smu7_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
return 0; return 0;
} }
int smu7_send_msg_to_smc_without_waiting(struct pp_smumgr *smumgr, uint16_t msg) int smu7_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr, uint16_t msg)
{ {
cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg); cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, msg);
return 0; return 0;
} }
int smu7_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter) int smu7_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr, uint16_t msg, uint32_t parameter)
{ {
if (!smu7_is_smc_ram_running(smumgr)) { if (!smu7_is_smc_ram_running(hwmgr)) {
return -EINVAL; return -EINVAL;
} }
SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0); SMUM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);
cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, parameter); cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, parameter);
return smu7_send_msg_to_smc(smumgr, msg); return smu7_send_msg_to_smc(hwmgr, msg);
} }
int smu7_send_msg_to_smc_with_parameter_without_waiting(struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter) int smu7_send_msg_to_smc_with_parameter_without_waiting(struct pp_hwmgr *hwmgr, uint16_t msg, uint32_t parameter)
{ {
cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, parameter); cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, parameter);
return smu7_send_msg_to_smc_without_waiting(smumgr, msg); return smu7_send_msg_to_smc_without_waiting(hwmgr, msg);
} }
int smu7_send_msg_to_smc_offset(struct pp_smumgr *smumgr) int smu7_send_msg_to_smc_offset(struct pp_hwmgr *hwmgr)
{ {
cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, 0x20000); cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, 0x20000);
cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, PPSMC_MSG_Test); cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, PPSMC_MSG_Test);
SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0); SMUM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);
if (1 != SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP)) if (1 != SMUM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP))
pr_info("Failed to send Message.\n"); pr_info("Failed to send Message.\n");
return 0; return 0;
} }
int smu7_wait_for_smc_inactive(struct pp_smumgr *smumgr) int smu7_wait_for_smc_inactive(struct pp_hwmgr *hwmgr)
{ {
if (!smu7_is_smc_ram_running(smumgr)) if (!smu7_is_smc_ram_running(hwmgr))
return -EINVAL; return -EINVAL;
SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, SMC_SYSCON_CLOCK_CNTL_0, cken, 0); SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, SMC_SYSCON_CLOCK_CNTL_0, cken, 0);
return 0; return 0;
} }
...@@ -289,29 +289,29 @@ enum cgs_ucode_id smu7_convert_fw_type_to_cgs(uint32_t fw_type) ...@@ -289,29 +289,29 @@ enum cgs_ucode_id smu7_convert_fw_type_to_cgs(uint32_t fw_type)
} }
int smu7_read_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t *value, uint32_t limit) int smu7_read_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_t *value, uint32_t limit)
{ {
int result; int result;
result = smu7_set_smc_sram_address(smumgr, smc_addr, limit); result = smu7_set_smc_sram_address(hwmgr, smc_addr, limit);
if (result) if (result)
return result; return result;
*value = cgs_read_register(smumgr->device, mmSMC_IND_DATA_11); *value = cgs_read_register(hwmgr->device, mmSMC_IND_DATA_11);
return 0; return 0;
} }
int smu7_write_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t value, uint32_t limit) int smu7_write_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_t value, uint32_t limit)
{ {
int result; int result;
result = smu7_set_smc_sram_address(smumgr, smc_addr, limit); result = smu7_set_smc_sram_address(hwmgr, smc_addr, limit);
if (result) if (result)
return result; return result;
cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, value); cgs_write_register(hwmgr->device, mmSMC_IND_DATA_11, value);
return 0; return 0;
} }
...@@ -354,14 +354,14 @@ static uint32_t smu7_get_mask_for_firmware_type(uint32_t fw_type) ...@@ -354,14 +354,14 @@ static uint32_t smu7_get_mask_for_firmware_type(uint32_t fw_type)
return result; return result;
} }
static int smu7_populate_single_firmware_entry(struct pp_smumgr *smumgr, static int smu7_populate_single_firmware_entry(struct pp_hwmgr *hwmgr,
uint32_t fw_type, uint32_t fw_type,
struct SMU_Entry *entry) struct SMU_Entry *entry)
{ {
int result = 0; int result = 0;
struct cgs_firmware_info info = {0}; struct cgs_firmware_info info = {0};
result = cgs_get_firmware_info(smumgr->device, result = cgs_get_firmware_info(hwmgr->device,
smu7_convert_fw_type_to_cgs(fw_type), smu7_convert_fw_type_to_cgs(fw_type),
&info); &info);
...@@ -374,7 +374,7 @@ static int smu7_populate_single_firmware_entry(struct pp_smumgr *smumgr, ...@@ -374,7 +374,7 @@ static int smu7_populate_single_firmware_entry(struct pp_smumgr *smumgr,
entry->meta_data_addr_low = 0; entry->meta_data_addr_low = 0;
/* digest need be excluded out */ /* digest need be excluded out */
if (cgs_is_virtualization_enabled(smumgr->device)) if (cgs_is_virtualization_enabled(hwmgr->device))
info.image_size -= 20; info.image_size -= 20;
entry->data_size_byte = info.image_size; entry->data_size_byte = info.image_size;
entry->num_register_entries = 0; entry->num_register_entries = 0;
...@@ -389,30 +389,30 @@ static int smu7_populate_single_firmware_entry(struct pp_smumgr *smumgr, ...@@ -389,30 +389,30 @@ static int smu7_populate_single_firmware_entry(struct pp_smumgr *smumgr,
return 0; return 0;
} }
int smu7_request_smu_load_fw(struct pp_smumgr *smumgr) int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr)
{ {
struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend); struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend);
uint32_t fw_to_load; uint32_t fw_to_load;
int result = 0; int result = 0;
struct SMU_DRAMData_TOC *toc; struct SMU_DRAMData_TOC *toc;
if (!smumgr->reload_fw) { if (!hwmgr->smumgr->reload_fw) {
pr_info("skip reloading...\n"); pr_info("skip reloading...\n");
return 0; return 0;
} }
if (smu_data->soft_regs_start) if (smu_data->soft_regs_start)
cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
smu_data->soft_regs_start + smum_get_offsetof(smumgr, smu_data->soft_regs_start + smum_get_offsetof(hwmgr,
SMU_SoftRegisters, UcodeLoadStatus), SMU_SoftRegisters, UcodeLoadStatus),
0x0); 0x0);
if (smumgr->chip_id > CHIP_TOPAZ) { /* add support for Topaz */ if (hwmgr->chip_id > CHIP_TOPAZ) { /* add support for Topaz */
if (!cgs_is_virtualization_enabled(smumgr->device)) { if (!cgs_is_virtualization_enabled(hwmgr->device)) {
smu7_send_msg_to_smc_with_parameter(smumgr, smu7_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SMU_DRAM_ADDR_HI, PPSMC_MSG_SMU_DRAM_ADDR_HI,
smu_data->smu_buffer.mc_addr_high); smu_data->smu_buffer.mc_addr_high);
smu7_send_msg_to_smc_with_parameter(smumgr, smu7_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SMU_DRAM_ADDR_LO, PPSMC_MSG_SMU_DRAM_ADDR_LO,
smu_data->smu_buffer.mc_addr_low); smu_data->smu_buffer.mc_addr_low);
} }
...@@ -439,80 +439,80 @@ int smu7_request_smu_load_fw(struct pp_smumgr *smumgr) ...@@ -439,80 +439,80 @@ int smu7_request_smu_load_fw(struct pp_smumgr *smumgr)
toc->num_entries = 0; toc->num_entries = 0;
toc->structure_version = 1; toc->structure_version = 1;
PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr, PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
UCODE_ID_RLC_G, &toc->entry[toc->num_entries++]), UCODE_ID_RLC_G, &toc->entry[toc->num_entries++]),
"Failed to Get Firmware Entry.", return -EINVAL); "Failed to Get Firmware Entry.", return -EINVAL);
PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr, PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
UCODE_ID_CP_CE, &toc->entry[toc->num_entries++]), UCODE_ID_CP_CE, &toc->entry[toc->num_entries++]),
"Failed to Get Firmware Entry.", return -EINVAL); "Failed to Get Firmware Entry.", return -EINVAL);
PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr, PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
UCODE_ID_CP_PFP, &toc->entry[toc->num_entries++]), UCODE_ID_CP_PFP, &toc->entry[toc->num_entries++]),
"Failed to Get Firmware Entry.", return -EINVAL); "Failed to Get Firmware Entry.", return -EINVAL);
PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr, PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
UCODE_ID_CP_ME, &toc->entry[toc->num_entries++]), UCODE_ID_CP_ME, &toc->entry[toc->num_entries++]),
"Failed to Get Firmware Entry.", return -EINVAL); "Failed to Get Firmware Entry.", return -EINVAL);
PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr, PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
UCODE_ID_CP_MEC, &toc->entry[toc->num_entries++]), UCODE_ID_CP_MEC, &toc->entry[toc->num_entries++]),
"Failed to Get Firmware Entry.", return -EINVAL); "Failed to Get Firmware Entry.", return -EINVAL);
PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr, PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
UCODE_ID_CP_MEC_JT1, &toc->entry[toc->num_entries++]), UCODE_ID_CP_MEC_JT1, &toc->entry[toc->num_entries++]),
"Failed to Get Firmware Entry.", return -EINVAL); "Failed to Get Firmware Entry.", return -EINVAL);
PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr, PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
UCODE_ID_CP_MEC_JT2, &toc->entry[toc->num_entries++]), UCODE_ID_CP_MEC_JT2, &toc->entry[toc->num_entries++]),
"Failed to Get Firmware Entry.", return -EINVAL); "Failed to Get Firmware Entry.", return -EINVAL);
PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr, PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
UCODE_ID_SDMA0, &toc->entry[toc->num_entries++]), UCODE_ID_SDMA0, &toc->entry[toc->num_entries++]),
"Failed to Get Firmware Entry.", return -EINVAL); "Failed to Get Firmware Entry.", return -EINVAL);
PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr, PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
UCODE_ID_SDMA1, &toc->entry[toc->num_entries++]), UCODE_ID_SDMA1, &toc->entry[toc->num_entries++]),
"Failed to Get Firmware Entry.", return -EINVAL); "Failed to Get Firmware Entry.", return -EINVAL);
if (cgs_is_virtualization_enabled(smumgr->device)) if (cgs_is_virtualization_enabled(hwmgr->device))
PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr, PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
UCODE_ID_MEC_STORAGE, &toc->entry[toc->num_entries++]), UCODE_ID_MEC_STORAGE, &toc->entry[toc->num_entries++]),
"Failed to Get Firmware Entry.", return -EINVAL); "Failed to Get Firmware Entry.", return -EINVAL);
smu7_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_DRV_DRAM_ADDR_HI, smu_data->header_buffer.mc_addr_high); smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DRV_DRAM_ADDR_HI, smu_data->header_buffer.mc_addr_high);
smu7_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_DRV_DRAM_ADDR_LO, smu_data->header_buffer.mc_addr_low); smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DRV_DRAM_ADDR_LO, smu_data->header_buffer.mc_addr_low);
if (smu7_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_LoadUcodes, fw_to_load)) if (smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_LoadUcodes, fw_to_load))
pr_err("Fail to Request SMU Load uCode"); pr_err("Fail to Request SMU Load uCode");
return result; return result;
} }
/* Check if the FW has been loaded, SMU will not return if loading has not finished. */ /* Check if the FW has been loaded, SMU will not return if loading has not finished. */
int smu7_check_fw_load_finish(struct pp_smumgr *smumgr, uint32_t fw_type) int smu7_check_fw_load_finish(struct pp_hwmgr *hwmgr, uint32_t fw_type)
{ {
struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend); struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend);
uint32_t fw_mask = smu7_get_mask_for_firmware_type(fw_type); uint32_t fw_mask = smu7_get_mask_for_firmware_type(fw_type);
uint32_t ret; uint32_t ret;
ret = smum_wait_on_indirect_register(smumgr, mmSMC_IND_INDEX_11, ret = smum_wait_on_indirect_register(hwmgr, mmSMC_IND_INDEX_11,
smu_data->soft_regs_start + smum_get_offsetof(smumgr, smu_data->soft_regs_start + smum_get_offsetof(hwmgr,
SMU_SoftRegisters, UcodeLoadStatus), SMU_SoftRegisters, UcodeLoadStatus),
fw_mask, fw_mask); fw_mask, fw_mask);
return ret; return ret;
} }
int smu7_reload_firmware(struct pp_smumgr *smumgr) int smu7_reload_firmware(struct pp_hwmgr *hwmgr)
{ {
return smumgr->smumgr_funcs->start_smu(smumgr); return hwmgr->smumgr->smumgr_funcs->start_smu(hwmgr);
} }
static int smu7_upload_smc_firmware_data(struct pp_smumgr *smumgr, uint32_t length, uint32_t *src, uint32_t limit) static int smu7_upload_smc_firmware_data(struct pp_hwmgr *hwmgr, uint32_t length, uint32_t *src, uint32_t limit)
{ {
uint32_t byte_count = length; uint32_t byte_count = length;
PP_ASSERT_WITH_CODE((limit >= byte_count), "SMC address is beyond the SMC RAM area.", return -EINVAL); PP_ASSERT_WITH_CODE((limit >= byte_count), "SMC address is beyond the SMC RAM area.", return -EINVAL);
cgs_write_register(smumgr->device, mmSMC_IND_INDEX_11, 0x20000); cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_11, 0x20000);
SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 1); SMUM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 1);
for (; byte_count >= 4; byte_count -= 4) for (; byte_count >= 4; byte_count -= 4)
cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, *src++); cgs_write_register(hwmgr->device, mmSMC_IND_DATA_11, *src++);
SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0); SMUM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0);
PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be dividable by 4.", return -EINVAL); PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be dividable by 4.", return -EINVAL);
...@@ -520,41 +520,41 @@ static int smu7_upload_smc_firmware_data(struct pp_smumgr *smumgr, uint32_t leng ...@@ -520,41 +520,41 @@ static int smu7_upload_smc_firmware_data(struct pp_smumgr *smumgr, uint32_t leng
} }
int smu7_upload_smu_firmware_image(struct pp_smumgr *smumgr) int smu7_upload_smu_firmware_image(struct pp_hwmgr *hwmgr)
{ {
int result = 0; int result = 0;
struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend); struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend);
struct cgs_firmware_info info = {0}; struct cgs_firmware_info info = {0};
if (smu_data->security_hard_key == 1) if (smu_data->security_hard_key == 1)
cgs_get_firmware_info(smumgr->device, cgs_get_firmware_info(hwmgr->device,
smu7_convert_fw_type_to_cgs(UCODE_ID_SMU), &info); smu7_convert_fw_type_to_cgs(UCODE_ID_SMU), &info);
else else
cgs_get_firmware_info(smumgr->device, cgs_get_firmware_info(hwmgr->device,
smu7_convert_fw_type_to_cgs(UCODE_ID_SMU_SK), &info); smu7_convert_fw_type_to_cgs(UCODE_ID_SMU_SK), &info);
smumgr->is_kicker = info.is_kicker; hwmgr->smumgr->is_kicker = info.is_kicker;
result = smu7_upload_smc_firmware_data(smumgr, info.image_size, (uint32_t *)info.kptr, SMU7_SMC_SIZE); result = smu7_upload_smc_firmware_data(hwmgr, info.image_size, (uint32_t *)info.kptr, SMU7_SMC_SIZE);
return result; return result;
} }
int smu7_init(struct pp_smumgr *smumgr) int smu7_init(struct pp_hwmgr *hwmgr)
{ {
struct smu7_smumgr *smu_data; struct smu7_smumgr *smu_data;
uint8_t *internal_buf; uint8_t *internal_buf;
uint64_t mc_addr = 0; uint64_t mc_addr = 0;
/* Allocate memory for backend private data */ /* Allocate memory for backend private data */
smu_data = (struct smu7_smumgr *)(smumgr->backend); smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend);
smu_data->header_buffer.data_size = smu_data->header_buffer.data_size =
((sizeof(struct SMU_DRAMData_TOC) / 4096) + 1) * 4096; ((sizeof(struct SMU_DRAMData_TOC) / 4096) + 1) * 4096;
/* Allocate FW image data structure and header buffer and /* Allocate FW image data structure and header buffer and
* send the header buffer address to SMU */ * send the header buffer address to SMU */
smu_allocate_memory(smumgr->device, smu_allocate_memory(hwmgr->device,
smu_data->header_buffer.data_size, smu_data->header_buffer.data_size,
CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB, CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
PAGE_SIZE, PAGE_SIZE,
...@@ -568,16 +568,16 @@ int smu7_init(struct pp_smumgr *smumgr) ...@@ -568,16 +568,16 @@ int smu7_init(struct pp_smumgr *smumgr)
PP_ASSERT_WITH_CODE((NULL != smu_data->header), PP_ASSERT_WITH_CODE((NULL != smu_data->header),
"Out of memory.", "Out of memory.",
kfree(smumgr->backend); kfree(hwmgr->smumgr->backend);
cgs_free_gpu_mem(smumgr->device, cgs_free_gpu_mem(hwmgr->device,
(cgs_handle_t)smu_data->header_buffer.handle); (cgs_handle_t)smu_data->header_buffer.handle);
return -EINVAL); return -EINVAL);
if (cgs_is_virtualization_enabled(smumgr->device)) if (cgs_is_virtualization_enabled(hwmgr->device))
return 0; return 0;
smu_data->smu_buffer.data_size = 200*4096; smu_data->smu_buffer.data_size = 200*4096;
smu_allocate_memory(smumgr->device, smu_allocate_memory(hwmgr->device,
smu_data->smu_buffer.data_size, smu_data->smu_buffer.data_size,
CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB, CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
PAGE_SIZE, PAGE_SIZE,
...@@ -591,12 +591,12 @@ int smu7_init(struct pp_smumgr *smumgr) ...@@ -591,12 +591,12 @@ int smu7_init(struct pp_smumgr *smumgr)
PP_ASSERT_WITH_CODE((NULL != internal_buf), PP_ASSERT_WITH_CODE((NULL != internal_buf),
"Out of memory.", "Out of memory.",
kfree(smumgr->backend); kfree(hwmgr->smumgr->backend);
cgs_free_gpu_mem(smumgr->device, cgs_free_gpu_mem(hwmgr->device,
(cgs_handle_t)smu_data->smu_buffer.handle); (cgs_handle_t)smu_data->smu_buffer.handle);
return -EINVAL); return -EINVAL);
if (smum_is_hw_avfs_present(smumgr)) if (smum_is_hw_avfs_present(hwmgr))
smu_data->avfs.avfs_btc_status = AVFS_BTC_BOOT; smu_data->avfs.avfs_btc_status = AVFS_BTC_BOOT;
else else
smu_data->avfs.avfs_btc_status = AVFS_BTC_NOTSUPPORTED; smu_data->avfs.avfs_btc_status = AVFS_BTC_NOTSUPPORTED;
...@@ -605,10 +605,10 @@ int smu7_init(struct pp_smumgr *smumgr) ...@@ -605,10 +605,10 @@ int smu7_init(struct pp_smumgr *smumgr)
} }
int smu7_smu_fini(struct pp_smumgr *smumgr) int smu7_smu_fini(struct pp_hwmgr *hwmgr)
{ {
kfree(smumgr->backend); kfree(hwmgr->smumgr->backend);
smumgr->backend = NULL; hwmgr->smumgr->backend = NULL;
cgs_rel_firmware(smumgr->device, CGS_UCODE_ID_SMU); cgs_rel_firmware(hwmgr->device, CGS_UCODE_ID_SMU);
return 0; return 0;
} }
drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h
浏览文件 @ d3f8c0ab
...@@ -60,32 +60,32 @@ struct smu7_smumgr { ...@@ -60,32 +60,32 @@ struct smu7_smumgr {
}; };
int smu7_copy_bytes_from_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address, int smu7_copy_bytes_from_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address,
uint32_t *dest, uint32_t byte_count, uint32_t limit); uint32_t *dest, uint32_t byte_count, uint32_t limit);
int smu7_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address, int smu7_copy_bytes_to_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address,
const uint8_t *src, uint32_t byte_count, uint32_t limit); const uint8_t *src, uint32_t byte_count, uint32_t limit);
int smu7_program_jump_on_start(struct pp_smumgr *smumgr); int smu7_program_jump_on_start(struct pp_hwmgr *hwmgr);
bool smu7_is_smc_ram_running(struct pp_smumgr *smumgr); bool smu7_is_smc_ram_running(struct pp_hwmgr *hwmgr);
int smu7_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg); int smu7_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg);
int smu7_send_msg_to_smc_without_waiting(struct pp_smumgr *smumgr, uint16_t msg); int smu7_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr, uint16_t msg);
int smu7_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, uint16_t msg, int smu7_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr, uint16_t msg,
uint32_t parameter); uint32_t parameter);
int smu7_send_msg_to_smc_with_parameter_without_waiting(struct pp_smumgr *smumgr, int smu7_send_msg_to_smc_with_parameter_without_waiting(struct pp_hwmgr *hwmgr,
uint16_t msg, uint32_t parameter); uint16_t msg, uint32_t parameter);
int smu7_send_msg_to_smc_offset(struct pp_smumgr *smumgr); int smu7_send_msg_to_smc_offset(struct pp_hwmgr *hwmgr);
int smu7_wait_for_smc_inactive(struct pp_smumgr *smumgr); int smu7_wait_for_smc_inactive(struct pp_hwmgr *hwmgr);
enum cgs_ucode_id smu7_convert_fw_type_to_cgs(uint32_t fw_type); enum cgs_ucode_id smu7_convert_fw_type_to_cgs(uint32_t fw_type);
int smu7_read_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, int smu7_read_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr,
uint32_t *value, uint32_t limit); uint32_t *value, uint32_t limit);
int smu7_write_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, int smu7_write_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr,
uint32_t value, uint32_t limit); uint32_t value, uint32_t limit);
int smu7_request_smu_load_fw(struct pp_smumgr *smumgr); int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr);
int smu7_check_fw_load_finish(struct pp_smumgr *smumgr, uint32_t fw_type); int smu7_check_fw_load_finish(struct pp_hwmgr *hwmgr, uint32_t fw_type);
int smu7_reload_firmware(struct pp_smumgr *smumgr); int smu7_reload_firmware(struct pp_hwmgr *hwmgr);
int smu7_upload_smu_firmware_image(struct pp_smumgr *smumgr); int smu7_upload_smu_firmware_image(struct pp_hwmgr *hwmgr);
int smu7_init(struct pp_smumgr *smumgr); int smu7_init(struct pp_hwmgr *hwmgr);
int smu7_smu_fini(struct pp_smumgr *smumgr); int smu7_smu_fini(struct pp_hwmgr *hwmgr);
#endif #endif
\ No newline at end of file
drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
浏览文件 @ d3f8c0ab
...@@ -151,10 +151,10 @@ int smum_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type) ...@@ -151,10 +151,10 @@ int smum_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
return 0; return 0;
} }
uint32_t smum_get_offsetof(struct pp_smumgr *smumgr, uint32_t type, uint32_t member) uint32_t smum_get_offsetof(struct pp_hwmgr *hwmgr, uint32_t type, uint32_t member)
{ {
if (NULL != smumgr->smumgr_funcs->get_offsetof) if (NULL != hwmgr->smumgr->smumgr_funcs->get_offsetof)
return smumgr->smumgr_funcs->get_offsetof(type, member); return hwmgr->smumgr->smumgr_funcs->get_offsetof(type, member);
return 0; return 0;
} }
...@@ -166,97 +166,96 @@ int smum_process_firmware_header(struct pp_hwmgr *hwmgr) ...@@ -166,97 +166,96 @@ int smum_process_firmware_header(struct pp_hwmgr *hwmgr)
return 0; return 0;
} }
int smum_get_argument(struct pp_smumgr *smumgr) int smum_get_argument(struct pp_hwmgr *hwmgr)
{ {
if (NULL != smumgr->smumgr_funcs->get_argument) if (NULL != hwmgr->smumgr->smumgr_funcs->get_argument)
return smumgr->smumgr_funcs->get_argument(smumgr); return hwmgr->smumgr->smumgr_funcs->get_argument(hwmgr);
return 0; return 0;
} }
uint32_t smum_get_mac_definition(struct pp_smumgr *smumgr, uint32_t value) uint32_t smum_get_mac_definition(struct pp_hwmgr *hwmgr, uint32_t value)
{ {
if (NULL != smumgr->smumgr_funcs->get_mac_definition) if (NULL != hwmgr->smumgr->smumgr_funcs->get_mac_definition)
return smumgr->smumgr_funcs->get_mac_definition(value); return hwmgr->smumgr->smumgr_funcs->get_mac_definition(value);
return 0; return 0;
} }
int smum_download_powerplay_table(struct pp_smumgr *smumgr, int smum_download_powerplay_table(struct pp_hwmgr *hwmgr, void **table)
void **table)
{ {
if (NULL != smumgr->smumgr_funcs->download_pptable_settings) if (NULL != hwmgr->smumgr->smumgr_funcs->download_pptable_settings)
return smumgr->smumgr_funcs->download_pptable_settings(smumgr, return hwmgr->smumgr->smumgr_funcs->download_pptable_settings(hwmgr,
table); table);
return 0; return 0;
} }
int smum_upload_powerplay_table(struct pp_smumgr *smumgr) int smum_upload_powerplay_table(struct pp_hwmgr *hwmgr)
{ {
if (NULL != smumgr->smumgr_funcs->upload_pptable_settings) if (NULL != hwmgr->smumgr->smumgr_funcs->upload_pptable_settings)
return smumgr->smumgr_funcs->upload_pptable_settings(smumgr); return hwmgr->smumgr->smumgr_funcs->upload_pptable_settings(hwmgr);
return 0; return 0;
} }
int smum_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg) int smum_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
{ {
if (smumgr == NULL || smumgr->smumgr_funcs->send_msg_to_smc == NULL) if (hwmgr == NULL || hwmgr->smumgr->smumgr_funcs->send_msg_to_smc == NULL)
return -EINVAL; return -EINVAL;
return smumgr->smumgr_funcs->send_msg_to_smc(smumgr, msg); return hwmgr->smumgr->smumgr_funcs->send_msg_to_smc(hwmgr, msg);
} }
int smum_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, int smum_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
uint16_t msg, uint32_t parameter) uint16_t msg, uint32_t parameter)
{ {
if (smumgr == NULL || if (hwmgr == NULL ||
smumgr->smumgr_funcs->send_msg_to_smc_with_parameter == NULL) hwmgr->smumgr->smumgr_funcs->send_msg_to_smc_with_parameter == NULL)
return -EINVAL; return -EINVAL;
return smumgr->smumgr_funcs->send_msg_to_smc_with_parameter( return hwmgr->smumgr->smumgr_funcs->send_msg_to_smc_with_parameter(
smumgr, msg, parameter); hwmgr, msg, parameter);
} }
/* /*
* Returns once the part of the register indicated by the mask has * Returns once the part of the register indicated by the mask has
* reached the given value. * reached the given value.
*/ */
int smum_wait_on_register(struct pp_smumgr *smumgr, int smum_wait_on_register(struct pp_hwmgr *hwmgr,
uint32_t index, uint32_t index,
uint32_t value, uint32_t mask) uint32_t value, uint32_t mask)
{ {
uint32_t i; uint32_t i;
uint32_t cur_value; uint32_t cur_value;
if (smumgr == NULL || smumgr->device == NULL) if (hwmgr == NULL || hwmgr->device == NULL)
return -EINVAL; return -EINVAL;
for (i = 0; i < smumgr->usec_timeout; i++) { for (i = 0; i < hwmgr->usec_timeout; i++) {
cur_value = cgs_read_register(smumgr->device, index); cur_value = cgs_read_register(hwmgr->device, index);
if ((cur_value & mask) == (value & mask)) if ((cur_value & mask) == (value & mask))
break; break;
udelay(1); udelay(1);
} }
/* timeout means wrong logic*/ /* timeout means wrong logic*/
if (i == smumgr->usec_timeout) if (i == hwmgr->usec_timeout)
return -1; return -1;
return 0; return 0;
} }
int smum_wait_for_register_unequal(struct pp_smumgr *smumgr, int smum_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
uint32_t index, uint32_t index,
uint32_t value, uint32_t mask) uint32_t value, uint32_t mask)
{ {
uint32_t i; uint32_t i;
uint32_t cur_value; uint32_t cur_value;
if (smumgr == NULL) if (hwmgr == NULL)
return -EINVAL; return -EINVAL;
for (i = 0; i < smumgr->usec_timeout; i++) { for (i = 0; i < hwmgr->usec_timeout; i++) {
cur_value = cgs_read_register(smumgr->device, cur_value = cgs_read_register(hwmgr->device,
index); index);
if ((cur_value & mask) != (value & mask)) if ((cur_value & mask) != (value & mask))
break; break;
...@@ -264,7 +263,7 @@ int smum_wait_for_register_unequal(struct pp_smumgr *smumgr, ...@@ -264,7 +263,7 @@ int smum_wait_for_register_unequal(struct pp_smumgr *smumgr,
} }
/* timeout means wrong logic */ /* timeout means wrong logic */
if (i == smumgr->usec_timeout) if (i == hwmgr->usec_timeout)
return -1; return -1;
return 0; return 0;
...@@ -276,31 +275,31 @@ int smum_wait_for_register_unequal(struct pp_smumgr *smumgr, ...@@ -276,31 +275,31 @@ int smum_wait_for_register_unequal(struct pp_smumgr *smumgr,
* has reached the given value.The indirect space is described by * has reached the given value.The indirect space is described by
* giving the memory-mapped index of the indirect index register. * giving the memory-mapped index of the indirect index register.
*/ */
int smum_wait_on_indirect_register(struct pp_smumgr *smumgr, int smum_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
uint32_t indirect_port, uint32_t indirect_port,
uint32_t index, uint32_t index,
uint32_t value, uint32_t value,
uint32_t mask) uint32_t mask)
{ {
if (smumgr == NULL || smumgr->device == NULL) if (hwmgr == NULL || hwmgr->device == NULL)
return -EINVAL; return -EINVAL;
cgs_write_register(smumgr->device, indirect_port, index); cgs_write_register(hwmgr->device, indirect_port, index);
return smum_wait_on_register(smumgr, indirect_port + 1, return smum_wait_on_register(hwmgr, indirect_port + 1,
mask, value); mask, value);
} }
void smum_wait_for_indirect_register_unequal( void smum_wait_for_indirect_register_unequal(
struct pp_smumgr *smumgr, struct pp_hwmgr *hwmgr,
uint32_t indirect_port, uint32_t indirect_port,
uint32_t index, uint32_t index,
uint32_t value, uint32_t value,
uint32_t mask) uint32_t mask)
{ {
if (smumgr == NULL || smumgr->device == NULL) if (hwmgr == NULL || hwmgr->device == NULL)
return; return;
cgs_write_register(smumgr->device, indirect_port, index); cgs_write_register(hwmgr->device, indirect_port, index);
smum_wait_for_register_unequal(smumgr, indirect_port + 1, smum_wait_for_register_unequal(hwmgr, indirect_port + 1,
value, mask); value, mask);
} }
...@@ -406,10 +405,10 @@ int smum_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr, ...@@ -406,10 +405,10 @@ int smum_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
return 0; return 0;
} }
bool smum_is_hw_avfs_present(struct pp_smumgr *smumgr) bool smum_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
{ {
if (smumgr->smumgr_funcs->is_hw_avfs_present) if (hwmgr->smumgr->smumgr_funcs->is_hw_avfs_present)
return smumgr->smumgr_funcs->is_hw_avfs_present(smumgr); return hwmgr->smumgr->smumgr_funcs->is_hw_avfs_present(hwmgr);
return false; return false;
} }
drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c
浏览文件 @ d3f8c0ab
...@@ -690,7 +690,7 @@ int tonga_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) ...@@ -690,7 +690,7 @@ int tonga_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
smu_data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled; smu_data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled;
} }
/* level count will send to smc once at init smc table and never change*/ /* level count will send to smc once at init smc table and never change*/
result = smu7_copy_bytes_to_smc(hwmgr->smumgr, level_array_address, result = smu7_copy_bytes_to_smc(hwmgr, level_array_address,
(uint8_t *)levels, (uint32_t)level_array_size, (uint8_t *)levels, (uint32_t)level_array_size,
SMC_RAM_END); SMC_RAM_END);
...@@ -1048,7 +1048,7 @@ int tonga_populate_all_memory_levels(struct pp_hwmgr *hwmgr) ...@@ -1048,7 +1048,7 @@ int tonga_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH; smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
/* level count will send to smc once at init smc table and never change*/ /* level count will send to smc once at init smc table and never change*/
result = smu7_copy_bytes_to_smc(hwmgr->smumgr, result = smu7_copy_bytes_to_smc(hwmgr,
level_array_address, (uint8_t *)levels, (uint32_t)level_array_size, level_array_address, (uint8_t *)levels, (uint32_t)level_array_size,
SMC_RAM_END); SMC_RAM_END);
...@@ -1475,7 +1475,7 @@ static int tonga_program_memory_timing_parameters(struct pp_hwmgr *hwmgr) ...@@ -1475,7 +1475,7 @@ static int tonga_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
if (!result) { if (!result) {
result = smu7_copy_bytes_to_smc( result = smu7_copy_bytes_to_smc(
hwmgr->smumgr, hwmgr,
smu_data->smu7_data.arb_table_start, smu_data->smu7_data.arb_table_start,
(uint8_t *)&arb_regs, (uint8_t *)&arb_regs,
sizeof(SMU72_Discrete_MCArbDramTimingTable), sizeof(SMU72_Discrete_MCArbDramTimingTable),
...@@ -1782,9 +1782,9 @@ static int tonga_populate_vr_config(struct pp_hwmgr *hwmgr, ...@@ -1782,9 +1782,9 @@ static int tonga_populate_vr_config(struct pp_hwmgr *hwmgr,
* @param hwmgr the address of the powerplay hardware manager. * @param hwmgr the address of the powerplay hardware manager.
* @return always 0 * @return always 0
*/ */
static int tonga_init_arb_table_index(struct pp_smumgr *smumgr) static int tonga_init_arb_table_index(struct pp_hwmgr *hwmgr)
{ {
struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(smumgr->backend); struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend);
uint32_t tmp; uint32_t tmp;
int result; int result;
...@@ -1797,7 +1797,7 @@ static int tonga_init_arb_table_index(struct pp_smumgr *smumgr) ...@@ -1797,7 +1797,7 @@ static int tonga_init_arb_table_index(struct pp_smumgr *smumgr)
* In reality this field should not be in that structure * In reality this field should not be in that structure
* but in a soft register. * but in a soft register.
*/ */
result = smu7_read_smc_sram_dword(smumgr, result = smu7_read_smc_sram_dword(hwmgr,
smu_data->smu7_data.arb_table_start, &tmp, SMC_RAM_END); smu_data->smu7_data.arb_table_start, &tmp, SMC_RAM_END);
if (result != 0) if (result != 0)
...@@ -1806,7 +1806,7 @@ static int tonga_init_arb_table_index(struct pp_smumgr *smumgr) ...@@ -1806,7 +1806,7 @@ static int tonga_init_arb_table_index(struct pp_smumgr *smumgr)
tmp &= 0x00FFFFFF; tmp &= 0x00FFFFFF;
tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24; tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
return smu7_write_smc_sram_dword(smumgr, return smu7_write_smc_sram_dword(hwmgr,
smu_data->smu7_data.arb_table_start, tmp, SMC_RAM_END); smu_data->smu7_data.arb_table_start, tmp, SMC_RAM_END);
} }
...@@ -1901,7 +1901,7 @@ static int tonga_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset ...@@ -1901,7 +1901,7 @@ static int tonga_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset
const struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults; const struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults;
uint32_t temp; uint32_t temp;
if (smu7_read_smc_sram_dword(hwmgr->smumgr, if (smu7_read_smc_sram_dword(hwmgr,
fuse_table_offset + fuse_table_offset +
offsetof(SMU72_Discrete_PmFuses, TdcWaterfallCtl), offsetof(SMU72_Discrete_PmFuses, TdcWaterfallCtl),
(uint32_t *)&temp, SMC_RAM_END)) (uint32_t *)&temp, SMC_RAM_END))
...@@ -1987,7 +1987,7 @@ static int tonga_populate_pm_fuses(struct pp_hwmgr *hwmgr) ...@@ -1987,7 +1987,7 @@ static int tonga_populate_pm_fuses(struct pp_hwmgr *hwmgr)
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_PowerContainment)) { PHM_PlatformCaps_PowerContainment)) {
if (smu7_read_smc_sram_dword(hwmgr->smumgr, if (smu7_read_smc_sram_dword(hwmgr,
SMU72_FIRMWARE_HEADER_LOCATION + SMU72_FIRMWARE_HEADER_LOCATION +
offsetof(SMU72_Firmware_Header, PmFuseTable), offsetof(SMU72_Firmware_Header, PmFuseTable),
&pm_fuse_table_offset, SMC_RAM_END)) &pm_fuse_table_offset, SMC_RAM_END))
...@@ -2038,7 +2038,7 @@ static int tonga_populate_pm_fuses(struct pp_hwmgr *hwmgr) ...@@ -2038,7 +2038,7 @@ static int tonga_populate_pm_fuses(struct pp_hwmgr *hwmgr)
"Hi and Lo Sidd Failed !", "Hi and Lo Sidd Failed !",
return -EINVAL); return -EINVAL);
if (smu7_copy_bytes_to_smc(hwmgr->smumgr, pm_fuse_table_offset, if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
(uint8_t *)&smu_data->power_tune_table, (uint8_t *)&smu_data->power_tune_table,
sizeof(struct SMU72_Discrete_PmFuses), SMC_RAM_END)) sizeof(struct SMU72_Discrete_PmFuses), SMC_RAM_END))
PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE(false,
...@@ -2048,10 +2048,10 @@ static int tonga_populate_pm_fuses(struct pp_hwmgr *hwmgr) ...@@ -2048,10 +2048,10 @@ static int tonga_populate_pm_fuses(struct pp_hwmgr *hwmgr)
return 0; return 0;
} }
static int tonga_populate_mc_reg_address(struct pp_smumgr *smumgr, static int tonga_populate_mc_reg_address(struct pp_hwmgr *hwmgr,
SMU72_Discrete_MCRegisters *mc_reg_table) SMU72_Discrete_MCRegisters *mc_reg_table)
{ {
const struct tonga_smumgr *smu_data = (struct tonga_smumgr *)smumgr->backend; const struct tonga_smumgr *smu_data = (struct tonga_smumgr *)hwmgr->smumgr->backend;
uint32_t i, j; uint32_t i, j;
...@@ -2092,12 +2092,12 @@ static void tonga_convert_mc_registers( ...@@ -2092,12 +2092,12 @@ static void tonga_convert_mc_registers(
} }
static int tonga_convert_mc_reg_table_entry_to_smc( static int tonga_convert_mc_reg_table_entry_to_smc(
struct pp_smumgr *smumgr, struct pp_hwmgr *hwmgr,
const uint32_t memory_clock, const uint32_t memory_clock,
SMU72_Discrete_MCRegisterSet *mc_reg_table_data SMU72_Discrete_MCRegisterSet *mc_reg_table_data
) )
{ {
struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(smumgr->backend); struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend);
uint32_t i = 0; uint32_t i = 0;
for (i = 0; i < smu_data->mc_reg_table.num_entries; i++) { for (i = 0; i < smu_data->mc_reg_table.num_entries; i++) {
...@@ -2127,7 +2127,7 @@ static int tonga_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr, ...@@ -2127,7 +2127,7 @@ static int tonga_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
for (i = 0; i < data->dpm_table.mclk_table.count; i++) { for (i = 0; i < data->dpm_table.mclk_table.count; i++) {
res = tonga_convert_mc_reg_table_entry_to_smc( res = tonga_convert_mc_reg_table_entry_to_smc(
hwmgr->smumgr, hwmgr,
data->dpm_table.mclk_table.dpm_levels[i].value, data->dpm_table.mclk_table.dpm_levels[i].value,
&mc_regs->data[i] &mc_regs->data[i]
); );
...@@ -2141,8 +2141,7 @@ static int tonga_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr, ...@@ -2141,8 +2141,7 @@ static int tonga_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
static int tonga_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr) static int tonga_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
{ {
struct pp_smumgr *smumgr = hwmgr->smumgr; struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend);
struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(smumgr->backend);
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
uint32_t address; uint32_t address;
int32_t result; int32_t result;
...@@ -2163,7 +2162,7 @@ static int tonga_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr) ...@@ -2163,7 +2162,7 @@ static int tonga_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
(uint32_t)offsetof(SMU72_Discrete_MCRegisters, data[0]); (uint32_t)offsetof(SMU72_Discrete_MCRegisters, data[0]);
return smu7_copy_bytes_to_smc( return smu7_copy_bytes_to_smc(
hwmgr->smumgr, address, hwmgr, address,
(uint8_t *)&smu_data->mc_regs.data[0], (uint8_t *)&smu_data->mc_regs.data[0],
sizeof(SMU72_Discrete_MCRegisterSet) * sizeof(SMU72_Discrete_MCRegisterSet) *
data->dpm_table.mclk_table.count, data->dpm_table.mclk_table.count,
...@@ -2173,11 +2172,10 @@ static int tonga_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr) ...@@ -2173,11 +2172,10 @@ static int tonga_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
static int tonga_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr) static int tonga_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
{ {
int result; int result;
struct pp_smumgr *smumgr = hwmgr->smumgr; struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend);
struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(smumgr->backend);
memset(&smu_data->mc_regs, 0x00, sizeof(SMU72_Discrete_MCRegisters)); memset(&smu_data->mc_regs, 0x00, sizeof(SMU72_Discrete_MCRegisters));
result = tonga_populate_mc_reg_address(smumgr, &(smu_data->mc_regs)); result = tonga_populate_mc_reg_address(hwmgr, &(smu_data->mc_regs));
PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE(!result,
"Failed to initialize MCRegTable for the MC register addresses !", "Failed to initialize MCRegTable for the MC register addresses !",
return result;); return result;);
...@@ -2187,7 +2185,7 @@ static int tonga_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr) ...@@ -2187,7 +2185,7 @@ static int tonga_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
"Failed to initialize MCRegTable for driver state !", "Failed to initialize MCRegTable for driver state !",
return result;); return result;);
return smu7_copy_bytes_to_smc(smumgr, smu_data->smu7_data.mc_reg_table_start, return smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.mc_reg_table_start,
(uint8_t *)&smu_data->mc_regs, sizeof(SMU72_Discrete_MCRegisters), SMC_RAM_END); (uint8_t *)&smu_data->mc_regs, sizeof(SMU72_Discrete_MCRegisters), SMC_RAM_END);
} }
...@@ -2471,7 +2469,7 @@ int tonga_init_smc_table(struct pp_hwmgr *hwmgr) ...@@ -2471,7 +2469,7 @@ int tonga_init_smc_table(struct pp_hwmgr *hwmgr)
/* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */ /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
result = smu7_copy_bytes_to_smc( result = smu7_copy_bytes_to_smc(
hwmgr->smumgr, hwmgr,
smu_data->smu7_data.dpm_table_start + offsetof(SMU72_Discrete_DpmTable, SystemFlags), smu_data->smu7_data.dpm_table_start + offsetof(SMU72_Discrete_DpmTable, SystemFlags),
(uint8_t *)&(table->SystemFlags), (uint8_t *)&(table->SystemFlags),
sizeof(SMU72_Discrete_DpmTable) - 3 * sizeof(SMU72_PIDController), sizeof(SMU72_Discrete_DpmTable) - 3 * sizeof(SMU72_PIDController),
...@@ -2480,7 +2478,7 @@ int tonga_init_smc_table(struct pp_hwmgr *hwmgr) ...@@ -2480,7 +2478,7 @@ int tonga_init_smc_table(struct pp_hwmgr *hwmgr)
PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE(!result,
"Failed to upload dpm data to SMC memory !", return result;); "Failed to upload dpm data to SMC memory !", return result;);
result = tonga_init_arb_table_index(hwmgr->smumgr); result = tonga_init_arb_table_index(hwmgr);
PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE(!result,
"Failed to upload arb data to SMC memory !", return result); "Failed to upload arb data to SMC memory !", return result);
...@@ -2588,7 +2586,7 @@ int tonga_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) ...@@ -2588,7 +2586,7 @@ int tonga_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
fan_table.FanControl_GL_Flag = 1; fan_table.FanControl_GL_Flag = 1;
res = smu7_copy_bytes_to_smc(hwmgr->smumgr, res = smu7_copy_bytes_to_smc(hwmgr,
smu_data->smu7_data.fan_table_start, smu_data->smu7_data.fan_table_start,
(uint8_t *)&fan_table, (uint8_t *)&fan_table,
(uint32_t)sizeof(fan_table), (uint32_t)sizeof(fan_table),
...@@ -2630,7 +2628,7 @@ int tonga_update_sclk_threshold(struct pp_hwmgr *hwmgr) ...@@ -2630,7 +2628,7 @@ int tonga_update_sclk_threshold(struct pp_hwmgr *hwmgr)
CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold); CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
result = smu7_copy_bytes_to_smc( result = smu7_copy_bytes_to_smc(
hwmgr->smumgr, hwmgr,
smu_data->smu7_data.dpm_table_start + smu_data->smu7_data.dpm_table_start +
offsetof(SMU72_Discrete_DpmTable, offsetof(SMU72_Discrete_DpmTable,
LowSclkInterruptThreshold), LowSclkInterruptThreshold),
...@@ -2741,7 +2739,7 @@ static int tonga_update_uvd_smc_table(struct pp_hwmgr *hwmgr) ...@@ -2741,7 +2739,7 @@ static int tonga_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
PHM_PlatformCaps_UVDDPM) || PHM_PlatformCaps_UVDDPM) ||
phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_StablePState)) PHM_PlatformCaps_StablePState))
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_UVDDPM_SetEnabledMask, PPSMC_MSG_UVDDPM_SetEnabledMask,
(uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel)); (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel));
return 0; return 0;
...@@ -2772,7 +2770,7 @@ static int tonga_update_vce_smc_table(struct pp_hwmgr *hwmgr) ...@@ -2772,7 +2770,7 @@ static int tonga_update_vce_smc_table(struct pp_hwmgr *hwmgr)
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_StablePState)) PHM_PlatformCaps_StablePState))
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_VCEDPM_SetEnabledMask, PPSMC_MSG_VCEDPM_SetEnabledMask,
(uint32_t)1 << smu_data->smc_state_table.VceBootLevel); (uint32_t)1 << smu_data->smc_state_table.VceBootLevel);
return 0; return 0;
...@@ -2798,7 +2796,7 @@ static int tonga_update_samu_smc_table(struct pp_hwmgr *hwmgr) ...@@ -2798,7 +2796,7 @@ static int tonga_update_samu_smc_table(struct pp_hwmgr *hwmgr)
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_StablePState)) PHM_PlatformCaps_StablePState))
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SAMUDPM_SetEnabledMask, PPSMC_MSG_SAMUDPM_SetEnabledMask,
(uint32_t)(1 << smu_data->smc_state_table.SamuBootLevel)); (uint32_t)(1 << smu_data->smc_state_table.SamuBootLevel));
return 0; return 0;
...@@ -2838,7 +2836,7 @@ int tonga_process_firmware_header(struct pp_hwmgr *hwmgr) ...@@ -2838,7 +2836,7 @@ int tonga_process_firmware_header(struct pp_hwmgr *hwmgr)
int result; int result;
bool error = false; bool error = false;
result = smu7_read_smc_sram_dword(hwmgr->smumgr, result = smu7_read_smc_sram_dword(hwmgr,
SMU72_FIRMWARE_HEADER_LOCATION + SMU72_FIRMWARE_HEADER_LOCATION +
offsetof(SMU72_Firmware_Header, DpmTable), offsetof(SMU72_Firmware_Header, DpmTable),
&tmp, SMC_RAM_END); &tmp, SMC_RAM_END);
...@@ -2848,7 +2846,7 @@ int tonga_process_firmware_header(struct pp_hwmgr *hwmgr) ...@@ -2848,7 +2846,7 @@ int tonga_process_firmware_header(struct pp_hwmgr *hwmgr)
error |= (result != 0); error |= (result != 0);
result = smu7_read_smc_sram_dword(hwmgr->smumgr, result = smu7_read_smc_sram_dword(hwmgr,
SMU72_FIRMWARE_HEADER_LOCATION + SMU72_FIRMWARE_HEADER_LOCATION +
offsetof(SMU72_Firmware_Header, SoftRegisters), offsetof(SMU72_Firmware_Header, SoftRegisters),
&tmp, SMC_RAM_END); &tmp, SMC_RAM_END);
...@@ -2861,7 +2859,7 @@ int tonga_process_firmware_header(struct pp_hwmgr *hwmgr) ...@@ -2861,7 +2859,7 @@ int tonga_process_firmware_header(struct pp_hwmgr *hwmgr)
error |= (result != 0); error |= (result != 0);
result = smu7_read_smc_sram_dword(hwmgr->smumgr, result = smu7_read_smc_sram_dword(hwmgr,
SMU72_FIRMWARE_HEADER_LOCATION + SMU72_FIRMWARE_HEADER_LOCATION +
offsetof(SMU72_Firmware_Header, mcRegisterTable), offsetof(SMU72_Firmware_Header, mcRegisterTable),
&tmp, SMC_RAM_END); &tmp, SMC_RAM_END);
...@@ -2869,7 +2867,7 @@ int tonga_process_firmware_header(struct pp_hwmgr *hwmgr) ...@@ -2869,7 +2867,7 @@ int tonga_process_firmware_header(struct pp_hwmgr *hwmgr)
if (!result) if (!result)
smu_data->smu7_data.mc_reg_table_start = tmp; smu_data->smu7_data.mc_reg_table_start = tmp;
result = smu7_read_smc_sram_dword(hwmgr->smumgr, result = smu7_read_smc_sram_dword(hwmgr,
SMU72_FIRMWARE_HEADER_LOCATION + SMU72_FIRMWARE_HEADER_LOCATION +
offsetof(SMU72_Firmware_Header, FanTable), offsetof(SMU72_Firmware_Header, FanTable),
&tmp, SMC_RAM_END); &tmp, SMC_RAM_END);
...@@ -2879,7 +2877,7 @@ int tonga_process_firmware_header(struct pp_hwmgr *hwmgr) ...@@ -2879,7 +2877,7 @@ int tonga_process_firmware_header(struct pp_hwmgr *hwmgr)
error |= (result != 0); error |= (result != 0);
result = smu7_read_smc_sram_dword(hwmgr->smumgr, result = smu7_read_smc_sram_dword(hwmgr,
SMU72_FIRMWARE_HEADER_LOCATION + SMU72_FIRMWARE_HEADER_LOCATION +
offsetof(SMU72_Firmware_Header, mcArbDramTimingTable), offsetof(SMU72_Firmware_Header, mcArbDramTimingTable),
&tmp, SMC_RAM_END); &tmp, SMC_RAM_END);
...@@ -2889,7 +2887,7 @@ int tonga_process_firmware_header(struct pp_hwmgr *hwmgr) ...@@ -2889,7 +2887,7 @@ int tonga_process_firmware_header(struct pp_hwmgr *hwmgr)
error |= (result != 0); error |= (result != 0);
result = smu7_read_smc_sram_dword(hwmgr->smumgr, result = smu7_read_smc_sram_dword(hwmgr,
SMU72_FIRMWARE_HEADER_LOCATION + SMU72_FIRMWARE_HEADER_LOCATION +
offsetof(SMU72_Firmware_Header, Version), offsetof(SMU72_Firmware_Header, Version),
&tmp, SMC_RAM_END); &tmp, SMC_RAM_END);
...@@ -3258,6 +3256,6 @@ int tonga_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr, ...@@ -3258,6 +3256,6 @@ int tonga_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
levels[i].DownHyst = request->down_hyst; levels[i].DownHyst = request->down_hyst;
} }
return smu7_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels, return smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
array_size, SMC_RAM_END); array_size, SMC_RAM_END);
} }
drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
浏览文件 @ d3f8c0ab
...@@ -37,125 +37,125 @@ ...@@ -37,125 +37,125 @@
#include "smu7_smumgr.h" #include "smu7_smumgr.h"
static int tonga_start_in_protection_mode(struct pp_smumgr *smumgr) static int tonga_start_in_protection_mode(struct pp_hwmgr *hwmgr)
{ {
int result; int result;
/* Assert reset */ /* Assert reset */
SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_RESET_CNTL, rst_reg, 1); SMC_SYSCON_RESET_CNTL, rst_reg, 1);
result = smu7_upload_smu_firmware_image(smumgr); result = smu7_upload_smu_firmware_image(hwmgr);
if (result) if (result)
return result; return result;
/* Clear status */ /* Clear status */
cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
ixSMU_STATUS, 0); ixSMU_STATUS, 0);
/* Enable clock */ /* Enable clock */
SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
/* De-assert reset */ /* De-assert reset */
SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_RESET_CNTL, rst_reg, 0); SMC_SYSCON_RESET_CNTL, rst_reg, 0);
/* Set SMU Auto Start */ /* Set SMU Auto Start */
SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMU_INPUT_DATA, AUTO_START, 1); SMU_INPUT_DATA, AUTO_START, 1);
/* Clear firmware interrupt enable flag */ /* Clear firmware interrupt enable flag */
cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
ixFIRMWARE_FLAGS, 0); ixFIRMWARE_FLAGS, 0);
SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1); RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1);
/** /**
* Call Test SMU message with 0x20000 offset to trigger SMU start * Call Test SMU message with 0x20000 offset to trigger SMU start
*/ */
smu7_send_msg_to_smc_offset(smumgr); smu7_send_msg_to_smc_offset(hwmgr);
/* Wait for done bit to be set */ /* Wait for done bit to be set */
SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
SMU_STATUS, SMU_DONE, 0); SMU_STATUS, SMU_DONE, 0);
/* Check pass/failed indicator */ /* Check pass/failed indicator */
if (1 != SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, if (1 != SMUM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
CGS_IND_REG__SMC, SMU_STATUS, SMU_PASS)) { CGS_IND_REG__SMC, SMU_STATUS, SMU_PASS)) {
pr_err("SMU Firmware start failed\n"); pr_err("SMU Firmware start failed\n");
return -EINVAL; return -EINVAL;
} }
/* Wait for firmware to initialize */ /* Wait for firmware to initialize */
SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1); FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
return 0; return 0;
} }
static int tonga_start_in_non_protection_mode(struct pp_smumgr *smumgr) static int tonga_start_in_non_protection_mode(struct pp_hwmgr *hwmgr)
{ {
int result = 0; int result = 0;
/* wait for smc boot up */ /* wait for smc boot up */
SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
RCU_UC_EVENTS, boot_seq_done, 0); RCU_UC_EVENTS, boot_seq_done, 0);
/*Clear firmware interrupt enable flag*/ /*Clear firmware interrupt enable flag*/
cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
ixFIRMWARE_FLAGS, 0); ixFIRMWARE_FLAGS, 0);
SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_RESET_CNTL, rst_reg, 1); SMC_SYSCON_RESET_CNTL, rst_reg, 1);
result = smu7_upload_smu_firmware_image(smumgr); result = smu7_upload_smu_firmware_image(hwmgr);
if (result != 0) if (result != 0)
return result; return result;
/* Set smc instruct start point at 0x0 */ /* Set smc instruct start point at 0x0 */
smu7_program_jump_on_start(smumgr); smu7_program_jump_on_start(hwmgr);
SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
/*De-assert reset*/ /*De-assert reset*/
SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_RESET_CNTL, rst_reg, 0); SMC_SYSCON_RESET_CNTL, rst_reg, 0);
/* Wait for firmware to initialize */ /* Wait for firmware to initialize */
SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1); FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
return result; return result;
} }
static int tonga_start_smu(struct pp_smumgr *smumgr) static int tonga_start_smu(struct pp_hwmgr *hwmgr)
{ {
int result; int result;
/* Only start SMC if SMC RAM is not running */ /* Only start SMC if SMC RAM is not running */
if (!(smu7_is_smc_ram_running(smumgr) || if (!(smu7_is_smc_ram_running(hwmgr) ||
cgs_is_virtualization_enabled(smumgr->device))) { cgs_is_virtualization_enabled(hwmgr->device))) {
/*Check if SMU is running in protected mode*/ /*Check if SMU is running in protected mode*/
if (0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, if (0 == SMUM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMU_FIRMWARE, SMU_MODE)) { SMU_FIRMWARE, SMU_MODE)) {
result = tonga_start_in_non_protection_mode(smumgr); result = tonga_start_in_non_protection_mode(hwmgr);
if (result) if (result)
return result; return result;
} else { } else {
result = tonga_start_in_protection_mode(smumgr); result = tonga_start_in_protection_mode(hwmgr);
if (result) if (result)
return result; return result;
} }
} }
result = smu7_request_smu_load_fw(smumgr); result = smu7_request_smu_load_fw(hwmgr);
return result; return result;
} }
...@@ -167,7 +167,7 @@ static int tonga_start_smu(struct pp_smumgr *smumgr) ...@@ -167,7 +167,7 @@ static int tonga_start_smu(struct pp_smumgr *smumgr)
* @param smcAddress the address in the SMC RAM to access. * @param smcAddress the address in the SMC RAM to access.
* @param value to write to the SMC SRAM. * @param value to write to the SMC SRAM.
*/ */
static int tonga_smu_init(struct pp_smumgr *smumgr) static int tonga_smu_init(struct pp_hwmgr *hwmgr)
{ {
struct tonga_smumgr *tonga_priv = NULL; struct tonga_smumgr *tonga_priv = NULL;
int i; int i;
...@@ -176,9 +176,9 @@ static int tonga_smu_init(struct pp_smumgr *smumgr) ...@@ -176,9 +176,9 @@ static int tonga_smu_init(struct pp_smumgr *smumgr)
if (tonga_priv == NULL) if (tonga_priv == NULL)
return -ENOMEM; return -ENOMEM;
smumgr->backend = tonga_priv; hwmgr->smumgr->backend = tonga_priv;
if (smu7_init(smumgr)) if (smu7_init(hwmgr))
return -EINVAL; return -EINVAL;
for (i = 0; i < SMU72_MAX_LEVELS_GRAPHICS; i++) for (i = 0; i < SMU72_MAX_LEVELS_GRAPHICS; i++)
......
drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
浏览文件 @ d3f8c0ab
...@@ -53,20 +53,20 @@ ...@@ -53,20 +53,20 @@
#define smnMP0_FW_INTF 0x3010104 #define smnMP0_FW_INTF 0x3010104
#define smnMP1_PUB_CTRL 0x3010b14 #define smnMP1_PUB_CTRL 0x3010b14
static bool vega10_is_smc_ram_running(struct pp_smumgr *smumgr) static bool vega10_is_smc_ram_running(struct pp_hwmgr *hwmgr)
{ {
uint32_t mp1_fw_flags, reg; uint32_t mp1_fw_flags, reg;
reg = soc15_get_register_offset(NBIF_HWID, 0, reg = soc15_get_register_offset(NBIF_HWID, 0,
mmPCIE_INDEX2_BASE_IDX, mmPCIE_INDEX2); mmPCIE_INDEX2_BASE_IDX, mmPCIE_INDEX2);
cgs_write_register(smumgr->device, reg, cgs_write_register(hwmgr->device, reg,
(MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff))); (MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff)));
reg = soc15_get_register_offset(NBIF_HWID, 0, reg = soc15_get_register_offset(NBIF_HWID, 0,
mmPCIE_DATA2_BASE_IDX, mmPCIE_DATA2); mmPCIE_DATA2_BASE_IDX, mmPCIE_DATA2);
mp1_fw_flags = cgs_read_register(smumgr->device, reg); mp1_fw_flags = cgs_read_register(hwmgr->device, reg);
if (mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) if (mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK)
return true; return true;
...@@ -80,20 +80,20 @@ static bool vega10_is_smc_ram_running(struct pp_smumgr *smumgr) ...@@ -80,20 +80,20 @@ static bool vega10_is_smc_ram_running(struct pp_smumgr *smumgr)
* @param smumgr the address of the powerplay hardware manager. * @param smumgr the address of the powerplay hardware manager.
* @return TRUE SMC has responded, FALSE otherwise. * @return TRUE SMC has responded, FALSE otherwise.
*/ */
static uint32_t vega10_wait_for_response(struct pp_smumgr *smumgr) static uint32_t vega10_wait_for_response(struct pp_hwmgr *hwmgr)
{ {
uint32_t reg; uint32_t reg;
if (!vega10_is_smc_ram_running(smumgr)) if (!vega10_is_smc_ram_running(hwmgr))
return -EINVAL; return -EINVAL;
reg = soc15_get_register_offset(MP1_HWID, 0, reg = soc15_get_register_offset(MP1_HWID, 0,
mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90); mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
smum_wait_for_register_unequal(smumgr, reg, smum_wait_for_register_unequal(hwmgr, reg,
0, MP1_C2PMSG_90__CONTENT_MASK); 0, MP1_C2PMSG_90__CONTENT_MASK);
return cgs_read_register(smumgr->device, reg); return cgs_read_register(hwmgr->device, reg);
} }
/* /*
...@@ -102,43 +102,43 @@ static uint32_t vega10_wait_for_response(struct pp_smumgr *smumgr) ...@@ -102,43 +102,43 @@ static uint32_t vega10_wait_for_response(struct pp_smumgr *smumgr)
* @param msg the message to send. * @param msg the message to send.
* @return Always return 0. * @return Always return 0.
*/ */
int vega10_send_msg_to_smc_without_waiting(struct pp_smumgr *smumgr, int vega10_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr,
uint16_t msg) uint16_t msg)
{ {
uint32_t reg; uint32_t reg;
if (!vega10_is_smc_ram_running(smumgr)) if (!vega10_is_smc_ram_running(hwmgr))
return -EINVAL; return -EINVAL;
reg = soc15_get_register_offset(MP1_HWID, 0, reg = soc15_get_register_offset(MP1_HWID, 0,
mmMP1_SMN_C2PMSG_66_BASE_IDX, mmMP1_SMN_C2PMSG_66); mmMP1_SMN_C2PMSG_66_BASE_IDX, mmMP1_SMN_C2PMSG_66);
cgs_write_register(smumgr->device, reg, msg); cgs_write_register(hwmgr->device, reg, msg);
return 0; return 0;
} }
/* /*
* Send a message to the SMC, and wait for its response. * Send a message to the SMC, and wait for its response.
* @param smumgr the address of the powerplay hardware manager. * @param hwmgr the address of the powerplay hardware manager.
* @param msg the message to send. * @param msg the message to send.
* @return Always return 0. * @return Always return 0.
*/ */
int vega10_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg) int vega10_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
{ {
uint32_t reg; uint32_t reg;
if (!vega10_is_smc_ram_running(smumgr)) if (!vega10_is_smc_ram_running(hwmgr))
return -EINVAL; return -EINVAL;
vega10_wait_for_response(smumgr); vega10_wait_for_response(hwmgr);
reg = soc15_get_register_offset(MP1_HWID, 0, reg = soc15_get_register_offset(MP1_HWID, 0,
mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90); mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
cgs_write_register(smumgr->device, reg, 0); cgs_write_register(hwmgr->device, reg, 0);
vega10_send_msg_to_smc_without_waiting(smumgr, msg); vega10_send_msg_to_smc_without_waiting(hwmgr, msg);
if (vega10_wait_for_response(smumgr) != 1) if (vega10_wait_for_response(hwmgr) != 1)
pr_err("Failed to send message: 0x%x\n", msg); pr_err("Failed to send message: 0x%x\n", msg);
return 0; return 0;
...@@ -146,32 +146,32 @@ int vega10_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg) ...@@ -146,32 +146,32 @@ int vega10_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
/* /*
* Send a message to the SMC with parameter * Send a message to the SMC with parameter
* @param smumgr: the address of the powerplay hardware manager. * @param hwmgr: the address of the powerplay hardware manager.
* @param msg: the message to send. * @param msg: the message to send.
* @param parameter: the parameter to send * @param parameter: the parameter to send
* @return Always return 0. * @return Always return 0.
*/ */
int vega10_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, int vega10_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
uint16_t msg, uint32_t parameter) uint16_t msg, uint32_t parameter)
{ {
uint32_t reg; uint32_t reg;
if (!vega10_is_smc_ram_running(smumgr)) if (!vega10_is_smc_ram_running(hwmgr))
return -EINVAL; return -EINVAL;
vega10_wait_for_response(smumgr); vega10_wait_for_response(hwmgr);
reg = soc15_get_register_offset(MP1_HWID, 0, reg = soc15_get_register_offset(MP1_HWID, 0,
mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90); mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
cgs_write_register(smumgr->device, reg, 0); cgs_write_register(hwmgr->device, reg, 0);
reg = soc15_get_register_offset(MP1_HWID, 0, reg = soc15_get_register_offset(MP1_HWID, 0,
mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82); mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82);
cgs_write_register(smumgr->device, reg, parameter); cgs_write_register(hwmgr->device, reg, parameter);
vega10_send_msg_to_smc_without_waiting(smumgr, msg); vega10_send_msg_to_smc_without_waiting(hwmgr, msg);
if (vega10_wait_for_response(smumgr) != 1) if (vega10_wait_for_response(hwmgr) != 1)
pr_err("Failed to send message: 0x%x\n", msg); pr_err("Failed to send message: 0x%x\n", msg);
return 0; return 0;
...@@ -180,51 +180,51 @@ int vega10_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, ...@@ -180,51 +180,51 @@ int vega10_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr,
/* /*
* Send a message to the SMC with parameter, do not wait for response * Send a message to the SMC with parameter, do not wait for response
* @param smumgr: the address of the powerplay hardware manager. * @param hwmgr: the address of the powerplay hardware manager.
* @param msg: the message to send. * @param msg: the message to send.
* @param parameter: the parameter to send * @param parameter: the parameter to send
* @return The response that came from the SMC. * @return The response that came from the SMC.
*/ */
int vega10_send_msg_to_smc_with_parameter_without_waiting( int vega10_send_msg_to_smc_with_parameter_without_waiting(
struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter) struct pp_hwmgr *hwmgr, uint16_t msg, uint32_t parameter)
{ {
uint32_t reg; uint32_t reg;
reg = soc15_get_register_offset(MP1_HWID, 0, reg = soc15_get_register_offset(MP1_HWID, 0,
mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82); mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82);
cgs_write_register(smumgr->device, reg, parameter); cgs_write_register(hwmgr->device, reg, parameter);
return vega10_send_msg_to_smc_without_waiting(smumgr, msg); return vega10_send_msg_to_smc_without_waiting(hwmgr, msg);
} }
/* /*
* Retrieve an argument from SMC. * Retrieve an argument from SMC.
* @param smumgr the address of the powerplay hardware manager. * @param hwmgr the address of the powerplay hardware manager.
* @param arg pointer to store the argument from SMC. * @param arg pointer to store the argument from SMC.
* @return Always return 0. * @return Always return 0.
*/ */
int vega10_read_arg_from_smc(struct pp_smumgr *smumgr, uint32_t *arg) int vega10_read_arg_from_smc(struct pp_hwmgr *hwmgr, uint32_t *arg)
{ {
uint32_t reg; uint32_t reg;
reg = soc15_get_register_offset(MP1_HWID, 0, reg = soc15_get_register_offset(MP1_HWID, 0,
mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82); mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82);
*arg = cgs_read_register(smumgr->device, reg); *arg = cgs_read_register(hwmgr->device, reg);
return 0; return 0;
} }
/* /*
* Copy table from SMC into driver FB * Copy table from SMC into driver FB
* @param smumgr the address of the SMC manager * @param hwmgr the address of the HW manager
* @param table_id the driver's table ID to copy from * @param table_id the driver's table ID to copy from
*/ */
int vega10_copy_table_from_smc(struct pp_smumgr *smumgr, int vega10_copy_table_from_smc(struct pp_hwmgr *hwmgr,
uint8_t *table, int16_t table_id) uint8_t *table, int16_t table_id)
{ {
struct vega10_smumgr *priv = struct vega10_smumgr *priv =
(struct vega10_smumgr *)(smumgr->backend); (struct vega10_smumgr *)(hwmgr->smumgr->backend);
PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE, PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
"Invalid SMU Table ID!", return -EINVAL); "Invalid SMU Table ID!", return -EINVAL);
...@@ -232,16 +232,16 @@ int vega10_copy_table_from_smc(struct pp_smumgr *smumgr, ...@@ -232,16 +232,16 @@ int vega10_copy_table_from_smc(struct pp_smumgr *smumgr,
"Invalid SMU Table version!", return -EINVAL); "Invalid SMU Table version!", return -EINVAL);
PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0, PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
"Invalid SMU Table Length!", return -EINVAL); "Invalid SMU Table Length!", return -EINVAL);
PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(smumgr, PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh,
priv->smu_tables.entry[table_id].table_addr_high) == 0, priv->smu_tables.entry[table_id].table_addr_high) == 0,
"[CopyTableFromSMC] Attempt to Set Dram Addr High Failed!", return -EINVAL); "[CopyTableFromSMC] Attempt to Set Dram Addr High Failed!", return -EINVAL);
PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(smumgr, PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow,
priv->smu_tables.entry[table_id].table_addr_low) == 0, priv->smu_tables.entry[table_id].table_addr_low) == 0,
"[CopyTableFromSMC] Attempt to Set Dram Addr Low Failed!", "[CopyTableFromSMC] Attempt to Set Dram Addr Low Failed!",
return -EINVAL); return -EINVAL);
PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(smumgr, PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram,
priv->smu_tables.entry[table_id].table_id) == 0, priv->smu_tables.entry[table_id].table_id) == 0,
"[CopyTableFromSMC] Attempt to Transfer Table From SMU Failed!", "[CopyTableFromSMC] Attempt to Transfer Table From SMU Failed!",
...@@ -255,14 +255,14 @@ int vega10_copy_table_from_smc(struct pp_smumgr *smumgr, ...@@ -255,14 +255,14 @@ int vega10_copy_table_from_smc(struct pp_smumgr *smumgr,
/* /*
* Copy table from Driver FB into SMC * Copy table from Driver FB into SMC
* @param smumgr the address of the SMC manager * @param hwmgr the address of the HW manager
* @param table_id the table to copy from * @param table_id the table to copy from
*/ */
int vega10_copy_table_to_smc(struct pp_smumgr *smumgr, int vega10_copy_table_to_smc(struct pp_hwmgr *hwmgr,
uint8_t *table, int16_t table_id) uint8_t *table, int16_t table_id)
{ {
struct vega10_smumgr *priv = struct vega10_smumgr *priv =
(struct vega10_smumgr *)(smumgr->backend); (struct vega10_smumgr *)(hwmgr->smumgr->backend);
PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE, PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
"Invalid SMU Table ID!", return -EINVAL); "Invalid SMU Table ID!", return -EINVAL);
...@@ -274,17 +274,17 @@ int vega10_copy_table_to_smc(struct pp_smumgr *smumgr, ...@@ -274,17 +274,17 @@ int vega10_copy_table_to_smc(struct pp_smumgr *smumgr,
memcpy(priv->smu_tables.entry[table_id].table, table, memcpy(priv->smu_tables.entry[table_id].table, table,
priv->smu_tables.entry[table_id].size); priv->smu_tables.entry[table_id].size);
PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(smumgr, PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh,
priv->smu_tables.entry[table_id].table_addr_high) == 0, priv->smu_tables.entry[table_id].table_addr_high) == 0,
"[CopyTableToSMC] Attempt to Set Dram Addr High Failed!", "[CopyTableToSMC] Attempt to Set Dram Addr High Failed!",
return -EINVAL;); return -EINVAL;);
PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(smumgr, PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow,
priv->smu_tables.entry[table_id].table_addr_low) == 0, priv->smu_tables.entry[table_id].table_addr_low) == 0,
"[CopyTableToSMC] Attempt to Set Dram Addr Low Failed!", "[CopyTableToSMC] Attempt to Set Dram Addr Low Failed!",
return -EINVAL); return -EINVAL);
PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(smumgr, PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu,
priv->smu_tables.entry[table_id].table_id) == 0, priv->smu_tables.entry[table_id].table_id) == 0,
"[CopyTableToSMC] Attempt to Transfer Table To SMU Failed!", "[CopyTableToSMC] Attempt to Transfer Table To SMU Failed!",
...@@ -293,87 +293,87 @@ int vega10_copy_table_to_smc(struct pp_smumgr *smumgr, ...@@ -293,87 +293,87 @@ int vega10_copy_table_to_smc(struct pp_smumgr *smumgr,
return 0; return 0;
} }
int vega10_save_vft_table(struct pp_smumgr *smumgr, uint8_t *avfs_table) int vega10_save_vft_table(struct pp_hwmgr *hwmgr, uint8_t *avfs_table)
{ {
PP_ASSERT_WITH_CODE(avfs_table, PP_ASSERT_WITH_CODE(avfs_table,
"No access to SMC AVFS Table", "No access to SMC AVFS Table",
return -EINVAL); return -EINVAL);
return vega10_copy_table_from_smc(smumgr, avfs_table, AVFSTABLE); return vega10_copy_table_from_smc(hwmgr, avfs_table, AVFSTABLE);
} }
int vega10_restore_vft_table(struct pp_smumgr *smumgr, uint8_t *avfs_table) int vega10_restore_vft_table(struct pp_hwmgr *hwmgr, uint8_t *avfs_table)
{ {
PP_ASSERT_WITH_CODE(avfs_table, PP_ASSERT_WITH_CODE(avfs_table,
"No access to SMC AVFS Table", "No access to SMC AVFS Table",
return -EINVAL); return -EINVAL);
return vega10_copy_table_to_smc(smumgr, avfs_table, AVFSTABLE); return vega10_copy_table_to_smc(hwmgr, avfs_table, AVFSTABLE);
} }
int vega10_enable_smc_features(struct pp_smumgr *smumgr, int vega10_enable_smc_features(struct pp_hwmgr *hwmgr,
bool enable, uint32_t feature_mask) bool enable, uint32_t feature_mask)
{ {
int msg = enable ? PPSMC_MSG_EnableSmuFeatures : int msg = enable ? PPSMC_MSG_EnableSmuFeatures :
PPSMC_MSG_DisableSmuFeatures; PPSMC_MSG_DisableSmuFeatures;
return vega10_send_msg_to_smc_with_parameter(smumgr, return vega10_send_msg_to_smc_with_parameter(hwmgr,
msg, feature_mask); msg, feature_mask);
} }
int vega10_get_smc_features(struct pp_smumgr *smumgr, int vega10_get_smc_features(struct pp_hwmgr *hwmgr,
uint32_t *features_enabled) uint32_t *features_enabled)
{ {
if (features_enabled == NULL) if (features_enabled == NULL)
return -EINVAL; return -EINVAL;
if (!vega10_send_msg_to_smc(smumgr, if (!vega10_send_msg_to_smc(hwmgr,
PPSMC_MSG_GetEnabledSmuFeatures)) { PPSMC_MSG_GetEnabledSmuFeatures)) {
vega10_read_arg_from_smc(smumgr, features_enabled); vega10_read_arg_from_smc(hwmgr, features_enabled);
return 0; return 0;
} }
return -EINVAL; return -EINVAL;
} }
int vega10_set_tools_address(struct pp_smumgr *smumgr) int vega10_set_tools_address(struct pp_hwmgr *hwmgr)
{ {
struct vega10_smumgr *priv = struct vega10_smumgr *priv =
(struct vega10_smumgr *)(smumgr->backend); (struct vega10_smumgr *)(hwmgr->smumgr->backend);
if (priv->smu_tables.entry[TOOLSTABLE].table_addr_high || if (priv->smu_tables.entry[TOOLSTABLE].table_addr_high ||
priv->smu_tables.entry[TOOLSTABLE].table_addr_low) { priv->smu_tables.entry[TOOLSTABLE].table_addr_low) {
if (!vega10_send_msg_to_smc_with_parameter(smumgr, if (!vega10_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh,
priv->smu_tables.entry[TOOLSTABLE].table_addr_high)) priv->smu_tables.entry[TOOLSTABLE].table_addr_high))
vega10_send_msg_to_smc_with_parameter(smumgr, vega10_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow,
priv->smu_tables.entry[TOOLSTABLE].table_addr_low); priv->smu_tables.entry[TOOLSTABLE].table_addr_low);
} }
return 0; return 0;
} }
static int vega10_verify_smc_interface(struct pp_smumgr *smumgr) static int vega10_verify_smc_interface(struct pp_hwmgr *hwmgr)
{ {
uint32_t smc_driver_if_version; uint32_t smc_driver_if_version;
struct cgs_system_info sys_info = {0}; struct cgs_system_info sys_info = {0};
uint32_t dev_id; uint32_t dev_id;
uint32_t rev_id; uint32_t rev_id;
PP_ASSERT_WITH_CODE(!vega10_send_msg_to_smc(smumgr, PP_ASSERT_WITH_CODE(!vega10_send_msg_to_smc(hwmgr,
PPSMC_MSG_GetDriverIfVersion), PPSMC_MSG_GetDriverIfVersion),
"Attempt to get SMC IF Version Number Failed!", "Attempt to get SMC IF Version Number Failed!",
return -EINVAL); return -EINVAL);
vega10_read_arg_from_smc(smumgr, &smc_driver_if_version); vega10_read_arg_from_smc(hwmgr, &smc_driver_if_version);
sys_info.size = sizeof(struct cgs_system_info); sys_info.size = sizeof(struct cgs_system_info);
sys_info.info_id = CGS_SYSTEM_INFO_PCIE_DEV; sys_info.info_id = CGS_SYSTEM_INFO_PCIE_DEV;
cgs_query_system_info(smumgr->device, &sys_info); cgs_query_system_info(hwmgr->device, &sys_info);
dev_id = (uint32_t)sys_info.value; dev_id = (uint32_t)sys_info.value;
sys_info.size = sizeof(struct cgs_system_info); sys_info.size = sizeof(struct cgs_system_info);
sys_info.info_id = CGS_SYSTEM_INFO_PCIE_REV; sys_info.info_id = CGS_SYSTEM_INFO_PCIE_REV;
cgs_query_system_info(smumgr->device, &sys_info); cgs_query_system_info(hwmgr->device, &sys_info);
rev_id = (uint32_t)sys_info.value; rev_id = (uint32_t)sys_info.value;
if (!((dev_id == 0x687f) && if (!((dev_id == 0x687f) &&
...@@ -392,7 +392,7 @@ static int vega10_verify_smc_interface(struct pp_smumgr *smumgr) ...@@ -392,7 +392,7 @@ static int vega10_verify_smc_interface(struct pp_smumgr *smumgr)
return 0; return 0;
} }
static int vega10_smu_init(struct pp_smumgr *smumgr) static int vega10_smu_init(struct pp_hwmgr *hwmgr)
{ {
struct vega10_smumgr *priv; struct vega10_smumgr *priv;
uint64_t mc_addr; uint64_t mc_addr;
...@@ -401,7 +401,7 @@ static int vega10_smu_init(struct pp_smumgr *smumgr) ...@@ -401,7 +401,7 @@ static int vega10_smu_init(struct pp_smumgr *smumgr)
int ret; int ret;
struct cgs_firmware_info info = {0}; struct cgs_firmware_info info = {0};
ret = cgs_get_firmware_info(smumgr->device, ret = cgs_get_firmware_info(hwmgr->device,
smu7_convert_fw_type_to_cgs(UCODE_ID_SMU), smu7_convert_fw_type_to_cgs(UCODE_ID_SMU),
&info); &info);
if (ret || !info.kptr) if (ret || !info.kptr)
...@@ -412,10 +412,10 @@ static int vega10_smu_init(struct pp_smumgr *smumgr) ...@@ -412,10 +412,10 @@ static int vega10_smu_init(struct pp_smumgr *smumgr)
if (!priv) if (!priv)
return -ENOMEM; return -ENOMEM;
smumgr->backend = priv; hwmgr->smumgr->backend = priv;
/* allocate space for pptable */ /* allocate space for pptable */
smu_allocate_memory(smumgr->device, smu_allocate_memory(hwmgr->device,
sizeof(PPTable_t), sizeof(PPTable_t),
CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB, CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
PAGE_SIZE, PAGE_SIZE,
...@@ -425,8 +425,8 @@ static int vega10_smu_init(struct pp_smumgr *smumgr) ...@@ -425,8 +425,8 @@ static int vega10_smu_init(struct pp_smumgr *smumgr)
PP_ASSERT_WITH_CODE(kaddr, PP_ASSERT_WITH_CODE(kaddr,
"[vega10_smu_init] Out of memory for pptable.", "[vega10_smu_init] Out of memory for pptable.",
kfree(smumgr->backend); kfree(hwmgr->smumgr->backend);
cgs_free_gpu_mem(smumgr->device, cgs_free_gpu_mem(hwmgr->device,
(cgs_handle_t)handle); (cgs_handle_t)handle);
return -EINVAL); return -EINVAL);
...@@ -441,7 +441,7 @@ static int vega10_smu_init(struct pp_smumgr *smumgr) ...@@ -441,7 +441,7 @@ static int vega10_smu_init(struct pp_smumgr *smumgr)
priv->smu_tables.entry[PPTABLE].handle = handle; priv->smu_tables.entry[PPTABLE].handle = handle;
/* allocate space for watermarks table */ /* allocate space for watermarks table */
smu_allocate_memory(smumgr->device, smu_allocate_memory(hwmgr->device,
sizeof(Watermarks_t), sizeof(Watermarks_t),
CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB, CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
PAGE_SIZE, PAGE_SIZE,
...@@ -451,10 +451,10 @@ static int vega10_smu_init(struct pp_smumgr *smumgr) ...@@ -451,10 +451,10 @@ static int vega10_smu_init(struct pp_smumgr *smumgr)
PP_ASSERT_WITH_CODE(kaddr, PP_ASSERT_WITH_CODE(kaddr,
"[vega10_smu_init] Out of memory for wmtable.", "[vega10_smu_init] Out of memory for wmtable.",
kfree(smumgr->backend); kfree(hwmgr->smumgr->backend);
cgs_free_gpu_mem(smumgr->device, cgs_free_gpu_mem(hwmgr->device,
(cgs_handle_t)priv->smu_tables.entry[PPTABLE].handle); (cgs_handle_t)priv->smu_tables.entry[PPTABLE].handle);
cgs_free_gpu_mem(smumgr->device, cgs_free_gpu_mem(hwmgr->device,
(cgs_handle_t)handle); (cgs_handle_t)handle);
return -EINVAL); return -EINVAL);
...@@ -469,7 +469,7 @@ static int vega10_smu_init(struct pp_smumgr *smumgr) ...@@ -469,7 +469,7 @@ static int vega10_smu_init(struct pp_smumgr *smumgr)
priv->smu_tables.entry[WMTABLE].handle = handle; priv->smu_tables.entry[WMTABLE].handle = handle;
/* allocate space for AVFS table */ /* allocate space for AVFS table */
smu_allocate_memory(smumgr->device, smu_allocate_memory(hwmgr->device,
sizeof(AvfsTable_t), sizeof(AvfsTable_t),
CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB, CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
PAGE_SIZE, PAGE_SIZE,
...@@ -479,12 +479,12 @@ static int vega10_smu_init(struct pp_smumgr *smumgr) ...@@ -479,12 +479,12 @@ static int vega10_smu_init(struct pp_smumgr *smumgr)
PP_ASSERT_WITH_CODE(kaddr, PP_ASSERT_WITH_CODE(kaddr,
"[vega10_smu_init] Out of memory for avfs table.", "[vega10_smu_init] Out of memory for avfs table.",
kfree(smumgr->backend); kfree(hwmgr->smumgr->backend);
cgs_free_gpu_mem(smumgr->device, cgs_free_gpu_mem(hwmgr->device,
(cgs_handle_t)priv->smu_tables.entry[PPTABLE].handle); (cgs_handle_t)priv->smu_tables.entry[PPTABLE].handle);
cgs_free_gpu_mem(smumgr->device, cgs_free_gpu_mem(hwmgr->device,
(cgs_handle_t)priv->smu_tables.entry[WMTABLE].handle); (cgs_handle_t)priv->smu_tables.entry[WMTABLE].handle);
cgs_free_gpu_mem(smumgr->device, cgs_free_gpu_mem(hwmgr->device,
(cgs_handle_t)handle); (cgs_handle_t)handle);
return -EINVAL); return -EINVAL);
...@@ -500,7 +500,7 @@ static int vega10_smu_init(struct pp_smumgr *smumgr) ...@@ -500,7 +500,7 @@ static int vega10_smu_init(struct pp_smumgr *smumgr)
tools_size = 0x19000; tools_size = 0x19000;
if (tools_size) { if (tools_size) {
smu_allocate_memory(smumgr->device, smu_allocate_memory(hwmgr->device,
tools_size, tools_size,
CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB, CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
PAGE_SIZE, PAGE_SIZE,
...@@ -522,7 +522,7 @@ static int vega10_smu_init(struct pp_smumgr *smumgr) ...@@ -522,7 +522,7 @@ static int vega10_smu_init(struct pp_smumgr *smumgr)
} }
/* allocate space for AVFS Fuse table */ /* allocate space for AVFS Fuse table */
smu_allocate_memory(smumgr->device, smu_allocate_memory(hwmgr->device,
sizeof(AvfsFuseOverride_t), sizeof(AvfsFuseOverride_t),
CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB, CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
PAGE_SIZE, PAGE_SIZE,
...@@ -532,16 +532,16 @@ static int vega10_smu_init(struct pp_smumgr *smumgr) ...@@ -532,16 +532,16 @@ static int vega10_smu_init(struct pp_smumgr *smumgr)
PP_ASSERT_WITH_CODE(kaddr, PP_ASSERT_WITH_CODE(kaddr,
"[vega10_smu_init] Out of memory for avfs fuse table.", "[vega10_smu_init] Out of memory for avfs fuse table.",
kfree(smumgr->backend); kfree(hwmgr->smumgr->backend);
cgs_free_gpu_mem(smumgr->device, cgs_free_gpu_mem(hwmgr->device,
(cgs_handle_t)priv->smu_tables.entry[PPTABLE].handle); (cgs_handle_t)priv->smu_tables.entry[PPTABLE].handle);
cgs_free_gpu_mem(smumgr->device, cgs_free_gpu_mem(hwmgr->device,
(cgs_handle_t)priv->smu_tables.entry[WMTABLE].handle); (cgs_handle_t)priv->smu_tables.entry[WMTABLE].handle);
cgs_free_gpu_mem(smumgr->device, cgs_free_gpu_mem(hwmgr->device,
(cgs_handle_t)priv->smu_tables.entry[AVFSTABLE].handle); (cgs_handle_t)priv->smu_tables.entry[AVFSTABLE].handle);
cgs_free_gpu_mem(smumgr->device, cgs_free_gpu_mem(hwmgr->device,
(cgs_handle_t)priv->smu_tables.entry[TOOLSTABLE].handle); (cgs_handle_t)priv->smu_tables.entry[TOOLSTABLE].handle);
cgs_free_gpu_mem(smumgr->device, cgs_free_gpu_mem(hwmgr->device,
(cgs_handle_t)handle); (cgs_handle_t)handle);
return -EINVAL); return -EINVAL);
...@@ -558,36 +558,36 @@ static int vega10_smu_init(struct pp_smumgr *smumgr) ...@@ -558,36 +558,36 @@ static int vega10_smu_init(struct pp_smumgr *smumgr)
return 0; return 0;
} }
static int vega10_smu_fini(struct pp_smumgr *smumgr) static int vega10_smu_fini(struct pp_hwmgr *hwmgr)
{ {
struct vega10_smumgr *priv = struct vega10_smumgr *priv =
(struct vega10_smumgr *)(smumgr->backend); (struct vega10_smumgr *)(hwmgr->smumgr->backend);
if (priv) { if (priv) {
cgs_free_gpu_mem(smumgr->device, cgs_free_gpu_mem(hwmgr->device,
(cgs_handle_t)priv->smu_tables.entry[PPTABLE].handle); (cgs_handle_t)priv->smu_tables.entry[PPTABLE].handle);
cgs_free_gpu_mem(smumgr->device, cgs_free_gpu_mem(hwmgr->device,
(cgs_handle_t)priv->smu_tables.entry[WMTABLE].handle); (cgs_handle_t)priv->smu_tables.entry[WMTABLE].handle);
cgs_free_gpu_mem(smumgr->device, cgs_free_gpu_mem(hwmgr->device,
(cgs_handle_t)priv->smu_tables.entry[AVFSTABLE].handle); (cgs_handle_t)priv->smu_tables.entry[AVFSTABLE].handle);
if (priv->smu_tables.entry[TOOLSTABLE].table) if (priv->smu_tables.entry[TOOLSTABLE].table)
cgs_free_gpu_mem(smumgr->device, cgs_free_gpu_mem(hwmgr->device,
(cgs_handle_t)priv->smu_tables.entry[TOOLSTABLE].handle); (cgs_handle_t)priv->smu_tables.entry[TOOLSTABLE].handle);
cgs_free_gpu_mem(smumgr->device, cgs_free_gpu_mem(hwmgr->device,
(cgs_handle_t)priv->smu_tables.entry[AVFSFUSETABLE].handle); (cgs_handle_t)priv->smu_tables.entry[AVFSFUSETABLE].handle);
kfree(smumgr->backend); kfree(hwmgr->smumgr->backend);
smumgr->backend = NULL; hwmgr->smumgr->backend = NULL;
} }
return 0; return 0;
} }
static int vega10_start_smu(struct pp_smumgr *smumgr) static int vega10_start_smu(struct pp_hwmgr *hwmgr)
{ {
PP_ASSERT_WITH_CODE(!vega10_verify_smc_interface(smumgr), PP_ASSERT_WITH_CODE(!vega10_verify_smc_interface(hwmgr),
"Failed to verify SMC interface!", "Failed to verify SMC interface!",
return -EINVAL); return -EINVAL);
vega10_set_tools_address(smumgr); vega10_set_tools_address(hwmgr);
return 0; return 0;
} }
......
drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.h
浏览文件 @ d3f8c0ab
...@@ -52,19 +52,19 @@ struct vega10_smumgr { ...@@ -52,19 +52,19 @@ struct vega10_smumgr {
struct smu_table_array smu_tables; struct smu_table_array smu_tables;
}; };
int vega10_read_arg_from_smc(struct pp_smumgr *smumgr, uint32_t *arg); int vega10_read_arg_from_smc(struct pp_hwmgr *hwmgr, uint32_t *arg);
int vega10_copy_table_from_smc(struct pp_smumgr *smumgr, int vega10_copy_table_from_smc(struct pp_hwmgr *hwmgr,
uint8_t *table, int16_t table_id); uint8_t *table, int16_t table_id);
int vega10_copy_table_to_smc(struct pp_smumgr *smumgr, int vega10_copy_table_to_smc(struct pp_hwmgr *hwmgr,
uint8_t *table, int16_t table_id); uint8_t *table, int16_t table_id);
int vega10_enable_smc_features(struct pp_smumgr *smumgr, int vega10_enable_smc_features(struct pp_hwmgr *hwmgr,
bool enable, uint32_t feature_mask); bool enable, uint32_t feature_mask);
int vega10_get_smc_features(struct pp_smumgr *smumgr, int vega10_get_smc_features(struct pp_hwmgr *hwmgr,
uint32_t *features_enabled); uint32_t *features_enabled);
int vega10_save_vft_table(struct pp_smumgr *smumgr, uint8_t *avfs_table); int vega10_save_vft_table(struct pp_hwmgr *hwmgr, uint8_t *avfs_table);
int vega10_restore_vft_table(struct pp_smumgr *smumgr, uint8_t *avfs_table); int vega10_restore_vft_table(struct pp_hwmgr *hwmgr, uint8_t *avfs_table);
int vega10_set_tools_address(struct pp_smumgr *smumgr); int vega10_set_tools_address(struct pp_hwmgr *hwmgr);
#endif #endif
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