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提交 d1c4dcfb 编写于 作者: D David Zhang 提交者： Alex Deucher
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drm/amdgpu: Add Fiji smu 7.1.3 headers (v2) 

v2: agd5f: prepare for release
Signed-off-by: NDavid Zhang <david1.zhang@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>
上级 aa8a3b53
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drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h 0 → 100644
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/*
* SMU_7_1_3 Register documentation
*
* Copyright (C) 2014 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef SMU_7_1_3_D_H
#define SMU_7_1_3_D_H
#define mmGCK_SMC_IND_INDEX 0x80
#define mmGCK0_GCK_SMC_IND_INDEX 0x80
#define mmGCK1_GCK_SMC_IND_INDEX 0x82
#define mmGCK2_GCK_SMC_IND_INDEX 0x84
#define mmGCK3_GCK_SMC_IND_INDEX 0x86
#define mmGCK_SMC_IND_DATA 0x81
#define mmGCK0_GCK_SMC_IND_DATA 0x81
#define mmGCK1_GCK_SMC_IND_DATA 0x83
#define mmGCK2_GCK_SMC_IND_DATA 0x85
#define mmGCK3_GCK_SMC_IND_DATA 0x87
#define ixGCK_MCLK_FUSES 0xc0500008
#define ixCG_DCLK_CNTL 0xc050009c
#define ixCG_DCLK_STATUS 0xc05000a0
#define ixCG_VCLK_CNTL 0xc05000a4
#define ixCG_VCLK_STATUS 0xc05000a8
#define ixCG_ECLK_CNTL 0xc05000ac
#define ixCG_ECLK_STATUS 0xc05000b0
#define ixCG_ACLK_CNTL 0xc05000dc
#define ixCG_MCLK_CNTL 0xc0500120
#define ixCG_MCLK_STATUS 0xc0500124
#define ixGCK_DFS_BYPASS_CNTL 0xc0500118
#define ixCG_SPLL_FUNC_CNTL 0xc0500140
#define ixCG_SPLL_FUNC_CNTL_2 0xc0500144
#define ixCG_SPLL_FUNC_CNTL_3 0xc0500148
#define ixCG_SPLL_FUNC_CNTL_4 0xc050014c
#define ixCG_SPLL_FUNC_CNTL_5 0xc0500150
#define ixCG_SPLL_FUNC_CNTL_6 0xc0500154
#define ixCG_SPLL_FUNC_CNTL_7 0xc0500158
#define ixSPLL_CNTL_MODE 0xc0500160
#define ixCG_SPLL_SPREAD_SPECTRUM 0xc0500164
#define ixCG_SPLL_SPREAD_SPECTRUM_2 0xc0500168
#define ixMPLL_BYPASSCLK_SEL 0xc050019c
#define ixCG_CLKPIN_CNTL 0xc05001a0
#define ixCG_CLKPIN_CNTL_2 0xc05001a4
#define ixCG_CLKPIN_CNTL_DC 0xc0500204
#define ixTHM_CLK_CNTL 0xc05001a8
#define ixMISC_CLK_CTRL 0xc05001ac
#define ixGCK_PLL_TEST_CNTL 0xc05001c0
#define ixGCK_PLL_TEST_CNTL_2 0xc05001c4
#define ixGCK_ADFS_CLK_BYPASS_CNTL1 0xc05001c8
#define mmSMC_IND_INDEX 0x80
#define mmSMC0_SMC_IND_INDEX 0x80
#define mmSMC1_SMC_IND_INDEX 0x82
#define mmSMC2_SMC_IND_INDEX 0x84
#define mmSMC3_SMC_IND_INDEX 0x86
#define mmSMC_IND_DATA 0x81
#define mmSMC0_SMC_IND_DATA 0x81
#define mmSMC1_SMC_IND_DATA 0x83
#define mmSMC2_SMC_IND_DATA 0x85
#define mmSMC3_SMC_IND_DATA 0x87
#define mmSMC_IND_INDEX_0 0x80
#define mmSMC_IND_DATA_0 0x81
#define mmSMC_IND_INDEX_1 0x82
#define mmSMC_IND_DATA_1 0x83
#define mmSMC_IND_INDEX_2 0x84
#define mmSMC_IND_DATA_2 0x85
#define mmSMC_IND_INDEX_3 0x86
#define mmSMC_IND_DATA_3 0x87
#define mmSMC_IND_INDEX_4 0x88
#define mmSMC_IND_DATA_4 0x89
#define mmSMC_IND_INDEX_5 0x8a
#define mmSMC_IND_DATA_5 0x8b
#define mmSMC_IND_INDEX_6 0x8c
#define mmSMC_IND_DATA_6 0x8d
#define mmSMC_IND_INDEX_7 0x8e
#define mmSMC_IND_DATA_7 0x8f
#define mmSMC_IND_ACCESS_CNTL 0x92
#define mmSMC_MESSAGE_0 0x94
#define mmSMC_RESP_0 0x95
#define mmSMC_MESSAGE_1 0x96
#define mmSMC_RESP_1 0x97
#define mmSMC_MESSAGE_2 0x98
#define mmSMC_RESP_2 0x99
#define mmSMC_MESSAGE_3 0x9a
#define mmSMC_RESP_3 0x9b
#define mmSMC_MESSAGE_4 0x9c
#define mmSMC_RESP_4 0x9d
#define mmSMC_MESSAGE_5 0x9e
#define mmSMC_RESP_5 0x9f
#define mmSMC_MESSAGE_6 0xa0
#define mmSMC_RESP_6 0xa1
#define mmSMC_MESSAGE_7 0xa2
#define mmSMC_RESP_7 0xa3
#define mmSMC_MSG_ARG_0 0xa4
#define mmSMC_MSG_ARG_1 0xa5
#define mmSMC_MSG_ARG_2 0xa6
#define mmSMC_MSG_ARG_3 0xa7
#define mmSMC_MSG_ARG_4 0xa8
#define mmSMC_MSG_ARG_5 0xa9
#define mmSMC_MSG_ARG_6 0xaa
#define mmSMC_MSG_ARG_7 0xab
#define mmSMC_MESSAGE_8 0xb5
#define mmSMC_RESP_8 0xb6
#define mmSMC_MESSAGE_9 0xb7
#define mmSMC_RESP_9 0xb8
#define mmSMC_MESSAGE_10 0xb9
#define mmSMC_RESP_10 0xba
#define mmSMC_MESSAGE_11 0xbb
#define mmSMC_RESP_11 0xbc
#define mmSMC_MSG_ARG_8 0xbd
#define mmSMC_MSG_ARG_9 0xbe
#define mmSMC_MSG_ARG_10 0xbf
#define mmSMC_MSG_ARG_11 0x93
#define ixSMC_SYSCON_RESET_CNTL 0x80000000
#define ixSMC_SYSCON_CLOCK_CNTL_0 0x80000004
#define ixSMC_SYSCON_CLOCK_CNTL_1 0x80000008
#define ixSMC_SYSCON_CLOCK_CNTL_2 0x8000000c
#define ixSMC_SYSCON_MISC_CNTL 0x80000010
#define ixSMC_SYSCON_MSG_ARG_0 0x80000068
#define ixSMC_PC_C 0x80000370
#define ixSMC_SCRATCH9 0x80000424
#define mmGPIOPAD_SW_INT_STAT 0x180
#define mmGPIOPAD_STRENGTH 0x181
#define mmGPIOPAD_MASK 0x182
#define mmGPIOPAD_A 0x183
#define mmGPIOPAD_EN 0x184
#define mmGPIOPAD_Y 0x185
#define mmGPIOPAD_PINSTRAPS 0x186
#define mmGPIOPAD_INT_STAT_EN 0x187
#define mmGPIOPAD_INT_STAT 0x188
#define mmGPIOPAD_INT_STAT_AK 0x189
#define mmGPIOPAD_INT_EN 0x18a
#define mmGPIOPAD_INT_TYPE 0x18b
#define mmGPIOPAD_INT_POLARITY 0x18c
#define mmGPIOPAD_EXTERN_TRIG_CNTL 0x18d
#define mmGPIOPAD_RCVR_SEL 0x191
#define mmGPIOPAD_PU_EN 0x192
#define mmGPIOPAD_PD_EN 0x193
#define mmCG_FPS_CNT 0x1b6
#define mmSMU_IND_INDEX_0 0x1a6
#define mmSMU_IND_DATA_0 0x1a7
#define mmSMU_IND_INDEX_1 0x1a8
#define mmSMU_IND_DATA_1 0x1a9
#define mmSMU_IND_INDEX_2 0x1aa
#define mmSMU_IND_DATA_2 0x1ab
#define mmSMU_IND_INDEX_3 0x1ac
#define mmSMU_IND_DATA_3 0x1ad
#define mmSMU_IND_INDEX_4 0x1ae
#define mmSMU_IND_DATA_4 0x1af
#define mmSMU_IND_INDEX_5 0x1b0
#define mmSMU_IND_DATA_5 0x1b1
#define mmSMU_IND_INDEX_6 0x1b2
#define mmSMU_IND_DATA_6 0x1b3
#define mmSMU_IND_INDEX_7 0x1b4
#define mmSMU_IND_DATA_7 0x1b5
#define mmSMU_SMC_IND_INDEX 0x80
#define mmSMU0_SMU_SMC_IND_INDEX 0x80
#define mmSMU1_SMU_SMC_IND_INDEX 0x82
#define mmSMU2_SMU_SMC_IND_INDEX 0x84
#define mmSMU3_SMU_SMC_IND_INDEX 0x86
#define mmSMU_SMC_IND_DATA 0x81
#define mmSMU0_SMU_SMC_IND_DATA 0x81
#define mmSMU1_SMU_SMC_IND_DATA 0x83
#define mmSMU2_SMU_SMC_IND_DATA 0x85
#define mmSMU3_SMU_SMC_IND_DATA 0x87
#define ixRCU_UC_EVENTS 0xc0000004
#define ixRCU_MISC_CTRL 0xc0000010
#define ixRCU_VIRT_RESET_REQ 0xc0000024
#define ixCC_RCU_FUSES 0xc00c0000
#define ixCC_SMU_MISC_FUSES 0xc00c0004
#define ixCC_SCLK_VID_FUSES 0xc00c0008
#define ixCC_GIO_IOCCFG_FUSES 0xc00c000c
#define ixCC_GIO_IOC_FUSES 0xc00c0010
#define ixCC_SMU_TST_EFUSE1_MISC 0xc00c001c
#define ixCC_TST_ID_STRAPS 0xc00c0020
#define ixCC_FCTRL_FUSES 0xc00c0024
#define ixCC_HARVEST_FUSES 0xc00c0028
#define ixSMU_MAIN_PLL_OP_FREQ 0xe0003020
#define ixSMU_STATUS 0xe0003088
#define ixSMU_FIRMWARE 0xe00030a4
#define ixSMU_INPUT_DATA 0xe00030b8
#define ixSMU_EFUSE_0 0xc0100000
#define ixFIRMWARE_FLAGS 0x3f000
#define ixTDC_STATUS 0x3f004
#define ixTDC_MV_AVERAGE 0x3f008
#define ixTDC_VRM_LIMIT 0x3f00c
#define ixFEATURE_STATUS 0x3f010
#define ixENTITY_TEMPERATURES_1 0x3f014
#define ixMCARB_DRAM_TIMING_TABLE_1 0x3f018
#define ixMCARB_DRAM_TIMING_TABLE_2 0x3f01c
#define ixMCARB_DRAM_TIMING_TABLE_3 0x3f020
#define ixMCARB_DRAM_TIMING_TABLE_4 0x3f024
#define ixMCARB_DRAM_TIMING_TABLE_5 0x3f028
#define ixMCARB_DRAM_TIMING_TABLE_6 0x3f02c
#define ixMCARB_DRAM_TIMING_TABLE_7 0x3f030
#define ixMCARB_DRAM_TIMING_TABLE_8 0x3f034
#define ixMCARB_DRAM_TIMING_TABLE_9 0x3f038
#define ixMCARB_DRAM_TIMING_TABLE_10 0x3f03c
#define ixMCARB_DRAM_TIMING_TABLE_11 0x3f040
#define ixMCARB_DRAM_TIMING_TABLE_12 0x3f044
#define ixMCARB_DRAM_TIMING_TABLE_13 0x3f048
#define ixMCARB_DRAM_TIMING_TABLE_14 0x3f04c
#define ixMCARB_DRAM_TIMING_TABLE_15 0x3f050
#define ixMCARB_DRAM_TIMING_TABLE_16 0x3f054
#define ixMCARB_DRAM_TIMING_TABLE_17 0x3f058
#define ixMCARB_DRAM_TIMING_TABLE_18 0x3f05c
#define ixMCARB_DRAM_TIMING_TABLE_19 0x3f060
#define ixMCARB_DRAM_TIMING_TABLE_20 0x3f064
#define ixMCARB_DRAM_TIMING_TABLE_21 0x3f068
#define ixMCARB_DRAM_TIMING_TABLE_22 0x3f06c
#define ixMCARB_DRAM_TIMING_TABLE_23 0x3f070
#define ixMCARB_DRAM_TIMING_TABLE_24 0x3f074
#define ixMCARB_DRAM_TIMING_TABLE_25 0x3f078
#define ixMCARB_DRAM_TIMING_TABLE_26 0x3f07c
#define ixMCARB_DRAM_TIMING_TABLE_27 0x3f080
#define ixMCARB_DRAM_TIMING_TABLE_28 0x3f084
#define ixMCARB_DRAM_TIMING_TABLE_29 0x3f088
#define ixMCARB_DRAM_TIMING_TABLE_30 0x3f08c
#define ixMCARB_DRAM_TIMING_TABLE_31 0x3f090
#define ixMCARB_DRAM_TIMING_TABLE_32 0x3f094
#define ixMCARB_DRAM_TIMING_TABLE_33 0x3f098
#define ixMCARB_DRAM_TIMING_TABLE_34 0x3f09c
#define ixMCARB_DRAM_TIMING_TABLE_35 0x3f0a0
#define ixMCARB_DRAM_TIMING_TABLE_36 0x3f0a4
#define ixMCARB_DRAM_TIMING_TABLE_37 0x3f0a8
#define ixMCARB_DRAM_TIMING_TABLE_38 0x3f0ac
#define ixMCARB_DRAM_TIMING_TABLE_39 0x3f0b0
#define ixMCARB_DRAM_TIMING_TABLE_40 0x3f0b4
#define ixMCARB_DRAM_TIMING_TABLE_41 0x3f0b8
#define ixMCARB_DRAM_TIMING_TABLE_42 0x3f0bc
#define ixMCARB_DRAM_TIMING_TABLE_43 0x3f0c0
#define ixMCARB_DRAM_TIMING_TABLE_44 0x3f0c4
#define ixMCARB_DRAM_TIMING_TABLE_45 0x3f0c8
#define ixMCARB_DRAM_TIMING_TABLE_46 0x3f0cc
#define ixMCARB_DRAM_TIMING_TABLE_47 0x3f0d0
#define ixMCARB_DRAM_TIMING_TABLE_48 0x3f0d4
#define ixMCARB_DRAM_TIMING_TABLE_49 0x3f0d8
#define ixMCARB_DRAM_TIMING_TABLE_50 0x3f0dc
#define ixMCARB_DRAM_TIMING_TABLE_51 0x3f0e0
#define ixMCARB_DRAM_TIMING_TABLE_52 0x3f0e4
#define ixMCARB_DRAM_TIMING_TABLE_53 0x3f0e8
#define ixMCARB_DRAM_TIMING_TABLE_54 0x3f0ec
#define ixMCARB_DRAM_TIMING_TABLE_55 0x3f0f0
#define ixMCARB_DRAM_TIMING_TABLE_56 0x3f0f4
#define ixMCARB_DRAM_TIMING_TABLE_57 0x3f0f8
#define ixMCARB_DRAM_TIMING_TABLE_58 0x3f0fc
#define ixMCARB_DRAM_TIMING_TABLE_59 0x3f100
#define ixMCARB_DRAM_TIMING_TABLE_60 0x3f104
#define ixMCARB_DRAM_TIMING_TABLE_61 0x3f108
#define ixMCARB_DRAM_TIMING_TABLE_62 0x3f10c
#define ixMCARB_DRAM_TIMING_TABLE_63 0x3f110
#define ixMCARB_DRAM_TIMING_TABLE_64 0x3f114
#define ixMCARB_DRAM_TIMING_TABLE_65 0x3f118
#define ixMCARB_DRAM_TIMING_TABLE_66 0x3f11c
#define ixMCARB_DRAM_TIMING_TABLE_67 0x3f120
#define ixMCARB_DRAM_TIMING_TABLE_68 0x3f124
#define ixMCARB_DRAM_TIMING_TABLE_69 0x3f128
#define ixMCARB_DRAM_TIMING_TABLE_70 0x3f12c
#define ixMCARB_DRAM_TIMING_TABLE_71 0x3f130
#define ixMCARB_DRAM_TIMING_TABLE_72 0x3f134
#define ixMCARB_DRAM_TIMING_TABLE_73 0x3f138
#define ixMCARB_DRAM_TIMING_TABLE_74 0x3f13c
#define ixMCARB_DRAM_TIMING_TABLE_75 0x3f140
#define ixMCARB_DRAM_TIMING_TABLE_76 0x3f144
#define ixMCARB_DRAM_TIMING_TABLE_77 0x3f148
#define ixMCARB_DRAM_TIMING_TABLE_78 0x3f14c
#define ixMCARB_DRAM_TIMING_TABLE_79 0x3f150
#define ixMCARB_DRAM_TIMING_TABLE_80 0x3f154
#define ixMCARB_DRAM_TIMING_TABLE_81 0x3f158
#define ixMCARB_DRAM_TIMING_TABLE_82 0x3f15c
#define ixMCARB_DRAM_TIMING_TABLE_83 0x3f160
#define ixMCARB_DRAM_TIMING_TABLE_84 0x3f164
#define ixMCARB_DRAM_TIMING_TABLE_85 0x3f168
#define ixMCARB_DRAM_TIMING_TABLE_86 0x3f16c
#define ixMCARB_DRAM_TIMING_TABLE_87 0x3f170
#define ixMCARB_DRAM_TIMING_TABLE_88 0x3f174
#define ixMCARB_DRAM_TIMING_TABLE_89 0x3f178
#define ixMCARB_DRAM_TIMING_TABLE_90 0x3f17c
#define ixMCARB_DRAM_TIMING_TABLE_91 0x3f180
#define ixMCARB_DRAM_TIMING_TABLE_92 0x3f184
#define ixMCARB_DRAM_TIMING_TABLE_93 0x3f188
#define ixMCARB_DRAM_TIMING_TABLE_94 0x3f18c
#define ixMCARB_DRAM_TIMING_TABLE_95 0x3f190
#define ixMCARB_DRAM_TIMING_TABLE_96 0x3f194
#define ixDPM_TABLE_1 0x3f198
#define ixDPM_TABLE_2 0x3f19c
#define ixDPM_TABLE_3 0x3f1a0
#define ixDPM_TABLE_4 0x3f1a4
#define ixDPM_TABLE_5 0x3f1a8
#define ixDPM_TABLE_6 0x3f1ac
#define ixDPM_TABLE_7 0x3f1b0
#define ixDPM_TABLE_8 0x3f1b4
#define ixDPM_TABLE_9 0x3f1b8
#define ixDPM_TABLE_10 0x3f1bc
#define ixDPM_TABLE_11 0x3f1c0
#define ixDPM_TABLE_12 0x3f1c4
#define ixDPM_TABLE_13 0x3f1c8
#define ixDPM_TABLE_14 0x3f1cc
#define ixDPM_TABLE_15 0x3f1d0
#define ixDPM_TABLE_16 0x3f1d4
#define ixDPM_TABLE_17 0x3f1d8
#define ixDPM_TABLE_18 0x3f1dc
#define ixDPM_TABLE_19 0x3f1e0
#define ixDPM_TABLE_20 0x3f1e4
#define ixDPM_TABLE_21 0x3f1e8
#define ixDPM_TABLE_22 0x3f1ec
#define ixDPM_TABLE_23 0x3f1f0
#define ixDPM_TABLE_24 0x3f1f4
#define ixDPM_TABLE_25 0x3f1f8
#define ixDPM_TABLE_26 0x3f1fc
#define ixDPM_TABLE_27 0x3f200
#define ixDPM_TABLE_28 0x3f204
#define ixDPM_TABLE_29 0x3f208
#define ixDPM_TABLE_30 0x3f20c
#define ixDPM_TABLE_31 0x3f210
#define ixDPM_TABLE_32 0x3f214
#define ixDPM_TABLE_33 0x3f218
#define ixDPM_TABLE_34 0x3f21c
#define ixDPM_TABLE_35 0x3f220
#define ixDPM_TABLE_36 0x3f224
#define ixDPM_TABLE_37 0x3f228
#define ixDPM_TABLE_38 0x3f22c
#define ixDPM_TABLE_39 0x3f230
#define ixDPM_TABLE_40 0x3f234
#define ixDPM_TABLE_41 0x3f238
#define ixDPM_TABLE_42 0x3f23c
#define ixDPM_TABLE_43 0x3f240
#define ixDPM_TABLE_44 0x3f244
#define ixDPM_TABLE_45 0x3f248
#define ixDPM_TABLE_46 0x3f24c
#define ixDPM_TABLE_47 0x3f250
#define ixDPM_TABLE_48 0x3f254
#define ixDPM_TABLE_49 0x3f258
#define ixDPM_TABLE_50 0x3f25c
#define ixDPM_TABLE_51 0x3f260
#define ixDPM_TABLE_52 0x3f264
#define ixDPM_TABLE_53 0x3f268
#define ixDPM_TABLE_54 0x3f26c
#define ixDPM_TABLE_55 0x3f270
#define ixDPM_TABLE_56 0x3f274
#define ixDPM_TABLE_57 0x3f278
#define ixDPM_TABLE_58 0x3f27c
#define ixDPM_TABLE_59 0x3f280
#define ixDPM_TABLE_60 0x3f284
#define ixDPM_TABLE_61 0x3f288
#define ixDPM_TABLE_62 0x3f28c
#define ixDPM_TABLE_63 0x3f290
#define ixDPM_TABLE_64 0x3f294
#define ixDPM_TABLE_65 0x3f298
#define ixDPM_TABLE_66 0x3f29c
#define ixDPM_TABLE_67 0x3f2a0
#define ixDPM_TABLE_68 0x3f2a4
#define ixDPM_TABLE_69 0x3f2a8
#define ixDPM_TABLE_70 0x3f2ac
#define ixDPM_TABLE_71 0x3f2b0
#define ixDPM_TABLE_72 0x3f2b4
#define ixDPM_TABLE_73 0x3f2b8
#define ixDPM_TABLE_74 0x3f2bc
#define ixDPM_TABLE_75 0x3f2c0
#define ixDPM_TABLE_76 0x3f2c4
#define ixDPM_TABLE_77 0x3f2c8
#define ixDPM_TABLE_78 0x3f2cc
#define ixDPM_TABLE_79 0x3f2d0
#define ixDPM_TABLE_80 0x3f2d4
#define ixDPM_TABLE_81 0x3f2d8
#define ixDPM_TABLE_82 0x3f2dc
#define ixDPM_TABLE_83 0x3f2e0
#define ixDPM_TABLE_84 0x3f2e4
#define ixDPM_TABLE_85 0x3f2e8
#define ixDPM_TABLE_86 0x3f2ec
#define ixDPM_TABLE_87 0x3f2f0
#define ixDPM_TABLE_88 0x3f2f4
#define ixDPM_TABLE_89 0x3f2f8
#define ixDPM_TABLE_90 0x3f2fc
#define ixDPM_TABLE_91 0x3f300
#define ixDPM_TABLE_92 0x3f304
#define ixDPM_TABLE_93 0x3f308
#define ixDPM_TABLE_94 0x3f30c
#define ixDPM_TABLE_95 0x3f310
#define ixDPM_TABLE_96 0x3f314
#define ixDPM_TABLE_97 0x3f318
#define ixDPM_TABLE_98 0x3f31c
#define ixDPM_TABLE_99 0x3f320
#define ixDPM_TABLE_100 0x3f324
#define ixDPM_TABLE_101 0x3f328
#define ixDPM_TABLE_102 0x3f32c
#define ixDPM_TABLE_103 0x3f330
#define ixDPM_TABLE_104 0x3f334
#define ixDPM_TABLE_105 0x3f338
#define ixDPM_TABLE_106 0x3f33c
#define ixDPM_TABLE_107 0x3f340
#define ixDPM_TABLE_108 0x3f344
#define ixDPM_TABLE_109 0x3f348
#define ixDPM_TABLE_110 0x3f34c
#define ixDPM_TABLE_111 0x3f350
#define ixDPM_TABLE_112 0x3f354
#define ixDPM_TABLE_113 0x3f358
#define ixDPM_TABLE_114 0x3f35c
#define ixDPM_TABLE_115 0x3f360
#define ixDPM_TABLE_116 0x3f364
#define ixDPM_TABLE_117 0x3f368
#define ixDPM_TABLE_118 0x3f36c
#define ixDPM_TABLE_119 0x3f370
#define ixDPM_TABLE_120 0x3f374
#define ixDPM_TABLE_121 0x3f378
#define ixDPM_TABLE_122 0x3f37c
#define ixDPM_TABLE_123 0x3f380
#define ixDPM_TABLE_124 0x3f384
#define ixDPM_TABLE_125 0x3f388
#define ixDPM_TABLE_126 0x3f38c
#define ixDPM_TABLE_127 0x3f390
#define ixDPM_TABLE_128 0x3f394
#define ixDPM_TABLE_129 0x3f398
#define ixDPM_TABLE_130 0x3f39c
#define ixDPM_TABLE_131 0x3f3a0
#define ixDPM_TABLE_132 0x3f3a4
#define ixDPM_TABLE_133 0x3f3a8
#define ixDPM_TABLE_134 0x3f3ac
#define ixDPM_TABLE_135 0x3f3b0
#define ixDPM_TABLE_136 0x3f3b4
#define ixDPM_TABLE_137 0x3f3b8
#define ixDPM_TABLE_138 0x3f3bc
#define ixDPM_TABLE_139 0x3f3c0
#define ixDPM_TABLE_140 0x3f3c4
#define ixDPM_TABLE_141 0x3f3c8
#define ixDPM_TABLE_142 0x3f3cc
#define ixDPM_TABLE_143 0x3f3d0
#define ixDPM_TABLE_144 0x3f3d4
#define ixDPM_TABLE_145 0x3f3d8
#define ixDPM_TABLE_146 0x3f3dc
#define ixDPM_TABLE_147 0x3f3e0
#define ixDPM_TABLE_148 0x3f3e4
#define ixDPM_TABLE_149 0x3f3e8
#define ixDPM_TABLE_150 0x3f3ec
#define ixDPM_TABLE_151 0x3f3f0
#define ixDPM_TABLE_152 0x3f3f4
#define ixDPM_TABLE_153 0x3f3f8
#define ixDPM_TABLE_154 0x3f3fc
#define ixDPM_TABLE_155 0x3f400
#define ixDPM_TABLE_156 0x3f404
#define ixDPM_TABLE_157 0x3f408
#define ixDPM_TABLE_158 0x3f40c
#define ixDPM_TABLE_159 0x3f410
#define ixDPM_TABLE_160 0x3f414
#define ixDPM_TABLE_161 0x3f418
#define ixDPM_TABLE_162 0x3f41c
#define ixDPM_TABLE_163 0x3f420
#define ixDPM_TABLE_164 0x3f424
#define ixDPM_TABLE_165 0x3f428
#define ixDPM_TABLE_166 0x3f42c
#define ixDPM_TABLE_167 0x3f430
#define ixDPM_TABLE_168 0x3f434
#define ixDPM_TABLE_169 0x3f438
#define ixDPM_TABLE_170 0x3f43c
#define ixDPM_TABLE_171 0x3f440
#define ixDPM_TABLE_172 0x3f444
#define ixDPM_TABLE_173 0x3f448
#define ixDPM_TABLE_174 0x3f44c
#define ixDPM_TABLE_175 0x3f450
#define ixDPM_TABLE_176 0x3f454
#define ixDPM_TABLE_177 0x3f458
#define ixDPM_TABLE_178 0x3f45c
#define ixDPM_TABLE_179 0x3f460
#define ixDPM_TABLE_180 0x3f464
#define ixDPM_TABLE_181 0x3f468
#define ixDPM_TABLE_182 0x3f46c
#define ixDPM_TABLE_183 0x3f470
#define ixDPM_TABLE_184 0x3f474
#define ixDPM_TABLE_185 0x3f478
#define ixDPM_TABLE_186 0x3f47c
#define ixDPM_TABLE_187 0x3f480
#define ixDPM_TABLE_188 0x3f484
#define ixDPM_TABLE_189 0x3f488
#define ixDPM_TABLE_190 0x3f48c
#define ixDPM_TABLE_191 0x3f490
#define ixDPM_TABLE_192 0x3f494
#define ixDPM_TABLE_193 0x3f498
#define ixDPM_TABLE_194 0x3f49c
#define ixDPM_TABLE_195 0x3f4a0
#define ixDPM_TABLE_196 0x3f4a4
#define ixDPM_TABLE_197 0x3f4a8
#define ixDPM_TABLE_198 0x3f4ac
#define ixDPM_TABLE_199 0x3f4b0
#define ixDPM_TABLE_200 0x3f4b4
#define ixDPM_TABLE_201 0x3f4b8
#define ixDPM_TABLE_202 0x3f4bc
#define ixDPM_TABLE_203 0x3f4c0
#define ixDPM_TABLE_204 0x3f4c4
#define ixDPM_TABLE_205 0x3f4c8
#define ixDPM_TABLE_206 0x3f4cc
#define ixDPM_TABLE_207 0x3f4d0
#define ixDPM_TABLE_208 0x3f4d4
#define ixDPM_TABLE_209 0x3f4d8
#define ixDPM_TABLE_210 0x3f4dc
#define ixDPM_TABLE_211 0x3f4e0
#define ixDPM_TABLE_212 0x3f4e4
#define ixDPM_TABLE_213 0x3f4e8
#define ixDPM_TABLE_214 0x3f4ec
#define ixDPM_TABLE_215 0x3f4f0
#define ixDPM_TABLE_216 0x3f4f4
#define ixDPM_TABLE_217 0x3f4f8
#define ixDPM_TABLE_218 0x3f4fc
#define ixDPM_TABLE_219 0x3f500
#define ixDPM_TABLE_220 0x3f504
#define ixDPM_TABLE_221 0x3f508
#define ixDPM_TABLE_222 0x3f50c
#define ixDPM_TABLE_223 0x3f510
#define ixDPM_TABLE_224 0x3f514
#define ixDPM_TABLE_225 0x3f518
#define ixDPM_TABLE_226 0x3f51c
#define ixDPM_TABLE_227 0x3f520
#define ixDPM_TABLE_228 0x3f524
#define ixDPM_TABLE_229 0x3f528
#define ixDPM_TABLE_230 0x3f52c
#define ixDPM_TABLE_231 0x3f530
#define ixDPM_TABLE_232 0x3f534
#define ixDPM_TABLE_233 0x3f538
#define ixDPM_TABLE_234 0x3f53c
#define ixDPM_TABLE_235 0x3f540
#define ixDPM_TABLE_236 0x3f544
#define ixDPM_TABLE_237 0x3f548
#define ixDPM_TABLE_238 0x3f54c
#define ixDPM_TABLE_239 0x3f550
#define ixDPM_TABLE_240 0x3f554
#define ixDPM_TABLE_241 0x3f558
#define ixDPM_TABLE_242 0x3f55c
#define ixDPM_TABLE_243 0x3f560
#define ixDPM_TABLE_244 0x3f564
#define ixDPM_TABLE_245 0x3f568
#define ixDPM_TABLE_246 0x3f56c
#define ixDPM_TABLE_247 0x3f570
#define ixDPM_TABLE_248 0x3f574
#define ixDPM_TABLE_249 0x3f578
#define ixDPM_TABLE_250 0x3f57c
#define ixDPM_TABLE_251 0x3f580
#define ixDPM_TABLE_252 0x3f584
#define ixDPM_TABLE_253 0x3f588
#define ixDPM_TABLE_254 0x3f58c
#define ixDPM_TABLE_255 0x3f590
#define ixDPM_TABLE_256 0x3f594
#define ixDPM_TABLE_257 0x3f598
#define ixDPM_TABLE_258 0x3f59c
#define ixDPM_TABLE_259 0x3f5a0
#define ixDPM_TABLE_260 0x3f5a4
#define ixDPM_TABLE_261 0x3f5a8
#define ixDPM_TABLE_262 0x3f5ac
#define ixDPM_TABLE_263 0x3f5b0
#define ixDPM_TABLE_264 0x3f5b4
#define ixDPM_TABLE_265 0x3f5b8
#define ixDPM_TABLE_266 0x3f5bc
#define ixDPM_TABLE_267 0x3f5c0
#define ixDPM_TABLE_268 0x3f5c4
#define ixDPM_TABLE_269 0x3f5c8
#define ixDPM_TABLE_270 0x3f5cc
#define ixDPM_TABLE_271 0x3f5d0
#define ixDPM_TABLE_272 0x3f5d4
#define ixDPM_TABLE_273 0x3f5d8
#define ixDPM_TABLE_274 0x3f5dc
#define ixDPM_TABLE_275 0x3f5e0
#define ixDPM_TABLE_276 0x3f5e4
#define ixDPM_TABLE_277 0x3f5e8
#define ixDPM_TABLE_278 0x3f5ec
#define ixDPM_TABLE_279 0x3f5f0
#define ixDPM_TABLE_280 0x3f5f4
#define ixDPM_TABLE_281 0x3f5f8
#define ixDPM_TABLE_282 0x3f5fc
#define ixDPM_TABLE_283 0x3f600
#define ixDPM_TABLE_284 0x3f604
#define ixDPM_TABLE_285 0x3f608
#define ixDPM_TABLE_286 0x3f60c
#define ixDPM_TABLE_287 0x3f610
#define ixDPM_TABLE_288 0x3f614
#define ixDPM_TABLE_289 0x3f618
#define ixDPM_TABLE_290 0x3f61c
#define ixDPM_TABLE_291 0x3f620
#define ixDPM_TABLE_292 0x3f624
#define ixDPM_TABLE_293 0x3f628
#define ixDPM_TABLE_294 0x3f62c
#define ixDPM_TABLE_295 0x3f630
#define ixDPM_TABLE_296 0x3f634
#define ixDPM_TABLE_297 0x3f638
#define ixDPM_TABLE_298 0x3f63c
#define ixDPM_TABLE_299 0x3f640
#define ixDPM_TABLE_300 0x3f644
#define ixDPM_TABLE_301 0x3f648
#define ixDPM_TABLE_302 0x3f64c
#define ixDPM_TABLE_303 0x3f650
#define ixDPM_TABLE_304 0x3f654
#define ixDPM_TABLE_305 0x3f658
#define ixDPM_TABLE_306 0x3f65c
#define ixDPM_TABLE_307 0x3f660
#define ixDPM_TABLE_308 0x3f664
#define ixDPM_TABLE_309 0x3f668
#define ixDPM_TABLE_310 0x3f66c
#define ixDPM_TABLE_311 0x3f670
#define ixDPM_TABLE_312 0x3f674
#define ixDPM_TABLE_313 0x3f678
#define ixDPM_TABLE_314 0x3f67c
#define ixDPM_TABLE_315 0x3f680
#define ixDPM_TABLE_316 0x3f684
#define ixDPM_TABLE_317 0x3f688
#define ixDPM_TABLE_318 0x3f68c
#define ixDPM_TABLE_319 0x3f690
#define ixDPM_TABLE_320 0x3f694
#define ixDPM_TABLE_321 0x3f698
#define ixDPM_TABLE_322 0x3f69c
#define ixDPM_TABLE_323 0x3f6a0
#define ixDPM_TABLE_324 0x3f6a4
#define ixDPM_TABLE_325 0x3f6a8
#define ixDPM_TABLE_326 0x3f6ac
#define ixDPM_TABLE_327 0x3f6b0
#define ixDPM_TABLE_328 0x3f6b4
#define ixDPM_TABLE_329 0x3f6b8
#define ixDPM_TABLE_330 0x3f6bc
#define ixDPM_TABLE_331 0x3f6c0
#define ixDPM_TABLE_332 0x3f6c4
#define ixDPM_TABLE_333 0x3f6c8
#define ixDPM_TABLE_334 0x3f6cc
#define ixDPM_TABLE_335 0x3f6d0
#define ixDPM_TABLE_336 0x3f6d4
#define ixDPM_TABLE_337 0x3f6d8
#define ixDPM_TABLE_338 0x3f6dc
#define ixDPM_TABLE_339 0x3f6e0
#define ixDPM_TABLE_340 0x3f6e4
#define ixDPM_TABLE_341 0x3f6e8
#define ixDPM_TABLE_342 0x3f6ec
#define ixDPM_TABLE_343 0x3f6f0
#define ixDPM_TABLE_344 0x3f6f4
#define ixDPM_TABLE_345 0x3f6f8
#define ixDPM_TABLE_346 0x3f6fc
#define ixDPM_TABLE_347 0x3f700
#define ixDPM_TABLE_348 0x3f704
#define ixDPM_TABLE_349 0x3f708
#define ixDPM_TABLE_350 0x3f70c
#define ixDPM_TABLE_351 0x3f710
#define ixDPM_TABLE_352 0x3f714
#define ixDPM_TABLE_353 0x3f718
#define ixDPM_TABLE_354 0x3f71c
#define ixDPM_TABLE_355 0x3f720
#define ixDPM_TABLE_356 0x3f724
#define ixDPM_TABLE_357 0x3f728
#define ixDPM_TABLE_358 0x3f72c
#define ixDPM_TABLE_359 0x3f730
#define ixDPM_TABLE_360 0x3f734
#define ixDPM_TABLE_361 0x3f738
#define ixDPM_TABLE_362 0x3f73c
#define ixDPM_TABLE_363 0x3f740
#define ixDPM_TABLE_364 0x3f744
#define ixDPM_TABLE_365 0x3f748
#define ixDPM_TABLE_366 0x3f74c
#define ixDPM_TABLE_367 0x3f750
#define ixDPM_TABLE_368 0x3f754
#define ixDPM_TABLE_369 0x3f758
#define ixDPM_TABLE_370 0x3f75c
#define ixDPM_TABLE_371 0x3f760
#define ixDPM_TABLE_372 0x3f764
#define ixDPM_TABLE_373 0x3f768
#define ixDPM_TABLE_374 0x3f76c
#define ixDPM_TABLE_375 0x3f770
#define ixDPM_TABLE_376 0x3f774
#define ixDPM_TABLE_377 0x3f778
#define ixDPM_TABLE_378 0x3f77c
#define ixDPM_TABLE_379 0x3f780
#define ixDPM_TABLE_380 0x3f784
#define ixDPM_TABLE_381 0x3f788
#define ixDPM_TABLE_382 0x3f78c
#define ixDPM_TABLE_383 0x3f790
#define ixDPM_TABLE_384 0x3f794
#define ixDPM_TABLE_385 0x3f798
#define ixDPM_TABLE_386 0x3f79c
#define ixDPM_TABLE_387 0x3f7a0
#define ixDPM_TABLE_388 0x3f7a4
#define ixDPM_TABLE_389 0x3f7a8
#define ixDPM_TABLE_390 0x3f7ac
#define ixDPM_TABLE_391 0x3f7b0
#define ixDPM_TABLE_392 0x3f7b4
#define ixDPM_TABLE_393 0x3f7b8
#define ixDPM_TABLE_394 0x3f7bc
#define ixDPM_TABLE_395 0x3f7c0
#define ixDPM_TABLE_396 0x3f7c4
#define ixDPM_TABLE_397 0x3f7c8
#define ixDPM_TABLE_398 0x3f7cc
#define ixDPM_TABLE_399 0x3f7d0
#define ixDPM_TABLE_400 0x3f7d4
#define ixDPM_TABLE_401 0x3f7d8
#define ixDPM_TABLE_402 0x3f7dc
#define ixDPM_TABLE_403 0x3f7e0
#define ixDPM_TABLE_404 0x3f7e4
#define ixDPM_TABLE_405 0x3f7e8
#define ixDPM_TABLE_406 0x3f7ec
#define ixDPM_TABLE_407 0x3f7f0
#define ixDPM_TABLE_408 0x3f7f4
#define ixDPM_TABLE_409 0x3f7f8
#define ixDPM_TABLE_410 0x3f7fc
#define ixDPM_TABLE_411 0x3f800
#define ixDPM_TABLE_412 0x3f804
#define ixDPM_TABLE_413 0x3f808
#define ixDPM_TABLE_414 0x3f80c
#define ixDPM_TABLE_415 0x3f810
#define ixDPM_TABLE_416 0x3f814
#define ixDPM_TABLE_417 0x3f818
#define ixDPM_TABLE_418 0x3f81c
#define ixDPM_TABLE_419 0x3f820
#define ixDPM_TABLE_420 0x3f824
#define ixDPM_TABLE_421 0x3f828
#define ixDPM_TABLE_422 0x3f82c
#define ixDPM_TABLE_423 0x3f830
#define ixDPM_TABLE_424 0x3f834
#define ixDPM_TABLE_425 0x3f838
#define ixDPM_TABLE_426 0x3f83c
#define ixDPM_TABLE_427 0x3f840
#define ixDPM_TABLE_428 0x3f844
#define ixDPM_TABLE_429 0x3f848
#define ixDPM_TABLE_430 0x3f84c
#define ixDPM_TABLE_431 0x3f850
#define ixDPM_TABLE_432 0x3f854
#define ixDPM_TABLE_433 0x3f858
#define ixDPM_TABLE_434 0x3f85c
#define ixDPM_TABLE_435 0x3f860
#define ixDPM_TABLE_436 0x3f864
#define ixDPM_TABLE_437 0x3f868
#define ixDPM_TABLE_438 0x3f86c
#define ixDPM_TABLE_439 0x3f870
#define ixDPM_TABLE_440 0x3f874
#define ixSOFT_REGISTERS_TABLE_1 0x3f89c
#define ixSOFT_REGISTERS_TABLE_2 0x3f8a0
#define ixSOFT_REGISTERS_TABLE_3 0x3f8a4
#define ixSOFT_REGISTERS_TABLE_4 0x3f8a8
#define ixSOFT_REGISTERS_TABLE_5 0x3f8ac
#define ixSOFT_REGISTERS_TABLE_6 0x3f8b0
#define ixSOFT_REGISTERS_TABLE_7 0x3f8b4
#define ixSOFT_REGISTERS_TABLE_8 0x3f8b8
#define ixSOFT_REGISTERS_TABLE_9 0x3f8bc
#define ixSOFT_REGISTERS_TABLE_10 0x3f8c0
#define ixSOFT_REGISTERS_TABLE_11 0x3f8c4
#define ixSOFT_REGISTERS_TABLE_12 0x3f8c8
#define ixSOFT_REGISTERS_TABLE_13 0x3f8cc
#define ixSOFT_REGISTERS_TABLE_14 0x3f8d0
#define ixSOFT_REGISTERS_TABLE_15 0x3f8d4
#define ixSOFT_REGISTERS_TABLE_16 0x3f8d8
#define ixSOFT_REGISTERS_TABLE_17 0x3f8dc
#define ixSOFT_REGISTERS_TABLE_18 0x3f8e0
#define ixSOFT_REGISTERS_TABLE_19 0x3f8e4
#define ixSOFT_REGISTERS_TABLE_20 0x3f8e8
#define ixSOFT_REGISTERS_TABLE_21 0x3f8ec
#define ixSOFT_REGISTERS_TABLE_22 0x3f8f0
#define ixSOFT_REGISTERS_TABLE_23 0x3f8f4
#define ixSOFT_REGISTERS_TABLE_24 0x3f8f8
#define ixSOFT_REGISTERS_TABLE_25 0x3f8fc
#define ixSOFT_REGISTERS_TABLE_26 0x3f900
#define ixSOFT_REGISTERS_TABLE_27 0x3f904
#define ixSOFT_REGISTERS_TABLE_28 0x3f888
#define ixSOFT_REGISTERS_TABLE_29 0x3f90c
#define ixSOFT_REGISTERS_TABLE_30 0x3f910
#define ixPM_FUSES_1 0x3f914
#define ixPM_FUSES_2 0x3f918
#define ixPM_FUSES_3 0x3f91c
#define ixPM_FUSES_4 0x3f920
#define ixPM_FUSES_5 0x3f924
#define ixPM_FUSES_6 0x3f928
#define ixPM_FUSES_7 0x3f92c
#define ixPM_FUSES_8 0x3f930
#define ixPM_FUSES_9 0x3f934
#define ixPM_FUSES_10 0x3f938
#define ixPM_FUSES_11 0x3f93c
#define ixPM_FUSES_12 0x3f940
#define ixPM_FUSES_13 0x3f944
#define ixPM_FUSES_14 0x3f948
#define ixPM_FUSES_15 0x3f94c
#define ixSMU_PM_STATUS_0 0x3fe00
#define ixSMU_PM_STATUS_1 0x3fe04
#define ixSMU_PM_STATUS_2 0x3fe08
#define ixSMU_PM_STATUS_3 0x3fe0c
#define ixSMU_PM_STATUS_4 0x3fe10
#define ixSMU_PM_STATUS_5 0x3fe14
#define ixSMU_PM_STATUS_6 0x3fe18
#define ixSMU_PM_STATUS_7 0x3fe1c
#define ixSMU_PM_STATUS_8 0x3fe20
#define ixSMU_PM_STATUS_9 0x3fe24
#define ixSMU_PM_STATUS_10 0x3fe28
#define ixSMU_PM_STATUS_11 0x3fe2c
#define ixSMU_PM_STATUS_12 0x3fe30
#define ixSMU_PM_STATUS_13 0x3fe34
#define ixSMU_PM_STATUS_14 0x3fe38
#define ixSMU_PM_STATUS_15 0x3fe3c
#define ixSMU_PM_STATUS_16 0x3fe40
#define ixSMU_PM_STATUS_17 0x3fe44
#define ixSMU_PM_STATUS_18 0x3fe48
#define ixSMU_PM_STATUS_19 0x3fe4c
#define ixSMU_PM_STATUS_20 0x3fe50
#define ixSMU_PM_STATUS_21 0x3fe54
#define ixSMU_PM_STATUS_22 0x3fe58
#define ixSMU_PM_STATUS_23 0x3fe5c
#define ixSMU_PM_STATUS_24 0x3fe60
#define ixSMU_PM_STATUS_25 0x3fe64
#define ixSMU_PM_STATUS_26 0x3fe68
#define ixSMU_PM_STATUS_27 0x3fe6c
#define ixSMU_PM_STATUS_28 0x3fe70
#define ixSMU_PM_STATUS_29 0x3fe74
#define ixSMU_PM_STATUS_30 0x3fe78
#define ixSMU_PM_STATUS_31 0x3fe7c
#define ixSMU_PM_STATUS_32 0x3fe80
#define ixSMU_PM_STATUS_33 0x3fe84
#define ixSMU_PM_STATUS_34 0x3fe88
#define ixSMU_PM_STATUS_35 0x3fe8c
#define ixSMU_PM_STATUS_36 0x3fe90
#define ixSMU_PM_STATUS_37 0x3fe94
#define ixSMU_PM_STATUS_38 0x3fe98
#define ixSMU_PM_STATUS_39 0x3fe9c
#define ixSMU_PM_STATUS_40 0x3fea0
#define ixSMU_PM_STATUS_41 0x3fea4
#define ixSMU_PM_STATUS_42 0x3fea8
#define ixSMU_PM_STATUS_43 0x3feac
#define ixSMU_PM_STATUS_44 0x3feb0
#define ixSMU_PM_STATUS_45 0x3feb4
#define ixSMU_PM_STATUS_46 0x3feb8
#define ixSMU_PM_STATUS_47 0x3febc
#define ixSMU_PM_STATUS_48 0x3fec0
#define ixSMU_PM_STATUS_49 0x3fec4
#define ixSMU_PM_STATUS_50 0x3fec8
#define ixSMU_PM_STATUS_51 0x3fecc
#define ixSMU_PM_STATUS_52 0x3fed0
#define ixSMU_PM_STATUS_53 0x3fed4
#define ixSMU_PM_STATUS_54 0x3fed8
#define ixSMU_PM_STATUS_55 0x3fedc
#define ixSMU_PM_STATUS_56 0x3fee0
#define ixSMU_PM_STATUS_57 0x3fee4
#define ixSMU_PM_STATUS_58 0x3fee8
#define ixSMU_PM_STATUS_59 0x3feec
#define ixSMU_PM_STATUS_60 0x3fef0
#define ixSMU_PM_STATUS_61 0x3fef4
#define ixSMU_PM_STATUS_62 0x3fef8
#define ixSMU_PM_STATUS_63 0x3fefc
#define ixSMU_PM_STATUS_64 0x3ff00
#define ixSMU_PM_STATUS_65 0x3ff04
#define ixSMU_PM_STATUS_66 0x3ff08
#define ixSMU_PM_STATUS_67 0x3ff0c
#define ixSMU_PM_STATUS_68 0x3ff10
#define ixSMU_PM_STATUS_69 0x3ff14
#define ixSMU_PM_STATUS_70 0x3ff18
#define ixSMU_PM_STATUS_71 0x3ff1c
#define ixSMU_PM_STATUS_72 0x3ff20
#define ixSMU_PM_STATUS_73 0x3ff24
#define ixSMU_PM_STATUS_74 0x3ff28
#define ixSMU_PM_STATUS_75 0x3ff2c
#define ixSMU_PM_STATUS_76 0x3ff30
#define ixSMU_PM_STATUS_77 0x3ff34
#define ixSMU_PM_STATUS_78 0x3ff38
#define ixSMU_PM_STATUS_79 0x3ff3c
#define ixSMU_PM_STATUS_80 0x3ff40
#define ixSMU_PM_STATUS_81 0x3ff44
#define ixSMU_PM_STATUS_82 0x3ff48
#define ixSMU_PM_STATUS_83 0x3ff4c
#define ixSMU_PM_STATUS_84 0x3ff50
#define ixSMU_PM_STATUS_85 0x3ff54
#define ixSMU_PM_STATUS_86 0x3ff58
#define ixSMU_PM_STATUS_87 0x3ff5c
#define ixSMU_PM_STATUS_88 0x3ff60
#define ixSMU_PM_STATUS_89 0x3ff64
#define ixSMU_PM_STATUS_90 0x3ff68
#define ixSMU_PM_STATUS_91 0x3ff6c
#define ixSMU_PM_STATUS_92 0x3ff70
#define ixSMU_PM_STATUS_93 0x3ff74
#define ixSMU_PM_STATUS_94 0x3ff78
#define ixSMU_PM_STATUS_95 0x3ff7c
#define ixSMU_PM_STATUS_96 0x3ff80
#define ixSMU_PM_STATUS_97 0x3ff84
#define ixSMU_PM_STATUS_98 0x3ff88
#define ixSMU_PM_STATUS_99 0x3ff8c
#define ixSMU_PM_STATUS_100 0x3ff90
#define ixSMU_PM_STATUS_101 0x3ff94
#define ixSMU_PM_STATUS_102 0x3ff98
#define ixSMU_PM_STATUS_103 0x3ff9c
#define ixSMU_PM_STATUS_104 0x3ffa0
#define ixSMU_PM_STATUS_105 0x3ffa4
#define ixSMU_PM_STATUS_106 0x3ffa8
#define ixSMU_PM_STATUS_107 0x3ffac
#define ixSMU_PM_STATUS_108 0x3ffb0
#define ixSMU_PM_STATUS_109 0x3ffb4
#define ixSMU_PM_STATUS_110 0x3ffb8
#define ixSMU_PM_STATUS_111 0x3ffbc
#define ixSMU_PM_STATUS_112 0x3ffc0
#define ixSMU_PM_STATUS_113 0x3ffc4
#define ixSMU_PM_STATUS_114 0x3ffc8
#define ixSMU_PM_STATUS_115 0x3ffcc
#define ixSMU_PM_STATUS_116 0x3ffd0
#define ixSMU_PM_STATUS_117 0x3ffd4
#define ixSMU_PM_STATUS_118 0x3ffd8
#define ixSMU_PM_STATUS_119 0x3ffdc
#define ixSMU_PM_STATUS_120 0x3ffe0
#define ixSMU_PM_STATUS_121 0x3ffe4
#define ixSMU_PM_STATUS_122 0x3ffe8
#define ixSMU_PM_STATUS_123 0x3ffec
#define ixSMU_PM_STATUS_124 0x3fff0
#define ixSMU_PM_STATUS_125 0x3fff4
#define ixSMU_PM_STATUS_126 0x3fff8
#define ixSMU_PM_STATUS_127 0x3fffc
#define ixCG_THERMAL_INT_ENA 0xc2100024
#define ixCG_THERMAL_INT_CTRL 0xc2100028
#define ixCG_THERMAL_INT_STATUS 0xc210002c
#define ixCG_THERMAL_CTRL 0xc0300004
#define ixCG_THERMAL_STATUS 0xc0300008
#define ixCG_THERMAL_INT 0xc030000c
#define ixCG_MULT_THERMAL_CTRL 0xc0300010
#define ixCG_MULT_THERMAL_STATUS 0xc0300014
#define ixTHM_TMON2_CTRL 0xc0300034
#define ixTHM_TMON2_CTRL2 0xc0300038
#define ixTHM_TMON2_CSR_WR 0xc0300054
#define ixTHM_TMON2_CSR_RD 0xc0300058
#define ixCG_FDO_CTRL0 0xc0300064
#define ixCG_FDO_CTRL1 0xc0300068
#define ixCG_FDO_CTRL2 0xc030006c
#define ixCG_TACH_CTRL 0xc0300070
#define ixCG_TACH_STATUS 0xc0300074
#define ixCC_THM_STRAPS0 0xc0300080
#define ixTHM_TMON0_RDIL0_DATA 0xc0300100
#define ixTHM_TMON0_RDIL1_DATA 0xc0300104
#define ixTHM_TMON0_RDIL2_DATA 0xc0300108
#define ixTHM_TMON0_RDIL3_DATA 0xc030010c
#define ixTHM_TMON0_RDIL4_DATA 0xc0300110
#define ixTHM_TMON0_RDIL5_DATA 0xc0300114
#define ixTHM_TMON0_RDIL6_DATA 0xc0300118
#define ixTHM_TMON0_RDIL7_DATA 0xc030011c
#define ixTHM_TMON0_RDIL8_DATA 0xc0300120
#define ixTHM_TMON0_RDIL9_DATA 0xc0300124
#define ixTHM_TMON0_RDIL10_DATA 0xc0300128
#define ixTHM_TMON0_RDIL11_DATA 0xc030012c
#define ixTHM_TMON0_RDIL12_DATA 0xc0300130
#define ixTHM_TMON0_RDIL13_DATA 0xc0300134
#define ixTHM_TMON0_RDIL14_DATA 0xc0300138
#define ixTHM_TMON0_RDIL15_DATA 0xc030013c
#define ixTHM_TMON0_RDIR0_DATA 0xc0300140
#define ixTHM_TMON0_RDIR1_DATA 0xc0300144
#define ixTHM_TMON0_RDIR2_DATA 0xc0300148
#define ixTHM_TMON0_RDIR3_DATA 0xc030014c
#define ixTHM_TMON0_RDIR4_DATA 0xc0300150
#define ixTHM_TMON0_RDIR5_DATA 0xc0300154
#define ixTHM_TMON0_RDIR6_DATA 0xc0300158
#define ixTHM_TMON0_RDIR7_DATA 0xc030015c
#define ixTHM_TMON0_RDIR8_DATA 0xc0300160
#define ixTHM_TMON0_RDIR9_DATA 0xc0300164
#define ixTHM_TMON0_RDIR10_DATA 0xc0300168
#define ixTHM_TMON0_RDIR11_DATA 0xc030016c
#define ixTHM_TMON0_RDIR12_DATA 0xc0300170
#define ixTHM_TMON0_RDIR13_DATA 0xc0300174
#define ixTHM_TMON0_RDIR14_DATA 0xc0300178
#define ixTHM_TMON0_RDIR15_DATA 0xc030017c
#define ixTHM_TMON1_RDIL0_DATA 0xc0300180
#define ixTHM_TMON1_RDIL1_DATA 0xc0300184
#define ixTHM_TMON1_RDIL2_DATA 0xc0300188
#define ixTHM_TMON1_RDIL3_DATA 0xc030018c
#define ixTHM_TMON1_RDIL4_DATA 0xc0300190
#define ixTHM_TMON1_RDIL5_DATA 0xc0300194
#define ixTHM_TMON1_RDIL6_DATA 0xc0300198
#define ixTHM_TMON1_RDIL7_DATA 0xc030019c
#define ixTHM_TMON1_RDIL8_DATA 0xc03001a0
#define ixTHM_TMON1_RDIL9_DATA 0xc03001a4
#define ixTHM_TMON1_RDIL10_DATA 0xc03001a8
#define ixTHM_TMON1_RDIL11_DATA 0xc03001ac
#define ixTHM_TMON1_RDIL12_DATA 0xc03001b0
#define ixTHM_TMON1_RDIL13_DATA 0xc03001b4
#define ixTHM_TMON1_RDIL14_DATA 0xc03001b8
#define ixTHM_TMON1_RDIL15_DATA 0xc03001bc
#define ixTHM_TMON1_RDIR0_DATA 0xc03001c0
#define ixTHM_TMON1_RDIR1_DATA 0xc03001c4
#define ixTHM_TMON1_RDIR2_DATA 0xc03001c8
#define ixTHM_TMON1_RDIR3_DATA 0xc03001cc
#define ixTHM_TMON1_RDIR4_DATA 0xc03001d0
#define ixTHM_TMON1_RDIR5_DATA 0xc03001d4
#define ixTHM_TMON1_RDIR6_DATA 0xc03001d8
#define ixTHM_TMON1_RDIR7_DATA 0xc03001dc
#define ixTHM_TMON1_RDIR8_DATA 0xc03001e0
#define ixTHM_TMON1_RDIR9_DATA 0xc03001e4
#define ixTHM_TMON1_RDIR10_DATA 0xc03001e8
#define ixTHM_TMON1_RDIR11_DATA 0xc03001ec
#define ixTHM_TMON1_RDIR12_DATA 0xc03001f0
#define ixTHM_TMON1_RDIR13_DATA 0xc03001f4
#define ixTHM_TMON1_RDIR14_DATA 0xc03001f8
#define ixTHM_TMON1_RDIR15_DATA 0xc03001fc
#define ixTHM_TMON2_RDIL0_DATA 0xc0300200
#define ixTHM_TMON2_RDIL1_DATA 0xc0300204
#define ixTHM_TMON2_RDIL2_DATA 0xc0300208
#define ixTHM_TMON2_RDIL3_DATA 0xc030020c
#define ixTHM_TMON2_RDIL4_DATA 0xc0300210
#define ixTHM_TMON2_RDIL5_DATA 0xc0300214
#define ixTHM_TMON2_RDIL6_DATA 0xc0300218
#define ixTHM_TMON2_RDIL7_DATA 0xc030021c
#define ixTHM_TMON2_RDIL8_DATA 0xc0300220
#define ixTHM_TMON2_RDIL9_DATA 0xc0300224
#define ixTHM_TMON2_RDIL10_DATA 0xc0300228
#define ixTHM_TMON2_RDIL11_DATA 0xc030022c
#define ixTHM_TMON2_RDIL12_DATA 0xc0300230
#define ixTHM_TMON2_RDIL13_DATA 0xc0300234
#define ixTHM_TMON2_RDIL14_DATA 0xc0300238
#define ixTHM_TMON2_RDIL15_DATA 0xc030023c
#define ixTHM_TMON2_RDIR0_DATA 0xc0300240
#define ixTHM_TMON2_RDIR1_DATA 0xc0300244
#define ixTHM_TMON2_RDIR2_DATA 0xc0300248
#define ixTHM_TMON2_RDIR3_DATA 0xc030024c
#define ixTHM_TMON2_RDIR4_DATA 0xc0300250
#define ixTHM_TMON2_RDIR5_DATA 0xc0300254
#define ixTHM_TMON2_RDIR6_DATA 0xc0300258
#define ixTHM_TMON2_RDIR7_DATA 0xc030025c
#define ixTHM_TMON2_RDIR8_DATA 0xc0300260
#define ixTHM_TMON2_RDIR9_DATA 0xc0300264
#define ixTHM_TMON2_RDIR10_DATA 0xc0300268
#define ixTHM_TMON2_RDIR11_DATA 0xc030026c
#define ixTHM_TMON2_RDIR12_DATA 0xc0300270
#define ixTHM_TMON2_RDIR13_DATA 0xc0300274
#define ixTHM_TMON2_RDIR14_DATA 0xc0300278
#define ixTHM_TMON2_RDIR15_DATA 0xc030027c
#define ixTHM_TMON0_INT_DATA 0xc0300300
#define ixTHM_TMON1_INT_DATA 0xc0300304
#define ixTHM_TMON2_INT_DATA 0xc0300308
#define ixTHM_TMON0_DEBUG 0xc0300310
#define ixTHM_TMON1_DEBUG 0xc0300314
#define ixTHM_TMON2_DEBUG 0xc0300318
#define ixTHM_TMON0_STATUS 0xc0300320
#define ixTHM_TMON1_STATUS 0xc0300324
#define ixTHM_TMON2_STATUS 0xc0300328
#define ixGENERAL_PWRMGT 0xc0200000
#define ixCNB_PWRMGT_CNTL 0xc0200004
#define ixSCLK_PWRMGT_CNTL 0xc0200008
#define ixTARGET_AND_CURRENT_PROFILE_INDEX 0xc0200014
#define ixPWR_PCC_CONTROL 0xc0200018
#define ixPWR_PCC_GPIO_SELECT 0xc020001c
#define ixCG_FREQ_TRAN_VOTING_0 0xc02001a8
#define ixCG_FREQ_TRAN_VOTING_1 0xc02001ac
#define ixCG_FREQ_TRAN_VOTING_2 0xc02001b0
#define ixCG_FREQ_TRAN_VOTING_3 0xc02001b4
#define ixCG_FREQ_TRAN_VOTING_4 0xc02001b8
#define ixCG_FREQ_TRAN_VOTING_5 0xc02001bc
#define ixCG_FREQ_TRAN_VOTING_6 0xc02001c0
#define ixCG_FREQ_TRAN_VOTING_7 0xc02001c4
#define ixPLL_TEST_CNTL 0xc020003c
#define ixCG_STATIC_SCREEN_PARAMETER 0xc0200044
#define ixCG_DISPLAY_GAP_CNTL 0xc0200060
#define ixCG_DISPLAY_GAP_CNTL2 0xc0200230
#define ixCG_ACPI_CNTL 0xc0200064
#define ixSCLK_DEEP_SLEEP_CNTL 0xc0200080
#define ixSCLK_DEEP_SLEEP_CNTL2 0xc0200084
#define ixSCLK_DEEP_SLEEP_CNTL3 0xc020009c
#define ixSCLK_DEEP_SLEEP_MISC_CNTL 0xc0200088
#define ixLCLK_DEEP_SLEEP_CNTL 0xc020008c
#define ixLCLK_DEEP_SLEEP_CNTL2 0xc0200310
#define ixTARGET_AND_CURRENT_PROFILE_INDEX_1 0xc02000f0
#define ixCG_ULV_PARAMETER 0xc020015c
#define ixSCLK_MIN_DIV 0xc02003ac
#define ixPWR_AVFS_SEL 0xc0200384
#define ixPWR_AVFS_CNTL 0xc0200388
#define ixPWR_AVFS0_CNTL_STATUS 0xc0200400
#define ixPWR_AVFS1_CNTL_STATUS 0xc0200404
#define ixPWR_AVFS2_CNTL_STATUS 0xc0200408
#define ixPWR_AVFS3_CNTL_STATUS 0xc020040c
#define ixPWR_AVFS4_CNTL_STATUS 0xc0200410
#define ixPWR_AVFS5_CNTL_STATUS 0xc0200414
#define ixPWR_AVFS6_CNTL_STATUS 0xc0200418
#define ixPWR_AVFS7_CNTL_STATUS 0xc020041c
#define ixPWR_AVFS8_CNTL_STATUS 0xc0200420
#define ixPWR_AVFS9_CNTL_STATUS 0xc0200424
#define ixPWR_AVFS10_CNTL_STATUS 0xc0200428
#define ixPWR_AVFS11_CNTL_STATUS 0xc020042c
#define ixPWR_AVFS12_CNTL_STATUS 0xc0200430
#define ixPWR_AVFS13_CNTL_STATUS 0xc0200434
#define ixPWR_AVFS14_CNTL_STATUS 0xc0200438
#define ixPWR_AVFS15_CNTL_STATUS 0xc020043c
#define ixPWR_AVFS16_CNTL_STATUS 0xc0200440
#define ixPWR_AVFS17_CNTL_STATUS 0xc0200444
#define ixPWR_AVFS18_CNTL_STATUS 0xc0200448
#define ixPWR_AVFS19_CNTL_STATUS 0xc020044c
#define ixPWR_AVFS20_CNTL_STATUS 0xc0200450
#define ixPWR_AVFS21_CNTL_STATUS 0xc0200454
#define ixPWR_AVFS22_CNTL_STATUS 0xc0200458
#define ixPWR_AVFS23_CNTL_STATUS 0xc020045c
#define ixPWR_AVFS24_CNTL_STATUS 0xc0200460
#define ixPWR_AVFS25_CNTL_STATUS 0xc0200464
#define ixPWR_AVFS26_CNTL_STATUS 0xc0200468
#define ixPWR_AVFS27_CNTL_STATUS 0xc020046c
#define ixPWR_CKS_ENABLE 0xc020034c
#define ixPWR_CKS_CNTL 0xc0200350
#define ixPWR_DISP_TIMER_CONTROL 0xc02003c0
#define ixPWR_DISP_TIMER_DEBUG 0xc02003c4
#define ixPWR_DISP_TIMER2_CONTROL 0xc02003c8
#define ixPWR_DISP_TIMER2_DEBUG 0xc02003cc
#define ixPWR_DISP_TIMER_CONTROL2 0xc0200378
#define ixVDDGFX_IDLE_PARAMETER 0xc020036c
#define ixVDDGFX_IDLE_CONTROL 0xc0200370
#define ixVDDGFX_IDLE_EXIT 0xc0200374
#define ixLCAC_MC0_CNTL 0xc0400130
#define ixLCAC_MC0_OVR_SEL 0xc0400134
#define ixLCAC_MC0_OVR_VAL 0xc0400138
#define ixLCAC_MC1_CNTL 0xc040013c
#define ixLCAC_MC1_OVR_SEL 0xc0400140
#define ixLCAC_MC1_OVR_VAL 0xc0400144
#define ixLCAC_MC2_CNTL 0xc0400148
#define ixLCAC_MC2_OVR_SEL 0xc040014c
#define ixLCAC_MC2_OVR_VAL 0xc0400150
#define ixLCAC_MC3_CNTL 0xc0400154
#define ixLCAC_MC3_OVR_SEL 0xc0400158
#define ixLCAC_MC3_OVR_VAL 0xc040015c
#define ixLCAC_MC4_CNTL 0xc0400d60
#define ixLCAC_MC4_OVR_SEL 0xc0400d64
#define ixLCAC_MC4_OVR_VAL 0xc0400d68
#define ixLCAC_MC5_CNTL 0xc0400d6c
#define ixLCAC_MC5_OVR_SEL 0xc0400d70
#define ixLCAC_MC5_OVR_VAL 0xc0400d74
#define ixLCAC_MC6_CNTL 0xc0400d78
#define ixLCAC_MC6_OVR_SEL 0xc0400d7c
#define ixLCAC_MC6_OVR_VAL 0xc0400d80
#define ixLCAC_MC7_CNTL 0xc0400d84
#define ixLCAC_MC7_OVR_SEL 0xc0400d88
#define ixLCAC_MC7_OVR_VAL 0xc0400d8c
#define ixLCAC_CPL_CNTL 0xc0400160
#define ixLCAC_CPL_OVR_SEL 0xc0400164
#define ixLCAC_CPL_OVR_VAL 0xc0400168
#define mmROM_SMC_IND_INDEX 0x80
#define mmROM0_ROM_SMC_IND_INDEX 0x80
#define mmROM1_ROM_SMC_IND_INDEX 0x82
#define mmROM2_ROM_SMC_IND_INDEX 0x84
#define mmROM3_ROM_SMC_IND_INDEX 0x86
#define mmROM_SMC_IND_DATA 0x81
#define mmROM0_ROM_SMC_IND_DATA 0x81
#define mmROM1_ROM_SMC_IND_DATA 0x83
#define mmROM2_ROM_SMC_IND_DATA 0x85
#define mmROM3_ROM_SMC_IND_DATA 0x87
#define ixROM_CNTL 0xc0600000
#define ixPAGE_MIRROR_CNTL 0xc0600004
#define ixROM_STATUS 0xc0600008
#define ixCGTT_ROM_CLK_CTRL0 0xc060000c
#define ixROM_INDEX 0xc0600010
#define ixROM_DATA 0xc0600014
#define ixROM_START 0xc0600018
#define ixROM_SW_CNTL 0xc060001c
#define ixROM_SW_STATUS 0xc0600020
#define ixROM_SW_COMMAND 0xc0600024
#define ixROM_SW_DATA_1 0xc0600028
#define ixROM_SW_DATA_2 0xc060002c
#define ixROM_SW_DATA_3 0xc0600030
#define ixROM_SW_DATA_4 0xc0600034
#define ixROM_SW_DATA_5 0xc0600038
#define ixROM_SW_DATA_6 0xc060003c
#define ixROM_SW_DATA_7 0xc0600040
#define ixROM_SW_DATA_8 0xc0600044
#define ixROM_SW_DATA_9 0xc0600048
#define ixROM_SW_DATA_10 0xc060004c
#define ixROM_SW_DATA_11 0xc0600050
#define ixROM_SW_DATA_12 0xc0600054
#define ixROM_SW_DATA_13 0xc0600058
#define ixROM_SW_DATA_14 0xc060005c
#define ixROM_SW_DATA_15 0xc0600060
#define ixROM_SW_DATA_16 0xc0600064
#define ixROM_SW_DATA_17 0xc0600068
#define ixROM_SW_DATA_18 0xc060006c
#define ixROM_SW_DATA_19 0xc0600070
#define ixROM_SW_DATA_20 0xc0600074
#define ixROM_SW_DATA_21 0xc0600078
#define ixROM_SW_DATA_22 0xc060007c
#define ixROM_SW_DATA_23 0xc0600080
#define ixROM_SW_DATA_24 0xc0600084
#define ixROM_SW_DATA_25 0xc0600088
#define ixROM_SW_DATA_26 0xc060008c
#define ixROM_SW_DATA_27 0xc0600090
#define ixROM_SW_DATA_28 0xc0600094
#define ixROM_SW_DATA_29 0xc0600098
#define ixROM_SW_DATA_30 0xc060009c
#define ixROM_SW_DATA_31 0xc06000a0
#define ixROM_SW_DATA_32 0xc06000a4
#define ixROM_SW_DATA_33 0xc06000a8
#define ixROM_SW_DATA_34 0xc06000ac
#define ixROM_SW_DATA_35 0xc06000b0
#define ixROM_SW_DATA_36 0xc06000b4
#define ixROM_SW_DATA_37 0xc06000b8
#define ixROM_SW_DATA_38 0xc06000bc
#define ixROM_SW_DATA_39 0xc06000c0
#define ixROM_SW_DATA_40 0xc06000c4
#define ixROM_SW_DATA_41 0xc06000c8
#define ixROM_SW_DATA_42 0xc06000cc
#define ixROM_SW_DATA_43 0xc06000d0
#define ixROM_SW_DATA_44 0xc06000d4
#define ixROM_SW_DATA_45 0xc06000d8
#define ixROM_SW_DATA_46 0xc06000dc
#define ixROM_SW_DATA_47 0xc06000e0
#define ixROM_SW_DATA_48 0xc06000e4
#define ixROM_SW_DATA_49 0xc06000e8
#define ixROM_SW_DATA_50 0xc06000ec
#define ixROM_SW_DATA_51 0xc06000f0
#define ixROM_SW_DATA_52 0xc06000f4
#define ixROM_SW_DATA_53 0xc06000f8
#define ixROM_SW_DATA_54 0xc06000fc
#define ixROM_SW_DATA_55 0xc0600100
#define ixROM_SW_DATA_56 0xc0600104
#define ixROM_SW_DATA_57 0xc0600108
#define ixROM_SW_DATA_58 0xc060010c
#define ixROM_SW_DATA_59 0xc0600110
#define ixROM_SW_DATA_60 0xc0600114
#define ixROM_SW_DATA_61 0xc0600118
#define ixROM_SW_DATA_62 0xc060011c
#define ixROM_SW_DATA_63 0xc0600120
#define ixROM_SW_DATA_64 0xc0600124
#define mmGC_CAC_CGTT_CLK_CTRL 0x3292
#define mmSE_CAC_CGTT_CLK_CTRL 0x3293
#define mmGC_CAC_LKG_AGGR_LOWER 0x3296
#define mmGC_CAC_LKG_AGGR_UPPER 0x3297
#define ixGC_CAC_WEIGHT_CU_0 0x32
#define ixGC_CAC_WEIGHT_CU_1 0x33
#define ixGC_CAC_WEIGHT_CU_2 0x34
#define ixGC_CAC_WEIGHT_CU_3 0x35
#define ixGC_CAC_WEIGHT_CU_4 0x36
#define ixGC_CAC_WEIGHT_CU_5 0x37
#define ixGC_CAC_WEIGHT_CU_6 0x38
#define ixGC_CAC_WEIGHT_CU_7 0x39
#define ixGC_CAC_ACC_CU0 0xba
#define ixGC_CAC_ACC_CU1 0xbb
#define ixGC_CAC_ACC_CU2 0xbc
#define ixGC_CAC_ACC_CU3 0xbd
#define ixGC_CAC_ACC_CU4 0xbe
#define ixGC_CAC_ACC_CU5 0xbf
#define ixGC_CAC_ACC_CU6 0xc0
#define ixGC_CAC_ACC_CU7 0xc1
#define ixGC_CAC_ACC_CU8 0xc2
#define ixGC_CAC_ACC_CU9 0xc3
#define ixGC_CAC_ACC_CU10 0xc4
#define ixGC_CAC_ACC_CU11 0xc5
#define ixGC_CAC_ACC_CU12 0xc6
#define ixGC_CAC_ACC_CU13 0xc7
#define ixGC_CAC_ACC_CU14 0xc8
#define ixGC_CAC_ACC_CU15 0xc9
#define ixGC_CAC_OVRD_CU 0xe7
#endif /* SMU_7_1_3_D_H */
drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_enum.h 0 → 100644
浏览文件 @ d1c4dcfb
/*
* SMU_7_1_3 Register documentation
*
* Copyright (C) 2014 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef SMU_7_1_3_ENUM_H
#define SMU_7_1_3_ENUM_H
#define CG_SRBM_START_ADDR 0x600
#define CG_SRBM_END_ADDR 0x8ff
#define RCU_CCF_DWORDS0 0xa0
#define RCU_CCF_BITS0 0x1400
#define RCU_SAM_BYTES 0x2c
#define RCU_SAM_RTL_BYTES 0x2c
#define RCU_SMU_BYTES 0x14
#define RCU_SMU_RTL_BYTES 0x14
#define SFP_CHAIN_ADDR 0x1
#define SFP_SADR 0x0
#define SFP_EADR 0x37f
#define SAMU_KEY_CHAIN_ADR 0x0
#define SAMU_KEY_SADR 0x280
#define SAMU_KEY_EADR 0x2ab
#define SMU_KEY_CHAIN_ADR 0x0
#define SMU_KEY_SADR 0x2ac
#define SMU_KEY_EADR 0x2bf
#define SMC_MSG_TEST 0x1
#define SMC_MSG_PHY_LN_OFF 0x2
#define SMC_MSG_PHY_LN_ON 0x3
#define SMC_MSG_DDI_PHY_OFF 0x4
#define SMC_MSG_DDI_PHY_ON 0x5
#define SMC_MSG_CASCADE_PLL_OFF 0x6
#define SMC_MSG_CASCADE_PLL_ON 0x7
#define SMC_MSG_PWR_OFF_x16 0x8
#define SMC_MSG_CONFIG_LCLK_DPM 0x9
#define SMC_MSG_FLUSH_DATA_CACHE 0xa
#define SMC_MSG_FLUSH_INSTRUCTION_CACHE 0xb
#define SMC_MSG_CONFIG_VPC_ACCUMULATOR 0xc
#define SMC_MSG_CONFIG_BAPM 0xd
#define SMC_MSG_CONFIG_TDC_LIMIT 0xe
#define SMC_MSG_CONFIG_LPMx 0xf
#define SMC_MSG_CONFIG_HTC_LIMIT 0x10
#define SMC_MSG_CONFIG_THERMAL_CNTL 0x11
#define SMC_MSG_CONFIG_VOLTAGE_CNTL 0x12
#define SMC_MSG_CONFIG_TDP_CNTL 0x13
#define SMC_MSG_EN_PM_CNTL 0x14
#define SMC_MSG_DIS_PM_CNTL 0x15
#define SMC_MSG_CONFIG_NBDPM 0x16
#define SMC_MSG_CONFIG_LOADLINE 0x17
#define SMC_MSG_ADJUST_LOADLINE 0x18
#define SMC_MSG_RESET 0x20
#define SMC_MSG_VOLTAGE 0x25
#define SMC_VERSION_MAJOR 0x7
#define SMC_VERSION_MINOR 0x0
#define SMC_HEADER_SIZE 0x40
#define ROM_SIGNATURE 0xaa55
typedef enum SurfaceEndian {
ENDIAN_NONE = 0x0,
ENDIAN_8IN16 = 0x1,
ENDIAN_8IN32 = 0x2,
ENDIAN_8IN64 = 0x3,
} SurfaceEndian;
typedef enum ArrayMode {
ARRAY_LINEAR_GENERAL = 0x0,
ARRAY_LINEAR_ALIGNED = 0x1,
ARRAY_1D_TILED_THIN1 = 0x2,
ARRAY_1D_TILED_THICK = 0x3,
ARRAY_2D_TILED_THIN1 = 0x4,
ARRAY_PRT_TILED_THIN1 = 0x5,
ARRAY_PRT_2D_TILED_THIN1 = 0x6,
ARRAY_2D_TILED_THICK = 0x7,
ARRAY_2D_TILED_XTHICK = 0x8,
ARRAY_PRT_TILED_THICK = 0x9,
ARRAY_PRT_2D_TILED_THICK = 0xa,
ARRAY_PRT_3D_TILED_THIN1 = 0xb,
ARRAY_3D_TILED_THIN1 = 0xc,
ARRAY_3D_TILED_THICK = 0xd,
ARRAY_3D_TILED_XTHICK = 0xe,
ARRAY_PRT_3D_TILED_THICK = 0xf,
} ArrayMode;
typedef enum PipeTiling {
CONFIG_1_PIPE = 0x0,
CONFIG_2_PIPE = 0x1,
CONFIG_4_PIPE = 0x2,
CONFIG_8_PIPE = 0x3,
} PipeTiling;
typedef enum BankTiling {
CONFIG_4_BANK = 0x0,
CONFIG_8_BANK = 0x1,
} BankTiling;
typedef enum GroupInterleave {
CONFIG_256B_GROUP = 0x0,
CONFIG_512B_GROUP = 0x1,
} GroupInterleave;
typedef enum RowTiling {
CONFIG_1KB_ROW = 0x0,
CONFIG_2KB_ROW = 0x1,
CONFIG_4KB_ROW = 0x2,
CONFIG_8KB_ROW = 0x3,
CONFIG_1KB_ROW_OPT = 0x4,
CONFIG_2KB_ROW_OPT = 0x5,
CONFIG_4KB_ROW_OPT = 0x6,
CONFIG_8KB_ROW_OPT = 0x7,
} RowTiling;
typedef enum BankSwapBytes {
CONFIG_128B_SWAPS = 0x0,
CONFIG_256B_SWAPS = 0x1,
CONFIG_512B_SWAPS = 0x2,
CONFIG_1KB_SWAPS = 0x3,
} BankSwapBytes;
typedef enum SampleSplitBytes {
CONFIG_1KB_SPLIT = 0x0,
CONFIG_2KB_SPLIT = 0x1,
CONFIG_4KB_SPLIT = 0x2,
CONFIG_8KB_SPLIT = 0x3,
} SampleSplitBytes;
typedef enum NumPipes {
ADDR_CONFIG_1_PIPE = 0x0,
ADDR_CONFIG_2_PIPE = 0x1,
ADDR_CONFIG_4_PIPE = 0x2,
ADDR_CONFIG_8_PIPE = 0x3,
} NumPipes;
typedef enum PipeInterleaveSize {
ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0,
ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1,
} PipeInterleaveSize;
typedef enum BankInterleaveSize {
ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0,
ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1,
ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3,
} BankInterleaveSize;
typedef enum NumShaderEngines {
ADDR_CONFIG_1_SHADER_ENGINE = 0x0,
ADDR_CONFIG_2_SHADER_ENGINE = 0x1,
} NumShaderEngines;
typedef enum ShaderEngineTileSize {
ADDR_CONFIG_SE_TILE_16 = 0x0,
ADDR_CONFIG_SE_TILE_32 = 0x1,
} ShaderEngineTileSize;
typedef enum NumGPUs {
ADDR_CONFIG_1_GPU = 0x0,
ADDR_CONFIG_2_GPU = 0x1,
ADDR_CONFIG_4_GPU = 0x2,
} NumGPUs;
typedef enum MultiGPUTileSize {
ADDR_CONFIG_GPU_TILE_16 = 0x0,
ADDR_CONFIG_GPU_TILE_32 = 0x1,
ADDR_CONFIG_GPU_TILE_64 = 0x2,
ADDR_CONFIG_GPU_TILE_128 = 0x3,
} MultiGPUTileSize;
typedef enum RowSize {
ADDR_CONFIG_1KB_ROW = 0x0,
ADDR_CONFIG_2KB_ROW = 0x1,
ADDR_CONFIG_4KB_ROW = 0x2,
} RowSize;
typedef enum NumLowerPipes {
ADDR_CONFIG_1_LOWER_PIPES = 0x0,
ADDR_CONFIG_2_LOWER_PIPES = 0x1,
} NumLowerPipes;
typedef enum DebugBlockId {
DBG_CLIENT_BLKID_RESERVED = 0x0,
DBG_CLIENT_BLKID_dbg = 0x1,
DBG_CLIENT_BLKID_scf2 = 0x2,
DBG_CLIENT_BLKID_mcd5_0 = 0x3,
DBG_CLIENT_BLKID_mcd5_1 = 0x4,
DBG_CLIENT_BLKID_mcd6_0 = 0x5,
DBG_CLIENT_BLKID_mcd6_1 = 0x6,
DBG_CLIENT_BLKID_mcd7_0 = 0x7,
DBG_CLIENT_BLKID_mcd7_1 = 0x8,
DBG_CLIENT_BLKID_vmc = 0x9,
DBG_CLIENT_BLKID_sx30 = 0xa,
DBG_CLIENT_BLKID_mcd2_0 = 0xb,
DBG_CLIENT_BLKID_mcd2_1 = 0xc,
DBG_CLIENT_BLKID_bci1 = 0xd,
DBG_CLIENT_BLKID_xdma_dbg_client_wrapper = 0xe,
DBG_CLIENT_BLKID_mcc0 = 0xf,
DBG_CLIENT_BLKID_uvdf_0 = 0x10,
DBG_CLIENT_BLKID_uvdf_1 = 0x11,
DBG_CLIENT_BLKID_uvdf_2 = 0x12,
DBG_CLIENT_BLKID_bci0 = 0x13,
DBG_CLIENT_BLKID_vcec0_0 = 0x14,
DBG_CLIENT_BLKID_cb100 = 0x15,
DBG_CLIENT_BLKID_cb001 = 0x16,
DBG_CLIENT_BLKID_cb002 = 0x17,
DBG_CLIENT_BLKID_cb003 = 0x18,
DBG_CLIENT_BLKID_mcd4_0 = 0x19,
DBG_CLIENT_BLKID_mcd4_1 = 0x1a,
DBG_CLIENT_BLKID_tmonw00 = 0x1b,
DBG_CLIENT_BLKID_cb101 = 0x1c,
DBG_CLIENT_BLKID_cb102 = 0x1d,
DBG_CLIENT_BLKID_cb103 = 0x1e,
DBG_CLIENT_BLKID_sx10 = 0x1f,
DBG_CLIENT_BLKID_cb301 = 0x20,
DBG_CLIENT_BLKID_cb302 = 0x21,
DBG_CLIENT_BLKID_cb303 = 0x22,
DBG_CLIENT_BLKID_tmonw01 = 0x23,
DBG_CLIENT_BLKID_tmonw02 = 0x24,
DBG_CLIENT_BLKID_vcea0_0 = 0x25,
DBG_CLIENT_BLKID_vcea0_1 = 0x26,
DBG_CLIENT_BLKID_vcea0_2 = 0x27,
DBG_CLIENT_BLKID_vcea0_3 = 0x28,
DBG_CLIENT_BLKID_scf1 = 0x29,
DBG_CLIENT_BLKID_sx20 = 0x2a,
DBG_CLIENT_BLKID_spim1 = 0x2b,
DBG_CLIENT_BLKID_scb1 = 0x2c,
DBG_CLIENT_BLKID_pa10 = 0x2d,
DBG_CLIENT_BLKID_pa00 = 0x2e,
DBG_CLIENT_BLKID_gmcon = 0x2f,
DBG_CLIENT_BLKID_mcb = 0x30,
DBG_CLIENT_BLKID_vgt0 = 0x31,
DBG_CLIENT_BLKID_pc0 = 0x32,
DBG_CLIENT_BLKID_bci2 = 0x33,
DBG_CLIENT_BLKID_uvdb_0 = 0x34,
DBG_CLIENT_BLKID_spim3 = 0x35,
DBG_CLIENT_BLKID_scb3 = 0x36,
DBG_CLIENT_BLKID_cpc_0 = 0x37,
DBG_CLIENT_BLKID_cpc_1 = 0x38,
DBG_CLIENT_BLKID_uvdm_0 = 0x39,
DBG_CLIENT_BLKID_uvdm_1 = 0x3a,
DBG_CLIENT_BLKID_uvdm_2 = 0x3b,
DBG_CLIENT_BLKID_uvdm_3 = 0x3c,
DBG_CLIENT_BLKID_cb000 = 0x3d,
DBG_CLIENT_BLKID_spim0 = 0x3e,
DBG_CLIENT_BLKID_scb0 = 0x3f,
DBG_CLIENT_BLKID_mcc2 = 0x40,
DBG_CLIENT_BLKID_ds0 = 0x41,
DBG_CLIENT_BLKID_srbm = 0x42,
DBG_CLIENT_BLKID_ih = 0x43,
DBG_CLIENT_BLKID_sem = 0x44,
DBG_CLIENT_BLKID_sdma_0 = 0x45,
DBG_CLIENT_BLKID_sdma_1 = 0x46,
DBG_CLIENT_BLKID_hdp = 0x47,
DBG_CLIENT_BLKID_acp_0 = 0x48,
DBG_CLIENT_BLKID_acp_1 = 0x49,
DBG_CLIENT_BLKID_cb200 = 0x4a,
DBG_CLIENT_BLKID_scf3 = 0x4b,
DBG_CLIENT_BLKID_bci3 = 0x4c,
DBG_CLIENT_BLKID_mcd0_0 = 0x4d,
DBG_CLIENT_BLKID_mcd0_1 = 0x4e,
DBG_CLIENT_BLKID_pa11 = 0x4f,
DBG_CLIENT_BLKID_pa01 = 0x50,
DBG_CLIENT_BLKID_cb201 = 0x51,
DBG_CLIENT_BLKID_cb202 = 0x52,
DBG_CLIENT_BLKID_cb203 = 0x53,
DBG_CLIENT_BLKID_spim2 = 0x54,
DBG_CLIENT_BLKID_scb2 = 0x55,
DBG_CLIENT_BLKID_vgt2 = 0x56,
DBG_CLIENT_BLKID_pc2 = 0x57,
DBG_CLIENT_BLKID_smu_0 = 0x58,
DBG_CLIENT_BLKID_smu_1 = 0x59,
DBG_CLIENT_BLKID_smu_2 = 0x5a,
DBG_CLIENT_BLKID_cb1 = 0x5b,
DBG_CLIENT_BLKID_ia0 = 0x5c,
DBG_CLIENT_BLKID_wd = 0x5d,
DBG_CLIENT_BLKID_ia1 = 0x5e,
DBG_CLIENT_BLKID_scf0 = 0x5f,
DBG_CLIENT_BLKID_vgt1 = 0x60,
DBG_CLIENT_BLKID_pc1 = 0x61,
DBG_CLIENT_BLKID_cb0 = 0x62,
DBG_CLIENT_BLKID_gdc_one_0 = 0x63,
DBG_CLIENT_BLKID_gdc_one_1 = 0x64,
DBG_CLIENT_BLKID_gdc_one_2 = 0x65,
DBG_CLIENT_BLKID_gdc_one_3 = 0x66,
DBG_CLIENT_BLKID_gdc_one_4 = 0x67,
DBG_CLIENT_BLKID_gdc_one_5 = 0x68,
DBG_CLIENT_BLKID_gdc_one_6 = 0x69,
DBG_CLIENT_BLKID_gdc_one_7 = 0x6a,
DBG_CLIENT_BLKID_gdc_one_8 = 0x6b,
DBG_CLIENT_BLKID_gdc_one_9 = 0x6c,
DBG_CLIENT_BLKID_gdc_one_10 = 0x6d,
DBG_CLIENT_BLKID_gdc_one_11 = 0x6e,
DBG_CLIENT_BLKID_gdc_one_12 = 0x6f,
DBG_CLIENT_BLKID_gdc_one_13 = 0x70,
DBG_CLIENT_BLKID_gdc_one_14 = 0x71,
DBG_CLIENT_BLKID_gdc_one_15 = 0x72,
DBG_CLIENT_BLKID_gdc_one_16 = 0x73,
DBG_CLIENT_BLKID_gdc_one_17 = 0x74,
DBG_CLIENT_BLKID_gdc_one_18 = 0x75,
DBG_CLIENT_BLKID_gdc_one_19 = 0x76,
DBG_CLIENT_BLKID_gdc_one_20 = 0x77,
DBG_CLIENT_BLKID_gdc_one_21 = 0x78,
DBG_CLIENT_BLKID_gdc_one_22 = 0x79,
DBG_CLIENT_BLKID_gdc_one_23 = 0x7a,
DBG_CLIENT_BLKID_gdc_one_24 = 0x7b,
DBG_CLIENT_BLKID_gdc_one_25 = 0x7c,
DBG_CLIENT_BLKID_gdc_one_26 = 0x7d,
DBG_CLIENT_BLKID_gdc_one_27 = 0x7e,
DBG_CLIENT_BLKID_gdc_one_28 = 0x7f,
DBG_CLIENT_BLKID_gdc_one_29 = 0x80,
DBG_CLIENT_BLKID_gdc_one_30 = 0x81,
DBG_CLIENT_BLKID_gdc_one_31 = 0x82,
DBG_CLIENT_BLKID_gdc_one_32 = 0x83,
DBG_CLIENT_BLKID_gdc_one_33 = 0x84,
DBG_CLIENT_BLKID_gdc_one_34 = 0x85,
DBG_CLIENT_BLKID_gdc_one_35 = 0x86,
DBG_CLIENT_BLKID_vceb0_0 = 0x87,
DBG_CLIENT_BLKID_vgt3 = 0x88,
DBG_CLIENT_BLKID_pc3 = 0x89,
DBG_CLIENT_BLKID_mcd3_0 = 0x8a,
DBG_CLIENT_BLKID_mcd3_1 = 0x8b,
DBG_CLIENT_BLKID_uvdu_0 = 0x8c,
DBG_CLIENT_BLKID_uvdu_1 = 0x8d,
DBG_CLIENT_BLKID_uvdu_2 = 0x8e,
DBG_CLIENT_BLKID_uvdu_3 = 0x8f,
DBG_CLIENT_BLKID_uvdu_4 = 0x90,
DBG_CLIENT_BLKID_uvdu_5 = 0x91,
DBG_CLIENT_BLKID_uvdu_6 = 0x92,
DBG_CLIENT_BLKID_cb300 = 0x93,
DBG_CLIENT_BLKID_mcd1_0 = 0x94,
DBG_CLIENT_BLKID_mcd1_1 = 0x95,
DBG_CLIENT_BLKID_sx00 = 0x96,
DBG_CLIENT_BLKID_uvdc_0 = 0x97,
DBG_CLIENT_BLKID_uvdc_1 = 0x98,
DBG_CLIENT_BLKID_mcc3 = 0x99,
DBG_CLIENT_BLKID_mcc4 = 0x9a,
DBG_CLIENT_BLKID_mcc5 = 0x9b,
DBG_CLIENT_BLKID_mcc6 = 0x9c,
DBG_CLIENT_BLKID_mcc7 = 0x9d,
DBG_CLIENT_BLKID_cpg_0 = 0x9e,
DBG_CLIENT_BLKID_cpg_1 = 0x9f,
DBG_CLIENT_BLKID_gck = 0xa0,
DBG_CLIENT_BLKID_mcc1 = 0xa1,
DBG_CLIENT_BLKID_cpf_0 = 0xa2,
DBG_CLIENT_BLKID_cpf_1 = 0xa3,
DBG_CLIENT_BLKID_rlc = 0xa4,
DBG_CLIENT_BLKID_grbm = 0xa5,
DBG_CLIENT_BLKID_sammsp = 0xa6,
DBG_CLIENT_BLKID_dci_pg = 0xa7,
DBG_CLIENT_BLKID_dci_0 = 0xa8,
DBG_CLIENT_BLKID_dccg0_0 = 0xa9,
DBG_CLIENT_BLKID_dccg0_1 = 0xaa,
DBG_CLIENT_BLKID_dcfe01_0 = 0xab,
DBG_CLIENT_BLKID_dcfe02_0 = 0xac,
DBG_CLIENT_BLKID_dcfe03_0 = 0xad,
DBG_CLIENT_BLKID_dcfe04_0 = 0xae,
DBG_CLIENT_BLKID_dcfe05_0 = 0xaf,
DBG_CLIENT_BLKID_dcfe06_0 = 0xb0,
DBG_CLIENT_BLKID_mcq0_0 = 0xb1,
DBG_CLIENT_BLKID_mcq0_1 = 0xb2,
DBG_CLIENT_BLKID_mcq1_0 = 0xb3,
DBG_CLIENT_BLKID_mcq1_1 = 0xb4,
DBG_CLIENT_BLKID_mcq2_0 = 0xb5,
DBG_CLIENT_BLKID_mcq2_1 = 0xb6,
DBG_CLIENT_BLKID_mcq3_0 = 0xb7,
DBG_CLIENT_BLKID_mcq3_1 = 0xb8,
DBG_CLIENT_BLKID_mcq4_0 = 0xb9,
DBG_CLIENT_BLKID_mcq4_1 = 0xba,
DBG_CLIENT_BLKID_mcq5_0 = 0xbb,
DBG_CLIENT_BLKID_mcq5_1 = 0xbc,
DBG_CLIENT_BLKID_mcq6_0 = 0xbd,
DBG_CLIENT_BLKID_mcq6_1 = 0xbe,
DBG_CLIENT_BLKID_mcq7_0 = 0xbf,
DBG_CLIENT_BLKID_mcq7_1 = 0xc0,
DBG_CLIENT_BLKID_uvdi_0 = 0xc1,
DBG_CLIENT_BLKID_RESERVED_LAST = 0xc2,
} DebugBlockId;
typedef enum DebugBlockId_OLD {
DBG_BLOCK_ID_RESERVED = 0x0,
DBG_BLOCK_ID_DBG = 0x1,
DBG_BLOCK_ID_VMC = 0x2,
DBG_BLOCK_ID_PDMA = 0x3,
DBG_BLOCK_ID_CG = 0x4,
DBG_BLOCK_ID_SRBM = 0x5,
DBG_BLOCK_ID_GRBM = 0x6,
DBG_BLOCK_ID_RLC = 0x7,
DBG_BLOCK_ID_CSC = 0x8,
DBG_BLOCK_ID_SEM = 0x9,
DBG_BLOCK_ID_IH = 0xa,
DBG_BLOCK_ID_SC = 0xb,
DBG_BLOCK_ID_SQ = 0xc,
DBG_BLOCK_ID_AVP = 0xd,
DBG_BLOCK_ID_GMCON = 0xe,
DBG_BLOCK_ID_SMU = 0xf,
DBG_BLOCK_ID_DMA0 = 0x10,
DBG_BLOCK_ID_DMA1 = 0x11,
DBG_BLOCK_ID_SPIM = 0x12,
DBG_BLOCK_ID_GDS = 0x13,
DBG_BLOCK_ID_SPIS = 0x14,
DBG_BLOCK_ID_UNUSED0 = 0x15,
DBG_BLOCK_ID_PA0 = 0x16,
DBG_BLOCK_ID_PA1 = 0x17,
DBG_BLOCK_ID_CP0 = 0x18,
DBG_BLOCK_ID_CP1 = 0x19,
DBG_BLOCK_ID_CP2 = 0x1a,
DBG_BLOCK_ID_UNUSED1 = 0x1b,
DBG_BLOCK_ID_UVDU = 0x1c,
DBG_BLOCK_ID_UVDM = 0x1d,
DBG_BLOCK_ID_VCE = 0x1e,
DBG_BLOCK_ID_UNUSED2 = 0x1f,
DBG_BLOCK_ID_VGT0 = 0x20,
DBG_BLOCK_ID_VGT1 = 0x21,
DBG_BLOCK_ID_IA = 0x22,
DBG_BLOCK_ID_UNUSED3 = 0x23,
DBG_BLOCK_ID_SCT0 = 0x24,
DBG_BLOCK_ID_SCT1 = 0x25,
DBG_BLOCK_ID_SPM0 = 0x26,
DBG_BLOCK_ID_SPM1 = 0x27,
DBG_BLOCK_ID_TCAA = 0x28,
DBG_BLOCK_ID_TCAB = 0x29,
DBG_BLOCK_ID_TCCA = 0x2a,
DBG_BLOCK_ID_TCCB = 0x2b,
DBG_BLOCK_ID_MCC0 = 0x2c,
DBG_BLOCK_ID_MCC1 = 0x2d,
DBG_BLOCK_ID_MCC2 = 0x2e,
DBG_BLOCK_ID_MCC3 = 0x2f,
DBG_BLOCK_ID_SX0 = 0x30,
DBG_BLOCK_ID_SX1 = 0x31,
DBG_BLOCK_ID_SX2 = 0x32,
DBG_BLOCK_ID_SX3 = 0x33,
DBG_BLOCK_ID_UNUSED4 = 0x34,
DBG_BLOCK_ID_UNUSED5 = 0x35,
DBG_BLOCK_ID_UNUSED6 = 0x36,
DBG_BLOCK_ID_UNUSED7 = 0x37,
DBG_BLOCK_ID_PC0 = 0x38,
DBG_BLOCK_ID_PC1 = 0x39,
DBG_BLOCK_ID_UNUSED8 = 0x3a,
DBG_BLOCK_ID_UNUSED9 = 0x3b,
DBG_BLOCK_ID_UNUSED10 = 0x3c,
DBG_BLOCK_ID_UNUSED11 = 0x3d,
DBG_BLOCK_ID_MCB = 0x3e,
DBG_BLOCK_ID_UNUSED12 = 0x3f,
DBG_BLOCK_ID_SCB0 = 0x40,
DBG_BLOCK_ID_SCB1 = 0x41,
DBG_BLOCK_ID_UNUSED13 = 0x42,
DBG_BLOCK_ID_UNUSED14 = 0x43,
DBG_BLOCK_ID_SCF0 = 0x44,
DBG_BLOCK_ID_SCF1 = 0x45,
DBG_BLOCK_ID_UNUSED15 = 0x46,
DBG_BLOCK_ID_UNUSED16 = 0x47,
DBG_BLOCK_ID_BCI0 = 0x48,
DBG_BLOCK_ID_BCI1 = 0x49,
DBG_BLOCK_ID_BCI2 = 0x4a,
DBG_BLOCK_ID_BCI3 = 0x4b,
DBG_BLOCK_ID_UNUSED17 = 0x4c,
DBG_BLOCK_ID_UNUSED18 = 0x4d,
DBG_BLOCK_ID_UNUSED19 = 0x4e,
DBG_BLOCK_ID_UNUSED20 = 0x4f,
DBG_BLOCK_ID_CB00 = 0x50,
DBG_BLOCK_ID_CB01 = 0x51,
DBG_BLOCK_ID_CB02 = 0x52,
DBG_BLOCK_ID_CB03 = 0x53,
DBG_BLOCK_ID_CB04 = 0x54,
DBG_BLOCK_ID_UNUSED21 = 0x55,
DBG_BLOCK_ID_UNUSED22 = 0x56,
DBG_BLOCK_ID_UNUSED23 = 0x57,
DBG_BLOCK_ID_CB10 = 0x58,
DBG_BLOCK_ID_CB11 = 0x59,
DBG_BLOCK_ID_CB12 = 0x5a,
DBG_BLOCK_ID_CB13 = 0x5b,
DBG_BLOCK_ID_CB14 = 0x5c,
DBG_BLOCK_ID_UNUSED24 = 0x5d,
DBG_BLOCK_ID_UNUSED25 = 0x5e,
DBG_BLOCK_ID_UNUSED26 = 0x5f,
DBG_BLOCK_ID_TCP0 = 0x60,
DBG_BLOCK_ID_TCP1 = 0x61,
DBG_BLOCK_ID_TCP2 = 0x62,
DBG_BLOCK_ID_TCP3 = 0x63,
DBG_BLOCK_ID_TCP4 = 0x64,
DBG_BLOCK_ID_TCP5 = 0x65,
DBG_BLOCK_ID_TCP6 = 0x66,
DBG_BLOCK_ID_TCP7 = 0x67,
DBG_BLOCK_ID_TCP8 = 0x68,
DBG_BLOCK_ID_TCP9 = 0x69,
DBG_BLOCK_ID_TCP10 = 0x6a,
DBG_BLOCK_ID_TCP11 = 0x6b,
DBG_BLOCK_ID_TCP12 = 0x6c,
DBG_BLOCK_ID_TCP13 = 0x6d,
DBG_BLOCK_ID_TCP14 = 0x6e,
DBG_BLOCK_ID_TCP15 = 0x6f,
DBG_BLOCK_ID_TCP16 = 0x70,
DBG_BLOCK_ID_TCP17 = 0x71,
DBG_BLOCK_ID_TCP18 = 0x72,
DBG_BLOCK_ID_TCP19 = 0x73,
DBG_BLOCK_ID_TCP20 = 0x74,
DBG_BLOCK_ID_TCP21 = 0x75,
DBG_BLOCK_ID_TCP22 = 0x76,
DBG_BLOCK_ID_TCP23 = 0x77,
DBG_BLOCK_ID_TCP_RESERVED0 = 0x78,
DBG_BLOCK_ID_TCP_RESERVED1 = 0x79,
DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a,
DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b,
DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c,
DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d,
DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e,
DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f,
DBG_BLOCK_ID_DB00 = 0x80,
DBG_BLOCK_ID_DB01 = 0x81,
DBG_BLOCK_ID_DB02 = 0x82,
DBG_BLOCK_ID_DB03 = 0x83,
DBG_BLOCK_ID_DB04 = 0x84,
DBG_BLOCK_ID_UNUSED27 = 0x85,
DBG_BLOCK_ID_UNUSED28 = 0x86,
DBG_BLOCK_ID_UNUSED29 = 0x87,
DBG_BLOCK_ID_DB10 = 0x88,
DBG_BLOCK_ID_DB11 = 0x89,
DBG_BLOCK_ID_DB12 = 0x8a,
DBG_BLOCK_ID_DB13 = 0x8b,
DBG_BLOCK_ID_DB14 = 0x8c,
DBG_BLOCK_ID_UNUSED30 = 0x8d,
DBG_BLOCK_ID_UNUSED31 = 0x8e,
DBG_BLOCK_ID_UNUSED32 = 0x8f,
DBG_BLOCK_ID_TCC0 = 0x90,
DBG_BLOCK_ID_TCC1 = 0x91,
DBG_BLOCK_ID_TCC2 = 0x92,
DBG_BLOCK_ID_TCC3 = 0x93,
DBG_BLOCK_ID_TCC4 = 0x94,
DBG_BLOCK_ID_TCC5 = 0x95,
DBG_BLOCK_ID_TCC6 = 0x96,
DBG_BLOCK_ID_TCC7 = 0x97,
DBG_BLOCK_ID_SPS00 = 0x98,
DBG_BLOCK_ID_SPS01 = 0x99,
DBG_BLOCK_ID_SPS02 = 0x9a,
DBG_BLOCK_ID_SPS10 = 0x9b,
DBG_BLOCK_ID_SPS11 = 0x9c,
DBG_BLOCK_ID_SPS12 = 0x9d,
DBG_BLOCK_ID_UNUSED33 = 0x9e,
DBG_BLOCK_ID_UNUSED34 = 0x9f,
DBG_BLOCK_ID_TA00 = 0xa0,
DBG_BLOCK_ID_TA01 = 0xa1,
DBG_BLOCK_ID_TA02 = 0xa2,
DBG_BLOCK_ID_TA03 = 0xa3,
DBG_BLOCK_ID_TA04 = 0xa4,
DBG_BLOCK_ID_TA05 = 0xa5,
DBG_BLOCK_ID_TA06 = 0xa6,
DBG_BLOCK_ID_TA07 = 0xa7,
DBG_BLOCK_ID_TA08 = 0xa8,
DBG_BLOCK_ID_TA09 = 0xa9,
DBG_BLOCK_ID_TA0A = 0xaa,
DBG_BLOCK_ID_TA0B = 0xab,
DBG_BLOCK_ID_UNUSED35 = 0xac,
DBG_BLOCK_ID_UNUSED36 = 0xad,
DBG_BLOCK_ID_UNUSED37 = 0xae,
DBG_BLOCK_ID_UNUSED38 = 0xaf,
DBG_BLOCK_ID_TA10 = 0xb0,
DBG_BLOCK_ID_TA11 = 0xb1,
DBG_BLOCK_ID_TA12 = 0xb2,
DBG_BLOCK_ID_TA13 = 0xb3,
DBG_BLOCK_ID_TA14 = 0xb4,
DBG_BLOCK_ID_TA15 = 0xb5,
DBG_BLOCK_ID_TA16 = 0xb6,
DBG_BLOCK_ID_TA17 = 0xb7,
DBG_BLOCK_ID_TA18 = 0xb8,
DBG_BLOCK_ID_TA19 = 0xb9,
DBG_BLOCK_ID_TA1A = 0xba,
DBG_BLOCK_ID_TA1B = 0xbb,
DBG_BLOCK_ID_UNUSED39 = 0xbc,
DBG_BLOCK_ID_UNUSED40 = 0xbd,
DBG_BLOCK_ID_UNUSED41 = 0xbe,
DBG_BLOCK_ID_UNUSED42 = 0xbf,
DBG_BLOCK_ID_TD00 = 0xc0,
DBG_BLOCK_ID_TD01 = 0xc1,
DBG_BLOCK_ID_TD02 = 0xc2,
DBG_BLOCK_ID_TD03 = 0xc3,
DBG_BLOCK_ID_TD04 = 0xc4,
DBG_BLOCK_ID_TD05 = 0xc5,
DBG_BLOCK_ID_TD06 = 0xc6,
DBG_BLOCK_ID_TD07 = 0xc7,
DBG_BLOCK_ID_TD08 = 0xc8,
DBG_BLOCK_ID_TD09 = 0xc9,
DBG_BLOCK_ID_TD0A = 0xca,
DBG_BLOCK_ID_TD0B = 0xcb,
DBG_BLOCK_ID_UNUSED43 = 0xcc,
DBG_BLOCK_ID_UNUSED44 = 0xcd,
DBG_BLOCK_ID_UNUSED45 = 0xce,
DBG_BLOCK_ID_UNUSED46 = 0xcf,
DBG_BLOCK_ID_TD10 = 0xd0,
DBG_BLOCK_ID_TD11 = 0xd1,
DBG_BLOCK_ID_TD12 = 0xd2,
DBG_BLOCK_ID_TD13 = 0xd3,
DBG_BLOCK_ID_TD14 = 0xd4,
DBG_BLOCK_ID_TD15 = 0xd5,
DBG_BLOCK_ID_TD16 = 0xd6,
DBG_BLOCK_ID_TD17 = 0xd7,
DBG_BLOCK_ID_TD18 = 0xd8,
DBG_BLOCK_ID_TD19 = 0xd9,
DBG_BLOCK_ID_TD1A = 0xda,
DBG_BLOCK_ID_TD1B = 0xdb,
DBG_BLOCK_ID_UNUSED47 = 0xdc,
DBG_BLOCK_ID_UNUSED48 = 0xdd,
DBG_BLOCK_ID_UNUSED49 = 0xde,
DBG_BLOCK_ID_UNUSED50 = 0xdf,
DBG_BLOCK_ID_MCD0 = 0xe0,
DBG_BLOCK_ID_MCD1 = 0xe1,
DBG_BLOCK_ID_MCD2 = 0xe2,
DBG_BLOCK_ID_MCD3 = 0xe3,
DBG_BLOCK_ID_MCD4 = 0xe4,
DBG_BLOCK_ID_MCD5 = 0xe5,
DBG_BLOCK_ID_UNUSED51 = 0xe6,
DBG_BLOCK_ID_UNUSED52 = 0xe7,
} DebugBlockId_OLD;
typedef enum DebugBlockId_BY2 {
DBG_BLOCK_ID_RESERVED_BY2 = 0x0,
DBG_BLOCK_ID_VMC_BY2 = 0x1,
DBG_BLOCK_ID_CG_BY2 = 0x2,
DBG_BLOCK_ID_GRBM_BY2 = 0x3,
DBG_BLOCK_ID_CSC_BY2 = 0x4,
DBG_BLOCK_ID_IH_BY2 = 0x5,
DBG_BLOCK_ID_SQ_BY2 = 0x6,
DBG_BLOCK_ID_GMCON_BY2 = 0x7,
DBG_BLOCK_ID_DMA0_BY2 = 0x8,
DBG_BLOCK_ID_SPIM_BY2 = 0x9,
DBG_BLOCK_ID_SPIS_BY2 = 0xa,
DBG_BLOCK_ID_PA0_BY2 = 0xb,
DBG_BLOCK_ID_CP0_BY2 = 0xc,
DBG_BLOCK_ID_CP2_BY2 = 0xd,
DBG_BLOCK_ID_UVDU_BY2 = 0xe,
DBG_BLOCK_ID_VCE_BY2 = 0xf,
DBG_BLOCK_ID_VGT0_BY2 = 0x10,
DBG_BLOCK_ID_IA_BY2 = 0x11,
DBG_BLOCK_ID_SCT0_BY2 = 0x12,
DBG_BLOCK_ID_SPM0_BY2 = 0x13,
DBG_BLOCK_ID_TCAA_BY2 = 0x14,
DBG_BLOCK_ID_TCCA_BY2 = 0x15,
DBG_BLOCK_ID_MCC0_BY2 = 0x16,
DBG_BLOCK_ID_MCC2_BY2 = 0x17,
DBG_BLOCK_ID_SX0_BY2 = 0x18,
DBG_BLOCK_ID_SX2_BY2 = 0x19,
DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a,
DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b,
DBG_BLOCK_ID_PC0_BY2 = 0x1c,
DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d,
DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e,
DBG_BLOCK_ID_MCB_BY2 = 0x1f,
DBG_BLOCK_ID_SCB0_BY2 = 0x20,
DBG_BLOCK_ID_UNUSED13_BY2 = 0x21,
DBG_BLOCK_ID_SCF0_BY2 = 0x22,
DBG_BLOCK_ID_UNUSED15_BY2 = 0x23,
DBG_BLOCK_ID_BCI0_BY2 = 0x24,
DBG_BLOCK_ID_BCI2_BY2 = 0x25,
DBG_BLOCK_ID_UNUSED17_BY2 = 0x26,
DBG_BLOCK_ID_UNUSED19_BY2 = 0x27,
DBG_BLOCK_ID_CB00_BY2 = 0x28,
DBG_BLOCK_ID_CB02_BY2 = 0x29,
DBG_BLOCK_ID_CB04_BY2 = 0x2a,
DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b,
DBG_BLOCK_ID_CB10_BY2 = 0x2c,
DBG_BLOCK_ID_CB12_BY2 = 0x2d,
DBG_BLOCK_ID_CB14_BY2 = 0x2e,
DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f,
DBG_BLOCK_ID_TCP0_BY2 = 0x30,
DBG_BLOCK_ID_TCP2_BY2 = 0x31,
DBG_BLOCK_ID_TCP4_BY2 = 0x32,
DBG_BLOCK_ID_TCP6_BY2 = 0x33,
DBG_BLOCK_ID_TCP8_BY2 = 0x34,
DBG_BLOCK_ID_TCP10_BY2 = 0x35,
DBG_BLOCK_ID_TCP12_BY2 = 0x36,
DBG_BLOCK_ID_TCP14_BY2 = 0x37,
DBG_BLOCK_ID_TCP16_BY2 = 0x38,
DBG_BLOCK_ID_TCP18_BY2 = 0x39,
DBG_BLOCK_ID_TCP20_BY2 = 0x3a,
DBG_BLOCK_ID_TCP22_BY2 = 0x3b,
DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c,
DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d,
DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e,
DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f,
DBG_BLOCK_ID_DB00_BY2 = 0x40,
DBG_BLOCK_ID_DB02_BY2 = 0x41,
DBG_BLOCK_ID_DB04_BY2 = 0x42,
DBG_BLOCK_ID_UNUSED28_BY2 = 0x43,
DBG_BLOCK_ID_DB10_BY2 = 0x44,
DBG_BLOCK_ID_DB12_BY2 = 0x45,
DBG_BLOCK_ID_DB14_BY2 = 0x46,
DBG_BLOCK_ID_UNUSED31_BY2 = 0x47,
DBG_BLOCK_ID_TCC0_BY2 = 0x48,
DBG_BLOCK_ID_TCC2_BY2 = 0x49,
DBG_BLOCK_ID_TCC4_BY2 = 0x4a,
DBG_BLOCK_ID_TCC6_BY2 = 0x4b,
DBG_BLOCK_ID_SPS00_BY2 = 0x4c,
DBG_BLOCK_ID_SPS02_BY2 = 0x4d,
DBG_BLOCK_ID_SPS11_BY2 = 0x4e,
DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f,
DBG_BLOCK_ID_TA00_BY2 = 0x50,
DBG_BLOCK_ID_TA02_BY2 = 0x51,
DBG_BLOCK_ID_TA04_BY2 = 0x52,
DBG_BLOCK_ID_TA06_BY2 = 0x53,
DBG_BLOCK_ID_TA08_BY2 = 0x54,
DBG_BLOCK_ID_TA0A_BY2 = 0x55,
DBG_BLOCK_ID_UNUSED35_BY2 = 0x56,
DBG_BLOCK_ID_UNUSED37_BY2 = 0x57,
DBG_BLOCK_ID_TA10_BY2 = 0x58,
DBG_BLOCK_ID_TA12_BY2 = 0x59,
DBG_BLOCK_ID_TA14_BY2 = 0x5a,
DBG_BLOCK_ID_TA16_BY2 = 0x5b,
DBG_BLOCK_ID_TA18_BY2 = 0x5c,
DBG_BLOCK_ID_TA1A_BY2 = 0x5d,
DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e,
DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f,
DBG_BLOCK_ID_TD00_BY2 = 0x60,
DBG_BLOCK_ID_TD02_BY2 = 0x61,
DBG_BLOCK_ID_TD04_BY2 = 0x62,
DBG_BLOCK_ID_TD06_BY2 = 0x63,
DBG_BLOCK_ID_TD08_BY2 = 0x64,
DBG_BLOCK_ID_TD0A_BY2 = 0x65,
DBG_BLOCK_ID_UNUSED43_BY2 = 0x66,
DBG_BLOCK_ID_UNUSED45_BY2 = 0x67,
DBG_BLOCK_ID_TD10_BY2 = 0x68,
DBG_BLOCK_ID_TD12_BY2 = 0x69,
DBG_BLOCK_ID_TD14_BY2 = 0x6a,
DBG_BLOCK_ID_TD16_BY2 = 0x6b,
DBG_BLOCK_ID_TD18_BY2 = 0x6c,
DBG_BLOCK_ID_TD1A_BY2 = 0x6d,
DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e,
DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f,
DBG_BLOCK_ID_MCD0_BY2 = 0x70,
DBG_BLOCK_ID_MCD2_BY2 = 0x71,
DBG_BLOCK_ID_MCD4_BY2 = 0x72,
DBG_BLOCK_ID_UNUSED51_BY2 = 0x73,
} DebugBlockId_BY2;
typedef enum DebugBlockId_BY4 {
DBG_BLOCK_ID_RESERVED_BY4 = 0x0,
DBG_BLOCK_ID_CG_BY4 = 0x1,
DBG_BLOCK_ID_CSC_BY4 = 0x2,
DBG_BLOCK_ID_SQ_BY4 = 0x3,
DBG_BLOCK_ID_DMA0_BY4 = 0x4,
DBG_BLOCK_ID_SPIS_BY4 = 0x5,
DBG_BLOCK_ID_CP0_BY4 = 0x6,
DBG_BLOCK_ID_UVDU_BY4 = 0x7,
DBG_BLOCK_ID_VGT0_BY4 = 0x8,
DBG_BLOCK_ID_SCT0_BY4 = 0x9,
DBG_BLOCK_ID_TCAA_BY4 = 0xa,
DBG_BLOCK_ID_MCC0_BY4 = 0xb,
DBG_BLOCK_ID_SX0_BY4 = 0xc,
DBG_BLOCK_ID_UNUSED4_BY4 = 0xd,
DBG_BLOCK_ID_PC0_BY4 = 0xe,
DBG_BLOCK_ID_UNUSED10_BY4 = 0xf,
DBG_BLOCK_ID_SCB0_BY4 = 0x10,
DBG_BLOCK_ID_SCF0_BY4 = 0x11,
DBG_BLOCK_ID_BCI0_BY4 = 0x12,
DBG_BLOCK_ID_UNUSED17_BY4 = 0x13,
DBG_BLOCK_ID_CB00_BY4 = 0x14,
DBG_BLOCK_ID_CB04_BY4 = 0x15,
DBG_BLOCK_ID_CB10_BY4 = 0x16,
DBG_BLOCK_ID_CB14_BY4 = 0x17,
DBG_BLOCK_ID_TCP0_BY4 = 0x18,
DBG_BLOCK_ID_TCP4_BY4 = 0x19,
DBG_BLOCK_ID_TCP8_BY4 = 0x1a,
DBG_BLOCK_ID_TCP12_BY4 = 0x1b,
DBG_BLOCK_ID_TCP16_BY4 = 0x1c,
DBG_BLOCK_ID_TCP20_BY4 = 0x1d,
DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e,
DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f,
DBG_BLOCK_ID_DB_BY4 = 0x20,
DBG_BLOCK_ID_DB04_BY4 = 0x21,
DBG_BLOCK_ID_DB10_BY4 = 0x22,
DBG_BLOCK_ID_DB14_BY4 = 0x23,
DBG_BLOCK_ID_TCC0_BY4 = 0x24,
DBG_BLOCK_ID_TCC4_BY4 = 0x25,
DBG_BLOCK_ID_SPS00_BY4 = 0x26,
DBG_BLOCK_ID_SPS11_BY4 = 0x27,
DBG_BLOCK_ID_TA00_BY4 = 0x28,
DBG_BLOCK_ID_TA04_BY4 = 0x29,
DBG_BLOCK_ID_TA08_BY4 = 0x2a,
DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b,
DBG_BLOCK_ID_TA10_BY4 = 0x2c,
DBG_BLOCK_ID_TA14_BY4 = 0x2d,
DBG_BLOCK_ID_TA18_BY4 = 0x2e,
DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f,
DBG_BLOCK_ID_TD00_BY4 = 0x30,
DBG_BLOCK_ID_TD04_BY4 = 0x31,
DBG_BLOCK_ID_TD08_BY4 = 0x32,
DBG_BLOCK_ID_UNUSED43_BY4 = 0x33,
DBG_BLOCK_ID_TD10_BY4 = 0x34,
DBG_BLOCK_ID_TD14_BY4 = 0x35,
DBG_BLOCK_ID_TD18_BY4 = 0x36,
DBG_BLOCK_ID_UNUSED47_BY4 = 0x37,
DBG_BLOCK_ID_MCD0_BY4 = 0x38,
DBG_BLOCK_ID_MCD4_BY4 = 0x39,
} DebugBlockId_BY4;
typedef enum DebugBlockId_BY8 {
DBG_BLOCK_ID_RESERVED_BY8 = 0x0,
DBG_BLOCK_ID_CSC_BY8 = 0x1,
DBG_BLOCK_ID_DMA0_BY8 = 0x2,
DBG_BLOCK_ID_CP0_BY8 = 0x3,
DBG_BLOCK_ID_VGT0_BY8 = 0x4,
DBG_BLOCK_ID_TCAA_BY8 = 0x5,
DBG_BLOCK_ID_SX0_BY8 = 0x6,
DBG_BLOCK_ID_PC0_BY8 = 0x7,
DBG_BLOCK_ID_SCB0_BY8 = 0x8,
DBG_BLOCK_ID_BCI0_BY8 = 0x9,
DBG_BLOCK_ID_CB00_BY8 = 0xa,
DBG_BLOCK_ID_CB10_BY8 = 0xb,
DBG_BLOCK_ID_TCP0_BY8 = 0xc,
DBG_BLOCK_ID_TCP8_BY8 = 0xd,
DBG_BLOCK_ID_TCP16_BY8 = 0xe,
DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf,
DBG_BLOCK_ID_DB00_BY8 = 0x10,
DBG_BLOCK_ID_DB10_BY8 = 0x11,
DBG_BLOCK_ID_TCC0_BY8 = 0x12,
DBG_BLOCK_ID_SPS00_BY8 = 0x13,
DBG_BLOCK_ID_TA00_BY8 = 0x14,
DBG_BLOCK_ID_TA08_BY8 = 0x15,
DBG_BLOCK_ID_TA10_BY8 = 0x16,
DBG_BLOCK_ID_TA18_BY8 = 0x17,
DBG_BLOCK_ID_TD00_BY8 = 0x18,
DBG_BLOCK_ID_TD08_BY8 = 0x19,
DBG_BLOCK_ID_TD10_BY8 = 0x1a,
DBG_BLOCK_ID_TD18_BY8 = 0x1b,
DBG_BLOCK_ID_MCD0_BY8 = 0x1c,
} DebugBlockId_BY8;
typedef enum DebugBlockId_BY16 {
DBG_BLOCK_ID_RESERVED_BY16 = 0x0,
DBG_BLOCK_ID_DMA0_BY16 = 0x1,
DBG_BLOCK_ID_VGT0_BY16 = 0x2,
DBG_BLOCK_ID_SX0_BY16 = 0x3,
DBG_BLOCK_ID_SCB0_BY16 = 0x4,
DBG_BLOCK_ID_CB00_BY16 = 0x5,
DBG_BLOCK_ID_TCP0_BY16 = 0x6,
DBG_BLOCK_ID_TCP16_BY16 = 0x7,
DBG_BLOCK_ID_DB00_BY16 = 0x8,
DBG_BLOCK_ID_TCC0_BY16 = 0x9,
DBG_BLOCK_ID_TA00_BY16 = 0xa,
DBG_BLOCK_ID_TA10_BY16 = 0xb,
DBG_BLOCK_ID_TD00_BY16 = 0xc,
DBG_BLOCK_ID_TD10_BY16 = 0xd,
DBG_BLOCK_ID_MCD0_BY16 = 0xe,
} DebugBlockId_BY16;
typedef enum ColorTransform {
DCC_CT_AUTO = 0x0,
DCC_CT_NONE = 0x1,
ABGR_TO_A_BG_G_RB = 0x2,
BGRA_TO_BG_G_RB_A = 0x3,
} ColorTransform;
typedef enum CompareRef {
REF_NEVER = 0x0,
REF_LESS = 0x1,
REF_EQUAL = 0x2,
REF_LEQUAL = 0x3,
REF_GREATER = 0x4,
REF_NOTEQUAL = 0x5,
REF_GEQUAL = 0x6,
REF_ALWAYS = 0x7,
} CompareRef;
typedef enum ReadSize {
READ_256_BITS = 0x0,
READ_512_BITS = 0x1,
} ReadSize;
typedef enum DepthFormat {
DEPTH_INVALID = 0x0,
DEPTH_16 = 0x1,
DEPTH_X8_24 = 0x2,
DEPTH_8_24 = 0x3,
DEPTH_X8_24_FLOAT = 0x4,
DEPTH_8_24_FLOAT = 0x5,
DEPTH_32_FLOAT = 0x6,
DEPTH_X24_8_32_FLOAT = 0x7,
} DepthFormat;
typedef enum ZFormat {
Z_INVALID = 0x0,
Z_16 = 0x1,
Z_24 = 0x2,
Z_32_FLOAT = 0x3,
} ZFormat;
typedef enum StencilFormat {
STENCIL_INVALID = 0x0,
STENCIL_8 = 0x1,
} StencilFormat;
typedef enum CmaskMode {
CMASK_CLEAR_NONE = 0x0,
CMASK_CLEAR_ONE = 0x1,
CMASK_CLEAR_ALL = 0x2,
CMASK_ANY_EXPANDED = 0x3,
CMASK_ALPHA0_FRAG1 = 0x4,
CMASK_ALPHA0_FRAG2 = 0x5,
CMASK_ALPHA0_FRAG4 = 0x6,
CMASK_ALPHA0_FRAGS = 0x7,
CMASK_ALPHA1_FRAG1 = 0x8,
CMASK_ALPHA1_FRAG2 = 0x9,
CMASK_ALPHA1_FRAG4 = 0xa,
CMASK_ALPHA1_FRAGS = 0xb,
CMASK_ALPHAX_FRAG1 = 0xc,
CMASK_ALPHAX_FRAG2 = 0xd,
CMASK_ALPHAX_FRAG4 = 0xe,
CMASK_ALPHAX_FRAGS = 0xf,
} CmaskMode;
typedef enum QuadExportFormat {
EXPORT_UNUSED = 0x0,
EXPORT_32_R = 0x1,
EXPORT_32_GR = 0x2,
EXPORT_32_AR = 0x3,
EXPORT_FP16_ABGR = 0x4,
EXPORT_UNSIGNED16_ABGR = 0x5,
EXPORT_SIGNED16_ABGR = 0x6,
EXPORT_32_ABGR = 0x7,
} QuadExportFormat;
typedef enum QuadExportFormatOld {
EXPORT_4P_32BPC_ABGR = 0x0,
EXPORT_4P_16BPC_ABGR = 0x1,
EXPORT_4P_32BPC_GR = 0x2,
EXPORT_4P_32BPC_AR = 0x3,
EXPORT_2P_32BPC_ABGR = 0x4,
EXPORT_8P_32BPC_R = 0x5,
} QuadExportFormatOld;
typedef enum ColorFormat {
COLOR_INVALID = 0x0,
COLOR_8 = 0x1,
COLOR_16 = 0x2,
COLOR_8_8 = 0x3,
COLOR_32 = 0x4,
COLOR_16_16 = 0x5,
COLOR_10_11_11 = 0x6,
COLOR_11_11_10 = 0x7,
COLOR_10_10_10_2 = 0x8,
COLOR_2_10_10_10 = 0x9,
COLOR_8_8_8_8 = 0xa,
COLOR_32_32 = 0xb,
COLOR_16_16_16_16 = 0xc,
COLOR_RESERVED_13 = 0xd,
COLOR_32_32_32_32 = 0xe,
COLOR_RESERVED_15 = 0xf,
COLOR_5_6_5 = 0x10,
COLOR_1_5_5_5 = 0x11,
COLOR_5_5_5_1 = 0x12,
COLOR_4_4_4_4 = 0x13,
COLOR_8_24 = 0x14,
COLOR_24_8 = 0x15,
COLOR_X24_8_32_FLOAT = 0x16,
COLOR_RESERVED_23 = 0x17,
} ColorFormat;
typedef enum SurfaceFormat {
FMT_INVALID = 0x0,
FMT_8 = 0x1,
FMT_16 = 0x2,
FMT_8_8 = 0x3,
FMT_32 = 0x4,
FMT_16_16 = 0x5,
FMT_10_11_11 = 0x6,
FMT_11_11_10 = 0x7,
FMT_10_10_10_2 = 0x8,
FMT_2_10_10_10 = 0x9,
FMT_8_8_8_8 = 0xa,
FMT_32_32 = 0xb,
FMT_16_16_16_16 = 0xc,
FMT_32_32_32 = 0xd,
FMT_32_32_32_32 = 0xe,
FMT_RESERVED_4 = 0xf,
FMT_5_6_5 = 0x10,
FMT_1_5_5_5 = 0x11,
FMT_5_5_5_1 = 0x12,
FMT_4_4_4_4 = 0x13,
FMT_8_24 = 0x14,
FMT_24_8 = 0x15,
FMT_X24_8_32_FLOAT = 0x16,
FMT_RESERVED_33 = 0x17,
FMT_11_11_10_FLOAT = 0x18,
FMT_16_FLOAT = 0x19,
FMT_32_FLOAT = 0x1a,
FMT_16_16_FLOAT = 0x1b,
FMT_8_24_FLOAT = 0x1c,
FMT_24_8_FLOAT = 0x1d,
FMT_32_32_FLOAT = 0x1e,
FMT_10_11_11_FLOAT = 0x1f,
FMT_16_16_16_16_FLOAT = 0x20,
FMT_3_3_2 = 0x21,
FMT_6_5_5 = 0x22,
FMT_32_32_32_32_FLOAT = 0x23,
FMT_RESERVED_36 = 0x24,
FMT_1 = 0x25,
FMT_1_REVERSED = 0x26,
FMT_GB_GR = 0x27,
FMT_BG_RG = 0x28,
FMT_32_AS_8 = 0x29,
FMT_32_AS_8_8 = 0x2a,
FMT_5_9_9_9_SHAREDEXP = 0x2b,
FMT_8_8_8 = 0x2c,
FMT_16_16_16 = 0x2d,
FMT_16_16_16_FLOAT = 0x2e,
FMT_4_4 = 0x2f,
FMT_32_32_32_FLOAT = 0x30,
FMT_BC1 = 0x31,
FMT_BC2 = 0x32,
FMT_BC3 = 0x33,
FMT_BC4 = 0x34,
FMT_BC5 = 0x35,
FMT_BC6 = 0x36,
FMT_BC7 = 0x37,
FMT_32_AS_32_32_32_32 = 0x38,
FMT_APC3 = 0x39,
FMT_APC4 = 0x3a,
FMT_APC5 = 0x3b,
FMT_APC6 = 0x3c,
FMT_APC7 = 0x3d,
FMT_CTX1 = 0x3e,
FMT_RESERVED_63 = 0x3f,
} SurfaceFormat;
typedef enum BUF_DATA_FORMAT {
BUF_DATA_FORMAT_INVALID = 0x0,
BUF_DATA_FORMAT_8 = 0x1,
BUF_DATA_FORMAT_16 = 0x2,
BUF_DATA_FORMAT_8_8 = 0x3,
BUF_DATA_FORMAT_32 = 0x4,
BUF_DATA_FORMAT_16_16 = 0x5,
BUF_DATA_FORMAT_10_11_11 = 0x6,
BUF_DATA_FORMAT_11_11_10 = 0x7,
BUF_DATA_FORMAT_10_10_10_2 = 0x8,
BUF_DATA_FORMAT_2_10_10_10 = 0x9,
BUF_DATA_FORMAT_8_8_8_8 = 0xa,
BUF_DATA_FORMAT_32_32 = 0xb,
BUF_DATA_FORMAT_16_16_16_16 = 0xc,
BUF_DATA_FORMAT_32_32_32 = 0xd,
BUF_DATA_FORMAT_32_32_32_32 = 0xe,
BUF_DATA_FORMAT_RESERVED_15 = 0xf,
} BUF_DATA_FORMAT;
typedef enum IMG_DATA_FORMAT {
IMG_DATA_FORMAT_INVALID = 0x0,
IMG_DATA_FORMAT_8 = 0x1,
IMG_DATA_FORMAT_16 = 0x2,
IMG_DATA_FORMAT_8_8 = 0x3,
IMG_DATA_FORMAT_32 = 0x4,
IMG_DATA_FORMAT_16_16 = 0x5,
IMG_DATA_FORMAT_10_11_11 = 0x6,
IMG_DATA_FORMAT_11_11_10 = 0x7,
IMG_DATA_FORMAT_10_10_10_2 = 0x8,
IMG_DATA_FORMAT_2_10_10_10 = 0x9,
IMG_DATA_FORMAT_8_8_8_8 = 0xa,
IMG_DATA_FORMAT_32_32 = 0xb,
IMG_DATA_FORMAT_16_16_16_16 = 0xc,
IMG_DATA_FORMAT_32_32_32 = 0xd,
IMG_DATA_FORMAT_32_32_32_32 = 0xe,
IMG_DATA_FORMAT_RESERVED_15 = 0xf,
IMG_DATA_FORMAT_5_6_5 = 0x10,
IMG_DATA_FORMAT_1_5_5_5 = 0x11,
IMG_DATA_FORMAT_5_5_5_1 = 0x12,
IMG_DATA_FORMAT_4_4_4_4 = 0x13,
IMG_DATA_FORMAT_8_24 = 0x14,
IMG_DATA_FORMAT_24_8 = 0x15,
IMG_DATA_FORMAT_X24_8_32 = 0x16,
IMG_DATA_FORMAT_RESERVED_23 = 0x17,
IMG_DATA_FORMAT_RESERVED_24 = 0x18,
IMG_DATA_FORMAT_RESERVED_25 = 0x19,
IMG_DATA_FORMAT_RESERVED_26 = 0x1a,
IMG_DATA_FORMAT_RESERVED_27 = 0x1b,
IMG_DATA_FORMAT_RESERVED_28 = 0x1c,
IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
IMG_DATA_FORMAT_RESERVED_30 = 0x1e,
IMG_DATA_FORMAT_RESERVED_31 = 0x1f,
IMG_DATA_FORMAT_GB_GR = 0x20,
IMG_DATA_FORMAT_BG_RG = 0x21,
IMG_DATA_FORMAT_5_9_9_9 = 0x22,
IMG_DATA_FORMAT_BC1 = 0x23,
IMG_DATA_FORMAT_BC2 = 0x24,
IMG_DATA_FORMAT_BC3 = 0x25,
IMG_DATA_FORMAT_BC4 = 0x26,
IMG_DATA_FORMAT_BC5 = 0x27,
IMG_DATA_FORMAT_BC6 = 0x28,
IMG_DATA_FORMAT_BC7 = 0x29,
IMG_DATA_FORMAT_RESERVED_42 = 0x2a,
IMG_DATA_FORMAT_RESERVED_43 = 0x2b,
IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c,
IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d,
IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e,
IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f,
IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30,
IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31,
IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32,
IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33,
IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34,
IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35,
IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36,
IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37,
IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38,
IMG_DATA_FORMAT_4_4 = 0x39,
IMG_DATA_FORMAT_6_5_5 = 0x3a,
IMG_DATA_FORMAT_1 = 0x3b,
IMG_DATA_FORMAT_1_REVERSED = 0x3c,
IMG_DATA_FORMAT_32_AS_8 = 0x3d,
IMG_DATA_FORMAT_32_AS_8_8 = 0x3e,
IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f,
} IMG_DATA_FORMAT;
typedef enum BUF_NUM_FORMAT {
BUF_NUM_FORMAT_UNORM = 0x0,
BUF_NUM_FORMAT_SNORM = 0x1,
BUF_NUM_FORMAT_USCALED = 0x2,
BUF_NUM_FORMAT_SSCALED = 0x3,
BUF_NUM_FORMAT_UINT = 0x4,
BUF_NUM_FORMAT_SINT = 0x5,
BUF_NUM_FORMAT_RESERVED_6 = 0x6,
BUF_NUM_FORMAT_FLOAT = 0x7,
} BUF_NUM_FORMAT;
typedef enum IMG_NUM_FORMAT {
IMG_NUM_FORMAT_UNORM = 0x0,
IMG_NUM_FORMAT_SNORM = 0x1,
IMG_NUM_FORMAT_USCALED = 0x2,
IMG_NUM_FORMAT_SSCALED = 0x3,
IMG_NUM_FORMAT_UINT = 0x4,
IMG_NUM_FORMAT_SINT = 0x5,
IMG_NUM_FORMAT_RESERVED_6 = 0x6,
IMG_NUM_FORMAT_FLOAT = 0x7,
IMG_NUM_FORMAT_RESERVED_8 = 0x8,
IMG_NUM_FORMAT_SRGB = 0x9,
IMG_NUM_FORMAT_RESERVED_10 = 0xa,
IMG_NUM_FORMAT_RESERVED_11 = 0xb,
IMG_NUM_FORMAT_RESERVED_12 = 0xc,
IMG_NUM_FORMAT_RESERVED_13 = 0xd,
IMG_NUM_FORMAT_RESERVED_14 = 0xe,
IMG_NUM_FORMAT_RESERVED_15 = 0xf,
} IMG_NUM_FORMAT;
typedef enum TileType {
ARRAY_COLOR_TILE = 0x0,
ARRAY_DEPTH_TILE = 0x1,
} TileType;
typedef enum NonDispTilingOrder {
ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
} NonDispTilingOrder;
typedef enum MicroTileMode {
ADDR_SURF_DISPLAY_MICRO_TILING = 0x0,
ADDR_SURF_THIN_MICRO_TILING = 0x1,
ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
ADDR_SURF_ROTATED_MICRO_TILING = 0x3,
ADDR_SURF_THICK_MICRO_TILING = 0x4,
} MicroTileMode;
typedef enum TileSplit {
ADDR_SURF_TILE_SPLIT_64B = 0x0,
ADDR_SURF_TILE_SPLIT_128B = 0x1,
ADDR_SURF_TILE_SPLIT_256B = 0x2,
ADDR_SURF_TILE_SPLIT_512B = 0x3,
ADDR_SURF_TILE_SPLIT_1KB = 0x4,
ADDR_SURF_TILE_SPLIT_2KB = 0x5,
ADDR_SURF_TILE_SPLIT_4KB = 0x6,
} TileSplit;
typedef enum SampleSplit {
ADDR_SURF_SAMPLE_SPLIT_1 = 0x0,
ADDR_SURF_SAMPLE_SPLIT_2 = 0x1,
ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
ADDR_SURF_SAMPLE_SPLIT_8 = 0x3,
} SampleSplit;
typedef enum PipeConfig {
ADDR_SURF_P2 = 0x0,
ADDR_SURF_P2_RESERVED0 = 0x1,
ADDR_SURF_P2_RESERVED1 = 0x2,
ADDR_SURF_P2_RESERVED2 = 0x3,
ADDR_SURF_P4_8x16 = 0x4,
ADDR_SURF_P4_16x16 = 0x5,
ADDR_SURF_P4_16x32 = 0x6,
ADDR_SURF_P4_32x32 = 0x7,
ADDR_SURF_P8_16x16_8x16 = 0x8,
ADDR_SURF_P8_16x32_8x16 = 0x9,
ADDR_SURF_P8_32x32_8x16 = 0xa,
ADDR_SURF_P8_16x32_16x16 = 0xb,
ADDR_SURF_P8_32x32_16x16 = 0xc,
ADDR_SURF_P8_32x32_16x32 = 0xd,
ADDR_SURF_P8_32x64_32x32 = 0xe,
ADDR_SURF_P8_RESERVED0 = 0xf,
ADDR_SURF_P16_32x32_8x16 = 0x10,
ADDR_SURF_P16_32x32_16x16 = 0x11,
} PipeConfig;
typedef enum NumBanks {
ADDR_SURF_2_BANK = 0x0,
ADDR_SURF_4_BANK = 0x1,
ADDR_SURF_8_BANK = 0x2,
ADDR_SURF_16_BANK = 0x3,
} NumBanks;
typedef enum BankWidth {
ADDR_SURF_BANK_WIDTH_1 = 0x0,
ADDR_SURF_BANK_WIDTH_2 = 0x1,
ADDR_SURF_BANK_WIDTH_4 = 0x2,
ADDR_SURF_BANK_WIDTH_8 = 0x3,
} BankWidth;
typedef enum BankHeight {
ADDR_SURF_BANK_HEIGHT_1 = 0x0,
ADDR_SURF_BANK_HEIGHT_2 = 0x1,
ADDR_SURF_BANK_HEIGHT_4 = 0x2,
ADDR_SURF_BANK_HEIGHT_8 = 0x3,
} BankHeight;
typedef enum BankWidthHeight {
ADDR_SURF_BANK_WH_1 = 0x0,
ADDR_SURF_BANK_WH_2 = 0x1,
ADDR_SURF_BANK_WH_4 = 0x2,
ADDR_SURF_BANK_WH_8 = 0x3,
} BankWidthHeight;
typedef enum MacroTileAspect {
ADDR_SURF_MACRO_ASPECT_1 = 0x0,
ADDR_SURF_MACRO_ASPECT_2 = 0x1,
ADDR_SURF_MACRO_ASPECT_4 = 0x2,
ADDR_SURF_MACRO_ASPECT_8 = 0x3,
} MacroTileAspect;
typedef enum GATCL1RequestType {
GATCL1_TYPE_NORMAL = 0x0,
GATCL1_TYPE_SHOOTDOWN = 0x1,
GATCL1_TYPE_BYPASS = 0x2,
} GATCL1RequestType;
typedef enum TCC_CACHE_POLICIES {
TCC_CACHE_POLICY_LRU = 0x0,
TCC_CACHE_POLICY_STREAM = 0x1,
} TCC_CACHE_POLICIES;
typedef enum MTYPE {
MTYPE_NC_NV = 0x0,
MTYPE_NC = 0x1,
MTYPE_CC = 0x2,
MTYPE_UC = 0x3,
} MTYPE;
typedef enum PERFMON_COUNTER_MODE {
PERFMON_COUNTER_MODE_ACCUM = 0x0,
PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1,
PERFMON_COUNTER_MODE_MAX = 0x2,
PERFMON_COUNTER_MODE_DIRTY = 0x3,
PERFMON_COUNTER_MODE_SAMPLE = 0x4,
PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5,
PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6,
PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7,
PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8,
PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9,
PERFMON_COUNTER_MODE_RESERVED = 0xf,
} PERFMON_COUNTER_MODE;
typedef enum PERFMON_SPM_MODE {
PERFMON_SPM_MODE_OFF = 0x0,
PERFMON_SPM_MODE_16BIT_CLAMP = 0x1,
PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
PERFMON_SPM_MODE_32BIT_CLAMP = 0x3,
PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4,
PERFMON_SPM_MODE_RESERVED_5 = 0x5,
PERFMON_SPM_MODE_RESERVED_6 = 0x6,
PERFMON_SPM_MODE_RESERVED_7 = 0x7,
PERFMON_SPM_MODE_TEST_MODE_0 = 0x8,
PERFMON_SPM_MODE_TEST_MODE_1 = 0x9,
PERFMON_SPM_MODE_TEST_MODE_2 = 0xa,
} PERFMON_SPM_MODE;
typedef enum SurfaceTiling {
ARRAY_LINEAR = 0x0,
ARRAY_TILED = 0x1,
} SurfaceTiling;
typedef enum SurfaceArray {
ARRAY_1D = 0x0,
ARRAY_2D = 0x1,
ARRAY_3D = 0x2,
ARRAY_3D_SLICE = 0x3,
} SurfaceArray;
typedef enum ColorArray {
ARRAY_2D_ALT_COLOR = 0x0,
ARRAY_2D_COLOR = 0x1,
ARRAY_3D_SLICE_COLOR = 0x3,
} ColorArray;
typedef enum DepthArray {
ARRAY_2D_ALT_DEPTH = 0x0,
ARRAY_2D_DEPTH = 0x1,
} DepthArray;
typedef enum ENUM_NUM_SIMD_PER_CU {
NUM_SIMD_PER_CU = 0x4,
} ENUM_NUM_SIMD_PER_CU;
typedef enum MEM_PWR_FORCE_CTRL {
NO_FORCE_REQUEST = 0x0,
FORCE_LIGHT_SLEEP_REQUEST = 0x1,
FORCE_DEEP_SLEEP_REQUEST = 0x2,
FORCE_SHUT_DOWN_REQUEST = 0x3,
} MEM_PWR_FORCE_CTRL;
typedef enum MEM_PWR_FORCE_CTRL2 {
NO_FORCE_REQ = 0x0,
FORCE_LIGHT_SLEEP_REQ = 0x1,
} MEM_PWR_FORCE_CTRL2;
typedef enum MEM_PWR_DIS_CTRL {
ENABLE_MEM_PWR_CTRL = 0x0,
DISABLE_MEM_PWR_CTRL = 0x1,
} MEM_PWR_DIS_CTRL;
typedef enum MEM_PWR_SEL_CTRL {
DYNAMIC_SHUT_DOWN_ENABLE = 0x0,
DYNAMIC_DEEP_SLEEP_ENABLE = 0x1,
DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
} MEM_PWR_SEL_CTRL;
typedef enum MEM_PWR_SEL_CTRL2 {
DYNAMIC_DEEP_SLEEP_EN = 0x0,
DYNAMIC_LIGHT_SLEEP_EN = 0x1,
} MEM_PWR_SEL_CTRL2;
#endif /* SMU_7_1_3_ENUM_H */
drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h 0 → 100644
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