diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index e20cdc24c3bbd5f71d5f21db7187d0a101324609..76929d3905e4d7d90bbfde5e3c8e38abd3cf41fb 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -266,7 +266,7 @@ status = "disabled"; }; - rtc@10070000 { + rtc: rtc@10070000 { compatible = "samsung,s3c6410-rtc"; reg = <0x10070000 0x100>; interrupt-parent = <&pmu_system_controller>; diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts index 173ffa479ad3cb03eb6e6742663fafaccacf9d53..c032cde11d5c298a4f2ab616c2f090d7327f19d2 100644 --- a/arch/arm/boot/dts/exynos4412-trats2.dts +++ b/arch/arm/boot/dts/exynos4412-trats2.dts @@ -16,6 +16,7 @@ #include "exynos4412.dtsi" #include #include +#include / { model = "Samsung Trats 2 based on Exynos4412"; @@ -214,7 +215,7 @@ pinctrl-names = "default"; status = "okay"; - max77686_pmic@09 { + max77686: max77686_pmic@09 { compatible = "maxim,max77686"; interrupt-parent = <&gpx0>; interrupts = <7 0>; @@ -1304,3 +1305,9 @@ PIN_SLP(gpv4-0, INPUT, DOWN); }; }; + +&rtc { + status = "okay"; + clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>; + clock-names = "rtc", "rtc_src"; +}; diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts index 4efcf7c8f609c03d1e558375217a705b79b4cb93..9924b870423f7b3e65f265f734acbabfdaff583f 100644 --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts @@ -13,6 +13,7 @@ #include "exynos5420.dtsi" #include #include +#include / { model = "Insignal Arndale Octa evaluation board based on EXYNOS5420"; @@ -38,10 +39,6 @@ }; }; - rtc@101E0000 { - status = "okay"; - }; - codec@11000000 { samsung,mfc-r = <0x43000000 0x800000>; samsung,mfc-l = <0x51000000 0x800000>; @@ -387,3 +384,9 @@ samsung,pin-drv = <0>; }; }; + +&rtc { + status = "okay"; + clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>; + clock-names = "rtc", "rtc_src"; +};