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kernel_linux
提交 c402c0d9 编写于 作者: P Paul Walmsley
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Merge branches 'dmtimer_precleanup_3.1', 'hwmod_core_cleanup_a_3.1',... 

Merge branches 'dmtimer_precleanup_3.1', 'hwmod_core_cleanup_a_3.1', 'combine_common_hwmod_3.1', 'omap4_hwmod_data_cleanup_a_3.1', 'clock_cleanup_a_3.1', 'prcm_cleanup_a_3.1', 'omap_pm_cleanup_3.1' and 'omap_device_cleanup_3.1' into prcm-cleanup-3.1
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arch/arm/mach-omap2/Makefile
浏览文件 @ c402c0d9
...@@ -145,9 +145,19 @@ obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o ...@@ -145,9 +145,19 @@ obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o
obj-$(CONFIG_SOC_OMAP2430) += opp2430_data.o obj-$(CONFIG_SOC_OMAP2430) += opp2430_data.o
# hwmod data # hwmod data
obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2420_data.o obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_ipblock_data.o \
obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2430_data.o omap_hwmod_2xxx_3xxx_ipblock_data.o \
obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o omap_hwmod_2xxx_interconnect_data.o \
omap_hwmod_2xxx_3xxx_interconnect_data.o \
omap_hwmod_2420_data.o
obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2xxx_ipblock_data.o \
omap_hwmod_2xxx_3xxx_ipblock_data.o \
omap_hwmod_2xxx_interconnect_data.o \
omap_hwmod_2xxx_3xxx_interconnect_data.o \
omap_hwmod_2430_data.o
obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_ipblock_data.o \
omap_hwmod_2xxx_3xxx_interconnect_data.o \
omap_hwmod_3xxx_data.o
obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
# EMU peripherals # EMU peripherals
......
arch/arm/mach-omap2/clock44xx.h
浏览文件 @ c402c0d9
...@@ -8,13 +8,6 @@ ...@@ -8,13 +8,6 @@
#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK44XX_H #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK44XX_H
#define __ARCH_ARM_MACH_OMAP2_CLOCK44XX_H #define __ARCH_ARM_MACH_OMAP2_CLOCK44XX_H
/*
* XXX Missing values for the OMAP4 DPLL_USB
* XXX Missing min_multiplier values for all OMAP4 DPLLs
*/
#define OMAP4430_MAX_DPLL_MULT 2047
#define OMAP4430_MAX_DPLL_DIV 128
int omap4xxx_clk_init(void); int omap4xxx_clk_init(void);
#endif #endif
arch/arm/mach-omap2/clock44xx_data.c
浏览文件 @ c402c0d9
...@@ -53,9 +53,9 @@ static struct clk extalt_clkin_ck = { ...@@ -53,9 +53,9 @@ static struct clk extalt_clkin_ck = {
static struct clk pad_clks_ck = { static struct clk pad_clks_ck = {
.name = "pad_clks_ck", .name = "pad_clks_ck",
.rate = 12000000, .rate = 12000000,
.ops = &clkops_omap2_dflt, .ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_CLKSEL_ABE, .enable_reg = OMAP4430_CM_CLKSEL_ABE,
.enable_bit = OMAP4430_PAD_CLKS_GATE_SHIFT, .enable_bit = OMAP4430_PAD_CLKS_GATE_SHIFT,
}; };
static struct clk pad_slimbus_core_clks_ck = { static struct clk pad_slimbus_core_clks_ck = {
...@@ -73,9 +73,9 @@ static struct clk secure_32k_clk_src_ck = { ...@@ -73,9 +73,9 @@ static struct clk secure_32k_clk_src_ck = {
static struct clk slimbus_clk = { static struct clk slimbus_clk = {
.name = "slimbus_clk", .name = "slimbus_clk",
.rate = 12000000, .rate = 12000000,
.ops = &clkops_omap2_dflt, .ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_CLKSEL_ABE, .enable_reg = OMAP4430_CM_CLKSEL_ABE,
.enable_bit = OMAP4430_SLIMBUS_CLK_GATE_SHIFT, .enable_bit = OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
}; };
static struct clk sys_32k_ck = { static struct clk sys_32k_ck = {
...@@ -258,8 +258,8 @@ static struct dpll_data dpll_abe_dd = { ...@@ -258,8 +258,8 @@ static struct dpll_data dpll_abe_dd = {
.enable_mask = OMAP4430_DPLL_EN_MASK, .enable_mask = OMAP4430_DPLL_EN_MASK,
.autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
.idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
.max_multiplier = OMAP4430_MAX_DPLL_MULT, .max_multiplier = 2047,
.max_divider = OMAP4430_MAX_DPLL_DIV, .max_divider = 128,
.min_divider = 1, .min_divider = 1,
}; };
...@@ -278,10 +278,10 @@ static struct clk dpll_abe_ck = { ...@@ -278,10 +278,10 @@ static struct clk dpll_abe_ck = {
static struct clk dpll_abe_x2_ck = { static struct clk dpll_abe_x2_ck = {
.name = "dpll_abe_x2_ck", .name = "dpll_abe_x2_ck",
.parent = &dpll_abe_ck, .parent = &dpll_abe_ck,
.clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
.flags = CLOCK_CLKOUTX2, .flags = CLOCK_CLKOUTX2,
.ops = &clkops_omap4_dpllmx_ops, .ops = &clkops_omap4_dpllmx_ops,
.recalc = &omap3_clkoutx2_recalc, .recalc = &omap3_clkoutx2_recalc,
.clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
}; };
static const struct clksel_rate div31_1to31_rates[] = { static const struct clksel_rate div31_1to31_rates[] = {
...@@ -434,8 +434,8 @@ static struct dpll_data dpll_core_dd = { ...@@ -434,8 +434,8 @@ static struct dpll_data dpll_core_dd = {
.enable_mask = OMAP4430_DPLL_EN_MASK, .enable_mask = OMAP4430_DPLL_EN_MASK,
.autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
.idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
.max_multiplier = OMAP4430_MAX_DPLL_MULT, .max_multiplier = 2047,
.max_divider = OMAP4430_MAX_DPLL_DIV, .max_divider = 128,
.min_divider = 1, .min_divider = 1,
}; };
...@@ -622,11 +622,11 @@ static struct clk dpll_core_m3x2_ck = { ...@@ -622,11 +622,11 @@ static struct clk dpll_core_m3x2_ck = {
.clksel_reg = OMAP4430_CM_DIV_M3_DPLL_CORE, .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_CORE,
.clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
.ops = &clkops_omap2_dflt, .ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_DIV_M3_DPLL_CORE,
.enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate, .round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate, .set_rate = &omap2_clksel_set_rate,
.enable_reg = OMAP4430_CM_DIV_M3_DPLL_CORE,
.enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
}; };
static struct clk dpll_core_m7x2_ck = { static struct clk dpll_core_m7x2_ck = {
...@@ -672,8 +672,8 @@ static struct dpll_data dpll_iva_dd = { ...@@ -672,8 +672,8 @@ static struct dpll_data dpll_iva_dd = {
.enable_mask = OMAP4430_DPLL_EN_MASK, .enable_mask = OMAP4430_DPLL_EN_MASK,
.autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
.idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
.max_multiplier = OMAP4430_MAX_DPLL_MULT, .max_multiplier = 2047,
.max_divider = OMAP4430_MAX_DPLL_DIV, .max_divider = 128,
.min_divider = 1, .min_divider = 1,
}; };
...@@ -740,8 +740,8 @@ static struct dpll_data dpll_mpu_dd = { ...@@ -740,8 +740,8 @@ static struct dpll_data dpll_mpu_dd = {
.enable_mask = OMAP4430_DPLL_EN_MASK, .enable_mask = OMAP4430_DPLL_EN_MASK,
.autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
.idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
.max_multiplier = OMAP4430_MAX_DPLL_MULT, .max_multiplier = 2047,
.max_divider = OMAP4430_MAX_DPLL_DIV, .max_divider = 128,
.min_divider = 1, .min_divider = 1,
}; };
...@@ -813,8 +813,8 @@ static struct dpll_data dpll_per_dd = { ...@@ -813,8 +813,8 @@ static struct dpll_data dpll_per_dd = {
.enable_mask = OMAP4430_DPLL_EN_MASK, .enable_mask = OMAP4430_DPLL_EN_MASK,
.autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
.idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
.max_multiplier = OMAP4430_MAX_DPLL_MULT, .max_multiplier = 2047,
.max_divider = OMAP4430_MAX_DPLL_DIV, .max_divider = 128,
.min_divider = 1, .min_divider = 1,
}; };
...@@ -850,10 +850,10 @@ static struct clk dpll_per_m2_ck = { ...@@ -850,10 +850,10 @@ static struct clk dpll_per_m2_ck = {
static struct clk dpll_per_x2_ck = { static struct clk dpll_per_x2_ck = {
.name = "dpll_per_x2_ck", .name = "dpll_per_x2_ck",
.parent = &dpll_per_ck, .parent = &dpll_per_ck,
.clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
.flags = CLOCK_CLKOUTX2, .flags = CLOCK_CLKOUTX2,
.ops = &clkops_omap4_dpllmx_ops, .ops = &clkops_omap4_dpllmx_ops,
.recalc = &omap3_clkoutx2_recalc, .recalc = &omap3_clkoutx2_recalc,
.clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
}; };
static const struct clksel dpll_per_m2x2_div[] = { static const struct clksel dpll_per_m2x2_div[] = {
...@@ -880,11 +880,11 @@ static struct clk dpll_per_m3x2_ck = { ...@@ -880,11 +880,11 @@ static struct clk dpll_per_m3x2_ck = {
.clksel_reg = OMAP4430_CM_DIV_M3_DPLL_PER, .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_PER,
.clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
.ops = &clkops_omap2_dflt, .ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_DIV_M3_DPLL_PER,
.enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate, .round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate, .set_rate = &omap2_clksel_set_rate,
.enable_reg = OMAP4430_CM_DIV_M3_DPLL_PER,
.enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
}; };
static struct clk dpll_per_m4x2_ck = { static struct clk dpll_per_m4x2_ck = {
...@@ -935,63 +935,6 @@ static struct clk dpll_per_m7x2_ck = { ...@@ -935,63 +935,6 @@ static struct clk dpll_per_m7x2_ck = {
.set_rate = &omap2_clksel_set_rate, .set_rate = &omap2_clksel_set_rate,
}; };
/* DPLL_UNIPRO */
static struct dpll_data dpll_unipro_dd = {
.mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_UNIPRO,
.clk_bypass = &sys_clkin_ck,
.clk_ref = &sys_clkin_ck,
.control_reg = OMAP4430_CM_CLKMODE_DPLL_UNIPRO,
.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
.autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO,
.idlest_reg = OMAP4430_CM_IDLEST_DPLL_UNIPRO,
.mult_mask = OMAP4430_DPLL_MULT_MASK,
.div1_mask = OMAP4430_DPLL_DIV_MASK,
.enable_mask = OMAP4430_DPLL_EN_MASK,
.autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
.idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
.sddiv_mask = OMAP4430_DPLL_SD_DIV_MASK,
.max_multiplier = OMAP4430_MAX_DPLL_MULT,
.max_divider = OMAP4430_MAX_DPLL_DIV,
.min_divider = 1,
};
static struct clk dpll_unipro_ck = {
.name = "dpll_unipro_ck",
.parent = &sys_clkin_ck,
.dpll_data = &dpll_unipro_dd,
.init = &omap2_init_dpll_parent,
.ops = &clkops_omap3_noncore_dpll_ops,
.recalc = &omap3_dpll_recalc,
.round_rate = &omap2_dpll_round_rate,
.set_rate = &omap3_noncore_dpll_set_rate,
};
static struct clk dpll_unipro_x2_ck = {
.name = "dpll_unipro_x2_ck",
.parent = &dpll_unipro_ck,
.flags = CLOCK_CLKOUTX2,
.ops = &clkops_null,
.recalc = &omap3_clkoutx2_recalc,
};
static const struct clksel dpll_unipro_m2x2_div[] = {
{ .parent = &dpll_unipro_x2_ck, .rates = div31_1to31_rates },
{ .parent = NULL },
};
static struct clk dpll_unipro_m2x2_ck = {
.name = "dpll_unipro_m2x2_ck",
.parent = &dpll_unipro_x2_ck,
.clksel = dpll_unipro_m2x2_div,
.clksel_reg = OMAP4430_CM_DIV_M2_DPLL_UNIPRO,
.clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
.ops = &clkops_omap4_dpllmx_ops,
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
};
static struct clk usb_hs_clk_div_ck = { static struct clk usb_hs_clk_div_ck = {
.name = "usb_hs_clk_div_ck", .name = "usb_hs_clk_div_ck",
.parent = &dpll_abe_m3x2_ck, .parent = &dpll_abe_m3x2_ck,
...@@ -1015,8 +958,9 @@ static struct dpll_data dpll_usb_dd = { ...@@ -1015,8 +958,9 @@ static struct dpll_data dpll_usb_dd = {
.enable_mask = OMAP4430_DPLL_EN_MASK, .enable_mask = OMAP4430_DPLL_EN_MASK,
.autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
.idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
.max_multiplier = OMAP4430_MAX_DPLL_MULT, .sddiv_mask = OMAP4430_DPLL_SD_DIV_MASK,
.max_divider = OMAP4430_MAX_DPLL_DIV, .max_multiplier = 4095,
.max_divider = 256,
.min_divider = 1, .min_divider = 1,
}; };
...@@ -1035,8 +979,8 @@ static struct clk dpll_usb_ck = { ...@@ -1035,8 +979,8 @@ static struct clk dpll_usb_ck = {
static struct clk dpll_usb_clkdcoldo_ck = { static struct clk dpll_usb_clkdcoldo_ck = {
.name = "dpll_usb_clkdcoldo_ck", .name = "dpll_usb_clkdcoldo_ck",
.parent = &dpll_usb_ck, .parent = &dpll_usb_ck,
.ops = &clkops_omap4_dpllmx_ops,
.clksel_reg = OMAP4430_CM_CLKDCOLDO_DPLL_USB, .clksel_reg = OMAP4430_CM_CLKDCOLDO_DPLL_USB,
.ops = &clkops_omap4_dpllmx_ops,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -1169,19 +1113,6 @@ static struct clk func_96m_fclk = { ...@@ -1169,19 +1113,6 @@ static struct clk func_96m_fclk = {
.set_rate = &omap2_clksel_set_rate, .set_rate = &omap2_clksel_set_rate,
}; };
static const struct clksel hsmmc6_fclk_sel[] = {
{ .parent = &func_64m_fclk, .rates = div_1_0_rates },
{ .parent = &func_96m_fclk, .rates = div_1_1_rates },
{ .parent = NULL },
};
static struct clk hsmmc6_fclk = {
.name = "hsmmc6_fclk",
.parent = &func_64m_fclk,
.ops = &clkops_null,
.recalc = &followparent_recalc,
};
static const struct clksel_rate div2_1to8_rates[] = { static const struct clksel_rate div2_1to8_rates[] = {
{ .div = 1, .val = 0, .flags = RATE_IN_4430 }, { .div = 1, .val = 0, .flags = RATE_IN_4430 },
{ .div = 8, .val = 1, .flags = RATE_IN_4430 }, { .div = 8, .val = 1, .flags = RATE_IN_4430 },
...@@ -1264,6 +1195,21 @@ static struct clk l4_wkup_clk_mux_ck = { ...@@ -1264,6 +1195,21 @@ static struct clk l4_wkup_clk_mux_ck = {
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
}; };
static struct clk ocp_abe_iclk = {
.name = "ocp_abe_iclk",
.parent = &aess_fclk,
.ops = &clkops_null,
.recalc = &followparent_recalc,
};
static struct clk per_abe_24m_fclk = {
.name = "per_abe_24m_fclk",
.parent = &dpll_abe_m2_ck,
.ops = &clkops_null,
.fixed_div = 4,
.recalc = &omap_fixed_divisor_recalc,
};
static const struct clksel per_abe_nc_fclk_div[] = { static const struct clksel per_abe_nc_fclk_div[] = {
{ .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates }, { .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates },
{ .parent = NULL }, { .parent = NULL },
...@@ -1281,41 +1227,6 @@ static struct clk per_abe_nc_fclk = { ...@@ -1281,41 +1227,6 @@ static struct clk per_abe_nc_fclk = {
.set_rate = &omap2_clksel_set_rate, .set_rate = &omap2_clksel_set_rate,
}; };
static const struct clksel mcasp2_fclk_sel[] = {
{ .parent = &func_96m_fclk, .rates = div_1_0_rates },
{ .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
{ .parent = NULL },
};
static struct clk mcasp2_fclk = {
.name = "mcasp2_fclk",
.parent = &func_96m_fclk,
.ops = &clkops_null,
.recalc = &followparent_recalc,
};
static struct clk mcasp3_fclk = {
.name = "mcasp3_fclk",
.parent = &func_96m_fclk,
.ops = &clkops_null,
.recalc = &followparent_recalc,
};
static struct clk ocp_abe_iclk = {
.name = "ocp_abe_iclk",
.parent = &aess_fclk,
.ops = &clkops_null,
.recalc = &followparent_recalc,
};
static struct clk per_abe_24m_fclk = {
.name = "per_abe_24m_fclk",
.parent = &dpll_abe_m2_ck,
.ops = &clkops_null,
.fixed_div = 4,
.recalc = &omap_fixed_divisor_recalc,
};
static const struct clksel pmd_stm_clock_mux_sel[] = { static const struct clksel pmd_stm_clock_mux_sel[] = {
{ .parent = &sys_clkin_ck, .rates = div_1_0_rates }, { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
{ .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates }, { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
...@@ -1846,8 +1757,8 @@ static struct clk l3_instr_ick = { ...@@ -1846,8 +1757,8 @@ static struct clk l3_instr_ick = {
.ops = &clkops_omap2_dflt, .ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL, .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
.clkdm_name = "l3_instr_clkdm",
.flags = ENABLE_ON_INIT, .flags = ENABLE_ON_INIT,
.clkdm_name = "l3_instr_clkdm",
.parent = &l3_div_ck, .parent = &l3_div_ck,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -1857,8 +1768,8 @@ static struct clk l3_main_3_ick = { ...@@ -1857,8 +1768,8 @@ static struct clk l3_main_3_ick = {
.ops = &clkops_omap2_dflt, .ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL, .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
.clkdm_name = "l3_instr_clkdm",
.flags = ENABLE_ON_INIT, .flags = ENABLE_ON_INIT,
.clkdm_name = "l3_instr_clkdm",
.parent = &l3_div_ck, .parent = &l3_div_ck,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -1995,10 +1906,16 @@ static struct clk mcbsp3_fck = { ...@@ -1995,10 +1906,16 @@ static struct clk mcbsp3_fck = {
.clkdm_name = "abe_clkdm", .clkdm_name = "abe_clkdm",
}; };
static const struct clksel mcbsp4_sync_mux_sel[] = {
{ .parent = &func_96m_fclk, .rates = div_1_0_rates },
{ .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
{ .parent = NULL },
};
static struct clk mcbsp4_sync_mux_ck = { static struct clk mcbsp4_sync_mux_ck = {
.name = "mcbsp4_sync_mux_ck", .name = "mcbsp4_sync_mux_ck",
.parent = &func_96m_fclk, .parent = &func_96m_fclk,
.clksel = mcasp2_fclk_sel, .clksel = mcbsp4_sync_mux_sel,
.init = &omap2_init_clksel_parent, .init = &omap2_init_clksel_parent,
.clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
.clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
...@@ -2077,11 +1994,17 @@ static struct clk mcspi4_fck = { ...@@ -2077,11 +1994,17 @@ static struct clk mcspi4_fck = {
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
static const struct clksel hsmmc1_fclk_sel[] = {
{ .parent = &func_64m_fclk, .rates = div_1_0_rates },
{ .parent = &func_96m_fclk, .rates = div_1_1_rates },
{ .parent = NULL },
};
/* Merged hsmmc1_fclk into mmc1 */ /* Merged hsmmc1_fclk into mmc1 */
static struct clk mmc1_fck = { static struct clk mmc1_fck = {
.name = "mmc1_fck", .name = "mmc1_fck",
.parent = &func_64m_fclk, .parent = &func_64m_fclk,
.clksel = hsmmc6_fclk_sel, .clksel = hsmmc1_fclk_sel,
.init = &omap2_init_clksel_parent, .init = &omap2_init_clksel_parent,
.clksel_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL, .clksel_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
.clksel_mask = OMAP4430_CLKSEL_MASK, .clksel_mask = OMAP4430_CLKSEL_MASK,
...@@ -2096,7 +2019,7 @@ static struct clk mmc1_fck = { ...@@ -2096,7 +2019,7 @@ static struct clk mmc1_fck = {
static struct clk mmc2_fck = { static struct clk mmc2_fck = {
.name = "mmc2_fck", .name = "mmc2_fck",
.parent = &func_64m_fclk, .parent = &func_64m_fclk,
.clksel = hsmmc6_fclk_sel, .clksel = hsmmc1_fclk_sel,
.init = &omap2_init_clksel_parent, .init = &omap2_init_clksel_parent,
.clksel_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL, .clksel_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
.clksel_mask = OMAP4430_CLKSEL_MASK, .clksel_mask = OMAP4430_CLKSEL_MASK,
...@@ -2162,8 +2085,8 @@ static struct clk ocp_wp_noc_ick = { ...@@ -2162,8 +2085,8 @@ static struct clk ocp_wp_noc_ick = {
.ops = &clkops_omap2_dflt, .ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL, .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
.clkdm_name = "l3_instr_clkdm",
.flags = ENABLE_ON_INIT, .flags = ENABLE_ON_INIT,
.clkdm_name = "l3_instr_clkdm",
.parent = &l3_div_ck, .parent = &l3_div_ck,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -2895,6 +2818,7 @@ static struct clk auxclk2_ck = { ...@@ -2895,6 +2818,7 @@ static struct clk auxclk2_ck = {
.enable_reg = OMAP4_SCRM_AUXCLK2, .enable_reg = OMAP4_SCRM_AUXCLK2,
.enable_bit = OMAP4_ENABLE_SHIFT, .enable_bit = OMAP4_ENABLE_SHIFT,
}; };
static struct clk auxclk3_ck = { static struct clk auxclk3_ck = {
.name = "auxclk3_ck", .name = "auxclk3_ck",
.parent = &sys_clkin_ck, .parent = &sys_clkin_ck,
...@@ -3077,9 +3001,6 @@ static struct omap_clk omap44xx_clks[] = { ...@@ -3077,9 +3001,6 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, CK_443X), CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, CK_443X),
CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck, CK_443X), CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck, CK_443X),
CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck, CK_443X), CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck, CK_443X),
CLK(NULL, "dpll_unipro_ck", &dpll_unipro_ck, CK_443X),
CLK(NULL, "dpll_unipro_x2_ck", &dpll_unipro_x2_ck, CK_443X),
CLK(NULL, "dpll_unipro_m2x2_ck", &dpll_unipro_m2x2_ck, CK_443X),
CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X), CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X),
CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X), CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X),
CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck, CK_443X), CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck, CK_443X),
...@@ -3092,17 +3013,14 @@ static struct omap_clk omap44xx_clks[] = { ...@@ -3092,17 +3013,14 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "func_48mc_fclk", &func_48mc_fclk, CK_443X), CLK(NULL, "func_48mc_fclk", &func_48mc_fclk, CK_443X),
CLK(NULL, "func_64m_fclk", &func_64m_fclk, CK_443X), CLK(NULL, "func_64m_fclk", &func_64m_fclk, CK_443X),
CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_443X), CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_443X),
CLK(NULL, "hsmmc6_fclk", &hsmmc6_fclk, CK_443X),
CLK(NULL, "init_60m_fclk", &init_60m_fclk, CK_443X), CLK(NULL, "init_60m_fclk", &init_60m_fclk, CK_443X),
CLK(NULL, "l3_div_ck", &l3_div_ck, CK_443X), CLK(NULL, "l3_div_ck", &l3_div_ck, CK_443X),
CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X), CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X),
CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X), CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X),
CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X), CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X),
CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X),
CLK(NULL, "mcasp2_fclk", &mcasp2_fclk, CK_443X),
CLK(NULL, "mcasp3_fclk", &mcasp3_fclk, CK_443X),
CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X), CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X),
CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X), CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X),
CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X),
CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X), CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X),
CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X), CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X),
CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X), CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X),
...@@ -3204,7 +3122,6 @@ static struct omap_clk omap44xx_clks[] = { ...@@ -3204,7 +3122,6 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "uart2_fck", &uart2_fck, CK_443X), CLK(NULL, "uart2_fck", &uart2_fck, CK_443X),
CLK(NULL, "uart3_fck", &uart3_fck, CK_443X), CLK(NULL, "uart3_fck", &uart3_fck, CK_443X),
CLK(NULL, "uart4_fck", &uart4_fck, CK_443X), CLK(NULL, "uart4_fck", &uart4_fck, CK_443X),
CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X),
CLK("usbhs-omap.0", "fs_fck", &usb_host_fs_fck, CK_443X), CLK("usbhs-omap.0", "fs_fck", &usb_host_fs_fck, CK_443X),
CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X), CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X),
CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X), CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X),
...@@ -3216,9 +3133,7 @@ static struct omap_clk omap44xx_clks[] = { ...@@ -3216,9 +3133,7 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X), CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X),
CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X), CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X),
CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X), CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X),
CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X),
CLK("usbhs-omap.0", "hs_fck", &usb_host_hs_fck, CK_443X), CLK("usbhs-omap.0", "hs_fck", &usb_host_hs_fck, CK_443X),
CLK("usbhs-omap.0", "usbhost_ick", &dummy_ck, CK_443X),
CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X), CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X),
CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X), CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X),
CLK("musb-omap2430", "ick", &usb_otg_hs_ick, CK_443X), CLK("musb-omap2430", "ick", &usb_otg_hs_ick, CK_443X),
...@@ -3226,17 +3141,26 @@ static struct omap_clk omap44xx_clks[] = { ...@@ -3226,17 +3141,26 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X), CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X),
CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X), CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X),
CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X), CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X),
CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X),
CLK("usbhs-omap.0", "usbtll_ick", &usb_tll_hs_ick, CK_443X), CLK("usbhs-omap.0", "usbtll_ick", &usb_tll_hs_ick, CK_443X),
CLK("usbhs-omap.0", "usbtll_fck", &dummy_ck, CK_443X),
CLK(NULL, "usim_ck", &usim_ck, CK_443X), CLK(NULL, "usim_ck", &usim_ck, CK_443X),
CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), CLK(NULL, "usim_fclk", &usim_fclk, CK_443X),
CLK(NULL, "usim_fck", &usim_fck, CK_443X), CLK(NULL, "usim_fck", &usim_fck, CK_443X),
CLK("omap_wdt", "fck", &wd_timer2_fck, CK_443X), CLK("omap_wdt", "fck", &wd_timer2_fck, CK_443X),
CLK(NULL, "mailboxes_ick", &dummy_ck, CK_443X),
CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X), CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X),
CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X), CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X),
CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X), CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X),
CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X),
CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X),
CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X),
CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X),
CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X),
CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X),
CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X),
CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X),
CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X),
CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X),
CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X),
CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X),
CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X), CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X),
CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X), CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X),
CLK(NULL, "gpt2_ick", &dummy_ck, CK_443X), CLK(NULL, "gpt2_ick", &dummy_ck, CK_443X),
...@@ -3253,6 +3177,7 @@ static struct omap_clk omap44xx_clks[] = { ...@@ -3253,6 +3177,7 @@ static struct omap_clk omap44xx_clks[] = {
CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X), CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X),
CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X), CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X),
CLK("omap_i2c.4", "ick", &dummy_ck, CK_443X), CLK("omap_i2c.4", "ick", &dummy_ck, CK_443X),
CLK(NULL, "mailboxes_ick", &dummy_ck, CK_443X),
CLK("omap_hsmmc.0", "ick", &dummy_ck, CK_443X), CLK("omap_hsmmc.0", "ick", &dummy_ck, CK_443X),
CLK("omap_hsmmc.1", "ick", &dummy_ck, CK_443X), CLK("omap_hsmmc.1", "ick", &dummy_ck, CK_443X),
CLK("omap_hsmmc.2", "ick", &dummy_ck, CK_443X), CLK("omap_hsmmc.2", "ick", &dummy_ck, CK_443X),
...@@ -3270,19 +3195,9 @@ static struct omap_clk omap44xx_clks[] = { ...@@ -3270,19 +3195,9 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "uart2_ick", &dummy_ck, CK_443X), CLK(NULL, "uart2_ick", &dummy_ck, CK_443X),
CLK(NULL, "uart3_ick", &dummy_ck, CK_443X), CLK(NULL, "uart3_ick", &dummy_ck, CK_443X),
CLK(NULL, "uart4_ick", &dummy_ck, CK_443X), CLK(NULL, "uart4_ick", &dummy_ck, CK_443X),
CLK("usbhs-omap.0", "usbhost_ick", &dummy_ck, CK_443X),
CLK("usbhs-omap.0", "usbtll_fck", &dummy_ck, CK_443X),
CLK("omap_wdt", "ick", &dummy_ck, CK_443X), CLK("omap_wdt", "ick", &dummy_ck, CK_443X),
CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X),
CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X),
CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X),
CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X),
CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X),
CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X),
CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X),
CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X),
CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X),
CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X),
CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X),
CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X),
}; };
int __init omap4xxx_clk_init(void) int __init omap4xxx_clk_init(void)
......
arch/arm/mach-omap2/clockdomains44xx_data.c
浏览文件 @ c402c0d9
/* /*
* OMAP4 Clock domains framework * OMAP4 Clock domains framework
* *
* Copyright (C) 2009 Texas Instruments, Inc. * Copyright (C) 2009-2011 Texas Instruments, Inc.
* Copyright (C) 2009 Nokia Corporation * Copyright (C) 2009-2011 Nokia Corporation
* *
* Abhijit Pagare (abhijitpagare@ti.com) * Abhijit Pagare (abhijitpagare@ti.com)
* Benoit Cousson (b-cousson@ti.com) * Benoit Cousson (b-cousson@ti.com)
* Paul Walmsley (paul@pwsan.com)
* *
* This file is automatically generated from the OMAP hardware databases. * This file is automatically generated from the OMAP hardware databases.
* We respectfully ask that any modifications to this file be coordinated * We respectfully ask that any modifications to this file be coordinated
...@@ -32,7 +33,7 @@ ...@@ -32,7 +33,7 @@
/* Static Dependencies for OMAP4 Clock Domains */ /* Static Dependencies for OMAP4 Clock Domains */
static struct clkdm_dep ducati_wkup_sleep_deps[] = { static struct clkdm_dep d2d_wkup_sleep_deps[] = {
{ {
.clkdm_name = "abe_clkdm", .clkdm_name = "abe_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
...@@ -50,103 +51,103 @@ static struct clkdm_dep ducati_wkup_sleep_deps[] = { ...@@ -50,103 +51,103 @@ static struct clkdm_dep ducati_wkup_sleep_deps[] = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
}, },
{ {
.clkdm_name = "l3_dss_clkdm", .clkdm_name = "l3_emif_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
}, },
{ {
.clkdm_name = "l3_emif_clkdm", .clkdm_name = "l3_init_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
}, },
{ {
.clkdm_name = "l3_gfx_clkdm", .clkdm_name = "l4_cfg_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
}, },
{ {
.clkdm_name = "l3_init_clkdm", .clkdm_name = "l4_per_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
}, },
{ NULL },
};
static struct clkdm_dep ducati_wkup_sleep_deps[] = {
{ {
.clkdm_name = "l4_cfg_clkdm", .clkdm_name = "abe_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
}, },
{ {
.clkdm_name = "l4_per_clkdm", .clkdm_name = "ivahd_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
}, },
{ {
.clkdm_name = "l4_secure_clkdm", .clkdm_name = "l3_1_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
}, },
{ {
.clkdm_name = "l4_wkup_clkdm", .clkdm_name = "l3_2_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
}, },
{ {
.clkdm_name = "tesla_clkdm", .clkdm_name = "l3_dss_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
}, },
{ NULL },
};
static struct clkdm_dep iss_wkup_sleep_deps[] = {
{ {
.clkdm_name = "ivahd_clkdm", .clkdm_name = "l3_emif_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
}, },
{ {
.clkdm_name = "l3_1_clkdm", .clkdm_name = "l3_gfx_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
}, },
{ {
.clkdm_name = "l3_emif_clkdm", .clkdm_name = "l3_init_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
}, },
{ NULL },
};
static struct clkdm_dep ivahd_wkup_sleep_deps[] = {
{ {
.clkdm_name = "l3_1_clkdm", .clkdm_name = "l4_cfg_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
}, },
{ {
.clkdm_name = "l3_emif_clkdm", .clkdm_name = "l4_per_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
}, },
{ NULL },
};
static struct clkdm_dep l3_d2d_wkup_sleep_deps[] = {
{ {
.clkdm_name = "abe_clkdm", .clkdm_name = "l4_secure_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
}, },
{ {
.clkdm_name = "ivahd_clkdm", .clkdm_name = "l4_wkup_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
}, },
{ {
.clkdm_name = "l3_1_clkdm", .clkdm_name = "tesla_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
}, },
{ NULL },
};
static struct clkdm_dep iss_wkup_sleep_deps[] = {
{ {
.clkdm_name = "l3_2_clkdm", .clkdm_name = "ivahd_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
}, },
{ {
.clkdm_name = "l3_emif_clkdm", .clkdm_name = "l3_1_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
}, },
{ {
.clkdm_name = "l3_init_clkdm", .clkdm_name = "l3_emif_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
}, },
{ NULL },
};
static struct clkdm_dep ivahd_wkup_sleep_deps[] = {
{ {
.clkdm_name = "l4_cfg_clkdm", .clkdm_name = "l3_1_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
}, },
{ {
.clkdm_name = "l4_per_clkdm", .clkdm_name = "l3_emif_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
}, },
{ NULL }, { NULL },
...@@ -280,7 +281,7 @@ static struct clkdm_dep l4_secure_wkup_sleep_deps[] = { ...@@ -280,7 +281,7 @@ static struct clkdm_dep l4_secure_wkup_sleep_deps[] = {
{ NULL }, { NULL },
}; };
static struct clkdm_dep mpuss_wkup_sleep_deps[] = { static struct clkdm_dep mpu_wkup_sleep_deps[] = {
{ {
.clkdm_name = "abe_clkdm", .clkdm_name = "abe_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
...@@ -497,14 +498,14 @@ static struct clockdomain l3_init_44xx_clkdm = { ...@@ -497,14 +498,14 @@ static struct clockdomain l3_init_44xx_clkdm = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
}; };
static struct clockdomain mpuss_44xx_clkdm = { static struct clockdomain d2d_44xx_clkdm = {
.name = "mpuss_clkdm", .name = "d2d_clkdm",
.pwrdm = { .name = "mpu_pwrdm" }, .pwrdm = { .name = "core_pwrdm" },
.prcm_partition = OMAP4430_CM1_PARTITION, .prcm_partition = OMAP4430_CM2_PARTITION,
.cm_inst = OMAP4430_CM1_MPU_INST, .cm_inst = OMAP4430_CM2_CORE_INST,
.clkdm_offs = OMAP4430_CM1_MPU_MPU_CDOFFS, .clkdm_offs = OMAP4430_CM2_CORE_D2D_CDOFFS,
.wkdep_srcs = mpuss_wkup_sleep_deps, .wkdep_srcs = d2d_wkup_sleep_deps,
.sleepdep_srcs = mpuss_wkup_sleep_deps, .sleepdep_srcs = d2d_wkup_sleep_deps,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
}; };
...@@ -563,6 +564,18 @@ static struct clockdomain ducati_44xx_clkdm = { ...@@ -563,6 +564,18 @@ static struct clockdomain ducati_44xx_clkdm = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
}; };
static struct clockdomain mpu_44xx_clkdm = {
.name = "mpu_clkdm",
.pwrdm = { .name = "mpu_pwrdm" },
.prcm_partition = OMAP4430_CM1_PARTITION,
.cm_inst = OMAP4430_CM1_MPU_INST,
.clkdm_offs = OMAP4430_CM1_MPU_MPU_CDOFFS,
.wkdep_srcs = mpu_wkup_sleep_deps,
.sleepdep_srcs = mpu_wkup_sleep_deps,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
static struct clockdomain l3_2_44xx_clkdm = { static struct clockdomain l3_2_44xx_clkdm = {
.name = "l3_2_clkdm", .name = "l3_2_clkdm",
.pwrdm = { .name = "core_pwrdm" }, .pwrdm = { .name = "core_pwrdm" },
...@@ -585,18 +598,6 @@ static struct clockdomain l3_1_44xx_clkdm = { ...@@ -585,18 +598,6 @@ static struct clockdomain l3_1_44xx_clkdm = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
}; };
static struct clockdomain l3_d2d_44xx_clkdm = {
.name = "l3_d2d_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.prcm_partition = OMAP4430_CM2_PARTITION,
.cm_inst = OMAP4430_CM2_CORE_INST,
.clkdm_offs = OMAP4430_CM2_CORE_D2D_CDOFFS,
.wkdep_srcs = l3_d2d_wkup_sleep_deps,
.sleepdep_srcs = l3_d2d_wkup_sleep_deps,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
static struct clockdomain iss_44xx_clkdm = { static struct clockdomain iss_44xx_clkdm = {
.name = "iss_clkdm", .name = "iss_clkdm",
.pwrdm = { .name = "cam_pwrdm" }, .pwrdm = { .name = "cam_pwrdm" },
...@@ -655,6 +656,7 @@ static struct clockdomain l3_dma_44xx_clkdm = { ...@@ -655,6 +656,7 @@ static struct clockdomain l3_dma_44xx_clkdm = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
}; };
/* As clockdomains are added or removed above, this list must also be changed */
static struct clockdomain *clockdomains_omap44xx[] __initdata = { static struct clockdomain *clockdomains_omap44xx[] __initdata = {
&l4_cefuse_44xx_clkdm, &l4_cefuse_44xx_clkdm,
&l4_cfg_44xx_clkdm, &l4_cfg_44xx_clkdm,
...@@ -666,21 +668,21 @@ static struct clockdomain *clockdomains_omap44xx[] __initdata = { ...@@ -666,21 +668,21 @@ static struct clockdomain *clockdomains_omap44xx[] __initdata = {
&abe_44xx_clkdm, &abe_44xx_clkdm,
&l3_instr_44xx_clkdm, &l3_instr_44xx_clkdm,
&l3_init_44xx_clkdm, &l3_init_44xx_clkdm,
&mpuss_44xx_clkdm, &d2d_44xx_clkdm,
&mpu0_44xx_clkdm, &mpu0_44xx_clkdm,
&mpu1_44xx_clkdm, &mpu1_44xx_clkdm,
&l3_emif_44xx_clkdm, &l3_emif_44xx_clkdm,
&l4_ao_44xx_clkdm, &l4_ao_44xx_clkdm,
&ducati_44xx_clkdm, &ducati_44xx_clkdm,
&mpu_44xx_clkdm,
&l3_2_44xx_clkdm, &l3_2_44xx_clkdm,
&l3_1_44xx_clkdm, &l3_1_44xx_clkdm,
&l3_d2d_44xx_clkdm,
&iss_44xx_clkdm, &iss_44xx_clkdm,
&l3_dss_44xx_clkdm, &l3_dss_44xx_clkdm,
&l4_wkup_44xx_clkdm, &l4_wkup_44xx_clkdm,
&emu_sys_44xx_clkdm, &emu_sys_44xx_clkdm,
&l3_dma_44xx_clkdm, &l3_dma_44xx_clkdm,
NULL, NULL
}; };
void __init omap44xx_clockdomains_init(void) void __init omap44xx_clockdomains_init(void)
......
arch/arm/mach-omap2/cm-regbits-44xx.h
浏览文件 @ c402c0d9
...@@ -22,22 +22,18 @@ ...@@ -22,22 +22,18 @@
#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
/* /* Used by CM_L3_1_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
* Used by CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP,
* CM_TESLA_DYNAMICDEP
*/
#define OMAP4430_ABE_DYNDEP_SHIFT 3 #define OMAP4430_ABE_DYNDEP_SHIFT 3
#define OMAP4430_ABE_DYNDEP_MASK (1 << 3) #define OMAP4430_ABE_DYNDEP_MASK (1 << 3)
/* /*
* Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP, * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP,
* CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
* CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
*/ */
#define OMAP4430_ABE_STATDEP_SHIFT 3 #define OMAP4430_ABE_STATDEP_SHIFT 3
#define OMAP4430_ABE_STATDEP_MASK (1 << 3) #define OMAP4430_ABE_STATDEP_MASK (1 << 3)
/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */ /* Used by CM_L4CFG_DYNAMICDEP */
#define OMAP4430_ALWONCORE_DYNDEP_SHIFT 16 #define OMAP4430_ALWONCORE_DYNDEP_SHIFT 16
#define OMAP4430_ALWONCORE_DYNDEP_MASK (1 << 16) #define OMAP4430_ALWONCORE_DYNDEP_MASK (1 << 16)
...@@ -47,14 +43,13 @@ ...@@ -47,14 +43,13 @@
/* /*
* Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE, * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE,
* CM_AUTOIDLE_DPLL_CORE_RESTORE, CM_AUTOIDLE_DPLL_DDRPHY, * CM_AUTOIDLE_DPLL_DDRPHY, CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU,
* CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER, * CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB
* CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB
*/ */
#define OMAP4430_AUTO_DPLL_MODE_SHIFT 0 #define OMAP4430_AUTO_DPLL_MODE_SHIFT 0
#define OMAP4430_AUTO_DPLL_MODE_MASK (0x7 << 0) #define OMAP4430_AUTO_DPLL_MODE_MASK (0x7 << 0)
/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */ /* Used by CM_L4CFG_DYNAMICDEP */
#define OMAP4430_CEFUSE_DYNDEP_SHIFT 17 #define OMAP4430_CEFUSE_DYNDEP_SHIFT 17
#define OMAP4430_CEFUSE_DYNDEP_MASK (1 << 17) #define OMAP4430_CEFUSE_DYNDEP_MASK (1 << 17)
...@@ -82,15 +77,15 @@ ...@@ -82,15 +77,15 @@
#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT 8 #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK (1 << 8) #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK (1 << 8)
/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ /* Used by CM_MEMIF_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT 11 #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT 11
#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK (1 << 11) #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK (1 << 11)
/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ /* Used by CM_MEMIF_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT 12 #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT 12
#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK (1 << 12) #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK (1 << 12)
/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ /* Used by CM_MEMIF_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT 13 #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT 13
#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK (1 << 13) #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK (1 << 13)
...@@ -110,31 +105,31 @@ ...@@ -110,31 +105,31 @@
#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9 #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9
#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9) #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9)
/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ /* Used by CM_MEMIF_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT 9 #define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT 9
#define OMAP4430_CLKACTIVITY_DLL_CLK_MASK (1 << 9) #define OMAP4430_CLKACTIVITY_DLL_CLK_MASK (1 << 9)
/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ /* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT 9 #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT 9
#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK (1 << 9) #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK (1 << 9)
/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ /* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT 10 #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT 10
#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK (1 << 10) #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK (1 << 10)
/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ /* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT 11 #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT 11
#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK (1 << 11) #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK (1 << 11)
/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ /* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT 12 #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT 12
#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK (1 << 12) #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK (1 << 12)
/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ /* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT 13 #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT 13
#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK (1 << 13) #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK (1 << 13)
/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ /* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT 14 #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT 14
#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK (1 << 14) #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK (1 << 14)
...@@ -158,7 +153,7 @@ ...@@ -158,7 +153,7 @@
#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT 10 #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT 10
#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK (1 << 10) #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK (1 << 10)
/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ /* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT 15 #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT 15
#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK (1 << 15) #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK (1 << 15)
...@@ -170,55 +165,55 @@ ...@@ -170,55 +165,55 @@
#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT 11 #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT 11
#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK (1 << 11) #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK (1 << 11)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ /* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT 20 #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT 20
#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK (1 << 20) #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK (1 << 20)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ /* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT 26 #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT 26
#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK (1 << 26) #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK (1 << 26)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ /* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT 21 #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT 21
#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK (1 << 21) #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK (1 << 21)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ /* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT 27 #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT 27
#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK (1 << 27) #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK (1 << 27)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ /* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT 13 #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT 13
#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK (1 << 13) #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK (1 << 13)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ /* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT 12 #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT 12
#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK (1 << 12) #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK (1 << 12)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ /* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT 28 #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT 28
#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK (1 << 28) #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK (1 << 28)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ /* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT 29 #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT 29
#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK (1 << 29) #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK (1 << 29)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ /* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT 11 #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT 11
#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK (1 << 11) #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK (1 << 11)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ /* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT 16 #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT 16
#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK (1 << 16) #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK (1 << 16)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ /* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT 17 #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT 17
#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK (1 << 17) #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK (1 << 17)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ /* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT 18 #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT 18
#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK (1 << 18) #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK (1 << 18)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ /* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT 19 #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT 19
#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK (1 << 19) #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK (1 << 19)
...@@ -234,11 +229,11 @@ ...@@ -234,11 +229,11 @@
#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_SHIFT 10 #define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_SHIFT 10
#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_MASK (1 << 10) #define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_MASK (1 << 10)
/* Used by CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE */ /* Used by CM_L3_1_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT 8 #define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK (1 << 8) #define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK (1 << 8)
/* Used by CM_L3_2_CLKSTCTRL, CM_L3_2_CLKSTCTRL_RESTORE */ /* Used by CM_L3_2_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT 8 #define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK (1 << 8) #define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK (1 << 8)
...@@ -254,7 +249,7 @@ ...@@ -254,7 +249,7 @@
#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT 8 #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK (1 << 8) #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK (1 << 8)
/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ /* Used by CM_MEMIF_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT 8 #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK (1 << 8) #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK (1 << 8)
...@@ -262,7 +257,7 @@ ...@@ -262,7 +257,7 @@
#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT 8 #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK (1 << 8) #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK (1 << 8)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ /* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT 8 #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK (1 << 8) #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK (1 << 8)
...@@ -282,7 +277,7 @@ ...@@ -282,7 +277,7 @@
#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8 #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8) #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8)
/* Used by CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE */ /* Used by CM_L4CFG_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT 8 #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK (1 << 8) #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK (1 << 8)
...@@ -290,11 +285,11 @@ ...@@ -290,11 +285,11 @@
#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT 9 #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT 9
#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK (1 << 9) #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK (1 << 9)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ /* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT 9 #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT 9
#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK (1 << 9) #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK (1 << 9)
/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ /* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT 8 #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK (1 << 8) #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK (1 << 8)
...@@ -306,7 +301,7 @@ ...@@ -306,7 +301,7 @@
#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT 12 #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT 12
#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK (1 << 12) #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK (1 << 12)
/* Used by CM_MPU_CLKSTCTRL, CM_MPU_CLKSTCTRL_RESTORE */ /* Used by CM_MPU_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT 8 #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK (1 << 8) #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK (1 << 8)
...@@ -314,43 +309,43 @@ ...@@ -314,43 +309,43 @@
#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT 9 #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT 9
#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK (1 << 9) #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK (1 << 9)
/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ /* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT 16 #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT 16
#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK (1 << 16) #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK (1 << 16)
/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ /* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT 17 #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT 17
#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK (1 << 17) #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK (1 << 17)
/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ /* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT 18 #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT 18
#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK (1 << 18) #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK (1 << 18)
/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ /* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT 19 #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT 19
#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK (1 << 19) #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK (1 << 19)
/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ /* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT 25 #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT 25
#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK (1 << 25) #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK (1 << 25)
/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ /* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT 20 #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT 20
#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK (1 << 20) #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK (1 << 20)
/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ /* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT 21 #define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT 21
#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK (1 << 21) #define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK (1 << 21)
/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ /* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT 22 #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT 22
#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK (1 << 22) #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK (1 << 22)
/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ /* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT 24 #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT 24
#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK (1 << 24) #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK (1 << 24)
/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ /* Used by CM_MEMIF_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT 10 #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT 10
#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK (1 << 10) #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK (1 << 10)
...@@ -378,27 +373,27 @@ ...@@ -378,27 +373,27 @@
#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT 8 #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK (1 << 8) #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK (1 << 8)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ /* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT 22 #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT 22
#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK (1 << 22) #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK (1 << 22)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ /* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT 23 #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT 23
#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK (1 << 23) #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK (1 << 23)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ /* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT 24 #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT 24
#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK (1 << 24) #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK (1 << 24)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ /* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_SHIFT 10 #define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_SHIFT 10
#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_MASK (1 << 10) #define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_MASK (1 << 10)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ /* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_SHIFT 14 #define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_SHIFT 14
#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_MASK (1 << 14) #define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_MASK (1 << 14)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ /* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT 15 #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT 15
#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK (1 << 15) #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK (1 << 15)
...@@ -406,11 +401,11 @@ ...@@ -406,11 +401,11 @@
#define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT 10 #define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT 10
#define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK (1 << 10) #define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK (1 << 10)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ /* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT 30 #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT 30
#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK (1 << 30) #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK (1 << 30)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ /* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT 25 #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT 25
#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK (1 << 25) #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK (1 << 25)
...@@ -432,7 +427,7 @@ ...@@ -432,7 +427,7 @@
/* /*
* Renamed from CLKSEL Used by CM_ABE_DSS_SYS_CLKSEL, CM_ABE_PLL_REF_CLKSEL, * Renamed from CLKSEL Used by CM_ABE_DSS_SYS_CLKSEL, CM_ABE_PLL_REF_CLKSEL,
* CM_L4_WKUP_CLKSEL, CM_CLKSEL_DUCATI_ISS_ROOT, CM_CLKSEL_USB_60MHZ * CM_CLKSEL_DUCATI_ISS_ROOT, CM_CLKSEL_USB_60MHZ, CM_L4_WKUP_CLKSEL
*/ */
#define OMAP4430_CLKSEL_0_0_SHIFT 0 #define OMAP4430_CLKSEL_0_0_SHIFT 0
#define OMAP4430_CLKSEL_0_0_MASK (1 << 0) #define OMAP4430_CLKSEL_0_0_MASK (1 << 0)
...@@ -453,14 +448,11 @@ ...@@ -453,14 +448,11 @@
#define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24 #define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24
#define OMAP4430_CLKSEL_AESS_FCLK_MASK (1 << 24) #define OMAP4430_CLKSEL_AESS_FCLK_MASK (1 << 24)
/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */ /* Used by CM_CLKSEL_CORE */
#define OMAP4430_CLKSEL_CORE_SHIFT 0 #define OMAP4430_CLKSEL_CORE_SHIFT 0
#define OMAP4430_CLKSEL_CORE_MASK (1 << 0) #define OMAP4430_CLKSEL_CORE_MASK (1 << 0)
/* /* Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2 */
* Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2_RESTORE,
* CM_SHADOW_FREQ_CONFIG2
*/
#define OMAP4430_CLKSEL_CORE_1_1_SHIFT 1 #define OMAP4430_CLKSEL_CORE_1_1_SHIFT 1
#define OMAP4430_CLKSEL_CORE_1_1_MASK (1 << 1) #define OMAP4430_CLKSEL_CORE_1_1_MASK (1 << 1)
...@@ -484,18 +476,15 @@ ...@@ -484,18 +476,15 @@
#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT 26 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT 26
#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK (0x3 << 26) #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK (0x3 << 26)
/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */ /* Used by CM_CLKSEL_CORE */
#define OMAP4430_CLKSEL_L3_SHIFT 4 #define OMAP4430_CLKSEL_L3_SHIFT 4
#define OMAP4430_CLKSEL_L3_MASK (1 << 4) #define OMAP4430_CLKSEL_L3_MASK (1 << 4)
/* /* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */
* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2_RESTORE,
* CM_SHADOW_FREQ_CONFIG2
*/
#define OMAP4430_CLKSEL_L3_SHADOW_SHIFT 2 #define OMAP4430_CLKSEL_L3_SHADOW_SHIFT 2
#define OMAP4430_CLKSEL_L3_SHADOW_MASK (1 << 2) #define OMAP4430_CLKSEL_L3_SHADOW_MASK (1 << 2)
/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */ /* Used by CM_CLKSEL_CORE */
#define OMAP4430_CLKSEL_L4_SHIFT 8 #define OMAP4430_CLKSEL_L4_SHIFT 8
#define OMAP4430_CLKSEL_L4_MASK (1 << 8) #define OMAP4430_CLKSEL_L4_MASK (1 << 8)
...@@ -526,11 +515,11 @@ ...@@ -526,11 +515,11 @@
#define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT 24 #define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT 24
#define OMAP4430_CLKSEL_SOURCE_24_24_MASK (1 << 24) #define OMAP4430_CLKSEL_SOURCE_24_24_MASK (1 << 24)
/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
#define OMAP4430_CLKSEL_UTMI_P1_SHIFT 24 #define OMAP4430_CLKSEL_UTMI_P1_SHIFT 24
#define OMAP4430_CLKSEL_UTMI_P1_MASK (1 << 24) #define OMAP4430_CLKSEL_UTMI_P1_MASK (1 << 24)
/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
#define OMAP4430_CLKSEL_UTMI_P2_SHIFT 25 #define OMAP4430_CLKSEL_UTMI_P2_SHIFT 25
#define OMAP4430_CLKSEL_UTMI_P2_MASK (1 << 25) #define OMAP4430_CLKSEL_UTMI_P2_MASK (1 << 25)
...@@ -538,13 +527,10 @@ ...@@ -538,13 +527,10 @@
* Used by CM1_ABE_CLKSTCTRL, CM_ALWON_CLKSTCTRL, CM_CAM_CLKSTCTRL, * Used by CM1_ABE_CLKSTCTRL, CM_ALWON_CLKSTCTRL, CM_CAM_CLKSTCTRL,
* CM_CEFUSE_CLKSTCTRL, CM_D2D_CLKSTCTRL, CM_DSS_CLKSTCTRL, * CM_CEFUSE_CLKSTCTRL, CM_D2D_CLKSTCTRL, CM_DSS_CLKSTCTRL,
* CM_DUCATI_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_IVAHD_CLKSTCTRL, * CM_DUCATI_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_IVAHD_CLKSTCTRL,
* CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE, CM_L3INSTR_CLKSTCTRL, * CM_L3INIT_CLKSTCTRL, CM_L3INSTR_CLKSTCTRL, CM_L3_1_CLKSTCTRL,
* CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE, CM_L3_2_CLKSTCTRL, * CM_L3_2_CLKSTCTRL, CM_L4CFG_CLKSTCTRL, CM_L4PER_CLKSTCTRL,
* CM_L3_2_CLKSTCTRL_RESTORE, CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE, * CM_L4SEC_CLKSTCTRL, CM_MEMIF_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_SDMA_CLKSTCTRL,
* CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE, CM_L4SEC_CLKSTCTRL, * CM_TESLA_CLKSTCTRL, CM_WKUP_CLKSTCTRL
* CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE, CM_MPU_CLKSTCTRL,
* CM_MPU_CLKSTCTRL_RESTORE, CM_SDMA_CLKSTCTRL, CM_TESLA_CLKSTCTRL,
* CM_WKUP_CLKSTCTRL
*/ */
#define OMAP4430_CLKTRCTRL_SHIFT 0 #define OMAP4430_CLKTRCTRL_SHIFT 0
#define OMAP4430_CLKTRCTRL_MASK (0x3 << 0) #define OMAP4430_CLKTRCTRL_MASK (0x3 << 0)
...@@ -561,10 +547,7 @@ ...@@ -561,10 +547,7 @@
#define OMAP4430_CUSTOM_SHIFT 6 #define OMAP4430_CUSTOM_SHIFT 6
#define OMAP4430_CUSTOM_MASK (0x3 << 6) #define OMAP4430_CUSTOM_MASK (0x3 << 6)
/* /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
* CM_L4CFG_DYNAMICDEP_RESTORE
*/
#define OMAP4430_D2D_DYNDEP_SHIFT 18 #define OMAP4430_D2D_DYNDEP_SHIFT 18
#define OMAP4430_D2D_DYNDEP_MASK (1 << 18) #define OMAP4430_D2D_DYNDEP_MASK (1 << 18)
...@@ -574,31 +557,29 @@ ...@@ -574,31 +557,29 @@
/* /*
* Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE, * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE,
* CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE, CM_SSC_DELTAMSTEP_DPLL_DDRPHY, * CM_SSC_DELTAMSTEP_DPLL_DDRPHY, CM_SSC_DELTAMSTEP_DPLL_IVA,
* CM_SSC_DELTAMSTEP_DPLL_IVA, CM_SSC_DELTAMSTEP_DPLL_MPU, * CM_SSC_DELTAMSTEP_DPLL_MPU, CM_SSC_DELTAMSTEP_DPLL_PER,
* CM_SSC_DELTAMSTEP_DPLL_PER, CM_SSC_DELTAMSTEP_DPLL_UNIPRO, * CM_SSC_DELTAMSTEP_DPLL_UNIPRO, CM_SSC_DELTAMSTEP_DPLL_USB
* CM_SSC_DELTAMSTEP_DPLL_USB
*/ */
#define OMAP4430_DELTAMSTEP_SHIFT 0 #define OMAP4430_DELTAMSTEP_SHIFT 0
#define OMAP4430_DELTAMSTEP_MASK (0xfffff << 0) #define OMAP4430_DELTAMSTEP_MASK (0xfffff << 0)
/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */ /* Used by CM_DLL_CTRL */
#define OMAP4430_DLL_OVERRIDE_SHIFT 2 #define OMAP4430_DLL_OVERRIDE_SHIFT 0
#define OMAP4430_DLL_OVERRIDE_MASK (1 << 2) #define OMAP4430_DLL_OVERRIDE_MASK (1 << 0)
/* Renamed from DLL_OVERRIDE Used by CM_DLL_CTRL */ /* Renamed from DLL_OVERRIDE Used by CM_SHADOW_FREQ_CONFIG1 */
#define OMAP4430_DLL_OVERRIDE_0_0_SHIFT 0 #define OMAP4430_DLL_OVERRIDE_2_2_SHIFT 2
#define OMAP4430_DLL_OVERRIDE_0_0_MASK (1 << 0) #define OMAP4430_DLL_OVERRIDE_2_2_MASK (1 << 2)
/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */ /* Used by CM_SHADOW_FREQ_CONFIG1 */
#define OMAP4430_DLL_RESET_SHIFT 3 #define OMAP4430_DLL_RESET_SHIFT 3
#define OMAP4430_DLL_RESET_MASK (1 << 3) #define OMAP4430_DLL_RESET_MASK (1 << 3)
/* /*
* Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY,
* CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER,
* CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO, * CM_CLKSEL_DPLL_UNIPRO, CM_CLKSEL_DPLL_USB
* CM_CLKSEL_DPLL_USB
*/ */
#define OMAP4430_DPLL_BYP_CLKSEL_SHIFT 23 #define OMAP4430_DPLL_BYP_CLKSEL_SHIFT 23
#define OMAP4430_DPLL_BYP_CLKSEL_MASK (1 << 23) #define OMAP4430_DPLL_BYP_CLKSEL_MASK (1 << 23)
...@@ -607,28 +588,19 @@ ...@@ -607,28 +588,19 @@
#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8 #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8
#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8) #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8)
/* Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_CORE_RESTORE */ /* Used by CM_CLKSEL_DPLL_CORE */
#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT 20 #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT 20
#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK (1 << 20) #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK (1 << 20)
/* /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
* CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
*/
#define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT 0 #define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT 0
#define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK (0x1f << 0) #define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK (0x1f << 0)
/* /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
* CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
*/
#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT 5 #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT 5
#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK (1 << 5) #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK (1 << 5)
/* /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
* CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
*/
#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT 8 #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT 8
#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK (1 << 8) #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK (1 << 8)
...@@ -637,9 +609,8 @@ ...@@ -637,9 +609,8 @@
#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10) #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10)
/* /*
* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
* CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU, * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
* CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
*/ */
#define OMAP4430_DPLL_CLKOUT_DIV_SHIFT 0 #define OMAP4430_DPLL_CLKOUT_DIV_SHIFT 0
#define OMAP4430_DPLL_CLKOUT_DIV_MASK (0x1f << 0) #define OMAP4430_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
...@@ -649,9 +620,8 @@ ...@@ -649,9 +620,8 @@
#define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0) #define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0)
/* /*
* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
* CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU, * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
* CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
*/ */
#define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT 5 #define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT 5
#define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5) #define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5)
...@@ -661,29 +631,28 @@ ...@@ -661,29 +631,28 @@
#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK (1 << 7) #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK (1 << 7)
/* /*
* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
* CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU, * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
* CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
*/ */
#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT 8 #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT 8
#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8) #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8)
/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */ /* Used by CM_SHADOW_FREQ_CONFIG1 */
#define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT 8 #define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT 8
#define OMAP4430_DPLL_CORE_DPLL_EN_MASK (0x7 << 8) #define OMAP4430_DPLL_CORE_DPLL_EN_MASK (0x7 << 8)
/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */ /* Used by CM_SHADOW_FREQ_CONFIG1 */
#define OMAP4430_DPLL_CORE_M2_DIV_SHIFT 11 #define OMAP4430_DPLL_CORE_M2_DIV_SHIFT 11
#define OMAP4430_DPLL_CORE_M2_DIV_MASK (0x1f << 11) #define OMAP4430_DPLL_CORE_M2_DIV_MASK (0x1f << 11)
/* Used by CM_SHADOW_FREQ_CONFIG2, CM_SHADOW_FREQ_CONFIG2_RESTORE */ /* Used by CM_SHADOW_FREQ_CONFIG2 */
#define OMAP4430_DPLL_CORE_M5_DIV_SHIFT 3 #define OMAP4430_DPLL_CORE_M5_DIV_SHIFT 3
#define OMAP4430_DPLL_CORE_M5_DIV_MASK (0x1f << 3) #define OMAP4430_DPLL_CORE_M5_DIV_MASK (0x1f << 3)
/* /*
* Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY,
* CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER,
* CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO * CM_CLKSEL_DPLL_UNIPRO
*/ */
#define OMAP4430_DPLL_DIV_SHIFT 0 #define OMAP4430_DPLL_DIV_SHIFT 0
#define OMAP4430_DPLL_DIV_MASK (0x7f << 0) #define OMAP4430_DPLL_DIV_MASK (0x7f << 0)
...@@ -693,9 +662,8 @@ ...@@ -693,9 +662,8 @@
#define OMAP4430_DPLL_DIV_0_7_MASK (0xff << 0) #define OMAP4430_DPLL_DIV_0_7_MASK (0xff << 0)
/* /*
* Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
* CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
*/ */
#define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT 8 #define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT 8
#define OMAP4430_DPLL_DRIFTGUARD_EN_MASK (1 << 8) #define OMAP4430_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
...@@ -705,26 +673,25 @@ ...@@ -705,26 +673,25 @@
#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK (1 << 3) #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK (1 << 3)
/* /*
* Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
* CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
* CM_CLKMODE_DPLL_USB
*/ */
#define OMAP4430_DPLL_EN_SHIFT 0 #define OMAP4430_DPLL_EN_SHIFT 0
#define OMAP4430_DPLL_EN_MASK (0x7 << 0) #define OMAP4430_DPLL_EN_MASK (0x7 << 0)
/* /*
* Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
* CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO * CM_CLKMODE_DPLL_UNIPRO
*/ */
#define OMAP4430_DPLL_LPMODE_EN_SHIFT 10 #define OMAP4430_DPLL_LPMODE_EN_SHIFT 10
#define OMAP4430_DPLL_LPMODE_EN_MASK (1 << 10) #define OMAP4430_DPLL_LPMODE_EN_MASK (1 << 10)
/* /*
* Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY,
* CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER,
* CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO * CM_CLKSEL_DPLL_UNIPRO
*/ */
#define OMAP4430_DPLL_MULT_SHIFT 8 #define OMAP4430_DPLL_MULT_SHIFT 8
#define OMAP4430_DPLL_MULT_MASK (0x7ff << 8) #define OMAP4430_DPLL_MULT_MASK (0x7ff << 8)
...@@ -734,9 +701,9 @@ ...@@ -734,9 +701,9 @@
#define OMAP4430_DPLL_MULT_USB_MASK (0xfff << 8) #define OMAP4430_DPLL_MULT_USB_MASK (0xfff << 8)
/* /*
* Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
* CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO * CM_CLKMODE_DPLL_UNIPRO
*/ */
#define OMAP4430_DPLL_REGM4XEN_SHIFT 11 #define OMAP4430_DPLL_REGM4XEN_SHIFT 11
#define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11) #define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11)
...@@ -746,55 +713,46 @@ ...@@ -746,55 +713,46 @@
#define OMAP4430_DPLL_SD_DIV_MASK (0xff << 24) #define OMAP4430_DPLL_SD_DIV_MASK (0xff << 24)
/* /*
* Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
* CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
* CM_CLKMODE_DPLL_USB
*/ */
#define OMAP4430_DPLL_SSC_ACK_SHIFT 13 #define OMAP4430_DPLL_SSC_ACK_SHIFT 13
#define OMAP4430_DPLL_SSC_ACK_MASK (1 << 13) #define OMAP4430_DPLL_SSC_ACK_MASK (1 << 13)
/* /*
* Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
* CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
* CM_CLKMODE_DPLL_USB
*/ */
#define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT 14 #define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT 14
#define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK (1 << 14) #define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK (1 << 14)
/* /*
* Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
* CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
* CM_CLKMODE_DPLL_USB
*/ */
#define OMAP4430_DPLL_SSC_EN_SHIFT 12 #define OMAP4430_DPLL_SSC_EN_SHIFT 12
#define OMAP4430_DPLL_SSC_EN_MASK (1 << 12) #define OMAP4430_DPLL_SSC_EN_MASK (1 << 12)
/* /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
* CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP, CM_L4PER_DYNAMICDEP_RESTORE
*/
#define OMAP4430_DSS_DYNDEP_SHIFT 8 #define OMAP4430_DSS_DYNDEP_SHIFT 8
#define OMAP4430_DSS_DYNDEP_MASK (1 << 8) #define OMAP4430_DSS_DYNDEP_MASK (1 << 8)
/* /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP */
* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
* CM_SDMA_STATICDEP_RESTORE
*/
#define OMAP4430_DSS_STATDEP_SHIFT 8 #define OMAP4430_DSS_STATDEP_SHIFT 8
#define OMAP4430_DSS_STATDEP_MASK (1 << 8) #define OMAP4430_DSS_STATDEP_MASK (1 << 8)
/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */ /* Used by CM_L3_2_DYNAMICDEP */
#define OMAP4430_DUCATI_DYNDEP_SHIFT 0 #define OMAP4430_DUCATI_DYNDEP_SHIFT 0
#define OMAP4430_DUCATI_DYNDEP_MASK (1 << 0) #define OMAP4430_DUCATI_DYNDEP_MASK (1 << 0)
/* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE */ /* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP */
#define OMAP4430_DUCATI_STATDEP_SHIFT 0 #define OMAP4430_DUCATI_STATDEP_SHIFT 0
#define OMAP4430_DUCATI_STATDEP_MASK (1 << 0) #define OMAP4430_DUCATI_STATDEP_MASK (1 << 0)
/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */ /* Used by CM_SHADOW_FREQ_CONFIG1 */
#define OMAP4430_FREQ_UPDATE_SHIFT 0 #define OMAP4430_FREQ_UPDATE_SHIFT 0
#define OMAP4430_FREQ_UPDATE_MASK (1 << 0) #define OMAP4430_FREQ_UPDATE_MASK (1 << 0)
...@@ -802,7 +760,7 @@ ...@@ -802,7 +760,7 @@
#define OMAP4430_FUNC_SHIFT 16 #define OMAP4430_FUNC_SHIFT 16
#define OMAP4430_FUNC_MASK (0xfff << 16) #define OMAP4430_FUNC_MASK (0xfff << 16)
/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */ /* Used by CM_L3_2_DYNAMICDEP */
#define OMAP4430_GFX_DYNDEP_SHIFT 10 #define OMAP4430_GFX_DYNDEP_SHIFT 10
#define OMAP4430_GFX_DYNDEP_MASK (1 << 10) #define OMAP4430_GFX_DYNDEP_MASK (1 << 10)
...@@ -810,119 +768,95 @@ ...@@ -810,119 +768,95 @@
#define OMAP4430_GFX_STATDEP_SHIFT 10 #define OMAP4430_GFX_STATDEP_SHIFT 10
#define OMAP4430_GFX_STATDEP_MASK (1 << 10) #define OMAP4430_GFX_STATDEP_MASK (1 << 10)
/* Used by CM_SHADOW_FREQ_CONFIG2, CM_SHADOW_FREQ_CONFIG2_RESTORE */ /* Used by CM_SHADOW_FREQ_CONFIG2 */
#define OMAP4430_GPMC_FREQ_UPDATE_SHIFT 0 #define OMAP4430_GPMC_FREQ_UPDATE_SHIFT 0
#define OMAP4430_GPMC_FREQ_UPDATE_MASK (1 << 0) #define OMAP4430_GPMC_FREQ_UPDATE_MASK (1 << 0)
/* /*
* Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE, * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
* CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER * CM_DIV_M4_DPLL_PER
*/ */
#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT 0 #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT 0
#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0) #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0)
/* /*
* Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE, * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
* CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER * CM_DIV_M4_DPLL_PER
*/ */
#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5 #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5
#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5) #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5)
/* /*
* Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE, * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
* CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER * CM_DIV_M4_DPLL_PER
*/ */
#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8 #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8
#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8) #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8)
/* /*
* Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE, * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
* CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER * CM_DIV_M4_DPLL_PER
*/ */
#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12 #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12
#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12) #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12)
/* /*
* Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE, * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
* CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER * CM_DIV_M5_DPLL_PER
*/ */
#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT 0 #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT 0
#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0) #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0)
/* /*
* Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE, * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
* CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER * CM_DIV_M5_DPLL_PER
*/ */
#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5 #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5
#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5) #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5)
/* /*
* Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE, * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
* CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER * CM_DIV_M5_DPLL_PER
*/ */
#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8 #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8
#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8) #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8)
/* /*
* Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE, * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
* CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER * CM_DIV_M5_DPLL_PER
*/ */
#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12 #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12
#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12) #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12)
/* /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
* CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
*/
#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT 0 #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT 0
#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0) #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0)
/* /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
* CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
*/
#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5 #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5
#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5) #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5)
/* /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
* CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
*/
#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8 #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8
#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8) #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8)
/* /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
* CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
*/
#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12 #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12
#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12) #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12)
/* /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
* CM_DIV_M7_DPLL_PER
*/
#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT 0 #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT 0
#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK (0x1f << 0) #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK (0x1f << 0)
/* /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
* CM_DIV_M7_DPLL_PER
*/
#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT 5 #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT 5
#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK (1 << 5) #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK (1 << 5)
/* /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
* CM_DIV_M7_DPLL_PER
*/
#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT 8 #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT 8
#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK (1 << 8) #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK (1 << 8)
/* /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
* CM_DIV_M7_DPLL_PER
*/
#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT 12 #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT 12
#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK (1 << 12) #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK (1 << 12)
...@@ -934,8 +868,7 @@ ...@@ -934,8 +868,7 @@
* CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL, * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL,
* CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL,
* CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
* CM_CM1_PROFILING_CLKCTRL, CM_CM1_PROFILING_CLKCTRL_RESTORE, * CM_CM1_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL,
* CM_CM2_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL_RESTORE,
* CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL,
* CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
* CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
...@@ -944,30 +877,24 @@ ...@@ -944,30 +877,24 @@
* CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
* CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
* CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL, * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL,
* CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_HOST_FS_CLKCTRL, * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
* CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL, * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL,
* CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, CM_L3INIT_XHPI_CLKCTRL, * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL,
* CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL_RESTORE,
* CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE,
* CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE,
* CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL, * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL,
* CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL, * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL,
* CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL, * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL,
* CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL, * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
* CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL, * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
* CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
* CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE, * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL,
* CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE, * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL,
* CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE, * CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL,
* CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE, * CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL,
* CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE, * CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL,
* CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, * CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL,
* CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, * CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL,
* CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, * CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL,
* CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, * CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
* CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL,
* CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL,
* CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
* CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL,
* CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
* CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
...@@ -983,166 +910,148 @@ ...@@ -983,166 +910,148 @@
#define OMAP4430_IDLEST_SHIFT 16 #define OMAP4430_IDLEST_SHIFT 16
#define OMAP4430_IDLEST_MASK (0x3 << 16) #define OMAP4430_IDLEST_MASK (0x3 << 16)
/* /* Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
* Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP,
* CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE
*/
#define OMAP4430_ISS_DYNDEP_SHIFT 9 #define OMAP4430_ISS_DYNDEP_SHIFT 9
#define OMAP4430_ISS_DYNDEP_MASK (1 << 9) #define OMAP4430_ISS_DYNDEP_MASK (1 << 9)
/* /*
* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
* CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP * CM_TESLA_STATICDEP
*/ */
#define OMAP4430_ISS_STATDEP_SHIFT 9 #define OMAP4430_ISS_STATDEP_SHIFT 9
#define OMAP4430_ISS_STATDEP_MASK (1 << 9) #define OMAP4430_ISS_STATDEP_MASK (1 << 9)
/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_TESLA_DYNAMICDEP */ /* Used by CM_L3_2_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
#define OMAP4430_IVAHD_DYNDEP_SHIFT 2 #define OMAP4430_IVAHD_DYNDEP_SHIFT 2
#define OMAP4430_IVAHD_DYNDEP_MASK (1 << 2) #define OMAP4430_IVAHD_DYNDEP_MASK (1 << 2)
/* /*
* Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
* CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_L3INIT_STATICDEP,
* CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
* CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
*/ */
#define OMAP4430_IVAHD_STATDEP_SHIFT 2 #define OMAP4430_IVAHD_STATDEP_SHIFT 2
#define OMAP4430_IVAHD_STATDEP_MASK (1 << 2) #define OMAP4430_IVAHD_STATDEP_MASK (1 << 2)
/* /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
* CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP, CM_L4PER_DYNAMICDEP_RESTORE
*/
#define OMAP4430_L3INIT_DYNDEP_SHIFT 7 #define OMAP4430_L3INIT_DYNDEP_SHIFT 7
#define OMAP4430_L3INIT_DYNDEP_MASK (1 << 7) #define OMAP4430_L3INIT_DYNDEP_MASK (1 << 7)
/* /*
* Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP, * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_MPU_STATICDEP,
* CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
* CM_TESLA_STATICDEP
*/ */
#define OMAP4430_L3INIT_STATDEP_SHIFT 7 #define OMAP4430_L3INIT_STATDEP_SHIFT 7
#define OMAP4430_L3INIT_STATDEP_MASK (1 << 7) #define OMAP4430_L3INIT_STATDEP_MASK (1 << 7)
/* /*
* Used by CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_2_DYNAMICDEP, * Used by CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_2_DYNAMICDEP,
* CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, * CM_L4CFG_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
* CM_L4CFG_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
*/ */
#define OMAP4430_L3_1_DYNDEP_SHIFT 5 #define OMAP4430_L3_1_DYNDEP_SHIFT 5
#define OMAP4430_L3_1_DYNDEP_MASK (1 << 5) #define OMAP4430_L3_1_DYNDEP_MASK (1 << 5)
/* /*
* Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
* CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP, * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
* CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
* CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
*/ */
#define OMAP4430_L3_1_STATDEP_SHIFT 5 #define OMAP4430_L3_1_STATDEP_SHIFT 5
#define OMAP4430_L3_1_STATDEP_MASK (1 << 5) #define OMAP4430_L3_1_STATDEP_MASK (1 << 5)
/* /*
* Used by CM_CAM_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE, * Used by CM_CAM_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP,
* CM_DUCATI_DYNAMICDEP, CM_EMU_DYNAMICDEP, CM_GFX_DYNAMICDEP, * CM_EMU_DYNAMICDEP, CM_GFX_DYNAMICDEP, CM_IVAHD_DYNAMICDEP,
* CM_IVAHD_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_1_DYNAMICDEP, * CM_L3INIT_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
* CM_L3_1_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, * CM_L4SEC_DYNAMICDEP, CM_SDMA_DYNAMICDEP
* CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4SEC_DYNAMICDEP, CM_SDMA_DYNAMICDEP
*/ */
#define OMAP4430_L3_2_DYNDEP_SHIFT 6 #define OMAP4430_L3_2_DYNDEP_SHIFT 6
#define OMAP4430_L3_2_DYNDEP_MASK (1 << 6) #define OMAP4430_L3_2_DYNDEP_MASK (1 << 6)
/* /*
* Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
* CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP, * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
* CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
* CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
*/ */
#define OMAP4430_L3_2_STATDEP_SHIFT 6 #define OMAP4430_L3_2_STATDEP_SHIFT 6
#define OMAP4430_L3_2_STATDEP_MASK (1 << 6) #define OMAP4430_L3_2_STATDEP_MASK (1 << 6)
/* Used by CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE */ /* Used by CM_L3_1_DYNAMICDEP */
#define OMAP4430_L4CFG_DYNDEP_SHIFT 12 #define OMAP4430_L4CFG_DYNDEP_SHIFT 12
#define OMAP4430_L4CFG_DYNDEP_MASK (1 << 12) #define OMAP4430_L4CFG_DYNDEP_MASK (1 << 12)
/* /*
* Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP, * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP,
* CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
* CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
*/ */
#define OMAP4430_L4CFG_STATDEP_SHIFT 12 #define OMAP4430_L4CFG_STATDEP_SHIFT 12
#define OMAP4430_L4CFG_STATDEP_MASK (1 << 12) #define OMAP4430_L4CFG_STATDEP_MASK (1 << 12)
/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */ /* Used by CM_L3_2_DYNAMICDEP */
#define OMAP4430_L4PER_DYNDEP_SHIFT 13 #define OMAP4430_L4PER_DYNDEP_SHIFT 13
#define OMAP4430_L4PER_DYNDEP_MASK (1 << 13) #define OMAP4430_L4PER_DYNDEP_MASK (1 << 13)
/* /*
* Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP, * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP,
* CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, * CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
* CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
*/ */
#define OMAP4430_L4PER_STATDEP_SHIFT 13 #define OMAP4430_L4PER_STATDEP_SHIFT 13
#define OMAP4430_L4PER_STATDEP_MASK (1 << 13) #define OMAP4430_L4PER_STATDEP_MASK (1 << 13)
/* /* Used by CM_L3_2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP,
* CM_L4PER_DYNAMICDEP_RESTORE
*/
#define OMAP4430_L4SEC_DYNDEP_SHIFT 14 #define OMAP4430_L4SEC_DYNDEP_SHIFT 14
#define OMAP4430_L4SEC_DYNDEP_MASK (1 << 14) #define OMAP4430_L4SEC_DYNDEP_MASK (1 << 14)
/* /*
* Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP,
* CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE * CM_SDMA_STATICDEP
*/ */
#define OMAP4430_L4SEC_STATDEP_SHIFT 14 #define OMAP4430_L4SEC_STATDEP_SHIFT 14
#define OMAP4430_L4SEC_STATDEP_MASK (1 << 14) #define OMAP4430_L4SEC_STATDEP_MASK (1 << 14)
/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */ /* Used by CM_L4CFG_DYNAMICDEP */
#define OMAP4430_L4WKUP_DYNDEP_SHIFT 15 #define OMAP4430_L4WKUP_DYNDEP_SHIFT 15
#define OMAP4430_L4WKUP_DYNDEP_MASK (1 << 15) #define OMAP4430_L4WKUP_DYNDEP_MASK (1 << 15)
/* /*
* Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP,
* CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
*/ */
#define OMAP4430_L4WKUP_STATDEP_SHIFT 15 #define OMAP4430_L4WKUP_STATDEP_SHIFT 15
#define OMAP4430_L4WKUP_STATDEP_MASK (1 << 15) #define OMAP4430_L4WKUP_STATDEP_MASK (1 << 15)
/* /*
* Used by CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE, CM_L3_1_DYNAMICDEP, * Used by CM_D2D_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
* CM_L3_1_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, * CM_MPU_DYNAMICDEP
* CM_L4CFG_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP
*/ */
#define OMAP4430_MEMIF_DYNDEP_SHIFT 4 #define OMAP4430_MEMIF_DYNDEP_SHIFT 4
#define OMAP4430_MEMIF_DYNDEP_MASK (1 << 4) #define OMAP4430_MEMIF_DYNDEP_MASK (1 << 4)
/* /*
* Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
* CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP, * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
* CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
* CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
*/ */
#define OMAP4430_MEMIF_STATDEP_SHIFT 4 #define OMAP4430_MEMIF_STATDEP_SHIFT 4
#define OMAP4430_MEMIF_STATDEP_MASK (1 << 4) #define OMAP4430_MEMIF_STATDEP_MASK (1 << 4)
/* /*
* Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
* CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, CM_SSC_MODFREQDIV_DPLL_DDRPHY, * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA,
* CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU, * CM_SSC_MODFREQDIV_DPLL_MPU, CM_SSC_MODFREQDIV_DPLL_PER,
* CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO, * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB
* CM_SSC_MODFREQDIV_DPLL_USB
*/ */
#define OMAP4430_MODFREQDIV_EXPONENT_SHIFT 8 #define OMAP4430_MODFREQDIV_EXPONENT_SHIFT 8
#define OMAP4430_MODFREQDIV_EXPONENT_MASK (0x7 << 8) #define OMAP4430_MODFREQDIV_EXPONENT_MASK (0x7 << 8)
/* /*
* Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
* CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, CM_SSC_MODFREQDIV_DPLL_DDRPHY, * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA,
* CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU, * CM_SSC_MODFREQDIV_DPLL_MPU, CM_SSC_MODFREQDIV_DPLL_PER,
* CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO, * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB
* CM_SSC_MODFREQDIV_DPLL_USB
*/ */
#define OMAP4430_MODFREQDIV_MANTISSA_SHIFT 0 #define OMAP4430_MODFREQDIV_MANTISSA_SHIFT 0
#define OMAP4430_MODFREQDIV_MANTISSA_MASK (0x7f << 0) #define OMAP4430_MODFREQDIV_MANTISSA_MASK (0x7f << 0)
...@@ -1155,8 +1064,7 @@ ...@@ -1155,8 +1064,7 @@
* CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL, * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL,
* CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL,
* CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
* CM_CM1_PROFILING_CLKCTRL, CM_CM1_PROFILING_CLKCTRL_RESTORE, * CM_CM1_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL,
* CM_CM2_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL_RESTORE,
* CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL,
* CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
* CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
...@@ -1165,30 +1073,24 @@ ...@@ -1165,30 +1073,24 @@
* CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
* CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
* CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL, * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL,
* CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_HOST_FS_CLKCTRL, * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
* CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL, * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL,
* CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, CM_L3INIT_XHPI_CLKCTRL, * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL,
* CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL_RESTORE,
* CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE,
* CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE,
* CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL, * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL,
* CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL, * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL,
* CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL, * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL,
* CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL, * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
* CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL, * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
* CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
* CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE, * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL,
* CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE, * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL,
* CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE, * CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL,
* CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE, * CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL,
* CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE, * CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL,
* CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, * CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL,
* CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, * CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL,
* CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, * CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL,
* CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, * CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
* CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL,
* CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL,
* CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
* CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL,
* CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
* CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
...@@ -1221,11 +1123,9 @@ ...@@ -1221,11 +1123,9 @@
#define OMAP4430_OPTFCLKEN_CTRLCLK_MASK (1 << 8) #define OMAP4430_OPTFCLKEN_CTRLCLK_MASK (1 << 8)
/* /*
* Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE, * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL,
* CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE, * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL,
* CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE, * CM_WKUP_GPIO1_CLKCTRL
* CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE,
* CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE, CM_WKUP_GPIO1_CLKCTRL
*/ */
#define OMAP4430_OPTFCLKEN_DBCLK_SHIFT 8 #define OMAP4430_OPTFCLKEN_DBCLK_SHIFT 8
#define OMAP4430_OPTFCLKEN_DBCLK_MASK (1 << 8) #define OMAP4430_OPTFCLKEN_DBCLK_MASK (1 << 8)
...@@ -1254,23 +1154,23 @@ ...@@ -1254,23 +1154,23 @@
#define OMAP4430_OPTFCLKEN_FCLK2_SHIFT 10 #define OMAP4430_OPTFCLKEN_FCLK2_SHIFT 10
#define OMAP4430_OPTFCLKEN_FCLK2_MASK (1 << 10) #define OMAP4430_OPTFCLKEN_FCLK2_MASK (1 << 10)
/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
#define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT 15 #define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT 15
#define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK (1 << 15) #define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK (1 << 15)
/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13 #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13
#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK (1 << 13) #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK (1 << 13)
/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14 #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14
#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK (1 << 14) #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK (1 << 14)
/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11 #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11
#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK (1 << 11) #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK (1 << 11)
/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12 #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12
#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK (1 << 12) #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK (1 << 12)
...@@ -1306,27 +1206,27 @@ ...@@ -1306,27 +1206,27 @@
#define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT 8 #define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT 8
#define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK (1 << 8) #define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK (1 << 8)
/* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ /* Used by CM_L3INIT_USB_TLL_CLKCTRL */
#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT 8 #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT 8
#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK (1 << 8) #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK (1 << 8)
/* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ /* Used by CM_L3INIT_USB_TLL_CLKCTRL */
#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT 9 #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT 9
#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK (1 << 9) #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK (1 << 9)
/* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ /* Used by CM_L3INIT_USB_TLL_CLKCTRL */
#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT 10 #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT 10
#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK (1 << 10) #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK (1 << 10)
/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8 #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8
#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK (1 << 8) #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK (1 << 8)
/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9 #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9
#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK (1 << 9) #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK (1 << 9)
/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10 #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10
#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK (1 << 10) #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK (1 << 10)
...@@ -1374,7 +1274,7 @@ ...@@ -1374,7 +1274,7 @@
#define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT 22 #define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT 22
#define OMAP4430_PMD_TRACE_MUX_CTRL_MASK (0x3 << 22) #define OMAP4430_PMD_TRACE_MUX_CTRL_MASK (0x3 << 22)
/* Used by CM_DYN_DEP_PRESCAL, CM_DYN_DEP_PRESCAL_RESTORE */ /* Used by CM_DYN_DEP_PRESCAL */
#define OMAP4430_PRESCAL_SHIFT 0 #define OMAP4430_PRESCAL_SHIFT 0
#define OMAP4430_PRESCAL_MASK (0x3f << 0) #define OMAP4430_PRESCAL_MASK (0x3f << 0)
...@@ -1382,10 +1282,7 @@ ...@@ -1382,10 +1282,7 @@
#define OMAP4430_R_RTL_SHIFT 11 #define OMAP4430_R_RTL_SHIFT 11
#define OMAP4430_R_RTL_MASK (0x1f << 11) #define OMAP4430_R_RTL_MASK (0x1f << 11)
/* /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL */
* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE,
* CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE
*/
#define OMAP4430_SAR_MODE_SHIFT 4 #define OMAP4430_SAR_MODE_SHIFT 4
#define OMAP4430_SAR_MODE_MASK (1 << 4) #define OMAP4430_SAR_MODE_MASK (1 << 4)
...@@ -1397,7 +1294,7 @@ ...@@ -1397,7 +1294,7 @@
#define OMAP4430_SCHEME_SHIFT 30 #define OMAP4430_SCHEME_SHIFT 30
#define OMAP4430_SCHEME_MASK (0x3 << 30) #define OMAP4430_SCHEME_MASK (0x3 << 30)
/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */ /* Used by CM_L4CFG_DYNAMICDEP */
#define OMAP4430_SDMA_DYNDEP_SHIFT 11 #define OMAP4430_SDMA_DYNDEP_SHIFT 11
#define OMAP4430_SDMA_DYNDEP_MASK (1 << 11) #define OMAP4430_SDMA_DYNDEP_MASK (1 << 11)
...@@ -1417,10 +1314,10 @@ ...@@ -1417,10 +1314,10 @@
* CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
* CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
* CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
* CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL,
* CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL, * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL,
* CM_L3INIT_XHPI_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL, * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
* CM_SDMA_SDMA_CLKCTRL, CM_TESLA_TESLA_CLKCTRL * CM_TESLA_TESLA_CLKCTRL
*/ */
#define OMAP4430_STBYST_SHIFT 18 #define OMAP4430_STBYST_SHIFT 18
#define OMAP4430_STBYST_MASK (1 << 18) #define OMAP4430_STBYST_MASK (1 << 18)
...@@ -1438,17 +1335,13 @@ ...@@ -1438,17 +1335,13 @@
#define OMAP4430_ST_DPLL_CLKDCOLDO_MASK (1 << 9) #define OMAP4430_ST_DPLL_CLKDCOLDO_MASK (1 << 9)
/* /*
* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
* CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU, * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
* CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
*/ */
#define OMAP4430_ST_DPLL_CLKOUT_SHIFT 9 #define OMAP4430_ST_DPLL_CLKOUT_SHIFT 9
#define OMAP4430_ST_DPLL_CLKOUT_MASK (1 << 9) #define OMAP4430_ST_DPLL_CLKOUT_MASK (1 << 9)
/* /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
* CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
*/
#define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT 9 #define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT 9
#define OMAP4430_ST_DPLL_CLKOUTHIF_MASK (1 << 9) #define OMAP4430_ST_DPLL_CLKOUTHIF_MASK (1 << 9)
...@@ -1457,30 +1350,24 @@ ...@@ -1457,30 +1350,24 @@
#define OMAP4430_ST_DPLL_CLKOUTX2_MASK (1 << 11) #define OMAP4430_ST_DPLL_CLKOUTX2_MASK (1 << 11)
/* /*
* Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE, * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
* CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER * CM_DIV_M4_DPLL_PER
*/ */
#define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT 9 #define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT 9
#define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9) #define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9)
/* /*
* Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE, * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
* CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER * CM_DIV_M5_DPLL_PER
*/ */
#define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT 9 #define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT 9
#define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9) #define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9)
/* /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
* CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
*/
#define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT 9 #define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT 9
#define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9) #define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9)
/* /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
* CM_DIV_M7_DPLL_PER
*/
#define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT 9 #define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT 9
#define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK (1 << 9) #define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK (1 << 9)
...@@ -1496,7 +1383,7 @@ ...@@ -1496,7 +1383,7 @@
#define OMAP4430_SYS_CLKSEL_SHIFT 0 #define OMAP4430_SYS_CLKSEL_SHIFT 0
#define OMAP4430_SYS_CLKSEL_MASK (0x7 << 0) #define OMAP4430_SYS_CLKSEL_MASK (0x7 << 0)
/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */ /* Used by CM_L4CFG_DYNAMICDEP */
#define OMAP4430_TESLA_DYNDEP_SHIFT 1 #define OMAP4430_TESLA_DYNDEP_SHIFT 1
#define OMAP4430_TESLA_DYNDEP_MASK (1 << 1) #define OMAP4430_TESLA_DYNDEP_MASK (1 << 1)
...@@ -1505,11 +1392,9 @@ ...@@ -1505,11 +1392,9 @@
#define OMAP4430_TESLA_STATDEP_MASK (1 << 1) #define OMAP4430_TESLA_STATDEP_MASK (1 << 1)
/* /*
* Used by CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE, CM_DUCATI_DYNAMICDEP, * Used by CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP, CM_EMU_DYNAMICDEP,
* CM_EMU_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE, * CM_L3_1_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
* CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, * CM_L4PER_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
* CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP,
* CM_L4PER_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
*/ */
#define OMAP4430_WINDOWSIZE_SHIFT 24 #define OMAP4430_WINDOWSIZE_SHIFT 24
#define OMAP4430_WINDOWSIZE_MASK (0xf << 24) #define OMAP4430_WINDOWSIZE_MASK (0xf << 24)
......
arch/arm/mach-omap2/cm1_44xx.h
浏览文件 @ c402c0d9
/* /*
* OMAP44xx CM1 instance offset macros * OMAP44xx CM1 instance offset macros
* *
* Copyright (C) 2009-2010 Texas Instruments, Inc. * Copyright (C) 2009-2011 Texas Instruments, Inc.
* Copyright (C) 2009-2010 Nokia Corporation * Copyright (C) 2009-2010 Nokia Corporation
* *
* Paul Walmsley (paul@pwsan.com) * Paul Walmsley (paul@pwsan.com)
...@@ -41,9 +41,9 @@ ...@@ -41,9 +41,9 @@
#define OMAP4430_CM1_INSTR_INST 0x0f00 #define OMAP4430_CM1_INSTR_INST 0x0f00
/* CM1 clockdomain register offsets (from instance start) */ /* CM1 clockdomain register offsets (from instance start) */
#define OMAP4430_CM1_ABE_ABE_CDOFFS 0x0000 #define OMAP4430_CM1_MPU_MPU_CDOFFS 0x0000
#define OMAP4430_CM1_MPU_MPU_CDOFFS 0x0000 #define OMAP4430_CM1_TESLA_TESLA_CDOFFS 0x0000
#define OMAP4430_CM1_TESLA_TESLA_CDOFFS 0x0000 #define OMAP4430_CM1_ABE_ABE_CDOFFS 0x0000
/* CM1 */ /* CM1 */
...@@ -82,8 +82,8 @@ ...@@ -82,8 +82,8 @@
#define OMAP4430_CM_DIV_M7_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0044) #define OMAP4430_CM_DIV_M7_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0044)
#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048 #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0048) #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0048)
#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_CORE_OFFSET 0x004c #define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c
#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x004c) #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x004c)
#define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET 0x0050 #define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET 0x0050
#define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0050) #define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0050)
#define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060 #define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060
...@@ -98,8 +98,8 @@ ...@@ -98,8 +98,8 @@
#define OMAP4430_CM_DIV_M2_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0070) #define OMAP4430_CM_DIV_M2_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0070)
#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088 #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0088) #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0088)
#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_MPU_OFFSET 0x008c #define OMAP4_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c
#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x008c) #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x008c)
#define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c #define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c
#define OMAP4430_CM_BYPCLK_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x009c) #define OMAP4430_CM_BYPCLK_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x009c)
#define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0 #define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0
...@@ -116,8 +116,8 @@ ...@@ -116,8 +116,8 @@
#define OMAP4430_CM_DIV_M5_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00bc) #define OMAP4430_CM_DIV_M5_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00bc)
#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8 #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00c8) #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00c8)
#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_IVA_OFFSET 0x00cc #define OMAP4_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc
#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00cc) #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00cc)
#define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc #define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc
#define OMAP4430_CM_BYPCLK_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00dc) #define OMAP4430_CM_BYPCLK_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00dc)
#define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0 #define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0
...@@ -134,8 +134,8 @@ ...@@ -134,8 +134,8 @@
#define OMAP4430_CM_DIV_M3_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f4) #define OMAP4430_CM_DIV_M3_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f4)
#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108 #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0108) #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0108)
#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_ABE_OFFSET 0x010c #define OMAP4_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c
#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x010c) #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x010c)
#define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET 0x0120 #define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET 0x0120
#define OMAP4430_CM_CLKMODE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0120) #define OMAP4430_CM_CLKMODE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0120)
#define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET 0x0124 #define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET 0x0124
...@@ -154,8 +154,8 @@ ...@@ -154,8 +154,8 @@
#define OMAP4430_CM_DIV_M6_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0140) #define OMAP4430_CM_DIV_M6_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0140)
#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET 0x0148 #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET 0x0148
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0148) #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0148)
#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_DDRPHY_OFFSET 0x014c #define OMAP4_CM_SSC_MODFREQDIV_DPLL_DDRPHY_OFFSET 0x014c
#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x014c) #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x014c)
#define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160 #define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160
#define OMAP4430_CM_SHADOW_FREQ_CONFIG1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0160) #define OMAP4430_CM_SHADOW_FREQ_CONFIG1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0160)
#define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164 #define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164
...@@ -217,42 +217,6 @@ ...@@ -217,42 +217,6 @@
#define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088 #define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088
#define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088) #define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088)
/* CM1.RESTORE_CM1 register offsets */
#define OMAP4_CM_CLKSEL_CORE_RESTORE_OFFSET 0x0000
#define OMAP4430_CM_CLKSEL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0000)
#define OMAP4_CM_DIV_M2_DPLL_CORE_RESTORE_OFFSET 0x0004
#define OMAP4430_CM_DIV_M2_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0004)
#define OMAP4_CM_DIV_M3_DPLL_CORE_RESTORE_OFFSET 0x0008
#define OMAP4430_CM_DIV_M3_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0008)
#define OMAP4_CM_DIV_M4_DPLL_CORE_RESTORE_OFFSET 0x000c
#define OMAP4430_CM_DIV_M4_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x000c)
#define OMAP4_CM_DIV_M5_DPLL_CORE_RESTORE_OFFSET 0x0010
#define OMAP4430_CM_DIV_M5_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0010)
#define OMAP4_CM_DIV_M6_DPLL_CORE_RESTORE_OFFSET 0x0014
#define OMAP4430_CM_DIV_M6_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0014)
#define OMAP4_CM_DIV_M7_DPLL_CORE_RESTORE_OFFSET 0x0018
#define OMAP4430_CM_DIV_M7_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0018)
#define OMAP4_CM_CLKSEL_DPLL_CORE_RESTORE_OFFSET 0x001c
#define OMAP4430_CM_CLKSEL_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x001c)
#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE_OFFSET 0x0020
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0020)
#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_CORE_RESTORE_OFFSET 0x0024
#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0024)
#define OMAP4_CM_CLKMODE_DPLL_CORE_RESTORE_OFFSET 0x0028
#define OMAP4430_CM_CLKMODE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0028)
#define OMAP4_CM_SHADOW_FREQ_CONFIG2_RESTORE_OFFSET 0x002c
#define OMAP4430_CM_SHADOW_FREQ_CONFIG2_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x002c)
#define OMAP4_CM_SHADOW_FREQ_CONFIG1_RESTORE_OFFSET 0x0030
#define OMAP4430_CM_SHADOW_FREQ_CONFIG1_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0030)
#define OMAP4_CM_AUTOIDLE_DPLL_CORE_RESTORE_OFFSET 0x0034
#define OMAP4430_CM_AUTOIDLE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0034)
#define OMAP4_CM_MPU_CLKSTCTRL_RESTORE_OFFSET 0x0038
#define OMAP4430_CM_MPU_CLKSTCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0038)
#define OMAP4_CM_CM1_PROFILING_CLKCTRL_RESTORE_OFFSET 0x003c
#define OMAP4430_CM_CM1_PROFILING_CLKCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x003c)
#define OMAP4_CM_DYN_DEP_PRESCAL_RESTORE_OFFSET 0x0040
#define OMAP4430_CM_DYN_DEP_PRESCAL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0040)
/* Function prototypes */ /* Function prototypes */
extern u32 omap4_cm1_read_inst_reg(s16 inst, u16 idx); extern u32 omap4_cm1_read_inst_reg(s16 inst, u16 idx);
extern void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 idx); extern void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 idx);
......
arch/arm/mach-omap2/cm2_44xx.h
浏览文件 @ c402c0d9
/* /*
* OMAP44xx CM2 instance offset macros * OMAP44xx CM2 instance offset macros
* *
* Copyright (C) 2009-2010 Texas Instruments, Inc. * Copyright (C) 2009-2011 Texas Instruments, Inc.
* Copyright (C) 2009-2010 Nokia Corporation * Copyright (C) 2009-2010 Nokia Corporation
* *
* Paul Walmsley (paul@pwsan.com) * Paul Walmsley (paul@pwsan.com)
...@@ -40,9 +40,9 @@ ...@@ -40,9 +40,9 @@
#define OMAP4430_CM2_CAM_INST 0x1000 #define OMAP4430_CM2_CAM_INST 0x1000
#define OMAP4430_CM2_DSS_INST 0x1100 #define OMAP4430_CM2_DSS_INST 0x1100
#define OMAP4430_CM2_GFX_INST 0x1200 #define OMAP4430_CM2_GFX_INST 0x1200
#define OMAP4430_CM2_L3INIT_INST 0x1300 #define OMAP4430_CM2_L3INIT_INST 0x1300
#define OMAP4430_CM2_L4PER_INST 0x1400 #define OMAP4430_CM2_L4PER_INST 0x1400
#define OMAP4430_CM2_CEFUSE_INST 0x1600 #define OMAP4430_CM2_CEFUSE_INST 0x1600
#define OMAP4430_CM2_RESTORE_INST 0x1e00 #define OMAP4430_CM2_RESTORE_INST 0x1e00
#define OMAP4430_CM2_INSTR_INST 0x1f00 #define OMAP4430_CM2_INSTR_INST 0x1f00
...@@ -65,7 +65,6 @@ ...@@ -65,7 +65,6 @@
#define OMAP4430_CM2_L4PER_L4SEC_CDOFFS 0x0180 #define OMAP4430_CM2_L4PER_L4SEC_CDOFFS 0x0180
#define OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS 0x0000 #define OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS 0x0000
/* CM2 */ /* CM2 */
/* CM2.OCP_SOCKET_CM2 register offsets */ /* CM2.OCP_SOCKET_CM2 register offsets */
...@@ -121,8 +120,8 @@ ...@@ -121,8 +120,8 @@
#define OMAP4430_CM_DIV_M7_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0064) #define OMAP4430_CM_DIV_M7_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0064)
#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0068 #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0068
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0068) #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0068)
#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_PER_OFFSET 0x006c #define OMAP4_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x006c
#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x006c) #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x006c)
#define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET 0x0080 #define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET 0x0080
#define OMAP4430_CM_CLKMODE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0080) #define OMAP4430_CM_CLKMODE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0080)
#define OMAP4_CM_IDLEST_DPLL_USB_OFFSET 0x0084 #define OMAP4_CM_IDLEST_DPLL_USB_OFFSET 0x0084
...@@ -135,8 +134,8 @@ ...@@ -135,8 +134,8 @@
#define OMAP4430_CM_DIV_M2_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0090) #define OMAP4430_CM_DIV_M2_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0090)
#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a8 #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a8
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00a8) #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00a8)
#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_USB_OFFSET 0x00ac #define OMAP4_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET 0x00ac
#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ac) #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ac)
#define OMAP4_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b4 #define OMAP4_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b4
#define OMAP4430_CM_CLKDCOLDO_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00b4) #define OMAP4430_CM_CLKDCOLDO_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00b4)
#define OMAP4_CM_CLKMODE_DPLL_UNIPRO_OFFSET 0x00c0 #define OMAP4_CM_CLKMODE_DPLL_UNIPRO_OFFSET 0x00c0
...@@ -151,8 +150,8 @@ ...@@ -151,8 +150,8 @@
#define OMAP4430_CM_DIV_M2_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00d0) #define OMAP4430_CM_DIV_M2_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00d0)
#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_UNIPRO_OFFSET 0x00e8 #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_UNIPRO_OFFSET 0x00e8
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00e8) #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00e8)
#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_UNIPRO_OFFSET 0x00ec #define OMAP4_CM_SSC_MODFREQDIV_DPLL_UNIPRO_OFFSET 0x00ec
#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ec) #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ec)
/* CM2.ALWAYS_ON_CM2 register offsets */ /* CM2.ALWAYS_ON_CM2 register offsets */
#define OMAP4_CM_ALWON_CLKSTCTRL_OFFSET 0x0000 #define OMAP4_CM_ALWON_CLKSTCTRL_OFFSET 0x0000
...@@ -227,8 +226,8 @@ ...@@ -227,8 +226,8 @@
#define OMAP4430_CM_D2D_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0508) #define OMAP4430_CM_D2D_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0508)
#define OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET 0x0520 #define OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET 0x0520
#define OMAP4430_CM_D2D_SAD2D_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0520) #define OMAP4430_CM_D2D_SAD2D_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0520)
#define OMAP4_CM_D2D_INSTEM_ICR_CLKCTRL_OFFSET 0x0528 #define OMAP4_CM_D2D_MODEM_ICR_CLKCTRL_OFFSET 0x0528
#define OMAP4430_CM_D2D_INSTEM_ICR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0528) #define OMAP4430_CM_D2D_MODEM_ICR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0528)
#define OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET 0x0530 #define OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET 0x0530
#define OMAP4430_CM_D2D_SAD2D_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0530) #define OMAP4430_CM_D2D_SAD2D_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0530)
#define OMAP4_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600 #define OMAP4_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600
...@@ -450,56 +449,6 @@ ...@@ -450,56 +449,6 @@
#define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020 #define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020
#define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0020) #define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0020)
/* CM2.RESTORE_CM2 register offsets */
#define OMAP4_CM_L3_1_CLKSTCTRL_RESTORE_OFFSET 0x0000
#define OMAP4430_CM_L3_1_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0000)
#define OMAP4_CM_L3_2_CLKSTCTRL_RESTORE_OFFSET 0x0004
#define OMAP4430_CM_L3_2_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0004)
#define OMAP4_CM_L4CFG_CLKSTCTRL_RESTORE_OFFSET 0x0008
#define OMAP4430_CM_L4CFG_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0008)
#define OMAP4_CM_MEMIF_CLKSTCTRL_RESTORE_OFFSET 0x000c
#define OMAP4430_CM_MEMIF_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x000c)
#define OMAP4_CM_L4PER_CLKSTCTRL_RESTORE_OFFSET 0x0010
#define OMAP4430_CM_L4PER_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0010)
#define OMAP4_CM_L3INIT_CLKSTCTRL_RESTORE_OFFSET 0x0014
#define OMAP4430_CM_L3INIT_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0014)
#define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_RESTORE_OFFSET 0x0018
#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0018)
#define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE_OFFSET 0x001c
#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x001c)
#define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE_OFFSET 0x0020
#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0020)
#define OMAP4_CM_CM2_PROFILING_CLKCTRL_RESTORE_OFFSET 0x0024
#define OMAP4430_CM_CM2_PROFILING_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0024)
#define OMAP4_CM_D2D_STATICDEP_RESTORE_OFFSET 0x0028
#define OMAP4430_CM_D2D_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0028)
#define OMAP4_CM_L3_1_DYNAMICDEP_RESTORE_OFFSET 0x002c
#define OMAP4430_CM_L3_1_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x002c)
#define OMAP4_CM_L3_2_DYNAMICDEP_RESTORE_OFFSET 0x0030
#define OMAP4430_CM_L3_2_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0030)
#define OMAP4_CM_D2D_DYNAMICDEP_RESTORE_OFFSET 0x0034
#define OMAP4430_CM_D2D_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0034)
#define OMAP4_CM_L4CFG_DYNAMICDEP_RESTORE_OFFSET 0x0038
#define OMAP4430_CM_L4CFG_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0038)
#define OMAP4_CM_L4PER_DYNAMICDEP_RESTORE_OFFSET 0x003c
#define OMAP4430_CM_L4PER_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x003c)
#define OMAP4_CM_L4PER_GPIO2_CLKCTRL_RESTORE_OFFSET 0x0040
#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0040)
#define OMAP4_CM_L4PER_GPIO3_CLKCTRL_RESTORE_OFFSET 0x0044
#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0044)
#define OMAP4_CM_L4PER_GPIO4_CLKCTRL_RESTORE_OFFSET 0x0048
#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0048)
#define OMAP4_CM_L4PER_GPIO5_CLKCTRL_RESTORE_OFFSET 0x004c
#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x004c)
#define OMAP4_CM_L4PER_GPIO6_CLKCTRL_RESTORE_OFFSET 0x0050
#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0050)
#define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE_OFFSET 0x0054
#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0054)
#define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE_OFFSET 0x0058
#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0058)
#define OMAP4_CM_SDMA_STATICDEP_RESTORE_OFFSET 0x005c
#define OMAP4430_CM_SDMA_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x005c)
/* Function prototypes */ /* Function prototypes */
extern u32 omap4_cm2_read_inst_reg(s16 inst, u16 idx); extern u32 omap4_cm2_read_inst_reg(s16 inst, u16 idx);
extern void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 idx); extern void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 idx);
......
arch/arm/mach-omap2/omap_hwmod.c
浏览文件 @ c402c0d9
...@@ -2,6 +2,7 @@ ...@@ -2,6 +2,7 @@
* omap_hwmod implementation for OMAP2/3/4 * omap_hwmod implementation for OMAP2/3/4
* *
* Copyright (C) 2009-2011 Nokia Corporation * Copyright (C) 2009-2011 Nokia Corporation
* Copyright (C) 2011 Texas Instruments, Inc.
* *
* Paul Walmsley, Benoît Cousson, Kevin Hilman * Paul Walmsley, Benoît Cousson, Kevin Hilman
* *
...@@ -387,11 +388,10 @@ static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle, ...@@ -387,11 +388,10 @@ static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle,
*/ */
static int _enable_wakeup(struct omap_hwmod *oh, u32 *v) static int _enable_wakeup(struct omap_hwmod *oh, u32 *v)
{ {
u32 wakeup_mask;
if (!oh->class->sysc || if (!oh->class->sysc ||
!((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) || !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) ||
(oh->class->sysc->idlemodes & SIDLE_SMART_WKUP))) (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) ||
(oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)))
return -EINVAL; return -EINVAL;
if (!oh->class->sysc->sysc_fields) { if (!oh->class->sysc->sysc_fields) {
...@@ -399,12 +399,13 @@ static int _enable_wakeup(struct omap_hwmod *oh, u32 *v) ...@@ -399,12 +399,13 @@ static int _enable_wakeup(struct omap_hwmod *oh, u32 *v)
return -EINVAL; return -EINVAL;
} }
wakeup_mask = (0x1 << oh->class->sysc->sysc_fields->enwkup_shift); if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)
*v |= 0x1 << oh->class->sysc->sysc_fields->enwkup_shift;
*v |= wakeup_mask;
if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)
_set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART_WKUP, v); _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART_WKUP, v);
if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
_set_master_standbymode(oh, HWMOD_IDLEMODE_SMART_WKUP, v);
/* XXX test pwrdm_get_wken for this hwmod's subsystem */ /* XXX test pwrdm_get_wken for this hwmod's subsystem */
...@@ -422,11 +423,10 @@ static int _enable_wakeup(struct omap_hwmod *oh, u32 *v) ...@@ -422,11 +423,10 @@ static int _enable_wakeup(struct omap_hwmod *oh, u32 *v)
*/ */
static int _disable_wakeup(struct omap_hwmod *oh, u32 *v) static int _disable_wakeup(struct omap_hwmod *oh, u32 *v)
{ {
u32 wakeup_mask;
if (!oh->class->sysc || if (!oh->class->sysc ||
!((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) || !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) ||
(oh->class->sysc->idlemodes & SIDLE_SMART_WKUP))) (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) ||
(oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)))
return -EINVAL; return -EINVAL;
if (!oh->class->sysc->sysc_fields) { if (!oh->class->sysc->sysc_fields) {
...@@ -434,12 +434,13 @@ static int _disable_wakeup(struct omap_hwmod *oh, u32 *v) ...@@ -434,12 +434,13 @@ static int _disable_wakeup(struct omap_hwmod *oh, u32 *v)
return -EINVAL; return -EINVAL;
} }
wakeup_mask = (0x1 << oh->class->sysc->sysc_fields->enwkup_shift); if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)
*v &= ~(0x1 << oh->class->sysc->sysc_fields->enwkup_shift);
*v &= ~wakeup_mask;
if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)
_set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART, v); _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART, v);
if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
_set_master_standbymode(oh, HWMOD_IDLEMODE_SMART_WKUP, v);
/* XXX test pwrdm_get_wken for this hwmod's subsystem */ /* XXX test pwrdm_get_wken for this hwmod's subsystem */
...@@ -677,6 +678,75 @@ static void _disable_optional_clocks(struct omap_hwmod *oh) ...@@ -677,6 +678,75 @@ static void _disable_optional_clocks(struct omap_hwmod *oh)
} }
} }
/**
* _count_mpu_irqs - count the number of MPU IRQ lines associated with @oh
* @oh: struct omap_hwmod *oh
*
* Count and return the number of MPU IRQs associated with the hwmod
* @oh. Used to allocate struct resource data. Returns 0 if @oh is
* NULL.
*/
static int _count_mpu_irqs(struct omap_hwmod *oh)
{
struct omap_hwmod_irq_info *ohii;
int i = 0;
if (!oh || !oh->mpu_irqs)
return 0;
do {
ohii = &oh->mpu_irqs[i++];
} while (ohii->irq != -1);
return i;
}
/**
* _count_sdma_reqs - count the number of SDMA request lines associated with @oh
* @oh: struct omap_hwmod *oh
*
* Count and return the number of SDMA request lines associated with
* the hwmod @oh. Used to allocate struct resource data. Returns 0
* if @oh is NULL.
*/
static int _count_sdma_reqs(struct omap_hwmod *oh)
{
struct omap_hwmod_dma_info *ohdi;
int i = 0;
if (!oh || !oh->sdma_reqs)
return 0;
do {
ohdi = &oh->sdma_reqs[i++];
} while (ohdi->dma_req != -1);
return i;
}
/**
* _count_ocp_if_addr_spaces - count the number of address space entries for @oh
* @oh: struct omap_hwmod *oh
*
* Count and return the number of address space ranges associated with
* the hwmod @oh. Used to allocate struct resource data. Returns 0
* if @oh is NULL.
*/
static int _count_ocp_if_addr_spaces(struct omap_hwmod_ocp_if *os)
{
struct omap_hwmod_addr_space *mem;
int i = 0;
if (!os || !os->addr)
return 0;
do {
mem = &os->addr[i++];
} while (mem->pa_start != mem->pa_end);
return i;
}
/** /**
* _find_mpu_port_index - find hwmod OCP slave port ID intended for MPU use * _find_mpu_port_index - find hwmod OCP slave port ID intended for MPU use
* @oh: struct omap_hwmod * * @oh: struct omap_hwmod *
...@@ -722,8 +792,7 @@ static void __iomem * __init _find_mpu_rt_base(struct omap_hwmod *oh, u8 index) ...@@ -722,8 +792,7 @@ static void __iomem * __init _find_mpu_rt_base(struct omap_hwmod *oh, u8 index)
{ {
struct omap_hwmod_ocp_if *os; struct omap_hwmod_ocp_if *os;
struct omap_hwmod_addr_space *mem; struct omap_hwmod_addr_space *mem;
int i; int i = 0, found = 0;
int found = 0;
void __iomem *va_start; void __iomem *va_start;
if (!oh || oh->slaves_cnt == 0) if (!oh || oh->slaves_cnt == 0)
...@@ -731,12 +800,14 @@ static void __iomem * __init _find_mpu_rt_base(struct omap_hwmod *oh, u8 index) ...@@ -731,12 +800,14 @@ static void __iomem * __init _find_mpu_rt_base(struct omap_hwmod *oh, u8 index)
os = oh->slaves[index]; os = oh->slaves[index];
for (i = 0, mem = os->addr; i < os->addr_cnt; i++, mem++) { if (!os->addr)
if (mem->flags & ADDR_TYPE_RT) { return NULL;
do {
mem = &os->addr[i++];
if (mem->flags & ADDR_TYPE_RT)
found = 1; found = 1;
break; } while (!found && mem->pa_start != mem->pa_end);
}
}
if (found) { if (found) {
va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start); va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start);
...@@ -781,8 +852,16 @@ static void _enable_sysc(struct omap_hwmod *oh) ...@@ -781,8 +852,16 @@ static void _enable_sysc(struct omap_hwmod *oh)
} }
if (sf & SYSC_HAS_MIDLEMODE) { if (sf & SYSC_HAS_MIDLEMODE) {
idlemode = (oh->flags & HWMOD_SWSUP_MSTANDBY) ? if (oh->flags & HWMOD_SWSUP_MSTANDBY) {
HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART; idlemode = HWMOD_IDLEMODE_NO;
} else {
if (sf & SYSC_HAS_ENAWAKEUP)
_enable_wakeup(oh, &v);
if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
idlemode = HWMOD_IDLEMODE_SMART_WKUP;
else
idlemode = HWMOD_IDLEMODE_SMART;
}
_set_master_standbymode(oh, idlemode, &v); _set_master_standbymode(oh, idlemode, &v);
} }
...@@ -840,8 +919,16 @@ static void _idle_sysc(struct omap_hwmod *oh) ...@@ -840,8 +919,16 @@ static void _idle_sysc(struct omap_hwmod *oh)
} }
if (sf & SYSC_HAS_MIDLEMODE) { if (sf & SYSC_HAS_MIDLEMODE) {
idlemode = (oh->flags & HWMOD_SWSUP_MSTANDBY) ? if (oh->flags & HWMOD_SWSUP_MSTANDBY) {
HWMOD_IDLEMODE_FORCE : HWMOD_IDLEMODE_SMART; idlemode = HWMOD_IDLEMODE_FORCE;
} else {
if (sf & SYSC_HAS_ENAWAKEUP)
_enable_wakeup(oh, &v);
if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
idlemode = HWMOD_IDLEMODE_SMART_WKUP;
else
idlemode = HWMOD_IDLEMODE_SMART;
}
_set_master_standbymode(oh, idlemode, &v); _set_master_standbymode(oh, idlemode, &v);
} }
...@@ -928,6 +1015,8 @@ static int _init_clocks(struct omap_hwmod *oh, void *data) ...@@ -928,6 +1015,8 @@ static int _init_clocks(struct omap_hwmod *oh, void *data)
if (!ret) if (!ret)
oh->_state = _HWMOD_STATE_CLKS_INITED; oh->_state = _HWMOD_STATE_CLKS_INITED;
else
pr_warning("omap_hwmod: %s: cannot _init_clocks\n", oh->name);
return ret; return ret;
} }
...@@ -1224,6 +1313,8 @@ static int _enable(struct omap_hwmod *oh) ...@@ -1224,6 +1313,8 @@ static int _enable(struct omap_hwmod *oh)
{ {
int r; int r;
pr_debug("omap_hwmod: %s: enabling\n", oh->name);
if (oh->_state != _HWMOD_STATE_INITIALIZED && if (oh->_state != _HWMOD_STATE_INITIALIZED &&
oh->_state != _HWMOD_STATE_IDLE && oh->_state != _HWMOD_STATE_IDLE &&
oh->_state != _HWMOD_STATE_DISABLED) { oh->_state != _HWMOD_STATE_DISABLED) {
...@@ -1232,17 +1323,6 @@ static int _enable(struct omap_hwmod *oh) ...@@ -1232,17 +1323,6 @@ static int _enable(struct omap_hwmod *oh)
return -EINVAL; return -EINVAL;
} }
pr_debug("omap_hwmod: %s: enabling\n", oh->name);
/*
* If an IP contains only one HW reset line, then de-assert it in order
* to allow to enable the clocks. Otherwise the PRCM will return
* Intransition status, and the init will failed.
*/
if ((oh->_state == _HWMOD_STATE_INITIALIZED ||
oh->_state == _HWMOD_STATE_DISABLED) && oh->rst_lines_cnt == 1)
_deassert_hardreset(oh, oh->rst_lines[0].name);
/* Mux pins for device runtime if populated */ /* Mux pins for device runtime if populated */
if (oh->mux && (!oh->mux->enabled || if (oh->mux && (!oh->mux->enabled ||
((oh->_state == _HWMOD_STATE_IDLE) && ((oh->_state == _HWMOD_STATE_IDLE) &&
...@@ -1252,20 +1332,31 @@ static int _enable(struct omap_hwmod *oh) ...@@ -1252,20 +1332,31 @@ static int _enable(struct omap_hwmod *oh)
_add_initiator_dep(oh, mpu_oh); _add_initiator_dep(oh, mpu_oh);
_enable_clocks(oh); _enable_clocks(oh);
r = _wait_target_ready(oh); /*
if (!r) { * If an IP contains only one HW reset line, then de-assert it in order
oh->_state = _HWMOD_STATE_ENABLED; * to allow the module state transition. Otherwise the PRCM will return
* Intransition status, and the init will failed.
*/
if ((oh->_state == _HWMOD_STATE_INITIALIZED ||
oh->_state == _HWMOD_STATE_DISABLED) && oh->rst_lines_cnt == 1)
_deassert_hardreset(oh, oh->rst_lines[0].name);
/* Access the sysconfig only if the target is ready */ r = _wait_target_ready(oh);
if (oh->class->sysc) { if (r) {
if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED))
_update_sysc_cache(oh);
_enable_sysc(oh);
}
} else {
_disable_clocks(oh);
pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n", pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n",
oh->name, r); oh->name, r);
_disable_clocks(oh);
return r;
}
oh->_state = _HWMOD_STATE_ENABLED;
/* Access the sysconfig only if the target is ready */
if (oh->class->sysc) {
if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED))
_update_sysc_cache(oh);
_enable_sysc(oh);
} }
return r; return r;
...@@ -1281,14 +1372,14 @@ static int _enable(struct omap_hwmod *oh) ...@@ -1281,14 +1372,14 @@ static int _enable(struct omap_hwmod *oh)
*/ */
static int _idle(struct omap_hwmod *oh) static int _idle(struct omap_hwmod *oh)
{ {
pr_debug("omap_hwmod: %s: idling\n", oh->name);
if (oh->_state != _HWMOD_STATE_ENABLED) { if (oh->_state != _HWMOD_STATE_ENABLED) {
WARN(1, "omap_hwmod: %s: idle state can only be entered from " WARN(1, "omap_hwmod: %s: idle state can only be entered from "
"enabled state\n", oh->name); "enabled state\n", oh->name);
return -EINVAL; return -EINVAL;
} }
pr_debug("omap_hwmod: %s: idling\n", oh->name);
if (oh->class->sysc) if (oh->class->sysc)
_idle_sysc(oh); _idle_sysc(oh);
_del_initiator_dep(oh, mpu_oh); _del_initiator_dep(oh, mpu_oh);
...@@ -1374,15 +1465,11 @@ static int _shutdown(struct omap_hwmod *oh) ...@@ -1374,15 +1465,11 @@ static int _shutdown(struct omap_hwmod *oh)
} }
} }
if (oh->class->sysc) if (oh->class->sysc) {
if (oh->_state == _HWMOD_STATE_IDLE)
_enable(oh);
_shutdown_sysc(oh); _shutdown_sysc(oh);
}
/*
* If an IP contains only one HW reset line, then assert it
* before disabling the clocks and shutting down the IP.
*/
if (oh->rst_lines_cnt == 1)
_assert_hardreset(oh, oh->rst_lines[0].name);
/* clocks and deps are already disabled in idle */ /* clocks and deps are already disabled in idle */
if (oh->_state == _HWMOD_STATE_ENABLED) { if (oh->_state == _HWMOD_STATE_ENABLED) {
...@@ -1392,6 +1479,13 @@ static int _shutdown(struct omap_hwmod *oh) ...@@ -1392,6 +1479,13 @@ static int _shutdown(struct omap_hwmod *oh)
} }
/* XXX Should this code also force-disable the optional clocks? */ /* XXX Should this code also force-disable the optional clocks? */
/*
* If an IP contains only one HW reset line, then assert it
* after disabling the clocks and before shutting down the IP.
*/
if (oh->rst_lines_cnt == 1)
_assert_hardreset(oh, oh->rst_lines[0].name);
/* Mux pins to safe mode or use populated off mode values */ /* Mux pins to safe mode or use populated off mode values */
if (oh->mux) if (oh->mux)
omap_hwmod_mux(oh->mux, _HWMOD_STATE_DISABLED); omap_hwmod_mux(oh->mux, _HWMOD_STATE_DISABLED);
...@@ -1685,9 +1779,6 @@ static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data) ...@@ -1685,9 +1779,6 @@ static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data)
return 0; return 0;
oh->_mpu_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index); oh->_mpu_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index);
if (!oh->_mpu_rt_va)
pr_warning("omap_hwmod: %s found no _mpu_rt_va for %s\n",
__func__, oh->name);
return 0; return 0;
} }
...@@ -1939,10 +2030,10 @@ int omap_hwmod_count_resources(struct omap_hwmod *oh) ...@@ -1939,10 +2030,10 @@ int omap_hwmod_count_resources(struct omap_hwmod *oh)
{ {
int ret, i; int ret, i;
ret = oh->mpu_irqs_cnt + oh->sdma_reqs_cnt; ret = _count_mpu_irqs(oh) + _count_sdma_reqs(oh);
for (i = 0; i < oh->slaves_cnt; i++) for (i = 0; i < oh->slaves_cnt; i++)
ret += oh->slaves[i]->addr_cnt; ret += _count_ocp_if_addr_spaces(oh->slaves[i]);
return ret; return ret;
} }
...@@ -1959,12 +2050,13 @@ int omap_hwmod_count_resources(struct omap_hwmod *oh) ...@@ -1959,12 +2050,13 @@ int omap_hwmod_count_resources(struct omap_hwmod *oh)
*/ */
int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res) int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
{ {
int i, j; int i, j, mpu_irqs_cnt, sdma_reqs_cnt;
int r = 0; int r = 0;
/* For each IRQ, DMA, memory area, fill in array.*/ /* For each IRQ, DMA, memory area, fill in array.*/
for (i = 0; i < oh->mpu_irqs_cnt; i++) { mpu_irqs_cnt = _count_mpu_irqs(oh);
for (i = 0; i < mpu_irqs_cnt; i++) {
(res + r)->name = (oh->mpu_irqs + i)->name; (res + r)->name = (oh->mpu_irqs + i)->name;
(res + r)->start = (oh->mpu_irqs + i)->irq; (res + r)->start = (oh->mpu_irqs + i)->irq;
(res + r)->end = (oh->mpu_irqs + i)->irq; (res + r)->end = (oh->mpu_irqs + i)->irq;
...@@ -1972,7 +2064,8 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res) ...@@ -1972,7 +2064,8 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
r++; r++;
} }
for (i = 0; i < oh->sdma_reqs_cnt; i++) { sdma_reqs_cnt = _count_sdma_reqs(oh);
for (i = 0; i < sdma_reqs_cnt; i++) {
(res + r)->name = (oh->sdma_reqs + i)->name; (res + r)->name = (oh->sdma_reqs + i)->name;
(res + r)->start = (oh->sdma_reqs + i)->dma_req; (res + r)->start = (oh->sdma_reqs + i)->dma_req;
(res + r)->end = (oh->sdma_reqs + i)->dma_req; (res + r)->end = (oh->sdma_reqs + i)->dma_req;
...@@ -1982,10 +2075,12 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res) ...@@ -1982,10 +2075,12 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
for (i = 0; i < oh->slaves_cnt; i++) { for (i = 0; i < oh->slaves_cnt; i++) {
struct omap_hwmod_ocp_if *os; struct omap_hwmod_ocp_if *os;
int addr_cnt;
os = oh->slaves[i]; os = oh->slaves[i];
addr_cnt = _count_ocp_if_addr_spaces(os);
for (j = 0; j < os->addr_cnt; j++) { for (j = 0; j < addr_cnt; j++) {
(res + r)->name = (os->addr + j)->name; (res + r)->name = (os->addr + j)->name;
(res + r)->start = (os->addr + j)->pa_start; (res + r)->start = (os->addr + j)->pa_start;
(res + r)->end = (os->addr + j)->pa_end; (res + r)->end = (os->addr + j)->pa_end;
......
arch/arm/mach-omap2/omap_hwmod_2420_data.c
浏览文件 @ c402c0d9
/* /*
* omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
* *
* Copyright (C) 2009-2010 Nokia Corporation * Copyright (C) 2009-2011 Nokia Corporation
* Paul Walmsley * Paul Walmsley
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
...@@ -114,38 +114,20 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod; ...@@ -114,38 +114,20 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod;
static struct omap_hwmod omap2420_mcbsp2_hwmod; static struct omap_hwmod omap2420_mcbsp2_hwmod;
/* l4 core -> mcspi1 interface */ /* l4 core -> mcspi1 interface */
static struct omap_hwmod_addr_space omap2420_mcspi1_addr_space[] = {
{
.pa_start = 0x48098000,
.pa_end = 0x480980ff,
.flags = ADDR_TYPE_RT,
},
};
static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = { static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = {
.master = &omap2420_l4_core_hwmod, .master = &omap2420_l4_core_hwmod,
.slave = &omap2420_mcspi1_hwmod, .slave = &omap2420_mcspi1_hwmod,
.clk = "mcspi1_ick", .clk = "mcspi1_ick",
.addr = omap2420_mcspi1_addr_space, .addr = omap2_mcspi1_addr_space,
.addr_cnt = ARRAY_SIZE(omap2420_mcspi1_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* l4 core -> mcspi2 interface */ /* l4 core -> mcspi2 interface */
static struct omap_hwmod_addr_space omap2420_mcspi2_addr_space[] = {
{
.pa_start = 0x4809a000,
.pa_end = 0x4809a0ff,
.flags = ADDR_TYPE_RT,
},
};
static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = { static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = {
.master = &omap2420_l4_core_hwmod, .master = &omap2420_l4_core_hwmod,
.slave = &omap2420_mcspi2_hwmod, .slave = &omap2420_mcspi2_hwmod,
.clk = "mcspi2_ick", .clk = "mcspi2_ick",
.addr = omap2420_mcspi2_addr_space, .addr = omap2_mcspi2_addr_space,
.addr_cnt = ARRAY_SIZE(omap2420_mcspi2_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -157,95 +139,47 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = { ...@@ -157,95 +139,47 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
}; };
/* L4 CORE -> UART1 interface */ /* L4 CORE -> UART1 interface */
static struct omap_hwmod_addr_space omap2420_uart1_addr_space[] = {
{
.pa_start = OMAP2_UART1_BASE,
.pa_end = OMAP2_UART1_BASE + SZ_8K - 1,
.flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
},
};
static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
.master = &omap2420_l4_core_hwmod, .master = &omap2420_l4_core_hwmod,
.slave = &omap2420_uart1_hwmod, .slave = &omap2420_uart1_hwmod,
.clk = "uart1_ick", .clk = "uart1_ick",
.addr = omap2420_uart1_addr_space, .addr = omap2xxx_uart1_addr_space,
.addr_cnt = ARRAY_SIZE(omap2420_uart1_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* L4 CORE -> UART2 interface */ /* L4 CORE -> UART2 interface */
static struct omap_hwmod_addr_space omap2420_uart2_addr_space[] = {
{
.pa_start = OMAP2_UART2_BASE,
.pa_end = OMAP2_UART2_BASE + SZ_1K - 1,
.flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
},
};
static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
.master = &omap2420_l4_core_hwmod, .master = &omap2420_l4_core_hwmod,
.slave = &omap2420_uart2_hwmod, .slave = &omap2420_uart2_hwmod,
.clk = "uart2_ick", .clk = "uart2_ick",
.addr = omap2420_uart2_addr_space, .addr = omap2xxx_uart2_addr_space,
.addr_cnt = ARRAY_SIZE(omap2420_uart2_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* L4 PER -> UART3 interface */ /* L4 PER -> UART3 interface */
static struct omap_hwmod_addr_space omap2420_uart3_addr_space[] = {
{
.pa_start = OMAP2_UART3_BASE,
.pa_end = OMAP2_UART3_BASE + SZ_1K - 1,
.flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
},
};
static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
.master = &omap2420_l4_core_hwmod, .master = &omap2420_l4_core_hwmod,
.slave = &omap2420_uart3_hwmod, .slave = &omap2420_uart3_hwmod,
.clk = "uart3_ick", .clk = "uart3_ick",
.addr = omap2420_uart3_addr_space, .addr = omap2xxx_uart3_addr_space,
.addr_cnt = ARRAY_SIZE(omap2420_uart3_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* I2C IP block address space length (in bytes) */
#define OMAP2_I2C_AS_LEN 128
/* L4 CORE -> I2C1 interface */ /* L4 CORE -> I2C1 interface */
static struct omap_hwmod_addr_space omap2420_i2c1_addr_space[] = {
{
.pa_start = 0x48070000,
.pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
.flags = ADDR_TYPE_RT,
},
};
static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = { static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
.master = &omap2420_l4_core_hwmod, .master = &omap2420_l4_core_hwmod,
.slave = &omap2420_i2c1_hwmod, .slave = &omap2420_i2c1_hwmod,
.clk = "i2c1_ick", .clk = "i2c1_ick",
.addr = omap2420_i2c1_addr_space, .addr = omap2_i2c1_addr_space,
.addr_cnt = ARRAY_SIZE(omap2420_i2c1_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* L4 CORE -> I2C2 interface */ /* L4 CORE -> I2C2 interface */
static struct omap_hwmod_addr_space omap2420_i2c2_addr_space[] = {
{
.pa_start = 0x48072000,
.pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
.flags = ADDR_TYPE_RT,
},
};
static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = { static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
.master = &omap2420_l4_core_hwmod, .master = &omap2420_l4_core_hwmod,
.slave = &omap2420_i2c2_hwmod, .slave = &omap2420_i2c2_hwmod,
.clk = "i2c2_ick", .clk = "i2c2_ick",
.addr = omap2420_i2c2_addr_space, .addr = omap2_i2c2_addr_space,
.addr_cnt = ARRAY_SIZE(omap2420_i2c2_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -340,29 +274,8 @@ static struct omap_hwmod omap2420_iva_hwmod = { ...@@ -340,29 +274,8 @@ static struct omap_hwmod omap2420_iva_hwmod = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
}; };
/* Timer Common */
static struct omap_hwmod_class_sysconfig omap2420_timer_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
SYSC_HAS_AUTOIDLE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap2420_timer_hwmod_class = {
.name = "timer",
.sysc = &omap2420_timer_sysc,
.rev = OMAP_TIMER_IP_VERSION_1,
};
/* timer1 */ /* timer1 */
static struct omap_hwmod omap2420_timer1_hwmod; static struct omap_hwmod omap2420_timer1_hwmod;
static struct omap_hwmod_irq_info omap2420_timer1_mpu_irqs[] = {
{ .irq = 37, },
};
static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = { static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
{ {
...@@ -370,6 +283,7 @@ static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = { ...@@ -370,6 +283,7 @@ static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
.pa_end = 0x48028000 + SZ_1K - 1, .pa_end = 0x48028000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_wkup -> timer1 */ /* l4_wkup -> timer1 */
...@@ -378,7 +292,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = { ...@@ -378,7 +292,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
.slave = &omap2420_timer1_hwmod, .slave = &omap2420_timer1_hwmod,
.clk = "gpt1_ick", .clk = "gpt1_ick",
.addr = omap2420_timer1_addrs, .addr = omap2420_timer1_addrs,
.addr_cnt = ARRAY_SIZE(omap2420_timer1_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -390,8 +303,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer1_slaves[] = { ...@@ -390,8 +303,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer1_slaves[] = {
/* timer1 hwmod */ /* timer1 hwmod */
static struct omap_hwmod omap2420_timer1_hwmod = { static struct omap_hwmod omap2420_timer1_hwmod = {
.name = "timer1", .name = "timer1",
.mpu_irqs = omap2420_timer1_mpu_irqs, .mpu_irqs = omap2_timer1_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer1_mpu_irqs),
.main_clk = "gpt1_fck", .main_clk = "gpt1_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -404,31 +316,19 @@ static struct omap_hwmod omap2420_timer1_hwmod = { ...@@ -404,31 +316,19 @@ static struct omap_hwmod omap2420_timer1_hwmod = {
}, },
.slaves = omap2420_timer1_slaves, .slaves = omap2420_timer1_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_timer1_slaves), .slaves_cnt = ARRAY_SIZE(omap2420_timer1_slaves),
.class = &omap2420_timer_hwmod_class, .class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
}; };
/* timer2 */ /* timer2 */
static struct omap_hwmod omap2420_timer2_hwmod; static struct omap_hwmod omap2420_timer2_hwmod;
static struct omap_hwmod_irq_info omap2420_timer2_mpu_irqs[] = {
{ .irq = 38, },
};
static struct omap_hwmod_addr_space omap2420_timer2_addrs[] = {
{
.pa_start = 0x4802a000,
.pa_end = 0x4802a000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
};
/* l4_core -> timer2 */ /* l4_core -> timer2 */
static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = { static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = {
.master = &omap2420_l4_core_hwmod, .master = &omap2420_l4_core_hwmod,
.slave = &omap2420_timer2_hwmod, .slave = &omap2420_timer2_hwmod,
.clk = "gpt2_ick", .clk = "gpt2_ick",
.addr = omap2420_timer2_addrs, .addr = omap2xxx_timer2_addrs,
.addr_cnt = ARRAY_SIZE(omap2420_timer2_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -440,8 +340,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer2_slaves[] = { ...@@ -440,8 +340,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer2_slaves[] = {
/* timer2 hwmod */ /* timer2 hwmod */
static struct omap_hwmod omap2420_timer2_hwmod = { static struct omap_hwmod omap2420_timer2_hwmod = {
.name = "timer2", .name = "timer2",
.mpu_irqs = omap2420_timer2_mpu_irqs, .mpu_irqs = omap2_timer2_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer2_mpu_irqs),
.main_clk = "gpt2_fck", .main_clk = "gpt2_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -454,31 +353,19 @@ static struct omap_hwmod omap2420_timer2_hwmod = { ...@@ -454,31 +353,19 @@ static struct omap_hwmod omap2420_timer2_hwmod = {
}, },
.slaves = omap2420_timer2_slaves, .slaves = omap2420_timer2_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_timer2_slaves), .slaves_cnt = ARRAY_SIZE(omap2420_timer2_slaves),
.class = &omap2420_timer_hwmod_class, .class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
}; };
/* timer3 */ /* timer3 */
static struct omap_hwmod omap2420_timer3_hwmod; static struct omap_hwmod omap2420_timer3_hwmod;
static struct omap_hwmod_irq_info omap2420_timer3_mpu_irqs[] = {
{ .irq = 39, },
};
static struct omap_hwmod_addr_space omap2420_timer3_addrs[] = {
{
.pa_start = 0x48078000,
.pa_end = 0x48078000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
};
/* l4_core -> timer3 */ /* l4_core -> timer3 */
static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = { static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = {
.master = &omap2420_l4_core_hwmod, .master = &omap2420_l4_core_hwmod,
.slave = &omap2420_timer3_hwmod, .slave = &omap2420_timer3_hwmod,
.clk = "gpt3_ick", .clk = "gpt3_ick",
.addr = omap2420_timer3_addrs, .addr = omap2xxx_timer3_addrs,
.addr_cnt = ARRAY_SIZE(omap2420_timer3_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -490,8 +377,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer3_slaves[] = { ...@@ -490,8 +377,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer3_slaves[] = {
/* timer3 hwmod */ /* timer3 hwmod */
static struct omap_hwmod omap2420_timer3_hwmod = { static struct omap_hwmod omap2420_timer3_hwmod = {
.name = "timer3", .name = "timer3",
.mpu_irqs = omap2420_timer3_mpu_irqs, .mpu_irqs = omap2_timer3_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer3_mpu_irqs),
.main_clk = "gpt3_fck", .main_clk = "gpt3_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -504,31 +390,19 @@ static struct omap_hwmod omap2420_timer3_hwmod = { ...@@ -504,31 +390,19 @@ static struct omap_hwmod omap2420_timer3_hwmod = {
}, },
.slaves = omap2420_timer3_slaves, .slaves = omap2420_timer3_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_timer3_slaves), .slaves_cnt = ARRAY_SIZE(omap2420_timer3_slaves),
.class = &omap2420_timer_hwmod_class, .class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
}; };
/* timer4 */ /* timer4 */
static struct omap_hwmod omap2420_timer4_hwmod; static struct omap_hwmod omap2420_timer4_hwmod;
static struct omap_hwmod_irq_info omap2420_timer4_mpu_irqs[] = {
{ .irq = 40, },
};
static struct omap_hwmod_addr_space omap2420_timer4_addrs[] = {
{
.pa_start = 0x4807a000,
.pa_end = 0x4807a000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
};
/* l4_core -> timer4 */ /* l4_core -> timer4 */
static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = { static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = {
.master = &omap2420_l4_core_hwmod, .master = &omap2420_l4_core_hwmod,
.slave = &omap2420_timer4_hwmod, .slave = &omap2420_timer4_hwmod,
.clk = "gpt4_ick", .clk = "gpt4_ick",
.addr = omap2420_timer4_addrs, .addr = omap2xxx_timer4_addrs,
.addr_cnt = ARRAY_SIZE(omap2420_timer4_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -540,8 +414,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer4_slaves[] = { ...@@ -540,8 +414,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer4_slaves[] = {
/* timer4 hwmod */ /* timer4 hwmod */
static struct omap_hwmod omap2420_timer4_hwmod = { static struct omap_hwmod omap2420_timer4_hwmod = {
.name = "timer4", .name = "timer4",
.mpu_irqs = omap2420_timer4_mpu_irqs, .mpu_irqs = omap2_timer4_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer4_mpu_irqs),
.main_clk = "gpt4_fck", .main_clk = "gpt4_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -554,31 +427,19 @@ static struct omap_hwmod omap2420_timer4_hwmod = { ...@@ -554,31 +427,19 @@ static struct omap_hwmod omap2420_timer4_hwmod = {
}, },
.slaves = omap2420_timer4_slaves, .slaves = omap2420_timer4_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_timer4_slaves), .slaves_cnt = ARRAY_SIZE(omap2420_timer4_slaves),
.class = &omap2420_timer_hwmod_class, .class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
}; };
/* timer5 */ /* timer5 */
static struct omap_hwmod omap2420_timer5_hwmod; static struct omap_hwmod omap2420_timer5_hwmod;
static struct omap_hwmod_irq_info omap2420_timer5_mpu_irqs[] = {
{ .irq = 41, },
};
static struct omap_hwmod_addr_space omap2420_timer5_addrs[] = {
{
.pa_start = 0x4807c000,
.pa_end = 0x4807c000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
};
/* l4_core -> timer5 */ /* l4_core -> timer5 */
static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = { static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = {
.master = &omap2420_l4_core_hwmod, .master = &omap2420_l4_core_hwmod,
.slave = &omap2420_timer5_hwmod, .slave = &omap2420_timer5_hwmod,
.clk = "gpt5_ick", .clk = "gpt5_ick",
.addr = omap2420_timer5_addrs, .addr = omap2xxx_timer5_addrs,
.addr_cnt = ARRAY_SIZE(omap2420_timer5_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -590,8 +451,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer5_slaves[] = { ...@@ -590,8 +451,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer5_slaves[] = {
/* timer5 hwmod */ /* timer5 hwmod */
static struct omap_hwmod omap2420_timer5_hwmod = { static struct omap_hwmod omap2420_timer5_hwmod = {
.name = "timer5", .name = "timer5",
.mpu_irqs = omap2420_timer5_mpu_irqs, .mpu_irqs = omap2_timer5_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer5_mpu_irqs),
.main_clk = "gpt5_fck", .main_clk = "gpt5_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -604,32 +464,20 @@ static struct omap_hwmod omap2420_timer5_hwmod = { ...@@ -604,32 +464,20 @@ static struct omap_hwmod omap2420_timer5_hwmod = {
}, },
.slaves = omap2420_timer5_slaves, .slaves = omap2420_timer5_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_timer5_slaves), .slaves_cnt = ARRAY_SIZE(omap2420_timer5_slaves),
.class = &omap2420_timer_hwmod_class, .class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
}; };
/* timer6 */ /* timer6 */
static struct omap_hwmod omap2420_timer6_hwmod; static struct omap_hwmod omap2420_timer6_hwmod;
static struct omap_hwmod_irq_info omap2420_timer6_mpu_irqs[] = {
{ .irq = 42, },
};
static struct omap_hwmod_addr_space omap2420_timer6_addrs[] = {
{
.pa_start = 0x4807e000,
.pa_end = 0x4807e000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
};
/* l4_core -> timer6 */ /* l4_core -> timer6 */
static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = { static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = {
.master = &omap2420_l4_core_hwmod, .master = &omap2420_l4_core_hwmod,
.slave = &omap2420_timer6_hwmod, .slave = &omap2420_timer6_hwmod,
.clk = "gpt6_ick", .clk = "gpt6_ick",
.addr = omap2420_timer6_addrs, .addr = omap2xxx_timer6_addrs,
.addr_cnt = ARRAY_SIZE(omap2420_timer6_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -641,8 +489,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer6_slaves[] = { ...@@ -641,8 +489,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer6_slaves[] = {
/* timer6 hwmod */ /* timer6 hwmod */
static struct omap_hwmod omap2420_timer6_hwmod = { static struct omap_hwmod omap2420_timer6_hwmod = {
.name = "timer6", .name = "timer6",
.mpu_irqs = omap2420_timer6_mpu_irqs, .mpu_irqs = omap2_timer6_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer6_mpu_irqs),
.main_clk = "gpt6_fck", .main_clk = "gpt6_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -655,31 +502,19 @@ static struct omap_hwmod omap2420_timer6_hwmod = { ...@@ -655,31 +502,19 @@ static struct omap_hwmod omap2420_timer6_hwmod = {
}, },
.slaves = omap2420_timer6_slaves, .slaves = omap2420_timer6_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_timer6_slaves), .slaves_cnt = ARRAY_SIZE(omap2420_timer6_slaves),
.class = &omap2420_timer_hwmod_class, .class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
}; };
/* timer7 */ /* timer7 */
static struct omap_hwmod omap2420_timer7_hwmod; static struct omap_hwmod omap2420_timer7_hwmod;
static struct omap_hwmod_irq_info omap2420_timer7_mpu_irqs[] = {
{ .irq = 43, },
};
static struct omap_hwmod_addr_space omap2420_timer7_addrs[] = {
{
.pa_start = 0x48080000,
.pa_end = 0x48080000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
};
/* l4_core -> timer7 */ /* l4_core -> timer7 */
static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = { static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = {
.master = &omap2420_l4_core_hwmod, .master = &omap2420_l4_core_hwmod,
.slave = &omap2420_timer7_hwmod, .slave = &omap2420_timer7_hwmod,
.clk = "gpt7_ick", .clk = "gpt7_ick",
.addr = omap2420_timer7_addrs, .addr = omap2xxx_timer7_addrs,
.addr_cnt = ARRAY_SIZE(omap2420_timer7_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -691,8 +526,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer7_slaves[] = { ...@@ -691,8 +526,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer7_slaves[] = {
/* timer7 hwmod */ /* timer7 hwmod */
static struct omap_hwmod omap2420_timer7_hwmod = { static struct omap_hwmod omap2420_timer7_hwmod = {
.name = "timer7", .name = "timer7",
.mpu_irqs = omap2420_timer7_mpu_irqs, .mpu_irqs = omap2_timer7_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer7_mpu_irqs),
.main_clk = "gpt7_fck", .main_clk = "gpt7_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -705,31 +539,19 @@ static struct omap_hwmod omap2420_timer7_hwmod = { ...@@ -705,31 +539,19 @@ static struct omap_hwmod omap2420_timer7_hwmod = {
}, },
.slaves = omap2420_timer7_slaves, .slaves = omap2420_timer7_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_timer7_slaves), .slaves_cnt = ARRAY_SIZE(omap2420_timer7_slaves),
.class = &omap2420_timer_hwmod_class, .class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
}; };
/* timer8 */ /* timer8 */
static struct omap_hwmod omap2420_timer8_hwmod; static struct omap_hwmod omap2420_timer8_hwmod;
static struct omap_hwmod_irq_info omap2420_timer8_mpu_irqs[] = {
{ .irq = 44, },
};
static struct omap_hwmod_addr_space omap2420_timer8_addrs[] = {
{
.pa_start = 0x48082000,
.pa_end = 0x48082000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
};
/* l4_core -> timer8 */ /* l4_core -> timer8 */
static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = { static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = {
.master = &omap2420_l4_core_hwmod, .master = &omap2420_l4_core_hwmod,
.slave = &omap2420_timer8_hwmod, .slave = &omap2420_timer8_hwmod,
.clk = "gpt8_ick", .clk = "gpt8_ick",
.addr = omap2420_timer8_addrs, .addr = omap2xxx_timer8_addrs,
.addr_cnt = ARRAY_SIZE(omap2420_timer8_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -741,8 +563,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer8_slaves[] = { ...@@ -741,8 +563,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer8_slaves[] = {
/* timer8 hwmod */ /* timer8 hwmod */
static struct omap_hwmod omap2420_timer8_hwmod = { static struct omap_hwmod omap2420_timer8_hwmod = {
.name = "timer8", .name = "timer8",
.mpu_irqs = omap2420_timer8_mpu_irqs, .mpu_irqs = omap2_timer8_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer8_mpu_irqs),
.main_clk = "gpt8_fck", .main_clk = "gpt8_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -755,31 +576,19 @@ static struct omap_hwmod omap2420_timer8_hwmod = { ...@@ -755,31 +576,19 @@ static struct omap_hwmod omap2420_timer8_hwmod = {
}, },
.slaves = omap2420_timer8_slaves, .slaves = omap2420_timer8_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_timer8_slaves), .slaves_cnt = ARRAY_SIZE(omap2420_timer8_slaves),
.class = &omap2420_timer_hwmod_class, .class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
}; };
/* timer9 */ /* timer9 */
static struct omap_hwmod omap2420_timer9_hwmod; static struct omap_hwmod omap2420_timer9_hwmod;
static struct omap_hwmod_irq_info omap2420_timer9_mpu_irqs[] = {
{ .irq = 45, },
};
static struct omap_hwmod_addr_space omap2420_timer9_addrs[] = {
{
.pa_start = 0x48084000,
.pa_end = 0x48084000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
};
/* l4_core -> timer9 */ /* l4_core -> timer9 */
static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = { static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = {
.master = &omap2420_l4_core_hwmod, .master = &omap2420_l4_core_hwmod,
.slave = &omap2420_timer9_hwmod, .slave = &omap2420_timer9_hwmod,
.clk = "gpt9_ick", .clk = "gpt9_ick",
.addr = omap2420_timer9_addrs, .addr = omap2xxx_timer9_addrs,
.addr_cnt = ARRAY_SIZE(omap2420_timer9_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -791,8 +600,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer9_slaves[] = { ...@@ -791,8 +600,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer9_slaves[] = {
/* timer9 hwmod */ /* timer9 hwmod */
static struct omap_hwmod omap2420_timer9_hwmod = { static struct omap_hwmod omap2420_timer9_hwmod = {
.name = "timer9", .name = "timer9",
.mpu_irqs = omap2420_timer9_mpu_irqs, .mpu_irqs = omap2_timer9_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer9_mpu_irqs),
.main_clk = "gpt9_fck", .main_clk = "gpt9_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -805,31 +613,19 @@ static struct omap_hwmod omap2420_timer9_hwmod = { ...@@ -805,31 +613,19 @@ static struct omap_hwmod omap2420_timer9_hwmod = {
}, },
.slaves = omap2420_timer9_slaves, .slaves = omap2420_timer9_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_timer9_slaves), .slaves_cnt = ARRAY_SIZE(omap2420_timer9_slaves),
.class = &omap2420_timer_hwmod_class, .class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
}; };
/* timer10 */ /* timer10 */
static struct omap_hwmod omap2420_timer10_hwmod; static struct omap_hwmod omap2420_timer10_hwmod;
static struct omap_hwmod_irq_info omap2420_timer10_mpu_irqs[] = {
{ .irq = 46, },
};
static struct omap_hwmod_addr_space omap2420_timer10_addrs[] = {
{
.pa_start = 0x48086000,
.pa_end = 0x48086000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
};
/* l4_core -> timer10 */ /* l4_core -> timer10 */
static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = { static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = {
.master = &omap2420_l4_core_hwmod, .master = &omap2420_l4_core_hwmod,
.slave = &omap2420_timer10_hwmod, .slave = &omap2420_timer10_hwmod,
.clk = "gpt10_ick", .clk = "gpt10_ick",
.addr = omap2420_timer10_addrs, .addr = omap2_timer10_addrs,
.addr_cnt = ARRAY_SIZE(omap2420_timer10_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -841,8 +637,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer10_slaves[] = { ...@@ -841,8 +637,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer10_slaves[] = {
/* timer10 hwmod */ /* timer10 hwmod */
static struct omap_hwmod omap2420_timer10_hwmod = { static struct omap_hwmod omap2420_timer10_hwmod = {
.name = "timer10", .name = "timer10",
.mpu_irqs = omap2420_timer10_mpu_irqs, .mpu_irqs = omap2_timer10_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer10_mpu_irqs),
.main_clk = "gpt10_fck", .main_clk = "gpt10_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -855,31 +650,19 @@ static struct omap_hwmod omap2420_timer10_hwmod = { ...@@ -855,31 +650,19 @@ static struct omap_hwmod omap2420_timer10_hwmod = {
}, },
.slaves = omap2420_timer10_slaves, .slaves = omap2420_timer10_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_timer10_slaves), .slaves_cnt = ARRAY_SIZE(omap2420_timer10_slaves),
.class = &omap2420_timer_hwmod_class, .class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
}; };
/* timer11 */ /* timer11 */
static struct omap_hwmod omap2420_timer11_hwmod; static struct omap_hwmod omap2420_timer11_hwmod;
static struct omap_hwmod_irq_info omap2420_timer11_mpu_irqs[] = {
{ .irq = 47, },
};
static struct omap_hwmod_addr_space omap2420_timer11_addrs[] = {
{
.pa_start = 0x48088000,
.pa_end = 0x48088000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
};
/* l4_core -> timer11 */ /* l4_core -> timer11 */
static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = { static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = {
.master = &omap2420_l4_core_hwmod, .master = &omap2420_l4_core_hwmod,
.slave = &omap2420_timer11_hwmod, .slave = &omap2420_timer11_hwmod,
.clk = "gpt11_ick", .clk = "gpt11_ick",
.addr = omap2420_timer11_addrs, .addr = omap2_timer11_addrs,
.addr_cnt = ARRAY_SIZE(omap2420_timer11_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -891,8 +674,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer11_slaves[] = { ...@@ -891,8 +674,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer11_slaves[] = {
/* timer11 hwmod */ /* timer11 hwmod */
static struct omap_hwmod omap2420_timer11_hwmod = { static struct omap_hwmod omap2420_timer11_hwmod = {
.name = "timer11", .name = "timer11",
.mpu_irqs = omap2420_timer11_mpu_irqs, .mpu_irqs = omap2_timer11_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer11_mpu_irqs),
.main_clk = "gpt11_fck", .main_clk = "gpt11_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -905,31 +687,19 @@ static struct omap_hwmod omap2420_timer11_hwmod = { ...@@ -905,31 +687,19 @@ static struct omap_hwmod omap2420_timer11_hwmod = {
}, },
.slaves = omap2420_timer11_slaves, .slaves = omap2420_timer11_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_timer11_slaves), .slaves_cnt = ARRAY_SIZE(omap2420_timer11_slaves),
.class = &omap2420_timer_hwmod_class, .class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
}; };
/* timer12 */ /* timer12 */
static struct omap_hwmod omap2420_timer12_hwmod; static struct omap_hwmod omap2420_timer12_hwmod;
static struct omap_hwmod_irq_info omap2420_timer12_mpu_irqs[] = {
{ .irq = 48, },
};
static struct omap_hwmod_addr_space omap2420_timer12_addrs[] = {
{
.pa_start = 0x4808a000,
.pa_end = 0x4808a000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
};
/* l4_core -> timer12 */ /* l4_core -> timer12 */
static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = { static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = {
.master = &omap2420_l4_core_hwmod, .master = &omap2420_l4_core_hwmod,
.slave = &omap2420_timer12_hwmod, .slave = &omap2420_timer12_hwmod,
.clk = "gpt12_ick", .clk = "gpt12_ick",
.addr = omap2420_timer12_addrs, .addr = omap2xxx_timer12_addrs,
.addr_cnt = ARRAY_SIZE(omap2420_timer12_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -941,8 +711,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer12_slaves[] = { ...@@ -941,8 +711,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer12_slaves[] = {
/* timer12 hwmod */ /* timer12 hwmod */
static struct omap_hwmod omap2420_timer12_hwmod = { static struct omap_hwmod omap2420_timer12_hwmod = {
.name = "timer12", .name = "timer12",
.mpu_irqs = omap2420_timer12_mpu_irqs, .mpu_irqs = omap2xxx_timer12_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer12_mpu_irqs),
.main_clk = "gpt12_fck", .main_clk = "gpt12_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -955,7 +724,7 @@ static struct omap_hwmod omap2420_timer12_hwmod = { ...@@ -955,7 +724,7 @@ static struct omap_hwmod omap2420_timer12_hwmod = {
}, },
.slaves = omap2420_timer12_slaves, .slaves = omap2420_timer12_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_timer12_slaves), .slaves_cnt = ARRAY_SIZE(omap2420_timer12_slaves),
.class = &omap2420_timer_hwmod_class, .class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
}; };
...@@ -966,6 +735,7 @@ static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = { ...@@ -966,6 +735,7 @@ static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
.pa_end = 0x4802207f, .pa_end = 0x4802207f,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = { static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
...@@ -973,31 +743,9 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = { ...@@ -973,31 +743,9 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
.slave = &omap2420_wd_timer2_hwmod, .slave = &omap2420_wd_timer2_hwmod,
.clk = "mpu_wdt_ick", .clk = "mpu_wdt_ick",
.addr = omap2420_wd_timer2_addrs, .addr = omap2420_wd_timer2_addrs,
.addr_cnt = ARRAY_SIZE(omap2420_wd_timer2_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/*
* 'wd_timer' class
* 32-bit watchdog upward counter that generates a pulse on the reset pin on
* overflow condition
*/
static struct omap_hwmod_class_sysconfig omap2420_wd_timer_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap2420_wd_timer_hwmod_class = {
.name = "wd_timer",
.sysc = &omap2420_wd_timer_sysc,
.pre_shutdown = &omap2_wd_timer_disable
};
/* wd_timer2 */ /* wd_timer2 */
static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = { static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = {
&omap2420_l4_wkup__wd_timer2, &omap2420_l4_wkup__wd_timer2,
...@@ -1005,7 +753,7 @@ static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = { ...@@ -1005,7 +753,7 @@ static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = {
static struct omap_hwmod omap2420_wd_timer2_hwmod = { static struct omap_hwmod omap2420_wd_timer2_hwmod = {
.name = "wd_timer2", .name = "wd_timer2",
.class = &omap2420_wd_timer_hwmod_class, .class = &omap2xxx_wd_timer_hwmod_class,
.main_clk = "mpu_wdt_fck", .main_clk = "mpu_wdt_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1021,45 +769,16 @@ static struct omap_hwmod omap2420_wd_timer2_hwmod = { ...@@ -1021,45 +769,16 @@ static struct omap_hwmod omap2420_wd_timer2_hwmod = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
}; };
/* UART */
static struct omap_hwmod_class_sysconfig uart_sysc = {
.rev_offs = 0x50,
.sysc_offs = 0x54,
.syss_offs = 0x58,
.sysc_flags = (SYSC_HAS_SIDLEMODE |
SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class uart_class = {
.name = "uart",
.sysc = &uart_sysc,
};
/* UART1 */ /* UART1 */
static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
{ .irq = INT_24XX_UART1_IRQ, },
};
static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
{ .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
{ .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
};
static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = { static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = {
&omap2_l4_core__uart1, &omap2_l4_core__uart1,
}; };
static struct omap_hwmod omap2420_uart1_hwmod = { static struct omap_hwmod omap2420_uart1_hwmod = {
.name = "uart1", .name = "uart1",
.mpu_irqs = uart1_mpu_irqs, .mpu_irqs = omap2_uart1_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs), .sdma_reqs = omap2_uart1_sdma_reqs,
.sdma_reqs = uart1_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs),
.main_clk = "uart1_fck", .main_clk = "uart1_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1072,31 +791,20 @@ static struct omap_hwmod omap2420_uart1_hwmod = { ...@@ -1072,31 +791,20 @@ static struct omap_hwmod omap2420_uart1_hwmod = {
}, },
.slaves = omap2420_uart1_slaves, .slaves = omap2420_uart1_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_uart1_slaves), .slaves_cnt = ARRAY_SIZE(omap2420_uart1_slaves),
.class = &uart_class, .class = &omap2_uart_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
}; };
/* UART2 */ /* UART2 */
static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
{ .irq = INT_24XX_UART2_IRQ, },
};
static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
{ .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
{ .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
};
static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = { static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = {
&omap2_l4_core__uart2, &omap2_l4_core__uart2,
}; };
static struct omap_hwmod omap2420_uart2_hwmod = { static struct omap_hwmod omap2420_uart2_hwmod = {
.name = "uart2", .name = "uart2",
.mpu_irqs = uart2_mpu_irqs, .mpu_irqs = omap2_uart2_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs), .sdma_reqs = omap2_uart2_sdma_reqs,
.sdma_reqs = uart2_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs),
.main_clk = "uart2_fck", .main_clk = "uart2_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1109,31 +817,20 @@ static struct omap_hwmod omap2420_uart2_hwmod = { ...@@ -1109,31 +817,20 @@ static struct omap_hwmod omap2420_uart2_hwmod = {
}, },
.slaves = omap2420_uart2_slaves, .slaves = omap2420_uart2_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_uart2_slaves), .slaves_cnt = ARRAY_SIZE(omap2420_uart2_slaves),
.class = &uart_class, .class = &omap2_uart_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
}; };
/* UART3 */ /* UART3 */
static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
{ .irq = INT_24XX_UART3_IRQ, },
};
static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
{ .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
{ .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
};
static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = { static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = {
&omap2_l4_core__uart3, &omap2_l4_core__uart3,
}; };
static struct omap_hwmod omap2420_uart3_hwmod = { static struct omap_hwmod omap2420_uart3_hwmod = {
.name = "uart3", .name = "uart3",
.mpu_irqs = uart3_mpu_irqs, .mpu_irqs = omap2_uart3_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs), .sdma_reqs = omap2_uart3_sdma_reqs,
.sdma_reqs = uart3_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs),
.main_clk = "uart3_fck", .main_clk = "uart3_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1146,53 +843,22 @@ static struct omap_hwmod omap2420_uart3_hwmod = { ...@@ -1146,53 +843,22 @@ static struct omap_hwmod omap2420_uart3_hwmod = {
}, },
.slaves = omap2420_uart3_slaves, .slaves = omap2420_uart3_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_uart3_slaves), .slaves_cnt = ARRAY_SIZE(omap2420_uart3_slaves),
.class = &uart_class, .class = &omap2_uart_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
}; };
/*
* 'dss' class
* display sub-system
*/
static struct omap_hwmod_class_sysconfig omap2420_dss_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap2420_dss_hwmod_class = {
.name = "dss",
.sysc = &omap2420_dss_sysc,
};
static struct omap_hwmod_dma_info omap2420_dss_sdma_chs[] = {
{ .name = "dispc", .dma_req = 5 },
};
/* dss */ /* dss */
/* dss master ports */ /* dss master ports */
static struct omap_hwmod_ocp_if *omap2420_dss_masters[] = { static struct omap_hwmod_ocp_if *omap2420_dss_masters[] = {
&omap2420_dss__l3, &omap2420_dss__l3,
}; };
static struct omap_hwmod_addr_space omap2420_dss_addrs[] = {
{
.pa_start = 0x48050000,
.pa_end = 0x480503FF,
.flags = ADDR_TYPE_RT
},
};
/* l4_core -> dss */ /* l4_core -> dss */
static struct omap_hwmod_ocp_if omap2420_l4_core__dss = { static struct omap_hwmod_ocp_if omap2420_l4_core__dss = {
.master = &omap2420_l4_core_hwmod, .master = &omap2420_l4_core_hwmod,
.slave = &omap2420_dss_core_hwmod, .slave = &omap2420_dss_core_hwmod,
.clk = "dss_ick", .clk = "dss_ick",
.addr = omap2420_dss_addrs, .addr = omap2_dss_addrs,
.addr_cnt = ARRAY_SIZE(omap2420_dss_addrs),
.fw = { .fw = {
.omap2 = { .omap2 = {
.l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
...@@ -1214,10 +880,9 @@ static struct omap_hwmod_opt_clk dss_opt_clks[] = { ...@@ -1214,10 +880,9 @@ static struct omap_hwmod_opt_clk dss_opt_clks[] = {
static struct omap_hwmod omap2420_dss_core_hwmod = { static struct omap_hwmod omap2420_dss_core_hwmod = {
.name = "dss_core", .name = "dss_core",
.class = &omap2420_dss_hwmod_class, .class = &omap2_dss_hwmod_class,
.main_clk = "dss1_fck", /* instead of dss_fck */ .main_clk = "dss1_fck", /* instead of dss_fck */
.sdma_reqs = omap2420_dss_sdma_chs, .sdma_reqs = omap2xxx_dss_sdma_chs,
.sdma_reqs_cnt = ARRAY_SIZE(omap2420_dss_sdma_chs),
.prcm = { .prcm = {
.omap2 = { .omap2 = {
.prcm_reg_id = 1, .prcm_reg_id = 1,
...@@ -1237,46 +902,12 @@ static struct omap_hwmod omap2420_dss_core_hwmod = { ...@@ -1237,46 +902,12 @@ static struct omap_hwmod omap2420_dss_core_hwmod = {
.flags = HWMOD_NO_IDLEST, .flags = HWMOD_NO_IDLEST,
}; };
/*
* 'dispc' class
* display controller
*/
static struct omap_hwmod_class_sysconfig omap2420_dispc_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap2420_dispc_hwmod_class = {
.name = "dispc",
.sysc = &omap2420_dispc_sysc,
};
static struct omap_hwmod_irq_info omap2420_dispc_irqs[] = {
{ .irq = 25 },
};
static struct omap_hwmod_addr_space omap2420_dss_dispc_addrs[] = {
{
.pa_start = 0x48050400,
.pa_end = 0x480507FF,
.flags = ADDR_TYPE_RT
},
};
/* l4_core -> dss_dispc */ /* l4_core -> dss_dispc */
static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = { static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = {
.master = &omap2420_l4_core_hwmod, .master = &omap2420_l4_core_hwmod,
.slave = &omap2420_dss_dispc_hwmod, .slave = &omap2420_dss_dispc_hwmod,
.clk = "dss_ick", .clk = "dss_ick",
.addr = omap2420_dss_dispc_addrs, .addr = omap2_dss_dispc_addrs,
.addr_cnt = ARRAY_SIZE(omap2420_dss_dispc_addrs),
.fw = { .fw = {
.omap2 = { .omap2 = {
.l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION, .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
...@@ -1293,9 +924,8 @@ static struct omap_hwmod_ocp_if *omap2420_dss_dispc_slaves[] = { ...@@ -1293,9 +924,8 @@ static struct omap_hwmod_ocp_if *omap2420_dss_dispc_slaves[] = {
static struct omap_hwmod omap2420_dss_dispc_hwmod = { static struct omap_hwmod omap2420_dss_dispc_hwmod = {
.name = "dss_dispc", .name = "dss_dispc",
.class = &omap2420_dispc_hwmod_class, .class = &omap2_dispc_hwmod_class,
.mpu_irqs = omap2420_dispc_irqs, .mpu_irqs = omap2_dispc_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2420_dispc_irqs),
.main_clk = "dss1_fck", .main_clk = "dss1_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1312,41 +942,12 @@ static struct omap_hwmod omap2420_dss_dispc_hwmod = { ...@@ -1312,41 +942,12 @@ static struct omap_hwmod omap2420_dss_dispc_hwmod = {
.flags = HWMOD_NO_IDLEST, .flags = HWMOD_NO_IDLEST,
}; };
/*
* 'rfbi' class
* remote frame buffer interface
*/
static struct omap_hwmod_class_sysconfig omap2420_rfbi_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
SYSC_HAS_AUTOIDLE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap2420_rfbi_hwmod_class = {
.name = "rfbi",
.sysc = &omap2420_rfbi_sysc,
};
static struct omap_hwmod_addr_space omap2420_dss_rfbi_addrs[] = {
{
.pa_start = 0x48050800,
.pa_end = 0x48050BFF,
.flags = ADDR_TYPE_RT
},
};
/* l4_core -> dss_rfbi */ /* l4_core -> dss_rfbi */
static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = { static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = {
.master = &omap2420_l4_core_hwmod, .master = &omap2420_l4_core_hwmod,
.slave = &omap2420_dss_rfbi_hwmod, .slave = &omap2420_dss_rfbi_hwmod,
.clk = "dss_ick", .clk = "dss_ick",
.addr = omap2420_dss_rfbi_addrs, .addr = omap2_dss_rfbi_addrs,
.addr_cnt = ARRAY_SIZE(omap2420_dss_rfbi_addrs),
.fw = { .fw = {
.omap2 = { .omap2 = {
.l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
...@@ -1363,7 +964,7 @@ static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = { ...@@ -1363,7 +964,7 @@ static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = {
static struct omap_hwmod omap2420_dss_rfbi_hwmod = { static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
.name = "dss_rfbi", .name = "dss_rfbi",
.class = &omap2420_rfbi_hwmod_class, .class = &omap2_rfbi_hwmod_class,
.main_clk = "dss1_fck", .main_clk = "dss1_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1378,31 +979,12 @@ static struct omap_hwmod omap2420_dss_rfbi_hwmod = { ...@@ -1378,31 +979,12 @@ static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
.flags = HWMOD_NO_IDLEST, .flags = HWMOD_NO_IDLEST,
}; };
/*
* 'venc' class
* video encoder
*/
static struct omap_hwmod_class omap2420_venc_hwmod_class = {
.name = "venc",
};
/* dss_venc */
static struct omap_hwmod_addr_space omap2420_dss_venc_addrs[] = {
{
.pa_start = 0x48050C00,
.pa_end = 0x48050FFF,
.flags = ADDR_TYPE_RT
},
};
/* l4_core -> dss_venc */ /* l4_core -> dss_venc */
static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = { static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = {
.master = &omap2420_l4_core_hwmod, .master = &omap2420_l4_core_hwmod,
.slave = &omap2420_dss_venc_hwmod, .slave = &omap2420_dss_venc_hwmod,
.clk = "dss_54m_fck", .clk = "dss_54m_fck",
.addr = omap2420_dss_venc_addrs, .addr = omap2_dss_venc_addrs,
.addr_cnt = ARRAY_SIZE(omap2420_dss_venc_addrs),
.fw = { .fw = {
.omap2 = { .omap2 = {
.l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION, .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
...@@ -1420,7 +1002,7 @@ static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = { ...@@ -1420,7 +1002,7 @@ static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = {
static struct omap_hwmod omap2420_dss_venc_hwmod = { static struct omap_hwmod omap2420_dss_venc_hwmod = {
.name = "dss_venc", .name = "dss_venc",
.class = &omap2420_venc_hwmod_class, .class = &omap2_venc_hwmod_class,
.main_clk = "dss1_fck", .main_clk = "dss1_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1453,25 +1035,14 @@ static struct omap_i2c_dev_attr i2c_dev_attr; ...@@ -1453,25 +1035,14 @@ static struct omap_i2c_dev_attr i2c_dev_attr;
/* I2C1 */ /* I2C1 */
static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
{ .irq = INT_24XX_I2C1_IRQ, },
};
static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
};
static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = { static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = {
&omap2420_l4_core__i2c1, &omap2420_l4_core__i2c1,
}; };
static struct omap_hwmod omap2420_i2c1_hwmod = { static struct omap_hwmod omap2420_i2c1_hwmod = {
.name = "i2c1", .name = "i2c1",
.mpu_irqs = i2c1_mpu_irqs, .mpu_irqs = omap2_i2c1_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs), .sdma_reqs = omap2_i2c1_sdma_reqs,
.sdma_reqs = i2c1_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
.main_clk = "i2c1_fck", .main_clk = "i2c1_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1492,25 +1063,14 @@ static struct omap_hwmod omap2420_i2c1_hwmod = { ...@@ -1492,25 +1063,14 @@ static struct omap_hwmod omap2420_i2c1_hwmod = {
/* I2C2 */ /* I2C2 */
static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
{ .irq = INT_24XX_I2C2_IRQ, },
};
static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
};
static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = { static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = {
&omap2420_l4_core__i2c2, &omap2420_l4_core__i2c2,
}; };
static struct omap_hwmod omap2420_i2c2_hwmod = { static struct omap_hwmod omap2420_i2c2_hwmod = {
.name = "i2c2", .name = "i2c2",
.mpu_irqs = i2c2_mpu_irqs, .mpu_irqs = omap2_i2c2_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs), .sdma_reqs = omap2_i2c2_sdma_reqs,
.sdma_reqs = i2c2_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
.main_clk = "i2c2_fck", .main_clk = "i2c2_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1536,6 +1096,7 @@ static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = { ...@@ -1536,6 +1096,7 @@ static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
.pa_end = 0x480181ff, .pa_end = 0x480181ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = { static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
...@@ -1543,7 +1104,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = { ...@@ -1543,7 +1104,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
.slave = &omap2420_gpio1_hwmod, .slave = &omap2420_gpio1_hwmod,
.clk = "gpios_ick", .clk = "gpios_ick",
.addr = omap2420_gpio1_addr_space, .addr = omap2420_gpio1_addr_space,
.addr_cnt = ARRAY_SIZE(omap2420_gpio1_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -1554,6 +1114,7 @@ static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = { ...@@ -1554,6 +1114,7 @@ static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = {
.pa_end = 0x4801a1ff, .pa_end = 0x4801a1ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = { static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
...@@ -1561,7 +1122,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = { ...@@ -1561,7 +1122,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
.slave = &omap2420_gpio2_hwmod, .slave = &omap2420_gpio2_hwmod,
.clk = "gpios_ick", .clk = "gpios_ick",
.addr = omap2420_gpio2_addr_space, .addr = omap2420_gpio2_addr_space,
.addr_cnt = ARRAY_SIZE(omap2420_gpio2_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -1572,6 +1132,7 @@ static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = { ...@@ -1572,6 +1132,7 @@ static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = {
.pa_end = 0x4801c1ff, .pa_end = 0x4801c1ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = { static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
...@@ -1579,7 +1140,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = { ...@@ -1579,7 +1140,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
.slave = &omap2420_gpio3_hwmod, .slave = &omap2420_gpio3_hwmod,
.clk = "gpios_ick", .clk = "gpios_ick",
.addr = omap2420_gpio3_addr_space, .addr = omap2420_gpio3_addr_space,
.addr_cnt = ARRAY_SIZE(omap2420_gpio3_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -1590,6 +1150,7 @@ static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = { ...@@ -1590,6 +1150,7 @@ static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = {
.pa_end = 0x4801e1ff, .pa_end = 0x4801e1ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = { static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
...@@ -1597,7 +1158,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = { ...@@ -1597,7 +1158,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
.slave = &omap2420_gpio4_hwmod, .slave = &omap2420_gpio4_hwmod,
.clk = "gpios_ick", .clk = "gpios_ick",
.addr = omap2420_gpio4_addr_space, .addr = omap2420_gpio4_addr_space,
.addr_cnt = ARRAY_SIZE(omap2420_gpio4_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -1607,32 +1167,7 @@ static struct omap_gpio_dev_attr gpio_dev_attr = { ...@@ -1607,32 +1167,7 @@ static struct omap_gpio_dev_attr gpio_dev_attr = {
.dbck_flag = false, .dbck_flag = false,
}; };
static struct omap_hwmod_class_sysconfig omap242x_gpio_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
/*
* 'gpio' class
* general purpose io module
*/
static struct omap_hwmod_class omap242x_gpio_hwmod_class = {
.name = "gpio",
.sysc = &omap242x_gpio_sysc,
.rev = 0,
};
/* gpio1 */ /* gpio1 */
static struct omap_hwmod_irq_info omap242x_gpio1_irqs[] = {
{ .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
};
static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = { static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = {
&omap2420_l4_wkup__gpio1, &omap2420_l4_wkup__gpio1,
}; };
...@@ -1640,8 +1175,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = { ...@@ -1640,8 +1175,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = {
static struct omap_hwmod omap2420_gpio1_hwmod = { static struct omap_hwmod omap2420_gpio1_hwmod = {
.name = "gpio1", .name = "gpio1",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap242x_gpio1_irqs, .mpu_irqs = omap2_gpio1_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio1_irqs),
.main_clk = "gpios_fck", .main_clk = "gpios_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1654,16 +1188,12 @@ static struct omap_hwmod omap2420_gpio1_hwmod = { ...@@ -1654,16 +1188,12 @@ static struct omap_hwmod omap2420_gpio1_hwmod = {
}, },
.slaves = omap2420_gpio1_slaves, .slaves = omap2420_gpio1_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_gpio1_slaves), .slaves_cnt = ARRAY_SIZE(omap2420_gpio1_slaves),
.class = &omap242x_gpio_hwmod_class, .class = &omap2xxx_gpio_hwmod_class,
.dev_attr = &gpio_dev_attr, .dev_attr = &gpio_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
}; };
/* gpio2 */ /* gpio2 */
static struct omap_hwmod_irq_info omap242x_gpio2_irqs[] = {
{ .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
};
static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = { static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = {
&omap2420_l4_wkup__gpio2, &omap2420_l4_wkup__gpio2,
}; };
...@@ -1671,8 +1201,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = { ...@@ -1671,8 +1201,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = {
static struct omap_hwmod omap2420_gpio2_hwmod = { static struct omap_hwmod omap2420_gpio2_hwmod = {
.name = "gpio2", .name = "gpio2",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap242x_gpio2_irqs, .mpu_irqs = omap2_gpio2_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio2_irqs),
.main_clk = "gpios_fck", .main_clk = "gpios_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1685,16 +1214,12 @@ static struct omap_hwmod omap2420_gpio2_hwmod = { ...@@ -1685,16 +1214,12 @@ static struct omap_hwmod omap2420_gpio2_hwmod = {
}, },
.slaves = omap2420_gpio2_slaves, .slaves = omap2420_gpio2_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_gpio2_slaves), .slaves_cnt = ARRAY_SIZE(omap2420_gpio2_slaves),
.class = &omap242x_gpio_hwmod_class, .class = &omap2xxx_gpio_hwmod_class,
.dev_attr = &gpio_dev_attr, .dev_attr = &gpio_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
}; };
/* gpio3 */ /* gpio3 */
static struct omap_hwmod_irq_info omap242x_gpio3_irqs[] = {
{ .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
};
static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = { static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = {
&omap2420_l4_wkup__gpio3, &omap2420_l4_wkup__gpio3,
}; };
...@@ -1702,8 +1227,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = { ...@@ -1702,8 +1227,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = {
static struct omap_hwmod omap2420_gpio3_hwmod = { static struct omap_hwmod omap2420_gpio3_hwmod = {
.name = "gpio3", .name = "gpio3",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap242x_gpio3_irqs, .mpu_irqs = omap2_gpio3_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio3_irqs),
.main_clk = "gpios_fck", .main_clk = "gpios_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1716,16 +1240,12 @@ static struct omap_hwmod omap2420_gpio3_hwmod = { ...@@ -1716,16 +1240,12 @@ static struct omap_hwmod omap2420_gpio3_hwmod = {
}, },
.slaves = omap2420_gpio3_slaves, .slaves = omap2420_gpio3_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_gpio3_slaves), .slaves_cnt = ARRAY_SIZE(omap2420_gpio3_slaves),
.class = &omap242x_gpio_hwmod_class, .class = &omap2xxx_gpio_hwmod_class,
.dev_attr = &gpio_dev_attr, .dev_attr = &gpio_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
}; };
/* gpio4 */ /* gpio4 */
static struct omap_hwmod_irq_info omap242x_gpio4_irqs[] = {
{ .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
};
static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = { static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = {
&omap2420_l4_wkup__gpio4, &omap2420_l4_wkup__gpio4,
}; };
...@@ -1733,8 +1253,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = { ...@@ -1733,8 +1253,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = {
static struct omap_hwmod omap2420_gpio4_hwmod = { static struct omap_hwmod omap2420_gpio4_hwmod = {
.name = "gpio4", .name = "gpio4",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap242x_gpio4_irqs, .mpu_irqs = omap2_gpio4_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio4_irqs),
.main_clk = "gpios_fck", .main_clk = "gpios_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1747,28 +1266,11 @@ static struct omap_hwmod omap2420_gpio4_hwmod = { ...@@ -1747,28 +1266,11 @@ static struct omap_hwmod omap2420_gpio4_hwmod = {
}, },
.slaves = omap2420_gpio4_slaves, .slaves = omap2420_gpio4_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_gpio4_slaves), .slaves_cnt = ARRAY_SIZE(omap2420_gpio4_slaves),
.class = &omap242x_gpio_hwmod_class, .class = &omap2xxx_gpio_hwmod_class,
.dev_attr = &gpio_dev_attr, .dev_attr = &gpio_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
}; };
/* system dma */
static struct omap_hwmod_class_sysconfig omap2420_dma_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x002c,
.syss_offs = 0x0028,
.sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
.idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap2420_dma_hwmod_class = {
.name = "dma",
.sysc = &omap2420_dma_sysc,
};
/* dma attributes */ /* dma attributes */
static struct omap_dma_dev_attr dma_dev_attr = { static struct omap_dma_dev_attr dma_dev_attr = {
.dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
...@@ -1776,21 +1278,6 @@ static struct omap_dma_dev_attr dma_dev_attr = { ...@@ -1776,21 +1278,6 @@ static struct omap_dma_dev_attr dma_dev_attr = {
.lch_count = 32, .lch_count = 32,
}; };
static struct omap_hwmod_irq_info omap2420_dma_system_irqs[] = {
{ .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
{ .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
{ .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
{ .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
};
static struct omap_hwmod_addr_space omap2420_dma_system_addrs[] = {
{
.pa_start = 0x48056000,
.pa_end = 0x48056fff,
.flags = ADDR_TYPE_RT
},
};
/* dma_system -> L3 */ /* dma_system -> L3 */
static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = { static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
.master = &omap2420_dma_system_hwmod, .master = &omap2420_dma_system_hwmod,
...@@ -1809,8 +1296,7 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = { ...@@ -1809,8 +1296,7 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
.master = &omap2420_l4_core_hwmod, .master = &omap2420_l4_core_hwmod,
.slave = &omap2420_dma_system_hwmod, .slave = &omap2420_dma_system_hwmod,
.clk = "sdma_ick", .clk = "sdma_ick",
.addr = omap2420_dma_system_addrs, .addr = omap2_dma_system_addrs,
.addr_cnt = ARRAY_SIZE(omap2420_dma_system_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -1821,9 +1307,8 @@ static struct omap_hwmod_ocp_if *omap2420_dma_system_slaves[] = { ...@@ -1821,9 +1307,8 @@ static struct omap_hwmod_ocp_if *omap2420_dma_system_slaves[] = {
static struct omap_hwmod omap2420_dma_system_hwmod = { static struct omap_hwmod omap2420_dma_system_hwmod = {
.name = "dma", .name = "dma",
.class = &omap2420_dma_hwmod_class, .class = &omap2xxx_dma_hwmod_class,
.mpu_irqs = omap2420_dma_system_irqs, .mpu_irqs = omap2_dma_system_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2420_dma_system_irqs),
.main_clk = "core_l3_ck", .main_clk = "core_l3_ck",
.slaves = omap2420_dma_system_slaves, .slaves = omap2420_dma_system_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_dma_system_slaves), .slaves_cnt = ARRAY_SIZE(omap2420_dma_system_slaves),
...@@ -1834,48 +1319,19 @@ static struct omap_hwmod omap2420_dma_system_hwmod = { ...@@ -1834,48 +1319,19 @@ static struct omap_hwmod omap2420_dma_system_hwmod = {
.flags = HWMOD_NO_IDLEST, .flags = HWMOD_NO_IDLEST,
}; };
/*
* 'mailbox' class
* mailbox module allowing communication between the on-chip processors
* using a queued mailbox-interrupt mechanism.
*/
static struct omap_hwmod_class_sysconfig omap2420_mailbox_sysc = {
.rev_offs = 0x000,
.sysc_offs = 0x010,
.syss_offs = 0x014,
.sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap2420_mailbox_hwmod_class = {
.name = "mailbox",
.sysc = &omap2420_mailbox_sysc,
};
/* mailbox */ /* mailbox */
static struct omap_hwmod omap2420_mailbox_hwmod; static struct omap_hwmod omap2420_mailbox_hwmod;
static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = { static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
{ .name = "dsp", .irq = 26 }, { .name = "dsp", .irq = 26 },
{ .name = "iva", .irq = 34 }, { .name = "iva", .irq = 34 },
}; { .irq = -1 }
static struct omap_hwmod_addr_space omap2420_mailbox_addrs[] = {
{
.pa_start = 0x48094000,
.pa_end = 0x480941ff,
.flags = ADDR_TYPE_RT,
},
}; };
/* l4_core -> mailbox */ /* l4_core -> mailbox */
static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = { static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
.master = &omap2420_l4_core_hwmod, .master = &omap2420_l4_core_hwmod,
.slave = &omap2420_mailbox_hwmod, .slave = &omap2420_mailbox_hwmod,
.addr = omap2420_mailbox_addrs, .addr = omap2_mailbox_addrs,
.addr_cnt = ARRAY_SIZE(omap2420_mailbox_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -1886,9 +1342,8 @@ static struct omap_hwmod_ocp_if *omap2420_mailbox_slaves[] = { ...@@ -1886,9 +1342,8 @@ static struct omap_hwmod_ocp_if *omap2420_mailbox_slaves[] = {
static struct omap_hwmod omap2420_mailbox_hwmod = { static struct omap_hwmod omap2420_mailbox_hwmod = {
.name = "mailbox", .name = "mailbox",
.class = &omap2420_mailbox_hwmod_class, .class = &omap2xxx_mailbox_hwmod_class,
.mpu_irqs = omap2420_mailbox_irqs, .mpu_irqs = omap2420_mailbox_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2420_mailbox_irqs),
.main_clk = "mailboxes_ick", .main_clk = "mailboxes_ick",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1904,45 +1359,7 @@ static struct omap_hwmod omap2420_mailbox_hwmod = { ...@@ -1904,45 +1359,7 @@ static struct omap_hwmod omap2420_mailbox_hwmod = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
}; };
/*
* 'mcspi' class
* multichannel serial port interface (mcspi) / master/slave synchronous serial
* bus
*/
static struct omap_hwmod_class_sysconfig omap2420_mcspi_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap2420_mcspi_class = {
.name = "mcspi",
.sysc = &omap2420_mcspi_sysc,
.rev = OMAP2_MCSPI_REV,
};
/* mcspi1 */ /* mcspi1 */
static struct omap_hwmod_irq_info omap2420_mcspi1_mpu_irqs[] = {
{ .irq = 65 },
};
static struct omap_hwmod_dma_info omap2420_mcspi1_sdma_reqs[] = {
{ .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
{ .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
{ .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
{ .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
{ .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
{ .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
{ .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
{ .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
};
static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = { static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = {
&omap2420_l4_core__mcspi1, &omap2420_l4_core__mcspi1,
}; };
...@@ -1953,10 +1370,8 @@ static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { ...@@ -1953,10 +1370,8 @@ static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
static struct omap_hwmod omap2420_mcspi1_hwmod = { static struct omap_hwmod omap2420_mcspi1_hwmod = {
.name = "mcspi1_hwmod", .name = "mcspi1_hwmod",
.mpu_irqs = omap2420_mcspi1_mpu_irqs, .mpu_irqs = omap2_mcspi1_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcspi1_mpu_irqs), .sdma_reqs = omap2_mcspi1_sdma_reqs,
.sdma_reqs = omap2420_mcspi1_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcspi1_sdma_reqs),
.main_clk = "mcspi1_fck", .main_clk = "mcspi1_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1969,23 +1384,12 @@ static struct omap_hwmod omap2420_mcspi1_hwmod = { ...@@ -1969,23 +1384,12 @@ static struct omap_hwmod omap2420_mcspi1_hwmod = {
}, },
.slaves = omap2420_mcspi1_slaves, .slaves = omap2420_mcspi1_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_mcspi1_slaves), .slaves_cnt = ARRAY_SIZE(omap2420_mcspi1_slaves),
.class = &omap2420_mcspi_class, .class = &omap2xxx_mcspi_class,
.dev_attr = &omap_mcspi1_dev_attr, .dev_attr = &omap_mcspi1_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
}; };
/* mcspi2 */ /* mcspi2 */
static struct omap_hwmod_irq_info omap2420_mcspi2_mpu_irqs[] = {
{ .irq = 66 },
};
static struct omap_hwmod_dma_info omap2420_mcspi2_sdma_reqs[] = {
{ .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
{ .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
{ .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
{ .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
};
static struct omap_hwmod_ocp_if *omap2420_mcspi2_slaves[] = { static struct omap_hwmod_ocp_if *omap2420_mcspi2_slaves[] = {
&omap2420_l4_core__mcspi2, &omap2420_l4_core__mcspi2,
}; };
...@@ -1996,10 +1400,8 @@ static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { ...@@ -1996,10 +1400,8 @@ static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
static struct omap_hwmod omap2420_mcspi2_hwmod = { static struct omap_hwmod omap2420_mcspi2_hwmod = {
.name = "mcspi2_hwmod", .name = "mcspi2_hwmod",
.mpu_irqs = omap2420_mcspi2_mpu_irqs, .mpu_irqs = omap2_mcspi2_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcspi2_mpu_irqs), .sdma_reqs = omap2_mcspi2_sdma_reqs,
.sdma_reqs = omap2420_mcspi2_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcspi2_sdma_reqs),
.main_clk = "mcspi2_fck", .main_clk = "mcspi2_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -2012,8 +1414,8 @@ static struct omap_hwmod omap2420_mcspi2_hwmod = { ...@@ -2012,8 +1414,8 @@ static struct omap_hwmod omap2420_mcspi2_hwmod = {
}, },
.slaves = omap2420_mcspi2_slaves, .slaves = omap2420_mcspi2_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_mcspi2_slaves), .slaves_cnt = ARRAY_SIZE(omap2420_mcspi2_slaves),
.class = &omap2420_mcspi_class, .class = &omap2xxx_mcspi_class,
.dev_attr = &omap_mcspi2_dev_attr, .dev_attr = &omap_mcspi2_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
}; };
...@@ -2030,20 +1432,7 @@ static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = { ...@@ -2030,20 +1432,7 @@ static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = { static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
{ .name = "tx", .irq = 59 }, { .name = "tx", .irq = 59 },
{ .name = "rx", .irq = 60 }, { .name = "rx", .irq = 60 },
}; { .irq = -1 }
static struct omap_hwmod_dma_info omap2420_mcbsp1_sdma_chs[] = {
{ .name = "rx", .dma_req = 32 },
{ .name = "tx", .dma_req = 31 },
};
static struct omap_hwmod_addr_space omap2420_mcbsp1_addrs[] = {
{
.name = "mpu",
.pa_start = 0x48074000,
.pa_end = 0x480740ff,
.flags = ADDR_TYPE_RT
},
}; };
/* l4_core -> mcbsp1 */ /* l4_core -> mcbsp1 */
...@@ -2051,8 +1440,7 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = { ...@@ -2051,8 +1440,7 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
.master = &omap2420_l4_core_hwmod, .master = &omap2420_l4_core_hwmod,
.slave = &omap2420_mcbsp1_hwmod, .slave = &omap2420_mcbsp1_hwmod,
.clk = "mcbsp1_ick", .clk = "mcbsp1_ick",
.addr = omap2420_mcbsp1_addrs, .addr = omap2_mcbsp1_addrs,
.addr_cnt = ARRAY_SIZE(omap2420_mcbsp1_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -2065,9 +1453,7 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod = { ...@@ -2065,9 +1453,7 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod = {
.name = "mcbsp1", .name = "mcbsp1",
.class = &omap2420_mcbsp_hwmod_class, .class = &omap2420_mcbsp_hwmod_class,
.mpu_irqs = omap2420_mcbsp1_irqs, .mpu_irqs = omap2420_mcbsp1_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcbsp1_irqs), .sdma_reqs = omap2_mcbsp1_sdma_reqs,
.sdma_reqs = omap2420_mcbsp1_sdma_chs,
.sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcbsp1_sdma_chs),
.main_clk = "mcbsp1_fck", .main_clk = "mcbsp1_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -2087,20 +1473,7 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod = { ...@@ -2087,20 +1473,7 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod = {
static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = { static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
{ .name = "tx", .irq = 62 }, { .name = "tx", .irq = 62 },
{ .name = "rx", .irq = 63 }, { .name = "rx", .irq = 63 },
}; { .irq = -1 }
static struct omap_hwmod_dma_info omap2420_mcbsp2_sdma_chs[] = {
{ .name = "rx", .dma_req = 34 },
{ .name = "tx", .dma_req = 33 },
};
static struct omap_hwmod_addr_space omap2420_mcbsp2_addrs[] = {
{
.name = "mpu",
.pa_start = 0x48076000,
.pa_end = 0x480760ff,
.flags = ADDR_TYPE_RT
},
}; };
/* l4_core -> mcbsp2 */ /* l4_core -> mcbsp2 */
...@@ -2108,8 +1481,7 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = { ...@@ -2108,8 +1481,7 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
.master = &omap2420_l4_core_hwmod, .master = &omap2420_l4_core_hwmod,
.slave = &omap2420_mcbsp2_hwmod, .slave = &omap2420_mcbsp2_hwmod,
.clk = "mcbsp2_ick", .clk = "mcbsp2_ick",
.addr = omap2420_mcbsp2_addrs, .addr = omap2xxx_mcbsp2_addrs,
.addr_cnt = ARRAY_SIZE(omap2420_mcbsp2_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -2122,9 +1494,7 @@ static struct omap_hwmod omap2420_mcbsp2_hwmod = { ...@@ -2122,9 +1494,7 @@ static struct omap_hwmod omap2420_mcbsp2_hwmod = {
.name = "mcbsp2", .name = "mcbsp2",
.class = &omap2420_mcbsp_hwmod_class, .class = &omap2420_mcbsp_hwmod_class,
.mpu_irqs = omap2420_mcbsp2_irqs, .mpu_irqs = omap2420_mcbsp2_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcbsp2_irqs), .sdma_reqs = omap2_mcbsp2_sdma_reqs,
.sdma_reqs = omap2420_mcbsp2_sdma_chs,
.sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcbsp2_sdma_chs),
.main_clk = "mcbsp2_fck", .main_clk = "mcbsp2_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
......
arch/arm/mach-omap2/omap_hwmod_2430_data.c
浏览文件 @ c402c0d9
/* /*
* omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips
* *
* Copyright (C) 2009-2010 Nokia Corporation * Copyright (C) 2009-2011 Nokia Corporation
* Paul Walmsley * Paul Walmsley
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
...@@ -131,42 +131,21 @@ static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = { ...@@ -131,42 +131,21 @@ static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
/* I2C IP block address space length (in bytes) */
#define OMAP2_I2C_AS_LEN 128
/* L4 CORE -> I2C1 interface */ /* L4 CORE -> I2C1 interface */
static struct omap_hwmod_addr_space omap2430_i2c1_addr_space[] = {
{
.pa_start = 0x48070000,
.pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
.flags = ADDR_TYPE_RT,
},
};
static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = { static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
.master = &omap2430_l4_core_hwmod, .master = &omap2430_l4_core_hwmod,
.slave = &omap2430_i2c1_hwmod, .slave = &omap2430_i2c1_hwmod,
.clk = "i2c1_ick", .clk = "i2c1_ick",
.addr = omap2430_i2c1_addr_space, .addr = omap2_i2c1_addr_space,
.addr_cnt = ARRAY_SIZE(omap2430_i2c1_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* L4 CORE -> I2C2 interface */ /* L4 CORE -> I2C2 interface */
static struct omap_hwmod_addr_space omap2430_i2c2_addr_space[] = {
{
.pa_start = 0x48072000,
.pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
.flags = ADDR_TYPE_RT,
},
};
static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = { static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
.master = &omap2430_l4_core_hwmod, .master = &omap2430_l4_core_hwmod,
.slave = &omap2430_i2c2_hwmod, .slave = &omap2430_i2c2_hwmod,
.clk = "i2c2_ick", .clk = "i2c2_ick",
.addr = omap2430_i2c2_addr_space, .addr = omap2_i2c2_addr_space,
.addr_cnt = ARRAY_SIZE(omap2430_i2c2_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -178,56 +157,29 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = { ...@@ -178,56 +157,29 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = {
}; };
/* L4 CORE -> UART1 interface */ /* L4 CORE -> UART1 interface */
static struct omap_hwmod_addr_space omap2430_uart1_addr_space[] = {
{
.pa_start = OMAP2_UART1_BASE,
.pa_end = OMAP2_UART1_BASE + SZ_8K - 1,
.flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
},
};
static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
.master = &omap2430_l4_core_hwmod, .master = &omap2430_l4_core_hwmod,
.slave = &omap2430_uart1_hwmod, .slave = &omap2430_uart1_hwmod,
.clk = "uart1_ick", .clk = "uart1_ick",
.addr = omap2430_uart1_addr_space, .addr = omap2xxx_uart1_addr_space,
.addr_cnt = ARRAY_SIZE(omap2430_uart1_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* L4 CORE -> UART2 interface */ /* L4 CORE -> UART2 interface */
static struct omap_hwmod_addr_space omap2430_uart2_addr_space[] = {
{
.pa_start = OMAP2_UART2_BASE,
.pa_end = OMAP2_UART2_BASE + SZ_1K - 1,
.flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
},
};
static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
.master = &omap2430_l4_core_hwmod, .master = &omap2430_l4_core_hwmod,
.slave = &omap2430_uart2_hwmod, .slave = &omap2430_uart2_hwmod,
.clk = "uart2_ick", .clk = "uart2_ick",
.addr = omap2430_uart2_addr_space, .addr = omap2xxx_uart2_addr_space,
.addr_cnt = ARRAY_SIZE(omap2430_uart2_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* L4 PER -> UART3 interface */ /* L4 PER -> UART3 interface */
static struct omap_hwmod_addr_space omap2430_uart3_addr_space[] = {
{
.pa_start = OMAP2_UART3_BASE,
.pa_end = OMAP2_UART3_BASE + SZ_1K - 1,
.flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
},
};
static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
.master = &omap2430_l4_core_hwmod, .master = &omap2430_l4_core_hwmod,
.slave = &omap2430_uart3_hwmod, .slave = &omap2430_uart3_hwmod,
.clk = "uart3_ick", .clk = "uart3_ick",
.addr = omap2430_uart3_addr_space, .addr = omap2xxx_uart3_addr_space,
.addr_cnt = ARRAY_SIZE(omap2430_uart3_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -248,7 +200,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = { ...@@ -248,7 +200,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
.slave = &omap2430_usbhsotg_hwmod, .slave = &omap2430_usbhsotg_hwmod,
.clk = "usb_l4_ick", .clk = "usb_l4_ick",
.addr = omap2430_usbhsotg_addrs, .addr = omap2430_usbhsotg_addrs,
.addr_cnt = ARRAY_SIZE(omap2430_usbhsotg_addrs),
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
...@@ -261,38 +212,20 @@ static struct omap_hwmod_ocp_if *omap2430_usbhsotg_slaves[] = { ...@@ -261,38 +212,20 @@ static struct omap_hwmod_ocp_if *omap2430_usbhsotg_slaves[] = {
}; };
/* L4 CORE -> MMC1 interface */ /* L4 CORE -> MMC1 interface */
static struct omap_hwmod_addr_space omap2430_mmc1_addr_space[] = {
{
.pa_start = 0x4809c000,
.pa_end = 0x4809c1ff,
.flags = ADDR_TYPE_RT,
},
};
static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = { static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
.master = &omap2430_l4_core_hwmod, .master = &omap2430_l4_core_hwmod,
.slave = &omap2430_mmc1_hwmod, .slave = &omap2430_mmc1_hwmod,
.clk = "mmchs1_ick", .clk = "mmchs1_ick",
.addr = omap2430_mmc1_addr_space, .addr = omap2430_mmc1_addr_space,
.addr_cnt = ARRAY_SIZE(omap2430_mmc1_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* L4 CORE -> MMC2 interface */ /* L4 CORE -> MMC2 interface */
static struct omap_hwmod_addr_space omap2430_mmc2_addr_space[] = {
{
.pa_start = 0x480b4000,
.pa_end = 0x480b41ff,
.flags = ADDR_TYPE_RT,
},
};
static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = { static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
.master = &omap2430_l4_core_hwmod, .master = &omap2430_l4_core_hwmod,
.slave = &omap2430_mmc2_hwmod, .slave = &omap2430_mmc2_hwmod,
.addr = omap2430_mmc2_addr_space,
.clk = "mmchs2_ick", .clk = "mmchs2_ick",
.addr_cnt = ARRAY_SIZE(omap2430_mmc2_addr_space), .addr = omap2430_mmc2_addr_space,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -333,56 +266,29 @@ static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = { ...@@ -333,56 +266,29 @@ static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = {
}; };
/* l4 core -> mcspi1 interface */ /* l4 core -> mcspi1 interface */
static struct omap_hwmod_addr_space omap2430_mcspi1_addr_space[] = {
{
.pa_start = 0x48098000,
.pa_end = 0x480980ff,
.flags = ADDR_TYPE_RT,
},
};
static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = { static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = {
.master = &omap2430_l4_core_hwmod, .master = &omap2430_l4_core_hwmod,
.slave = &omap2430_mcspi1_hwmod, .slave = &omap2430_mcspi1_hwmod,
.clk = "mcspi1_ick", .clk = "mcspi1_ick",
.addr = omap2430_mcspi1_addr_space, .addr = omap2_mcspi1_addr_space,
.addr_cnt = ARRAY_SIZE(omap2430_mcspi1_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* l4 core -> mcspi2 interface */ /* l4 core -> mcspi2 interface */
static struct omap_hwmod_addr_space omap2430_mcspi2_addr_space[] = {
{
.pa_start = 0x4809a000,
.pa_end = 0x4809a0ff,
.flags = ADDR_TYPE_RT,
},
};
static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = { static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = {
.master = &omap2430_l4_core_hwmod, .master = &omap2430_l4_core_hwmod,
.slave = &omap2430_mcspi2_hwmod, .slave = &omap2430_mcspi2_hwmod,
.clk = "mcspi2_ick", .clk = "mcspi2_ick",
.addr = omap2430_mcspi2_addr_space, .addr = omap2_mcspi2_addr_space,
.addr_cnt = ARRAY_SIZE(omap2430_mcspi2_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* l4 core -> mcspi3 interface */ /* l4 core -> mcspi3 interface */
static struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[] = {
{
.pa_start = 0x480b8000,
.pa_end = 0x480b80ff,
.flags = ADDR_TYPE_RT,
},
};
static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = { static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
.master = &omap2430_l4_core_hwmod, .master = &omap2430_l4_core_hwmod,
.slave = &omap2430_mcspi3_hwmod, .slave = &omap2430_mcspi3_hwmod,
.clk = "mcspi3_ick", .clk = "mcspi3_ick",
.addr = omap2430_mcspi3_addr_space, .addr = omap2430_mcspi3_addr_space,
.addr_cnt = ARRAY_SIZE(omap2430_mcspi3_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -441,29 +347,8 @@ static struct omap_hwmod omap2430_iva_hwmod = { ...@@ -441,29 +347,8 @@ static struct omap_hwmod omap2430_iva_hwmod = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
}; };
/* Timer Common */
static struct omap_hwmod_class_sysconfig omap2430_timer_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
SYSC_HAS_AUTOIDLE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap2430_timer_hwmod_class = {
.name = "timer",
.sysc = &omap2430_timer_sysc,
.rev = OMAP_TIMER_IP_VERSION_1,
};
/* timer1 */ /* timer1 */
static struct omap_hwmod omap2430_timer1_hwmod; static struct omap_hwmod omap2430_timer1_hwmod;
static struct omap_hwmod_irq_info omap2430_timer1_mpu_irqs[] = {
{ .irq = 37, },
};
static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = { static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
{ {
...@@ -471,6 +356,7 @@ static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = { ...@@ -471,6 +356,7 @@ static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
.pa_end = 0x49018000 + SZ_1K - 1, .pa_end = 0x49018000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_wkup -> timer1 */ /* l4_wkup -> timer1 */
...@@ -479,7 +365,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = { ...@@ -479,7 +365,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
.slave = &omap2430_timer1_hwmod, .slave = &omap2430_timer1_hwmod,
.clk = "gpt1_ick", .clk = "gpt1_ick",
.addr = omap2430_timer1_addrs, .addr = omap2430_timer1_addrs,
.addr_cnt = ARRAY_SIZE(omap2430_timer1_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -491,8 +376,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer1_slaves[] = { ...@@ -491,8 +376,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer1_slaves[] = {
/* timer1 hwmod */ /* timer1 hwmod */
static struct omap_hwmod omap2430_timer1_hwmod = { static struct omap_hwmod omap2430_timer1_hwmod = {
.name = "timer1", .name = "timer1",
.mpu_irqs = omap2430_timer1_mpu_irqs, .mpu_irqs = omap2_timer1_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer1_mpu_irqs),
.main_clk = "gpt1_fck", .main_clk = "gpt1_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -505,31 +389,19 @@ static struct omap_hwmod omap2430_timer1_hwmod = { ...@@ -505,31 +389,19 @@ static struct omap_hwmod omap2430_timer1_hwmod = {
}, },
.slaves = omap2430_timer1_slaves, .slaves = omap2430_timer1_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_timer1_slaves), .slaves_cnt = ARRAY_SIZE(omap2430_timer1_slaves),
.class = &omap2430_timer_hwmod_class, .class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
}; };
/* timer2 */ /* timer2 */
static struct omap_hwmod omap2430_timer2_hwmod; static struct omap_hwmod omap2430_timer2_hwmod;
static struct omap_hwmod_irq_info omap2430_timer2_mpu_irqs[] = {
{ .irq = 38, },
};
static struct omap_hwmod_addr_space omap2430_timer2_addrs[] = {
{
.pa_start = 0x4802a000,
.pa_end = 0x4802a000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
};
/* l4_core -> timer2 */ /* l4_core -> timer2 */
static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = { static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = {
.master = &omap2430_l4_core_hwmod, .master = &omap2430_l4_core_hwmod,
.slave = &omap2430_timer2_hwmod, .slave = &omap2430_timer2_hwmod,
.clk = "gpt2_ick", .clk = "gpt2_ick",
.addr = omap2430_timer2_addrs, .addr = omap2xxx_timer2_addrs,
.addr_cnt = ARRAY_SIZE(omap2430_timer2_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -541,8 +413,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer2_slaves[] = { ...@@ -541,8 +413,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer2_slaves[] = {
/* timer2 hwmod */ /* timer2 hwmod */
static struct omap_hwmod omap2430_timer2_hwmod = { static struct omap_hwmod omap2430_timer2_hwmod = {
.name = "timer2", .name = "timer2",
.mpu_irqs = omap2430_timer2_mpu_irqs, .mpu_irqs = omap2_timer2_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer2_mpu_irqs),
.main_clk = "gpt2_fck", .main_clk = "gpt2_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -555,31 +426,19 @@ static struct omap_hwmod omap2430_timer2_hwmod = { ...@@ -555,31 +426,19 @@ static struct omap_hwmod omap2430_timer2_hwmod = {
}, },
.slaves = omap2430_timer2_slaves, .slaves = omap2430_timer2_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_timer2_slaves), .slaves_cnt = ARRAY_SIZE(omap2430_timer2_slaves),
.class = &omap2430_timer_hwmod_class, .class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
}; };
/* timer3 */ /* timer3 */
static struct omap_hwmod omap2430_timer3_hwmod; static struct omap_hwmod omap2430_timer3_hwmod;
static struct omap_hwmod_irq_info omap2430_timer3_mpu_irqs[] = {
{ .irq = 39, },
};
static struct omap_hwmod_addr_space omap2430_timer3_addrs[] = {
{
.pa_start = 0x48078000,
.pa_end = 0x48078000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
};
/* l4_core -> timer3 */ /* l4_core -> timer3 */
static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = { static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = {
.master = &omap2430_l4_core_hwmod, .master = &omap2430_l4_core_hwmod,
.slave = &omap2430_timer3_hwmod, .slave = &omap2430_timer3_hwmod,
.clk = "gpt3_ick", .clk = "gpt3_ick",
.addr = omap2430_timer3_addrs, .addr = omap2xxx_timer3_addrs,
.addr_cnt = ARRAY_SIZE(omap2430_timer3_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -591,8 +450,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer3_slaves[] = { ...@@ -591,8 +450,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer3_slaves[] = {
/* timer3 hwmod */ /* timer3 hwmod */
static struct omap_hwmod omap2430_timer3_hwmod = { static struct omap_hwmod omap2430_timer3_hwmod = {
.name = "timer3", .name = "timer3",
.mpu_irqs = omap2430_timer3_mpu_irqs, .mpu_irqs = omap2_timer3_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer3_mpu_irqs),
.main_clk = "gpt3_fck", .main_clk = "gpt3_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -605,31 +463,19 @@ static struct omap_hwmod omap2430_timer3_hwmod = { ...@@ -605,31 +463,19 @@ static struct omap_hwmod omap2430_timer3_hwmod = {
}, },
.slaves = omap2430_timer3_slaves, .slaves = omap2430_timer3_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_timer3_slaves), .slaves_cnt = ARRAY_SIZE(omap2430_timer3_slaves),
.class = &omap2430_timer_hwmod_class, .class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
}; };
/* timer4 */ /* timer4 */
static struct omap_hwmod omap2430_timer4_hwmod; static struct omap_hwmod omap2430_timer4_hwmod;
static struct omap_hwmod_irq_info omap2430_timer4_mpu_irqs[] = {
{ .irq = 40, },
};
static struct omap_hwmod_addr_space omap2430_timer4_addrs[] = {
{
.pa_start = 0x4807a000,
.pa_end = 0x4807a000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
};
/* l4_core -> timer4 */ /* l4_core -> timer4 */
static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = { static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = {
.master = &omap2430_l4_core_hwmod, .master = &omap2430_l4_core_hwmod,
.slave = &omap2430_timer4_hwmod, .slave = &omap2430_timer4_hwmod,
.clk = "gpt4_ick", .clk = "gpt4_ick",
.addr = omap2430_timer4_addrs, .addr = omap2xxx_timer4_addrs,
.addr_cnt = ARRAY_SIZE(omap2430_timer4_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -641,8 +487,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer4_slaves[] = { ...@@ -641,8 +487,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer4_slaves[] = {
/* timer4 hwmod */ /* timer4 hwmod */
static struct omap_hwmod omap2430_timer4_hwmod = { static struct omap_hwmod omap2430_timer4_hwmod = {
.name = "timer4", .name = "timer4",
.mpu_irqs = omap2430_timer4_mpu_irqs, .mpu_irqs = omap2_timer4_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer4_mpu_irqs),
.main_clk = "gpt4_fck", .main_clk = "gpt4_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -655,31 +500,19 @@ static struct omap_hwmod omap2430_timer4_hwmod = { ...@@ -655,31 +500,19 @@ static struct omap_hwmod omap2430_timer4_hwmod = {
}, },
.slaves = omap2430_timer4_slaves, .slaves = omap2430_timer4_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_timer4_slaves), .slaves_cnt = ARRAY_SIZE(omap2430_timer4_slaves),
.class = &omap2430_timer_hwmod_class, .class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
}; };
/* timer5 */ /* timer5 */
static struct omap_hwmod omap2430_timer5_hwmod; static struct omap_hwmod omap2430_timer5_hwmod;
static struct omap_hwmod_irq_info omap2430_timer5_mpu_irqs[] = {
{ .irq = 41, },
};
static struct omap_hwmod_addr_space omap2430_timer5_addrs[] = {
{
.pa_start = 0x4807c000,
.pa_end = 0x4807c000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
};
/* l4_core -> timer5 */ /* l4_core -> timer5 */
static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = { static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = {
.master = &omap2430_l4_core_hwmod, .master = &omap2430_l4_core_hwmod,
.slave = &omap2430_timer5_hwmod, .slave = &omap2430_timer5_hwmod,
.clk = "gpt5_ick", .clk = "gpt5_ick",
.addr = omap2430_timer5_addrs, .addr = omap2xxx_timer5_addrs,
.addr_cnt = ARRAY_SIZE(omap2430_timer5_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -691,8 +524,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer5_slaves[] = { ...@@ -691,8 +524,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer5_slaves[] = {
/* timer5 hwmod */ /* timer5 hwmod */
static struct omap_hwmod omap2430_timer5_hwmod = { static struct omap_hwmod omap2430_timer5_hwmod = {
.name = "timer5", .name = "timer5",
.mpu_irqs = omap2430_timer5_mpu_irqs, .mpu_irqs = omap2_timer5_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer5_mpu_irqs),
.main_clk = "gpt5_fck", .main_clk = "gpt5_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -705,31 +537,19 @@ static struct omap_hwmod omap2430_timer5_hwmod = { ...@@ -705,31 +537,19 @@ static struct omap_hwmod omap2430_timer5_hwmod = {
}, },
.slaves = omap2430_timer5_slaves, .slaves = omap2430_timer5_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_timer5_slaves), .slaves_cnt = ARRAY_SIZE(omap2430_timer5_slaves),
.class = &omap2430_timer_hwmod_class, .class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
}; };
/* timer6 */ /* timer6 */
static struct omap_hwmod omap2430_timer6_hwmod; static struct omap_hwmod omap2430_timer6_hwmod;
static struct omap_hwmod_irq_info omap2430_timer6_mpu_irqs[] = {
{ .irq = 42, },
};
static struct omap_hwmod_addr_space omap2430_timer6_addrs[] = {
{
.pa_start = 0x4807e000,
.pa_end = 0x4807e000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
};
/* l4_core -> timer6 */ /* l4_core -> timer6 */
static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = { static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = {
.master = &omap2430_l4_core_hwmod, .master = &omap2430_l4_core_hwmod,
.slave = &omap2430_timer6_hwmod, .slave = &omap2430_timer6_hwmod,
.clk = "gpt6_ick", .clk = "gpt6_ick",
.addr = omap2430_timer6_addrs, .addr = omap2xxx_timer6_addrs,
.addr_cnt = ARRAY_SIZE(omap2430_timer6_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -741,8 +561,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer6_slaves[] = { ...@@ -741,8 +561,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer6_slaves[] = {
/* timer6 hwmod */ /* timer6 hwmod */
static struct omap_hwmod omap2430_timer6_hwmod = { static struct omap_hwmod omap2430_timer6_hwmod = {
.name = "timer6", .name = "timer6",
.mpu_irqs = omap2430_timer6_mpu_irqs, .mpu_irqs = omap2_timer6_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer6_mpu_irqs),
.main_clk = "gpt6_fck", .main_clk = "gpt6_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -755,31 +574,19 @@ static struct omap_hwmod omap2430_timer6_hwmod = { ...@@ -755,31 +574,19 @@ static struct omap_hwmod omap2430_timer6_hwmod = {
}, },
.slaves = omap2430_timer6_slaves, .slaves = omap2430_timer6_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_timer6_slaves), .slaves_cnt = ARRAY_SIZE(omap2430_timer6_slaves),
.class = &omap2430_timer_hwmod_class, .class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
}; };
/* timer7 */ /* timer7 */
static struct omap_hwmod omap2430_timer7_hwmod; static struct omap_hwmod omap2430_timer7_hwmod;
static struct omap_hwmod_irq_info omap2430_timer7_mpu_irqs[] = {
{ .irq = 43, },
};
static struct omap_hwmod_addr_space omap2430_timer7_addrs[] = {
{
.pa_start = 0x48080000,
.pa_end = 0x48080000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
};
/* l4_core -> timer7 */ /* l4_core -> timer7 */
static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = { static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = {
.master = &omap2430_l4_core_hwmod, .master = &omap2430_l4_core_hwmod,
.slave = &omap2430_timer7_hwmod, .slave = &omap2430_timer7_hwmod,
.clk = "gpt7_ick", .clk = "gpt7_ick",
.addr = omap2430_timer7_addrs, .addr = omap2xxx_timer7_addrs,
.addr_cnt = ARRAY_SIZE(omap2430_timer7_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -791,8 +598,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer7_slaves[] = { ...@@ -791,8 +598,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer7_slaves[] = {
/* timer7 hwmod */ /* timer7 hwmod */
static struct omap_hwmod omap2430_timer7_hwmod = { static struct omap_hwmod omap2430_timer7_hwmod = {
.name = "timer7", .name = "timer7",
.mpu_irqs = omap2430_timer7_mpu_irqs, .mpu_irqs = omap2_timer7_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer7_mpu_irqs),
.main_clk = "gpt7_fck", .main_clk = "gpt7_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -805,31 +611,19 @@ static struct omap_hwmod omap2430_timer7_hwmod = { ...@@ -805,31 +611,19 @@ static struct omap_hwmod omap2430_timer7_hwmod = {
}, },
.slaves = omap2430_timer7_slaves, .slaves = omap2430_timer7_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_timer7_slaves), .slaves_cnt = ARRAY_SIZE(omap2430_timer7_slaves),
.class = &omap2430_timer_hwmod_class, .class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
}; };
/* timer8 */ /* timer8 */
static struct omap_hwmod omap2430_timer8_hwmod; static struct omap_hwmod omap2430_timer8_hwmod;
static struct omap_hwmod_irq_info omap2430_timer8_mpu_irqs[] = {
{ .irq = 44, },
};
static struct omap_hwmod_addr_space omap2430_timer8_addrs[] = {
{
.pa_start = 0x48082000,
.pa_end = 0x48082000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
};
/* l4_core -> timer8 */ /* l4_core -> timer8 */
static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = { static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = {
.master = &omap2430_l4_core_hwmod, .master = &omap2430_l4_core_hwmod,
.slave = &omap2430_timer8_hwmod, .slave = &omap2430_timer8_hwmod,
.clk = "gpt8_ick", .clk = "gpt8_ick",
.addr = omap2430_timer8_addrs, .addr = omap2xxx_timer8_addrs,
.addr_cnt = ARRAY_SIZE(omap2430_timer8_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -841,8 +635,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer8_slaves[] = { ...@@ -841,8 +635,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer8_slaves[] = {
/* timer8 hwmod */ /* timer8 hwmod */
static struct omap_hwmod omap2430_timer8_hwmod = { static struct omap_hwmod omap2430_timer8_hwmod = {
.name = "timer8", .name = "timer8",
.mpu_irqs = omap2430_timer8_mpu_irqs, .mpu_irqs = omap2_timer8_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer8_mpu_irqs),
.main_clk = "gpt8_fck", .main_clk = "gpt8_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -855,31 +648,19 @@ static struct omap_hwmod omap2430_timer8_hwmod = { ...@@ -855,31 +648,19 @@ static struct omap_hwmod omap2430_timer8_hwmod = {
}, },
.slaves = omap2430_timer8_slaves, .slaves = omap2430_timer8_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_timer8_slaves), .slaves_cnt = ARRAY_SIZE(omap2430_timer8_slaves),
.class = &omap2430_timer_hwmod_class, .class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
}; };
/* timer9 */ /* timer9 */
static struct omap_hwmod omap2430_timer9_hwmod; static struct omap_hwmod omap2430_timer9_hwmod;
static struct omap_hwmod_irq_info omap2430_timer9_mpu_irqs[] = {
{ .irq = 45, },
};
static struct omap_hwmod_addr_space omap2430_timer9_addrs[] = {
{
.pa_start = 0x48084000,
.pa_end = 0x48084000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
};
/* l4_core -> timer9 */ /* l4_core -> timer9 */
static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = { static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = {
.master = &omap2430_l4_core_hwmod, .master = &omap2430_l4_core_hwmod,
.slave = &omap2430_timer9_hwmod, .slave = &omap2430_timer9_hwmod,
.clk = "gpt9_ick", .clk = "gpt9_ick",
.addr = omap2430_timer9_addrs, .addr = omap2xxx_timer9_addrs,
.addr_cnt = ARRAY_SIZE(omap2430_timer9_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -891,8 +672,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer9_slaves[] = { ...@@ -891,8 +672,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer9_slaves[] = {
/* timer9 hwmod */ /* timer9 hwmod */
static struct omap_hwmod omap2430_timer9_hwmod = { static struct omap_hwmod omap2430_timer9_hwmod = {
.name = "timer9", .name = "timer9",
.mpu_irqs = omap2430_timer9_mpu_irqs, .mpu_irqs = omap2_timer9_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer9_mpu_irqs),
.main_clk = "gpt9_fck", .main_clk = "gpt9_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -905,31 +685,19 @@ static struct omap_hwmod omap2430_timer9_hwmod = { ...@@ -905,31 +685,19 @@ static struct omap_hwmod omap2430_timer9_hwmod = {
}, },
.slaves = omap2430_timer9_slaves, .slaves = omap2430_timer9_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_timer9_slaves), .slaves_cnt = ARRAY_SIZE(omap2430_timer9_slaves),
.class = &omap2430_timer_hwmod_class, .class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
}; };
/* timer10 */ /* timer10 */
static struct omap_hwmod omap2430_timer10_hwmod; static struct omap_hwmod omap2430_timer10_hwmod;
static struct omap_hwmod_irq_info omap2430_timer10_mpu_irqs[] = {
{ .irq = 46, },
};
static struct omap_hwmod_addr_space omap2430_timer10_addrs[] = {
{
.pa_start = 0x48086000,
.pa_end = 0x48086000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
};
/* l4_core -> timer10 */ /* l4_core -> timer10 */
static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = { static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = {
.master = &omap2430_l4_core_hwmod, .master = &omap2430_l4_core_hwmod,
.slave = &omap2430_timer10_hwmod, .slave = &omap2430_timer10_hwmod,
.clk = "gpt10_ick", .clk = "gpt10_ick",
.addr = omap2430_timer10_addrs, .addr = omap2_timer10_addrs,
.addr_cnt = ARRAY_SIZE(omap2430_timer10_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -941,8 +709,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer10_slaves[] = { ...@@ -941,8 +709,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer10_slaves[] = {
/* timer10 hwmod */ /* timer10 hwmod */
static struct omap_hwmod omap2430_timer10_hwmod = { static struct omap_hwmod omap2430_timer10_hwmod = {
.name = "timer10", .name = "timer10",
.mpu_irqs = omap2430_timer10_mpu_irqs, .mpu_irqs = omap2_timer10_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer10_mpu_irqs),
.main_clk = "gpt10_fck", .main_clk = "gpt10_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -955,31 +722,19 @@ static struct omap_hwmod omap2430_timer10_hwmod = { ...@@ -955,31 +722,19 @@ static struct omap_hwmod omap2430_timer10_hwmod = {
}, },
.slaves = omap2430_timer10_slaves, .slaves = omap2430_timer10_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_timer10_slaves), .slaves_cnt = ARRAY_SIZE(omap2430_timer10_slaves),
.class = &omap2430_timer_hwmod_class, .class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
}; };
/* timer11 */ /* timer11 */
static struct omap_hwmod omap2430_timer11_hwmod; static struct omap_hwmod omap2430_timer11_hwmod;
static struct omap_hwmod_irq_info omap2430_timer11_mpu_irqs[] = {
{ .irq = 47, },
};
static struct omap_hwmod_addr_space omap2430_timer11_addrs[] = {
{
.pa_start = 0x48088000,
.pa_end = 0x48088000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
};
/* l4_core -> timer11 */ /* l4_core -> timer11 */
static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = { static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = {
.master = &omap2430_l4_core_hwmod, .master = &omap2430_l4_core_hwmod,
.slave = &omap2430_timer11_hwmod, .slave = &omap2430_timer11_hwmod,
.clk = "gpt11_ick", .clk = "gpt11_ick",
.addr = omap2430_timer11_addrs, .addr = omap2_timer11_addrs,
.addr_cnt = ARRAY_SIZE(omap2430_timer11_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -991,8 +746,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer11_slaves[] = { ...@@ -991,8 +746,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer11_slaves[] = {
/* timer11 hwmod */ /* timer11 hwmod */
static struct omap_hwmod omap2430_timer11_hwmod = { static struct omap_hwmod omap2430_timer11_hwmod = {
.name = "timer11", .name = "timer11",
.mpu_irqs = omap2430_timer11_mpu_irqs, .mpu_irqs = omap2_timer11_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer11_mpu_irqs),
.main_clk = "gpt11_fck", .main_clk = "gpt11_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1005,31 +759,19 @@ static struct omap_hwmod omap2430_timer11_hwmod = { ...@@ -1005,31 +759,19 @@ static struct omap_hwmod omap2430_timer11_hwmod = {
}, },
.slaves = omap2430_timer11_slaves, .slaves = omap2430_timer11_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_timer11_slaves), .slaves_cnt = ARRAY_SIZE(omap2430_timer11_slaves),
.class = &omap2430_timer_hwmod_class, .class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
}; };
/* timer12 */ /* timer12 */
static struct omap_hwmod omap2430_timer12_hwmod; static struct omap_hwmod omap2430_timer12_hwmod;
static struct omap_hwmod_irq_info omap2430_timer12_mpu_irqs[] = {
{ .irq = 48, },
};
static struct omap_hwmod_addr_space omap2430_timer12_addrs[] = {
{
.pa_start = 0x4808a000,
.pa_end = 0x4808a000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
};
/* l4_core -> timer12 */ /* l4_core -> timer12 */
static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = { static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = {
.master = &omap2430_l4_core_hwmod, .master = &omap2430_l4_core_hwmod,
.slave = &omap2430_timer12_hwmod, .slave = &omap2430_timer12_hwmod,
.clk = "gpt12_ick", .clk = "gpt12_ick",
.addr = omap2430_timer12_addrs, .addr = omap2xxx_timer12_addrs,
.addr_cnt = ARRAY_SIZE(omap2430_timer12_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -1041,8 +783,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer12_slaves[] = { ...@@ -1041,8 +783,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer12_slaves[] = {
/* timer12 hwmod */ /* timer12 hwmod */
static struct omap_hwmod omap2430_timer12_hwmod = { static struct omap_hwmod omap2430_timer12_hwmod = {
.name = "timer12", .name = "timer12",
.mpu_irqs = omap2430_timer12_mpu_irqs, .mpu_irqs = omap2xxx_timer12_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer12_mpu_irqs),
.main_clk = "gpt12_fck", .main_clk = "gpt12_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1055,7 +796,7 @@ static struct omap_hwmod omap2430_timer12_hwmod = { ...@@ -1055,7 +796,7 @@ static struct omap_hwmod omap2430_timer12_hwmod = {
}, },
.slaves = omap2430_timer12_slaves, .slaves = omap2430_timer12_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_timer12_slaves), .slaves_cnt = ARRAY_SIZE(omap2430_timer12_slaves),
.class = &omap2430_timer_hwmod_class, .class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
}; };
...@@ -1066,6 +807,7 @@ static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = { ...@@ -1066,6 +807,7 @@ static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
.pa_end = 0x4901607f, .pa_end = 0x4901607f,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = { static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
...@@ -1073,31 +815,9 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = { ...@@ -1073,31 +815,9 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
.slave = &omap2430_wd_timer2_hwmod, .slave = &omap2430_wd_timer2_hwmod,
.clk = "mpu_wdt_ick", .clk = "mpu_wdt_ick",
.addr = omap2430_wd_timer2_addrs, .addr = omap2430_wd_timer2_addrs,
.addr_cnt = ARRAY_SIZE(omap2430_wd_timer2_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/*
* 'wd_timer' class
* 32-bit watchdog upward counter that generates a pulse on the reset pin on
* overflow condition
*/
static struct omap_hwmod_class_sysconfig omap2430_wd_timer_sysc = {
.rev_offs = 0x0,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap2430_wd_timer_hwmod_class = {
.name = "wd_timer",
.sysc = &omap2430_wd_timer_sysc,
.pre_shutdown = &omap2_wd_timer_disable
};
/* wd_timer2 */ /* wd_timer2 */
static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = { static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = {
&omap2430_l4_wkup__wd_timer2, &omap2430_l4_wkup__wd_timer2,
...@@ -1105,7 +825,7 @@ static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = { ...@@ -1105,7 +825,7 @@ static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = {
static struct omap_hwmod omap2430_wd_timer2_hwmod = { static struct omap_hwmod omap2430_wd_timer2_hwmod = {
.name = "wd_timer2", .name = "wd_timer2",
.class = &omap2430_wd_timer_hwmod_class, .class = &omap2xxx_wd_timer_hwmod_class,
.main_clk = "mpu_wdt_fck", .main_clk = "mpu_wdt_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1121,45 +841,16 @@ static struct omap_hwmod omap2430_wd_timer2_hwmod = { ...@@ -1121,45 +841,16 @@ static struct omap_hwmod omap2430_wd_timer2_hwmod = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
}; };
/* UART */
static struct omap_hwmod_class_sysconfig uart_sysc = {
.rev_offs = 0x50,
.sysc_offs = 0x54,
.syss_offs = 0x58,
.sysc_flags = (SYSC_HAS_SIDLEMODE |
SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class uart_class = {
.name = "uart",
.sysc = &uart_sysc,
};
/* UART1 */ /* UART1 */
static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
{ .irq = INT_24XX_UART1_IRQ, },
};
static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
{ .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
{ .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
};
static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = { static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = {
&omap2_l4_core__uart1, &omap2_l4_core__uart1,
}; };
static struct omap_hwmod omap2430_uart1_hwmod = { static struct omap_hwmod omap2430_uart1_hwmod = {
.name = "uart1", .name = "uart1",
.mpu_irqs = uart1_mpu_irqs, .mpu_irqs = omap2_uart1_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs), .sdma_reqs = omap2_uart1_sdma_reqs,
.sdma_reqs = uart1_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs),
.main_clk = "uart1_fck", .main_clk = "uart1_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1172,31 +863,20 @@ static struct omap_hwmod omap2430_uart1_hwmod = { ...@@ -1172,31 +863,20 @@ static struct omap_hwmod omap2430_uart1_hwmod = {
}, },
.slaves = omap2430_uart1_slaves, .slaves = omap2430_uart1_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_uart1_slaves), .slaves_cnt = ARRAY_SIZE(omap2430_uart1_slaves),
.class = &uart_class, .class = &omap2_uart_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
}; };
/* UART2 */ /* UART2 */
static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
{ .irq = INT_24XX_UART2_IRQ, },
};
static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
{ .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
{ .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
};
static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = { static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = {
&omap2_l4_core__uart2, &omap2_l4_core__uart2,
}; };
static struct omap_hwmod omap2430_uart2_hwmod = { static struct omap_hwmod omap2430_uart2_hwmod = {
.name = "uart2", .name = "uart2",
.mpu_irqs = uart2_mpu_irqs, .mpu_irqs = omap2_uart2_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs), .sdma_reqs = omap2_uart2_sdma_reqs,
.sdma_reqs = uart2_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs),
.main_clk = "uart2_fck", .main_clk = "uart2_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1209,31 +889,20 @@ static struct omap_hwmod omap2430_uart2_hwmod = { ...@@ -1209,31 +889,20 @@ static struct omap_hwmod omap2430_uart2_hwmod = {
}, },
.slaves = omap2430_uart2_slaves, .slaves = omap2430_uart2_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_uart2_slaves), .slaves_cnt = ARRAY_SIZE(omap2430_uart2_slaves),
.class = &uart_class, .class = &omap2_uart_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
}; };
/* UART3 */ /* UART3 */
static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
{ .irq = INT_24XX_UART3_IRQ, },
};
static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
{ .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
{ .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
};
static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = { static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = {
&omap2_l4_core__uart3, &omap2_l4_core__uart3,
}; };
static struct omap_hwmod omap2430_uart3_hwmod = { static struct omap_hwmod omap2430_uart3_hwmod = {
.name = "uart3", .name = "uart3",
.mpu_irqs = uart3_mpu_irqs, .mpu_irqs = omap2_uart3_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs), .sdma_reqs = omap2_uart3_sdma_reqs,
.sdma_reqs = uart3_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs),
.main_clk = "uart3_fck", .main_clk = "uart3_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1246,53 +915,22 @@ static struct omap_hwmod omap2430_uart3_hwmod = { ...@@ -1246,53 +915,22 @@ static struct omap_hwmod omap2430_uart3_hwmod = {
}, },
.slaves = omap2430_uart3_slaves, .slaves = omap2430_uart3_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_uart3_slaves), .slaves_cnt = ARRAY_SIZE(omap2430_uart3_slaves),
.class = &uart_class, .class = &omap2_uart_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
}; };
/*
* 'dss' class
* display sub-system
*/
static struct omap_hwmod_class_sysconfig omap2430_dss_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap2430_dss_hwmod_class = {
.name = "dss",
.sysc = &omap2430_dss_sysc,
};
static struct omap_hwmod_dma_info omap2430_dss_sdma_chs[] = {
{ .name = "dispc", .dma_req = 5 },
};
/* dss */ /* dss */
/* dss master ports */ /* dss master ports */
static struct omap_hwmod_ocp_if *omap2430_dss_masters[] = { static struct omap_hwmod_ocp_if *omap2430_dss_masters[] = {
&omap2430_dss__l3, &omap2430_dss__l3,
}; };
static struct omap_hwmod_addr_space omap2430_dss_addrs[] = {
{
.pa_start = 0x48050000,
.pa_end = 0x480503FF,
.flags = ADDR_TYPE_RT
},
};
/* l4_core -> dss */ /* l4_core -> dss */
static struct omap_hwmod_ocp_if omap2430_l4_core__dss = { static struct omap_hwmod_ocp_if omap2430_l4_core__dss = {
.master = &omap2430_l4_core_hwmod, .master = &omap2430_l4_core_hwmod,
.slave = &omap2430_dss_core_hwmod, .slave = &omap2430_dss_core_hwmod,
.clk = "dss_ick", .clk = "dss_ick",
.addr = omap2430_dss_addrs, .addr = omap2_dss_addrs,
.addr_cnt = ARRAY_SIZE(omap2430_dss_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -1308,10 +946,9 @@ static struct omap_hwmod_opt_clk dss_opt_clks[] = { ...@@ -1308,10 +946,9 @@ static struct omap_hwmod_opt_clk dss_opt_clks[] = {
static struct omap_hwmod omap2430_dss_core_hwmod = { static struct omap_hwmod omap2430_dss_core_hwmod = {
.name = "dss_core", .name = "dss_core",
.class = &omap2430_dss_hwmod_class, .class = &omap2_dss_hwmod_class,
.main_clk = "dss1_fck", /* instead of dss_fck */ .main_clk = "dss1_fck", /* instead of dss_fck */
.sdma_reqs = omap2430_dss_sdma_chs, .sdma_reqs = omap2xxx_dss_sdma_chs,
.sdma_reqs_cnt = ARRAY_SIZE(omap2430_dss_sdma_chs),
.prcm = { .prcm = {
.omap2 = { .omap2 = {
.prcm_reg_id = 1, .prcm_reg_id = 1,
...@@ -1331,46 +968,12 @@ static struct omap_hwmod omap2430_dss_core_hwmod = { ...@@ -1331,46 +968,12 @@ static struct omap_hwmod omap2430_dss_core_hwmod = {
.flags = HWMOD_NO_IDLEST, .flags = HWMOD_NO_IDLEST,
}; };
/*
* 'dispc' class
* display controller
*/
static struct omap_hwmod_class_sysconfig omap2430_dispc_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap2430_dispc_hwmod_class = {
.name = "dispc",
.sysc = &omap2430_dispc_sysc,
};
static struct omap_hwmod_irq_info omap2430_dispc_irqs[] = {
{ .irq = 25 },
};
static struct omap_hwmod_addr_space omap2430_dss_dispc_addrs[] = {
{
.pa_start = 0x48050400,
.pa_end = 0x480507FF,
.flags = ADDR_TYPE_RT
},
};
/* l4_core -> dss_dispc */ /* l4_core -> dss_dispc */
static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = { static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = {
.master = &omap2430_l4_core_hwmod, .master = &omap2430_l4_core_hwmod,
.slave = &omap2430_dss_dispc_hwmod, .slave = &omap2430_dss_dispc_hwmod,
.clk = "dss_ick", .clk = "dss_ick",
.addr = omap2430_dss_dispc_addrs, .addr = omap2_dss_dispc_addrs,
.addr_cnt = ARRAY_SIZE(omap2430_dss_dispc_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -1381,9 +984,8 @@ static struct omap_hwmod_ocp_if *omap2430_dss_dispc_slaves[] = { ...@@ -1381,9 +984,8 @@ static struct omap_hwmod_ocp_if *omap2430_dss_dispc_slaves[] = {
static struct omap_hwmod omap2430_dss_dispc_hwmod = { static struct omap_hwmod omap2430_dss_dispc_hwmod = {
.name = "dss_dispc", .name = "dss_dispc",
.class = &omap2430_dispc_hwmod_class, .class = &omap2_dispc_hwmod_class,
.mpu_irqs = omap2430_dispc_irqs, .mpu_irqs = omap2_dispc_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_dispc_irqs),
.main_clk = "dss1_fck", .main_clk = "dss1_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1400,41 +1002,12 @@ static struct omap_hwmod omap2430_dss_dispc_hwmod = { ...@@ -1400,41 +1002,12 @@ static struct omap_hwmod omap2430_dss_dispc_hwmod = {
.flags = HWMOD_NO_IDLEST, .flags = HWMOD_NO_IDLEST,
}; };
/*
* 'rfbi' class
* remote frame buffer interface
*/
static struct omap_hwmod_class_sysconfig omap2430_rfbi_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
SYSC_HAS_AUTOIDLE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap2430_rfbi_hwmod_class = {
.name = "rfbi",
.sysc = &omap2430_rfbi_sysc,
};
static struct omap_hwmod_addr_space omap2430_dss_rfbi_addrs[] = {
{
.pa_start = 0x48050800,
.pa_end = 0x48050BFF,
.flags = ADDR_TYPE_RT
},
};
/* l4_core -> dss_rfbi */ /* l4_core -> dss_rfbi */
static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = { static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = {
.master = &omap2430_l4_core_hwmod, .master = &omap2430_l4_core_hwmod,
.slave = &omap2430_dss_rfbi_hwmod, .slave = &omap2430_dss_rfbi_hwmod,
.clk = "dss_ick", .clk = "dss_ick",
.addr = omap2430_dss_rfbi_addrs, .addr = omap2_dss_rfbi_addrs,
.addr_cnt = ARRAY_SIZE(omap2430_dss_rfbi_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -1445,7 +1018,7 @@ static struct omap_hwmod_ocp_if *omap2430_dss_rfbi_slaves[] = { ...@@ -1445,7 +1018,7 @@ static struct omap_hwmod_ocp_if *omap2430_dss_rfbi_slaves[] = {
static struct omap_hwmod omap2430_dss_rfbi_hwmod = { static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
.name = "dss_rfbi", .name = "dss_rfbi",
.class = &omap2430_rfbi_hwmod_class, .class = &omap2_rfbi_hwmod_class,
.main_clk = "dss1_fck", .main_clk = "dss1_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1460,31 +1033,12 @@ static struct omap_hwmod omap2430_dss_rfbi_hwmod = { ...@@ -1460,31 +1033,12 @@ static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
.flags = HWMOD_NO_IDLEST, .flags = HWMOD_NO_IDLEST,
}; };
/*
* 'venc' class
* video encoder
*/
static struct omap_hwmod_class omap2430_venc_hwmod_class = {
.name = "venc",
};
/* dss_venc */
static struct omap_hwmod_addr_space omap2430_dss_venc_addrs[] = {
{
.pa_start = 0x48050C00,
.pa_end = 0x48050FFF,
.flags = ADDR_TYPE_RT
},
};
/* l4_core -> dss_venc */ /* l4_core -> dss_venc */
static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = { static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = {
.master = &omap2430_l4_core_hwmod, .master = &omap2430_l4_core_hwmod,
.slave = &omap2430_dss_venc_hwmod, .slave = &omap2430_dss_venc_hwmod,
.clk = "dss_54m_fck", .clk = "dss_54m_fck",
.addr = omap2430_dss_venc_addrs, .addr = omap2_dss_venc_addrs,
.addr_cnt = ARRAY_SIZE(omap2430_dss_venc_addrs),
.flags = OCPIF_SWSUP_IDLE, .flags = OCPIF_SWSUP_IDLE,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -1496,7 +1050,7 @@ static struct omap_hwmod_ocp_if *omap2430_dss_venc_slaves[] = { ...@@ -1496,7 +1050,7 @@ static struct omap_hwmod_ocp_if *omap2430_dss_venc_slaves[] = {
static struct omap_hwmod omap2430_dss_venc_hwmod = { static struct omap_hwmod omap2430_dss_venc_hwmod = {
.name = "dss_venc", .name = "dss_venc",
.class = &omap2430_venc_hwmod_class, .class = &omap2_venc_hwmod_class,
.main_clk = "dss1_fck", .main_clk = "dss1_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1532,25 +1086,14 @@ static struct omap_i2c_dev_attr i2c_dev_attr = { ...@@ -1532,25 +1086,14 @@ static struct omap_i2c_dev_attr i2c_dev_attr = {
/* I2C1 */ /* I2C1 */
static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
{ .irq = INT_24XX_I2C1_IRQ, },
};
static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
};
static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = { static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = {
&omap2430_l4_core__i2c1, &omap2430_l4_core__i2c1,
}; };
static struct omap_hwmod omap2430_i2c1_hwmod = { static struct omap_hwmod omap2430_i2c1_hwmod = {
.name = "i2c1", .name = "i2c1",
.mpu_irqs = i2c1_mpu_irqs, .mpu_irqs = omap2_i2c1_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs), .sdma_reqs = omap2_i2c1_sdma_reqs,
.sdma_reqs = i2c1_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
.main_clk = "i2chs1_fck", .main_clk = "i2chs1_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1578,25 +1121,14 @@ static struct omap_hwmod omap2430_i2c1_hwmod = { ...@@ -1578,25 +1121,14 @@ static struct omap_hwmod omap2430_i2c1_hwmod = {
/* I2C2 */ /* I2C2 */
static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
{ .irq = INT_24XX_I2C2_IRQ, },
};
static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
};
static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = { static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = {
&omap2430_l4_core__i2c2, &omap2430_l4_core__i2c2,
}; };
static struct omap_hwmod omap2430_i2c2_hwmod = { static struct omap_hwmod omap2430_i2c2_hwmod = {
.name = "i2c2", .name = "i2c2",
.mpu_irqs = i2c2_mpu_irqs, .mpu_irqs = omap2_i2c2_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs), .sdma_reqs = omap2_i2c2_sdma_reqs,
.sdma_reqs = i2c2_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
.main_clk = "i2chs2_fck", .main_clk = "i2chs2_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1621,6 +1153,7 @@ static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = { ...@@ -1621,6 +1153,7 @@ static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = {
.pa_end = 0x4900C1ff, .pa_end = 0x4900C1ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = { static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
...@@ -1628,7 +1161,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = { ...@@ -1628,7 +1161,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
.slave = &omap2430_gpio1_hwmod, .slave = &omap2430_gpio1_hwmod,
.clk = "gpios_ick", .clk = "gpios_ick",
.addr = omap2430_gpio1_addr_space, .addr = omap2430_gpio1_addr_space,
.addr_cnt = ARRAY_SIZE(omap2430_gpio1_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -1639,6 +1171,7 @@ static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = { ...@@ -1639,6 +1171,7 @@ static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = {
.pa_end = 0x4900E1ff, .pa_end = 0x4900E1ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = { static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
...@@ -1646,7 +1179,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = { ...@@ -1646,7 +1179,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
.slave = &omap2430_gpio2_hwmod, .slave = &omap2430_gpio2_hwmod,
.clk = "gpios_ick", .clk = "gpios_ick",
.addr = omap2430_gpio2_addr_space, .addr = omap2430_gpio2_addr_space,
.addr_cnt = ARRAY_SIZE(omap2430_gpio2_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -1657,6 +1189,7 @@ static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = { ...@@ -1657,6 +1189,7 @@ static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = {
.pa_end = 0x490101ff, .pa_end = 0x490101ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = { static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
...@@ -1664,7 +1197,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = { ...@@ -1664,7 +1197,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
.slave = &omap2430_gpio3_hwmod, .slave = &omap2430_gpio3_hwmod,
.clk = "gpios_ick", .clk = "gpios_ick",
.addr = omap2430_gpio3_addr_space, .addr = omap2430_gpio3_addr_space,
.addr_cnt = ARRAY_SIZE(omap2430_gpio3_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -1675,6 +1207,7 @@ static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = { ...@@ -1675,6 +1207,7 @@ static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = {
.pa_end = 0x490121ff, .pa_end = 0x490121ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = { static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
...@@ -1682,7 +1215,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = { ...@@ -1682,7 +1215,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
.slave = &omap2430_gpio4_hwmod, .slave = &omap2430_gpio4_hwmod,
.clk = "gpios_ick", .clk = "gpios_ick",
.addr = omap2430_gpio4_addr_space, .addr = omap2430_gpio4_addr_space,
.addr_cnt = ARRAY_SIZE(omap2430_gpio4_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -1693,6 +1225,7 @@ static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = { ...@@ -1693,6 +1225,7 @@ static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = {
.pa_end = 0x480B61ff, .pa_end = 0x480B61ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = { static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
...@@ -1700,7 +1233,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = { ...@@ -1700,7 +1233,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
.slave = &omap2430_gpio5_hwmod, .slave = &omap2430_gpio5_hwmod,
.clk = "gpio5_ick", .clk = "gpio5_ick",
.addr = omap2430_gpio5_addr_space, .addr = omap2430_gpio5_addr_space,
.addr_cnt = ARRAY_SIZE(omap2430_gpio5_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -1710,32 +1242,7 @@ static struct omap_gpio_dev_attr gpio_dev_attr = { ...@@ -1710,32 +1242,7 @@ static struct omap_gpio_dev_attr gpio_dev_attr = {
.dbck_flag = false, .dbck_flag = false,
}; };
static struct omap_hwmod_class_sysconfig omap243x_gpio_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
/*
* 'gpio' class
* general purpose io module
*/
static struct omap_hwmod_class omap243x_gpio_hwmod_class = {
.name = "gpio",
.sysc = &omap243x_gpio_sysc,
.rev = 0,
};
/* gpio1 */ /* gpio1 */
static struct omap_hwmod_irq_info omap243x_gpio1_irqs[] = {
{ .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
};
static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = { static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = {
&omap2430_l4_wkup__gpio1, &omap2430_l4_wkup__gpio1,
}; };
...@@ -1743,8 +1250,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = { ...@@ -1743,8 +1250,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = {
static struct omap_hwmod omap2430_gpio1_hwmod = { static struct omap_hwmod omap2430_gpio1_hwmod = {
.name = "gpio1", .name = "gpio1",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap243x_gpio1_irqs, .mpu_irqs = omap2_gpio1_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio1_irqs),
.main_clk = "gpios_fck", .main_clk = "gpios_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1757,16 +1263,12 @@ static struct omap_hwmod omap2430_gpio1_hwmod = { ...@@ -1757,16 +1263,12 @@ static struct omap_hwmod omap2430_gpio1_hwmod = {
}, },
.slaves = omap2430_gpio1_slaves, .slaves = omap2430_gpio1_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_gpio1_slaves), .slaves_cnt = ARRAY_SIZE(omap2430_gpio1_slaves),
.class = &omap243x_gpio_hwmod_class, .class = &omap2xxx_gpio_hwmod_class,
.dev_attr = &gpio_dev_attr, .dev_attr = &gpio_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
}; };
/* gpio2 */ /* gpio2 */
static struct omap_hwmod_irq_info omap243x_gpio2_irqs[] = {
{ .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
};
static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = { static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = {
&omap2430_l4_wkup__gpio2, &omap2430_l4_wkup__gpio2,
}; };
...@@ -1774,8 +1276,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = { ...@@ -1774,8 +1276,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = {
static struct omap_hwmod omap2430_gpio2_hwmod = { static struct omap_hwmod omap2430_gpio2_hwmod = {
.name = "gpio2", .name = "gpio2",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap243x_gpio2_irqs, .mpu_irqs = omap2_gpio2_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio2_irqs),
.main_clk = "gpios_fck", .main_clk = "gpios_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1788,16 +1289,12 @@ static struct omap_hwmod omap2430_gpio2_hwmod = { ...@@ -1788,16 +1289,12 @@ static struct omap_hwmod omap2430_gpio2_hwmod = {
}, },
.slaves = omap2430_gpio2_slaves, .slaves = omap2430_gpio2_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_gpio2_slaves), .slaves_cnt = ARRAY_SIZE(omap2430_gpio2_slaves),
.class = &omap243x_gpio_hwmod_class, .class = &omap2xxx_gpio_hwmod_class,
.dev_attr = &gpio_dev_attr, .dev_attr = &gpio_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
}; };
/* gpio3 */ /* gpio3 */
static struct omap_hwmod_irq_info omap243x_gpio3_irqs[] = {
{ .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
};
static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = { static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = {
&omap2430_l4_wkup__gpio3, &omap2430_l4_wkup__gpio3,
}; };
...@@ -1805,8 +1302,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = { ...@@ -1805,8 +1302,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = {
static struct omap_hwmod omap2430_gpio3_hwmod = { static struct omap_hwmod omap2430_gpio3_hwmod = {
.name = "gpio3", .name = "gpio3",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap243x_gpio3_irqs, .mpu_irqs = omap2_gpio3_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio3_irqs),
.main_clk = "gpios_fck", .main_clk = "gpios_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1819,16 +1315,12 @@ static struct omap_hwmod omap2430_gpio3_hwmod = { ...@@ -1819,16 +1315,12 @@ static struct omap_hwmod omap2430_gpio3_hwmod = {
}, },
.slaves = omap2430_gpio3_slaves, .slaves = omap2430_gpio3_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_gpio3_slaves), .slaves_cnt = ARRAY_SIZE(omap2430_gpio3_slaves),
.class = &omap243x_gpio_hwmod_class, .class = &omap2xxx_gpio_hwmod_class,
.dev_attr = &gpio_dev_attr, .dev_attr = &gpio_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
}; };
/* gpio4 */ /* gpio4 */
static struct omap_hwmod_irq_info omap243x_gpio4_irqs[] = {
{ .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
};
static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = { static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = {
&omap2430_l4_wkup__gpio4, &omap2430_l4_wkup__gpio4,
}; };
...@@ -1836,8 +1328,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = { ...@@ -1836,8 +1328,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = {
static struct omap_hwmod omap2430_gpio4_hwmod = { static struct omap_hwmod omap2430_gpio4_hwmod = {
.name = "gpio4", .name = "gpio4",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap243x_gpio4_irqs, .mpu_irqs = omap2_gpio4_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio4_irqs),
.main_clk = "gpios_fck", .main_clk = "gpios_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1850,7 +1341,7 @@ static struct omap_hwmod omap2430_gpio4_hwmod = { ...@@ -1850,7 +1341,7 @@ static struct omap_hwmod omap2430_gpio4_hwmod = {
}, },
.slaves = omap2430_gpio4_slaves, .slaves = omap2430_gpio4_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_gpio4_slaves), .slaves_cnt = ARRAY_SIZE(omap2430_gpio4_slaves),
.class = &omap243x_gpio_hwmod_class, .class = &omap2xxx_gpio_hwmod_class,
.dev_attr = &gpio_dev_attr, .dev_attr = &gpio_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
}; };
...@@ -1858,6 +1349,7 @@ static struct omap_hwmod omap2430_gpio4_hwmod = { ...@@ -1858,6 +1349,7 @@ static struct omap_hwmod omap2430_gpio4_hwmod = {
/* gpio5 */ /* gpio5 */
static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = { static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = {
{ .irq = 33 }, /* INT_24XX_GPIO_BANK5 */ { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */
{ .irq = -1 }
}; };
static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = { static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = {
...@@ -1868,7 +1360,6 @@ static struct omap_hwmod omap2430_gpio5_hwmod = { ...@@ -1868,7 +1360,6 @@ static struct omap_hwmod omap2430_gpio5_hwmod = {
.name = "gpio5", .name = "gpio5",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap243x_gpio5_irqs, .mpu_irqs = omap243x_gpio5_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio5_irqs),
.main_clk = "gpio5_fck", .main_clk = "gpio5_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1881,28 +1372,11 @@ static struct omap_hwmod omap2430_gpio5_hwmod = { ...@@ -1881,28 +1372,11 @@ static struct omap_hwmod omap2430_gpio5_hwmod = {
}, },
.slaves = omap2430_gpio5_slaves, .slaves = omap2430_gpio5_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_gpio5_slaves), .slaves_cnt = ARRAY_SIZE(omap2430_gpio5_slaves),
.class = &omap243x_gpio_hwmod_class, .class = &omap2xxx_gpio_hwmod_class,
.dev_attr = &gpio_dev_attr, .dev_attr = &gpio_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
}; };
/* dma_system */
static struct omap_hwmod_class_sysconfig omap2430_dma_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x002c,
.syss_offs = 0x0028,
.sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
.idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap2430_dma_hwmod_class = {
.name = "dma",
.sysc = &omap2430_dma_sysc,
};
/* dma attributes */ /* dma attributes */
static struct omap_dma_dev_attr dma_dev_attr = { static struct omap_dma_dev_attr dma_dev_attr = {
.dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
...@@ -1910,21 +1384,6 @@ static struct omap_dma_dev_attr dma_dev_attr = { ...@@ -1910,21 +1384,6 @@ static struct omap_dma_dev_attr dma_dev_attr = {
.lch_count = 32, .lch_count = 32,
}; };
static struct omap_hwmod_irq_info omap2430_dma_system_irqs[] = {
{ .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
{ .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
{ .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
{ .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
};
static struct omap_hwmod_addr_space omap2430_dma_system_addrs[] = {
{
.pa_start = 0x48056000,
.pa_end = 0x48056fff,
.flags = ADDR_TYPE_RT
},
};
/* dma_system -> L3 */ /* dma_system -> L3 */
static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = { static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = {
.master = &omap2430_dma_system_hwmod, .master = &omap2430_dma_system_hwmod,
...@@ -1943,8 +1402,7 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = { ...@@ -1943,8 +1402,7 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
.master = &omap2430_l4_core_hwmod, .master = &omap2430_l4_core_hwmod,
.slave = &omap2430_dma_system_hwmod, .slave = &omap2430_dma_system_hwmod,
.clk = "sdma_ick", .clk = "sdma_ick",
.addr = omap2430_dma_system_addrs, .addr = omap2_dma_system_addrs,
.addr_cnt = ARRAY_SIZE(omap2430_dma_system_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -1955,9 +1413,8 @@ static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = { ...@@ -1955,9 +1413,8 @@ static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = {
static struct omap_hwmod omap2430_dma_system_hwmod = { static struct omap_hwmod omap2430_dma_system_hwmod = {
.name = "dma", .name = "dma",
.class = &omap2430_dma_hwmod_class, .class = &omap2xxx_dma_hwmod_class,
.mpu_irqs = omap2430_dma_system_irqs, .mpu_irqs = omap2_dma_system_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_dma_system_irqs),
.main_clk = "core_l3_ck", .main_clk = "core_l3_ck",
.slaves = omap2430_dma_system_slaves, .slaves = omap2430_dma_system_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_dma_system_slaves), .slaves_cnt = ARRAY_SIZE(omap2430_dma_system_slaves),
...@@ -1968,47 +1425,18 @@ static struct omap_hwmod omap2430_dma_system_hwmod = { ...@@ -1968,47 +1425,18 @@ static struct omap_hwmod omap2430_dma_system_hwmod = {
.flags = HWMOD_NO_IDLEST, .flags = HWMOD_NO_IDLEST,
}; };
/*
* 'mailbox' class
* mailbox module allowing communication between the on-chip processors
* using a queued mailbox-interrupt mechanism.
*/
static struct omap_hwmod_class_sysconfig omap2430_mailbox_sysc = {
.rev_offs = 0x000,
.sysc_offs = 0x010,
.syss_offs = 0x014,
.sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap2430_mailbox_hwmod_class = {
.name = "mailbox",
.sysc = &omap2430_mailbox_sysc,
};
/* mailbox */ /* mailbox */
static struct omap_hwmod omap2430_mailbox_hwmod; static struct omap_hwmod omap2430_mailbox_hwmod;
static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = { static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
{ .irq = 26 }, { .irq = 26 },
}; { .irq = -1 }
static struct omap_hwmod_addr_space omap2430_mailbox_addrs[] = {
{
.pa_start = 0x48094000,
.pa_end = 0x480941ff,
.flags = ADDR_TYPE_RT,
},
}; };
/* l4_core -> mailbox */ /* l4_core -> mailbox */
static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = { static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
.master = &omap2430_l4_core_hwmod, .master = &omap2430_l4_core_hwmod,
.slave = &omap2430_mailbox_hwmod, .slave = &omap2430_mailbox_hwmod,
.addr = omap2430_mailbox_addrs, .addr = omap2_mailbox_addrs,
.addr_cnt = ARRAY_SIZE(omap2430_mailbox_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -2019,9 +1447,8 @@ static struct omap_hwmod_ocp_if *omap2430_mailbox_slaves[] = { ...@@ -2019,9 +1447,8 @@ static struct omap_hwmod_ocp_if *omap2430_mailbox_slaves[] = {
static struct omap_hwmod omap2430_mailbox_hwmod = { static struct omap_hwmod omap2430_mailbox_hwmod = {
.name = "mailbox", .name = "mailbox",
.class = &omap2430_mailbox_hwmod_class, .class = &omap2xxx_mailbox_hwmod_class,
.mpu_irqs = omap2430_mailbox_irqs, .mpu_irqs = omap2430_mailbox_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_mailbox_irqs),
.main_clk = "mailboxes_ick", .main_clk = "mailboxes_ick",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -2037,45 +1464,7 @@ static struct omap_hwmod omap2430_mailbox_hwmod = { ...@@ -2037,45 +1464,7 @@ static struct omap_hwmod omap2430_mailbox_hwmod = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
}; };
/*
* 'mcspi' class
* multichannel serial port interface (mcspi) / master/slave synchronous serial
* bus
*/
static struct omap_hwmod_class_sysconfig omap2430_mcspi_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap2430_mcspi_class = {
.name = "mcspi",
.sysc = &omap2430_mcspi_sysc,
.rev = OMAP2_MCSPI_REV,
};
/* mcspi1 */ /* mcspi1 */
static struct omap_hwmod_irq_info omap2430_mcspi1_mpu_irqs[] = {
{ .irq = 65 },
};
static struct omap_hwmod_dma_info omap2430_mcspi1_sdma_reqs[] = {
{ .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
{ .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
{ .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
{ .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
{ .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
{ .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
{ .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
{ .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
};
static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = { static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = {
&omap2430_l4_core__mcspi1, &omap2430_l4_core__mcspi1,
}; };
...@@ -2086,10 +1475,8 @@ static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { ...@@ -2086,10 +1475,8 @@ static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
static struct omap_hwmod omap2430_mcspi1_hwmod = { static struct omap_hwmod omap2430_mcspi1_hwmod = {
.name = "mcspi1_hwmod", .name = "mcspi1_hwmod",
.mpu_irqs = omap2430_mcspi1_mpu_irqs, .mpu_irqs = omap2_mcspi1_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi1_mpu_irqs), .sdma_reqs = omap2_mcspi1_sdma_reqs,
.sdma_reqs = omap2430_mcspi1_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi1_sdma_reqs),
.main_clk = "mcspi1_fck", .main_clk = "mcspi1_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -2102,23 +1489,12 @@ static struct omap_hwmod omap2430_mcspi1_hwmod = { ...@@ -2102,23 +1489,12 @@ static struct omap_hwmod omap2430_mcspi1_hwmod = {
}, },
.slaves = omap2430_mcspi1_slaves, .slaves = omap2430_mcspi1_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_mcspi1_slaves), .slaves_cnt = ARRAY_SIZE(omap2430_mcspi1_slaves),
.class = &omap2430_mcspi_class, .class = &omap2xxx_mcspi_class,
.dev_attr = &omap_mcspi1_dev_attr, .dev_attr = &omap_mcspi1_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
}; };
/* mcspi2 */ /* mcspi2 */
static struct omap_hwmod_irq_info omap2430_mcspi2_mpu_irqs[] = {
{ .irq = 66 },
};
static struct omap_hwmod_dma_info omap2430_mcspi2_sdma_reqs[] = {
{ .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
{ .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
{ .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
{ .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
};
static struct omap_hwmod_ocp_if *omap2430_mcspi2_slaves[] = { static struct omap_hwmod_ocp_if *omap2430_mcspi2_slaves[] = {
&omap2430_l4_core__mcspi2, &omap2430_l4_core__mcspi2,
}; };
...@@ -2129,10 +1505,8 @@ static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { ...@@ -2129,10 +1505,8 @@ static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
static struct omap_hwmod omap2430_mcspi2_hwmod = { static struct omap_hwmod omap2430_mcspi2_hwmod = {
.name = "mcspi2_hwmod", .name = "mcspi2_hwmod",
.mpu_irqs = omap2430_mcspi2_mpu_irqs, .mpu_irqs = omap2_mcspi2_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi2_mpu_irqs), .sdma_reqs = omap2_mcspi2_sdma_reqs,
.sdma_reqs = omap2430_mcspi2_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi2_sdma_reqs),
.main_clk = "mcspi2_fck", .main_clk = "mcspi2_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -2145,14 +1519,15 @@ static struct omap_hwmod omap2430_mcspi2_hwmod = { ...@@ -2145,14 +1519,15 @@ static struct omap_hwmod omap2430_mcspi2_hwmod = {
}, },
.slaves = omap2430_mcspi2_slaves, .slaves = omap2430_mcspi2_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_mcspi2_slaves), .slaves_cnt = ARRAY_SIZE(omap2430_mcspi2_slaves),
.class = &omap2430_mcspi_class, .class = &omap2xxx_mcspi_class,
.dev_attr = &omap_mcspi2_dev_attr, .dev_attr = &omap_mcspi2_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
}; };
/* mcspi3 */ /* mcspi3 */
static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = { static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = {
{ .irq = 91 }, { .irq = 91 },
{ .irq = -1 }
}; };
static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = { static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = {
...@@ -2160,6 +1535,7 @@ static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = { ...@@ -2160,6 +1535,7 @@ static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = {
{ .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */ { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */
{ .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */ { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */
{ .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */ { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */
{ .dma_req = -1 }
}; };
static struct omap_hwmod_ocp_if *omap2430_mcspi3_slaves[] = { static struct omap_hwmod_ocp_if *omap2430_mcspi3_slaves[] = {
...@@ -2173,9 +1549,7 @@ static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { ...@@ -2173,9 +1549,7 @@ static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
static struct omap_hwmod omap2430_mcspi3_hwmod = { static struct omap_hwmod omap2430_mcspi3_hwmod = {
.name = "mcspi3_hwmod", .name = "mcspi3_hwmod",
.mpu_irqs = omap2430_mcspi3_mpu_irqs, .mpu_irqs = omap2430_mcspi3_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi3_mpu_irqs),
.sdma_reqs = omap2430_mcspi3_sdma_reqs, .sdma_reqs = omap2430_mcspi3_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi3_sdma_reqs),
.main_clk = "mcspi3_fck", .main_clk = "mcspi3_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -2188,8 +1562,8 @@ static struct omap_hwmod omap2430_mcspi3_hwmod = { ...@@ -2188,8 +1562,8 @@ static struct omap_hwmod omap2430_mcspi3_hwmod = {
}, },
.slaves = omap2430_mcspi3_slaves, .slaves = omap2430_mcspi3_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_mcspi3_slaves), .slaves_cnt = ARRAY_SIZE(omap2430_mcspi3_slaves),
.class = &omap2430_mcspi_class, .class = &omap2xxx_mcspi_class,
.dev_attr = &omap_mcspi3_dev_attr, .dev_attr = &omap_mcspi3_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
}; };
...@@ -2218,12 +1592,12 @@ static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = { ...@@ -2218,12 +1592,12 @@ static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = {
{ .name = "mc", .irq = 92 }, { .name = "mc", .irq = 92 },
{ .name = "dma", .irq = 93 }, { .name = "dma", .irq = 93 },
{ .irq = -1 }
}; };
static struct omap_hwmod omap2430_usbhsotg_hwmod = { static struct omap_hwmod omap2430_usbhsotg_hwmod = {
.name = "usb_otg_hs", .name = "usb_otg_hs",
.mpu_irqs = omap2430_usbhsotg_mpu_irqs, .mpu_irqs = omap2430_usbhsotg_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_usbhsotg_mpu_irqs),
.main_clk = "usbhs_ick", .main_clk = "usbhs_ick",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -2273,20 +1647,7 @@ static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = { ...@@ -2273,20 +1647,7 @@ static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = {
{ .name = "rx", .irq = 60 }, { .name = "rx", .irq = 60 },
{ .name = "ovr", .irq = 61 }, { .name = "ovr", .irq = 61 },
{ .name = "common", .irq = 64 }, { .name = "common", .irq = 64 },
}; { .irq = -1 }
static struct omap_hwmod_dma_info omap2430_mcbsp1_sdma_chs[] = {
{ .name = "rx", .dma_req = 32 },
{ .name = "tx", .dma_req = 31 },
};
static struct omap_hwmod_addr_space omap2430_mcbsp1_addrs[] = {
{
.name = "mpu",
.pa_start = 0x48074000,
.pa_end = 0x480740ff,
.flags = ADDR_TYPE_RT
},
}; };
/* l4_core -> mcbsp1 */ /* l4_core -> mcbsp1 */
...@@ -2294,8 +1655,7 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = { ...@@ -2294,8 +1655,7 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
.master = &omap2430_l4_core_hwmod, .master = &omap2430_l4_core_hwmod,
.slave = &omap2430_mcbsp1_hwmod, .slave = &omap2430_mcbsp1_hwmod,
.clk = "mcbsp1_ick", .clk = "mcbsp1_ick",
.addr = omap2430_mcbsp1_addrs, .addr = omap2_mcbsp1_addrs,
.addr_cnt = ARRAY_SIZE(omap2430_mcbsp1_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -2308,9 +1668,7 @@ static struct omap_hwmod omap2430_mcbsp1_hwmod = { ...@@ -2308,9 +1668,7 @@ static struct omap_hwmod omap2430_mcbsp1_hwmod = {
.name = "mcbsp1", .name = "mcbsp1",
.class = &omap2430_mcbsp_hwmod_class, .class = &omap2430_mcbsp_hwmod_class,
.mpu_irqs = omap2430_mcbsp1_irqs, .mpu_irqs = omap2430_mcbsp1_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp1_irqs), .sdma_reqs = omap2_mcbsp1_sdma_reqs,
.sdma_reqs = omap2430_mcbsp1_sdma_chs,
.sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp1_sdma_chs),
.main_clk = "mcbsp1_fck", .main_clk = "mcbsp1_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -2331,20 +1689,7 @@ static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = { ...@@ -2331,20 +1689,7 @@ static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = {
{ .name = "tx", .irq = 62 }, { .name = "tx", .irq = 62 },
{ .name = "rx", .irq = 63 }, { .name = "rx", .irq = 63 },
{ .name = "common", .irq = 16 }, { .name = "common", .irq = 16 },
}; { .irq = -1 }
static struct omap_hwmod_dma_info omap2430_mcbsp2_sdma_chs[] = {
{ .name = "rx", .dma_req = 34 },
{ .name = "tx", .dma_req = 33 },
};
static struct omap_hwmod_addr_space omap2430_mcbsp2_addrs[] = {
{
.name = "mpu",
.pa_start = 0x48076000,
.pa_end = 0x480760ff,
.flags = ADDR_TYPE_RT
},
}; };
/* l4_core -> mcbsp2 */ /* l4_core -> mcbsp2 */
...@@ -2352,8 +1697,7 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = { ...@@ -2352,8 +1697,7 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
.master = &omap2430_l4_core_hwmod, .master = &omap2430_l4_core_hwmod,
.slave = &omap2430_mcbsp2_hwmod, .slave = &omap2430_mcbsp2_hwmod,
.clk = "mcbsp2_ick", .clk = "mcbsp2_ick",
.addr = omap2430_mcbsp2_addrs, .addr = omap2xxx_mcbsp2_addrs,
.addr_cnt = ARRAY_SIZE(omap2430_mcbsp2_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -2366,9 +1710,7 @@ static struct omap_hwmod omap2430_mcbsp2_hwmod = { ...@@ -2366,9 +1710,7 @@ static struct omap_hwmod omap2430_mcbsp2_hwmod = {
.name = "mcbsp2", .name = "mcbsp2",
.class = &omap2430_mcbsp_hwmod_class, .class = &omap2430_mcbsp_hwmod_class,
.mpu_irqs = omap2430_mcbsp2_irqs, .mpu_irqs = omap2430_mcbsp2_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp2_irqs), .sdma_reqs = omap2_mcbsp2_sdma_reqs,
.sdma_reqs = omap2430_mcbsp2_sdma_chs,
.sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp2_sdma_chs),
.main_clk = "mcbsp2_fck", .main_clk = "mcbsp2_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -2389,11 +1731,7 @@ static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = { ...@@ -2389,11 +1731,7 @@ static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = {
{ .name = "tx", .irq = 89 }, { .name = "tx", .irq = 89 },
{ .name = "rx", .irq = 90 }, { .name = "rx", .irq = 90 },
{ .name = "common", .irq = 17 }, { .name = "common", .irq = 17 },
}; { .irq = -1 }
static struct omap_hwmod_dma_info omap2430_mcbsp3_sdma_chs[] = {
{ .name = "rx", .dma_req = 18 },
{ .name = "tx", .dma_req = 17 },
}; };
static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = { static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = {
...@@ -2403,6 +1741,7 @@ static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = { ...@@ -2403,6 +1741,7 @@ static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = {
.pa_end = 0x4808C0ff, .pa_end = 0x4808C0ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_core -> mcbsp3 */ /* l4_core -> mcbsp3 */
...@@ -2411,7 +1750,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = { ...@@ -2411,7 +1750,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
.slave = &omap2430_mcbsp3_hwmod, .slave = &omap2430_mcbsp3_hwmod,
.clk = "mcbsp3_ick", .clk = "mcbsp3_ick",
.addr = omap2430_mcbsp3_addrs, .addr = omap2430_mcbsp3_addrs,
.addr_cnt = ARRAY_SIZE(omap2430_mcbsp3_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -2424,9 +1762,7 @@ static struct omap_hwmod omap2430_mcbsp3_hwmod = { ...@@ -2424,9 +1762,7 @@ static struct omap_hwmod omap2430_mcbsp3_hwmod = {
.name = "mcbsp3", .name = "mcbsp3",
.class = &omap2430_mcbsp_hwmod_class, .class = &omap2430_mcbsp_hwmod_class,
.mpu_irqs = omap2430_mcbsp3_irqs, .mpu_irqs = omap2430_mcbsp3_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp3_irqs), .sdma_reqs = omap2_mcbsp3_sdma_reqs,
.sdma_reqs = omap2430_mcbsp3_sdma_chs,
.sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp3_sdma_chs),
.main_clk = "mcbsp3_fck", .main_clk = "mcbsp3_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -2447,11 +1783,13 @@ static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = { ...@@ -2447,11 +1783,13 @@ static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = {
{ .name = "tx", .irq = 54 }, { .name = "tx", .irq = 54 },
{ .name = "rx", .irq = 55 }, { .name = "rx", .irq = 55 },
{ .name = "common", .irq = 18 }, { .name = "common", .irq = 18 },
{ .irq = -1 }
}; };
static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = { static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = {
{ .name = "rx", .dma_req = 20 }, { .name = "rx", .dma_req = 20 },
{ .name = "tx", .dma_req = 19 }, { .name = "tx", .dma_req = 19 },
{ .dma_req = -1 }
}; };
static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = { static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = {
...@@ -2461,6 +1799,7 @@ static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = { ...@@ -2461,6 +1799,7 @@ static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = {
.pa_end = 0x4808E0ff, .pa_end = 0x4808E0ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_core -> mcbsp4 */ /* l4_core -> mcbsp4 */
...@@ -2469,7 +1808,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = { ...@@ -2469,7 +1808,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
.slave = &omap2430_mcbsp4_hwmod, .slave = &omap2430_mcbsp4_hwmod,
.clk = "mcbsp4_ick", .clk = "mcbsp4_ick",
.addr = omap2430_mcbsp4_addrs, .addr = omap2430_mcbsp4_addrs,
.addr_cnt = ARRAY_SIZE(omap2430_mcbsp4_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -2482,9 +1820,7 @@ static struct omap_hwmod omap2430_mcbsp4_hwmod = { ...@@ -2482,9 +1820,7 @@ static struct omap_hwmod omap2430_mcbsp4_hwmod = {
.name = "mcbsp4", .name = "mcbsp4",
.class = &omap2430_mcbsp_hwmod_class, .class = &omap2430_mcbsp_hwmod_class,
.mpu_irqs = omap2430_mcbsp4_irqs, .mpu_irqs = omap2430_mcbsp4_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp4_irqs),
.sdma_reqs = omap2430_mcbsp4_sdma_chs, .sdma_reqs = omap2430_mcbsp4_sdma_chs,
.sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp4_sdma_chs),
.main_clk = "mcbsp4_fck", .main_clk = "mcbsp4_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -2505,11 +1841,13 @@ static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = { ...@@ -2505,11 +1841,13 @@ static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = {
{ .name = "tx", .irq = 81 }, { .name = "tx", .irq = 81 },
{ .name = "rx", .irq = 82 }, { .name = "rx", .irq = 82 },
{ .name = "common", .irq = 19 }, { .name = "common", .irq = 19 },
{ .irq = -1 }
}; };
static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = { static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = {
{ .name = "rx", .dma_req = 22 }, { .name = "rx", .dma_req = 22 },
{ .name = "tx", .dma_req = 21 }, { .name = "tx", .dma_req = 21 },
{ .dma_req = -1 }
}; };
static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = { static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = {
...@@ -2519,6 +1857,7 @@ static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = { ...@@ -2519,6 +1857,7 @@ static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = {
.pa_end = 0x480960ff, .pa_end = 0x480960ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_core -> mcbsp5 */ /* l4_core -> mcbsp5 */
...@@ -2527,7 +1866,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = { ...@@ -2527,7 +1866,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
.slave = &omap2430_mcbsp5_hwmod, .slave = &omap2430_mcbsp5_hwmod,
.clk = "mcbsp5_ick", .clk = "mcbsp5_ick",
.addr = omap2430_mcbsp5_addrs, .addr = omap2430_mcbsp5_addrs,
.addr_cnt = ARRAY_SIZE(omap2430_mcbsp5_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -2540,9 +1878,7 @@ static struct omap_hwmod omap2430_mcbsp5_hwmod = { ...@@ -2540,9 +1878,7 @@ static struct omap_hwmod omap2430_mcbsp5_hwmod = {
.name = "mcbsp5", .name = "mcbsp5",
.class = &omap2430_mcbsp_hwmod_class, .class = &omap2430_mcbsp_hwmod_class,
.mpu_irqs = omap2430_mcbsp5_irqs, .mpu_irqs = omap2430_mcbsp5_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp5_irqs),
.sdma_reqs = omap2430_mcbsp5_sdma_chs, .sdma_reqs = omap2430_mcbsp5_sdma_chs,
.sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp5_sdma_chs),
.main_clk = "mcbsp5_fck", .main_clk = "mcbsp5_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -2580,11 +1916,13 @@ static struct omap_hwmod_class omap2430_mmc_class = { ...@@ -2580,11 +1916,13 @@ static struct omap_hwmod_class omap2430_mmc_class = {
static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = { static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = {
{ .irq = 83 }, { .irq = 83 },
{ .irq = -1 }
}; };
static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = { static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = {
{ .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */ { .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */
{ .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */ { .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */
{ .dma_req = -1 }
}; };
static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = { static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
...@@ -2603,9 +1941,7 @@ static struct omap_hwmod omap2430_mmc1_hwmod = { ...@@ -2603,9 +1941,7 @@ static struct omap_hwmod omap2430_mmc1_hwmod = {
.name = "mmc1", .name = "mmc1",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap2430_mmc1_mpu_irqs, .mpu_irqs = omap2430_mmc1_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_mmc1_mpu_irqs),
.sdma_reqs = omap2430_mmc1_sdma_reqs, .sdma_reqs = omap2430_mmc1_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap2430_mmc1_sdma_reqs),
.opt_clks = omap2430_mmc1_opt_clks, .opt_clks = omap2430_mmc1_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks), .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks),
.main_clk = "mmchs1_fck", .main_clk = "mmchs1_fck",
...@@ -2629,11 +1965,13 @@ static struct omap_hwmod omap2430_mmc1_hwmod = { ...@@ -2629,11 +1965,13 @@ static struct omap_hwmod omap2430_mmc1_hwmod = {
static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = { static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = {
{ .irq = 86 }, { .irq = 86 },
{ .irq = -1 }
}; };
static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = { static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = {
{ .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */ { .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */
{ .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */ { .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */
{ .dma_req = -1 }
}; };
static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = { static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
...@@ -2648,9 +1986,7 @@ static struct omap_hwmod omap2430_mmc2_hwmod = { ...@@ -2648,9 +1986,7 @@ static struct omap_hwmod omap2430_mmc2_hwmod = {
.name = "mmc2", .name = "mmc2",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap2430_mmc2_mpu_irqs, .mpu_irqs = omap2430_mmc2_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_mmc2_mpu_irqs),
.sdma_reqs = omap2430_mmc2_sdma_reqs, .sdma_reqs = omap2430_mmc2_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap2430_mmc2_sdma_reqs),
.opt_clks = omap2430_mmc2_opt_clks, .opt_clks = omap2430_mmc2_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks), .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks),
.main_clk = "mmchs2_fck", .main_clk = "mmchs2_fck",
......
arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c 0 → 100644
浏览文件 @ c402c0d9
/*
* omap_hwmod_2xxx_3xxx_interconnect_data.c - common interconnect data, OMAP2/3
*
* Copyright (C) 2009-2011 Nokia Corporation
* Paul Walmsley
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* XXX handle crossbar/shared link difference for L3?
* XXX these should be marked initdata for multi-OMAP kernels
*/
#include <asm/sizes.h>
#include <plat/omap_hwmod.h>
#include <plat/serial.h>
#include "omap_hwmod_common_data.h"
struct omap_hwmod_addr_space omap2430_mmc1_addr_space[] = {
{
.pa_start = 0x4809c000,
.pa_end = 0x4809c1ff,
.flags = ADDR_TYPE_RT,
},
{ }
};
struct omap_hwmod_addr_space omap2430_mmc2_addr_space[] = {
{
.pa_start = 0x480b4000,
.pa_end = 0x480b41ff,
.flags = ADDR_TYPE_RT,
},
{ }
};
struct omap_hwmod_addr_space omap2_i2c1_addr_space[] = {
{
.pa_start = 0x48070000,
.pa_end = 0x48070000 + SZ_128 - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
struct omap_hwmod_addr_space omap2_i2c2_addr_space[] = {
{
.pa_start = 0x48072000,
.pa_end = 0x48072000 + SZ_128 - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
struct omap_hwmod_addr_space omap2_dss_addrs[] = {
{
.pa_start = 0x48050000,
.pa_end = 0x48050000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
struct omap_hwmod_addr_space omap2_dss_dispc_addrs[] = {
{
.pa_start = 0x48050400,
.pa_end = 0x48050400 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
struct omap_hwmod_addr_space omap2_dss_rfbi_addrs[] = {
{
.pa_start = 0x48050800,
.pa_end = 0x48050800 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
struct omap_hwmod_addr_space omap2_dss_venc_addrs[] = {
{
.pa_start = 0x48050C00,
.pa_end = 0x48050C00 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
struct omap_hwmod_addr_space omap2_timer10_addrs[] = {
{
.pa_start = 0x48086000,
.pa_end = 0x48086000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
struct omap_hwmod_addr_space omap2_timer11_addrs[] = {
{
.pa_start = 0x48088000,
.pa_end = 0x48088000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
struct omap_hwmod_addr_space omap2xxx_timer12_addrs[] = {
{
.pa_start = 0x4808a000,
.pa_end = 0x4808a000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
struct omap_hwmod_addr_space omap2_mcspi1_addr_space[] = {
{
.pa_start = 0x48098000,
.pa_end = 0x48098000 + SZ_256 - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
struct omap_hwmod_addr_space omap2_mcspi2_addr_space[] = {
{
.pa_start = 0x4809a000,
.pa_end = 0x4809a000 + SZ_256 - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[] = {
{
.pa_start = 0x480b8000,
.pa_end = 0x480b8000 + SZ_256 - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
struct omap_hwmod_addr_space omap2_dma_system_addrs[] = {
{
.pa_start = 0x48056000,
.pa_end = 0x48056000 + SZ_4K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
struct omap_hwmod_addr_space omap2_mailbox_addrs[] = {
{
.pa_start = 0x48094000,
.pa_end = 0x48094000 + SZ_512 - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
struct omap_hwmod_addr_space omap2_mcbsp1_addrs[] = {
{
.name = "mpu",
.pa_start = 0x48074000,
.pa_end = 0x480740ff,
.flags = ADDR_TYPE_RT
},
{ }
};
arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c 0 → 100644
浏览文件 @ c402c0d9
/*
* omap_hwmod_2xxx_3xxx_ipblock_data.c - common IP block data for OMAP2/3
*
* Copyright (C) 2011 Nokia Corporation
* Paul Walmsley
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <plat/omap_hwmod.h>
#include <plat/serial.h>
#include <plat/dma.h>
#include <mach/irqs.h>
#include "omap_hwmod_common_data.h"
/* UART */
static struct omap_hwmod_class_sysconfig omap2_uart_sysc = {
.rev_offs = 0x50,
.sysc_offs = 0x54,
.syss_offs = 0x58,
.sysc_flags = (SYSC_HAS_SIDLEMODE |
SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
struct omap_hwmod_class omap2_uart_class = {
.name = "uart",
.sysc = &omap2_uart_sysc,
};
/*
* 'dss' class
* display sub-system
*/
static struct omap_hwmod_class_sysconfig omap2_dss_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
.sysc_fields = &omap_hwmod_sysc_type1,
};
struct omap_hwmod_class omap2_dss_hwmod_class = {
.name = "dss",
.sysc = &omap2_dss_sysc,
};
/*
* 'dispc' class
* display controller
*/
static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
struct omap_hwmod_class omap2_dispc_hwmod_class = {
.name = "dispc",
.sysc = &omap2_dispc_sysc,
};
/*
* 'rfbi' class
* remote frame buffer interface
*/
static struct omap_hwmod_class_sysconfig omap2_rfbi_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
SYSC_HAS_AUTOIDLE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
struct omap_hwmod_class omap2_rfbi_hwmod_class = {
.name = "rfbi",
.sysc = &omap2_rfbi_sysc,
};
/*
* 'venc' class
* video encoder
*/
struct omap_hwmod_class omap2_venc_hwmod_class = {
.name = "venc",
};
/* Common DMA request line data */
struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[] = {
{ .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
{ .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[] = {
{ .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
{ .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[] = {
{ .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
{ .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[] = {
{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[] = {
{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_mcspi1_sdma_reqs[] = {
{ .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
{ .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
{ .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
{ .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
{ .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
{ .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
{ .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
{ .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_mcspi2_sdma_reqs[] = {
{ .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
{ .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
{ .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
{ .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_mcbsp1_sdma_reqs[] = {
{ .name = "rx", .dma_req = 32 },
{ .name = "tx", .dma_req = 31 },
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_mcbsp2_sdma_reqs[] = {
{ .name = "rx", .dma_req = 34 },
{ .name = "tx", .dma_req = 33 },
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_mcbsp3_sdma_reqs[] = {
{ .name = "rx", .dma_req = 18 },
{ .name = "tx", .dma_req = 17 },
{ .dma_req = -1 }
};
/* Other IP block data */
/*
* omap_hwmod class data
*/
struct omap_hwmod_class l3_hwmod_class = {
.name = "l3"
};
struct omap_hwmod_class l4_hwmod_class = {
.name = "l4"
};
struct omap_hwmod_class mpu_hwmod_class = {
.name = "mpu"
};
struct omap_hwmod_class iva_hwmod_class = {
.name = "iva"
};
/* Common MPU IRQ line data */
struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[] = {
{ .irq = 37, },
{ .irq = -1 }
};
struct omap_hwmod_irq_info omap2_timer2_mpu_irqs[] = {
{ .irq = 38, },
{ .irq = -1 }
};
struct omap_hwmod_irq_info omap2_timer3_mpu_irqs[] = {
{ .irq = 39, },
{ .irq = -1 }
};
struct omap_hwmod_irq_info omap2_timer4_mpu_irqs[] = {
{ .irq = 40, },
{ .irq = -1 }
};
struct omap_hwmod_irq_info omap2_timer5_mpu_irqs[] = {
{ .irq = 41, },
{ .irq = -1 }
};
struct omap_hwmod_irq_info omap2_timer6_mpu_irqs[] = {
{ .irq = 42, },
{ .irq = -1 }
};
struct omap_hwmod_irq_info omap2_timer7_mpu_irqs[] = {
{ .irq = 43, },
{ .irq = -1 }
};
struct omap_hwmod_irq_info omap2_timer8_mpu_irqs[] = {
{ .irq = 44, },
{ .irq = -1 }
};
struct omap_hwmod_irq_info omap2_timer9_mpu_irqs[] = {
{ .irq = 45, },
{ .irq = -1 }
};
struct omap_hwmod_irq_info omap2_timer10_mpu_irqs[] = {
{ .irq = 46, },
{ .irq = -1 }
};
struct omap_hwmod_irq_info omap2_timer11_mpu_irqs[] = {
{ .irq = 47, },
{ .irq = -1 }
};
struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[] = {
{ .irq = INT_24XX_UART1_IRQ, },
{ .irq = -1 }
};
struct omap_hwmod_irq_info omap2_uart2_mpu_irqs[] = {
{ .irq = INT_24XX_UART2_IRQ, },
{ .irq = -1 }
};
struct omap_hwmod_irq_info omap2_uart3_mpu_irqs[] = {
{ .irq = INT_24XX_UART3_IRQ, },
{ .irq = -1 }
};
struct omap_hwmod_irq_info omap2_dispc_irqs[] = {
{ .irq = 25 },
{ .irq = -1 }
};
struct omap_hwmod_irq_info omap2_i2c1_mpu_irqs[] = {
{ .irq = INT_24XX_I2C1_IRQ, },
{ .irq = -1 }
};
struct omap_hwmod_irq_info omap2_i2c2_mpu_irqs[] = {
{ .irq = INT_24XX_I2C2_IRQ, },
{ .irq = -1 }
};
struct omap_hwmod_irq_info omap2_gpio1_irqs[] = {
{ .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
{ .irq = -1 }
};
struct omap_hwmod_irq_info omap2_gpio2_irqs[] = {
{ .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
{ .irq = -1 }
};
struct omap_hwmod_irq_info omap2_gpio3_irqs[] = {
{ .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
{ .irq = -1 }
};
struct omap_hwmod_irq_info omap2_gpio4_irqs[] = {
{ .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
{ .irq = -1 }
};
struct omap_hwmod_irq_info omap2_dma_system_irqs[] = {
{ .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
{ .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
{ .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
{ .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
{ .irq = -1 }
};
struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[] = {
{ .irq = 65 },
{ .irq = -1 }
};
struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[] = {
{ .irq = 66 },
{ .irq = -1 }
};
arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c 0 → 100644
浏览文件 @ c402c0d9
/*
* omap_hwmod_2xxx_interconnect_data.c - common interconnect data for OMAP2xxx
*
* Copyright (C) 2009-2011 Nokia Corporation
* Paul Walmsley
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* XXX handle crossbar/shared link difference for L3?
* XXX these should be marked initdata for multi-OMAP kernels
*/
#include <asm/sizes.h>
#include <plat/omap_hwmod.h>
#include <plat/serial.h>
#include "omap_hwmod_common_data.h"
struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = {
{
.pa_start = OMAP2_UART1_BASE,
.pa_end = OMAP2_UART1_BASE + SZ_8K - 1,
.flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
},
{ }
};
struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = {
{
.pa_start = OMAP2_UART2_BASE,
.pa_end = OMAP2_UART2_BASE + SZ_1K - 1,
.flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
},
{ }
};
struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = {
{
.pa_start = OMAP2_UART3_BASE,
.pa_end = OMAP2_UART3_BASE + SZ_1K - 1,
.flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
},
{ }
};
struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = {
{
.pa_start = 0x4802a000,
.pa_end = 0x4802a000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = {
{
.pa_start = 0x48078000,
.pa_end = 0x48078000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = {
{
.pa_start = 0x4807a000,
.pa_end = 0x4807a000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = {
{
.pa_start = 0x4807c000,
.pa_end = 0x4807c000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = {
{
.pa_start = 0x4807e000,
.pa_end = 0x4807e000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = {
{
.pa_start = 0x48080000,
.pa_end = 0x48080000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = {
{
.pa_start = 0x48082000,
.pa_end = 0x48082000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
struct omap_hwmod_addr_space omap2xxx_timer9_addrs[] = {
{
.pa_start = 0x48084000,
.pa_end = 0x48084000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[] = {
{
.name = "mpu",
.pa_start = 0x48076000,
.pa_end = 0x480760ff,
.flags = ADDR_TYPE_RT
},
{ }
};
arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c 0 → 100644
浏览文件 @ c402c0d9
/*
* omap_hwmod_2xxx_ipblock_data.c - common IP block data for OMAP2xxx
*
* Copyright (C) 2011 Nokia Corporation
* Paul Walmsley
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <plat/omap_hwmod.h>
#include <plat/serial.h>
#include <plat/dma.h>
#include <plat/dmtimer.h>
#include <plat/mcspi.h>
#include <mach/irqs.h>
#include "omap_hwmod_common_data.h"
#include "wd_timer.h"
struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = {
{ .irq = 48, },
{ .irq = -1 }
};
struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = {
{ .name = "dispc", .dma_req = 5 },
{ .dma_req = -1 }
};
/* OMAP2xxx Timer Common */
static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
SYSC_HAS_AUTOIDLE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
.name = "timer",
.sysc = &omap2xxx_timer_sysc,
.rev = OMAP_TIMER_IP_VERSION_1,
};
/*
* 'wd_timer' class
* 32-bit watchdog upward counter that generates a pulse on the reset pin on
* overflow condition
*/
static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
.sysc_fields = &omap_hwmod_sysc_type1,
};
struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
.name = "wd_timer",
.sysc = &omap2xxx_wd_timer_sysc,
.pre_shutdown = &omap2_wd_timer_disable
};
/*
* 'gpio' class
* general purpose io module
*/
static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {
.name = "gpio",
.sysc = &omap2xxx_gpio_sysc,
.rev = 0,
};
/* system dma */
static struct omap_hwmod_class_sysconfig omap2xxx_dma_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x002c,
.syss_offs = 0x0028,
.sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
.idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
struct omap_hwmod_class omap2xxx_dma_hwmod_class = {
.name = "dma",
.sysc = &omap2xxx_dma_sysc,
};
/*
* 'mailbox' class
* mailbox module allowing communication between the on-chip processors
* using a queued mailbox-interrupt mechanism.
*/
static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = {
.rev_offs = 0x000,
.sysc_offs = 0x010,
.syss_offs = 0x014,
.sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = {
.name = "mailbox",
.sysc = &omap2xxx_mailbox_sysc,
};
/*
* 'mcspi' class
* multichannel serial port interface (mcspi) / master/slave synchronous serial
* bus
*/
static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
struct omap_hwmod_class omap2xxx_mcspi_class = {
.name = "mcspi",
.sysc = &omap2xxx_mcspi_sysc,
.rev = OMAP2_MCSPI_REV,
};
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
浏览文件 @ c402c0d9
/* /*
* omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
* *
* Copyright (C) 2009-2010 Nokia Corporation * Copyright (C) 2009-2011 Nokia Corporation
* Paul Walmsley * Paul Walmsley
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
...@@ -103,6 +103,7 @@ static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = { ...@@ -103,6 +103,7 @@ static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = { static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
{ .irq = INT_34XX_L3_DBG_IRQ }, { .irq = INT_34XX_L3_DBG_IRQ },
{ .irq = INT_34XX_L3_APP_IRQ }, { .irq = INT_34XX_L3_APP_IRQ },
{ .irq = -1 }
}; };
static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = { static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
...@@ -111,6 +112,7 @@ static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = { ...@@ -111,6 +112,7 @@ static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
.pa_end = 0x6800ffff, .pa_end = 0x6800ffff,
.flags = ADDR_TYPE_RT, .flags = ADDR_TYPE_RT,
}, },
{ }
}; };
/* MPU -> L3 interface */ /* MPU -> L3 interface */
...@@ -118,7 +120,6 @@ static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = { ...@@ -118,7 +120,6 @@ static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
.master = &omap3xxx_mpu_hwmod, .master = &omap3xxx_mpu_hwmod,
.slave = &omap3xxx_l3_main_hwmod, .slave = &omap3xxx_l3_main_hwmod,
.addr = omap3xxx_l3_main_addrs, .addr = omap3xxx_l3_main_addrs,
.addr_cnt = ARRAY_SIZE(omap3xxx_l3_main_addrs),
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
...@@ -150,8 +151,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = { ...@@ -150,8 +151,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
static struct omap_hwmod omap3xxx_l3_main_hwmod = { static struct omap_hwmod omap3xxx_l3_main_hwmod = {
.name = "l3_main", .name = "l3_main",
.class = &l3_hwmod_class, .class = &l3_hwmod_class,
.mpu_irqs = omap3xxx_l3_main_irqs, .mpu_irqs = omap3xxx_l3_main_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_l3_main_irqs),
.masters = omap3xxx_l3_main_masters, .masters = omap3xxx_l3_main_masters,
.masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters), .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters),
.slaves = omap3xxx_l3_main_slaves, .slaves = omap3xxx_l3_main_slaves,
...@@ -190,39 +190,21 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { ...@@ -190,39 +190,21 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
}; };
/* L4 CORE -> MMC1 interface */ /* L4 CORE -> MMC1 interface */
static struct omap_hwmod_addr_space omap3xxx_mmc1_addr_space[] = {
{
.pa_start = 0x4809c000,
.pa_end = 0x4809c1ff,
.flags = ADDR_TYPE_RT,
},
};
static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = { static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_mmc1_hwmod, .slave = &omap3xxx_mmc1_hwmod,
.clk = "mmchs1_ick", .clk = "mmchs1_ick",
.addr = omap3xxx_mmc1_addr_space, .addr = omap2430_mmc1_addr_space,
.addr_cnt = ARRAY_SIZE(omap3xxx_mmc1_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
.flags = OMAP_FIREWALL_L4 .flags = OMAP_FIREWALL_L4
}; };
/* L4 CORE -> MMC2 interface */ /* L4 CORE -> MMC2 interface */
static struct omap_hwmod_addr_space omap3xxx_mmc2_addr_space[] = {
{
.pa_start = 0x480b4000,
.pa_end = 0x480b41ff,
.flags = ADDR_TYPE_RT,
},
};
static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = { static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_mmc2_hwmod, .slave = &omap3xxx_mmc2_hwmod,
.clk = "mmchs2_ick", .clk = "mmchs2_ick",
.addr = omap3xxx_mmc2_addr_space, .addr = omap2430_mmc2_addr_space,
.addr_cnt = ARRAY_SIZE(omap3xxx_mmc2_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
.flags = OMAP_FIREWALL_L4 .flags = OMAP_FIREWALL_L4
}; };
...@@ -234,6 +216,7 @@ static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = { ...@@ -234,6 +216,7 @@ static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
.pa_end = 0x480ad1ff, .pa_end = 0x480ad1ff,
.flags = ADDR_TYPE_RT, .flags = ADDR_TYPE_RT,
}, },
{ }
}; };
static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = { static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
...@@ -241,7 +224,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = { ...@@ -241,7 +224,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
.slave = &omap3xxx_mmc3_hwmod, .slave = &omap3xxx_mmc3_hwmod,
.clk = "mmchs3_ick", .clk = "mmchs3_ick",
.addr = omap3xxx_mmc3_addr_space, .addr = omap3xxx_mmc3_addr_space,
.addr_cnt = ARRAY_SIZE(omap3xxx_mmc3_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
.flags = OMAP_FIREWALL_L4 .flags = OMAP_FIREWALL_L4
}; };
...@@ -253,6 +235,7 @@ static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = { ...@@ -253,6 +235,7 @@ static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
.pa_end = OMAP3_UART1_BASE + SZ_8K - 1, .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
.flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
}, },
{ }
}; };
static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = { static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
...@@ -260,7 +243,6 @@ static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = { ...@@ -260,7 +243,6 @@ static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
.slave = &omap3xxx_uart1_hwmod, .slave = &omap3xxx_uart1_hwmod,
.clk = "uart1_ick", .clk = "uart1_ick",
.addr = omap3xxx_uart1_addr_space, .addr = omap3xxx_uart1_addr_space,
.addr_cnt = ARRAY_SIZE(omap3xxx_uart1_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -271,6 +253,7 @@ static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = { ...@@ -271,6 +253,7 @@ static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
.pa_end = OMAP3_UART2_BASE + SZ_1K - 1, .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
.flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
}, },
{ }
}; };
static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = { static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
...@@ -278,7 +261,6 @@ static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = { ...@@ -278,7 +261,6 @@ static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
.slave = &omap3xxx_uart2_hwmod, .slave = &omap3xxx_uart2_hwmod,
.clk = "uart2_ick", .clk = "uart2_ick",
.addr = omap3xxx_uart2_addr_space, .addr = omap3xxx_uart2_addr_space,
.addr_cnt = ARRAY_SIZE(omap3xxx_uart2_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -289,6 +271,7 @@ static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = { ...@@ -289,6 +271,7 @@ static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
.pa_end = OMAP3_UART3_BASE + SZ_1K - 1, .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
.flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
}, },
{ }
}; };
static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = { static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
...@@ -296,7 +279,6 @@ static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = { ...@@ -296,7 +279,6 @@ static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
.slave = &omap3xxx_uart3_hwmod, .slave = &omap3xxx_uart3_hwmod,
.clk = "uart3_ick", .clk = "uart3_ick",
.addr = omap3xxx_uart3_addr_space, .addr = omap3xxx_uart3_addr_space,
.addr_cnt = ARRAY_SIZE(omap3xxx_uart3_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -307,6 +289,7 @@ static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = { ...@@ -307,6 +289,7 @@ static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
.pa_end = OMAP3_UART4_BASE + SZ_1K - 1, .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
.flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
}, },
{ }
}; };
static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = { static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
...@@ -314,28 +297,15 @@ static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = { ...@@ -314,28 +297,15 @@ static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
.slave = &omap3xxx_uart4_hwmod, .slave = &omap3xxx_uart4_hwmod,
.clk = "uart4_ick", .clk = "uart4_ick",
.addr = omap3xxx_uart4_addr_space, .addr = omap3xxx_uart4_addr_space,
.addr_cnt = ARRAY_SIZE(omap3xxx_uart4_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* I2C IP block address space length (in bytes) */
#define OMAP2_I2C_AS_LEN 128
/* L4 CORE -> I2C1 interface */ /* L4 CORE -> I2C1 interface */
static struct omap_hwmod_addr_space omap3xxx_i2c1_addr_space[] = {
{
.pa_start = 0x48070000,
.pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
.flags = ADDR_TYPE_RT,
},
};
static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = { static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_i2c1_hwmod, .slave = &omap3xxx_i2c1_hwmod,
.clk = "i2c1_ick", .clk = "i2c1_ick",
.addr = omap3xxx_i2c1_addr_space, .addr = omap2_i2c1_addr_space,
.addr_cnt = ARRAY_SIZE(omap3xxx_i2c1_addr_space),
.fw = { .fw = {
.omap2 = { .omap2 = {
.l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION, .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
...@@ -347,20 +317,11 @@ static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = { ...@@ -347,20 +317,11 @@ static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
}; };
/* L4 CORE -> I2C2 interface */ /* L4 CORE -> I2C2 interface */
static struct omap_hwmod_addr_space omap3xxx_i2c2_addr_space[] = {
{
.pa_start = 0x48072000,
.pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
.flags = ADDR_TYPE_RT,
},
};
static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = { static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_i2c2_hwmod, .slave = &omap3xxx_i2c2_hwmod,
.clk = "i2c2_ick", .clk = "i2c2_ick",
.addr = omap3xxx_i2c2_addr_space, .addr = omap2_i2c2_addr_space,
.addr_cnt = ARRAY_SIZE(omap3xxx_i2c2_addr_space),
.fw = { .fw = {
.omap2 = { .omap2 = {
.l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION, .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
...@@ -375,9 +336,10 @@ static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = { ...@@ -375,9 +336,10 @@ static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = { static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
{ {
.pa_start = 0x48060000, .pa_start = 0x48060000,
.pa_end = 0x48060000 + OMAP2_I2C_AS_LEN - 1, .pa_end = 0x48060000 + SZ_128 - 1,
.flags = ADDR_TYPE_RT, .flags = ADDR_TYPE_RT,
}, },
{ }
}; };
static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = { static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
...@@ -385,7 +347,6 @@ static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = { ...@@ -385,7 +347,6 @@ static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
.slave = &omap3xxx_i2c3_hwmod, .slave = &omap3xxx_i2c3_hwmod,
.clk = "i2c3_ick", .clk = "i2c3_ick",
.addr = omap3xxx_i2c3_addr_space, .addr = omap3xxx_i2c3_addr_space,
.addr_cnt = ARRAY_SIZE(omap3xxx_i2c3_addr_space),
.fw = { .fw = {
.omap2 = { .omap2 = {
.l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION, .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
...@@ -403,6 +364,7 @@ static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = { ...@@ -403,6 +364,7 @@ static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
.pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1, .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
.flags = ADDR_TYPE_RT, .flags = ADDR_TYPE_RT,
}, },
{ }
}; };
static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = { static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
...@@ -410,7 +372,6 @@ static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = { ...@@ -410,7 +372,6 @@ static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
.slave = &omap34xx_sr1_hwmod, .slave = &omap34xx_sr1_hwmod,
.clk = "sr_l4_ick", .clk = "sr_l4_ick",
.addr = omap3_sr1_addr_space, .addr = omap3_sr1_addr_space,
.addr_cnt = ARRAY_SIZE(omap3_sr1_addr_space),
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
...@@ -421,6 +382,7 @@ static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = { ...@@ -421,6 +382,7 @@ static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
.pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1, .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
.flags = ADDR_TYPE_RT, .flags = ADDR_TYPE_RT,
}, },
{ }
}; };
static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = { static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
...@@ -428,7 +390,6 @@ static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = { ...@@ -428,7 +390,6 @@ static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
.slave = &omap34xx_sr2_hwmod, .slave = &omap34xx_sr2_hwmod,
.clk = "sr_l4_ick", .clk = "sr_l4_ick",
.addr = omap3_sr2_addr_space, .addr = omap3_sr2_addr_space,
.addr_cnt = ARRAY_SIZE(omap3_sr2_addr_space),
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
...@@ -442,6 +403,7 @@ static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = { ...@@ -442,6 +403,7 @@ static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
.pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1, .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_core -> usbhsotg */ /* l4_core -> usbhsotg */
...@@ -450,7 +412,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = { ...@@ -450,7 +412,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
.slave = &omap3xxx_usbhsotg_hwmod, .slave = &omap3xxx_usbhsotg_hwmod,
.clk = "l4_ick", .clk = "l4_ick",
.addr = omap3xxx_usbhsotg_addrs, .addr = omap3xxx_usbhsotg_addrs,
.addr_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_addrs),
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
...@@ -468,6 +429,7 @@ static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = { ...@@ -468,6 +429,7 @@ static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
.pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1, .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_core -> usbhsotg */ /* l4_core -> usbhsotg */
...@@ -476,7 +438,6 @@ static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = { ...@@ -476,7 +438,6 @@ static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
.slave = &am35xx_usbhsotg_hwmod, .slave = &am35xx_usbhsotg_hwmod,
.clk = "l4_ick", .clk = "l4_ick",
.addr = am35xx_usbhsotg_addrs, .addr = am35xx_usbhsotg_addrs,
.addr_cnt = ARRAY_SIZE(am35xx_usbhsotg_addrs),
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
...@@ -611,9 +572,6 @@ static struct omap_hwmod_class omap3xxx_timer_hwmod_class = { ...@@ -611,9 +572,6 @@ static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
/* timer1 */ /* timer1 */
static struct omap_hwmod omap3xxx_timer1_hwmod; static struct omap_hwmod omap3xxx_timer1_hwmod;
static struct omap_hwmod_irq_info omap3xxx_timer1_mpu_irqs[] = {
{ .irq = 37, },
};
static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = { static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
{ {
...@@ -621,6 +579,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = { ...@@ -621,6 +579,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
.pa_end = 0x48318000 + SZ_1K - 1, .pa_end = 0x48318000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_wkup -> timer1 */ /* l4_wkup -> timer1 */
...@@ -629,7 +588,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = { ...@@ -629,7 +588,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
.slave = &omap3xxx_timer1_hwmod, .slave = &omap3xxx_timer1_hwmod,
.clk = "gpt1_ick", .clk = "gpt1_ick",
.addr = omap3xxx_timer1_addrs, .addr = omap3xxx_timer1_addrs,
.addr_cnt = ARRAY_SIZE(omap3xxx_timer1_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -641,8 +599,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = { ...@@ -641,8 +599,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
/* timer1 hwmod */ /* timer1 hwmod */
static struct omap_hwmod omap3xxx_timer1_hwmod = { static struct omap_hwmod omap3xxx_timer1_hwmod = {
.name = "timer1", .name = "timer1",
.mpu_irqs = omap3xxx_timer1_mpu_irqs, .mpu_irqs = omap2_timer1_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer1_mpu_irqs),
.main_clk = "gpt1_fck", .main_clk = "gpt1_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -661,9 +618,6 @@ static struct omap_hwmod omap3xxx_timer1_hwmod = { ...@@ -661,9 +618,6 @@ static struct omap_hwmod omap3xxx_timer1_hwmod = {
/* timer2 */ /* timer2 */
static struct omap_hwmod omap3xxx_timer2_hwmod; static struct omap_hwmod omap3xxx_timer2_hwmod;
static struct omap_hwmod_irq_info omap3xxx_timer2_mpu_irqs[] = {
{ .irq = 38, },
};
static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = { static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
{ {
...@@ -671,6 +625,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = { ...@@ -671,6 +625,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
.pa_end = 0x49032000 + SZ_1K - 1, .pa_end = 0x49032000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_per -> timer2 */ /* l4_per -> timer2 */
...@@ -679,7 +634,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = { ...@@ -679,7 +634,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
.slave = &omap3xxx_timer2_hwmod, .slave = &omap3xxx_timer2_hwmod,
.clk = "gpt2_ick", .clk = "gpt2_ick",
.addr = omap3xxx_timer2_addrs, .addr = omap3xxx_timer2_addrs,
.addr_cnt = ARRAY_SIZE(omap3xxx_timer2_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -691,8 +645,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = { ...@@ -691,8 +645,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
/* timer2 hwmod */ /* timer2 hwmod */
static struct omap_hwmod omap3xxx_timer2_hwmod = { static struct omap_hwmod omap3xxx_timer2_hwmod = {
.name = "timer2", .name = "timer2",
.mpu_irqs = omap3xxx_timer2_mpu_irqs, .mpu_irqs = omap2_timer2_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer2_mpu_irqs),
.main_clk = "gpt2_fck", .main_clk = "gpt2_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -711,9 +664,6 @@ static struct omap_hwmod omap3xxx_timer2_hwmod = { ...@@ -711,9 +664,6 @@ static struct omap_hwmod omap3xxx_timer2_hwmod = {
/* timer3 */ /* timer3 */
static struct omap_hwmod omap3xxx_timer3_hwmod; static struct omap_hwmod omap3xxx_timer3_hwmod;
static struct omap_hwmod_irq_info omap3xxx_timer3_mpu_irqs[] = {
{ .irq = 39, },
};
static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = { static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
{ {
...@@ -721,6 +671,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = { ...@@ -721,6 +671,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
.pa_end = 0x49034000 + SZ_1K - 1, .pa_end = 0x49034000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_per -> timer3 */ /* l4_per -> timer3 */
...@@ -729,7 +680,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = { ...@@ -729,7 +680,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
.slave = &omap3xxx_timer3_hwmod, .slave = &omap3xxx_timer3_hwmod,
.clk = "gpt3_ick", .clk = "gpt3_ick",
.addr = omap3xxx_timer3_addrs, .addr = omap3xxx_timer3_addrs,
.addr_cnt = ARRAY_SIZE(omap3xxx_timer3_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -741,8 +691,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = { ...@@ -741,8 +691,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
/* timer3 hwmod */ /* timer3 hwmod */
static struct omap_hwmod omap3xxx_timer3_hwmod = { static struct omap_hwmod omap3xxx_timer3_hwmod = {
.name = "timer3", .name = "timer3",
.mpu_irqs = omap3xxx_timer3_mpu_irqs, .mpu_irqs = omap2_timer3_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer3_mpu_irqs),
.main_clk = "gpt3_fck", .main_clk = "gpt3_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -761,9 +710,6 @@ static struct omap_hwmod omap3xxx_timer3_hwmod = { ...@@ -761,9 +710,6 @@ static struct omap_hwmod omap3xxx_timer3_hwmod = {
/* timer4 */ /* timer4 */
static struct omap_hwmod omap3xxx_timer4_hwmod; static struct omap_hwmod omap3xxx_timer4_hwmod;
static struct omap_hwmod_irq_info omap3xxx_timer4_mpu_irqs[] = {
{ .irq = 40, },
};
static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = { static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
{ {
...@@ -771,6 +717,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = { ...@@ -771,6 +717,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
.pa_end = 0x49036000 + SZ_1K - 1, .pa_end = 0x49036000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_per -> timer4 */ /* l4_per -> timer4 */
...@@ -779,7 +726,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = { ...@@ -779,7 +726,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
.slave = &omap3xxx_timer4_hwmod, .slave = &omap3xxx_timer4_hwmod,
.clk = "gpt4_ick", .clk = "gpt4_ick",
.addr = omap3xxx_timer4_addrs, .addr = omap3xxx_timer4_addrs,
.addr_cnt = ARRAY_SIZE(omap3xxx_timer4_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -791,8 +737,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = { ...@@ -791,8 +737,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
/* timer4 hwmod */ /* timer4 hwmod */
static struct omap_hwmod omap3xxx_timer4_hwmod = { static struct omap_hwmod omap3xxx_timer4_hwmod = {
.name = "timer4", .name = "timer4",
.mpu_irqs = omap3xxx_timer4_mpu_irqs, .mpu_irqs = omap2_timer4_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer4_mpu_irqs),
.main_clk = "gpt4_fck", .main_clk = "gpt4_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -811,9 +756,6 @@ static struct omap_hwmod omap3xxx_timer4_hwmod = { ...@@ -811,9 +756,6 @@ static struct omap_hwmod omap3xxx_timer4_hwmod = {
/* timer5 */ /* timer5 */
static struct omap_hwmod omap3xxx_timer5_hwmod; static struct omap_hwmod omap3xxx_timer5_hwmod;
static struct omap_hwmod_irq_info omap3xxx_timer5_mpu_irqs[] = {
{ .irq = 41, },
};
static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = { static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
{ {
...@@ -821,6 +763,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = { ...@@ -821,6 +763,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
.pa_end = 0x49038000 + SZ_1K - 1, .pa_end = 0x49038000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_per -> timer5 */ /* l4_per -> timer5 */
...@@ -829,7 +772,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = { ...@@ -829,7 +772,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
.slave = &omap3xxx_timer5_hwmod, .slave = &omap3xxx_timer5_hwmod,
.clk = "gpt5_ick", .clk = "gpt5_ick",
.addr = omap3xxx_timer5_addrs, .addr = omap3xxx_timer5_addrs,
.addr_cnt = ARRAY_SIZE(omap3xxx_timer5_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -841,8 +783,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = { ...@@ -841,8 +783,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
/* timer5 hwmod */ /* timer5 hwmod */
static struct omap_hwmod omap3xxx_timer5_hwmod = { static struct omap_hwmod omap3xxx_timer5_hwmod = {
.name = "timer5", .name = "timer5",
.mpu_irqs = omap3xxx_timer5_mpu_irqs, .mpu_irqs = omap2_timer5_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer5_mpu_irqs),
.main_clk = "gpt5_fck", .main_clk = "gpt5_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -861,9 +802,6 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = { ...@@ -861,9 +802,6 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = {
/* timer6 */ /* timer6 */
static struct omap_hwmod omap3xxx_timer6_hwmod; static struct omap_hwmod omap3xxx_timer6_hwmod;
static struct omap_hwmod_irq_info omap3xxx_timer6_mpu_irqs[] = {
{ .irq = 42, },
};
static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = { static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
{ {
...@@ -871,6 +809,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = { ...@@ -871,6 +809,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
.pa_end = 0x4903A000 + SZ_1K - 1, .pa_end = 0x4903A000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_per -> timer6 */ /* l4_per -> timer6 */
...@@ -879,7 +818,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = { ...@@ -879,7 +818,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
.slave = &omap3xxx_timer6_hwmod, .slave = &omap3xxx_timer6_hwmod,
.clk = "gpt6_ick", .clk = "gpt6_ick",
.addr = omap3xxx_timer6_addrs, .addr = omap3xxx_timer6_addrs,
.addr_cnt = ARRAY_SIZE(omap3xxx_timer6_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -891,8 +829,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = { ...@@ -891,8 +829,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
/* timer6 hwmod */ /* timer6 hwmod */
static struct omap_hwmod omap3xxx_timer6_hwmod = { static struct omap_hwmod omap3xxx_timer6_hwmod = {
.name = "timer6", .name = "timer6",
.mpu_irqs = omap3xxx_timer6_mpu_irqs, .mpu_irqs = omap2_timer6_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer6_mpu_irqs),
.main_clk = "gpt6_fck", .main_clk = "gpt6_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -911,9 +848,6 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = { ...@@ -911,9 +848,6 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = {
/* timer7 */ /* timer7 */
static struct omap_hwmod omap3xxx_timer7_hwmod; static struct omap_hwmod omap3xxx_timer7_hwmod;
static struct omap_hwmod_irq_info omap3xxx_timer7_mpu_irqs[] = {
{ .irq = 43, },
};
static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = { static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
{ {
...@@ -921,6 +855,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = { ...@@ -921,6 +855,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
.pa_end = 0x4903C000 + SZ_1K - 1, .pa_end = 0x4903C000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_per -> timer7 */ /* l4_per -> timer7 */
...@@ -929,7 +864,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = { ...@@ -929,7 +864,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
.slave = &omap3xxx_timer7_hwmod, .slave = &omap3xxx_timer7_hwmod,
.clk = "gpt7_ick", .clk = "gpt7_ick",
.addr = omap3xxx_timer7_addrs, .addr = omap3xxx_timer7_addrs,
.addr_cnt = ARRAY_SIZE(omap3xxx_timer7_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -941,8 +875,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = { ...@@ -941,8 +875,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
/* timer7 hwmod */ /* timer7 hwmod */
static struct omap_hwmod omap3xxx_timer7_hwmod = { static struct omap_hwmod omap3xxx_timer7_hwmod = {
.name = "timer7", .name = "timer7",
.mpu_irqs = omap3xxx_timer7_mpu_irqs, .mpu_irqs = omap2_timer7_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer7_mpu_irqs),
.main_clk = "gpt7_fck", .main_clk = "gpt7_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -961,9 +894,6 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = { ...@@ -961,9 +894,6 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = {
/* timer8 */ /* timer8 */
static struct omap_hwmod omap3xxx_timer8_hwmod; static struct omap_hwmod omap3xxx_timer8_hwmod;
static struct omap_hwmod_irq_info omap3xxx_timer8_mpu_irqs[] = {
{ .irq = 44, },
};
static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = { static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
{ {
...@@ -971,6 +901,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = { ...@@ -971,6 +901,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
.pa_end = 0x4903E000 + SZ_1K - 1, .pa_end = 0x4903E000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_per -> timer8 */ /* l4_per -> timer8 */
...@@ -979,7 +910,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = { ...@@ -979,7 +910,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
.slave = &omap3xxx_timer8_hwmod, .slave = &omap3xxx_timer8_hwmod,
.clk = "gpt8_ick", .clk = "gpt8_ick",
.addr = omap3xxx_timer8_addrs, .addr = omap3xxx_timer8_addrs,
.addr_cnt = ARRAY_SIZE(omap3xxx_timer8_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -991,8 +921,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = { ...@@ -991,8 +921,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
/* timer8 hwmod */ /* timer8 hwmod */
static struct omap_hwmod omap3xxx_timer8_hwmod = { static struct omap_hwmod omap3xxx_timer8_hwmod = {
.name = "timer8", .name = "timer8",
.mpu_irqs = omap3xxx_timer8_mpu_irqs, .mpu_irqs = omap2_timer8_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer8_mpu_irqs),
.main_clk = "gpt8_fck", .main_clk = "gpt8_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1011,9 +940,6 @@ static struct omap_hwmod omap3xxx_timer8_hwmod = { ...@@ -1011,9 +940,6 @@ static struct omap_hwmod omap3xxx_timer8_hwmod = {
/* timer9 */ /* timer9 */
static struct omap_hwmod omap3xxx_timer9_hwmod; static struct omap_hwmod omap3xxx_timer9_hwmod;
static struct omap_hwmod_irq_info omap3xxx_timer9_mpu_irqs[] = {
{ .irq = 45, },
};
static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = { static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
{ {
...@@ -1021,6 +947,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = { ...@@ -1021,6 +947,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
.pa_end = 0x49040000 + SZ_1K - 1, .pa_end = 0x49040000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_per -> timer9 */ /* l4_per -> timer9 */
...@@ -1029,7 +956,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = { ...@@ -1029,7 +956,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
.slave = &omap3xxx_timer9_hwmod, .slave = &omap3xxx_timer9_hwmod,
.clk = "gpt9_ick", .clk = "gpt9_ick",
.addr = omap3xxx_timer9_addrs, .addr = omap3xxx_timer9_addrs,
.addr_cnt = ARRAY_SIZE(omap3xxx_timer9_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -1041,8 +967,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = { ...@@ -1041,8 +967,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
/* timer9 hwmod */ /* timer9 hwmod */
static struct omap_hwmod omap3xxx_timer9_hwmod = { static struct omap_hwmod omap3xxx_timer9_hwmod = {
.name = "timer9", .name = "timer9",
.mpu_irqs = omap3xxx_timer9_mpu_irqs, .mpu_irqs = omap2_timer9_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer9_mpu_irqs),
.main_clk = "gpt9_fck", .main_clk = "gpt9_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1061,25 +986,13 @@ static struct omap_hwmod omap3xxx_timer9_hwmod = { ...@@ -1061,25 +986,13 @@ static struct omap_hwmod omap3xxx_timer9_hwmod = {
/* timer10 */ /* timer10 */
static struct omap_hwmod omap3xxx_timer10_hwmod; static struct omap_hwmod omap3xxx_timer10_hwmod;
static struct omap_hwmod_irq_info omap3xxx_timer10_mpu_irqs[] = {
{ .irq = 46, },
};
static struct omap_hwmod_addr_space omap3xxx_timer10_addrs[] = {
{
.pa_start = 0x48086000,
.pa_end = 0x48086000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
};
/* l4_core -> timer10 */ /* l4_core -> timer10 */
static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = { static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_timer10_hwmod, .slave = &omap3xxx_timer10_hwmod,
.clk = "gpt10_ick", .clk = "gpt10_ick",
.addr = omap3xxx_timer10_addrs, .addr = omap2_timer10_addrs,
.addr_cnt = ARRAY_SIZE(omap3xxx_timer10_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -1091,8 +1004,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = { ...@@ -1091,8 +1004,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
/* timer10 hwmod */ /* timer10 hwmod */
static struct omap_hwmod omap3xxx_timer10_hwmod = { static struct omap_hwmod omap3xxx_timer10_hwmod = {
.name = "timer10", .name = "timer10",
.mpu_irqs = omap3xxx_timer10_mpu_irqs, .mpu_irqs = omap2_timer10_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer10_mpu_irqs),
.main_clk = "gpt10_fck", .main_clk = "gpt10_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1111,25 +1023,13 @@ static struct omap_hwmod omap3xxx_timer10_hwmod = { ...@@ -1111,25 +1023,13 @@ static struct omap_hwmod omap3xxx_timer10_hwmod = {
/* timer11 */ /* timer11 */
static struct omap_hwmod omap3xxx_timer11_hwmod; static struct omap_hwmod omap3xxx_timer11_hwmod;
static struct omap_hwmod_irq_info omap3xxx_timer11_mpu_irqs[] = {
{ .irq = 47, },
};
static struct omap_hwmod_addr_space omap3xxx_timer11_addrs[] = {
{
.pa_start = 0x48088000,
.pa_end = 0x48088000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
};
/* l4_core -> timer11 */ /* l4_core -> timer11 */
static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = { static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_timer11_hwmod, .slave = &omap3xxx_timer11_hwmod,
.clk = "gpt11_ick", .clk = "gpt11_ick",
.addr = omap3xxx_timer11_addrs, .addr = omap2_timer11_addrs,
.addr_cnt = ARRAY_SIZE(omap3xxx_timer11_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -1141,8 +1041,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = { ...@@ -1141,8 +1041,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
/* timer11 hwmod */ /* timer11 hwmod */
static struct omap_hwmod omap3xxx_timer11_hwmod = { static struct omap_hwmod omap3xxx_timer11_hwmod = {
.name = "timer11", .name = "timer11",
.mpu_irqs = omap3xxx_timer11_mpu_irqs, .mpu_irqs = omap2_timer11_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer11_mpu_irqs),
.main_clk = "gpt11_fck", .main_clk = "gpt11_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1163,6 +1062,7 @@ static struct omap_hwmod omap3xxx_timer11_hwmod = { ...@@ -1163,6 +1062,7 @@ static struct omap_hwmod omap3xxx_timer11_hwmod = {
static struct omap_hwmod omap3xxx_timer12_hwmod; static struct omap_hwmod omap3xxx_timer12_hwmod;
static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = { static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
{ .irq = 95, }, { .irq = 95, },
{ .irq = -1 }
}; };
static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = { static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
...@@ -1171,6 +1071,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = { ...@@ -1171,6 +1071,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
.pa_end = 0x48304000 + SZ_1K - 1, .pa_end = 0x48304000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_core -> timer12 */ /* l4_core -> timer12 */
...@@ -1179,7 +1080,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = { ...@@ -1179,7 +1080,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
.slave = &omap3xxx_timer12_hwmod, .slave = &omap3xxx_timer12_hwmod,
.clk = "gpt12_ick", .clk = "gpt12_ick",
.addr = omap3xxx_timer12_addrs, .addr = omap3xxx_timer12_addrs,
.addr_cnt = ARRAY_SIZE(omap3xxx_timer12_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -1192,7 +1092,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = { ...@@ -1192,7 +1092,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
static struct omap_hwmod omap3xxx_timer12_hwmod = { static struct omap_hwmod omap3xxx_timer12_hwmod = {
.name = "timer12", .name = "timer12",
.mpu_irqs = omap3xxx_timer12_mpu_irqs, .mpu_irqs = omap3xxx_timer12_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer12_mpu_irqs),
.main_clk = "gpt12_fck", .main_clk = "gpt12_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1216,6 +1115,7 @@ static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = { ...@@ -1216,6 +1115,7 @@ static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
.pa_end = 0x4831407f, .pa_end = 0x4831407f,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = { static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
...@@ -1223,7 +1123,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = { ...@@ -1223,7 +1123,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
.slave = &omap3xxx_wd_timer2_hwmod, .slave = &omap3xxx_wd_timer2_hwmod,
.clk = "wdt2_ick", .clk = "wdt2_ick",
.addr = omap3xxx_wd_timer2_addrs, .addr = omap3xxx_wd_timer2_addrs,
.addr_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -1291,45 +1190,16 @@ static struct omap_hwmod omap3xxx_wd_timer2_hwmod = { ...@@ -1291,45 +1190,16 @@ static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
.flags = HWMOD_SWSUP_SIDLE, .flags = HWMOD_SWSUP_SIDLE,
}; };
/* UART common */
static struct omap_hwmod_class_sysconfig uart_sysc = {
.rev_offs = 0x50,
.sysc_offs = 0x54,
.syss_offs = 0x58,
.sysc_flags = (SYSC_HAS_SIDLEMODE |
SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class uart_class = {
.name = "uart",
.sysc = &uart_sysc,
};
/* UART1 */ /* UART1 */
static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
{ .irq = INT_24XX_UART1_IRQ, },
};
static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
{ .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
{ .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
};
static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = { static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
&omap3_l4_core__uart1, &omap3_l4_core__uart1,
}; };
static struct omap_hwmod omap3xxx_uart1_hwmod = { static struct omap_hwmod omap3xxx_uart1_hwmod = {
.name = "uart1", .name = "uart1",
.mpu_irqs = uart1_mpu_irqs, .mpu_irqs = omap2_uart1_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs), .sdma_reqs = omap2_uart1_sdma_reqs,
.sdma_reqs = uart1_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs),
.main_clk = "uart1_fck", .main_clk = "uart1_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1342,31 +1212,20 @@ static struct omap_hwmod omap3xxx_uart1_hwmod = { ...@@ -1342,31 +1212,20 @@ static struct omap_hwmod omap3xxx_uart1_hwmod = {
}, },
.slaves = omap3xxx_uart1_slaves, .slaves = omap3xxx_uart1_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves), .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves),
.class = &uart_class, .class = &omap2_uart_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
}; };
/* UART2 */ /* UART2 */
static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
{ .irq = INT_24XX_UART2_IRQ, },
};
static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
{ .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
{ .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
};
static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = { static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
&omap3_l4_core__uart2, &omap3_l4_core__uart2,
}; };
static struct omap_hwmod omap3xxx_uart2_hwmod = { static struct omap_hwmod omap3xxx_uart2_hwmod = {
.name = "uart2", .name = "uart2",
.mpu_irqs = uart2_mpu_irqs, .mpu_irqs = omap2_uart2_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs), .sdma_reqs = omap2_uart2_sdma_reqs,
.sdma_reqs = uart2_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs),
.main_clk = "uart2_fck", .main_clk = "uart2_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1379,31 +1238,20 @@ static struct omap_hwmod omap3xxx_uart2_hwmod = { ...@@ -1379,31 +1238,20 @@ static struct omap_hwmod omap3xxx_uart2_hwmod = {
}, },
.slaves = omap3xxx_uart2_slaves, .slaves = omap3xxx_uart2_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves), .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves),
.class = &uart_class, .class = &omap2_uart_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
}; };
/* UART3 */ /* UART3 */
static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
{ .irq = INT_24XX_UART3_IRQ, },
};
static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
{ .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
{ .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
};
static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = { static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
&omap3_l4_per__uart3, &omap3_l4_per__uart3,
}; };
static struct omap_hwmod omap3xxx_uart3_hwmod = { static struct omap_hwmod omap3xxx_uart3_hwmod = {
.name = "uart3", .name = "uart3",
.mpu_irqs = uart3_mpu_irqs, .mpu_irqs = omap2_uart3_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs), .sdma_reqs = omap2_uart3_sdma_reqs,
.sdma_reqs = uart3_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs),
.main_clk = "uart3_fck", .main_clk = "uart3_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1416,7 +1264,7 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = { ...@@ -1416,7 +1264,7 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = {
}, },
.slaves = omap3xxx_uart3_slaves, .slaves = omap3xxx_uart3_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves), .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves),
.class = &uart_class, .class = &omap2_uart_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
}; };
...@@ -1424,11 +1272,13 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = { ...@@ -1424,11 +1272,13 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = {
static struct omap_hwmod_irq_info uart4_mpu_irqs[] = { static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
{ .irq = INT_36XX_UART4_IRQ, }, { .irq = INT_36XX_UART4_IRQ, },
{ .irq = -1 }
}; };
static struct omap_hwmod_dma_info uart4_sdma_reqs[] = { static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
{ .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, }, { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
{ .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, }, { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
{ .dma_req = -1 }
}; };
static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = { static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
...@@ -1438,9 +1288,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = { ...@@ -1438,9 +1288,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
static struct omap_hwmod omap3xxx_uart4_hwmod = { static struct omap_hwmod omap3xxx_uart4_hwmod = {
.name = "uart4", .name = "uart4",
.mpu_irqs = uart4_mpu_irqs, .mpu_irqs = uart4_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(uart4_mpu_irqs),
.sdma_reqs = uart4_sdma_reqs, .sdma_reqs = uart4_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(uart4_sdma_reqs),
.main_clk = "uart4_fck", .main_clk = "uart4_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1453,7 +1301,7 @@ static struct omap_hwmod omap3xxx_uart4_hwmod = { ...@@ -1453,7 +1301,7 @@ static struct omap_hwmod omap3xxx_uart4_hwmod = {
}, },
.slaves = omap3xxx_uart4_slaves, .slaves = omap3xxx_uart4_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves), .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves),
.class = &uart_class, .class = &omap2_uart_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
}; };
...@@ -1462,27 +1310,10 @@ static struct omap_hwmod_class i2c_class = { ...@@ -1462,27 +1310,10 @@ static struct omap_hwmod_class i2c_class = {
.sysc = &i2c_sysc, .sysc = &i2c_sysc,
}; };
/*
* 'dss' class
* display sub-system
*/
static struct omap_hwmod_class_sysconfig omap3xxx_dss_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap3xxx_dss_hwmod_class = {
.name = "dss",
.sysc = &omap3xxx_dss_sysc,
};
static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = { static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
{ .name = "dispc", .dma_req = 5 }, { .name = "dispc", .dma_req = 5 },
{ .name = "dsi1", .dma_req = 74 }, { .name = "dsi1", .dma_req = 74 },
{ .dma_req = -1 }
}; };
/* dss */ /* dss */
...@@ -1491,21 +1322,12 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = { ...@@ -1491,21 +1322,12 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
&omap3xxx_dss__l3, &omap3xxx_dss__l3,
}; };
static struct omap_hwmod_addr_space omap3xxx_dss_addrs[] = {
{
.pa_start = 0x48050000,
.pa_end = 0x480503FF,
.flags = ADDR_TYPE_RT
},
};
/* l4_core -> dss */ /* l4_core -> dss */
static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = { static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &omap3430es1_dss_core_hwmod, .slave = &omap3430es1_dss_core_hwmod,
.clk = "dss_ick", .clk = "dss_ick",
.addr = omap3xxx_dss_addrs, .addr = omap2_dss_addrs,
.addr_cnt = ARRAY_SIZE(omap3xxx_dss_addrs),
.fw = { .fw = {
.omap2 = { .omap2 = {
.l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION, .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
...@@ -1520,8 +1342,7 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = { ...@@ -1520,8 +1342,7 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_dss_core_hwmod, .slave = &omap3xxx_dss_core_hwmod,
.clk = "dss_ick", .clk = "dss_ick",
.addr = omap3xxx_dss_addrs, .addr = omap2_dss_addrs,
.addr_cnt = ARRAY_SIZE(omap3xxx_dss_addrs),
.fw = { .fw = {
.omap2 = { .omap2 = {
.l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION, .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
...@@ -1549,11 +1370,9 @@ static struct omap_hwmod_opt_clk dss_opt_clks[] = { ...@@ -1549,11 +1370,9 @@ static struct omap_hwmod_opt_clk dss_opt_clks[] = {
static struct omap_hwmod omap3430es1_dss_core_hwmod = { static struct omap_hwmod omap3430es1_dss_core_hwmod = {
.name = "dss_core", .name = "dss_core",
.class = &omap3xxx_dss_hwmod_class, .class = &omap2_dss_hwmod_class,
.main_clk = "dss1_alwon_fck", /* instead of dss_fck */ .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
.sdma_reqs = omap3xxx_dss_sdma_chs, .sdma_reqs = omap3xxx_dss_sdma_chs,
.sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
.prcm = { .prcm = {
.omap2 = { .omap2 = {
.prcm_reg_id = 1, .prcm_reg_id = 1,
...@@ -1575,11 +1394,9 @@ static struct omap_hwmod omap3430es1_dss_core_hwmod = { ...@@ -1575,11 +1394,9 @@ static struct omap_hwmod omap3430es1_dss_core_hwmod = {
static struct omap_hwmod omap3xxx_dss_core_hwmod = { static struct omap_hwmod omap3xxx_dss_core_hwmod = {
.name = "dss_core", .name = "dss_core",
.class = &omap3xxx_dss_hwmod_class, .class = &omap2_dss_hwmod_class,
.main_clk = "dss1_alwon_fck", /* instead of dss_fck */ .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
.sdma_reqs = omap3xxx_dss_sdma_chs, .sdma_reqs = omap3xxx_dss_sdma_chs,
.sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
.prcm = { .prcm = {
.omap2 = { .omap2 = {
.prcm_reg_id = 1, .prcm_reg_id = 1,
...@@ -1600,47 +1417,12 @@ static struct omap_hwmod omap3xxx_dss_core_hwmod = { ...@@ -1600,47 +1417,12 @@ static struct omap_hwmod omap3xxx_dss_core_hwmod = {
CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1), CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1),
}; };
/*
* 'dispc' class
* display controller
*/
static struct omap_hwmod_class_sysconfig omap3xxx_dispc_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
SYSC_HAS_MIDLEMODE | SYSC_HAS_ENAWAKEUP |
SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap3xxx_dispc_hwmod_class = {
.name = "dispc",
.sysc = &omap3xxx_dispc_sysc,
};
static struct omap_hwmod_irq_info omap3xxx_dispc_irqs[] = {
{ .irq = 25 },
};
static struct omap_hwmod_addr_space omap3xxx_dss_dispc_addrs[] = {
{
.pa_start = 0x48050400,
.pa_end = 0x480507FF,
.flags = ADDR_TYPE_RT
},
};
/* l4_core -> dss_dispc */ /* l4_core -> dss_dispc */
static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = { static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_dss_dispc_hwmod, .slave = &omap3xxx_dss_dispc_hwmod,
.clk = "dss_ick", .clk = "dss_ick",
.addr = omap3xxx_dss_dispc_addrs, .addr = omap2_dss_dispc_addrs,
.addr_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_addrs),
.fw = { .fw = {
.omap2 = { .omap2 = {
.l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION, .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
...@@ -1658,9 +1440,8 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = { ...@@ -1658,9 +1440,8 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
.name = "dss_dispc", .name = "dss_dispc",
.class = &omap3xxx_dispc_hwmod_class, .class = &omap2_dispc_hwmod_class,
.mpu_irqs = omap3xxx_dispc_irqs, .mpu_irqs = omap2_dispc_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dispc_irqs),
.main_clk = "dss1_alwon_fck", .main_clk = "dss1_alwon_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1688,6 +1469,7 @@ static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = { ...@@ -1688,6 +1469,7 @@ static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = { static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
{ .irq = 25 }, { .irq = 25 },
{ .irq = -1 }
}; };
/* dss_dsi1 */ /* dss_dsi1 */
...@@ -1697,6 +1479,7 @@ static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = { ...@@ -1697,6 +1479,7 @@ static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
.pa_end = 0x4804FFFF, .pa_end = 0x4804FFFF,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_core -> dss_dsi1 */ /* l4_core -> dss_dsi1 */
...@@ -1704,7 +1487,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = { ...@@ -1704,7 +1487,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_dss_dsi1_hwmod, .slave = &omap3xxx_dss_dsi1_hwmod,
.addr = omap3xxx_dss_dsi1_addrs, .addr = omap3xxx_dss_dsi1_addrs,
.addr_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_addrs),
.fw = { .fw = {
.omap2 = { .omap2 = {
.l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION, .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
...@@ -1724,7 +1506,6 @@ static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = { ...@@ -1724,7 +1506,6 @@ static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
.name = "dss_dsi1", .name = "dss_dsi1",
.class = &omap3xxx_dsi_hwmod_class, .class = &omap3xxx_dsi_hwmod_class,
.mpu_irqs = omap3xxx_dsi1_irqs, .mpu_irqs = omap3xxx_dsi1_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dsi1_irqs),
.main_clk = "dss1_alwon_fck", .main_clk = "dss1_alwon_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1741,41 +1522,12 @@ static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = { ...@@ -1741,41 +1522,12 @@ static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
.flags = HWMOD_NO_IDLEST, .flags = HWMOD_NO_IDLEST,
}; };
/*
* 'rfbi' class
* remote frame buffer interface
*/
static struct omap_hwmod_class_sysconfig omap3xxx_rfbi_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
SYSC_HAS_AUTOIDLE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap3xxx_rfbi_hwmod_class = {
.name = "rfbi",
.sysc = &omap3xxx_rfbi_sysc,
};
static struct omap_hwmod_addr_space omap3xxx_dss_rfbi_addrs[] = {
{
.pa_start = 0x48050800,
.pa_end = 0x48050BFF,
.flags = ADDR_TYPE_RT
},
};
/* l4_core -> dss_rfbi */ /* l4_core -> dss_rfbi */
static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = { static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_dss_rfbi_hwmod, .slave = &omap3xxx_dss_rfbi_hwmod,
.clk = "dss_ick", .clk = "dss_ick",
.addr = omap3xxx_dss_rfbi_addrs, .addr = omap2_dss_rfbi_addrs,
.addr_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_addrs),
.fw = { .fw = {
.omap2 = { .omap2 = {
.l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION, .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
...@@ -1793,7 +1545,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = { ...@@ -1793,7 +1545,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = { static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
.name = "dss_rfbi", .name = "dss_rfbi",
.class = &omap3xxx_rfbi_hwmod_class, .class = &omap2_rfbi_hwmod_class,
.main_clk = "dss1_alwon_fck", .main_clk = "dss1_alwon_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1810,31 +1562,12 @@ static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = { ...@@ -1810,31 +1562,12 @@ static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
.flags = HWMOD_NO_IDLEST, .flags = HWMOD_NO_IDLEST,
}; };
/*
* 'venc' class
* video encoder
*/
static struct omap_hwmod_class omap3xxx_venc_hwmod_class = {
.name = "venc",
};
/* dss_venc */
static struct omap_hwmod_addr_space omap3xxx_dss_venc_addrs[] = {
{
.pa_start = 0x48050C00,
.pa_end = 0x48050FFF,
.flags = ADDR_TYPE_RT
},
};
/* l4_core -> dss_venc */ /* l4_core -> dss_venc */
static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = { static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_dss_venc_hwmod, .slave = &omap3xxx_dss_venc_hwmod,
.clk = "dss_tv_fck", .clk = "dss_tv_fck",
.addr = omap3xxx_dss_venc_addrs, .addr = omap2_dss_venc_addrs,
.addr_cnt = ARRAY_SIZE(omap3xxx_dss_venc_addrs),
.fw = { .fw = {
.omap2 = { .omap2 = {
.l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION, .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
...@@ -1853,7 +1586,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = { ...@@ -1853,7 +1586,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
static struct omap_hwmod omap3xxx_dss_venc_hwmod = { static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
.name = "dss_venc", .name = "dss_venc",
.class = &omap3xxx_venc_hwmod_class, .class = &omap2_venc_hwmod_class,
.main_clk = "dss1_alwon_fck", .main_clk = "dss1_alwon_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1876,25 +1609,14 @@ static struct omap_i2c_dev_attr i2c1_dev_attr = { ...@@ -1876,25 +1609,14 @@ static struct omap_i2c_dev_attr i2c1_dev_attr = {
.fifo_depth = 8, /* bytes */ .fifo_depth = 8, /* bytes */
}; };
static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
{ .irq = INT_24XX_I2C1_IRQ, },
};
static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
};
static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = { static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
&omap3_l4_core__i2c1, &omap3_l4_core__i2c1,
}; };
static struct omap_hwmod omap3xxx_i2c1_hwmod = { static struct omap_hwmod omap3xxx_i2c1_hwmod = {
.name = "i2c1", .name = "i2c1",
.mpu_irqs = i2c1_mpu_irqs, .mpu_irqs = omap2_i2c1_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs), .sdma_reqs = omap2_i2c1_sdma_reqs,
.sdma_reqs = i2c1_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
.main_clk = "i2c1_fck", .main_clk = "i2c1_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1918,25 +1640,14 @@ static struct omap_i2c_dev_attr i2c2_dev_attr = { ...@@ -1918,25 +1640,14 @@ static struct omap_i2c_dev_attr i2c2_dev_attr = {
.fifo_depth = 8, /* bytes */ .fifo_depth = 8, /* bytes */
}; };
static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
{ .irq = INT_24XX_I2C2_IRQ, },
};
static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
};
static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = { static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
&omap3_l4_core__i2c2, &omap3_l4_core__i2c2,
}; };
static struct omap_hwmod omap3xxx_i2c2_hwmod = { static struct omap_hwmod omap3xxx_i2c2_hwmod = {
.name = "i2c2", .name = "i2c2",
.mpu_irqs = i2c2_mpu_irqs, .mpu_irqs = omap2_i2c2_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs), .sdma_reqs = omap2_i2c2_sdma_reqs,
.sdma_reqs = i2c2_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
.main_clk = "i2c2_fck", .main_clk = "i2c2_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1962,11 +1673,13 @@ static struct omap_i2c_dev_attr i2c3_dev_attr = { ...@@ -1962,11 +1673,13 @@ static struct omap_i2c_dev_attr i2c3_dev_attr = {
static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = { static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
{ .irq = INT_34XX_I2C3_IRQ, }, { .irq = INT_34XX_I2C3_IRQ, },
{ .irq = -1 }
}; };
static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = { static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
{ .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX }, { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
{ .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX }, { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
{ .dma_req = -1 }
}; };
static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = { static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
...@@ -1976,9 +1689,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = { ...@@ -1976,9 +1689,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
static struct omap_hwmod omap3xxx_i2c3_hwmod = { static struct omap_hwmod omap3xxx_i2c3_hwmod = {
.name = "i2c3", .name = "i2c3",
.mpu_irqs = i2c3_mpu_irqs, .mpu_irqs = i2c3_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(i2c3_mpu_irqs),
.sdma_reqs = i2c3_sdma_reqs, .sdma_reqs = i2c3_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(i2c3_sdma_reqs),
.main_clk = "i2c3_fck", .main_clk = "i2c3_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -2003,13 +1714,13 @@ static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = { ...@@ -2003,13 +1714,13 @@ static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
.pa_end = 0x483101ff, .pa_end = 0x483101ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = { static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
.master = &omap3xxx_l4_wkup_hwmod, .master = &omap3xxx_l4_wkup_hwmod,
.slave = &omap3xxx_gpio1_hwmod, .slave = &omap3xxx_gpio1_hwmod,
.addr = omap3xxx_gpio1_addrs, .addr = omap3xxx_gpio1_addrs,
.addr_cnt = ARRAY_SIZE(omap3xxx_gpio1_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -2020,13 +1731,13 @@ static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = { ...@@ -2020,13 +1731,13 @@ static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
.pa_end = 0x490501ff, .pa_end = 0x490501ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = { static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
.master = &omap3xxx_l4_per_hwmod, .master = &omap3xxx_l4_per_hwmod,
.slave = &omap3xxx_gpio2_hwmod, .slave = &omap3xxx_gpio2_hwmod,
.addr = omap3xxx_gpio2_addrs, .addr = omap3xxx_gpio2_addrs,
.addr_cnt = ARRAY_SIZE(omap3xxx_gpio2_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -2037,13 +1748,13 @@ static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = { ...@@ -2037,13 +1748,13 @@ static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
.pa_end = 0x490521ff, .pa_end = 0x490521ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = { static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
.master = &omap3xxx_l4_per_hwmod, .master = &omap3xxx_l4_per_hwmod,
.slave = &omap3xxx_gpio3_hwmod, .slave = &omap3xxx_gpio3_hwmod,
.addr = omap3xxx_gpio3_addrs, .addr = omap3xxx_gpio3_addrs,
.addr_cnt = ARRAY_SIZE(omap3xxx_gpio3_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -2054,13 +1765,13 @@ static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = { ...@@ -2054,13 +1765,13 @@ static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
.pa_end = 0x490541ff, .pa_end = 0x490541ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = { static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
.master = &omap3xxx_l4_per_hwmod, .master = &omap3xxx_l4_per_hwmod,
.slave = &omap3xxx_gpio4_hwmod, .slave = &omap3xxx_gpio4_hwmod,
.addr = omap3xxx_gpio4_addrs, .addr = omap3xxx_gpio4_addrs,
.addr_cnt = ARRAY_SIZE(omap3xxx_gpio4_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -2071,13 +1782,13 @@ static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = { ...@@ -2071,13 +1782,13 @@ static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
.pa_end = 0x490561ff, .pa_end = 0x490561ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = { static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
.master = &omap3xxx_l4_per_hwmod, .master = &omap3xxx_l4_per_hwmod,
.slave = &omap3xxx_gpio5_hwmod, .slave = &omap3xxx_gpio5_hwmod,
.addr = omap3xxx_gpio5_addrs, .addr = omap3xxx_gpio5_addrs,
.addr_cnt = ARRAY_SIZE(omap3xxx_gpio5_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -2088,13 +1799,13 @@ static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = { ...@@ -2088,13 +1799,13 @@ static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
.pa_end = 0x490581ff, .pa_end = 0x490581ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = { static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
.master = &omap3xxx_l4_per_hwmod, .master = &omap3xxx_l4_per_hwmod,
.slave = &omap3xxx_gpio6_hwmod, .slave = &omap3xxx_gpio6_hwmod,
.addr = omap3xxx_gpio6_addrs, .addr = omap3xxx_gpio6_addrs,
.addr_cnt = ARRAY_SIZE(omap3xxx_gpio6_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -2127,10 +1838,6 @@ static struct omap_gpio_dev_attr gpio_dev_attr = { ...@@ -2127,10 +1838,6 @@ static struct omap_gpio_dev_attr gpio_dev_attr = {
}; };
/* gpio1 */ /* gpio1 */
static struct omap_hwmod_irq_info omap3xxx_gpio1_irqs[] = {
{ .irq = 29 }, /* INT_34XX_GPIO_BANK1 */
};
static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio1_dbck", }, { .role = "dbclk", .clk = "gpio1_dbck", },
}; };
...@@ -2142,8 +1849,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = { ...@@ -2142,8 +1849,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
static struct omap_hwmod omap3xxx_gpio1_hwmod = { static struct omap_hwmod omap3xxx_gpio1_hwmod = {
.name = "gpio1", .name = "gpio1",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap3xxx_gpio1_irqs, .mpu_irqs = omap2_gpio1_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio1_irqs),
.main_clk = "gpio1_ick", .main_clk = "gpio1_ick",
.opt_clks = gpio1_opt_clks, .opt_clks = gpio1_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
...@@ -2164,10 +1870,6 @@ static struct omap_hwmod omap3xxx_gpio1_hwmod = { ...@@ -2164,10 +1870,6 @@ static struct omap_hwmod omap3xxx_gpio1_hwmod = {
}; };
/* gpio2 */ /* gpio2 */
static struct omap_hwmod_irq_info omap3xxx_gpio2_irqs[] = {
{ .irq = 30 }, /* INT_34XX_GPIO_BANK2 */
};
static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio2_dbck", }, { .role = "dbclk", .clk = "gpio2_dbck", },
}; };
...@@ -2179,8 +1881,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = { ...@@ -2179,8 +1881,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
static struct omap_hwmod omap3xxx_gpio2_hwmod = { static struct omap_hwmod omap3xxx_gpio2_hwmod = {
.name = "gpio2", .name = "gpio2",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap3xxx_gpio2_irqs, .mpu_irqs = omap2_gpio2_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio2_irqs),
.main_clk = "gpio2_ick", .main_clk = "gpio2_ick",
.opt_clks = gpio2_opt_clks, .opt_clks = gpio2_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
...@@ -2201,10 +1902,6 @@ static struct omap_hwmod omap3xxx_gpio2_hwmod = { ...@@ -2201,10 +1902,6 @@ static struct omap_hwmod omap3xxx_gpio2_hwmod = {
}; };
/* gpio3 */ /* gpio3 */
static struct omap_hwmod_irq_info omap3xxx_gpio3_irqs[] = {
{ .irq = 31 }, /* INT_34XX_GPIO_BANK3 */
};
static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio3_dbck", }, { .role = "dbclk", .clk = "gpio3_dbck", },
}; };
...@@ -2216,8 +1913,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = { ...@@ -2216,8 +1913,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
static struct omap_hwmod omap3xxx_gpio3_hwmod = { static struct omap_hwmod omap3xxx_gpio3_hwmod = {
.name = "gpio3", .name = "gpio3",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap3xxx_gpio3_irqs, .mpu_irqs = omap2_gpio3_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio3_irqs),
.main_clk = "gpio3_ick", .main_clk = "gpio3_ick",
.opt_clks = gpio3_opt_clks, .opt_clks = gpio3_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
...@@ -2238,10 +1934,6 @@ static struct omap_hwmod omap3xxx_gpio3_hwmod = { ...@@ -2238,10 +1934,6 @@ static struct omap_hwmod omap3xxx_gpio3_hwmod = {
}; };
/* gpio4 */ /* gpio4 */
static struct omap_hwmod_irq_info omap3xxx_gpio4_irqs[] = {
{ .irq = 32 }, /* INT_34XX_GPIO_BANK4 */
};
static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio4_dbck", }, { .role = "dbclk", .clk = "gpio4_dbck", },
}; };
...@@ -2253,8 +1945,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = { ...@@ -2253,8 +1945,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
static struct omap_hwmod omap3xxx_gpio4_hwmod = { static struct omap_hwmod omap3xxx_gpio4_hwmod = {
.name = "gpio4", .name = "gpio4",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap3xxx_gpio4_irqs, .mpu_irqs = omap2_gpio4_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio4_irqs),
.main_clk = "gpio4_ick", .main_clk = "gpio4_ick",
.opt_clks = gpio4_opt_clks, .opt_clks = gpio4_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
...@@ -2277,6 +1968,7 @@ static struct omap_hwmod omap3xxx_gpio4_hwmod = { ...@@ -2277,6 +1968,7 @@ static struct omap_hwmod omap3xxx_gpio4_hwmod = {
/* gpio5 */ /* gpio5 */
static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = { static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
{ .irq = 33 }, /* INT_34XX_GPIO_BANK5 */ { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
{ .irq = -1 }
}; };
static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
...@@ -2291,7 +1983,6 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod = { ...@@ -2291,7 +1983,6 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod = {
.name = "gpio5", .name = "gpio5",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap3xxx_gpio5_irqs, .mpu_irqs = omap3xxx_gpio5_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio5_irqs),
.main_clk = "gpio5_ick", .main_clk = "gpio5_ick",
.opt_clks = gpio5_opt_clks, .opt_clks = gpio5_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
...@@ -2314,6 +2005,7 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod = { ...@@ -2314,6 +2005,7 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod = {
/* gpio6 */ /* gpio6 */
static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = { static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
{ .irq = 34 }, /* INT_34XX_GPIO_BANK6 */ { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
{ .irq = -1 }
}; };
static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
...@@ -2328,7 +2020,6 @@ static struct omap_hwmod omap3xxx_gpio6_hwmod = { ...@@ -2328,7 +2020,6 @@ static struct omap_hwmod omap3xxx_gpio6_hwmod = {
.name = "gpio6", .name = "gpio6",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap3xxx_gpio6_irqs, .mpu_irqs = omap3xxx_gpio6_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio6_irqs),
.main_clk = "gpio6_ick", .main_clk = "gpio6_ick",
.opt_clks = gpio6_opt_clks, .opt_clks = gpio6_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
...@@ -2382,19 +2073,13 @@ static struct omap_hwmod_class omap3xxx_dma_hwmod_class = { ...@@ -2382,19 +2073,13 @@ static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
}; };
/* dma_system */ /* dma_system */
static struct omap_hwmod_irq_info omap3xxx_dma_system_irqs[] = {
{ .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
{ .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
{ .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
{ .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
};
static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = { static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
{ {
.pa_start = 0x48056000, .pa_start = 0x48056000,
.pa_end = 0x48056fff, .pa_end = 0x48056fff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* dma_system master ports */ /* dma_system master ports */
...@@ -2408,7 +2093,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = { ...@@ -2408,7 +2093,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
.slave = &omap3xxx_dma_system_hwmod, .slave = &omap3xxx_dma_system_hwmod,
.clk = "core_l4_ick", .clk = "core_l4_ick",
.addr = omap3xxx_dma_system_addrs, .addr = omap3xxx_dma_system_addrs,
.addr_cnt = ARRAY_SIZE(omap3xxx_dma_system_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -2420,8 +2104,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = { ...@@ -2420,8 +2104,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
static struct omap_hwmod omap3xxx_dma_system_hwmod = { static struct omap_hwmod omap3xxx_dma_system_hwmod = {
.name = "dma", .name = "dma",
.class = &omap3xxx_dma_hwmod_class, .class = &omap3xxx_dma_hwmod_class,
.mpu_irqs = omap3xxx_dma_system_irqs, .mpu_irqs = omap2_dma_system_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dma_system_irqs),
.main_clk = "core_l3_ick", .main_clk = "core_l3_ick",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -2466,11 +2149,7 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = { ...@@ -2466,11 +2149,7 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
{ .name = "irq", .irq = 16 }, { .name = "irq", .irq = 16 },
{ .name = "tx", .irq = 59 }, { .name = "tx", .irq = 59 },
{ .name = "rx", .irq = 60 }, { .name = "rx", .irq = 60 },
}; { .irq = -1 }
static struct omap_hwmod_dma_info omap3xxx_mcbsp1_sdma_chs[] = {
{ .name = "rx", .dma_req = 32 },
{ .name = "tx", .dma_req = 31 },
}; };
static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = { static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
...@@ -2480,6 +2159,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = { ...@@ -2480,6 +2159,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
.pa_end = 0x480740ff, .pa_end = 0x480740ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_core -> mcbsp1 */ /* l4_core -> mcbsp1 */
...@@ -2488,7 +2168,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = { ...@@ -2488,7 +2168,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
.slave = &omap3xxx_mcbsp1_hwmod, .slave = &omap3xxx_mcbsp1_hwmod,
.clk = "mcbsp1_ick", .clk = "mcbsp1_ick",
.addr = omap3xxx_mcbsp1_addrs, .addr = omap3xxx_mcbsp1_addrs,
.addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -2501,9 +2180,7 @@ static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { ...@@ -2501,9 +2180,7 @@ static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
.name = "mcbsp1", .name = "mcbsp1",
.class = &omap3xxx_mcbsp_hwmod_class, .class = &omap3xxx_mcbsp_hwmod_class,
.mpu_irqs = omap3xxx_mcbsp1_irqs, .mpu_irqs = omap3xxx_mcbsp1_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_irqs), .sdma_reqs = omap2_mcbsp1_sdma_reqs,
.sdma_reqs = omap3xxx_mcbsp1_sdma_chs,
.sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_sdma_chs),
.main_clk = "mcbsp1_fck", .main_clk = "mcbsp1_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -2524,11 +2201,7 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = { ...@@ -2524,11 +2201,7 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
{ .name = "irq", .irq = 17 }, { .name = "irq", .irq = 17 },
{ .name = "tx", .irq = 62 }, { .name = "tx", .irq = 62 },
{ .name = "rx", .irq = 63 }, { .name = "rx", .irq = 63 },
}; { .irq = -1 }
static struct omap_hwmod_dma_info omap3xxx_mcbsp2_sdma_chs[] = {
{ .name = "rx", .dma_req = 34 },
{ .name = "tx", .dma_req = 33 },
}; };
static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = { static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
...@@ -2538,6 +2211,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = { ...@@ -2538,6 +2211,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
.pa_end = 0x490220ff, .pa_end = 0x490220ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_per -> mcbsp2 */ /* l4_per -> mcbsp2 */
...@@ -2546,7 +2220,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = { ...@@ -2546,7 +2220,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
.slave = &omap3xxx_mcbsp2_hwmod, .slave = &omap3xxx_mcbsp2_hwmod,
.clk = "mcbsp2_ick", .clk = "mcbsp2_ick",
.addr = omap3xxx_mcbsp2_addrs, .addr = omap3xxx_mcbsp2_addrs,
.addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -2563,9 +2236,7 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = { ...@@ -2563,9 +2236,7 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
.name = "mcbsp2", .name = "mcbsp2",
.class = &omap3xxx_mcbsp_hwmod_class, .class = &omap3xxx_mcbsp_hwmod_class,
.mpu_irqs = omap3xxx_mcbsp2_irqs, .mpu_irqs = omap3xxx_mcbsp2_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_irqs), .sdma_reqs = omap2_mcbsp2_sdma_reqs,
.sdma_reqs = omap3xxx_mcbsp2_sdma_chs,
.sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sdma_chs),
.main_clk = "mcbsp2_fck", .main_clk = "mcbsp2_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -2587,11 +2258,7 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = { ...@@ -2587,11 +2258,7 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
{ .name = "irq", .irq = 22 }, { .name = "irq", .irq = 22 },
{ .name = "tx", .irq = 89 }, { .name = "tx", .irq = 89 },
{ .name = "rx", .irq = 90 }, { .name = "rx", .irq = 90 },
}; { .irq = -1 }
static struct omap_hwmod_dma_info omap3xxx_mcbsp3_sdma_chs[] = {
{ .name = "rx", .dma_req = 18 },
{ .name = "tx", .dma_req = 17 },
}; };
static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = { static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
...@@ -2601,6 +2268,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = { ...@@ -2601,6 +2268,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
.pa_end = 0x490240ff, .pa_end = 0x490240ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_per -> mcbsp3 */ /* l4_per -> mcbsp3 */
...@@ -2609,7 +2277,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = { ...@@ -2609,7 +2277,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
.slave = &omap3xxx_mcbsp3_hwmod, .slave = &omap3xxx_mcbsp3_hwmod,
.clk = "mcbsp3_ick", .clk = "mcbsp3_ick",
.addr = omap3xxx_mcbsp3_addrs, .addr = omap3xxx_mcbsp3_addrs,
.addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -2626,9 +2293,7 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { ...@@ -2626,9 +2293,7 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
.name = "mcbsp3", .name = "mcbsp3",
.class = &omap3xxx_mcbsp_hwmod_class, .class = &omap3xxx_mcbsp_hwmod_class,
.mpu_irqs = omap3xxx_mcbsp3_irqs, .mpu_irqs = omap3xxx_mcbsp3_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_irqs), .sdma_reqs = omap2_mcbsp3_sdma_reqs,
.sdma_reqs = omap3xxx_mcbsp3_sdma_chs,
.sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sdma_chs),
.main_clk = "mcbsp3_fck", .main_clk = "mcbsp3_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -2650,11 +2315,13 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = { ...@@ -2650,11 +2315,13 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
{ .name = "irq", .irq = 23 }, { .name = "irq", .irq = 23 },
{ .name = "tx", .irq = 54 }, { .name = "tx", .irq = 54 },
{ .name = "rx", .irq = 55 }, { .name = "rx", .irq = 55 },
{ .irq = -1 }
}; };
static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = { static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
{ .name = "rx", .dma_req = 20 }, { .name = "rx", .dma_req = 20 },
{ .name = "tx", .dma_req = 19 }, { .name = "tx", .dma_req = 19 },
{ .dma_req = -1 }
}; };
static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = { static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
...@@ -2664,6 +2331,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = { ...@@ -2664,6 +2331,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
.pa_end = 0x490260ff, .pa_end = 0x490260ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_per -> mcbsp4 */ /* l4_per -> mcbsp4 */
...@@ -2672,7 +2340,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = { ...@@ -2672,7 +2340,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
.slave = &omap3xxx_mcbsp4_hwmod, .slave = &omap3xxx_mcbsp4_hwmod,
.clk = "mcbsp4_ick", .clk = "mcbsp4_ick",
.addr = omap3xxx_mcbsp4_addrs, .addr = omap3xxx_mcbsp4_addrs,
.addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -2685,9 +2352,7 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod = { ...@@ -2685,9 +2352,7 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
.name = "mcbsp4", .name = "mcbsp4",
.class = &omap3xxx_mcbsp_hwmod_class, .class = &omap3xxx_mcbsp_hwmod_class,
.mpu_irqs = omap3xxx_mcbsp4_irqs, .mpu_irqs = omap3xxx_mcbsp4_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_irqs),
.sdma_reqs = omap3xxx_mcbsp4_sdma_chs, .sdma_reqs = omap3xxx_mcbsp4_sdma_chs,
.sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_sdma_chs),
.main_clk = "mcbsp4_fck", .main_clk = "mcbsp4_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -2708,11 +2373,13 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = { ...@@ -2708,11 +2373,13 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
{ .name = "irq", .irq = 27 }, { .name = "irq", .irq = 27 },
{ .name = "tx", .irq = 81 }, { .name = "tx", .irq = 81 },
{ .name = "rx", .irq = 82 }, { .name = "rx", .irq = 82 },
{ .irq = -1 }
}; };
static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = { static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
{ .name = "rx", .dma_req = 22 }, { .name = "rx", .dma_req = 22 },
{ .name = "tx", .dma_req = 21 }, { .name = "tx", .dma_req = 21 },
{ .dma_req = -1 }
}; };
static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = { static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
...@@ -2722,6 +2389,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = { ...@@ -2722,6 +2389,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
.pa_end = 0x480960ff, .pa_end = 0x480960ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_core -> mcbsp5 */ /* l4_core -> mcbsp5 */
...@@ -2730,7 +2398,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = { ...@@ -2730,7 +2398,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
.slave = &omap3xxx_mcbsp5_hwmod, .slave = &omap3xxx_mcbsp5_hwmod,
.clk = "mcbsp5_ick", .clk = "mcbsp5_ick",
.addr = omap3xxx_mcbsp5_addrs, .addr = omap3xxx_mcbsp5_addrs,
.addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -2743,9 +2410,7 @@ static struct omap_hwmod omap3xxx_mcbsp5_hwmod = { ...@@ -2743,9 +2410,7 @@ static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
.name = "mcbsp5", .name = "mcbsp5",
.class = &omap3xxx_mcbsp_hwmod_class, .class = &omap3xxx_mcbsp_hwmod_class,
.mpu_irqs = omap3xxx_mcbsp5_irqs, .mpu_irqs = omap3xxx_mcbsp5_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_irqs),
.sdma_reqs = omap3xxx_mcbsp5_sdma_chs, .sdma_reqs = omap3xxx_mcbsp5_sdma_chs,
.sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_sdma_chs),
.main_clk = "mcbsp5_fck", .main_clk = "mcbsp5_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -2776,6 +2441,7 @@ static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = { ...@@ -2776,6 +2441,7 @@ static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
/* mcbsp2_sidetone */ /* mcbsp2_sidetone */
static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = { static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
{ .name = "irq", .irq = 4 }, { .name = "irq", .irq = 4 },
{ .irq = -1 }
}; };
static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = { static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
...@@ -2785,6 +2451,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = { ...@@ -2785,6 +2451,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
.pa_end = 0x490280ff, .pa_end = 0x490280ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_per -> mcbsp2_sidetone */ /* l4_per -> mcbsp2_sidetone */
...@@ -2793,7 +2460,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = { ...@@ -2793,7 +2460,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
.slave = &omap3xxx_mcbsp2_sidetone_hwmod, .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
.clk = "mcbsp2_ick", .clk = "mcbsp2_ick",
.addr = omap3xxx_mcbsp2_sidetone_addrs, .addr = omap3xxx_mcbsp2_sidetone_addrs,
.addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_addrs),
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
...@@ -2806,7 +2472,6 @@ static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { ...@@ -2806,7 +2472,6 @@ static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
.name = "mcbsp2_sidetone", .name = "mcbsp2_sidetone",
.class = &omap3xxx_mcbsp_sidetone_hwmod_class, .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
.mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs, .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_irqs),
.main_clk = "mcbsp2_fck", .main_clk = "mcbsp2_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -2825,6 +2490,7 @@ static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { ...@@ -2825,6 +2490,7 @@ static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
/* mcbsp3_sidetone */ /* mcbsp3_sidetone */
static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = { static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
{ .name = "irq", .irq = 5 }, { .name = "irq", .irq = 5 },
{ .irq = -1 }
}; };
static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = { static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
...@@ -2834,6 +2500,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = { ...@@ -2834,6 +2500,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
.pa_end = 0x4902A0ff, .pa_end = 0x4902A0ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_per -> mcbsp3_sidetone */ /* l4_per -> mcbsp3_sidetone */
...@@ -2842,7 +2509,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = { ...@@ -2842,7 +2509,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
.slave = &omap3xxx_mcbsp3_sidetone_hwmod, .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
.clk = "mcbsp3_ick", .clk = "mcbsp3_ick",
.addr = omap3xxx_mcbsp3_sidetone_addrs, .addr = omap3xxx_mcbsp3_sidetone_addrs,
.addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_addrs),
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
...@@ -2855,7 +2521,6 @@ static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = { ...@@ -2855,7 +2521,6 @@ static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
.name = "mcbsp3_sidetone", .name = "mcbsp3_sidetone",
.class = &omap3xxx_mcbsp_sidetone_hwmod_class, .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
.mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs, .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_irqs),
.main_clk = "mcbsp3_fck", .main_clk = "mcbsp3_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -3025,6 +2690,7 @@ static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = { ...@@ -3025,6 +2690,7 @@ static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
static struct omap_hwmod omap3xxx_mailbox_hwmod; static struct omap_hwmod omap3xxx_mailbox_hwmod;
static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = { static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
{ .irq = 26 }, { .irq = 26 },
{ .irq = -1 }
}; };
static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = { static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
...@@ -3033,6 +2699,7 @@ static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = { ...@@ -3033,6 +2699,7 @@ static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
.pa_end = 0x480941ff, .pa_end = 0x480941ff,
.flags = ADDR_TYPE_RT, .flags = ADDR_TYPE_RT,
}, },
{ }
}; };
/* l4_core -> mailbox */ /* l4_core -> mailbox */
...@@ -3040,7 +2707,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = { ...@@ -3040,7 +2707,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_mailbox_hwmod, .slave = &omap3xxx_mailbox_hwmod,
.addr = omap3xxx_mailbox_addrs, .addr = omap3xxx_mailbox_addrs,
.addr_cnt = ARRAY_SIZE(omap3xxx_mailbox_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -3053,7 +2719,6 @@ static struct omap_hwmod omap3xxx_mailbox_hwmod = { ...@@ -3053,7 +2719,6 @@ static struct omap_hwmod omap3xxx_mailbox_hwmod = {
.name = "mailbox", .name = "mailbox",
.class = &omap3xxx_mailbox_hwmod_class, .class = &omap3xxx_mailbox_hwmod_class,
.mpu_irqs = omap3xxx_mailbox_irqs, .mpu_irqs = omap3xxx_mailbox_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mailbox_irqs),
.main_clk = "mailboxes_ick", .main_clk = "mailboxes_ick",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -3070,56 +2735,29 @@ static struct omap_hwmod omap3xxx_mailbox_hwmod = { ...@@ -3070,56 +2735,29 @@ static struct omap_hwmod omap3xxx_mailbox_hwmod = {
}; };
/* l4 core -> mcspi1 interface */ /* l4 core -> mcspi1 interface */
static struct omap_hwmod_addr_space omap34xx_mcspi1_addr_space[] = {
{
.pa_start = 0x48098000,
.pa_end = 0x480980ff,
.flags = ADDR_TYPE_RT,
},
};
static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = { static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &omap34xx_mcspi1, .slave = &omap34xx_mcspi1,
.clk = "mcspi1_ick", .clk = "mcspi1_ick",
.addr = omap34xx_mcspi1_addr_space, .addr = omap2_mcspi1_addr_space,
.addr_cnt = ARRAY_SIZE(omap34xx_mcspi1_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* l4 core -> mcspi2 interface */ /* l4 core -> mcspi2 interface */
static struct omap_hwmod_addr_space omap34xx_mcspi2_addr_space[] = {
{
.pa_start = 0x4809a000,
.pa_end = 0x4809a0ff,
.flags = ADDR_TYPE_RT,
},
};
static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = { static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &omap34xx_mcspi2, .slave = &omap34xx_mcspi2,
.clk = "mcspi2_ick", .clk = "mcspi2_ick",
.addr = omap34xx_mcspi2_addr_space, .addr = omap2_mcspi2_addr_space,
.addr_cnt = ARRAY_SIZE(omap34xx_mcspi2_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* l4 core -> mcspi3 interface */ /* l4 core -> mcspi3 interface */
static struct omap_hwmod_addr_space omap34xx_mcspi3_addr_space[] = {
{
.pa_start = 0x480b8000,
.pa_end = 0x480b80ff,
.flags = ADDR_TYPE_RT,
},
};
static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = { static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &omap34xx_mcspi3, .slave = &omap34xx_mcspi3,
.clk = "mcspi3_ick", .clk = "mcspi3_ick",
.addr = omap34xx_mcspi3_addr_space, .addr = omap2430_mcspi3_addr_space,
.addr_cnt = ARRAY_SIZE(omap34xx_mcspi3_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -3130,6 +2768,7 @@ static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = { ...@@ -3130,6 +2768,7 @@ static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
.pa_end = 0x480ba0ff, .pa_end = 0x480ba0ff,
.flags = ADDR_TYPE_RT, .flags = ADDR_TYPE_RT,
}, },
{ }
}; };
static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = { static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
...@@ -3137,7 +2776,6 @@ static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = { ...@@ -3137,7 +2776,6 @@ static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
.slave = &omap34xx_mcspi4, .slave = &omap34xx_mcspi4,
.clk = "mcspi4_ick", .clk = "mcspi4_ick",
.addr = omap34xx_mcspi4_addr_space, .addr = omap34xx_mcspi4_addr_space,
.addr_cnt = ARRAY_SIZE(omap34xx_mcspi4_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -3165,21 +2803,6 @@ static struct omap_hwmod_class omap34xx_mcspi_class = { ...@@ -3165,21 +2803,6 @@ static struct omap_hwmod_class omap34xx_mcspi_class = {
}; };
/* mcspi1 */ /* mcspi1 */
static struct omap_hwmod_irq_info omap34xx_mcspi1_mpu_irqs[] = {
{ .name = "irq", .irq = 65 },
};
static struct omap_hwmod_dma_info omap34xx_mcspi1_sdma_reqs[] = {
{ .name = "tx0", .dma_req = 35 },
{ .name = "rx0", .dma_req = 36 },
{ .name = "tx1", .dma_req = 37 },
{ .name = "rx1", .dma_req = 38 },
{ .name = "tx2", .dma_req = 39 },
{ .name = "rx2", .dma_req = 40 },
{ .name = "tx3", .dma_req = 41 },
{ .name = "rx3", .dma_req = 42 },
};
static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = { static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
&omap34xx_l4_core__mcspi1, &omap34xx_l4_core__mcspi1,
}; };
...@@ -3190,10 +2813,8 @@ static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { ...@@ -3190,10 +2813,8 @@ static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
static struct omap_hwmod omap34xx_mcspi1 = { static struct omap_hwmod omap34xx_mcspi1 = {
.name = "mcspi1", .name = "mcspi1",
.mpu_irqs = omap34xx_mcspi1_mpu_irqs, .mpu_irqs = omap2_mcspi1_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi1_mpu_irqs), .sdma_reqs = omap2_mcspi1_sdma_reqs,
.sdma_reqs = omap34xx_mcspi1_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi1_sdma_reqs),
.main_clk = "mcspi1_fck", .main_clk = "mcspi1_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -3212,17 +2833,6 @@ static struct omap_hwmod omap34xx_mcspi1 = { ...@@ -3212,17 +2833,6 @@ static struct omap_hwmod omap34xx_mcspi1 = {
}; };
/* mcspi2 */ /* mcspi2 */
static struct omap_hwmod_irq_info omap34xx_mcspi2_mpu_irqs[] = {
{ .name = "irq", .irq = 66 },
};
static struct omap_hwmod_dma_info omap34xx_mcspi2_sdma_reqs[] = {
{ .name = "tx0", .dma_req = 43 },
{ .name = "rx0", .dma_req = 44 },
{ .name = "tx1", .dma_req = 45 },
{ .name = "rx1", .dma_req = 46 },
};
static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = { static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
&omap34xx_l4_core__mcspi2, &omap34xx_l4_core__mcspi2,
}; };
...@@ -3233,10 +2843,8 @@ static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { ...@@ -3233,10 +2843,8 @@ static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
static struct omap_hwmod omap34xx_mcspi2 = { static struct omap_hwmod omap34xx_mcspi2 = {
.name = "mcspi2", .name = "mcspi2",
.mpu_irqs = omap34xx_mcspi2_mpu_irqs, .mpu_irqs = omap2_mcspi2_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi2_mpu_irqs), .sdma_reqs = omap2_mcspi2_sdma_reqs,
.sdma_reqs = omap34xx_mcspi2_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi2_sdma_reqs),
.main_clk = "mcspi2_fck", .main_clk = "mcspi2_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -3257,6 +2865,7 @@ static struct omap_hwmod omap34xx_mcspi2 = { ...@@ -3257,6 +2865,7 @@ static struct omap_hwmod omap34xx_mcspi2 = {
/* mcspi3 */ /* mcspi3 */
static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = { static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
{ .name = "irq", .irq = 91 }, /* 91 */ { .name = "irq", .irq = 91 }, /* 91 */
{ .irq = -1 }
}; };
static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = { static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
...@@ -3264,6 +2873,7 @@ static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = { ...@@ -3264,6 +2873,7 @@ static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
{ .name = "rx0", .dma_req = 16 }, { .name = "rx0", .dma_req = 16 },
{ .name = "tx1", .dma_req = 23 }, { .name = "tx1", .dma_req = 23 },
{ .name = "rx1", .dma_req = 24 }, { .name = "rx1", .dma_req = 24 },
{ .dma_req = -1 }
}; };
static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = { static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
...@@ -3277,9 +2887,7 @@ static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { ...@@ -3277,9 +2887,7 @@ static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
static struct omap_hwmod omap34xx_mcspi3 = { static struct omap_hwmod omap34xx_mcspi3 = {
.name = "mcspi3", .name = "mcspi3",
.mpu_irqs = omap34xx_mcspi3_mpu_irqs, .mpu_irqs = omap34xx_mcspi3_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi3_mpu_irqs),
.sdma_reqs = omap34xx_mcspi3_sdma_reqs, .sdma_reqs = omap34xx_mcspi3_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi3_sdma_reqs),
.main_clk = "mcspi3_fck", .main_clk = "mcspi3_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -3300,11 +2908,13 @@ static struct omap_hwmod omap34xx_mcspi3 = { ...@@ -3300,11 +2908,13 @@ static struct omap_hwmod omap34xx_mcspi3 = {
/* SPI4 */ /* SPI4 */
static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = { static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
{ .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */ { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
{ .irq = -1 }
}; };
static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = { static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
{ .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */ { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
{ .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */ { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
{ .dma_req = -1 }
}; };
static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = { static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
...@@ -3318,9 +2928,7 @@ static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = { ...@@ -3318,9 +2928,7 @@ static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
static struct omap_hwmod omap34xx_mcspi4 = { static struct omap_hwmod omap34xx_mcspi4 = {
.name = "mcspi4", .name = "mcspi4",
.mpu_irqs = omap34xx_mcspi4_mpu_irqs, .mpu_irqs = omap34xx_mcspi4_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi4_mpu_irqs),
.sdma_reqs = omap34xx_mcspi4_sdma_reqs, .sdma_reqs = omap34xx_mcspi4_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi4_sdma_reqs),
.main_clk = "mcspi4_fck", .main_clk = "mcspi4_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -3362,12 +2970,12 @@ static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = { ...@@ -3362,12 +2970,12 @@ static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
{ .name = "mc", .irq = 92 }, { .name = "mc", .irq = 92 },
{ .name = "dma", .irq = 93 }, { .name = "dma", .irq = 93 },
{ .irq = -1 }
}; };
static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
.name = "usb_otg_hs", .name = "usb_otg_hs",
.mpu_irqs = omap3xxx_usbhsotg_mpu_irqs, .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_mpu_irqs),
.main_clk = "hsotgusb_ick", .main_clk = "hsotgusb_ick",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -3399,6 +3007,7 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { ...@@ -3399,6 +3007,7 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = { static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
{ .name = "mc", .irq = 71 }, { .name = "mc", .irq = 71 },
{ .irq = -1 }
}; };
static struct omap_hwmod_class am35xx_usbotg_class = { static struct omap_hwmod_class am35xx_usbotg_class = {
...@@ -3409,7 +3018,6 @@ static struct omap_hwmod_class am35xx_usbotg_class = { ...@@ -3409,7 +3018,6 @@ static struct omap_hwmod_class am35xx_usbotg_class = {
static struct omap_hwmod am35xx_usbhsotg_hwmod = { static struct omap_hwmod am35xx_usbhsotg_hwmod = {
.name = "am35x_otg_hs", .name = "am35x_otg_hs",
.mpu_irqs = am35xx_usbhsotg_mpu_irqs, .mpu_irqs = am35xx_usbhsotg_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(am35xx_usbhsotg_mpu_irqs),
.main_clk = NULL, .main_clk = NULL,
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -3445,11 +3053,13 @@ static struct omap_hwmod_class omap34xx_mmc_class = { ...@@ -3445,11 +3053,13 @@ static struct omap_hwmod_class omap34xx_mmc_class = {
static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = { static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
{ .irq = 83, }, { .irq = 83, },
{ .irq = -1 }
}; };
static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = { static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
{ .name = "tx", .dma_req = 61, }, { .name = "tx", .dma_req = 61, },
{ .name = "rx", .dma_req = 62, }, { .name = "rx", .dma_req = 62, },
{ .dma_req = -1 }
}; };
static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = { static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
...@@ -3467,9 +3077,7 @@ static struct omap_mmc_dev_attr mmc1_dev_attr = { ...@@ -3467,9 +3077,7 @@ static struct omap_mmc_dev_attr mmc1_dev_attr = {
static struct omap_hwmod omap3xxx_mmc1_hwmod = { static struct omap_hwmod omap3xxx_mmc1_hwmod = {
.name = "mmc1", .name = "mmc1",
.mpu_irqs = omap34xx_mmc1_mpu_irqs, .mpu_irqs = omap34xx_mmc1_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mmc1_mpu_irqs),
.sdma_reqs = omap34xx_mmc1_sdma_reqs, .sdma_reqs = omap34xx_mmc1_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc1_sdma_reqs),
.opt_clks = omap34xx_mmc1_opt_clks, .opt_clks = omap34xx_mmc1_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
.main_clk = "mmchs1_fck", .main_clk = "mmchs1_fck",
...@@ -3493,11 +3101,13 @@ static struct omap_hwmod omap3xxx_mmc1_hwmod = { ...@@ -3493,11 +3101,13 @@ static struct omap_hwmod omap3xxx_mmc1_hwmod = {
static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = { static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
{ .irq = INT_24XX_MMC2_IRQ, }, { .irq = INT_24XX_MMC2_IRQ, },
{ .irq = -1 }
}; };
static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = { static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
{ .name = "tx", .dma_req = 47, }, { .name = "tx", .dma_req = 47, },
{ .name = "rx", .dma_req = 48, }, { .name = "rx", .dma_req = 48, },
{ .dma_req = -1 }
}; };
static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = { static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
...@@ -3511,9 +3121,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = { ...@@ -3511,9 +3121,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
static struct omap_hwmod omap3xxx_mmc2_hwmod = { static struct omap_hwmod omap3xxx_mmc2_hwmod = {
.name = "mmc2", .name = "mmc2",
.mpu_irqs = omap34xx_mmc2_mpu_irqs, .mpu_irqs = omap34xx_mmc2_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mmc2_mpu_irqs),
.sdma_reqs = omap34xx_mmc2_sdma_reqs, .sdma_reqs = omap34xx_mmc2_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc2_sdma_reqs),
.opt_clks = omap34xx_mmc2_opt_clks, .opt_clks = omap34xx_mmc2_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
.main_clk = "mmchs2_fck", .main_clk = "mmchs2_fck",
...@@ -3536,11 +3144,13 @@ static struct omap_hwmod omap3xxx_mmc2_hwmod = { ...@@ -3536,11 +3144,13 @@ static struct omap_hwmod omap3xxx_mmc2_hwmod = {
static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = { static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
{ .irq = 94, }, { .irq = 94, },
{ .irq = -1 }
}; };
static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = { static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
{ .name = "tx", .dma_req = 77, }, { .name = "tx", .dma_req = 77, },
{ .name = "rx", .dma_req = 78, }, { .name = "rx", .dma_req = 78, },
{ .dma_req = -1 }
}; };
static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = { static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
...@@ -3554,9 +3164,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = { ...@@ -3554,9 +3164,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = {
static struct omap_hwmod omap3xxx_mmc3_hwmod = { static struct omap_hwmod omap3xxx_mmc3_hwmod = {
.name = "mmc3", .name = "mmc3",
.mpu_irqs = omap34xx_mmc3_mpu_irqs, .mpu_irqs = omap34xx_mmc3_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mmc3_mpu_irqs),
.sdma_reqs = omap34xx_mmc3_sdma_reqs, .sdma_reqs = omap34xx_mmc3_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc3_sdma_reqs),
.opt_clks = omap34xx_mmc3_opt_clks, .opt_clks = omap34xx_mmc3_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks), .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
.main_clk = "mmchs3_fck", .main_clk = "mmchs3_fck",
......
arch/arm/mach-omap2/omap_hwmod_44xx_data.c
浏览文件 @ c402c0d9
...@@ -80,7 +80,12 @@ static struct omap_hwmod_class omap44xx_dmm_hwmod_class = { ...@@ -80,7 +80,12 @@ static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
.name = "dmm", .name = "dmm",
}; };
/* dmm interface data */ /* dmm */
static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
{ .irq = 113 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
/* l3_main_1 -> dmm */ /* l3_main_1 -> dmm */
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = { static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
.master = &omap44xx_l3_main_1_hwmod, .master = &omap44xx_l3_main_1_hwmod,
...@@ -95,6 +100,7 @@ static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = { ...@@ -95,6 +100,7 @@ static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
.pa_end = 0x4e0007ff, .pa_end = 0x4e0007ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* mpu -> dmm */ /* mpu -> dmm */
...@@ -103,7 +109,6 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = { ...@@ -103,7 +109,6 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
.slave = &omap44xx_dmm_hwmod, .slave = &omap44xx_dmm_hwmod,
.clk = "l3_div_ck", .clk = "l3_div_ck",
.addr = omap44xx_dmm_addrs, .addr = omap44xx_dmm_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_dmm_addrs),
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
...@@ -113,17 +118,12 @@ static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = { ...@@ -113,17 +118,12 @@ static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
&omap44xx_mpu__dmm, &omap44xx_mpu__dmm,
}; };
static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
{ .irq = 113 + OMAP44XX_IRQ_GIC_START },
};
static struct omap_hwmod omap44xx_dmm_hwmod = { static struct omap_hwmod omap44xx_dmm_hwmod = {
.name = "dmm", .name = "dmm",
.class = &omap44xx_dmm_hwmod_class, .class = &omap44xx_dmm_hwmod_class,
.mpu_irqs = omap44xx_dmm_irqs,
.slaves = omap44xx_dmm_slaves, .slaves = omap44xx_dmm_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves), .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves),
.mpu_irqs = omap44xx_dmm_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dmm_irqs),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
}; };
...@@ -135,7 +135,7 @@ static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = { ...@@ -135,7 +135,7 @@ static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
.name = "emif_fw", .name = "emif_fw",
}; };
/* emif_fw interface data */ /* emif_fw */
/* dmm -> emif_fw */ /* dmm -> emif_fw */
static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = { static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
.master = &omap44xx_dmm_hwmod, .master = &omap44xx_dmm_hwmod,
...@@ -150,6 +150,7 @@ static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = { ...@@ -150,6 +150,7 @@ static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
.pa_end = 0x4a20c0ff, .pa_end = 0x4a20c0ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_cfg -> emif_fw */ /* l4_cfg -> emif_fw */
...@@ -158,7 +159,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = { ...@@ -158,7 +159,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
.slave = &omap44xx_emif_fw_hwmod, .slave = &omap44xx_emif_fw_hwmod,
.clk = "l4_div_ck", .clk = "l4_div_ck",
.addr = omap44xx_emif_fw_addrs, .addr = omap44xx_emif_fw_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_emif_fw_addrs),
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
...@@ -184,7 +184,7 @@ static struct omap_hwmod_class omap44xx_l3_hwmod_class = { ...@@ -184,7 +184,7 @@ static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
.name = "l3", .name = "l3",
}; };
/* l3_instr interface data */ /* l3_instr */
/* iva -> l3_instr */ /* iva -> l3_instr */
static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = { static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
.master = &omap44xx_iva_hwmod, .master = &omap44xx_iva_hwmod,
...@@ -215,7 +215,13 @@ static struct omap_hwmod omap44xx_l3_instr_hwmod = { ...@@ -215,7 +215,13 @@ static struct omap_hwmod omap44xx_l3_instr_hwmod = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
}; };
/* l3_main_1 interface data */ /* l3_main_1 */
static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
{ .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
{ .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
/* dsp -> l3_main_1 */ /* dsp -> l3_main_1 */
static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = { static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
.master = &omap44xx_dsp_hwmod, .master = &omap44xx_dsp_hwmod,
...@@ -264,18 +270,13 @@ static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = { ...@@ -264,18 +270,13 @@ static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* L3 target configuration and error log registers */
static struct omap_hwmod_irq_info omap44xx_l3_targ_irqs[] = {
{ .irq = 9 + OMAP44XX_IRQ_GIC_START },
{ .irq = 10 + OMAP44XX_IRQ_GIC_START },
};
static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = { static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
{ {
.pa_start = 0x44000000, .pa_start = 0x44000000,
.pa_end = 0x44000fff, .pa_end = 0x44000fff,
.flags = ADDR_TYPE_RT, .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* mpu -> l3_main_1 */ /* mpu -> l3_main_1 */
...@@ -284,8 +285,7 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { ...@@ -284,8 +285,7 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
.slave = &omap44xx_l3_main_1_hwmod, .slave = &omap44xx_l3_main_1_hwmod,
.clk = "l3_div_ck", .clk = "l3_div_ck",
.addr = omap44xx_l3_main_1_addrs, .addr = omap44xx_l3_main_1_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_l3_main_1_addrs), .user = OCP_USER_MPU,
.user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* l3_main_1 slave ports */ /* l3_main_1 slave ports */
...@@ -302,14 +302,13 @@ static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = { ...@@ -302,14 +302,13 @@ static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
static struct omap_hwmod omap44xx_l3_main_1_hwmod = { static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
.name = "l3_main_1", .name = "l3_main_1",
.class = &omap44xx_l3_hwmod_class, .class = &omap44xx_l3_hwmod_class,
.mpu_irqs = omap44xx_l3_targ_irqs, .mpu_irqs = omap44xx_l3_main_1_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_l3_targ_irqs),
.slaves = omap44xx_l3_main_1_slaves, .slaves = omap44xx_l3_main_1_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves), .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
}; };
/* l3_main_2 interface data */ /* l3_main_2 */
/* dma_system -> l3_main_2 */ /* dma_system -> l3_main_2 */
static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = { static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
.master = &omap44xx_dma_system_hwmod, .master = &omap44xx_dma_system_hwmod,
...@@ -354,8 +353,9 @@ static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = { ...@@ -354,8 +353,9 @@ static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
{ {
.pa_start = 0x44800000, .pa_start = 0x44800000,
.pa_end = 0x44801fff, .pa_end = 0x44801fff,
.flags = ADDR_TYPE_RT, .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l3_main_1 -> l3_main_2 */ /* l3_main_1 -> l3_main_2 */
...@@ -364,8 +364,7 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = { ...@@ -364,8 +364,7 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
.slave = &omap44xx_l3_main_2_hwmod, .slave = &omap44xx_l3_main_2_hwmod,
.clk = "l3_div_ck", .clk = "l3_div_ck",
.addr = omap44xx_l3_main_2_addrs, .addr = omap44xx_l3_main_2_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_l3_main_2_addrs), .user = OCP_USER_MPU,
.user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* l4_cfg -> l3_main_2 */ /* l4_cfg -> l3_main_2 */
...@@ -404,13 +403,14 @@ static struct omap_hwmod omap44xx_l3_main_2_hwmod = { ...@@ -404,13 +403,14 @@ static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
}; };
/* l3_main_3 interface data */ /* l3_main_3 */
static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = { static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
{ {
.pa_start = 0x45000000, .pa_start = 0x45000000,
.pa_end = 0x45000fff, .pa_end = 0x45000fff,
.flags = ADDR_TYPE_RT, .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l3_main_1 -> l3_main_3 */ /* l3_main_1 -> l3_main_3 */
...@@ -419,8 +419,7 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = { ...@@ -419,8 +419,7 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
.slave = &omap44xx_l3_main_3_hwmod, .slave = &omap44xx_l3_main_3_hwmod,
.clk = "l3_div_ck", .clk = "l3_div_ck",
.addr = omap44xx_l3_main_3_addrs, .addr = omap44xx_l3_main_3_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_l3_main_3_addrs), .user = OCP_USER_MPU,
.user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* l3_main_2 -> l3_main_3 */ /* l3_main_2 -> l3_main_3 */
...@@ -462,7 +461,7 @@ static struct omap_hwmod_class omap44xx_l4_hwmod_class = { ...@@ -462,7 +461,7 @@ static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
.name = "l4", .name = "l4",
}; };
/* l4_abe interface data */ /* l4_abe */
/* aess -> l4_abe */ /* aess -> l4_abe */
static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = { static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
.master = &omap44xx_aess_hwmod, .master = &omap44xx_aess_hwmod,
...@@ -511,7 +510,7 @@ static struct omap_hwmod omap44xx_l4_abe_hwmod = { ...@@ -511,7 +510,7 @@ static struct omap_hwmod omap44xx_l4_abe_hwmod = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
}; };
/* l4_cfg interface data */ /* l4_cfg */
/* l3_main_1 -> l4_cfg */ /* l3_main_1 -> l4_cfg */
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = { static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
.master = &omap44xx_l3_main_1_hwmod, .master = &omap44xx_l3_main_1_hwmod,
...@@ -533,7 +532,7 @@ static struct omap_hwmod omap44xx_l4_cfg_hwmod = { ...@@ -533,7 +532,7 @@ static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
}; };
/* l4_per interface data */ /* l4_per */
/* l3_main_2 -> l4_per */ /* l3_main_2 -> l4_per */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = { static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
.master = &omap44xx_l3_main_2_hwmod, .master = &omap44xx_l3_main_2_hwmod,
...@@ -555,7 +554,7 @@ static struct omap_hwmod omap44xx_l4_per_hwmod = { ...@@ -555,7 +554,7 @@ static struct omap_hwmod omap44xx_l4_per_hwmod = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
}; };
/* l4_wkup interface data */ /* l4_wkup */
/* l4_cfg -> l4_wkup */ /* l4_cfg -> l4_wkup */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = { static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
.master = &omap44xx_l4_cfg_hwmod, .master = &omap44xx_l4_cfg_hwmod,
...@@ -585,7 +584,7 @@ static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = { ...@@ -585,7 +584,7 @@ static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
.name = "mpu_bus", .name = "mpu_bus",
}; };
/* mpu_private interface data */ /* mpu_private */
/* mpu -> mpu_private */ /* mpu -> mpu_private */
static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = { static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
.master = &omap44xx_mpu_hwmod, .master = &omap44xx_mpu_hwmod,
...@@ -633,7 +632,9 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = { ...@@ -633,7 +632,9 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
* gpmc * gpmc
* gpu * gpu
* hdq1w * hdq1w
* hsi * mcasp
* mpu_c0
* mpu_c1
* ocmc_ram * ocmc_ram
* ocp2scp_usb_phy * ocp2scp_usb_phy
* ocp_wp_noc * ocp_wp_noc
...@@ -660,7 +661,8 @@ static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = { ...@@ -660,7 +661,8 @@ static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
.sysc_offs = 0x0010, .sysc_offs = 0x0010,
.sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE), .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
MSTANDBY_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type2, .sysc_fields = &omap_hwmod_sysc_type2,
}; };
...@@ -672,6 +674,7 @@ static struct omap_hwmod_class omap44xx_aess_hwmod_class = { ...@@ -672,6 +674,7 @@ static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
/* aess */ /* aess */
static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = { static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
{ .irq = 99 + OMAP44XX_IRQ_GIC_START }, { .irq = 99 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = { static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
...@@ -683,6 +686,7 @@ static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = { ...@@ -683,6 +686,7 @@ static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
{ .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START }, { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
{ .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START }, { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
{ .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START }, { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
{ .dma_req = -1 }
}; };
/* aess master ports */ /* aess master ports */
...@@ -696,6 +700,7 @@ static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = { ...@@ -696,6 +700,7 @@ static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
.pa_end = 0x401f13ff, .pa_end = 0x401f13ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_abe -> aess */ /* l4_abe -> aess */
...@@ -704,7 +709,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = { ...@@ -704,7 +709,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
.slave = &omap44xx_aess_hwmod, .slave = &omap44xx_aess_hwmod,
.clk = "ocp_abe_iclk", .clk = "ocp_abe_iclk",
.addr = omap44xx_aess_addrs, .addr = omap44xx_aess_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_aess_addrs),
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
...@@ -714,6 +718,7 @@ static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = { ...@@ -714,6 +718,7 @@ static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
.pa_end = 0x490f13ff, .pa_end = 0x490f13ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_abe -> aess (dma) */ /* l4_abe -> aess (dma) */
...@@ -722,7 +727,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = { ...@@ -722,7 +727,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
.slave = &omap44xx_aess_hwmod, .slave = &omap44xx_aess_hwmod,
.clk = "ocp_abe_iclk", .clk = "ocp_abe_iclk",
.addr = omap44xx_aess_dma_addrs, .addr = omap44xx_aess_dma_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_aess_dma_addrs),
.user = OCP_USER_SDMA, .user = OCP_USER_SDMA,
}; };
...@@ -736,11 +740,9 @@ static struct omap_hwmod omap44xx_aess_hwmod = { ...@@ -736,11 +740,9 @@ static struct omap_hwmod omap44xx_aess_hwmod = {
.name = "aess", .name = "aess",
.class = &omap44xx_aess_hwmod_class, .class = &omap44xx_aess_hwmod_class,
.mpu_irqs = omap44xx_aess_irqs, .mpu_irqs = omap44xx_aess_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_aess_irqs),
.sdma_reqs = omap44xx_aess_sdma_reqs, .sdma_reqs = omap44xx_aess_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_aess_sdma_reqs),
.main_clk = "aess_fck", .main_clk = "aess_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
.clkctrl_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL, .clkctrl_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
}, },
...@@ -769,7 +771,7 @@ static struct omap_hwmod_opt_clk bandgap_opt_clks[] = { ...@@ -769,7 +771,7 @@ static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
static struct omap_hwmod omap44xx_bandgap_hwmod = { static struct omap_hwmod omap44xx_bandgap_hwmod = {
.name = "bandgap", .name = "bandgap",
.class = &omap44xx_bandgap_hwmod_class, .class = &omap44xx_bandgap_hwmod_class,
.prcm = { .prcm = {
.omap4 = { .omap4 = {
.clkctrl_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, .clkctrl_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
}, },
...@@ -806,6 +808,7 @@ static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = { ...@@ -806,6 +808,7 @@ static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
.pa_end = 0x4a30401f, .pa_end = 0x4a30401f,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_wkup -> counter_32k */ /* l4_wkup -> counter_32k */
...@@ -814,7 +817,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = { ...@@ -814,7 +817,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
.slave = &omap44xx_counter_32k_hwmod, .slave = &omap44xx_counter_32k_hwmod,
.clk = "l4_wkup_clk_mux_ck", .clk = "l4_wkup_clk_mux_ck",
.addr = omap44xx_counter_32k_addrs, .addr = omap44xx_counter_32k_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_counter_32k_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -828,7 +830,7 @@ static struct omap_hwmod omap44xx_counter_32k_hwmod = { ...@@ -828,7 +830,7 @@ static struct omap_hwmod omap44xx_counter_32k_hwmod = {
.class = &omap44xx_counter_hwmod_class, .class = &omap44xx_counter_hwmod_class,
.flags = HWMOD_SWSUP_SIDLE, .flags = HWMOD_SWSUP_SIDLE,
.main_clk = "sys_32k_ck", .main_clk = "sys_32k_ck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
.clkctrl_reg = OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL, .clkctrl_reg = OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL,
}, },
...@@ -875,6 +877,7 @@ static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = { ...@@ -875,6 +877,7 @@ static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
{ .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START }, { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
{ .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START }, { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
{ .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START }, { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
/* dma_system master ports */ /* dma_system master ports */
...@@ -888,6 +891,7 @@ static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = { ...@@ -888,6 +891,7 @@ static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
.pa_end = 0x4a056fff, .pa_end = 0x4a056fff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_cfg -> dma_system */ /* l4_cfg -> dma_system */
...@@ -896,7 +900,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = { ...@@ -896,7 +900,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
.slave = &omap44xx_dma_system_hwmod, .slave = &omap44xx_dma_system_hwmod,
.clk = "l4_div_ck", .clk = "l4_div_ck",
.addr = omap44xx_dma_system_addrs, .addr = omap44xx_dma_system_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_dma_system_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -909,7 +912,6 @@ static struct omap_hwmod omap44xx_dma_system_hwmod = { ...@@ -909,7 +912,6 @@ static struct omap_hwmod omap44xx_dma_system_hwmod = {
.name = "dma_system", .name = "dma_system",
.class = &omap44xx_dma_hwmod_class, .class = &omap44xx_dma_hwmod_class,
.mpu_irqs = omap44xx_dma_system_irqs, .mpu_irqs = omap44xx_dma_system_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dma_system_irqs),
.main_clk = "l3_div_ck", .main_clk = "l3_div_ck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -948,10 +950,12 @@ static struct omap_hwmod_class omap44xx_dmic_hwmod_class = { ...@@ -948,10 +950,12 @@ static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
static struct omap_hwmod omap44xx_dmic_hwmod; static struct omap_hwmod omap44xx_dmic_hwmod;
static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = { static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
{ .irq = 114 + OMAP44XX_IRQ_GIC_START }, { .irq = 114 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = { static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
{ .dma_req = 66 + OMAP44XX_DMA_REQ_START }, { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
{ .dma_req = -1 }
}; };
static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = { static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
...@@ -960,6 +964,7 @@ static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = { ...@@ -960,6 +964,7 @@ static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
.pa_end = 0x4012e07f, .pa_end = 0x4012e07f,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_abe -> dmic */ /* l4_abe -> dmic */
...@@ -968,7 +973,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = { ...@@ -968,7 +973,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
.slave = &omap44xx_dmic_hwmod, .slave = &omap44xx_dmic_hwmod,
.clk = "ocp_abe_iclk", .clk = "ocp_abe_iclk",
.addr = omap44xx_dmic_addrs, .addr = omap44xx_dmic_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_dmic_addrs),
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
...@@ -978,6 +982,7 @@ static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = { ...@@ -978,6 +982,7 @@ static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
.pa_end = 0x4902e07f, .pa_end = 0x4902e07f,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_abe -> dmic (dma) */ /* l4_abe -> dmic (dma) */
...@@ -986,7 +991,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = { ...@@ -986,7 +991,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
.slave = &omap44xx_dmic_hwmod, .slave = &omap44xx_dmic_hwmod,
.clk = "ocp_abe_iclk", .clk = "ocp_abe_iclk",
.addr = omap44xx_dmic_dma_addrs, .addr = omap44xx_dmic_dma_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_dmic_dma_addrs),
.user = OCP_USER_SDMA, .user = OCP_USER_SDMA,
}; };
...@@ -1000,11 +1004,9 @@ static struct omap_hwmod omap44xx_dmic_hwmod = { ...@@ -1000,11 +1004,9 @@ static struct omap_hwmod omap44xx_dmic_hwmod = {
.name = "dmic", .name = "dmic",
.class = &omap44xx_dmic_hwmod_class, .class = &omap44xx_dmic_hwmod_class,
.mpu_irqs = omap44xx_dmic_irqs, .mpu_irqs = omap44xx_dmic_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dmic_irqs),
.sdma_reqs = omap44xx_dmic_sdma_reqs, .sdma_reqs = omap44xx_dmic_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dmic_sdma_reqs),
.main_clk = "dmic_fck", .main_clk = "dmic_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
.clkctrl_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL, .clkctrl_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
}, },
...@@ -1026,6 +1028,7 @@ static struct omap_hwmod_class omap44xx_dsp_hwmod_class = { ...@@ -1026,6 +1028,7 @@ static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
/* dsp */ /* dsp */
static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = { static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
{ .irq = 28 + OMAP44XX_IRQ_GIC_START }, { .irq = 28 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = { static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
...@@ -1082,7 +1085,6 @@ static struct omap_hwmod omap44xx_dsp_hwmod = { ...@@ -1082,7 +1085,6 @@ static struct omap_hwmod omap44xx_dsp_hwmod = {
.name = "dsp", .name = "dsp",
.class = &omap44xx_dsp_hwmod_class, .class = &omap44xx_dsp_hwmod_class,
.mpu_irqs = omap44xx_dsp_irqs, .mpu_irqs = omap44xx_dsp_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dsp_irqs),
.rst_lines = omap44xx_dsp_resets, .rst_lines = omap44xx_dsp_resets,
.rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets), .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets),
.main_clk = "dsp_fck", .main_clk = "dsp_fck",
...@@ -1127,6 +1129,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = { ...@@ -1127,6 +1129,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
.pa_end = 0x5800007f, .pa_end = 0x5800007f,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l3_main_2 -> dss */ /* l3_main_2 -> dss */
...@@ -1135,7 +1138,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = { ...@@ -1135,7 +1138,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
.slave = &omap44xx_dss_hwmod, .slave = &omap44xx_dss_hwmod,
.clk = "l3_div_ck", .clk = "l3_div_ck",
.addr = omap44xx_dss_dma_addrs, .addr = omap44xx_dss_dma_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_dss_dma_addrs),
.user = OCP_USER_SDMA, .user = OCP_USER_SDMA,
}; };
...@@ -1145,6 +1147,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = { ...@@ -1145,6 +1147,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
.pa_end = 0x4804007f, .pa_end = 0x4804007f,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_per -> dss */ /* l4_per -> dss */
...@@ -1153,7 +1156,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = { ...@@ -1153,7 +1156,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
.slave = &omap44xx_dss_hwmod, .slave = &omap44xx_dss_hwmod,
.clk = "l4_div_ck", .clk = "l4_div_ck",
.addr = omap44xx_dss_addrs, .addr = omap44xx_dss_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_dss_addrs),
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
...@@ -1215,10 +1217,12 @@ static struct omap_hwmod_class omap44xx_dispc_hwmod_class = { ...@@ -1215,10 +1217,12 @@ static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
static struct omap_hwmod omap44xx_dss_dispc_hwmod; static struct omap_hwmod omap44xx_dss_dispc_hwmod;
static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = { static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
{ .irq = 25 + OMAP44XX_IRQ_GIC_START }, { .irq = 25 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = { static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
{ .dma_req = 5 + OMAP44XX_DMA_REQ_START }, { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
{ .dma_req = -1 }
}; };
static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = { static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
...@@ -1227,6 +1231,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = { ...@@ -1227,6 +1231,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
.pa_end = 0x58001fff, .pa_end = 0x58001fff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l3_main_2 -> dss_dispc */ /* l3_main_2 -> dss_dispc */
...@@ -1235,7 +1240,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = { ...@@ -1235,7 +1240,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
.slave = &omap44xx_dss_dispc_hwmod, .slave = &omap44xx_dss_dispc_hwmod,
.clk = "l3_div_ck", .clk = "l3_div_ck",
.addr = omap44xx_dss_dispc_dma_addrs, .addr = omap44xx_dss_dispc_dma_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_dss_dispc_dma_addrs),
.user = OCP_USER_SDMA, .user = OCP_USER_SDMA,
}; };
...@@ -1245,6 +1249,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = { ...@@ -1245,6 +1249,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
.pa_end = 0x48041fff, .pa_end = 0x48041fff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_per -> dss_dispc */ /* l4_per -> dss_dispc */
...@@ -1253,7 +1258,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = { ...@@ -1253,7 +1258,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
.slave = &omap44xx_dss_dispc_hwmod, .slave = &omap44xx_dss_dispc_hwmod,
.clk = "l4_div_ck", .clk = "l4_div_ck",
.addr = omap44xx_dss_dispc_addrs, .addr = omap44xx_dss_dispc_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_dss_dispc_addrs),
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
...@@ -1267,9 +1271,7 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = { ...@@ -1267,9 +1271,7 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
.name = "dss_dispc", .name = "dss_dispc",
.class = &omap44xx_dispc_hwmod_class, .class = &omap44xx_dispc_hwmod_class,
.mpu_irqs = omap44xx_dss_dispc_irqs, .mpu_irqs = omap44xx_dss_dispc_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dispc_irqs),
.sdma_reqs = omap44xx_dss_dispc_sdma_reqs, .sdma_reqs = omap44xx_dss_dispc_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dispc_sdma_reqs),
.main_clk = "dss_fck", .main_clk = "dss_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -1306,10 +1308,12 @@ static struct omap_hwmod_class omap44xx_dsi_hwmod_class = { ...@@ -1306,10 +1308,12 @@ static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
static struct omap_hwmod omap44xx_dss_dsi1_hwmod; static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = { static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
{ .irq = 53 + OMAP44XX_IRQ_GIC_START }, { .irq = 53 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = { static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
{ .dma_req = 74 + OMAP44XX_DMA_REQ_START }, { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
{ .dma_req = -1 }
}; };
static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = { static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
...@@ -1318,6 +1322,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = { ...@@ -1318,6 +1322,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
.pa_end = 0x580041ff, .pa_end = 0x580041ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l3_main_2 -> dss_dsi1 */ /* l3_main_2 -> dss_dsi1 */
...@@ -1326,7 +1331,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = { ...@@ -1326,7 +1331,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
.slave = &omap44xx_dss_dsi1_hwmod, .slave = &omap44xx_dss_dsi1_hwmod,
.clk = "l3_div_ck", .clk = "l3_div_ck",
.addr = omap44xx_dss_dsi1_dma_addrs, .addr = omap44xx_dss_dsi1_dma_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_dma_addrs),
.user = OCP_USER_SDMA, .user = OCP_USER_SDMA,
}; };
...@@ -1336,6 +1340,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = { ...@@ -1336,6 +1340,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
.pa_end = 0x480441ff, .pa_end = 0x480441ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_per -> dss_dsi1 */ /* l4_per -> dss_dsi1 */
...@@ -1344,7 +1349,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = { ...@@ -1344,7 +1349,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
.slave = &omap44xx_dss_dsi1_hwmod, .slave = &omap44xx_dss_dsi1_hwmod,
.clk = "l4_div_ck", .clk = "l4_div_ck",
.addr = omap44xx_dss_dsi1_addrs, .addr = omap44xx_dss_dsi1_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_addrs),
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
...@@ -1358,9 +1362,7 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = { ...@@ -1358,9 +1362,7 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
.name = "dss_dsi1", .name = "dss_dsi1",
.class = &omap44xx_dsi_hwmod_class, .class = &omap44xx_dsi_hwmod_class,
.mpu_irqs = omap44xx_dss_dsi1_irqs, .mpu_irqs = omap44xx_dss_dsi1_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_irqs),
.sdma_reqs = omap44xx_dss_dsi1_sdma_reqs, .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_sdma_reqs),
.main_clk = "dss_fck", .main_clk = "dss_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -1376,10 +1378,12 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = { ...@@ -1376,10 +1378,12 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
static struct omap_hwmod omap44xx_dss_dsi2_hwmod; static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = { static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
{ .irq = 84 + OMAP44XX_IRQ_GIC_START }, { .irq = 84 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = { static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
{ .dma_req = 83 + OMAP44XX_DMA_REQ_START }, { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
{ .dma_req = -1 }
}; };
static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = { static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
...@@ -1388,6 +1392,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = { ...@@ -1388,6 +1392,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
.pa_end = 0x580051ff, .pa_end = 0x580051ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l3_main_2 -> dss_dsi2 */ /* l3_main_2 -> dss_dsi2 */
...@@ -1396,7 +1401,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = { ...@@ -1396,7 +1401,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
.slave = &omap44xx_dss_dsi2_hwmod, .slave = &omap44xx_dss_dsi2_hwmod,
.clk = "l3_div_ck", .clk = "l3_div_ck",
.addr = omap44xx_dss_dsi2_dma_addrs, .addr = omap44xx_dss_dsi2_dma_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_dma_addrs),
.user = OCP_USER_SDMA, .user = OCP_USER_SDMA,
}; };
...@@ -1406,6 +1410,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = { ...@@ -1406,6 +1410,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
.pa_end = 0x480451ff, .pa_end = 0x480451ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_per -> dss_dsi2 */ /* l4_per -> dss_dsi2 */
...@@ -1414,7 +1419,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = { ...@@ -1414,7 +1419,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
.slave = &omap44xx_dss_dsi2_hwmod, .slave = &omap44xx_dss_dsi2_hwmod,
.clk = "l4_div_ck", .clk = "l4_div_ck",
.addr = omap44xx_dss_dsi2_addrs, .addr = omap44xx_dss_dsi2_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_addrs),
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
...@@ -1428,9 +1432,7 @@ static struct omap_hwmod omap44xx_dss_dsi2_hwmod = { ...@@ -1428,9 +1432,7 @@ static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
.name = "dss_dsi2", .name = "dss_dsi2",
.class = &omap44xx_dsi_hwmod_class, .class = &omap44xx_dsi_hwmod_class,
.mpu_irqs = omap44xx_dss_dsi2_irqs, .mpu_irqs = omap44xx_dss_dsi2_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_irqs),
.sdma_reqs = omap44xx_dss_dsi2_sdma_reqs, .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_sdma_reqs),
.main_clk = "dss_fck", .main_clk = "dss_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -1466,10 +1468,12 @@ static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = { ...@@ -1466,10 +1468,12 @@ static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
static struct omap_hwmod omap44xx_dss_hdmi_hwmod; static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = { static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
{ .irq = 101 + OMAP44XX_IRQ_GIC_START }, { .irq = 101 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = { static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
{ .dma_req = 75 + OMAP44XX_DMA_REQ_START }, { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
{ .dma_req = -1 }
}; };
static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = { static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
...@@ -1478,6 +1482,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = { ...@@ -1478,6 +1482,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
.pa_end = 0x58006fff, .pa_end = 0x58006fff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l3_main_2 -> dss_hdmi */ /* l3_main_2 -> dss_hdmi */
...@@ -1486,7 +1491,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = { ...@@ -1486,7 +1491,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
.slave = &omap44xx_dss_hdmi_hwmod, .slave = &omap44xx_dss_hdmi_hwmod,
.clk = "l3_div_ck", .clk = "l3_div_ck",
.addr = omap44xx_dss_hdmi_dma_addrs, .addr = omap44xx_dss_hdmi_dma_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_dma_addrs),
.user = OCP_USER_SDMA, .user = OCP_USER_SDMA,
}; };
...@@ -1496,6 +1500,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = { ...@@ -1496,6 +1500,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
.pa_end = 0x48046fff, .pa_end = 0x48046fff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_per -> dss_hdmi */ /* l4_per -> dss_hdmi */
...@@ -1504,7 +1509,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = { ...@@ -1504,7 +1509,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
.slave = &omap44xx_dss_hdmi_hwmod, .slave = &omap44xx_dss_hdmi_hwmod,
.clk = "l4_div_ck", .clk = "l4_div_ck",
.addr = omap44xx_dss_hdmi_addrs, .addr = omap44xx_dss_hdmi_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_addrs),
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
...@@ -1518,9 +1522,7 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = { ...@@ -1518,9 +1522,7 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
.name = "dss_hdmi", .name = "dss_hdmi",
.class = &omap44xx_hdmi_hwmod_class, .class = &omap44xx_hdmi_hwmod_class,
.mpu_irqs = omap44xx_dss_hdmi_irqs, .mpu_irqs = omap44xx_dss_hdmi_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_irqs),
.sdma_reqs = omap44xx_dss_hdmi_sdma_reqs, .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_sdma_reqs),
.main_clk = "dss_fck", .main_clk = "dss_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -1556,6 +1558,7 @@ static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = { ...@@ -1556,6 +1558,7 @@ static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
static struct omap_hwmod omap44xx_dss_rfbi_hwmod; static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = { static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
{ .dma_req = 13 + OMAP44XX_DMA_REQ_START }, { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
{ .dma_req = -1 }
}; };
static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = { static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
...@@ -1564,6 +1567,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = { ...@@ -1564,6 +1567,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
.pa_end = 0x580020ff, .pa_end = 0x580020ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l3_main_2 -> dss_rfbi */ /* l3_main_2 -> dss_rfbi */
...@@ -1572,7 +1576,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = { ...@@ -1572,7 +1576,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
.slave = &omap44xx_dss_rfbi_hwmod, .slave = &omap44xx_dss_rfbi_hwmod,
.clk = "l3_div_ck", .clk = "l3_div_ck",
.addr = omap44xx_dss_rfbi_dma_addrs, .addr = omap44xx_dss_rfbi_dma_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_dma_addrs),
.user = OCP_USER_SDMA, .user = OCP_USER_SDMA,
}; };
...@@ -1582,6 +1585,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = { ...@@ -1582,6 +1585,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
.pa_end = 0x480420ff, .pa_end = 0x480420ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_per -> dss_rfbi */ /* l4_per -> dss_rfbi */
...@@ -1590,7 +1594,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = { ...@@ -1590,7 +1594,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
.slave = &omap44xx_dss_rfbi_hwmod, .slave = &omap44xx_dss_rfbi_hwmod,
.clk = "l4_div_ck", .clk = "l4_div_ck",
.addr = omap44xx_dss_rfbi_addrs, .addr = omap44xx_dss_rfbi_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_addrs),
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
...@@ -1604,7 +1607,6 @@ static struct omap_hwmod omap44xx_dss_rfbi_hwmod = { ...@@ -1604,7 +1607,6 @@ static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
.name = "dss_rfbi", .name = "dss_rfbi",
.class = &omap44xx_rfbi_hwmod_class, .class = &omap44xx_rfbi_hwmod_class,
.sdma_reqs = omap44xx_dss_rfbi_sdma_reqs, .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_sdma_reqs),
.main_clk = "dss_fck", .main_clk = "dss_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -1633,6 +1635,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = { ...@@ -1633,6 +1635,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
.pa_end = 0x580030ff, .pa_end = 0x580030ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l3_main_2 -> dss_venc */ /* l3_main_2 -> dss_venc */
...@@ -1641,7 +1644,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = { ...@@ -1641,7 +1644,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
.slave = &omap44xx_dss_venc_hwmod, .slave = &omap44xx_dss_venc_hwmod,
.clk = "l3_div_ck", .clk = "l3_div_ck",
.addr = omap44xx_dss_venc_dma_addrs, .addr = omap44xx_dss_venc_dma_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_dss_venc_dma_addrs),
.user = OCP_USER_SDMA, .user = OCP_USER_SDMA,
}; };
...@@ -1651,6 +1653,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = { ...@@ -1651,6 +1653,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
.pa_end = 0x480430ff, .pa_end = 0x480430ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_per -> dss_venc */ /* l4_per -> dss_venc */
...@@ -1659,7 +1662,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = { ...@@ -1659,7 +1662,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
.slave = &omap44xx_dss_venc_hwmod, .slave = &omap44xx_dss_venc_hwmod,
.clk = "l4_div_ck", .clk = "l4_div_ck",
.addr = omap44xx_dss_venc_addrs, .addr = omap44xx_dss_venc_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_dss_venc_addrs),
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
...@@ -1716,6 +1718,7 @@ static struct omap_gpio_dev_attr gpio_dev_attr = { ...@@ -1716,6 +1718,7 @@ static struct omap_gpio_dev_attr gpio_dev_attr = {
static struct omap_hwmod omap44xx_gpio1_hwmod; static struct omap_hwmod omap44xx_gpio1_hwmod;
static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = { static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
{ .irq = 29 + OMAP44XX_IRQ_GIC_START }, { .irq = 29 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = { static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
...@@ -1724,6 +1727,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = { ...@@ -1724,6 +1727,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
.pa_end = 0x4a3101ff, .pa_end = 0x4a3101ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_wkup -> gpio1 */ /* l4_wkup -> gpio1 */
...@@ -1732,7 +1736,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = { ...@@ -1732,7 +1736,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
.slave = &omap44xx_gpio1_hwmod, .slave = &omap44xx_gpio1_hwmod,
.clk = "l4_wkup_clk_mux_ck", .clk = "l4_wkup_clk_mux_ck",
.addr = omap44xx_gpio1_addrs, .addr = omap44xx_gpio1_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_gpio1_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -1749,7 +1752,6 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = { ...@@ -1749,7 +1752,6 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = {
.name = "gpio1", .name = "gpio1",
.class = &omap44xx_gpio_hwmod_class, .class = &omap44xx_gpio_hwmod_class,
.mpu_irqs = omap44xx_gpio1_irqs, .mpu_irqs = omap44xx_gpio1_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio1_irqs),
.main_clk = "gpio1_ick", .main_clk = "gpio1_ick",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -1768,6 +1770,7 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = { ...@@ -1768,6 +1770,7 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = {
static struct omap_hwmod omap44xx_gpio2_hwmod; static struct omap_hwmod omap44xx_gpio2_hwmod;
static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = { static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
{ .irq = 30 + OMAP44XX_IRQ_GIC_START }, { .irq = 30 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = { static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
...@@ -1776,6 +1779,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = { ...@@ -1776,6 +1779,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
.pa_end = 0x480551ff, .pa_end = 0x480551ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_per -> gpio2 */ /* l4_per -> gpio2 */
...@@ -1784,7 +1788,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = { ...@@ -1784,7 +1788,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
.slave = &omap44xx_gpio2_hwmod, .slave = &omap44xx_gpio2_hwmod,
.clk = "l4_div_ck", .clk = "l4_div_ck",
.addr = omap44xx_gpio2_addrs, .addr = omap44xx_gpio2_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_gpio2_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -1802,7 +1805,6 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = { ...@@ -1802,7 +1805,6 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = {
.class = &omap44xx_gpio_hwmod_class, .class = &omap44xx_gpio_hwmod_class,
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap44xx_gpio2_irqs, .mpu_irqs = omap44xx_gpio2_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio2_irqs),
.main_clk = "gpio2_ick", .main_clk = "gpio2_ick",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -1821,6 +1823,7 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = { ...@@ -1821,6 +1823,7 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = {
static struct omap_hwmod omap44xx_gpio3_hwmod; static struct omap_hwmod omap44xx_gpio3_hwmod;
static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = { static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
{ .irq = 31 + OMAP44XX_IRQ_GIC_START }, { .irq = 31 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = { static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
...@@ -1829,6 +1832,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = { ...@@ -1829,6 +1832,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
.pa_end = 0x480571ff, .pa_end = 0x480571ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_per -> gpio3 */ /* l4_per -> gpio3 */
...@@ -1837,7 +1841,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = { ...@@ -1837,7 +1841,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
.slave = &omap44xx_gpio3_hwmod, .slave = &omap44xx_gpio3_hwmod,
.clk = "l4_div_ck", .clk = "l4_div_ck",
.addr = omap44xx_gpio3_addrs, .addr = omap44xx_gpio3_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_gpio3_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -1855,7 +1858,6 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = { ...@@ -1855,7 +1858,6 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = {
.class = &omap44xx_gpio_hwmod_class, .class = &omap44xx_gpio_hwmod_class,
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap44xx_gpio3_irqs, .mpu_irqs = omap44xx_gpio3_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio3_irqs),
.main_clk = "gpio3_ick", .main_clk = "gpio3_ick",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -1874,6 +1876,7 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = { ...@@ -1874,6 +1876,7 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = {
static struct omap_hwmod omap44xx_gpio4_hwmod; static struct omap_hwmod omap44xx_gpio4_hwmod;
static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = { static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
{ .irq = 32 + OMAP44XX_IRQ_GIC_START }, { .irq = 32 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = { static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
...@@ -1882,6 +1885,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = { ...@@ -1882,6 +1885,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
.pa_end = 0x480591ff, .pa_end = 0x480591ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_per -> gpio4 */ /* l4_per -> gpio4 */
...@@ -1890,7 +1894,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = { ...@@ -1890,7 +1894,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
.slave = &omap44xx_gpio4_hwmod, .slave = &omap44xx_gpio4_hwmod,
.clk = "l4_div_ck", .clk = "l4_div_ck",
.addr = omap44xx_gpio4_addrs, .addr = omap44xx_gpio4_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_gpio4_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -1908,7 +1911,6 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = { ...@@ -1908,7 +1911,6 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = {
.class = &omap44xx_gpio_hwmod_class, .class = &omap44xx_gpio_hwmod_class,
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap44xx_gpio4_irqs, .mpu_irqs = omap44xx_gpio4_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio4_irqs),
.main_clk = "gpio4_ick", .main_clk = "gpio4_ick",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -1927,6 +1929,7 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = { ...@@ -1927,6 +1929,7 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = {
static struct omap_hwmod omap44xx_gpio5_hwmod; static struct omap_hwmod omap44xx_gpio5_hwmod;
static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = { static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
{ .irq = 33 + OMAP44XX_IRQ_GIC_START }, { .irq = 33 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = { static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
...@@ -1935,6 +1938,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = { ...@@ -1935,6 +1938,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
.pa_end = 0x4805b1ff, .pa_end = 0x4805b1ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_per -> gpio5 */ /* l4_per -> gpio5 */
...@@ -1943,7 +1947,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = { ...@@ -1943,7 +1947,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
.slave = &omap44xx_gpio5_hwmod, .slave = &omap44xx_gpio5_hwmod,
.clk = "l4_div_ck", .clk = "l4_div_ck",
.addr = omap44xx_gpio5_addrs, .addr = omap44xx_gpio5_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_gpio5_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -1961,7 +1964,6 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = { ...@@ -1961,7 +1964,6 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = {
.class = &omap44xx_gpio_hwmod_class, .class = &omap44xx_gpio_hwmod_class,
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap44xx_gpio5_irqs, .mpu_irqs = omap44xx_gpio5_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio5_irqs),
.main_clk = "gpio5_ick", .main_clk = "gpio5_ick",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -1980,6 +1982,7 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = { ...@@ -1980,6 +1982,7 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = {
static struct omap_hwmod omap44xx_gpio6_hwmod; static struct omap_hwmod omap44xx_gpio6_hwmod;
static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = { static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
{ .irq = 34 + OMAP44XX_IRQ_GIC_START }, { .irq = 34 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = { static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
...@@ -1988,6 +1991,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = { ...@@ -1988,6 +1991,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
.pa_end = 0x4805d1ff, .pa_end = 0x4805d1ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_per -> gpio6 */ /* l4_per -> gpio6 */
...@@ -1996,7 +2000,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = { ...@@ -1996,7 +2000,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
.slave = &omap44xx_gpio6_hwmod, .slave = &omap44xx_gpio6_hwmod,
.clk = "l4_div_ck", .clk = "l4_div_ck",
.addr = omap44xx_gpio6_addrs, .addr = omap44xx_gpio6_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_gpio6_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -2014,7 +2017,6 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = { ...@@ -2014,7 +2017,6 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = {
.class = &omap44xx_gpio_hwmod_class, .class = &omap44xx_gpio_hwmod_class,
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap44xx_gpio6_irqs, .mpu_irqs = omap44xx_gpio6_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio6_irqs),
.main_clk = "gpio6_ick", .main_clk = "gpio6_ick",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -2044,7 +2046,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = { ...@@ -2044,7 +2046,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
MSTANDBY_SMART), MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type1, .sysc_fields = &omap_hwmod_sysc_type1,
}; };
...@@ -2058,6 +2060,7 @@ static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = { ...@@ -2058,6 +2060,7 @@ static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
{ .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START }, { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
{ .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START }, { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
{ .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START }, { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
/* hsi master ports */ /* hsi master ports */
...@@ -2071,6 +2074,7 @@ static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = { ...@@ -2071,6 +2074,7 @@ static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
.pa_end = 0x4a05bfff, .pa_end = 0x4a05bfff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_cfg -> hsi */ /* l4_cfg -> hsi */
...@@ -2079,7 +2083,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = { ...@@ -2079,7 +2083,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
.slave = &omap44xx_hsi_hwmod, .slave = &omap44xx_hsi_hwmod,
.clk = "l4_div_ck", .clk = "l4_div_ck",
.addr = omap44xx_hsi_addrs, .addr = omap44xx_hsi_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_hsi_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -2092,9 +2095,8 @@ static struct omap_hwmod omap44xx_hsi_hwmod = { ...@@ -2092,9 +2095,8 @@ static struct omap_hwmod omap44xx_hsi_hwmod = {
.name = "hsi", .name = "hsi",
.class = &omap44xx_hsi_hwmod_class, .class = &omap44xx_hsi_hwmod_class,
.mpu_irqs = omap44xx_hsi_irqs, .mpu_irqs = omap44xx_hsi_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_hsi_irqs),
.main_clk = "hsi_fck", .main_clk = "hsi_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
.clkctrl_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, .clkctrl_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
}, },
...@@ -2131,11 +2133,13 @@ static struct omap_hwmod_class omap44xx_i2c_hwmod_class = { ...@@ -2131,11 +2133,13 @@ static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
static struct omap_hwmod omap44xx_i2c1_hwmod; static struct omap_hwmod omap44xx_i2c1_hwmod;
static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = { static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
{ .irq = 56 + OMAP44XX_IRQ_GIC_START }, { .irq = 56 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = { static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
{ .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START }, { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
{ .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START }, { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
{ .dma_req = -1 }
}; };
static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = { static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
...@@ -2144,6 +2148,7 @@ static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = { ...@@ -2144,6 +2148,7 @@ static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
.pa_end = 0x480700ff, .pa_end = 0x480700ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_per -> i2c1 */ /* l4_per -> i2c1 */
...@@ -2152,7 +2157,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = { ...@@ -2152,7 +2157,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
.slave = &omap44xx_i2c1_hwmod, .slave = &omap44xx_i2c1_hwmod,
.clk = "l4_div_ck", .clk = "l4_div_ck",
.addr = omap44xx_i2c1_addrs, .addr = omap44xx_i2c1_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_i2c1_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -2166,9 +2170,7 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = { ...@@ -2166,9 +2170,7 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = {
.class = &omap44xx_i2c_hwmod_class, .class = &omap44xx_i2c_hwmod_class,
.flags = HWMOD_INIT_NO_RESET, .flags = HWMOD_INIT_NO_RESET,
.mpu_irqs = omap44xx_i2c1_irqs, .mpu_irqs = omap44xx_i2c1_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c1_irqs),
.sdma_reqs = omap44xx_i2c1_sdma_reqs, .sdma_reqs = omap44xx_i2c1_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c1_sdma_reqs),
.main_clk = "i2c1_fck", .main_clk = "i2c1_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -2184,11 +2186,13 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = { ...@@ -2184,11 +2186,13 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = {
static struct omap_hwmod omap44xx_i2c2_hwmod; static struct omap_hwmod omap44xx_i2c2_hwmod;
static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = { static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
{ .irq = 57 + OMAP44XX_IRQ_GIC_START }, { .irq = 57 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = { static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
{ .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START }, { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
{ .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START }, { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
{ .dma_req = -1 }
}; };
static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = { static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
...@@ -2197,6 +2201,7 @@ static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = { ...@@ -2197,6 +2201,7 @@ static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
.pa_end = 0x480720ff, .pa_end = 0x480720ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_per -> i2c2 */ /* l4_per -> i2c2 */
...@@ -2205,7 +2210,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = { ...@@ -2205,7 +2210,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
.slave = &omap44xx_i2c2_hwmod, .slave = &omap44xx_i2c2_hwmod,
.clk = "l4_div_ck", .clk = "l4_div_ck",
.addr = omap44xx_i2c2_addrs, .addr = omap44xx_i2c2_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_i2c2_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -2219,9 +2223,7 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = { ...@@ -2219,9 +2223,7 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = {
.class = &omap44xx_i2c_hwmod_class, .class = &omap44xx_i2c_hwmod_class,
.flags = HWMOD_INIT_NO_RESET, .flags = HWMOD_INIT_NO_RESET,
.mpu_irqs = omap44xx_i2c2_irqs, .mpu_irqs = omap44xx_i2c2_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c2_irqs),
.sdma_reqs = omap44xx_i2c2_sdma_reqs, .sdma_reqs = omap44xx_i2c2_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c2_sdma_reqs),
.main_clk = "i2c2_fck", .main_clk = "i2c2_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -2237,11 +2239,13 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = { ...@@ -2237,11 +2239,13 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = {
static struct omap_hwmod omap44xx_i2c3_hwmod; static struct omap_hwmod omap44xx_i2c3_hwmod;
static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = { static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
{ .irq = 61 + OMAP44XX_IRQ_GIC_START }, { .irq = 61 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = { static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
{ .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START }, { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
{ .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START }, { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
{ .dma_req = -1 }
}; };
static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = { static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
...@@ -2250,6 +2254,7 @@ static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = { ...@@ -2250,6 +2254,7 @@ static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
.pa_end = 0x480600ff, .pa_end = 0x480600ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_per -> i2c3 */ /* l4_per -> i2c3 */
...@@ -2258,7 +2263,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = { ...@@ -2258,7 +2263,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
.slave = &omap44xx_i2c3_hwmod, .slave = &omap44xx_i2c3_hwmod,
.clk = "l4_div_ck", .clk = "l4_div_ck",
.addr = omap44xx_i2c3_addrs, .addr = omap44xx_i2c3_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_i2c3_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -2272,9 +2276,7 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = { ...@@ -2272,9 +2276,7 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = {
.class = &omap44xx_i2c_hwmod_class, .class = &omap44xx_i2c_hwmod_class,
.flags = HWMOD_INIT_NO_RESET, .flags = HWMOD_INIT_NO_RESET,
.mpu_irqs = omap44xx_i2c3_irqs, .mpu_irqs = omap44xx_i2c3_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c3_irqs),
.sdma_reqs = omap44xx_i2c3_sdma_reqs, .sdma_reqs = omap44xx_i2c3_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c3_sdma_reqs),
.main_clk = "i2c3_fck", .main_clk = "i2c3_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -2290,11 +2292,13 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = { ...@@ -2290,11 +2292,13 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = {
static struct omap_hwmod omap44xx_i2c4_hwmod; static struct omap_hwmod omap44xx_i2c4_hwmod;
static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = { static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
{ .irq = 62 + OMAP44XX_IRQ_GIC_START }, { .irq = 62 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = { static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
{ .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START }, { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
{ .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START }, { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
{ .dma_req = -1 }
}; };
static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = { static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
...@@ -2303,6 +2307,7 @@ static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = { ...@@ -2303,6 +2307,7 @@ static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
.pa_end = 0x483500ff, .pa_end = 0x483500ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_per -> i2c4 */ /* l4_per -> i2c4 */
...@@ -2311,7 +2316,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = { ...@@ -2311,7 +2316,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
.slave = &omap44xx_i2c4_hwmod, .slave = &omap44xx_i2c4_hwmod,
.clk = "l4_div_ck", .clk = "l4_div_ck",
.addr = omap44xx_i2c4_addrs, .addr = omap44xx_i2c4_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_i2c4_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -2325,9 +2329,7 @@ static struct omap_hwmod omap44xx_i2c4_hwmod = { ...@@ -2325,9 +2329,7 @@ static struct omap_hwmod omap44xx_i2c4_hwmod = {
.class = &omap44xx_i2c_hwmod_class, .class = &omap44xx_i2c_hwmod_class,
.flags = HWMOD_INIT_NO_RESET, .flags = HWMOD_INIT_NO_RESET,
.mpu_irqs = omap44xx_i2c4_irqs, .mpu_irqs = omap44xx_i2c4_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c4_irqs),
.sdma_reqs = omap44xx_i2c4_sdma_reqs, .sdma_reqs = omap44xx_i2c4_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c4_sdma_reqs),
.main_clk = "i2c4_fck", .main_clk = "i2c4_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -2351,6 +2353,7 @@ static struct omap_hwmod_class omap44xx_ipu_hwmod_class = { ...@@ -2351,6 +2353,7 @@ static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
/* ipu */ /* ipu */
static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = { static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
{ .irq = 100 + OMAP44XX_IRQ_GIC_START }, { .irq = 100 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = { static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = {
...@@ -2390,7 +2393,7 @@ static struct omap_hwmod omap44xx_ipu_c0_hwmod = { ...@@ -2390,7 +2393,7 @@ static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
.flags = HWMOD_INIT_NO_RESET, .flags = HWMOD_INIT_NO_RESET,
.rst_lines = omap44xx_ipu_c0_resets, .rst_lines = omap44xx_ipu_c0_resets,
.rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c0_resets), .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c0_resets),
.prcm = { .prcm = {
.omap4 = { .omap4 = {
.rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL, .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
}, },
...@@ -2405,7 +2408,7 @@ static struct omap_hwmod omap44xx_ipu_c1_hwmod = { ...@@ -2405,7 +2408,7 @@ static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
.flags = HWMOD_INIT_NO_RESET, .flags = HWMOD_INIT_NO_RESET,
.rst_lines = omap44xx_ipu_c1_resets, .rst_lines = omap44xx_ipu_c1_resets,
.rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c1_resets), .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c1_resets),
.prcm = { .prcm = {
.omap4 = { .omap4 = {
.rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL, .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
}, },
...@@ -2417,11 +2420,10 @@ static struct omap_hwmod omap44xx_ipu_hwmod = { ...@@ -2417,11 +2420,10 @@ static struct omap_hwmod omap44xx_ipu_hwmod = {
.name = "ipu", .name = "ipu",
.class = &omap44xx_ipu_hwmod_class, .class = &omap44xx_ipu_hwmod_class,
.mpu_irqs = omap44xx_ipu_irqs, .mpu_irqs = omap44xx_ipu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_ipu_irqs),
.rst_lines = omap44xx_ipu_resets, .rst_lines = omap44xx_ipu_resets,
.rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets), .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets),
.main_clk = "ipu_fck", .main_clk = "ipu_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
.clkctrl_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL, .clkctrl_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
.rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL, .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
...@@ -2446,7 +2448,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = { ...@@ -2446,7 +2448,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
MSTANDBY_SMART), MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type2, .sysc_fields = &omap_hwmod_sysc_type2,
}; };
...@@ -2458,6 +2460,7 @@ static struct omap_hwmod_class omap44xx_iss_hwmod_class = { ...@@ -2458,6 +2460,7 @@ static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
/* iss */ /* iss */
static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = { static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
{ .irq = 24 + OMAP44XX_IRQ_GIC_START }, { .irq = 24 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = { static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
...@@ -2465,6 +2468,7 @@ static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = { ...@@ -2465,6 +2468,7 @@ static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
{ .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START }, { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
{ .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START }, { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
{ .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START }, { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
{ .dma_req = -1 }
}; };
/* iss master ports */ /* iss master ports */
...@@ -2478,6 +2482,7 @@ static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = { ...@@ -2478,6 +2482,7 @@ static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
.pa_end = 0x520000ff, .pa_end = 0x520000ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l3_main_2 -> iss */ /* l3_main_2 -> iss */
...@@ -2486,7 +2491,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = { ...@@ -2486,7 +2491,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
.slave = &omap44xx_iss_hwmod, .slave = &omap44xx_iss_hwmod,
.clk = "l3_div_ck", .clk = "l3_div_ck",
.addr = omap44xx_iss_addrs, .addr = omap44xx_iss_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_iss_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -2503,11 +2507,9 @@ static struct omap_hwmod omap44xx_iss_hwmod = { ...@@ -2503,11 +2507,9 @@ static struct omap_hwmod omap44xx_iss_hwmod = {
.name = "iss", .name = "iss",
.class = &omap44xx_iss_hwmod_class, .class = &omap44xx_iss_hwmod_class,
.mpu_irqs = omap44xx_iss_irqs, .mpu_irqs = omap44xx_iss_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_iss_irqs),
.sdma_reqs = omap44xx_iss_sdma_reqs, .sdma_reqs = omap44xx_iss_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_iss_sdma_reqs),
.main_clk = "iss_fck", .main_clk = "iss_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
.clkctrl_reg = OMAP4430_CM_CAM_ISS_CLKCTRL, .clkctrl_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
}, },
...@@ -2535,6 +2537,7 @@ static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = { ...@@ -2535,6 +2537,7 @@ static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
{ .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START }, { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
{ .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START }, { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
{ .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START }, { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_rst_info omap44xx_iva_resets[] = { static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
...@@ -2561,6 +2564,7 @@ static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = { ...@@ -2561,6 +2564,7 @@ static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
.pa_end = 0x5a07ffff, .pa_end = 0x5a07ffff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l3_main_2 -> iva */ /* l3_main_2 -> iva */
...@@ -2569,7 +2573,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = { ...@@ -2569,7 +2573,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
.slave = &omap44xx_iva_hwmod, .slave = &omap44xx_iva_hwmod,
.clk = "l3_div_ck", .clk = "l3_div_ck",
.addr = omap44xx_iva_addrs, .addr = omap44xx_iva_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_iva_addrs),
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
...@@ -2613,7 +2616,6 @@ static struct omap_hwmod omap44xx_iva_hwmod = { ...@@ -2613,7 +2616,6 @@ static struct omap_hwmod omap44xx_iva_hwmod = {
.name = "iva", .name = "iva",
.class = &omap44xx_iva_hwmod_class, .class = &omap44xx_iva_hwmod_class,
.mpu_irqs = omap44xx_iva_irqs, .mpu_irqs = omap44xx_iva_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_iva_irqs),
.rst_lines = omap44xx_iva_resets, .rst_lines = omap44xx_iva_resets,
.rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets), .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets),
.main_clk = "iva_fck", .main_clk = "iva_fck",
...@@ -2656,6 +2658,7 @@ static struct omap_hwmod_class omap44xx_kbd_hwmod_class = { ...@@ -2656,6 +2658,7 @@ static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
static struct omap_hwmod omap44xx_kbd_hwmod; static struct omap_hwmod omap44xx_kbd_hwmod;
static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = { static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
{ .irq = 120 + OMAP44XX_IRQ_GIC_START }, { .irq = 120 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = { static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
...@@ -2664,6 +2667,7 @@ static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = { ...@@ -2664,6 +2667,7 @@ static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
.pa_end = 0x4a31c07f, .pa_end = 0x4a31c07f,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_wkup -> kbd */ /* l4_wkup -> kbd */
...@@ -2672,7 +2676,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = { ...@@ -2672,7 +2676,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
.slave = &omap44xx_kbd_hwmod, .slave = &omap44xx_kbd_hwmod,
.clk = "l4_wkup_clk_mux_ck", .clk = "l4_wkup_clk_mux_ck",
.addr = omap44xx_kbd_addrs, .addr = omap44xx_kbd_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_kbd_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -2685,9 +2688,8 @@ static struct omap_hwmod omap44xx_kbd_hwmod = { ...@@ -2685,9 +2688,8 @@ static struct omap_hwmod omap44xx_kbd_hwmod = {
.name = "kbd", .name = "kbd",
.class = &omap44xx_kbd_hwmod_class, .class = &omap44xx_kbd_hwmod_class,
.mpu_irqs = omap44xx_kbd_irqs, .mpu_irqs = omap44xx_kbd_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_kbd_irqs),
.main_clk = "kbd_fck", .main_clk = "kbd_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
.clkctrl_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL, .clkctrl_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
}, },
...@@ -2721,6 +2723,7 @@ static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = { ...@@ -2721,6 +2723,7 @@ static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
static struct omap_hwmod omap44xx_mailbox_hwmod; static struct omap_hwmod omap44xx_mailbox_hwmod;
static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = { static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
{ .irq = 26 + OMAP44XX_IRQ_GIC_START }, { .irq = 26 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = { static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
...@@ -2729,6 +2732,7 @@ static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = { ...@@ -2729,6 +2732,7 @@ static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
.pa_end = 0x4a0f41ff, .pa_end = 0x4a0f41ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_cfg -> mailbox */ /* l4_cfg -> mailbox */
...@@ -2737,7 +2741,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = { ...@@ -2737,7 +2741,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
.slave = &omap44xx_mailbox_hwmod, .slave = &omap44xx_mailbox_hwmod,
.clk = "l4_div_ck", .clk = "l4_div_ck",
.addr = omap44xx_mailbox_addrs, .addr = omap44xx_mailbox_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_mailbox_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -2750,8 +2753,7 @@ static struct omap_hwmod omap44xx_mailbox_hwmod = { ...@@ -2750,8 +2753,7 @@ static struct omap_hwmod omap44xx_mailbox_hwmod = {
.name = "mailbox", .name = "mailbox",
.class = &omap44xx_mailbox_hwmod_class, .class = &omap44xx_mailbox_hwmod_class,
.mpu_irqs = omap44xx_mailbox_irqs, .mpu_irqs = omap44xx_mailbox_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mailbox_irqs), .prcm = {
.prcm = {
.omap4 = { .omap4 = {
.clkctrl_reg = OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL, .clkctrl_reg = OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL,
}, },
...@@ -2784,11 +2786,13 @@ static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = { ...@@ -2784,11 +2786,13 @@ static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
static struct omap_hwmod omap44xx_mcbsp1_hwmod; static struct omap_hwmod omap44xx_mcbsp1_hwmod;
static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = { static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
{ .irq = 17 + OMAP44XX_IRQ_GIC_START }, { .irq = 17 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = { static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
{ .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START }, { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
{ .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START }, { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
{ .dma_req = -1 }
}; };
static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = { static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
...@@ -2798,6 +2802,7 @@ static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = { ...@@ -2798,6 +2802,7 @@ static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
.pa_end = 0x401220ff, .pa_end = 0x401220ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_abe -> mcbsp1 */ /* l4_abe -> mcbsp1 */
...@@ -2806,7 +2811,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = { ...@@ -2806,7 +2811,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
.slave = &omap44xx_mcbsp1_hwmod, .slave = &omap44xx_mcbsp1_hwmod,
.clk = "ocp_abe_iclk", .clk = "ocp_abe_iclk",
.addr = omap44xx_mcbsp1_addrs, .addr = omap44xx_mcbsp1_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_mcbsp1_addrs),
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
...@@ -2817,6 +2821,7 @@ static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = { ...@@ -2817,6 +2821,7 @@ static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
.pa_end = 0x490220ff, .pa_end = 0x490220ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_abe -> mcbsp1 (dma) */ /* l4_abe -> mcbsp1 (dma) */
...@@ -2825,7 +2830,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = { ...@@ -2825,7 +2830,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
.slave = &omap44xx_mcbsp1_hwmod, .slave = &omap44xx_mcbsp1_hwmod,
.clk = "ocp_abe_iclk", .clk = "ocp_abe_iclk",
.addr = omap44xx_mcbsp1_dma_addrs, .addr = omap44xx_mcbsp1_dma_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_mcbsp1_dma_addrs),
.user = OCP_USER_SDMA, .user = OCP_USER_SDMA,
}; };
...@@ -2839,9 +2843,7 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = { ...@@ -2839,9 +2843,7 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
.name = "mcbsp1", .name = "mcbsp1",
.class = &omap44xx_mcbsp_hwmod_class, .class = &omap44xx_mcbsp_hwmod_class,
.mpu_irqs = omap44xx_mcbsp1_irqs, .mpu_irqs = omap44xx_mcbsp1_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp1_irqs),
.sdma_reqs = omap44xx_mcbsp1_sdma_reqs, .sdma_reqs = omap44xx_mcbsp1_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp1_sdma_reqs),
.main_clk = "mcbsp1_fck", .main_clk = "mcbsp1_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -2857,11 +2859,13 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = { ...@@ -2857,11 +2859,13 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
static struct omap_hwmod omap44xx_mcbsp2_hwmod; static struct omap_hwmod omap44xx_mcbsp2_hwmod;
static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = { static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
{ .irq = 22 + OMAP44XX_IRQ_GIC_START }, { .irq = 22 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = { static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
{ .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START }, { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
{ .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START }, { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
{ .dma_req = -1 }
}; };
static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = { static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
...@@ -2871,6 +2875,7 @@ static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = { ...@@ -2871,6 +2875,7 @@ static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
.pa_end = 0x401240ff, .pa_end = 0x401240ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_abe -> mcbsp2 */ /* l4_abe -> mcbsp2 */
...@@ -2879,7 +2884,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = { ...@@ -2879,7 +2884,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
.slave = &omap44xx_mcbsp2_hwmod, .slave = &omap44xx_mcbsp2_hwmod,
.clk = "ocp_abe_iclk", .clk = "ocp_abe_iclk",
.addr = omap44xx_mcbsp2_addrs, .addr = omap44xx_mcbsp2_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_mcbsp2_addrs),
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
...@@ -2890,6 +2894,7 @@ static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = { ...@@ -2890,6 +2894,7 @@ static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
.pa_end = 0x490240ff, .pa_end = 0x490240ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_abe -> mcbsp2 (dma) */ /* l4_abe -> mcbsp2 (dma) */
...@@ -2898,7 +2903,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = { ...@@ -2898,7 +2903,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
.slave = &omap44xx_mcbsp2_hwmod, .slave = &omap44xx_mcbsp2_hwmod,
.clk = "ocp_abe_iclk", .clk = "ocp_abe_iclk",
.addr = omap44xx_mcbsp2_dma_addrs, .addr = omap44xx_mcbsp2_dma_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_mcbsp2_dma_addrs),
.user = OCP_USER_SDMA, .user = OCP_USER_SDMA,
}; };
...@@ -2912,9 +2916,7 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = { ...@@ -2912,9 +2916,7 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
.name = "mcbsp2", .name = "mcbsp2",
.class = &omap44xx_mcbsp_hwmod_class, .class = &omap44xx_mcbsp_hwmod_class,
.mpu_irqs = omap44xx_mcbsp2_irqs, .mpu_irqs = omap44xx_mcbsp2_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp2_irqs),
.sdma_reqs = omap44xx_mcbsp2_sdma_reqs, .sdma_reqs = omap44xx_mcbsp2_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp2_sdma_reqs),
.main_clk = "mcbsp2_fck", .main_clk = "mcbsp2_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -2930,11 +2932,13 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = { ...@@ -2930,11 +2932,13 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
static struct omap_hwmod omap44xx_mcbsp3_hwmod; static struct omap_hwmod omap44xx_mcbsp3_hwmod;
static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = { static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
{ .irq = 23 + OMAP44XX_IRQ_GIC_START }, { .irq = 23 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = { static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
{ .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START }, { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
{ .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START }, { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
{ .dma_req = -1 }
}; };
static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = { static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
...@@ -2944,6 +2948,7 @@ static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = { ...@@ -2944,6 +2948,7 @@ static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
.pa_end = 0x401260ff, .pa_end = 0x401260ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_abe -> mcbsp3 */ /* l4_abe -> mcbsp3 */
...@@ -2952,7 +2957,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = { ...@@ -2952,7 +2957,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
.slave = &omap44xx_mcbsp3_hwmod, .slave = &omap44xx_mcbsp3_hwmod,
.clk = "ocp_abe_iclk", .clk = "ocp_abe_iclk",
.addr = omap44xx_mcbsp3_addrs, .addr = omap44xx_mcbsp3_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_mcbsp3_addrs),
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
...@@ -2963,6 +2967,7 @@ static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = { ...@@ -2963,6 +2967,7 @@ static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
.pa_end = 0x490260ff, .pa_end = 0x490260ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_abe -> mcbsp3 (dma) */ /* l4_abe -> mcbsp3 (dma) */
...@@ -2971,7 +2976,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = { ...@@ -2971,7 +2976,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
.slave = &omap44xx_mcbsp3_hwmod, .slave = &omap44xx_mcbsp3_hwmod,
.clk = "ocp_abe_iclk", .clk = "ocp_abe_iclk",
.addr = omap44xx_mcbsp3_dma_addrs, .addr = omap44xx_mcbsp3_dma_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_mcbsp3_dma_addrs),
.user = OCP_USER_SDMA, .user = OCP_USER_SDMA,
}; };
...@@ -2985,9 +2989,7 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = { ...@@ -2985,9 +2989,7 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
.name = "mcbsp3", .name = "mcbsp3",
.class = &omap44xx_mcbsp_hwmod_class, .class = &omap44xx_mcbsp_hwmod_class,
.mpu_irqs = omap44xx_mcbsp3_irqs, .mpu_irqs = omap44xx_mcbsp3_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp3_irqs),
.sdma_reqs = omap44xx_mcbsp3_sdma_reqs, .sdma_reqs = omap44xx_mcbsp3_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp3_sdma_reqs),
.main_clk = "mcbsp3_fck", .main_clk = "mcbsp3_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -3003,11 +3005,13 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = { ...@@ -3003,11 +3005,13 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
static struct omap_hwmod omap44xx_mcbsp4_hwmod; static struct omap_hwmod omap44xx_mcbsp4_hwmod;
static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = { static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
{ .irq = 16 + OMAP44XX_IRQ_GIC_START }, { .irq = 16 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = { static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
{ .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START }, { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
{ .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START }, { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
{ .dma_req = -1 }
}; };
static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = { static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
...@@ -3016,6 +3020,7 @@ static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = { ...@@ -3016,6 +3020,7 @@ static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
.pa_end = 0x480960ff, .pa_end = 0x480960ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_per -> mcbsp4 */ /* l4_per -> mcbsp4 */
...@@ -3024,7 +3029,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = { ...@@ -3024,7 +3029,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
.slave = &omap44xx_mcbsp4_hwmod, .slave = &omap44xx_mcbsp4_hwmod,
.clk = "l4_div_ck", .clk = "l4_div_ck",
.addr = omap44xx_mcbsp4_addrs, .addr = omap44xx_mcbsp4_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_mcbsp4_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -3037,9 +3041,7 @@ static struct omap_hwmod omap44xx_mcbsp4_hwmod = { ...@@ -3037,9 +3041,7 @@ static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
.name = "mcbsp4", .name = "mcbsp4",
.class = &omap44xx_mcbsp_hwmod_class, .class = &omap44xx_mcbsp_hwmod_class,
.mpu_irqs = omap44xx_mcbsp4_irqs, .mpu_irqs = omap44xx_mcbsp4_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp4_irqs),
.sdma_reqs = omap44xx_mcbsp4_sdma_reqs, .sdma_reqs = omap44xx_mcbsp4_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp4_sdma_reqs),
.main_clk = "mcbsp4_fck", .main_clk = "mcbsp4_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -3076,11 +3078,13 @@ static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = { ...@@ -3076,11 +3078,13 @@ static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
static struct omap_hwmod omap44xx_mcpdm_hwmod; static struct omap_hwmod omap44xx_mcpdm_hwmod;
static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = { static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
{ .irq = 112 + OMAP44XX_IRQ_GIC_START }, { .irq = 112 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = { static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
{ .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START }, { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
{ .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START }, { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
{ .dma_req = -1 }
}; };
static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = { static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
...@@ -3089,6 +3093,7 @@ static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = { ...@@ -3089,6 +3093,7 @@ static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
.pa_end = 0x4013207f, .pa_end = 0x4013207f,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_abe -> mcpdm */ /* l4_abe -> mcpdm */
...@@ -3097,7 +3102,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = { ...@@ -3097,7 +3102,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
.slave = &omap44xx_mcpdm_hwmod, .slave = &omap44xx_mcpdm_hwmod,
.clk = "ocp_abe_iclk", .clk = "ocp_abe_iclk",
.addr = omap44xx_mcpdm_addrs, .addr = omap44xx_mcpdm_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_mcpdm_addrs),
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
...@@ -3107,6 +3111,7 @@ static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = { ...@@ -3107,6 +3111,7 @@ static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
.pa_end = 0x4903207f, .pa_end = 0x4903207f,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_abe -> mcpdm (dma) */ /* l4_abe -> mcpdm (dma) */
...@@ -3115,7 +3120,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = { ...@@ -3115,7 +3120,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
.slave = &omap44xx_mcpdm_hwmod, .slave = &omap44xx_mcpdm_hwmod,
.clk = "ocp_abe_iclk", .clk = "ocp_abe_iclk",
.addr = omap44xx_mcpdm_dma_addrs, .addr = omap44xx_mcpdm_dma_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_mcpdm_dma_addrs),
.user = OCP_USER_SDMA, .user = OCP_USER_SDMA,
}; };
...@@ -3129,11 +3133,9 @@ static struct omap_hwmod omap44xx_mcpdm_hwmod = { ...@@ -3129,11 +3133,9 @@ static struct omap_hwmod omap44xx_mcpdm_hwmod = {
.name = "mcpdm", .name = "mcpdm",
.class = &omap44xx_mcpdm_hwmod_class, .class = &omap44xx_mcpdm_hwmod_class,
.mpu_irqs = omap44xx_mcpdm_irqs, .mpu_irqs = omap44xx_mcpdm_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcpdm_irqs),
.sdma_reqs = omap44xx_mcpdm_sdma_reqs, .sdma_reqs = omap44xx_mcpdm_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcpdm_sdma_reqs),
.main_clk = "mcpdm_fck", .main_clk = "mcpdm_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
.clkctrl_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL, .clkctrl_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL,
}, },
...@@ -3169,6 +3171,7 @@ static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = { ...@@ -3169,6 +3171,7 @@ static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
static struct omap_hwmod omap44xx_mcspi1_hwmod; static struct omap_hwmod omap44xx_mcspi1_hwmod;
static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = { static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
{ .irq = 65 + OMAP44XX_IRQ_GIC_START }, { .irq = 65 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = { static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
...@@ -3180,6 +3183,7 @@ static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = { ...@@ -3180,6 +3183,7 @@ static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
{ .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START }, { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
{ .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START }, { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
{ .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START }, { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
{ .dma_req = -1 }
}; };
static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = { static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
...@@ -3188,6 +3192,7 @@ static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = { ...@@ -3188,6 +3192,7 @@ static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
.pa_end = 0x480981ff, .pa_end = 0x480981ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_per -> mcspi1 */ /* l4_per -> mcspi1 */
...@@ -3196,7 +3201,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = { ...@@ -3196,7 +3201,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
.slave = &omap44xx_mcspi1_hwmod, .slave = &omap44xx_mcspi1_hwmod,
.clk = "l4_div_ck", .clk = "l4_div_ck",
.addr = omap44xx_mcspi1_addrs, .addr = omap44xx_mcspi1_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_mcspi1_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -3214,9 +3218,7 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = { ...@@ -3214,9 +3218,7 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = {
.name = "mcspi1", .name = "mcspi1",
.class = &omap44xx_mcspi_hwmod_class, .class = &omap44xx_mcspi_hwmod_class,
.mpu_irqs = omap44xx_mcspi1_irqs, .mpu_irqs = omap44xx_mcspi1_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi1_irqs),
.sdma_reqs = omap44xx_mcspi1_sdma_reqs, .sdma_reqs = omap44xx_mcspi1_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi1_sdma_reqs),
.main_clk = "mcspi1_fck", .main_clk = "mcspi1_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -3233,6 +3235,7 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = { ...@@ -3233,6 +3235,7 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = {
static struct omap_hwmod omap44xx_mcspi2_hwmod; static struct omap_hwmod omap44xx_mcspi2_hwmod;
static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = { static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
{ .irq = 66 + OMAP44XX_IRQ_GIC_START }, { .irq = 66 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = { static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
...@@ -3240,6 +3243,7 @@ static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = { ...@@ -3240,6 +3243,7 @@ static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
{ .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START }, { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
{ .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START }, { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
{ .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START }, { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
{ .dma_req = -1 }
}; };
static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = { static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
...@@ -3248,6 +3252,7 @@ static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = { ...@@ -3248,6 +3252,7 @@ static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
.pa_end = 0x4809a1ff, .pa_end = 0x4809a1ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_per -> mcspi2 */ /* l4_per -> mcspi2 */
...@@ -3256,7 +3261,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = { ...@@ -3256,7 +3261,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
.slave = &omap44xx_mcspi2_hwmod, .slave = &omap44xx_mcspi2_hwmod,
.clk = "l4_div_ck", .clk = "l4_div_ck",
.addr = omap44xx_mcspi2_addrs, .addr = omap44xx_mcspi2_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_mcspi2_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -3274,9 +3278,7 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = { ...@@ -3274,9 +3278,7 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = {
.name = "mcspi2", .name = "mcspi2",
.class = &omap44xx_mcspi_hwmod_class, .class = &omap44xx_mcspi_hwmod_class,
.mpu_irqs = omap44xx_mcspi2_irqs, .mpu_irqs = omap44xx_mcspi2_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi2_irqs),
.sdma_reqs = omap44xx_mcspi2_sdma_reqs, .sdma_reqs = omap44xx_mcspi2_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi2_sdma_reqs),
.main_clk = "mcspi2_fck", .main_clk = "mcspi2_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -3293,6 +3295,7 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = { ...@@ -3293,6 +3295,7 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = {
static struct omap_hwmod omap44xx_mcspi3_hwmod; static struct omap_hwmod omap44xx_mcspi3_hwmod;
static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = { static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
{ .irq = 91 + OMAP44XX_IRQ_GIC_START }, { .irq = 91 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = { static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
...@@ -3300,6 +3303,7 @@ static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = { ...@@ -3300,6 +3303,7 @@ static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
{ .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START }, { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
{ .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START }, { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
{ .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START }, { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
{ .dma_req = -1 }
}; };
static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = { static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
...@@ -3308,6 +3312,7 @@ static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = { ...@@ -3308,6 +3312,7 @@ static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
.pa_end = 0x480b81ff, .pa_end = 0x480b81ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_per -> mcspi3 */ /* l4_per -> mcspi3 */
...@@ -3316,7 +3321,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = { ...@@ -3316,7 +3321,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
.slave = &omap44xx_mcspi3_hwmod, .slave = &omap44xx_mcspi3_hwmod,
.clk = "l4_div_ck", .clk = "l4_div_ck",
.addr = omap44xx_mcspi3_addrs, .addr = omap44xx_mcspi3_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_mcspi3_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -3334,9 +3338,7 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = { ...@@ -3334,9 +3338,7 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = {
.name = "mcspi3", .name = "mcspi3",
.class = &omap44xx_mcspi_hwmod_class, .class = &omap44xx_mcspi_hwmod_class,
.mpu_irqs = omap44xx_mcspi3_irqs, .mpu_irqs = omap44xx_mcspi3_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi3_irqs),
.sdma_reqs = omap44xx_mcspi3_sdma_reqs, .sdma_reqs = omap44xx_mcspi3_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi3_sdma_reqs),
.main_clk = "mcspi3_fck", .main_clk = "mcspi3_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -3353,11 +3355,13 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = { ...@@ -3353,11 +3355,13 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = {
static struct omap_hwmod omap44xx_mcspi4_hwmod; static struct omap_hwmod omap44xx_mcspi4_hwmod;
static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = { static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
{ .irq = 48 + OMAP44XX_IRQ_GIC_START }, { .irq = 48 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = { static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
{ .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START }, { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
{ .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START }, { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
{ .dma_req = -1 }
}; };
static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = { static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
...@@ -3366,6 +3370,7 @@ static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = { ...@@ -3366,6 +3370,7 @@ static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
.pa_end = 0x480ba1ff, .pa_end = 0x480ba1ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_per -> mcspi4 */ /* l4_per -> mcspi4 */
...@@ -3374,7 +3379,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = { ...@@ -3374,7 +3379,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
.slave = &omap44xx_mcspi4_hwmod, .slave = &omap44xx_mcspi4_hwmod,
.clk = "l4_div_ck", .clk = "l4_div_ck",
.addr = omap44xx_mcspi4_addrs, .addr = omap44xx_mcspi4_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_mcspi4_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -3392,9 +3396,7 @@ static struct omap_hwmod omap44xx_mcspi4_hwmod = { ...@@ -3392,9 +3396,7 @@ static struct omap_hwmod omap44xx_mcspi4_hwmod = {
.name = "mcspi4", .name = "mcspi4",
.class = &omap44xx_mcspi_hwmod_class, .class = &omap44xx_mcspi_hwmod_class,
.mpu_irqs = omap44xx_mcspi4_irqs, .mpu_irqs = omap44xx_mcspi4_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi4_irqs),
.sdma_reqs = omap44xx_mcspi4_sdma_reqs, .sdma_reqs = omap44xx_mcspi4_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi4_sdma_reqs),
.main_clk = "mcspi4_fck", .main_clk = "mcspi4_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -3420,7 +3422,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = { ...@@ -3420,7 +3422,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
SYSC_HAS_SOFTRESET), SYSC_HAS_SOFTRESET),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
MSTANDBY_SMART), MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type2, .sysc_fields = &omap_hwmod_sysc_type2,
}; };
...@@ -3430,14 +3432,15 @@ static struct omap_hwmod_class omap44xx_mmc_hwmod_class = { ...@@ -3430,14 +3432,15 @@ static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
}; };
/* mmc1 */ /* mmc1 */
static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = { static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
{ .irq = 83 + OMAP44XX_IRQ_GIC_START }, { .irq = 83 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = { static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
{ .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START }, { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
{ .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START }, { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
{ .dma_req = -1 }
}; };
/* mmc1 master ports */ /* mmc1 master ports */
...@@ -3451,6 +3454,7 @@ static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = { ...@@ -3451,6 +3454,7 @@ static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
.pa_end = 0x4809c3ff, .pa_end = 0x4809c3ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_per -> mmc1 */ /* l4_per -> mmc1 */
...@@ -3459,7 +3463,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = { ...@@ -3459,7 +3463,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
.slave = &omap44xx_mmc1_hwmod, .slave = &omap44xx_mmc1_hwmod,
.clk = "l4_div_ck", .clk = "l4_div_ck",
.addr = omap44xx_mmc1_addrs, .addr = omap44xx_mmc1_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_mmc1_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -3477,11 +3480,9 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = { ...@@ -3477,11 +3480,9 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = {
.name = "mmc1", .name = "mmc1",
.class = &omap44xx_mmc_hwmod_class, .class = &omap44xx_mmc_hwmod_class,
.mpu_irqs = omap44xx_mmc1_irqs, .mpu_irqs = omap44xx_mmc1_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc1_irqs),
.sdma_reqs = omap44xx_mmc1_sdma_reqs, .sdma_reqs = omap44xx_mmc1_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc1_sdma_reqs),
.main_clk = "mmc1_fck", .main_clk = "mmc1_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
.clkctrl_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL, .clkctrl_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
}, },
...@@ -3497,11 +3498,13 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = { ...@@ -3497,11 +3498,13 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = {
/* mmc2 */ /* mmc2 */
static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = { static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
{ .irq = 86 + OMAP44XX_IRQ_GIC_START }, { .irq = 86 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = { static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
{ .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START }, { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
{ .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START }, { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
{ .dma_req = -1 }
}; };
/* mmc2 master ports */ /* mmc2 master ports */
...@@ -3515,6 +3518,7 @@ static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = { ...@@ -3515,6 +3518,7 @@ static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
.pa_end = 0x480b43ff, .pa_end = 0x480b43ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_per -> mmc2 */ /* l4_per -> mmc2 */
...@@ -3523,7 +3527,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = { ...@@ -3523,7 +3527,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
.slave = &omap44xx_mmc2_hwmod, .slave = &omap44xx_mmc2_hwmod,
.clk = "l4_div_ck", .clk = "l4_div_ck",
.addr = omap44xx_mmc2_addrs, .addr = omap44xx_mmc2_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_mmc2_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -3536,11 +3539,9 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = { ...@@ -3536,11 +3539,9 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = {
.name = "mmc2", .name = "mmc2",
.class = &omap44xx_mmc_hwmod_class, .class = &omap44xx_mmc_hwmod_class,
.mpu_irqs = omap44xx_mmc2_irqs, .mpu_irqs = omap44xx_mmc2_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc2_irqs),
.sdma_reqs = omap44xx_mmc2_sdma_reqs, .sdma_reqs = omap44xx_mmc2_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc2_sdma_reqs),
.main_clk = "mmc2_fck", .main_clk = "mmc2_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
.clkctrl_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL, .clkctrl_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
}, },
...@@ -3556,11 +3557,13 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = { ...@@ -3556,11 +3557,13 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = {
static struct omap_hwmod omap44xx_mmc3_hwmod; static struct omap_hwmod omap44xx_mmc3_hwmod;
static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = { static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
{ .irq = 94 + OMAP44XX_IRQ_GIC_START }, { .irq = 94 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = { static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
{ .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START }, { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
{ .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START }, { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
{ .dma_req = -1 }
}; };
static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = { static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
...@@ -3569,6 +3572,7 @@ static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = { ...@@ -3569,6 +3572,7 @@ static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
.pa_end = 0x480ad3ff, .pa_end = 0x480ad3ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_per -> mmc3 */ /* l4_per -> mmc3 */
...@@ -3577,7 +3581,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = { ...@@ -3577,7 +3581,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
.slave = &omap44xx_mmc3_hwmod, .slave = &omap44xx_mmc3_hwmod,
.clk = "l4_div_ck", .clk = "l4_div_ck",
.addr = omap44xx_mmc3_addrs, .addr = omap44xx_mmc3_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_mmc3_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -3590,11 +3593,9 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = { ...@@ -3590,11 +3593,9 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = {
.name = "mmc3", .name = "mmc3",
.class = &omap44xx_mmc_hwmod_class, .class = &omap44xx_mmc_hwmod_class,
.mpu_irqs = omap44xx_mmc3_irqs, .mpu_irqs = omap44xx_mmc3_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc3_irqs),
.sdma_reqs = omap44xx_mmc3_sdma_reqs, .sdma_reqs = omap44xx_mmc3_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc3_sdma_reqs),
.main_clk = "mmc3_fck", .main_clk = "mmc3_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
.clkctrl_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL, .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
}, },
...@@ -3608,11 +3609,13 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = { ...@@ -3608,11 +3609,13 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = {
static struct omap_hwmod omap44xx_mmc4_hwmod; static struct omap_hwmod omap44xx_mmc4_hwmod;
static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = { static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
{ .irq = 96 + OMAP44XX_IRQ_GIC_START }, { .irq = 96 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = { static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
{ .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START }, { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
{ .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START }, { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
{ .dma_req = -1 }
}; };
static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = { static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
...@@ -3621,6 +3624,7 @@ static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = { ...@@ -3621,6 +3624,7 @@ static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
.pa_end = 0x480d13ff, .pa_end = 0x480d13ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_per -> mmc4 */ /* l4_per -> mmc4 */
...@@ -3629,7 +3633,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = { ...@@ -3629,7 +3633,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
.slave = &omap44xx_mmc4_hwmod, .slave = &omap44xx_mmc4_hwmod,
.clk = "l4_div_ck", .clk = "l4_div_ck",
.addr = omap44xx_mmc4_addrs, .addr = omap44xx_mmc4_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_mmc4_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -3642,11 +3645,10 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = { ...@@ -3642,11 +3645,10 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = {
.name = "mmc4", .name = "mmc4",
.class = &omap44xx_mmc_hwmod_class, .class = &omap44xx_mmc_hwmod_class,
.mpu_irqs = omap44xx_mmc4_irqs, .mpu_irqs = omap44xx_mmc4_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc4_irqs),
.sdma_reqs = omap44xx_mmc4_sdma_reqs, .sdma_reqs = omap44xx_mmc4_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc4_sdma_reqs),
.main_clk = "mmc4_fck", .main_clk = "mmc4_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
.clkctrl_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL, .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
}, },
...@@ -3660,11 +3662,13 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = { ...@@ -3660,11 +3662,13 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = {
static struct omap_hwmod omap44xx_mmc5_hwmod; static struct omap_hwmod omap44xx_mmc5_hwmod;
static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = { static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
{ .irq = 59 + OMAP44XX_IRQ_GIC_START }, { .irq = 59 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = { static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
{ .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START }, { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
{ .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START }, { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
{ .dma_req = -1 }
}; };
static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = { static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
...@@ -3673,6 +3677,7 @@ static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = { ...@@ -3673,6 +3677,7 @@ static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
.pa_end = 0x480d53ff, .pa_end = 0x480d53ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_per -> mmc5 */ /* l4_per -> mmc5 */
...@@ -3681,7 +3686,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = { ...@@ -3681,7 +3686,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
.slave = &omap44xx_mmc5_hwmod, .slave = &omap44xx_mmc5_hwmod,
.clk = "l4_div_ck", .clk = "l4_div_ck",
.addr = omap44xx_mmc5_addrs, .addr = omap44xx_mmc5_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_mmc5_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -3694,11 +3698,9 @@ static struct omap_hwmod omap44xx_mmc5_hwmod = { ...@@ -3694,11 +3698,9 @@ static struct omap_hwmod omap44xx_mmc5_hwmod = {
.name = "mmc5", .name = "mmc5",
.class = &omap44xx_mmc_hwmod_class, .class = &omap44xx_mmc_hwmod_class,
.mpu_irqs = omap44xx_mmc5_irqs, .mpu_irqs = omap44xx_mmc5_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc5_irqs),
.sdma_reqs = omap44xx_mmc5_sdma_reqs, .sdma_reqs = omap44xx_mmc5_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc5_sdma_reqs),
.main_clk = "mmc5_fck", .main_clk = "mmc5_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
.clkctrl_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL, .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
}, },
...@@ -3722,6 +3724,7 @@ static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = { ...@@ -3722,6 +3724,7 @@ static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
{ .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START }, { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
{ .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START }, { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
{ .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START }, { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
/* mpu master ports */ /* mpu master ports */
...@@ -3734,9 +3737,8 @@ static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = { ...@@ -3734,9 +3737,8 @@ static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
static struct omap_hwmod omap44xx_mpu_hwmod = { static struct omap_hwmod omap44xx_mpu_hwmod = {
.name = "mpu", .name = "mpu",
.class = &omap44xx_mpu_hwmod_class, .class = &omap44xx_mpu_hwmod_class,
.flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
.mpu_irqs = omap44xx_mpu_irqs, .mpu_irqs = omap44xx_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mpu_irqs),
.main_clk = "dpll_mpu_m2_ck", .main_clk = "dpll_mpu_m2_ck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -3778,6 +3780,7 @@ static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = { ...@@ -3778,6 +3780,7 @@ static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
static struct omap_hwmod omap44xx_smartreflex_core_hwmod; static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = { static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
{ .irq = 19 + OMAP44XX_IRQ_GIC_START }, { .irq = 19 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = { static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
...@@ -3786,6 +3789,7 @@ static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = { ...@@ -3786,6 +3789,7 @@ static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
.pa_end = 0x4a0dd03f, .pa_end = 0x4a0dd03f,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_cfg -> smartreflex_core */ /* l4_cfg -> smartreflex_core */
...@@ -3794,7 +3798,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = { ...@@ -3794,7 +3798,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
.slave = &omap44xx_smartreflex_core_hwmod, .slave = &omap44xx_smartreflex_core_hwmod,
.clk = "l4_div_ck", .clk = "l4_div_ck",
.addr = omap44xx_smartreflex_core_addrs, .addr = omap44xx_smartreflex_core_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -3807,7 +3810,7 @@ static struct omap_hwmod omap44xx_smartreflex_core_hwmod = { ...@@ -3807,7 +3810,7 @@ static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
.name = "smartreflex_core", .name = "smartreflex_core",
.class = &omap44xx_smartreflex_hwmod_class, .class = &omap44xx_smartreflex_hwmod_class,
.mpu_irqs = omap44xx_smartreflex_core_irqs, .mpu_irqs = omap44xx_smartreflex_core_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_irqs),
.main_clk = "smartreflex_core_fck", .main_clk = "smartreflex_core_fck",
.vdd_name = "core", .vdd_name = "core",
.prcm = { .prcm = {
...@@ -3824,6 +3827,7 @@ static struct omap_hwmod omap44xx_smartreflex_core_hwmod = { ...@@ -3824,6 +3827,7 @@ static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
static struct omap_hwmod omap44xx_smartreflex_iva_hwmod; static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = { static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
{ .irq = 102 + OMAP44XX_IRQ_GIC_START }, { .irq = 102 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = { static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
...@@ -3832,6 +3836,7 @@ static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = { ...@@ -3832,6 +3836,7 @@ static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
.pa_end = 0x4a0db03f, .pa_end = 0x4a0db03f,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_cfg -> smartreflex_iva */ /* l4_cfg -> smartreflex_iva */
...@@ -3840,7 +3845,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = { ...@@ -3840,7 +3845,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
.slave = &omap44xx_smartreflex_iva_hwmod, .slave = &omap44xx_smartreflex_iva_hwmod,
.clk = "l4_div_ck", .clk = "l4_div_ck",
.addr = omap44xx_smartreflex_iva_addrs, .addr = omap44xx_smartreflex_iva_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -3853,7 +3857,6 @@ static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = { ...@@ -3853,7 +3857,6 @@ static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
.name = "smartreflex_iva", .name = "smartreflex_iva",
.class = &omap44xx_smartreflex_hwmod_class, .class = &omap44xx_smartreflex_hwmod_class,
.mpu_irqs = omap44xx_smartreflex_iva_irqs, .mpu_irqs = omap44xx_smartreflex_iva_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_irqs),
.main_clk = "smartreflex_iva_fck", .main_clk = "smartreflex_iva_fck",
.vdd_name = "iva", .vdd_name = "iva",
.prcm = { .prcm = {
...@@ -3870,6 +3873,7 @@ static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = { ...@@ -3870,6 +3873,7 @@ static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod; static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = { static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
{ .irq = 18 + OMAP44XX_IRQ_GIC_START }, { .irq = 18 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = { static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
...@@ -3878,6 +3882,7 @@ static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = { ...@@ -3878,6 +3882,7 @@ static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
.pa_end = 0x4a0d903f, .pa_end = 0x4a0d903f,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_cfg -> smartreflex_mpu */ /* l4_cfg -> smartreflex_mpu */
...@@ -3886,7 +3891,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = { ...@@ -3886,7 +3891,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
.slave = &omap44xx_smartreflex_mpu_hwmod, .slave = &omap44xx_smartreflex_mpu_hwmod,
.clk = "l4_div_ck", .clk = "l4_div_ck",
.addr = omap44xx_smartreflex_mpu_addrs, .addr = omap44xx_smartreflex_mpu_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -3899,7 +3903,6 @@ static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = { ...@@ -3899,7 +3903,6 @@ static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
.name = "smartreflex_mpu", .name = "smartreflex_mpu",
.class = &omap44xx_smartreflex_hwmod_class, .class = &omap44xx_smartreflex_hwmod_class,
.mpu_irqs = omap44xx_smartreflex_mpu_irqs, .mpu_irqs = omap44xx_smartreflex_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_irqs),
.main_clk = "smartreflex_mpu_fck", .main_clk = "smartreflex_mpu_fck",
.vdd_name = "mpu", .vdd_name = "mpu",
.prcm = { .prcm = {
...@@ -3943,6 +3946,7 @@ static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = { ...@@ -3943,6 +3946,7 @@ static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
.pa_end = 0x4a0f6fff, .pa_end = 0x4a0f6fff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_cfg -> spinlock */ /* l4_cfg -> spinlock */
...@@ -3951,7 +3955,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = { ...@@ -3951,7 +3955,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
.slave = &omap44xx_spinlock_hwmod, .slave = &omap44xx_spinlock_hwmod,
.clk = "l4_div_ck", .clk = "l4_div_ck",
.addr = omap44xx_spinlock_addrs, .addr = omap44xx_spinlock_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_spinlock_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -4015,6 +4018,7 @@ static struct omap_hwmod_class omap44xx_timer_hwmod_class = { ...@@ -4015,6 +4018,7 @@ static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
static struct omap_hwmod omap44xx_timer1_hwmod; static struct omap_hwmod omap44xx_timer1_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = { static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
{ .irq = 37 + OMAP44XX_IRQ_GIC_START }, { .irq = 37 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = { static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
...@@ -4023,6 +4027,7 @@ static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = { ...@@ -4023,6 +4027,7 @@ static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
.pa_end = 0x4a31807f, .pa_end = 0x4a31807f,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_wkup -> timer1 */ /* l4_wkup -> timer1 */
...@@ -4031,7 +4036,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = { ...@@ -4031,7 +4036,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
.slave = &omap44xx_timer1_hwmod, .slave = &omap44xx_timer1_hwmod,
.clk = "l4_wkup_clk_mux_ck", .clk = "l4_wkup_clk_mux_ck",
.addr = omap44xx_timer1_addrs, .addr = omap44xx_timer1_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_timer1_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -4044,7 +4048,6 @@ static struct omap_hwmod omap44xx_timer1_hwmod = { ...@@ -4044,7 +4048,6 @@ static struct omap_hwmod omap44xx_timer1_hwmod = {
.name = "timer1", .name = "timer1",
.class = &omap44xx_timer_1ms_hwmod_class, .class = &omap44xx_timer_1ms_hwmod_class,
.mpu_irqs = omap44xx_timer1_irqs, .mpu_irqs = omap44xx_timer1_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer1_irqs),
.main_clk = "timer1_fck", .main_clk = "timer1_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -4060,6 +4063,7 @@ static struct omap_hwmod omap44xx_timer1_hwmod = { ...@@ -4060,6 +4063,7 @@ static struct omap_hwmod omap44xx_timer1_hwmod = {
static struct omap_hwmod omap44xx_timer2_hwmod; static struct omap_hwmod omap44xx_timer2_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = { static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
{ .irq = 38 + OMAP44XX_IRQ_GIC_START }, { .irq = 38 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = { static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
...@@ -4068,6 +4072,7 @@ static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = { ...@@ -4068,6 +4072,7 @@ static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
.pa_end = 0x4803207f, .pa_end = 0x4803207f,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_per -> timer2 */ /* l4_per -> timer2 */
...@@ -4076,7 +4081,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = { ...@@ -4076,7 +4081,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
.slave = &omap44xx_timer2_hwmod, .slave = &omap44xx_timer2_hwmod,
.clk = "l4_div_ck", .clk = "l4_div_ck",
.addr = omap44xx_timer2_addrs, .addr = omap44xx_timer2_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_timer2_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -4089,7 +4093,6 @@ static struct omap_hwmod omap44xx_timer2_hwmod = { ...@@ -4089,7 +4093,6 @@ static struct omap_hwmod omap44xx_timer2_hwmod = {
.name = "timer2", .name = "timer2",
.class = &omap44xx_timer_1ms_hwmod_class, .class = &omap44xx_timer_1ms_hwmod_class,
.mpu_irqs = omap44xx_timer2_irqs, .mpu_irqs = omap44xx_timer2_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer2_irqs),
.main_clk = "timer2_fck", .main_clk = "timer2_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -4105,6 +4108,7 @@ static struct omap_hwmod omap44xx_timer2_hwmod = { ...@@ -4105,6 +4108,7 @@ static struct omap_hwmod omap44xx_timer2_hwmod = {
static struct omap_hwmod omap44xx_timer3_hwmod; static struct omap_hwmod omap44xx_timer3_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = { static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
{ .irq = 39 + OMAP44XX_IRQ_GIC_START }, { .irq = 39 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = { static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
...@@ -4113,6 +4117,7 @@ static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = { ...@@ -4113,6 +4117,7 @@ static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
.pa_end = 0x4803407f, .pa_end = 0x4803407f,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_per -> timer3 */ /* l4_per -> timer3 */
...@@ -4121,7 +4126,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = { ...@@ -4121,7 +4126,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
.slave = &omap44xx_timer3_hwmod, .slave = &omap44xx_timer3_hwmod,
.clk = "l4_div_ck", .clk = "l4_div_ck",
.addr = omap44xx_timer3_addrs, .addr = omap44xx_timer3_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_timer3_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -4134,7 +4138,6 @@ static struct omap_hwmod omap44xx_timer3_hwmod = { ...@@ -4134,7 +4138,6 @@ static struct omap_hwmod omap44xx_timer3_hwmod = {
.name = "timer3", .name = "timer3",
.class = &omap44xx_timer_hwmod_class, .class = &omap44xx_timer_hwmod_class,
.mpu_irqs = omap44xx_timer3_irqs, .mpu_irqs = omap44xx_timer3_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer3_irqs),
.main_clk = "timer3_fck", .main_clk = "timer3_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -4150,6 +4153,7 @@ static struct omap_hwmod omap44xx_timer3_hwmod = { ...@@ -4150,6 +4153,7 @@ static struct omap_hwmod omap44xx_timer3_hwmod = {
static struct omap_hwmod omap44xx_timer4_hwmod; static struct omap_hwmod omap44xx_timer4_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = { static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
{ .irq = 40 + OMAP44XX_IRQ_GIC_START }, { .irq = 40 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = { static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
...@@ -4158,6 +4162,7 @@ static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = { ...@@ -4158,6 +4162,7 @@ static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
.pa_end = 0x4803607f, .pa_end = 0x4803607f,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_per -> timer4 */ /* l4_per -> timer4 */
...@@ -4166,7 +4171,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = { ...@@ -4166,7 +4171,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
.slave = &omap44xx_timer4_hwmod, .slave = &omap44xx_timer4_hwmod,
.clk = "l4_div_ck", .clk = "l4_div_ck",
.addr = omap44xx_timer4_addrs, .addr = omap44xx_timer4_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_timer4_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -4179,7 +4183,6 @@ static struct omap_hwmod omap44xx_timer4_hwmod = { ...@@ -4179,7 +4183,6 @@ static struct omap_hwmod omap44xx_timer4_hwmod = {
.name = "timer4", .name = "timer4",
.class = &omap44xx_timer_hwmod_class, .class = &omap44xx_timer_hwmod_class,
.mpu_irqs = omap44xx_timer4_irqs, .mpu_irqs = omap44xx_timer4_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer4_irqs),
.main_clk = "timer4_fck", .main_clk = "timer4_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -4195,6 +4198,7 @@ static struct omap_hwmod omap44xx_timer4_hwmod = { ...@@ -4195,6 +4198,7 @@ static struct omap_hwmod omap44xx_timer4_hwmod = {
static struct omap_hwmod omap44xx_timer5_hwmod; static struct omap_hwmod omap44xx_timer5_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = { static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
{ .irq = 41 + OMAP44XX_IRQ_GIC_START }, { .irq = 41 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = { static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
...@@ -4203,6 +4207,7 @@ static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = { ...@@ -4203,6 +4207,7 @@ static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
.pa_end = 0x4013807f, .pa_end = 0x4013807f,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_abe -> timer5 */ /* l4_abe -> timer5 */
...@@ -4211,7 +4216,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = { ...@@ -4211,7 +4216,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
.slave = &omap44xx_timer5_hwmod, .slave = &omap44xx_timer5_hwmod,
.clk = "ocp_abe_iclk", .clk = "ocp_abe_iclk",
.addr = omap44xx_timer5_addrs, .addr = omap44xx_timer5_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_timer5_addrs),
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
...@@ -4221,6 +4225,7 @@ static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = { ...@@ -4221,6 +4225,7 @@ static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
.pa_end = 0x4903807f, .pa_end = 0x4903807f,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_abe -> timer5 (dma) */ /* l4_abe -> timer5 (dma) */
...@@ -4229,7 +4234,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = { ...@@ -4229,7 +4234,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
.slave = &omap44xx_timer5_hwmod, .slave = &omap44xx_timer5_hwmod,
.clk = "ocp_abe_iclk", .clk = "ocp_abe_iclk",
.addr = omap44xx_timer5_dma_addrs, .addr = omap44xx_timer5_dma_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_timer5_dma_addrs),
.user = OCP_USER_SDMA, .user = OCP_USER_SDMA,
}; };
...@@ -4243,7 +4247,6 @@ static struct omap_hwmod omap44xx_timer5_hwmod = { ...@@ -4243,7 +4247,6 @@ static struct omap_hwmod omap44xx_timer5_hwmod = {
.name = "timer5", .name = "timer5",
.class = &omap44xx_timer_hwmod_class, .class = &omap44xx_timer_hwmod_class,
.mpu_irqs = omap44xx_timer5_irqs, .mpu_irqs = omap44xx_timer5_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer5_irqs),
.main_clk = "timer5_fck", .main_clk = "timer5_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -4259,6 +4262,7 @@ static struct omap_hwmod omap44xx_timer5_hwmod = { ...@@ -4259,6 +4262,7 @@ static struct omap_hwmod omap44xx_timer5_hwmod = {
static struct omap_hwmod omap44xx_timer6_hwmod; static struct omap_hwmod omap44xx_timer6_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = { static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
{ .irq = 42 + OMAP44XX_IRQ_GIC_START }, { .irq = 42 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = { static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
...@@ -4267,6 +4271,7 @@ static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = { ...@@ -4267,6 +4271,7 @@ static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
.pa_end = 0x4013a07f, .pa_end = 0x4013a07f,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_abe -> timer6 */ /* l4_abe -> timer6 */
...@@ -4275,7 +4280,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = { ...@@ -4275,7 +4280,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
.slave = &omap44xx_timer6_hwmod, .slave = &omap44xx_timer6_hwmod,
.clk = "ocp_abe_iclk", .clk = "ocp_abe_iclk",
.addr = omap44xx_timer6_addrs, .addr = omap44xx_timer6_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_timer6_addrs),
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
...@@ -4285,6 +4289,7 @@ static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = { ...@@ -4285,6 +4289,7 @@ static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
.pa_end = 0x4903a07f, .pa_end = 0x4903a07f,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_abe -> timer6 (dma) */ /* l4_abe -> timer6 (dma) */
...@@ -4293,7 +4298,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = { ...@@ -4293,7 +4298,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
.slave = &omap44xx_timer6_hwmod, .slave = &omap44xx_timer6_hwmod,
.clk = "ocp_abe_iclk", .clk = "ocp_abe_iclk",
.addr = omap44xx_timer6_dma_addrs, .addr = omap44xx_timer6_dma_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_timer6_dma_addrs),
.user = OCP_USER_SDMA, .user = OCP_USER_SDMA,
}; };
...@@ -4307,7 +4311,7 @@ static struct omap_hwmod omap44xx_timer6_hwmod = { ...@@ -4307,7 +4311,7 @@ static struct omap_hwmod omap44xx_timer6_hwmod = {
.name = "timer6", .name = "timer6",
.class = &omap44xx_timer_hwmod_class, .class = &omap44xx_timer_hwmod_class,
.mpu_irqs = omap44xx_timer6_irqs, .mpu_irqs = omap44xx_timer6_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer6_irqs),
.main_clk = "timer6_fck", .main_clk = "timer6_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -4323,6 +4327,7 @@ static struct omap_hwmod omap44xx_timer6_hwmod = { ...@@ -4323,6 +4327,7 @@ static struct omap_hwmod omap44xx_timer6_hwmod = {
static struct omap_hwmod omap44xx_timer7_hwmod; static struct omap_hwmod omap44xx_timer7_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = { static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
{ .irq = 43 + OMAP44XX_IRQ_GIC_START }, { .irq = 43 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = { static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
...@@ -4331,6 +4336,7 @@ static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = { ...@@ -4331,6 +4336,7 @@ static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
.pa_end = 0x4013c07f, .pa_end = 0x4013c07f,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_abe -> timer7 */ /* l4_abe -> timer7 */
...@@ -4339,7 +4345,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = { ...@@ -4339,7 +4345,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
.slave = &omap44xx_timer7_hwmod, .slave = &omap44xx_timer7_hwmod,
.clk = "ocp_abe_iclk", .clk = "ocp_abe_iclk",
.addr = omap44xx_timer7_addrs, .addr = omap44xx_timer7_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_timer7_addrs),
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
...@@ -4349,6 +4354,7 @@ static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = { ...@@ -4349,6 +4354,7 @@ static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
.pa_end = 0x4903c07f, .pa_end = 0x4903c07f,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_abe -> timer7 (dma) */ /* l4_abe -> timer7 (dma) */
...@@ -4357,7 +4363,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = { ...@@ -4357,7 +4363,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
.slave = &omap44xx_timer7_hwmod, .slave = &omap44xx_timer7_hwmod,
.clk = "ocp_abe_iclk", .clk = "ocp_abe_iclk",
.addr = omap44xx_timer7_dma_addrs, .addr = omap44xx_timer7_dma_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_timer7_dma_addrs),
.user = OCP_USER_SDMA, .user = OCP_USER_SDMA,
}; };
...@@ -4371,7 +4376,6 @@ static struct omap_hwmod omap44xx_timer7_hwmod = { ...@@ -4371,7 +4376,6 @@ static struct omap_hwmod omap44xx_timer7_hwmod = {
.name = "timer7", .name = "timer7",
.class = &omap44xx_timer_hwmod_class, .class = &omap44xx_timer_hwmod_class,
.mpu_irqs = omap44xx_timer7_irqs, .mpu_irqs = omap44xx_timer7_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer7_irqs),
.main_clk = "timer7_fck", .main_clk = "timer7_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -4387,6 +4391,7 @@ static struct omap_hwmod omap44xx_timer7_hwmod = { ...@@ -4387,6 +4391,7 @@ static struct omap_hwmod omap44xx_timer7_hwmod = {
static struct omap_hwmod omap44xx_timer8_hwmod; static struct omap_hwmod omap44xx_timer8_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = { static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
{ .irq = 44 + OMAP44XX_IRQ_GIC_START }, { .irq = 44 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = { static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
...@@ -4395,6 +4400,7 @@ static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = { ...@@ -4395,6 +4400,7 @@ static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
.pa_end = 0x4013e07f, .pa_end = 0x4013e07f,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_abe -> timer8 */ /* l4_abe -> timer8 */
...@@ -4403,7 +4409,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = { ...@@ -4403,7 +4409,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
.slave = &omap44xx_timer8_hwmod, .slave = &omap44xx_timer8_hwmod,
.clk = "ocp_abe_iclk", .clk = "ocp_abe_iclk",
.addr = omap44xx_timer8_addrs, .addr = omap44xx_timer8_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_timer8_addrs),
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
...@@ -4413,6 +4418,7 @@ static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = { ...@@ -4413,6 +4418,7 @@ static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
.pa_end = 0x4903e07f, .pa_end = 0x4903e07f,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_abe -> timer8 (dma) */ /* l4_abe -> timer8 (dma) */
...@@ -4421,7 +4427,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = { ...@@ -4421,7 +4427,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
.slave = &omap44xx_timer8_hwmod, .slave = &omap44xx_timer8_hwmod,
.clk = "ocp_abe_iclk", .clk = "ocp_abe_iclk",
.addr = omap44xx_timer8_dma_addrs, .addr = omap44xx_timer8_dma_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_timer8_dma_addrs),
.user = OCP_USER_SDMA, .user = OCP_USER_SDMA,
}; };
...@@ -4435,7 +4440,6 @@ static struct omap_hwmod omap44xx_timer8_hwmod = { ...@@ -4435,7 +4440,6 @@ static struct omap_hwmod omap44xx_timer8_hwmod = {
.name = "timer8", .name = "timer8",
.class = &omap44xx_timer_hwmod_class, .class = &omap44xx_timer_hwmod_class,
.mpu_irqs = omap44xx_timer8_irqs, .mpu_irqs = omap44xx_timer8_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer8_irqs),
.main_clk = "timer8_fck", .main_clk = "timer8_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -4451,6 +4455,7 @@ static struct omap_hwmod omap44xx_timer8_hwmod = { ...@@ -4451,6 +4455,7 @@ static struct omap_hwmod omap44xx_timer8_hwmod = {
static struct omap_hwmod omap44xx_timer9_hwmod; static struct omap_hwmod omap44xx_timer9_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = { static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
{ .irq = 45 + OMAP44XX_IRQ_GIC_START }, { .irq = 45 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = { static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
...@@ -4459,6 +4464,7 @@ static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = { ...@@ -4459,6 +4464,7 @@ static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
.pa_end = 0x4803e07f, .pa_end = 0x4803e07f,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_per -> timer9 */ /* l4_per -> timer9 */
...@@ -4467,7 +4473,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = { ...@@ -4467,7 +4473,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
.slave = &omap44xx_timer9_hwmod, .slave = &omap44xx_timer9_hwmod,
.clk = "l4_div_ck", .clk = "l4_div_ck",
.addr = omap44xx_timer9_addrs, .addr = omap44xx_timer9_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_timer9_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -4480,7 +4485,6 @@ static struct omap_hwmod omap44xx_timer9_hwmod = { ...@@ -4480,7 +4485,6 @@ static struct omap_hwmod omap44xx_timer9_hwmod = {
.name = "timer9", .name = "timer9",
.class = &omap44xx_timer_hwmod_class, .class = &omap44xx_timer_hwmod_class,
.mpu_irqs = omap44xx_timer9_irqs, .mpu_irqs = omap44xx_timer9_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer9_irqs),
.main_clk = "timer9_fck", .main_clk = "timer9_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -4496,6 +4500,7 @@ static struct omap_hwmod omap44xx_timer9_hwmod = { ...@@ -4496,6 +4500,7 @@ static struct omap_hwmod omap44xx_timer9_hwmod = {
static struct omap_hwmod omap44xx_timer10_hwmod; static struct omap_hwmod omap44xx_timer10_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = { static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
{ .irq = 46 + OMAP44XX_IRQ_GIC_START }, { .irq = 46 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = { static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
...@@ -4504,6 +4509,7 @@ static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = { ...@@ -4504,6 +4509,7 @@ static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
.pa_end = 0x4808607f, .pa_end = 0x4808607f,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_per -> timer10 */ /* l4_per -> timer10 */
...@@ -4512,7 +4518,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = { ...@@ -4512,7 +4518,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
.slave = &omap44xx_timer10_hwmod, .slave = &omap44xx_timer10_hwmod,
.clk = "l4_div_ck", .clk = "l4_div_ck",
.addr = omap44xx_timer10_addrs, .addr = omap44xx_timer10_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_timer10_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -4525,7 +4530,6 @@ static struct omap_hwmod omap44xx_timer10_hwmod = { ...@@ -4525,7 +4530,6 @@ static struct omap_hwmod omap44xx_timer10_hwmod = {
.name = "timer10", .name = "timer10",
.class = &omap44xx_timer_1ms_hwmod_class, .class = &omap44xx_timer_1ms_hwmod_class,
.mpu_irqs = omap44xx_timer10_irqs, .mpu_irqs = omap44xx_timer10_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer10_irqs),
.main_clk = "timer10_fck", .main_clk = "timer10_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -4541,6 +4545,7 @@ static struct omap_hwmod omap44xx_timer10_hwmod = { ...@@ -4541,6 +4545,7 @@ static struct omap_hwmod omap44xx_timer10_hwmod = {
static struct omap_hwmod omap44xx_timer11_hwmod; static struct omap_hwmod omap44xx_timer11_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = { static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
{ .irq = 47 + OMAP44XX_IRQ_GIC_START }, { .irq = 47 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = { static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
...@@ -4549,6 +4554,7 @@ static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = { ...@@ -4549,6 +4554,7 @@ static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
.pa_end = 0x4808807f, .pa_end = 0x4808807f,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_per -> timer11 */ /* l4_per -> timer11 */
...@@ -4557,7 +4563,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = { ...@@ -4557,7 +4563,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
.slave = &omap44xx_timer11_hwmod, .slave = &omap44xx_timer11_hwmod,
.clk = "l4_div_ck", .clk = "l4_div_ck",
.addr = omap44xx_timer11_addrs, .addr = omap44xx_timer11_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_timer11_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -4570,7 +4575,6 @@ static struct omap_hwmod omap44xx_timer11_hwmod = { ...@@ -4570,7 +4575,6 @@ static struct omap_hwmod omap44xx_timer11_hwmod = {
.name = "timer11", .name = "timer11",
.class = &omap44xx_timer_hwmod_class, .class = &omap44xx_timer_hwmod_class,
.mpu_irqs = omap44xx_timer11_irqs, .mpu_irqs = omap44xx_timer11_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer11_irqs),
.main_clk = "timer11_fck", .main_clk = "timer11_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -4608,11 +4612,13 @@ static struct omap_hwmod_class omap44xx_uart_hwmod_class = { ...@@ -4608,11 +4612,13 @@ static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
static struct omap_hwmod omap44xx_uart1_hwmod; static struct omap_hwmod omap44xx_uart1_hwmod;
static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = { static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
{ .irq = 72 + OMAP44XX_IRQ_GIC_START }, { .irq = 72 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = { static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
{ .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START }, { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
{ .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START }, { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
{ .dma_req = -1 }
}; };
static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = { static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
...@@ -4621,6 +4627,7 @@ static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = { ...@@ -4621,6 +4627,7 @@ static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
.pa_end = 0x4806a0ff, .pa_end = 0x4806a0ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_per -> uart1 */ /* l4_per -> uart1 */
...@@ -4629,7 +4636,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = { ...@@ -4629,7 +4636,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
.slave = &omap44xx_uart1_hwmod, .slave = &omap44xx_uart1_hwmod,
.clk = "l4_div_ck", .clk = "l4_div_ck",
.addr = omap44xx_uart1_addrs, .addr = omap44xx_uart1_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_uart1_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -4642,9 +4648,7 @@ static struct omap_hwmod omap44xx_uart1_hwmod = { ...@@ -4642,9 +4648,7 @@ static struct omap_hwmod omap44xx_uart1_hwmod = {
.name = "uart1", .name = "uart1",
.class = &omap44xx_uart_hwmod_class, .class = &omap44xx_uart_hwmod_class,
.mpu_irqs = omap44xx_uart1_irqs, .mpu_irqs = omap44xx_uart1_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart1_irqs),
.sdma_reqs = omap44xx_uart1_sdma_reqs, .sdma_reqs = omap44xx_uart1_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart1_sdma_reqs),
.main_clk = "uart1_fck", .main_clk = "uart1_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -4660,11 +4664,13 @@ static struct omap_hwmod omap44xx_uart1_hwmod = { ...@@ -4660,11 +4664,13 @@ static struct omap_hwmod omap44xx_uart1_hwmod = {
static struct omap_hwmod omap44xx_uart2_hwmod; static struct omap_hwmod omap44xx_uart2_hwmod;
static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = { static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
{ .irq = 73 + OMAP44XX_IRQ_GIC_START }, { .irq = 73 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = { static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
{ .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START }, { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
{ .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START }, { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
{ .dma_req = -1 }
}; };
static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = { static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
...@@ -4673,6 +4679,7 @@ static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = { ...@@ -4673,6 +4679,7 @@ static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
.pa_end = 0x4806c0ff, .pa_end = 0x4806c0ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_per -> uart2 */ /* l4_per -> uart2 */
...@@ -4681,7 +4688,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = { ...@@ -4681,7 +4688,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
.slave = &omap44xx_uart2_hwmod, .slave = &omap44xx_uart2_hwmod,
.clk = "l4_div_ck", .clk = "l4_div_ck",
.addr = omap44xx_uart2_addrs, .addr = omap44xx_uart2_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_uart2_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -4694,9 +4700,7 @@ static struct omap_hwmod omap44xx_uart2_hwmod = { ...@@ -4694,9 +4700,7 @@ static struct omap_hwmod omap44xx_uart2_hwmod = {
.name = "uart2", .name = "uart2",
.class = &omap44xx_uart_hwmod_class, .class = &omap44xx_uart_hwmod_class,
.mpu_irqs = omap44xx_uart2_irqs, .mpu_irqs = omap44xx_uart2_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart2_irqs),
.sdma_reqs = omap44xx_uart2_sdma_reqs, .sdma_reqs = omap44xx_uart2_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart2_sdma_reqs),
.main_clk = "uart2_fck", .main_clk = "uart2_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -4712,11 +4716,13 @@ static struct omap_hwmod omap44xx_uart2_hwmod = { ...@@ -4712,11 +4716,13 @@ static struct omap_hwmod omap44xx_uart2_hwmod = {
static struct omap_hwmod omap44xx_uart3_hwmod; static struct omap_hwmod omap44xx_uart3_hwmod;
static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = { static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
{ .irq = 74 + OMAP44XX_IRQ_GIC_START }, { .irq = 74 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = { static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
{ .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START }, { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
{ .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START }, { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
{ .dma_req = -1 }
}; };
static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = { static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
...@@ -4725,6 +4731,7 @@ static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = { ...@@ -4725,6 +4731,7 @@ static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
.pa_end = 0x480200ff, .pa_end = 0x480200ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_per -> uart3 */ /* l4_per -> uart3 */
...@@ -4733,7 +4740,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = { ...@@ -4733,7 +4740,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
.slave = &omap44xx_uart3_hwmod, .slave = &omap44xx_uart3_hwmod,
.clk = "l4_div_ck", .clk = "l4_div_ck",
.addr = omap44xx_uart3_addrs, .addr = omap44xx_uart3_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_uart3_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -4745,11 +4751,9 @@ static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = { ...@@ -4745,11 +4751,9 @@ static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
static struct omap_hwmod omap44xx_uart3_hwmod = { static struct omap_hwmod omap44xx_uart3_hwmod = {
.name = "uart3", .name = "uart3",
.class = &omap44xx_uart_hwmod_class, .class = &omap44xx_uart_hwmod_class,
.flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
.mpu_irqs = omap44xx_uart3_irqs, .mpu_irqs = omap44xx_uart3_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart3_irqs),
.sdma_reqs = omap44xx_uart3_sdma_reqs, .sdma_reqs = omap44xx_uart3_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart3_sdma_reqs),
.main_clk = "uart3_fck", .main_clk = "uart3_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -4765,11 +4769,13 @@ static struct omap_hwmod omap44xx_uart3_hwmod = { ...@@ -4765,11 +4769,13 @@ static struct omap_hwmod omap44xx_uart3_hwmod = {
static struct omap_hwmod omap44xx_uart4_hwmod; static struct omap_hwmod omap44xx_uart4_hwmod;
static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = { static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
{ .irq = 70 + OMAP44XX_IRQ_GIC_START }, { .irq = 70 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = { static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
{ .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START }, { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
{ .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START }, { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
{ .dma_req = -1 }
}; };
static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = { static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
...@@ -4778,6 +4784,7 @@ static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = { ...@@ -4778,6 +4784,7 @@ static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
.pa_end = 0x4806e0ff, .pa_end = 0x4806e0ff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_per -> uart4 */ /* l4_per -> uart4 */
...@@ -4786,7 +4793,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = { ...@@ -4786,7 +4793,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
.slave = &omap44xx_uart4_hwmod, .slave = &omap44xx_uart4_hwmod,
.clk = "l4_div_ck", .clk = "l4_div_ck",
.addr = omap44xx_uart4_addrs, .addr = omap44xx_uart4_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_uart4_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -4799,9 +4805,7 @@ static struct omap_hwmod omap44xx_uart4_hwmod = { ...@@ -4799,9 +4805,7 @@ static struct omap_hwmod omap44xx_uart4_hwmod = {
.name = "uart4", .name = "uart4",
.class = &omap44xx_uart_hwmod_class, .class = &omap44xx_uart_hwmod_class,
.mpu_irqs = omap44xx_uart4_irqs, .mpu_irqs = omap44xx_uart4_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart4_irqs),
.sdma_reqs = omap44xx_uart4_sdma_reqs, .sdma_reqs = omap44xx_uart4_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart4_sdma_reqs),
.main_clk = "uart4_fck", .main_clk = "uart4_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -4832,14 +4836,15 @@ static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = { ...@@ -4832,14 +4836,15 @@ static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
}; };
static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = { static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
.name = "usb_otg_hs", .name = "usb_otg_hs",
.sysc = &omap44xx_usb_otg_hs_sysc, .sysc = &omap44xx_usb_otg_hs_sysc,
}; };
/* usb_otg_hs */ /* usb_otg_hs */
static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = { static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
{ .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START }, { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
{ .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START }, { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
/* usb_otg_hs master ports */ /* usb_otg_hs master ports */
...@@ -4853,6 +4858,7 @@ static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = { ...@@ -4853,6 +4858,7 @@ static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
.pa_end = 0x4a0ab003, .pa_end = 0x4a0ab003,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_cfg -> usb_otg_hs */ /* l4_cfg -> usb_otg_hs */
...@@ -4861,7 +4867,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = { ...@@ -4861,7 +4867,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
.slave = &omap44xx_usb_otg_hs_hwmod, .slave = &omap44xx_usb_otg_hs_hwmod,
.clk = "l4_div_ck", .clk = "l4_div_ck",
.addr = omap44xx_usb_otg_hs_addrs, .addr = omap44xx_usb_otg_hs_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -4879,7 +4884,6 @@ static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = { ...@@ -4879,7 +4884,6 @@ static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
.class = &omap44xx_usb_otg_hs_hwmod_class, .class = &omap44xx_usb_otg_hs_hwmod_class,
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
.mpu_irqs = omap44xx_usb_otg_hs_irqs, .mpu_irqs = omap44xx_usb_otg_hs_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_irqs),
.main_clk = "usb_otg_hs_ick", .main_clk = "usb_otg_hs_ick",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -4887,7 +4891,7 @@ static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = { ...@@ -4887,7 +4891,7 @@ static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
}, },
}, },
.opt_clks = usb_otg_hs_opt_clks, .opt_clks = usb_otg_hs_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks), .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
.slaves = omap44xx_usb_otg_hs_slaves, .slaves = omap44xx_usb_otg_hs_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves), .slaves_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves),
.masters = omap44xx_usb_otg_hs_masters, .masters = omap44xx_usb_otg_hs_masters,
...@@ -4922,6 +4926,7 @@ static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = { ...@@ -4922,6 +4926,7 @@ static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
static struct omap_hwmod omap44xx_wd_timer2_hwmod; static struct omap_hwmod omap44xx_wd_timer2_hwmod;
static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = { static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
{ .irq = 80 + OMAP44XX_IRQ_GIC_START }, { .irq = 80 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = { static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
...@@ -4930,6 +4935,7 @@ static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = { ...@@ -4930,6 +4935,7 @@ static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
.pa_end = 0x4a31407f, .pa_end = 0x4a31407f,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_wkup -> wd_timer2 */ /* l4_wkup -> wd_timer2 */
...@@ -4938,7 +4944,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = { ...@@ -4938,7 +4944,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
.slave = &omap44xx_wd_timer2_hwmod, .slave = &omap44xx_wd_timer2_hwmod,
.clk = "l4_wkup_clk_mux_ck", .clk = "l4_wkup_clk_mux_ck",
.addr = omap44xx_wd_timer2_addrs, .addr = omap44xx_wd_timer2_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_wd_timer2_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -4951,7 +4956,6 @@ static struct omap_hwmod omap44xx_wd_timer2_hwmod = { ...@@ -4951,7 +4956,6 @@ static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
.name = "wd_timer2", .name = "wd_timer2",
.class = &omap44xx_wd_timer_hwmod_class, .class = &omap44xx_wd_timer_hwmod_class,
.mpu_irqs = omap44xx_wd_timer2_irqs, .mpu_irqs = omap44xx_wd_timer2_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer2_irqs),
.main_clk = "wd_timer2_fck", .main_clk = "wd_timer2_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -4967,6 +4971,7 @@ static struct omap_hwmod omap44xx_wd_timer2_hwmod = { ...@@ -4967,6 +4971,7 @@ static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
static struct omap_hwmod omap44xx_wd_timer3_hwmod; static struct omap_hwmod omap44xx_wd_timer3_hwmod;
static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = { static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
{ .irq = 36 + OMAP44XX_IRQ_GIC_START }, { .irq = 36 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
}; };
static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = { static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
...@@ -4975,6 +4980,7 @@ static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = { ...@@ -4975,6 +4980,7 @@ static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
.pa_end = 0x4013007f, .pa_end = 0x4013007f,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_abe -> wd_timer3 */ /* l4_abe -> wd_timer3 */
...@@ -4983,7 +4989,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = { ...@@ -4983,7 +4989,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
.slave = &omap44xx_wd_timer3_hwmod, .slave = &omap44xx_wd_timer3_hwmod,
.clk = "ocp_abe_iclk", .clk = "ocp_abe_iclk",
.addr = omap44xx_wd_timer3_addrs, .addr = omap44xx_wd_timer3_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_addrs),
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
...@@ -4993,6 +4998,7 @@ static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = { ...@@ -4993,6 +4998,7 @@ static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
.pa_end = 0x4903007f, .pa_end = 0x4903007f,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
}; };
/* l4_abe -> wd_timer3 (dma) */ /* l4_abe -> wd_timer3 (dma) */
...@@ -5001,7 +5007,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = { ...@@ -5001,7 +5007,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
.slave = &omap44xx_wd_timer3_hwmod, .slave = &omap44xx_wd_timer3_hwmod,
.clk = "ocp_abe_iclk", .clk = "ocp_abe_iclk",
.addr = omap44xx_wd_timer3_dma_addrs, .addr = omap44xx_wd_timer3_dma_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_dma_addrs),
.user = OCP_USER_SDMA, .user = OCP_USER_SDMA,
}; };
...@@ -5015,7 +5020,6 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = { ...@@ -5015,7 +5020,6 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
.name = "wd_timer3", .name = "wd_timer3",
.class = &omap44xx_wd_timer_hwmod_class, .class = &omap44xx_wd_timer_hwmod_class,
.mpu_irqs = omap44xx_wd_timer3_irqs, .mpu_irqs = omap44xx_wd_timer3_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer3_irqs),
.main_clk = "wd_timer3_fck", .main_clk = "wd_timer3_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
......
arch/arm/mach-omap2/omap_hwmod_common_data.c
浏览文件 @ c402c0d9
...@@ -49,23 +49,3 @@ struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2 = { ...@@ -49,23 +49,3 @@ struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2 = {
.srst_shift = SYSC_TYPE2_SOFTRESET_SHIFT, .srst_shift = SYSC_TYPE2_SOFTRESET_SHIFT,
}; };
/*
* omap_hwmod class data
*/
struct omap_hwmod_class l3_hwmod_class = {
.name = "l3"
};
struct omap_hwmod_class l4_hwmod_class = {
.name = "l4"
};
struct omap_hwmod_class mpu_hwmod_class = {
.name = "mpu"
};
struct omap_hwmod_class iva_hwmod_class = {
.name = "iva"
};
arch/arm/mach-omap2/omap_hwmod_common_data.h
浏览文件 @ c402c0d9
/* /*
* omap_hwmod_common_data.h - OMAP hwmod common macros and declarations * omap_hwmod_common_data.h - OMAP hwmod common macros and declarations
* *
* Copyright (C) 2010 Nokia Corporation * Copyright (C) 2010-2011 Nokia Corporation
* Paul Walmsley * Paul Walmsley
* *
* Copyright (C) 2010 Texas Instruments, Inc. * Copyright (C) 2010-2011 Texas Instruments, Inc.
* Benoît Cousson * Benoît Cousson
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
...@@ -16,10 +16,99 @@ ...@@ -16,10 +16,99 @@
#include <plat/omap_hwmod.h> #include <plat/omap_hwmod.h>
/* Common address space across OMAP2xxx */
extern struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[];
extern struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[];
extern struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[];
extern struct omap_hwmod_addr_space omap2xxx_timer2_addrs[];
extern struct omap_hwmod_addr_space omap2xxx_timer3_addrs[];
extern struct omap_hwmod_addr_space omap2xxx_timer4_addrs[];
extern struct omap_hwmod_addr_space omap2xxx_timer5_addrs[];
extern struct omap_hwmod_addr_space omap2xxx_timer6_addrs[];
extern struct omap_hwmod_addr_space omap2xxx_timer7_addrs[];
extern struct omap_hwmod_addr_space omap2xxx_timer8_addrs[];
extern struct omap_hwmod_addr_space omap2xxx_timer9_addrs[];
extern struct omap_hwmod_addr_space omap2xxx_timer12_addrs[];
extern struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[];
/* Common address space across OMAP2xxx/3xxx */
extern struct omap_hwmod_addr_space omap2_i2c1_addr_space[];
extern struct omap_hwmod_addr_space omap2_i2c2_addr_space[];
extern struct omap_hwmod_addr_space omap2_dss_addrs[];
extern struct omap_hwmod_addr_space omap2_dss_dispc_addrs[];
extern struct omap_hwmod_addr_space omap2_dss_rfbi_addrs[];
extern struct omap_hwmod_addr_space omap2_dss_venc_addrs[];
extern struct omap_hwmod_addr_space omap2_timer10_addrs[];
extern struct omap_hwmod_addr_space omap2_timer11_addrs[];
extern struct omap_hwmod_addr_space omap2430_mmc1_addr_space[];
extern struct omap_hwmod_addr_space omap2430_mmc2_addr_space[];
extern struct omap_hwmod_addr_space omap2_mcspi1_addr_space[];
extern struct omap_hwmod_addr_space omap2_mcspi2_addr_space[];
extern struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[];
extern struct omap_hwmod_addr_space omap2_dma_system_addrs[];
extern struct omap_hwmod_addr_space omap2_mailbox_addrs[];
extern struct omap_hwmod_addr_space omap2_mcbsp1_addrs[];
/* Common IP block data across OMAP2xxx */
extern struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[];
extern struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[];
/* Common IP block data */
extern struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[];
extern struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[];
extern struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[];
extern struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[];
extern struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[];
extern struct omap_hwmod_dma_info omap2_mcspi1_sdma_reqs[];
extern struct omap_hwmod_dma_info omap2_mcspi2_sdma_reqs[];
extern struct omap_hwmod_dma_info omap2_mcbsp1_sdma_reqs[];
extern struct omap_hwmod_dma_info omap2_mcbsp2_sdma_reqs[];
/* Common IP block data on OMAP2430/OMAP3 */
extern struct omap_hwmod_dma_info omap2_mcbsp3_sdma_reqs[];
/* Common IP block data across OMAP2/3 */
extern struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[];
extern struct omap_hwmod_irq_info omap2_timer2_mpu_irqs[];
extern struct omap_hwmod_irq_info omap2_timer3_mpu_irqs[];
extern struct omap_hwmod_irq_info omap2_timer4_mpu_irqs[];
extern struct omap_hwmod_irq_info omap2_timer5_mpu_irqs[];
extern struct omap_hwmod_irq_info omap2_timer6_mpu_irqs[];
extern struct omap_hwmod_irq_info omap2_timer7_mpu_irqs[];
extern struct omap_hwmod_irq_info omap2_timer8_mpu_irqs[];
extern struct omap_hwmod_irq_info omap2_timer9_mpu_irqs[];
extern struct omap_hwmod_irq_info omap2_timer10_mpu_irqs[];
extern struct omap_hwmod_irq_info omap2_timer11_mpu_irqs[];
extern struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[];
extern struct omap_hwmod_irq_info omap2_uart2_mpu_irqs[];
extern struct omap_hwmod_irq_info omap2_uart3_mpu_irqs[];
extern struct omap_hwmod_irq_info omap2_dispc_irqs[];
extern struct omap_hwmod_irq_info omap2_i2c1_mpu_irqs[];
extern struct omap_hwmod_irq_info omap2_i2c2_mpu_irqs[];
extern struct omap_hwmod_irq_info omap2_gpio1_irqs[];
extern struct omap_hwmod_irq_info omap2_gpio2_irqs[];
extern struct omap_hwmod_irq_info omap2_gpio3_irqs[];
extern struct omap_hwmod_irq_info omap2_gpio4_irqs[];
extern struct omap_hwmod_irq_info omap2_dma_system_irqs[];
extern struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[];
extern struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[];
/* OMAP hwmod classes - forward declarations */ /* OMAP hwmod classes - forward declarations */
extern struct omap_hwmod_class l3_hwmod_class; extern struct omap_hwmod_class l3_hwmod_class;
extern struct omap_hwmod_class l4_hwmod_class; extern struct omap_hwmod_class l4_hwmod_class;
extern struct omap_hwmod_class mpu_hwmod_class; extern struct omap_hwmod_class mpu_hwmod_class;
extern struct omap_hwmod_class iva_hwmod_class; extern struct omap_hwmod_class iva_hwmod_class;
extern struct omap_hwmod_class omap2_uart_class;
extern struct omap_hwmod_class omap2_dss_hwmod_class;
extern struct omap_hwmod_class omap2_dispc_hwmod_class;
extern struct omap_hwmod_class omap2_rfbi_hwmod_class;
extern struct omap_hwmod_class omap2_venc_hwmod_class;
extern struct omap_hwmod_class omap2xxx_timer_hwmod_class;
extern struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class;
extern struct omap_hwmod_class omap2xxx_gpio_hwmod_class;
extern struct omap_hwmod_class omap2xxx_dma_hwmod_class;
extern struct omap_hwmod_class omap2xxx_mailbox_hwmod_class;
extern struct omap_hwmod_class omap2xxx_mcspi_class;
#endif #endif
arch/arm/mach-omap2/powerdomains44xx_data.c
浏览文件 @ c402c0d9
...@@ -53,7 +53,7 @@ static struct powerdomain core_44xx_pwrdm = { ...@@ -53,7 +53,7 @@ static struct powerdomain core_44xx_pwrdm = {
[3] = PWRSTS_ON, /* ducati_l2ram */ [3] = PWRSTS_ON, /* ducati_l2ram */
[4] = PWRSTS_ON, /* ducati_unicache */ [4] = PWRSTS_ON, /* ducati_unicache */
}, },
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
}; };
/* gfx_44xx_pwrdm: 3D accelerator power domain */ /* gfx_44xx_pwrdm: 3D accelerator power domain */
...@@ -70,7 +70,7 @@ static struct powerdomain gfx_44xx_pwrdm = { ...@@ -70,7 +70,7 @@ static struct powerdomain gfx_44xx_pwrdm = {
.pwrsts_mem_on = { .pwrsts_mem_on = {
[0] = PWRSTS_ON, /* gfx_mem */ [0] = PWRSTS_ON, /* gfx_mem */
}, },
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
}; };
/* abe_44xx_pwrdm: Audio back end power domain */ /* abe_44xx_pwrdm: Audio back end power domain */
...@@ -90,7 +90,7 @@ static struct powerdomain abe_44xx_pwrdm = { ...@@ -90,7 +90,7 @@ static struct powerdomain abe_44xx_pwrdm = {
[0] = PWRSTS_ON, /* aessmem */ [0] = PWRSTS_ON, /* aessmem */
[1] = PWRSTS_ON, /* periphmem */ [1] = PWRSTS_ON, /* periphmem */
}, },
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
}; };
/* dss_44xx_pwrdm: Display subsystem power domain */ /* dss_44xx_pwrdm: Display subsystem power domain */
...@@ -108,7 +108,7 @@ static struct powerdomain dss_44xx_pwrdm = { ...@@ -108,7 +108,7 @@ static struct powerdomain dss_44xx_pwrdm = {
.pwrsts_mem_on = { .pwrsts_mem_on = {
[0] = PWRSTS_ON, /* dss_mem */ [0] = PWRSTS_ON, /* dss_mem */
}, },
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
}; };
/* tesla_44xx_pwrdm: Tesla processor power domain */ /* tesla_44xx_pwrdm: Tesla processor power domain */
...@@ -130,7 +130,7 @@ static struct powerdomain tesla_44xx_pwrdm = { ...@@ -130,7 +130,7 @@ static struct powerdomain tesla_44xx_pwrdm = {
[1] = PWRSTS_ON, /* tesla_l1 */ [1] = PWRSTS_ON, /* tesla_l1 */
[2] = PWRSTS_ON, /* tesla_l2 */ [2] = PWRSTS_ON, /* tesla_l2 */
}, },
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
}; };
/* wkup_44xx_pwrdm: Wake-up power domain */ /* wkup_44xx_pwrdm: Wake-up power domain */
...@@ -241,7 +241,7 @@ static struct powerdomain ivahd_44xx_pwrdm = { ...@@ -241,7 +241,7 @@ static struct powerdomain ivahd_44xx_pwrdm = {
[2] = PWRSTS_ON, /* tcm1_mem */ [2] = PWRSTS_ON, /* tcm1_mem */
[3] = PWRSTS_ON, /* tcm2_mem */ [3] = PWRSTS_ON, /* tcm2_mem */
}, },
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
}; };
/* cam_44xx_pwrdm: Camera subsystem power domain */ /* cam_44xx_pwrdm: Camera subsystem power domain */
...@@ -258,7 +258,7 @@ static struct powerdomain cam_44xx_pwrdm = { ...@@ -258,7 +258,7 @@ static struct powerdomain cam_44xx_pwrdm = {
.pwrsts_mem_on = { .pwrsts_mem_on = {
[0] = PWRSTS_ON, /* cam_mem */ [0] = PWRSTS_ON, /* cam_mem */
}, },
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
}; };
/* l3init_44xx_pwrdm: L3 initators pheripherals power domain */ /* l3init_44xx_pwrdm: L3 initators pheripherals power domain */
...@@ -276,7 +276,7 @@ static struct powerdomain l3init_44xx_pwrdm = { ...@@ -276,7 +276,7 @@ static struct powerdomain l3init_44xx_pwrdm = {
.pwrsts_mem_on = { .pwrsts_mem_on = {
[0] = PWRSTS_ON, /* l3init_bank1 */ [0] = PWRSTS_ON, /* l3init_bank1 */
}, },
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
}; };
/* l4per_44xx_pwrdm: Target peripherals power domain */ /* l4per_44xx_pwrdm: Target peripherals power domain */
...@@ -296,7 +296,7 @@ static struct powerdomain l4per_44xx_pwrdm = { ...@@ -296,7 +296,7 @@ static struct powerdomain l4per_44xx_pwrdm = {
[0] = PWRSTS_ON, /* nonretained_bank */ [0] = PWRSTS_ON, /* nonretained_bank */
[1] = PWRSTS_ON, /* retained_bank */ [1] = PWRSTS_ON, /* retained_bank */
}, },
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
}; };
/* /*
......
arch/arm/mach-omap2/prcm_mpu44xx.h
浏览文件 @ c402c0d9
...@@ -31,7 +31,6 @@ ...@@ -31,7 +31,6 @@
OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (inst) + (reg)) OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (inst) + (reg))
/* PRCM_MPU instances */ /* PRCM_MPU instances */
#define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST 0x0000 #define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST 0x0000
#define OMAP4430_PRCM_MPU_DEVICE_PRM_INST 0x0200 #define OMAP4430_PRCM_MPU_DEVICE_PRM_INST 0x0200
#define OMAP4430_PRCM_MPU_CPU0_INST 0x0400 #define OMAP4430_PRCM_MPU_CPU0_INST 0x0400
...@@ -52,46 +51,46 @@ ...@@ -52,46 +51,46 @@
*/ */
/* PRCM_MPU.OCP_SOCKET_PRCM register offsets */ /* PRCM_MPU.OCP_SOCKET_PRCM register offsets */
#define OMAP4_REVISION_PRCM_OFFSET 0x0000 #define OMAP4_REVISION_PRCM_OFFSET 0x0000
#define OMAP4430_REVISION_PRCM OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST, 0x0000) #define OMAP4430_REVISION_PRCM OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST, 0x0000)
/* PRCM_MPU.DEVICE_PRM register offsets */ /* PRCM_MPU.DEVICE_PRM register offsets */
#define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000 #define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000
#define OMAP4430_PRCM_MPU_PRM_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0000) #define OMAP4430_PRCM_MPU_PRM_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0000)
#define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004 #define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004
#define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0004) #define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0004)
/* PRCM_MPU.CPU0 register offsets */ /* PRCM_MPU.CPU0 register offsets */
#define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET 0x0000 #define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET 0x0000
#define OMAP4430_PM_CPU0_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0000) #define OMAP4430_PM_CPU0_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0000)
#define OMAP4_PM_CPU0_PWRSTST_OFFSET 0x0004 #define OMAP4_PM_CPU0_PWRSTST_OFFSET 0x0004
#define OMAP4430_PM_CPU0_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0004) #define OMAP4430_PM_CPU0_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0004)
#define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0008 #define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0008
#define OMAP4430_RM_CPU0_CPU0_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0008) #define OMAP4430_RM_CPU0_CPU0_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0008)
#define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x000c #define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x000c
#define OMAP4430_RM_CPU0_CPU0_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x000c) #define OMAP4430_RM_CPU0_CPU0_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x000c)
#define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET 0x0010 #define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET 0x0010
#define OMAP4430_RM_CPU0_CPU0_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0010) #define OMAP4430_RM_CPU0_CPU0_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0010)
#define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0014 #define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0014
#define OMAP4430_CM_CPU0_CPU0_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0014) #define OMAP4430_CM_CPU0_CPU0_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0014)
#define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET 0x0018 #define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET 0x0018
#define OMAP4430_CM_CPU0_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0018) #define OMAP4430_CM_CPU0_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0018)
/* PRCM_MPU.CPU1 register offsets */ /* PRCM_MPU.CPU1 register offsets */
#define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET 0x0000 #define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET 0x0000
#define OMAP4430_PM_CPU1_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0000) #define OMAP4430_PM_CPU1_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0000)
#define OMAP4_PM_CPU1_PWRSTST_OFFSET 0x0004 #define OMAP4_PM_CPU1_PWRSTST_OFFSET 0x0004
#define OMAP4430_PM_CPU1_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0004) #define OMAP4430_PM_CPU1_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0004)
#define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0008 #define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0008
#define OMAP4430_RM_CPU1_CPU1_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0008) #define OMAP4430_RM_CPU1_CPU1_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0008)
#define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x000c #define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x000c
#define OMAP4430_RM_CPU1_CPU1_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x000c) #define OMAP4430_RM_CPU1_CPU1_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x000c)
#define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET 0x0010 #define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET 0x0010
#define OMAP4430_RM_CPU1_CPU1_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0010) #define OMAP4430_RM_CPU1_CPU1_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0010)
#define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0014 #define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0014
#define OMAP4430_CM_CPU1_CPU1_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0014) #define OMAP4430_CM_CPU1_CPU1_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0014)
#define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET 0x0018 #define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET 0x0018
#define OMAP4430_CM_CPU1_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018) #define OMAP4430_CM_CPU1_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018)
/* Function prototypes */ /* Function prototypes */
# ifndef __ASSEMBLER__ # ifndef __ASSEMBLER__
......
arch/arm/mach-omap2/prm44xx.h
浏览文件 @ c402c0d9
...@@ -31,7 +31,7 @@ ...@@ -31,7 +31,7 @@
#define OMAP4430_PRM_BASE 0x4a306000 #define OMAP4430_PRM_BASE 0x4a306000
#define OMAP44XX_PRM_REGADDR(inst, reg) \ #define OMAP44XX_PRM_REGADDR(inst, reg) \
OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (inst) + (reg)) OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (inst) + (reg))
/* PRM instances */ /* PRM instances */
...@@ -46,30 +46,18 @@ ...@@ -46,30 +46,18 @@
#define OMAP4430_PRM_CAM_INST 0x1000 #define OMAP4430_PRM_CAM_INST 0x1000
#define OMAP4430_PRM_DSS_INST 0x1100 #define OMAP4430_PRM_DSS_INST 0x1100
#define OMAP4430_PRM_GFX_INST 0x1200 #define OMAP4430_PRM_GFX_INST 0x1200
#define OMAP4430_PRM_L3INIT_INST 0x1300 #define OMAP4430_PRM_L3INIT_INST 0x1300
#define OMAP4430_PRM_L4PER_INST 0x1400 #define OMAP4430_PRM_L4PER_INST 0x1400
#define OMAP4430_PRM_CEFUSE_INST 0x1600 #define OMAP4430_PRM_CEFUSE_INST 0x1600
#define OMAP4430_PRM_WKUP_INST 0x1700 #define OMAP4430_PRM_WKUP_INST 0x1700
#define OMAP4430_PRM_WKUP_CM_INST 0x1800 #define OMAP4430_PRM_WKUP_CM_INST 0x1800
#define OMAP4430_PRM_EMU_INST 0x1900 #define OMAP4430_PRM_EMU_INST 0x1900
#define OMAP4430_PRM_EMU_CM_INST 0x1a00 #define OMAP4430_PRM_EMU_CM_INST 0x1a00
#define OMAP4430_PRM_DEVICE_INST 0x1b00 #define OMAP4430_PRM_DEVICE_INST 0x1b00
#define OMAP4430_PRM_INSTR_INST 0x1f00 #define OMAP4430_PRM_INSTR_INST 0x1f00
/* PRM clockdomain register offsets (from instance start) */ /* PRM clockdomain register offsets (from instance start) */
#define OMAP4430_PRM_MPU_MPU_CDOFFS 0x0000
#define OMAP4430_PRM_TESLA_TESLA_CDOFFS 0x0000
#define OMAP4430_PRM_ABE_ABE_CDOFFS 0x0000
#define OMAP4430_PRM_CORE_CORE_CDOFFS 0x0000
#define OMAP4430_PRM_IVAHD_IVAHD_CDOFFS 0x0000
#define OMAP4430_PRM_CAM_CAM_CDOFFS 0x0000
#define OMAP4430_PRM_DSS_DSS_CDOFFS 0x0000
#define OMAP4430_PRM_GFX_GFX_CDOFFS 0x0000
#define OMAP4430_PRM_L3INIT_L3INIT_CDOFFS 0x0000
#define OMAP4430_PRM_L4PER_L4PER_CDOFFS 0x0000
#define OMAP4430_PRM_CEFUSE_CEFUSE_CDOFFS 0x0000
#define OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS 0x0000 #define OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS 0x0000
#define OMAP4430_PRM_EMU_EMU_CDOFFS 0x0000
#define OMAP4430_PRM_EMU_CM_EMU_CDOFFS 0x0000 #define OMAP4430_PRM_EMU_CM_EMU_CDOFFS 0x0000
/* OMAP4 specific register offsets */ /* OMAP4 specific register offsets */
...@@ -247,8 +235,8 @@ ...@@ -247,8 +235,8 @@
#define OMAP4430_RM_MEMIF_DLL_H_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0464) #define OMAP4430_RM_MEMIF_DLL_H_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0464)
#define OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET 0x0524 #define OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET 0x0524
#define OMAP4430_RM_D2D_SAD2D_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0524) #define OMAP4430_RM_D2D_SAD2D_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0524)
#define OMAP4_RM_D2D_INSTEM_ICR_CONTEXT_OFFSET 0x052c #define OMAP4_RM_D2D_MODEM_ICR_CONTEXT_OFFSET 0x052c
#define OMAP4430_RM_D2D_INSTEM_ICR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x052c) #define OMAP4430_RM_D2D_MODEM_ICR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x052c)
#define OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET 0x0534 #define OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET 0x0534
#define OMAP4430_RM_D2D_SAD2D_FW_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0534) #define OMAP4430_RM_D2D_SAD2D_FW_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0534)
#define OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET 0x0624 #define OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET 0x0624
...@@ -713,8 +701,8 @@ ...@@ -713,8 +701,8 @@
#define OMAP4430_PRM_VC_VAL_BYPASS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a0) #define OMAP4430_PRM_VC_VAL_BYPASS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a0)
#define OMAP4_PRM_VC_CFG_CHANNEL_OFFSET 0x00a4 #define OMAP4_PRM_VC_CFG_CHANNEL_OFFSET 0x00a4
#define OMAP4430_PRM_VC_CFG_CHANNEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a4) #define OMAP4430_PRM_VC_CFG_CHANNEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a4)
#define OMAP4_PRM_VC_CFG_I2C_INSTE_OFFSET 0x00a8 #define OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET 0x00a8
#define OMAP4430_PRM_VC_CFG_I2C_INSTE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a8) #define OMAP4430_PRM_VC_CFG_I2C_MODE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a8)
#define OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET 0x00ac #define OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET 0x00ac
#define OMAP4430_PRM_VC_CFG_I2C_CLK OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ac) #define OMAP4430_PRM_VC_CFG_I2C_CLK OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ac)
#define OMAP4_PRM_SRAM_COUNT_OFFSET 0x00b0 #define OMAP4_PRM_SRAM_COUNT_OFFSET 0x00b0
...@@ -751,8 +739,8 @@ ...@@ -751,8 +739,8 @@
#define OMAP4430_PRM_PHASE2A_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ec) #define OMAP4430_PRM_PHASE2A_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ec)
#define OMAP4_PRM_PHASE2B_CNDP_OFFSET 0x00f0 #define OMAP4_PRM_PHASE2B_CNDP_OFFSET 0x00f0
#define OMAP4430_PRM_PHASE2B_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f0) #define OMAP4430_PRM_PHASE2B_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f0)
#define OMAP4_PRM_INSTEM_IF_CTRL_OFFSET 0x00f4 #define OMAP4_PRM_MODEM_IF_CTRL_OFFSET 0x00f4
#define OMAP4430_PRM_INSTEM_IF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f4) #define OMAP4430_PRM_MODEM_IF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f4)
#define OMAP4_PRM_VC_ERRST_OFFSET 0x00f8 #define OMAP4_PRM_VC_ERRST_OFFSET 0x00f8
#define OMAP4430_PRM_VC_ERRST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f8) #define OMAP4430_PRM_VC_ERRST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f8)
......
arch/arm/plat-omap/Kconfig
浏览文件 @ c402c0d9
...@@ -211,9 +211,6 @@ choice ...@@ -211,9 +211,6 @@ choice
depends on ARCH_OMAP depends on ARCH_OMAP
default OMAP_PM_NOOP default OMAP_PM_NOOP
config OMAP_PM_NONE
bool "No PM layer"
config OMAP_PM_NOOP config OMAP_PM_NOOP
bool "No-op/debug PM layer" bool "No-op/debug PM layer"
......
arch/arm/plat-omap/include/plat/clock.h
浏览文件 @ c402c0d9
...@@ -152,7 +152,7 @@ struct dpll_data { ...@@ -152,7 +152,7 @@ struct dpll_data {
u16 max_multiplier; u16 max_multiplier;
u8 last_rounded_n; u8 last_rounded_n;
u8 min_divider; u8 min_divider;
u8 max_divider; u16 max_divider;
u8 modes; u8 modes;
#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
void __iomem *autoidle_reg; void __iomem *autoidle_reg;
......
arch/arm/plat-omap/include/plat/omap-pm.h
浏览文件 @ c402c0d9
...@@ -40,11 +40,7 @@ ...@@ -40,11 +40,7 @@
* framework starts. The "_if_" is to avoid name collisions with the * framework starts. The "_if_" is to avoid name collisions with the
* PM idle-loop code. * PM idle-loop code.
*/ */
#ifdef CONFIG_OMAP_PM_NONE
#define omap_pm_if_early_init() 0
#else
int __init omap_pm_if_early_init(void); int __init omap_pm_if_early_init(void);
#endif
/** /**
* omap_pm_if_init - OMAP PM init code called after clock fw init * omap_pm_if_init - OMAP PM init code called after clock fw init
...@@ -52,11 +48,7 @@ int __init omap_pm_if_early_init(void); ...@@ -52,11 +48,7 @@ int __init omap_pm_if_early_init(void);
* The main initialization code. OPP tables are passed in here. The * The main initialization code. OPP tables are passed in here. The
* "_if_" is to avoid name collisions with the PM idle-loop code. * "_if_" is to avoid name collisions with the PM idle-loop code.
*/ */
#ifdef CONFIG_OMAP_PM_NONE
#define omap_pm_if_init() 0
#else
int __init omap_pm_if_init(void); int __init omap_pm_if_init(void);
#endif
/** /**
* omap_pm_if_exit - OMAP PM exit code * omap_pm_if_exit - OMAP PM exit code
......
arch/arm/plat-omap/include/plat/omap_hwmod.h
浏览文件 @ c402c0d9
...@@ -77,7 +77,6 @@ extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2; ...@@ -77,7 +77,6 @@ extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2;
#define HWMOD_IDLEMODE_FORCE (1 << 0) #define HWMOD_IDLEMODE_FORCE (1 << 0)
#define HWMOD_IDLEMODE_NO (1 << 1) #define HWMOD_IDLEMODE_NO (1 << 1)
#define HWMOD_IDLEMODE_SMART (1 << 2) #define HWMOD_IDLEMODE_SMART (1 << 2)
/* Slave idle mode flag only */
#define HWMOD_IDLEMODE_SMART_WKUP (1 << 3) #define HWMOD_IDLEMODE_SMART_WKUP (1 << 3)
/** /**
...@@ -98,7 +97,7 @@ struct omap_hwmod_mux_info { ...@@ -98,7 +97,7 @@ struct omap_hwmod_mux_info {
/** /**
* struct omap_hwmod_irq_info - MPU IRQs used by the hwmod * struct omap_hwmod_irq_info - MPU IRQs used by the hwmod
* @name: name of the IRQ channel (module local name) * @name: name of the IRQ channel (module local name)
* @irq_ch: IRQ channel ID * @irq: IRQ channel ID (should be non-negative except -1 = terminator)
* *
* @name should be something short, e.g., "tx" or "rx". It is for use * @name should be something short, e.g., "tx" or "rx". It is for use
* by platform_get_resource_byname(). It is defined locally to the * by platform_get_resource_byname(). It is defined locally to the
...@@ -106,13 +105,13 @@ struct omap_hwmod_mux_info { ...@@ -106,13 +105,13 @@ struct omap_hwmod_mux_info {
*/ */
struct omap_hwmod_irq_info { struct omap_hwmod_irq_info {
const char *name; const char *name;
u16 irq; s16 irq;
}; };
/** /**
* struct omap_hwmod_dma_info - DMA channels used by the hwmod * struct omap_hwmod_dma_info - DMA channels used by the hwmod
* @name: name of the DMA channel (module local name) * @name: name of the DMA channel (module local name)
* @dma_req: DMA request ID * @dma_req: DMA request ID (should be non-negative except -1 = terminator)
* *
* @name should be something short, e.g., "tx" or "rx". It is for use * @name should be something short, e.g., "tx" or "rx". It is for use
* by platform_get_resource_byname(). It is defined locally to the * by platform_get_resource_byname(). It is defined locally to the
...@@ -120,7 +119,7 @@ struct omap_hwmod_irq_info { ...@@ -120,7 +119,7 @@ struct omap_hwmod_irq_info {
*/ */
struct omap_hwmod_dma_info { struct omap_hwmod_dma_info {
const char *name; const char *name;
u16 dma_req; s16 dma_req;
}; };
/** /**
...@@ -220,7 +219,6 @@ struct omap_hwmod_addr_space { ...@@ -220,7 +219,6 @@ struct omap_hwmod_addr_space {
* @clk: interface clock: OMAP clock name * @clk: interface clock: OMAP clock name
* @_clk: pointer to the interface struct clk (filled in at runtime) * @_clk: pointer to the interface struct clk (filled in at runtime)
* @fw: interface firewall data * @fw: interface firewall data
* @addr_cnt: ARRAY_SIZE(@addr)
* @width: OCP data width * @width: OCP data width
* @user: initiators using this interface (see OCP_USER_* macros above) * @user: initiators using this interface (see OCP_USER_* macros above)
* @flags: OCP interface flags (see OCPIF_* macros above) * @flags: OCP interface flags (see OCPIF_* macros above)
...@@ -239,7 +237,6 @@ struct omap_hwmod_ocp_if { ...@@ -239,7 +237,6 @@ struct omap_hwmod_ocp_if {
union { union {
struct omap_hwmod_omap2_firewall omap2; struct omap_hwmod_omap2_firewall omap2;
} fw; } fw;
u8 addr_cnt;
u8 width; u8 width;
u8 user; u8 user;
u8 flags; u8 flags;
...@@ -258,6 +255,7 @@ struct omap_hwmod_ocp_if { ...@@ -258,6 +255,7 @@ struct omap_hwmod_ocp_if {
#define MSTANDBY_FORCE (HWMOD_IDLEMODE_FORCE << MASTER_STANDBY_SHIFT) #define MSTANDBY_FORCE (HWMOD_IDLEMODE_FORCE << MASTER_STANDBY_SHIFT)
#define MSTANDBY_NO (HWMOD_IDLEMODE_NO << MASTER_STANDBY_SHIFT) #define MSTANDBY_NO (HWMOD_IDLEMODE_NO << MASTER_STANDBY_SHIFT)
#define MSTANDBY_SMART (HWMOD_IDLEMODE_SMART << MASTER_STANDBY_SHIFT) #define MSTANDBY_SMART (HWMOD_IDLEMODE_SMART << MASTER_STANDBY_SHIFT)
#define MSTANDBY_SMART_WKUP (HWMOD_IDLEMODE_SMART_WKUP << MASTER_STANDBY_SHIFT)
/* omap_hwmod_sysconfig.sysc_flags capability flags */ /* omap_hwmod_sysconfig.sysc_flags capability flags */
#define SYSC_HAS_AUTOIDLE (1 << 0) #define SYSC_HAS_AUTOIDLE (1 << 0)
...@@ -468,8 +466,8 @@ struct omap_hwmod_class { ...@@ -468,8 +466,8 @@ struct omap_hwmod_class {
* @name: name of the hwmod * @name: name of the hwmod
* @class: struct omap_hwmod_class * to the class of this hwmod * @class: struct omap_hwmod_class * to the class of this hwmod
* @od: struct omap_device currently associated with this hwmod (internal use) * @od: struct omap_device currently associated with this hwmod (internal use)
* @mpu_irqs: ptr to an array of MPU IRQs (see also mpu_irqs_cnt) * @mpu_irqs: ptr to an array of MPU IRQs
* @sdma_reqs: ptr to an array of System DMA request IDs (see sdma_reqs_cnt) * @sdma_reqs: ptr to an array of System DMA request IDs
* @prcm: PRCM data pertaining to this hwmod * @prcm: PRCM data pertaining to this hwmod
* @main_clk: main clock: OMAP clock name * @main_clk: main clock: OMAP clock name
* @_clk: pointer to the main struct clk (filled in at runtime) * @_clk: pointer to the main struct clk (filled in at runtime)
...@@ -482,8 +480,6 @@ struct omap_hwmod_class { ...@@ -482,8 +480,6 @@ struct omap_hwmod_class {
* @_sysc_cache: internal-use hwmod flags * @_sysc_cache: internal-use hwmod flags
* @_mpu_rt_va: cached register target start address (internal use) * @_mpu_rt_va: cached register target start address (internal use)
* @_mpu_port_index: cached MPU register target slave ID (internal use) * @_mpu_port_index: cached MPU register target slave ID (internal use)
* @mpu_irqs_cnt: number of @mpu_irqs
* @sdma_reqs_cnt: number of @sdma_reqs
* @opt_clks_cnt: number of @opt_clks * @opt_clks_cnt: number of @opt_clks
* @master_cnt: number of @master entries * @master_cnt: number of @master entries
* @slaves_cnt: number of @slave entries * @slaves_cnt: number of @slave entries
...@@ -531,8 +527,6 @@ struct omap_hwmod { ...@@ -531,8 +527,6 @@ struct omap_hwmod {
u16 flags; u16 flags;
u8 _mpu_port_index; u8 _mpu_port_index;
u8 response_lat; u8 response_lat;
u8 mpu_irqs_cnt;
u8 sdma_reqs_cnt;
u8 rst_lines_cnt; u8 rst_lines_cnt;
u8 opt_clks_cnt; u8 opt_clks_cnt;
u8 masters_cnt; u8 masters_cnt;
......
arch/arm/plat-omap/omap_device.c
浏览文件 @ c402c0d9
...@@ -236,11 +236,6 @@ static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat) ...@@ -236,11 +236,6 @@ static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat)
return 0; return 0;
} }
static inline struct omap_device *_find_by_pdev(struct platform_device *pdev)
{
return container_of(pdev, struct omap_device, pdev);
}
/** /**
* _add_optional_clock_clkdev - Add clkdev entry for hwmod optional clocks * _add_optional_clock_clkdev - Add clkdev entry for hwmod optional clocks
* @od: struct omap_device *od * @od: struct omap_device *od
...@@ -316,7 +311,7 @@ u32 omap_device_get_context_loss_count(struct platform_device *pdev) ...@@ -316,7 +311,7 @@ u32 omap_device_get_context_loss_count(struct platform_device *pdev)
struct omap_device *od; struct omap_device *od;
u32 ret = 0; u32 ret = 0;
od = _find_by_pdev(pdev); od = to_omap_device(pdev);
if (od->hwmods_cnt) if (od->hwmods_cnt)
ret = omap_hwmod_get_context_loss_count(od->hwmods[0]); ret = omap_hwmod_get_context_loss_count(od->hwmods[0]);
...@@ -611,7 +606,7 @@ int omap_device_enable(struct platform_device *pdev) ...@@ -611,7 +606,7 @@ int omap_device_enable(struct platform_device *pdev)
int ret; int ret;
struct omap_device *od; struct omap_device *od;
od = _find_by_pdev(pdev); od = to_omap_device(pdev);
if (od->_state == OMAP_DEVICE_STATE_ENABLED) { if (od->_state == OMAP_DEVICE_STATE_ENABLED) {
WARN(1, "omap_device: %s.%d: %s() called from invalid state %d\n", WARN(1, "omap_device: %s.%d: %s() called from invalid state %d\n",
...@@ -650,7 +645,7 @@ int omap_device_idle(struct platform_device *pdev) ...@@ -650,7 +645,7 @@ int omap_device_idle(struct platform_device *pdev)
int ret; int ret;
struct omap_device *od; struct omap_device *od;
od = _find_by_pdev(pdev); od = to_omap_device(pdev);
if (od->_state != OMAP_DEVICE_STATE_ENABLED) { if (od->_state != OMAP_DEVICE_STATE_ENABLED) {
WARN(1, "omap_device: %s.%d: %s() called from invalid state %d\n", WARN(1, "omap_device: %s.%d: %s() called from invalid state %d\n",
...@@ -681,7 +676,7 @@ int omap_device_shutdown(struct platform_device *pdev) ...@@ -681,7 +676,7 @@ int omap_device_shutdown(struct platform_device *pdev)
int ret, i; int ret, i;
struct omap_device *od; struct omap_device *od;
od = _find_by_pdev(pdev); od = to_omap_device(pdev);
if (od->_state != OMAP_DEVICE_STATE_ENABLED && if (od->_state != OMAP_DEVICE_STATE_ENABLED &&
od->_state != OMAP_DEVICE_STATE_IDLE) { od->_state != OMAP_DEVICE_STATE_IDLE) {
...@@ -722,7 +717,7 @@ int omap_device_align_pm_lat(struct platform_device *pdev, ...@@ -722,7 +717,7 @@ int omap_device_align_pm_lat(struct platform_device *pdev,
int ret = -EINVAL; int ret = -EINVAL;
struct omap_device *od; struct omap_device *od;
od = _find_by_pdev(pdev); od = to_omap_device(pdev);
if (new_wakeup_lat_limit == od->dev_wakeup_lat) if (new_wakeup_lat_limit == od->dev_wakeup_lat)
return 0; return 0;
......
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