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提交 bd6a6b43 编写于 作者: A Alex Deucher
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drm/amdgpu: add GMC 8.1 register headers 

These are register headers for the GMC (Graphics Memory Controller)
block on the GPU.
Acked-by: NChristian König <christian.koenig@amd.com>
Acked-by: NJammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
上级 97330527
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drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_d.h 0 → 100644
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/*
* GMC_8_1 Register documentation
*
* Copyright (C) 2014 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef GMC_8_1_D_H
#define GMC_8_1_D_H
#define mmMC_CONFIG 0x800
#define mmMC_ARB_ATOMIC 0x9be
#define mmMC_ARB_AGE_CNTL 0x9bf
#define mmMC_ARB_RET_CREDITS2 0x9c0
#define mmMC_ARB_FED_CNTL 0x9c1
#define mmMC_ARB_GECC2_STATUS 0x9c2
#define mmMC_ARB_GECC2_MISC 0x9c3
#define mmMC_ARB_GECC2_DEBUG 0x9c4
#define mmMC_ARB_GECC2_DEBUG2 0x9c5
#define mmMC_ARB_PERF_CID 0x9c6
#define mmMC_ARB_SNOOP 0x9c7
#define mmMC_ARB_GRUB 0x9c8
#define mmMC_ARB_GECC2 0x9c9
#define mmMC_ARB_GECC2_CLI 0x9ca
#define mmMC_ARB_ADDR_SWIZ0 0x9cb
#define mmMC_ARB_ADDR_SWIZ1 0x9cc
#define mmMC_ARB_MISC3 0x9cd
#define mmMC_ARB_GRUB_PROMOTE 0x9ce
#define mmMC_ARB_RTT_DATA 0x9cf
#define mmMC_ARB_RTT_CNTL0 0x9d0
#define mmMC_ARB_RTT_CNTL1 0x9d1
#define mmMC_ARB_RTT_CNTL2 0x9d2
#define mmMC_ARB_RTT_DEBUG 0x9d3
#define mmMC_ARB_CAC_CNTL 0x9d4
#define mmMC_ARB_MISC2 0x9d5
#define mmMC_ARB_MISC 0x9d6
#define mmMC_ARB_BANKMAP 0x9d7
#define mmMC_ARB_RAMCFG 0x9d8
#define mmMC_ARB_POP 0x9d9
#define mmMC_ARB_MINCLKS 0x9da
#define mmMC_ARB_SQM_CNTL 0x9db
#define mmMC_ARB_ADDR_HASH 0x9dc
#define mmMC_ARB_DRAM_TIMING 0x9dd
#define mmMC_ARB_DRAM_TIMING2 0x9de
#define mmMC_ARB_WTM_CNTL_RD 0x9df
#define mmMC_ARB_WTM_CNTL_WR 0x9e0
#define mmMC_ARB_WTM_GRPWT_RD 0x9e1
#define mmMC_ARB_WTM_GRPWT_WR 0x9e2
#define mmMC_ARB_TM_CNTL_RD 0x9e3
#define mmMC_ARB_TM_CNTL_WR 0x9e4
#define mmMC_ARB_LAZY0_RD 0x9e5
#define mmMC_ARB_LAZY0_WR 0x9e6
#define mmMC_ARB_LAZY1_RD 0x9e7
#define mmMC_ARB_LAZY1_WR 0x9e8
#define mmMC_ARB_AGE_RD 0x9e9
#define mmMC_ARB_AGE_WR 0x9ea
#define mmMC_ARB_RFSH_CNTL 0x9eb
#define mmMC_ARB_RFSH_RATE 0x9ec
#define mmMC_ARB_PM_CNTL 0x9ed
#define mmMC_ARB_GDEC_RD_CNTL 0x9ee
#define mmMC_ARB_GDEC_WR_CNTL 0x9ef
#define mmMC_ARB_LM_RD 0x9f0
#define mmMC_ARB_LM_WR 0x9f1
#define mmMC_ARB_REMREQ 0x9f2
#define mmMC_ARB_REPLAY 0x9f3
#define mmMC_ARB_RET_CREDITS_RD 0x9f4
#define mmMC_ARB_RET_CREDITS_WR 0x9f5
#define mmMC_ARB_MAX_LAT_CID 0x9f6
#define mmMC_ARB_MAX_LAT_RSLT0 0x9f7
#define mmMC_ARB_MAX_LAT_RSLT1 0x9f8
#define mmMC_ARB_GRUB_REALTIME_RD 0x9f9
#define mmMC_ARB_CG 0x9fa
#define mmMC_ARB_GRUB_REALTIME_WR 0x9fb
#define mmMC_ARB_DRAM_TIMING_1 0x9fc
#define mmMC_ARB_BUSY_STATUS 0x9fd
#define mmMC_ARB_DRAM_TIMING2_1 0x9ff
#define mmMC_ARB_GRUB2 0xa01
#define mmMC_ARB_BURST_TIME 0xa02
#define mmMC_CITF_XTRA_ENABLE 0x96d
#define mmCC_MC_MAX_CHANNEL 0x96e
#define mmMC_CG_CONFIG 0x96f
#define mmMC_CITF_CNTL 0x970
#define mmMC_CITF_CREDITS_VM 0x971
#define mmMC_CITF_CREDITS_ARB_RD 0x972
#define mmMC_CITF_CREDITS_ARB_WR 0x973
#define mmMC_CITF_DAGB_CNTL 0x974
#define mmMC_CITF_INT_CREDITS 0x975
#define mmMC_CITF_RET_MODE 0x976
#define mmMC_CITF_DAGB_DLY 0x977
#define mmMC_RD_GRP_EXT 0x978
#define mmMC_WR_GRP_EXT 0x979
#define mmMC_CITF_REMREQ 0x97a
#define mmMC_WR_TC0 0x97b
#define mmMC_WR_TC1 0x97c
#define mmMC_CITF_INT_CREDITS_WR 0x97d
#define mmMC_CITF_CREDITS_ARB_RD2 0x97e
#define mmMC_CITF_WTM_RD_CNTL 0x97f
#define mmMC_CITF_WTM_WR_CNTL 0x980
#define mmMC_RD_CB 0x981
#define mmMC_RD_DB 0x982
#define mmMC_RD_TC0 0x983
#define mmMC_RD_TC1 0x984
#define mmMC_RD_HUB 0x985
#define mmMC_WR_CB 0x986
#define mmMC_WR_DB 0x987
#define mmMC_WR_HUB 0x988
#define mmMC_CITF_CREDITS_XBAR 0x989
#define mmMC_RD_GRP_LCL 0x98a
#define mmMC_WR_GRP_LCL 0x98b
#define mmMC_CITF_PERF_MON_CNTL2 0x98e
#define mmMC_CITF_PERF_MON_RSLT2 0x991
#define mmMC_CITF_MISC_RD_CG 0x992
#define mmMC_CITF_MISC_WR_CG 0x993
#define mmMC_CITF_MISC_VM_CG 0x994
#define mmMC_HUB_MISC_POWER 0x82d
#define mmMC_HUB_MISC_HUB_CG 0x82e
#define mmMC_HUB_MISC_VM_CG 0x82f
#define mmMC_HUB_MISC_SIP_CG 0x830
#define mmMC_HUB_MISC_STATUS 0x832
#define mmMC_HUB_MISC_OVERRIDE 0x833
#define mmMC_HUB_MISC_FRAMING 0x834
#define mmMC_HUB_WDP_CNTL 0x835
#define mmMC_HUB_WDP_ERR 0x836
#define mmMC_HUB_WDP_BP 0x837
#define mmMC_HUB_WDP_STATUS 0x838
#define mmMC_HUB_RDREQ_STATUS 0x839
#define mmMC_HUB_WRRET_STATUS 0x83a
#define mmMC_HUB_RDREQ_CNTL 0x83b
#define mmMC_HUB_WRRET_CNTL 0x83c
#define mmMC_HUB_RDREQ_WTM_CNTL 0x83d
#define mmMC_HUB_WDP_WTM_CNTL 0x83e
#define mmMC_HUB_WDP_CREDITS 0x83f
#define mmMC_HUB_WDP_CREDITS2 0x840
#define mmMC_HUB_WDP_GBL0 0x841
#define mmMC_HUB_WDP_GBL1 0x842
#define mmMC_HUB_WDP_CREDITS3 0x843
#define mmMC_HUB_RDREQ_CREDITS 0x844
#define mmMC_HUB_RDREQ_CREDITS2 0x845
#define mmMC_HUB_SHARED_DAGB_DLY 0x846
#define mmMC_HUB_MISC_IDLE_STATUS 0x847
#define mmMC_HUB_RDREQ_DMIF_LIMIT 0x848
#define mmMC_HUB_RDREQ_ACPG_LIMIT 0x849
#define mmMC_HUB_WDP_BYPASS_GBL0 0x84a
#define mmMC_HUB_WDP_BYPASS_GBL1 0x84b
#define mmMC_HUB_RDREQ_BYPASS_GBL0 0x84c
#define mmMC_HUB_WDP_SH2 0x84d
#define mmMC_HUB_WDP_SH3 0x84e
#define mmMC_HUB_MISC_ATOMIC_IDLE_STATUS 0x84f
#define mmMC_HUB_WDP_VIN0 0x850
#define mmMC_HUB_RDREQ_MCDW 0x851
#define mmMC_HUB_RDREQ_MCDX 0x852
#define mmMC_HUB_RDREQ_MCDY 0x853
#define mmMC_HUB_RDREQ_MCDZ 0x854
#define mmMC_HUB_RDREQ_SIP 0x855
#define mmMC_HUB_RDREQ_GBL0 0x856
#define mmMC_HUB_RDREQ_GBL1 0x857
#define mmMC_HUB_RDREQ_SMU 0x858
#define mmMC_HUB_RDREQ_SDMA0 0x859
#define mmMC_HUB_RDREQ_HDP 0x85a
#define mmMC_HUB_RDREQ_SDMA1 0x85b
#define mmMC_HUB_RDREQ_RLC 0x85c
#define mmMC_HUB_RDREQ_SEM 0x85d
#define mmMC_HUB_RDREQ_VCE0 0x85e
#define mmMC_HUB_RDREQ_UMC 0x85f
#define mmMC_HUB_RDREQ_UVD 0x860
#define mmMC_HUB_RDREQ_TLS 0x861
#define mmMC_HUB_RDREQ_DMIF 0x862
#define mmMC_HUB_RDREQ_MCIF 0x863
#define mmMC_HUB_RDREQ_VMC 0x864
#define mmMC_HUB_RDREQ_VCEU0 0x865
#define mmMC_HUB_WDP_MCDW 0x866
#define mmMC_HUB_WDP_MCDX 0x867
#define mmMC_HUB_WDP_MCDY 0x868
#define mmMC_HUB_WDP_MCDZ 0x869
#define mmMC_HUB_WDP_SIP 0x86a
#define mmMC_HUB_WDP_SDMA1 0x86b
#define mmMC_HUB_WDP_SH0 0x86c
#define mmMC_HUB_WDP_MCIF 0x86d
#define mmMC_HUB_WDP_VCE0 0x86e
#define mmMC_HUB_WDP_XDP 0x86f
#define mmMC_HUB_WDP_IH 0x870
#define mmMC_HUB_WDP_RLC 0x871
#define mmMC_HUB_WDP_SEM 0x872
#define mmMC_HUB_WDP_SMU 0x873
#define mmMC_HUB_WDP_SH1 0x874
#define mmMC_HUB_WDP_UMC 0x875
#define mmMC_HUB_WDP_UVD 0x876
#define mmMC_HUB_WDP_HDP 0x877
#define mmMC_HUB_WDP_SDMA0 0x878
#define mmMC_HUB_WRRET_MCDW 0x879
#define mmMC_HUB_WRRET_MCDX 0x87a
#define mmMC_HUB_WRRET_MCDY 0x87b
#define mmMC_HUB_WRRET_MCDZ 0x87c
#define mmMC_HUB_WDP_VCEU0 0x87d
#define mmMC_HUB_WDP_XDMAM 0x87e
#define mmMC_HUB_WDP_XDMA 0x87f
#define mmMC_HUB_RDREQ_XDMAM 0x880
#define mmMC_HUB_RDREQ_ACPG 0x881
#define mmMC_HUB_RDREQ_ACPO 0x882
#define mmMC_HUB_RDREQ_SAMMSP 0x883
#define mmMC_HUB_RDREQ_VP8 0x884
#define mmMC_HUB_RDREQ_VP8U 0x885
#define mmMC_HUB_WDP_ACPG 0x886
#define mmMC_HUB_WDP_ACPO 0x887
#define mmMC_HUB_WDP_SAMMSP 0x888
#define mmMC_HUB_WDP_VP8 0x889
#define mmMC_HUB_WDP_VP8U 0x88a
#define mmMC_HUB_RDREQ_ISP_SPM 0xde0
#define mmMC_HUB_RDREQ_ISP_MPM 0xde1
#define mmMC_HUB_RDREQ_ISP_CCPU 0xde2
#define mmMC_HUB_WDP_ISP_SPM 0xde3
#define mmMC_HUB_WDP_ISP_MPS 0xde4
#define mmMC_HUB_WDP_ISP_MPM 0xde5
#define mmMC_HUB_WDP_ISP_CCPU 0xde6
#define mmMC_HUB_RDREQ_MCDS 0xde7
#define mmMC_HUB_RDREQ_MCDT 0xde8
#define mmMC_HUB_RDREQ_MCDU 0xde9
#define mmMC_HUB_RDREQ_MCDV 0xdea
#define mmMC_HUB_WDP_MCDS 0xdeb
#define mmMC_HUB_WDP_MCDT 0xdec
#define mmMC_HUB_WDP_MCDU 0xded
#define mmMC_HUB_WDP_MCDV 0xdee
#define mmMC_HUB_WRRET_MCDS 0xdef
#define mmMC_HUB_WRRET_MCDT 0xdf0
#define mmMC_HUB_WRRET_MCDU 0xdf1
#define mmMC_HUB_WRRET_MCDV 0xdf2
#define mmMC_HUB_WDP_CREDITS_MCDW 0xdf3
#define mmMC_HUB_WDP_CREDITS_MCDX 0xdf4
#define mmMC_HUB_WDP_CREDITS_MCDY 0xdf5
#define mmMC_HUB_WDP_CREDITS_MCDZ 0xdf6
#define mmMC_HUB_WDP_CREDITS_MCDS 0xdf7
#define mmMC_HUB_WDP_CREDITS_MCDT 0xdf8
#define mmMC_HUB_WDP_CREDITS_MCDU 0xdf9
#define mmMC_HUB_WDP_CREDITS_MCDV 0xdfa
#define mmMC_HUB_WDP_BP2 0xdfb
#define mmMC_HUB_RDREQ_VCE1 0xdfc
#define mmMC_HUB_RDREQ_VCEU1 0xdfd
#define mmMC_HUB_WDP_VCE1 0xdfe
#define mmMC_HUB_WDP_VCEU1 0xdff
#define mmMC_RPB_CONF 0x94d
#define mmMC_RPB_IF_CONF 0x94e
#define mmMC_RPB_DBG1 0x94f
#define mmMC_RPB_EFF_CNTL 0x950
#define mmMC_RPB_ARB_CNTL 0x951
#define mmMC_RPB_BIF_CNTL 0x952
#define mmMC_RPB_WR_SWITCH_CNTL 0x953
#define mmMC_RPB_WR_COMBINE_CNTL 0x954
#define mmMC_RPB_RD_SWITCH_CNTL 0x955
#define mmMC_RPB_CID_QUEUE_WR 0x956
#define mmMC_RPB_CID_QUEUE_RD 0x957
#define mmMC_RPB_PERF_COUNTER_CNTL 0x958
#define mmMC_RPB_PERF_COUNTER_STATUS 0x959
#define mmMC_RPB_CID_QUEUE_EX 0x95a
#define mmMC_RPB_CID_QUEUE_EX_DATA 0x95b
#define mmMC_RPB_TCI_CNTL 0x95c
#define mmMC_RPB_TCI_CNTL2 0x95d
#define mmMC_SHARED_CHMAP 0x801
#define mmMC_SHARED_CHREMAP 0x802
#define mmMC_RD_GRP_GFX 0x803
#define mmMC_WR_GRP_GFX 0x804
#define mmMC_RD_GRP_SYS 0x805
#define mmMC_WR_GRP_SYS 0x806
#define mmMC_RD_GRP_OTH 0x807
#define mmMC_WR_GRP_OTH 0x808
#define mmMC_VM_FB_LOCATION 0x809
#define mmMC_VM_AGP_TOP 0x80a
#define mmMC_VM_AGP_BOT 0x80b
#define mmMC_VM_AGP_BASE 0x80c
#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x80d
#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x80e
#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x80f
#define mmMC_VM_DC_WRITE_CNTL 0x810
#define mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR 0x811
#define mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR 0x812
#define mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR 0x813
#define mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR 0x814
#define mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR 0x815
#define mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR 0x816
#define mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR 0x817
#define mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR 0x818
#define mmMC_VM_MX_L1_TLB_CNTL 0x819
#define mmMC_VM_FB_OFFSET 0x81a
#define mmMC_VM_STEERING 0x81b
#define mmMC_SHARED_CHREMAP2 0x81c
#define mmMC_SHARED_VF_ENABLE 0x81d
#define mmMC_SHARED_VIRT_RESET_REQ 0x81e
#define mmMC_SHARED_ACTIVE_FCN_ID 0x81f
#define mmMC_CONFIG_MCD 0x828
#define mmMC_CG_CONFIG_MCD 0x829
#define mmMC_MEM_POWER_LS 0x82a
#define mmMC_SHARED_BLACKOUT_CNTL 0x82b
#define mmMC_VM_MB_L1_TLB0_DEBUG 0x891
#define mmMC_VM_MB_L1_TLB1_DEBUG 0x892
#define mmMC_VM_MB_L1_TLB2_DEBUG 0x893
#define mmMC_VM_MB_L1_TLB0_STATUS 0x895
#define mmMC_VM_MB_L1_TLB1_STATUS 0x896
#define mmMC_VM_MB_L1_TLB2_STATUS 0x897
#define mmMC_VM_MB_L2ARBITER_L2_CREDITS 0x8a1
#define mmMC_VM_MB_L1_TLB3_DEBUG 0x8a5
#define mmMC_VM_MB_L1_TLB3_STATUS 0x8a6
#define mmMC_VM_MD_L1_TLB0_DEBUG 0x998
#define mmMC_VM_MD_L1_TLB1_DEBUG 0x999
#define mmMC_VM_MD_L1_TLB2_DEBUG 0x99a
#define mmMC_VM_MD_L1_TLB0_STATUS 0x99b
#define mmMC_VM_MD_L1_TLB1_STATUS 0x99c
#define mmMC_VM_MD_L1_TLB2_STATUS 0x99d
#define mmMC_VM_MD_L2ARBITER_L2_CREDITS 0x9a4
#define mmMC_VM_MD_L1_TLB3_DEBUG 0x9a7
#define mmMC_VM_MD_L1_TLB3_STATUS 0x9a8
#define mmMC_XPB_RTR_SRC_APRTR0 0x8cd
#define mmMC_XPB_RTR_SRC_APRTR1 0x8ce
#define mmMC_XPB_RTR_SRC_APRTR2 0x8cf
#define mmMC_XPB_RTR_SRC_APRTR3 0x8d0
#define mmMC_XPB_RTR_SRC_APRTR4 0x8d1
#define mmMC_XPB_RTR_SRC_APRTR5 0x8d2
#define mmMC_XPB_RTR_SRC_APRTR6 0x8d3
#define mmMC_XPB_RTR_SRC_APRTR7 0x8d4
#define mmMC_XPB_RTR_SRC_APRTR8 0x8d5
#define mmMC_XPB_RTR_SRC_APRTR9 0x8d6
#define mmMC_XPB_XDMA_RTR_SRC_APRTR0 0x8d7
#define mmMC_XPB_XDMA_RTR_SRC_APRTR1 0x8d8
#define mmMC_XPB_XDMA_RTR_SRC_APRTR2 0x8d9
#define mmMC_XPB_XDMA_RTR_SRC_APRTR3 0x8da
#define mmMC_XPB_RTR_DEST_MAP0 0x8db
#define mmMC_XPB_RTR_DEST_MAP1 0x8dc
#define mmMC_XPB_RTR_DEST_MAP2 0x8dd
#define mmMC_XPB_RTR_DEST_MAP3 0x8de
#define mmMC_XPB_RTR_DEST_MAP4 0x8df
#define mmMC_XPB_RTR_DEST_MAP5 0x8e0
#define mmMC_XPB_RTR_DEST_MAP6 0x8e1
#define mmMC_XPB_RTR_DEST_MAP7 0x8e2
#define mmMC_XPB_RTR_DEST_MAP8 0x8e3
#define mmMC_XPB_RTR_DEST_MAP9 0x8e4
#define mmMC_XPB_XDMA_RTR_DEST_MAP0 0x8e5
#define mmMC_XPB_XDMA_RTR_DEST_MAP1 0x8e6
#define mmMC_XPB_XDMA_RTR_DEST_MAP2 0x8e7
#define mmMC_XPB_XDMA_RTR_DEST_MAP3 0x8e8
#define mmMC_XPB_CLG_CFG0 0x8e9
#define mmMC_XPB_CLG_CFG1 0x8ea
#define mmMC_XPB_CLG_CFG2 0x8eb
#define mmMC_XPB_CLG_CFG3 0x8ec
#define mmMC_XPB_CLG_CFG4 0x8ed
#define mmMC_XPB_CLG_CFG5 0x8ee
#define mmMC_XPB_CLG_CFG6 0x8ef
#define mmMC_XPB_CLG_CFG7 0x8f0
#define mmMC_XPB_CLG_CFG8 0x8f1
#define mmMC_XPB_CLG_CFG9 0x8f2
#define mmMC_XPB_CLG_CFG10 0x8f3
#define mmMC_XPB_CLG_CFG11 0x8f4
#define mmMC_XPB_CLG_CFG12 0x8f5
#define mmMC_XPB_CLG_CFG13 0x8f6
#define mmMC_XPB_CLG_CFG14 0x8f7
#define mmMC_XPB_CLG_CFG15 0x8f8
#define mmMC_XPB_CLG_CFG16 0x8f9
#define mmMC_XPB_CLG_CFG17 0x8fa
#define mmMC_XPB_CLG_CFG18 0x8fb
#define mmMC_XPB_CLG_CFG19 0x8fc
#define mmMC_XPB_CLG_EXTRA 0x8fd
#define mmMC_XPB_LB_ADDR 0x8fe
#define mmMC_XPB_UNC_THRESH_HST 0x8ff
#define mmMC_XPB_UNC_THRESH_SID 0x900
#define mmMC_XPB_WCB_STS 0x901
#define mmMC_XPB_WCB_CFG 0x902
#define mmMC_XPB_P2P_BAR_CFG 0x903
#define mmMC_XPB_P2P_BAR0 0x904
#define mmMC_XPB_P2P_BAR1 0x905
#define mmMC_XPB_P2P_BAR2 0x906
#define mmMC_XPB_P2P_BAR3 0x907
#define mmMC_XPB_P2P_BAR4 0x908
#define mmMC_XPB_P2P_BAR5 0x909
#define mmMC_XPB_P2P_BAR6 0x90a
#define mmMC_XPB_P2P_BAR7 0x90b
#define mmMC_XPB_P2P_BAR_SETUP 0x90c
#define mmMC_XPB_P2P_BAR_DEBUG 0x90d
#define mmMC_XPB_P2P_BAR_DELTA_ABOVE 0x90e
#define mmMC_XPB_P2P_BAR_DELTA_BELOW 0x90f
#define mmMC_XPB_PEER_SYS_BAR0 0x910
#define mmMC_XPB_PEER_SYS_BAR1 0x911
#define mmMC_XPB_PEER_SYS_BAR2 0x912
#define mmMC_XPB_PEER_SYS_BAR3 0x913
#define mmMC_XPB_PEER_SYS_BAR4 0x914
#define mmMC_XPB_PEER_SYS_BAR5 0x915
#define mmMC_XPB_PEER_SYS_BAR6 0x916
#define mmMC_XPB_PEER_SYS_BAR7 0x917
#define mmMC_XPB_PEER_SYS_BAR8 0x918
#define mmMC_XPB_PEER_SYS_BAR9 0x919
#define mmMC_XPB_XDMA_PEER_SYS_BAR0 0x91a
#define mmMC_XPB_XDMA_PEER_SYS_BAR1 0x91b
#define mmMC_XPB_XDMA_PEER_SYS_BAR2 0x91c
#define mmMC_XPB_XDMA_PEER_SYS_BAR3 0x91d
#define mmMC_XPB_CLK_GAT 0x91e
#define mmMC_XPB_INTF_CFG 0x91f
#define mmMC_XPB_INTF_STS 0x920
#define mmMC_XPB_PIPE_STS 0x921
#define mmMC_XPB_SUB_CTRL 0x922
#define mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB 0x923
#define mmMC_XPB_PERF_KNOBS 0x924
#define mmMC_XPB_STICKY 0x925
#define mmMC_XPB_STICKY_W1C 0x926
#define mmMC_XPB_MISC_CFG 0x927
#define mmMC_XPB_CLG_CFG20 0x928
#define mmMC_XPB_CLG_CFG21 0x929
#define mmMC_XPB_CLG_CFG22 0x92a
#define mmMC_XPB_CLG_CFG23 0x92b
#define mmMC_XPB_CLG_CFG24 0x92c
#define mmMC_XPB_CLG_CFG25 0x92d
#define mmMC_XPB_CLG_CFG26 0x92e
#define mmMC_XPB_CLG_CFG27 0x92f
#define mmMC_XPB_CLG_CFG28 0x930
#define mmMC_XPB_CLG_CFG29 0x931
#define mmMC_XPB_CLG_CFG30 0x932
#define mmMC_XPB_CLG_CFG31 0x933
#define mmMC_XPB_INTF_CFG2 0x934
#define mmMC_XPB_CLG_EXTRA_RD 0x935
#define mmMC_XPB_CLG_CFG32 0x936
#define mmMC_XPB_CLG_CFG33 0x937
#define mmMC_XPB_CLG_CFG34 0x938
#define mmMC_XPB_CLG_CFG35 0x939
#define mmMC_XPB_CLG_CFG36 0x93a
#define mmMC_XBAR_ADDR_DEC 0xc80
#define mmMC_XBAR_REMOTE 0xc81
#define mmMC_XBAR_WRREQ_CREDIT 0xc82
#define mmMC_XBAR_RDREQ_CREDIT 0xc83
#define mmMC_XBAR_RDREQ_PRI_CREDIT 0xc84
#define mmMC_XBAR_WRRET_CREDIT1 0xc85
#define mmMC_XBAR_WRRET_CREDIT2 0xc86
#define mmMC_XBAR_RDRET_CREDIT1 0xc87
#define mmMC_XBAR_RDRET_CREDIT2 0xc88
#define mmMC_XBAR_RDRET_PRI_CREDIT1 0xc89
#define mmMC_XBAR_RDRET_PRI_CREDIT2 0xc8a
#define mmMC_XBAR_CHTRIREMAP 0xc8b
#define mmMC_XBAR_TWOCHAN 0xc8c
#define mmMC_XBAR_ARB 0xc8d
#define mmMC_XBAR_ARB_MAX_BURST 0xc8e
#define mmMC_XBAR_FIFO_MON_CNTL0 0xc8f
#define mmMC_XBAR_FIFO_MON_CNTL1 0xc90
#define mmMC_XBAR_FIFO_MON_CNTL2 0xc91
#define mmMC_XBAR_FIFO_MON_RSLT0 0xc92
#define mmMC_XBAR_FIFO_MON_RSLT1 0xc93
#define mmMC_XBAR_FIFO_MON_RSLT2 0xc94
#define mmMC_XBAR_FIFO_MON_RSLT3 0xc95
#define mmMC_XBAR_FIFO_MON_MAX_THSH 0xc96
#define mmMC_XBAR_SPARE0 0xc97
#define mmMC_XBAR_SPARE1 0xc98
#define mmMC_CITF_PERFCOUNTER_LO 0x7a0
#define mmMC_HUB_PERFCOUNTER_LO 0x7a1
#define mmMC_RPB_PERFCOUNTER_LO 0x7a2
#define mmMC_MCBVM_PERFCOUNTER_LO 0x7a3
#define mmMC_MCDVM_PERFCOUNTER_LO 0x7a4
#define mmMC_VM_L2_PERFCOUNTER_LO 0x7a5
#define mmMC_ARB_PERFCOUNTER_LO 0x7a6
#define mmATC_PERFCOUNTER_LO 0x7a7
#define mmMC_CITF_PERFCOUNTER_HI 0x7a8
#define mmMC_HUB_PERFCOUNTER_HI 0x7a9
#define mmMC_MCBVM_PERFCOUNTER_HI 0x7aa
#define mmMC_MCDVM_PERFCOUNTER_HI 0x7ab
#define mmMC_RPB_PERFCOUNTER_HI 0x7ac
#define mmMC_VM_L2_PERFCOUNTER_HI 0x7ad
#define mmMC_ARB_PERFCOUNTER_HI 0x7ae
#define mmATC_PERFCOUNTER_HI 0x7af
#define mmMC_CITF_PERFCOUNTER0_CFG 0x7b0
#define mmMC_CITF_PERFCOUNTER1_CFG 0x7b1
#define mmMC_CITF_PERFCOUNTER2_CFG 0x7b2
#define mmMC_CITF_PERFCOUNTER3_CFG 0x7b3
#define mmMC_HUB_PERFCOUNTER0_CFG 0x7b4
#define mmMC_HUB_PERFCOUNTER1_CFG 0x7b5
#define mmMC_HUB_PERFCOUNTER2_CFG 0x7b6
#define mmMC_HUB_PERFCOUNTER3_CFG 0x7b7
#define mmMC_RPB_PERFCOUNTER0_CFG 0x7b8
#define mmMC_RPB_PERFCOUNTER1_CFG 0x7b9
#define mmMC_RPB_PERFCOUNTER2_CFG 0x7ba
#define mmMC_RPB_PERFCOUNTER3_CFG 0x7bb
#define mmMC_ARB_PERFCOUNTER0_CFG 0x7bc
#define mmMC_ARB_PERFCOUNTER1_CFG 0x7bd
#define mmMC_ARB_PERFCOUNTER2_CFG 0x7be
#define mmMC_ARB_PERFCOUNTER3_CFG 0x7bf
#define mmMC_MCBVM_PERFCOUNTER0_CFG 0x7c0
#define mmMC_MCBVM_PERFCOUNTER1_CFG 0x7c1
#define mmMC_MCBVM_PERFCOUNTER2_CFG 0x7c2
#define mmMC_MCBVM_PERFCOUNTER3_CFG 0x7c3
#define mmMC_MCDVM_PERFCOUNTER0_CFG 0x7c4
#define mmMC_MCDVM_PERFCOUNTER1_CFG 0x7c5
#define mmMC_MCDVM_PERFCOUNTER2_CFG 0x7c6
#define mmMC_MCDVM_PERFCOUNTER3_CFG 0x7c7
#define mmATC_PERFCOUNTER0_CFG 0x7c8
#define mmATC_PERFCOUNTER1_CFG 0x7c9
#define mmATC_PERFCOUNTER2_CFG 0x7ca
#define mmATC_PERFCOUNTER3_CFG 0x7cb
#define mmMC_VM_L2_PERFCOUNTER0_CFG 0x7cc
#define mmMC_VM_L2_PERFCOUNTER1_CFG 0x7cd
#define mmMC_CITF_PERFCOUNTER_RSLT_CNTL 0x7ce
#define mmMC_HUB_PERFCOUNTER_RSLT_CNTL 0x7cf
#define mmMC_RPB_PERFCOUNTER_RSLT_CNTL 0x7d0
#define mmMC_MCBVM_PERFCOUNTER_RSLT_CNTL 0x7d1
#define mmMC_MCDVM_PERFCOUNTER_RSLT_CNTL 0x7d2
#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x7d3
#define mmMC_ARB_PERFCOUNTER_RSLT_CNTL 0x7d4
#define mmATC_PERFCOUNTER_RSLT_CNTL 0x7d5
#define mmCHUB_ATC_PERFCOUNTER_LO 0x7d6
#define mmCHUB_ATC_PERFCOUNTER_HI 0x7d7
#define mmCHUB_ATC_PERFCOUNTER0_CFG 0x7d8
#define mmCHUB_ATC_PERFCOUNTER1_CFG 0x7d9
#define mmCHUB_ATC_PERFCOUNTER_RSLT_CNTL 0x7da
#define mmATC_VM_APERTURE0_LOW_ADDR 0xcc0
#define mmATC_VM_APERTURE1_LOW_ADDR 0xcc1
#define mmATC_VM_APERTURE0_HIGH_ADDR 0xcc2
#define mmATC_VM_APERTURE1_HIGH_ADDR 0xcc3
#define mmATC_VM_APERTURE0_CNTL 0xcc4
#define mmATC_VM_APERTURE1_CNTL 0xcc5
#define mmATC_VM_APERTURE0_CNTL2 0xcc6
#define mmATC_VM_APERTURE1_CNTL2 0xcc7
#define mmATC_ATS_CNTL 0xcc9
#define mmATC_ATS_DEBUG 0xcca
#define mmATC_ATS_FAULT_DEBUG 0xccb
#define mmATC_ATS_STATUS 0xccc
#define mmATC_ATS_FAULT_CNTL 0xccd
#define mmATC_ATS_FAULT_STATUS_INFO 0xcce
#define mmATC_ATS_FAULT_STATUS_ADDR 0xccf
#define mmATC_ATS_DEFAULT_PAGE_LOW 0xcd0
#define mmATC_ATS_DEFAULT_PAGE_CNTL 0xcd1
#define mmATC_ATS_FAULT_STATUS_INFO2 0xcd2
#define mmATC_MISC_CG 0xcd4
#define mmATC_L2_CNTL 0xcd5
#define mmATC_L2_CNTL2 0xcd6
#define mmATC_L2_DEBUG 0xcd7
#define mmATC_L2_DEBUG2 0xcd8
#define mmATC_L2_CACHE_DATA0 0xcd9
#define mmATC_L2_CACHE_DATA1 0xcda
#define mmATC_L2_CACHE_DATA2 0xcdb
#define mmATC_L1_CNTL 0xcdc
#define mmATC_L1_ADDRESS_OFFSET 0xcdd
#define mmATC_L1RD_DEBUG_TLB 0xcde
#define mmATC_L1WR_DEBUG_TLB 0xcdf
#define mmATC_L1RD_STATUS 0xce0
#define mmATC_L1WR_STATUS 0xce1
#define mmATC_L1RD_DEBUG2_TLB 0xce2
#define mmATC_L1WR_DEBUG2_TLB 0xce3
#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS 0xce6
#define mmATC_VMID0_PASID_MAPPING 0xce7
#define mmATC_VMID1_PASID_MAPPING 0xce8
#define mmATC_VMID2_PASID_MAPPING 0xce9
#define mmATC_VMID3_PASID_MAPPING 0xcea
#define mmATC_VMID4_PASID_MAPPING 0xceb
#define mmATC_VMID5_PASID_MAPPING 0xcec
#define mmATC_VMID6_PASID_MAPPING 0xced
#define mmATC_VMID7_PASID_MAPPING 0xcee
#define mmATC_VMID8_PASID_MAPPING 0xcef
#define mmATC_VMID9_PASID_MAPPING 0xcf0
#define mmATC_VMID10_PASID_MAPPING 0xcf1
#define mmATC_VMID11_PASID_MAPPING 0xcf2
#define mmATC_VMID12_PASID_MAPPING 0xcf3
#define mmATC_VMID13_PASID_MAPPING 0xcf4
#define mmATC_VMID14_PASID_MAPPING 0xcf5
#define mmATC_VMID15_PASID_MAPPING 0xcf6
#define mmATC_ATS_VMID_STATUS 0xd07
#define mmATC_ATS_SMU_STATUS 0xd08
#define mmATC_L2_CNTL3 0xd09
#define mmATC_L2_STATUS 0xd0a
#define mmATC_L2_STATUS2 0xd0b
#define mmGMCON_RENG_RAM_INDEX 0xd40
#define mmGMCON_RENG_RAM_DATA 0xd41
#define mmGMCON_RENG_EXECUTE 0xd42
#define mmGMCON_MISC 0xd43
#define mmGMCON_MISC2 0xd44
#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE0 0xd45
#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE1 0xd46
#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE2 0xd47
#define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0 0xd48
#define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1 0xd49
#define mmGMCON_PERF_MON_CNTL0 0xd4a
#define mmGMCON_PERF_MON_CNTL1 0xd4b
#define mmGMCON_PERF_MON_RSLT0 0xd4c
#define mmGMCON_PERF_MON_RSLT1 0xd4d
#define mmGMCON_PGFSM_CONFIG 0xd4e
#define mmGMCON_PGFSM_WRITE 0xd4f
#define mmGMCON_PGFSM_READ 0xd50
#define mmGMCON_MISC3 0xd51
#define mmGMCON_MASK 0xd52
#define mmGMCON_LPT_TARGET 0xd53
#define mmGMCON_DEBUG 0xd5f
#define mmVM_L2_CNTL 0x500
#define mmVM_L2_CNTL2 0x501
#define mmVM_L2_CNTL3 0x502
#define mmVM_L2_STATUS 0x503
#define mmVM_CONTEXT0_CNTL 0x504
#define mmVM_CONTEXT1_CNTL 0x505
#define mmVM_DUMMY_PAGE_FAULT_CNTL 0x506
#define mmVM_DUMMY_PAGE_FAULT_ADDR 0x507
#define mmVM_CONTEXT0_CNTL2 0x50c
#define mmVM_CONTEXT1_CNTL2 0x50d
#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x50e
#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x50f
#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x510
#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x511
#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x512
#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x513
#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x514
#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x515
#define mmVM_INVALIDATE_REQUEST 0x51e
#define mmVM_INVALIDATE_RESPONSE 0x51f
#define mmVM_PRT_APERTURE0_LOW_ADDR 0x52c
#define mmVM_PRT_APERTURE1_LOW_ADDR 0x52d
#define mmVM_PRT_APERTURE2_LOW_ADDR 0x52e
#define mmVM_PRT_APERTURE3_LOW_ADDR 0x52f
#define mmVM_PRT_APERTURE0_HIGH_ADDR 0x530
#define mmVM_PRT_APERTURE1_HIGH_ADDR 0x531
#define mmVM_PRT_APERTURE2_HIGH_ADDR 0x532
#define mmVM_PRT_APERTURE3_HIGH_ADDR 0x533
#define mmVM_PRT_CNTL 0x534
#define mmVM_CONTEXTS_DISABLE 0x535
#define mmVM_CONTEXT0_PROTECTION_FAULT_STATUS 0x536
#define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS 0x537
#define mmVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT 0x538
#define mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT 0x539
#define mmVM_CONTEXT0_PROTECTION_FAULT_ADDR 0x53e
#define mmVM_CONTEXT1_PROTECTION_FAULT_ADDR 0x53f
#define mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x546
#define mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x547
#define mmVM_FAULT_CLIENT_ID 0x54e
#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x54f
#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x550
#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x551
#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x552
#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x553
#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x554
#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x555
#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x556
#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR 0x557
#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR 0x558
#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR 0x55f
#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR 0x560
#define mmVM_DEBUG 0x56f
#define mmVM_L2_CG 0x570
#define mmVM_L2_BANK_SELECT_MASKA 0x572
#define mmVM_L2_BANK_SELECT_MASKB 0x573
#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR 0x575
#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR 0x576
#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET 0x577
#define mmVM_L2_CNTL4 0x578
#define mmVM_L2_BANK_SELECT_RESERVED_CID 0x579
#define mmVM_L2_BANK_SELECT_RESERVED_CID2 0x57a
#define mmMC_VM_FB_SIZE_OFFSET_VF0 0xf980
#define mmMC_VM_FB_SIZE_OFFSET_VF1 0xf981
#define mmMC_VM_FB_SIZE_OFFSET_VF2 0xf982
#define mmMC_VM_FB_SIZE_OFFSET_VF3 0xf983
#define mmMC_VM_FB_SIZE_OFFSET_VF4 0xf984
#define mmMC_VM_FB_SIZE_OFFSET_VF5 0xf985
#define mmMC_VM_FB_SIZE_OFFSET_VF6 0xf986
#define mmMC_VM_FB_SIZE_OFFSET_VF7 0xf987
#define mmMC_VM_FB_SIZE_OFFSET_VF8 0xf988
#define mmMC_VM_FB_SIZE_OFFSET_VF9 0xf989
#define mmMC_VM_FB_SIZE_OFFSET_VF10 0xf98a
#define mmMC_VM_FB_SIZE_OFFSET_VF11 0xf98b
#define mmMC_VM_FB_SIZE_OFFSET_VF12 0xf98c
#define mmMC_VM_FB_SIZE_OFFSET_VF13 0xf98d
#define mmMC_VM_FB_SIZE_OFFSET_VF14 0xf98e
#define mmMC_VM_FB_SIZE_OFFSET_VF15 0xf98f
#define mmMC_VM_NB_MMIOBASE 0xf990
#define mmMC_VM_NB_MMIOLIMIT 0xf991
#define mmMC_VM_NB_PCI_CTRL 0xf992
#define mmMC_VM_NB_PCI_ARB 0xf993
#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1 0xf994
#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2 0xf995
#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2 0xf996
#define mmMC_VM_NB_TOP_OF_DRAM3 0xf997
#define mmMC_VM_MARC_BASE_LO_0 0xf998
#define mmMC_VM_MARC_BASE_LO_1 0xf99e
#define mmMC_VM_MARC_BASE_LO_2 0xf9a4
#define mmMC_VM_MARC_BASE_LO_3 0xf9aa
#define mmMC_VM_MARC_BASE_HI_0 0xf999
#define mmMC_VM_MARC_BASE_HI_1 0xf99f
#define mmMC_VM_MARC_BASE_HI_2 0xf9a5
#define mmMC_VM_MARC_BASE_HI_3 0xf9ab
#define mmMC_VM_MARC_RELOC_LO_0 0xf99a
#define mmMC_VM_MARC_RELOC_LO_1 0xf9a0
#define mmMC_VM_MARC_RELOC_LO_2 0xf9a6
#define mmMC_VM_MARC_RELOC_LO_3 0xf9ac
#define mmMC_VM_MARC_RELOC_HI_0 0xf99b
#define mmMC_VM_MARC_RELOC_HI_1 0xf9a1
#define mmMC_VM_MARC_RELOC_HI_2 0xf9a7
#define mmMC_VM_MARC_RELOC_HI_3 0xf9ad
#define mmMC_VM_MARC_LEN_LO_0 0xf99c
#define mmMC_VM_MARC_LEN_LO_1 0xf9a2
#define mmMC_VM_MARC_LEN_LO_2 0xf9a8
#define mmMC_VM_MARC_LEN_LO_3 0xf9ae
#define mmMC_VM_MARC_LEN_HI_0 0xf99d
#define mmMC_VM_MARC_LEN_HI_1 0xf9a3
#define mmMC_VM_MARC_LEN_HI_2 0xf9a9
#define mmMC_VM_MARC_LEN_HI_3 0xf9af
#define mmMC_VM_MARC_CNTL 0xf9b0
#define mmMC_VM_MB_L1_TLS0_CNTL0 0xf9b1
#define mmMC_VM_MB_L1_TLS0_CNTL1 0xf9b4
#define mmMC_VM_MB_L1_TLS0_CNTL2 0xf9b7
#define mmMC_VM_MB_L1_TLS0_CNTL3 0xf9ba
#define mmMC_VM_MB_L1_TLS0_CNTL4 0xf9bd
#define mmMC_VM_MB_L1_TLS0_CNTL5 0xf9c0
#define mmMC_VM_MB_L1_TLS0_CNTL6 0xf9c3
#define mmMC_VM_MB_L1_TLS0_CNTL7 0xf9c6
#define mmMC_VM_MB_L1_TLS0_CNTL8 0xf9c9
#define mmMC_VM_MB_L1_TLS0_START_ADDR0 0xf9b2
#define mmMC_VM_MB_L1_TLS0_START_ADDR1 0xf9b5
#define mmMC_VM_MB_L1_TLS0_START_ADDR2 0xf9b8
#define mmMC_VM_MB_L1_TLS0_START_ADDR3 0xf9bb
#define mmMC_VM_MB_L1_TLS0_START_ADDR4 0xf9be
#define mmMC_VM_MB_L1_TLS0_START_ADDR5 0xf9c1
#define mmMC_VM_MB_L1_TLS0_START_ADDR6 0xf9c4
#define mmMC_VM_MB_L1_TLS0_START_ADDR7 0xf9c7
#define mmMC_VM_MB_L1_TLS0_START_ADDR8 0xf9ca
#define mmMC_VM_MB_L1_TLS0_END_ADDR0 0xf9b3
#define mmMC_VM_MB_L1_TLS0_END_ADDR1 0xf9b6
#define mmMC_VM_MB_L1_TLS0_END_ADDR2 0xf9b9
#define mmMC_VM_MB_L1_TLS0_END_ADDR3 0xf9bc
#define mmMC_VM_MB_L1_TLS0_END_ADDR4 0xf9bf
#define mmMC_VM_MB_L1_TLS0_END_ADDR5 0xf9c2
#define mmMC_VM_MB_L1_TLS0_END_ADDR6 0xf9c5
#define mmMC_VM_MB_L1_TLS0_END_ADDR7 0xf9c8
#define mmMC_VM_MB_L1_TLS0_END_ADDR8 0xf9cb
#define mmMC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS 0xf9cc
#define mmMC_VM_MB_L1_TLS0_PROTECTION_FAULT_ADDR 0xf9cd
#define mmMC_SEQ_CNTL 0xa25
#define mmMC_SEQ_CNTL_2 0xad4
#define mmMC_SEQ_DRAM 0xa26
#define mmMC_SEQ_DRAM_2 0xa27
#define mmMC_SEQ_RAS_TIMING 0xa28
#define mmMC_SEQ_CAS_TIMING 0xa29
#define mmMC_SEQ_MISC_TIMING 0xa2a
#define mmMC_SEQ_MISC_TIMING2 0xa2b
#define mmMC_SEQ_PMG_TIMING 0xa2c
#define mmMC_SEQ_RD_CTL_D0 0xa2d
#define mmMC_SEQ_RD_CTL_D1 0xa2e
#define mmMC_SEQ_WR_CTL_D0 0xa2f
#define mmMC_SEQ_WR_CTL_D1 0xa30
#define mmMC_SEQ_WR_CTL_2 0xad5
#define mmMC_SEQ_CMD 0xa31
#define mmMC_PMG_CMD_EMRS 0xa83
#define mmMC_PMG_CMD_MRS 0xaab
#define mmMC_PMG_CMD_MRS1 0xad1
#define mmMC_PMG_CMD_MRS2 0xad7
#define mmMC_PMG_CFG 0xa84
#define mmMC_PMG_AUTO_CMD 0xa34
#define mmMC_PMG_AUTO_CFG 0xa35
#define mmMC_IMP_CNTL 0xa36
#define mmMC_IMP_DEBUG 0xa37
#define mmMC_IMP_STATUS 0xa38
#define mmMC_IMP_DQ_STATUS 0xabc
#define mmMC_SEQ_WCDR_CTRL 0xa39
#define mmMC_SEQ_TRAIN_WAKEUP_CNTL 0xa3a
#define mmMC_SEQ_TRAIN_EDC_THRESHOLD 0xa3b
#define mmMC_SEQ_TRAIN_EDC_THRESHOLD2 0xafe
#define mmMC_SEQ_TRAIN_EDC_THRESHOLD3 0xaff
#define mmMC_SEQ_TRAIN_WAKEUP_EDGE 0xa3c
#define mmMC_SEQ_TRAIN_WAKEUP_MASK 0xa3d
#define mmMC_SEQ_TRAIN_CAPTURE 0xa3e
#define mmMC_SEQ_TRAIN_WAKEUP_CLEAR 0xa3f
#define mmMC_SEQ_TRAIN_TIMING 0xa40
#define mmMC_TRAIN_EDCCDR_R_D0 0xa41
#define mmMC_TRAIN_EDCCDR_R_D1 0xa42
#define mmMC_TRAIN_PRBSERR_0_D0 0xa43
#define mmMC_TRAIN_PRBSERR_1_D0 0xa44
#define mmMC_TRAIN_PRBSERR_2_D0 0xafb
#define mmMC_TRAIN_EDC_STATUS_D0 0xa45
#define mmMC_TRAIN_PRBSERR_0_D1 0xa46
#define mmMC_TRAIN_PRBSERR_1_D1 0xa47
#define mmMC_TRAIN_PRBSERR_2_D1 0xafc
#define mmMC_TRAIN_EDC_STATUS_D1 0xa48
#define mmMC_IO_TXCNTL_DPHY0_D0 0xa49
#define mmMC_IO_TXCNTL_DPHY1_D0 0xa4a
#define mmMC_IO_TXCNTL_APHY_D0 0xa4b
#define mmMC_IO_RXCNTL_DPHY0_D0 0xa4c
#define mmMC_IO_RXCNTL1_DPHY0_D0 0xadf
#define mmMC_IO_RXCNTL_DPHY1_D0 0xa4d
#define mmMC_IO_RXCNTL1_DPHY1_D0 0xae0
#define mmMC_IO_DPHY_STR_CNTL_D0 0xa4e
#define mmMC_IO_APHY_STR_CNTL_D0 0xa97
#define mmMC_IO_TXCNTL_DPHY0_D1 0xa4f
#define mmMC_IO_TXCNTL_DPHY1_D1 0xa50
#define mmMC_IO_TXCNTL_APHY_D1 0xa51
#define mmMC_IO_RXCNTL_DPHY0_D1 0xa52
#define mmMC_IO_RXCNTL1_DPHY0_D1 0xae1
#define mmMC_IO_RXCNTL_DPHY1_D1 0xa53
#define mmMC_IO_RXCNTL1_DPHY1_D1 0xae2
#define mmMC_IO_DPHY_STR_CNTL_D1 0xa54
#define mmMC_IO_APHY_STR_CNTL_D1 0xa98
#define mmMC_IO_CDRCNTL_D0 0xa55
#define mmMC_IO_CDRCNTL1_D0 0xadd
#define mmMC_IO_CDRCNTL2_D0 0xae4
#define mmMC_IO_CDRCNTL_D1 0xa56
#define mmMC_IO_CDRCNTL1_D1 0xade
#define mmMC_IO_CDRCNTL2_D1 0xae5
#define mmMC_SEQ_FIFO_CTL 0xa57
#define mmMC_SEQ_TXFRAMING_BYTE0_D0 0xa58
#define mmMC_SEQ_TXFRAMING_BYTE1_D0 0xa59
#define mmMC_SEQ_TXFRAMING_BYTE2_D0 0xa5a
#define mmMC_SEQ_TXFRAMING_BYTE3_D0 0xa5b
#define mmMC_SEQ_TXFRAMING_DBI_D0 0xa5c
#define mmMC_SEQ_TXFRAMING_EDC_D0 0xa5d
#define mmMC_SEQ_TXFRAMING_FCK_D0 0xa5e
#define mmMC_SEQ_TXFRAMING_BYTE0_D1 0xa60
#define mmMC_SEQ_TXFRAMING_BYTE1_D1 0xa61
#define mmMC_SEQ_TXFRAMING_BYTE2_D1 0xa62
#define mmMC_SEQ_TXFRAMING_BYTE3_D1 0xa63
#define mmMC_SEQ_TXFRAMING_DBI_D1 0xa64
#define mmMC_SEQ_TXFRAMING_EDC_D1 0xa65
#define mmMC_SEQ_TXFRAMING_FCK_D1 0xa66
#define mmMC_SEQ_RXFRAMING_BYTE0_D0 0xa67
#define mmMC_SEQ_RXFRAMING_BYTE1_D0 0xa68
#define mmMC_SEQ_RXFRAMING_BYTE2_D0 0xa69
#define mmMC_SEQ_RXFRAMING_BYTE3_D0 0xa6a
#define mmMC_SEQ_RXFRAMING_DBI_D0 0xa6b
#define mmMC_SEQ_RXFRAMING_EDC_D0 0xa6c
#define mmMC_SEQ_RXFRAMING_BYTE0_D1 0xa6d
#define mmMC_SEQ_RXFRAMING_BYTE1_D1 0xa6e
#define mmMC_SEQ_RXFRAMING_BYTE2_D1 0xa6f
#define mmMC_SEQ_RXFRAMING_BYTE3_D1 0xa70
#define mmMC_SEQ_RXFRAMING_DBI_D1 0xa71
#define mmMC_SEQ_RXFRAMING_EDC_D1 0xa72
#define mmMC_IO_PAD_CNTL 0xa73
#define mmMC_IO_PAD_CNTL_D0 0xa74
#define mmMC_IO_PAD_CNTL_D1 0xa75
#define mmMC_NPL_STATUS 0xa76
#define mmMC_BIST_CMD_CNTL 0xa8e
#define mmMC_BIST_CNTL 0xa05
#define mmMC_BIST_AUTO_CNTL 0xa06
#define mmMC_BIST_DIR_CNTL 0xa07
#define mmMC_BIST_SADDR 0xa08
#define mmMC_BIST_EADDR 0xa09
#define mmMC_BIST_CMP_CNTL 0xa8d
#define mmMC_BIST_CMP_CNTL_2 0xab6
#define mmMC_BIST_DATA_WORD0 0xa0a
#define mmMC_BIST_DATA_WORD1 0xa0b
#define mmMC_BIST_DATA_WORD2 0xa0c
#define mmMC_BIST_DATA_WORD3 0xa0d
#define mmMC_BIST_DATA_WORD4 0xa0e
#define mmMC_BIST_DATA_WORD5 0xa0f
#define mmMC_BIST_DATA_WORD6 0xa10
#define mmMC_BIST_DATA_WORD7 0xa11
#define mmMC_BIST_DATA_MASK 0xa12
#define mmMC_BIST_MISMATCH_ADDR 0xa13
#define mmMC_BIST_RDATA_WORD0 0xa14
#define mmMC_BIST_RDATA_WORD1 0xa15
#define mmMC_BIST_RDATA_WORD2 0xa16
#define mmMC_BIST_RDATA_WORD3 0xa17
#define mmMC_BIST_RDATA_WORD4 0xa18
#define mmMC_BIST_RDATA_WORD5 0xa19
#define mmMC_BIST_RDATA_WORD6 0xa1a
#define mmMC_BIST_RDATA_WORD7 0xa1b
#define mmMC_BIST_RDATA_MASK 0xa1c
#define mmMC_BIST_RDATA_EDC 0xa1d
#define mmMC_SEQ_PERF_CNTL 0xa77
#define mmMC_SEQ_PERF_CNTL_1 0xafd
#define mmMC_SEQ_PERF_SEQ_CTL 0xa78
#define mmMC_SEQ_PERF_SEQ_CNT_A_I0 0xa79
#define mmMC_SEQ_PERF_SEQ_CNT_A_I1 0xa7a
#define mmMC_SEQ_PERF_SEQ_CNT_B_I0 0xa7b
#define mmMC_SEQ_PERF_SEQ_CNT_B_I1 0xa7c
#define mmMC_SEQ_PERF_SEQ_CNT_C_I0 0xad9
#define mmMC_SEQ_PERF_SEQ_CNT_C_I1 0xada
#define mmMC_SEQ_PERF_SEQ_CNT_D_I0 0xadb
#define mmMC_SEQ_PERF_SEQ_CNT_D_I1 0xadc
#define mmMC_SEQ_STATUS_M 0xa7d
#define mmMC_SEQ_STATUS_S 0xa20
#define mmMC_CG_DATAPORT 0xa21
#define mmMC_SEQ_VENDOR_ID_I0 0xa7e
#define mmMC_SEQ_VENDOR_ID_I1 0xa7f
#define mmMC_SEQ_MISC0 0xa80
#define mmMC_SEQ_MISC1 0xa81
#define mmMC_SEQ_RESERVE_0_S 0xa1e
#define mmMC_SEQ_RESERVE_1_S 0xa1f
#define mmMC_SEQ_RESERVE_M 0xa82
#define mmMC_SEQ_IO_RESERVE_D0 0xab7
#define mmMC_SEQ_IO_RESERVE_D1 0xab8
#define mmMC_SEQ_SUP_CNTL 0xa32
#define mmMC_SEQ_SUP_PGM 0xa33
#define mmMC_SEQ_SUP_GP0_STAT 0xa8f
#define mmMC_SEQ_SUP_GP1_STAT 0xa90
#define mmMC_SEQ_SUP_GP2_STAT 0xa85
#define mmMC_SEQ_SUP_GP3_STAT 0xa86
#define mmMC_SEQ_SUP_IR_STAT 0xa87
#define mmMC_SEQ_SUP_DEC_STAT 0xa88
#define mmMC_SEQ_SUP_PGM_STAT 0xa89
#define mmMC_SEQ_SUP_R_PGM 0xa8a
#define mmMC_SEQ_MISC3 0xa8b
#define mmMC_SEQ_MISC4 0xa8c
#define mmMC_SEQ_MISC5 0xa95
#define mmMC_SEQ_MISC6 0xa96
#define mmMC_SEQ_MISC7 0xa99
#define mmMC_SEQ_MISC8 0xa5f
#define mmMC_SEQ_MISC9 0xae7
#define mmMC_SEQ_CG 0xa9a
#define mmMC_SEQ_BYTE_REMAP_D0 0xa93
#define mmMC_SEQ_BYTE_REMAP_D1 0xa94
#define mmMC_SEQ_BIT_REMAP_B0_D0 0xaa3
#define mmMC_SEQ_BIT_REMAP_B1_D0 0xaa4
#define mmMC_SEQ_BIT_REMAP_B2_D0 0xaa5
#define mmMC_SEQ_BIT_REMAP_B3_D0 0xaa6
#define mmMC_SEQ_BIT_REMAP_B0_D1 0xaa7
#define mmMC_SEQ_BIT_REMAP_B1_D1 0xaa8
#define mmMC_SEQ_BIT_REMAP_B2_D1 0xaa9
#define mmMC_SEQ_BIT_REMAP_B3_D1 0xaaa
#define mmMC_SEQ_RAS_TIMING_LP 0xa9b
#define mmMC_SEQ_CAS_TIMING_LP 0xa9c
#define mmMC_SEQ_MISC_TIMING_LP 0xa9d
#define mmMC_SEQ_MISC_TIMING2_LP 0xa9e
#define mmMC_SEQ_RD_CTL_D0_LP 0xac7
#define mmMC_SEQ_RD_CTL_D1_LP 0xac8
#define mmMC_SEQ_WR_CTL_D0_LP 0xa9f
#define mmMC_SEQ_WR_CTL_D1_LP 0xaa0
#define mmMC_SEQ_WR_CTL_2_LP 0xad6
#define mmMC_SEQ_PMG_CMD_EMRS_LP 0xaa1
#define mmMC_SEQ_PMG_CMD_MRS_LP 0xaa2
#define mmMC_SEQ_PMG_CMD_MRS1_LP 0xad2
#define mmMC_SEQ_PMG_CMD_MRS2_LP 0xad8
#define mmMC_SEQ_PMG_TIMING_LP 0xad3
#define mmMC_SEQ_IO_RWORD0 0xaac
#define mmMC_SEQ_IO_RWORD1 0xaad
#define mmMC_SEQ_IO_RWORD2 0xaae
#define mmMC_SEQ_IO_RWORD3 0xaaf
#define mmMC_SEQ_IO_RWORD4 0xab0
#define mmMC_SEQ_IO_RWORD5 0xab1
#define mmMC_SEQ_IO_RWORD6 0xab2
#define mmMC_SEQ_IO_RWORD7 0xab3
#define mmMC_SEQ_IO_RDBI 0xab4
#define mmMC_SEQ_IO_REDC 0xab5
#define mmMC_SEQ_TCG_CNTL 0xabd
#define mmMC_SEQ_TSM_CTRL 0xabe
#define mmMC_SEQ_TSM_GCNT 0xabf
#define mmMC_SEQ_TSM_OCNT 0xac0
#define mmMC_SEQ_TSM_NCNT 0xac1
#define mmMC_SEQ_TSM_BCNT 0xac2
#define mmMC_SEQ_TSM_FLAG 0xac3
#define mmMC_SEQ_TSM_UPDATE 0xac4
#define mmMC_SEQ_TSM_EDC 0xac5
#define mmMC_SEQ_TSM_DBI 0xac6
#define mmMC_SEQ_TSM_WCDR 0xae3
#define mmMC_SEQ_TSM_MISC 0xae6
#define mmMC_SEQ_TIMER_WR 0xac9
#define mmMC_SEQ_TIMER_RD 0xaca
#define mmMC_SEQ_DRAM_ERROR_INSERTION 0xacb
#define mmMC_PHY_TIMING_D0 0xacc
#define mmMC_PHY_TIMING_D1 0xacd
#define mmMC_PHY_TIMING_2 0xace
#define mmMC_SEQ_MPLL_OVERRIDE 0xa22
#define mmMCLK_PWRMGT_CNTL 0xae8
#define mmDLL_CNTL 0xae9
#define mmMPLL_SEQ_UCODE_1 0xaea
#define mmMPLL_SEQ_UCODE_2 0xaeb
#define mmMPLL_CNTL_MODE 0xaec
#define mmMPLL_FUNC_CNTL 0xaed
#define mmMPLL_FUNC_CNTL_1 0xaee
#define mmMPLL_FUNC_CNTL_2 0xaef
#define mmMPLL_AD_FUNC_CNTL 0xaf0
#define mmMPLL_DQ_FUNC_CNTL 0xaf1
#define mmMPLL_TIME 0xaf2
#define mmMPLL_SS1 0xaf3
#define mmMPLL_SS2 0xaf4
#define mmMPLL_CONTROL 0xaf5
#define mmMPLL_AD_STATUS 0xaf6
#define mmMPLL_DQ_0_0_STATUS 0xaf7
#define mmMPLL_DQ_0_1_STATUS 0xaf8
#define mmMPLL_DQ_1_0_STATUS 0xaf9
#define mmMPLL_DQ_1_1_STATUS 0xafa
#define mmMC_SEQ_PMG_PG_HWCNTL 0xab9
#define mmMC_SEQ_PMG_PG_SWCNTL_0 0xaba
#define mmMC_SEQ_PMG_PG_SWCNTL_1 0xabb
#define mmMC_SEQ_TSM_DEBUG_INDEX 0xacf
#define mmMC_SEQ_TSM_DEBUG_DATA 0xad0
#define ixMC_TSM_DEBUG_GCNT 0x0
#define ixMC_TSM_DEBUG_FLAG 0x1
#define ixMC_TSM_DEBUG_MISC 0x2
#define ixMC_TSM_DEBUG_BCNT0 0x3
#define ixMC_TSM_DEBUG_BCNT1 0x4
#define ixMC_TSM_DEBUG_BCNT2 0x5
#define ixMC_TSM_DEBUG_BCNT3 0x6
#define ixMC_TSM_DEBUG_BCNT4 0x7
#define ixMC_TSM_DEBUG_BCNT5 0x8
#define ixMC_TSM_DEBUG_BCNT6 0x9
#define ixMC_TSM_DEBUG_BCNT7 0xa
#define ixMC_TSM_DEBUG_BCNT8 0xb
#define ixMC_TSM_DEBUG_BCNT9 0xc
#define ixMC_TSM_DEBUG_BCNT10 0xd
#define ixMC_TSM_DEBUG_ST01 0x10
#define ixMC_TSM_DEBUG_ST23 0x11
#define ixMC_TSM_DEBUG_ST45 0x12
#define ixMC_TSM_DEBUG_BKPT 0x13
#define mmMC_SEQ_IO_DEBUG_INDEX 0xa91
#define mmMC_SEQ_IO_DEBUG_DATA 0xa92
#define ixMC_IO_DEBUG_UP_0 0x0
#define ixMC_IO_DEBUG_UP_1 0x1
#define ixMC_IO_DEBUG_UP_2 0x2
#define ixMC_IO_DEBUG_UP_3 0x3
#define ixMC_IO_DEBUG_UP_4 0x4
#define ixMC_IO_DEBUG_UP_5 0x5
#define ixMC_IO_DEBUG_UP_6 0x6
#define ixMC_IO_DEBUG_UP_7 0x7
#define ixMC_IO_DEBUG_UP_8 0x8
#define ixMC_IO_DEBUG_UP_9 0x9
#define ixMC_IO_DEBUG_UP_10 0xa
#define ixMC_IO_DEBUG_UP_11 0xb
#define ixMC_IO_DEBUG_UP_12 0xc
#define ixMC_IO_DEBUG_UP_13 0xd
#define ixMC_IO_DEBUG_UP_14 0xe
#define ixMC_IO_DEBUG_UP_15 0xf
#define ixMC_IO_DEBUG_UP_16 0x10
#define ixMC_IO_DEBUG_UP_17 0x11
#define ixMC_IO_DEBUG_UP_18 0x12
#define ixMC_IO_DEBUG_UP_19 0x13
#define ixMC_IO_DEBUG_UP_20 0x14
#define ixMC_IO_DEBUG_UP_21 0x15
#define ixMC_IO_DEBUG_UP_22 0x16
#define ixMC_IO_DEBUG_UP_23 0x17
#define ixMC_IO_DEBUG_UP_24 0x18
#define ixMC_IO_DEBUG_UP_25 0x19
#define ixMC_IO_DEBUG_UP_26 0x1a
#define ixMC_IO_DEBUG_UP_27 0x1b
#define ixMC_IO_DEBUG_UP_28 0x1c
#define ixMC_IO_DEBUG_UP_29 0x1d
#define ixMC_IO_DEBUG_UP_30 0x1e
#define ixMC_IO_DEBUG_UP_31 0x1f
#define ixMC_IO_DEBUG_UP_32 0x20
#define ixMC_IO_DEBUG_UP_33 0x21
#define ixMC_IO_DEBUG_UP_34 0x22
#define ixMC_IO_DEBUG_UP_35 0x23
#define ixMC_IO_DEBUG_UP_36 0x24
#define ixMC_IO_DEBUG_UP_37 0x25
#define ixMC_IO_DEBUG_UP_38 0x26
#define ixMC_IO_DEBUG_UP_39 0x27
#define ixMC_IO_DEBUG_UP_40 0x28
#define ixMC_IO_DEBUG_UP_41 0x29
#define ixMC_IO_DEBUG_UP_42 0x2a
#define ixMC_IO_DEBUG_UP_43 0x2b
#define ixMC_IO_DEBUG_UP_44 0x2c
#define ixMC_IO_DEBUG_UP_45 0x2d
#define ixMC_IO_DEBUG_UP_46 0x2e
#define ixMC_IO_DEBUG_UP_47 0x2f
#define ixMC_IO_DEBUG_UP_48 0x30
#define ixMC_IO_DEBUG_UP_49 0x31
#define ixMC_IO_DEBUG_UP_50 0x32
#define ixMC_IO_DEBUG_UP_51 0x33
#define ixMC_IO_DEBUG_UP_52 0x34
#define ixMC_IO_DEBUG_UP_53 0x35
#define ixMC_IO_DEBUG_UP_54 0x36
#define ixMC_IO_DEBUG_UP_55 0x37
#define ixMC_IO_DEBUG_UP_56 0x38
#define ixMC_IO_DEBUG_UP_57 0x39
#define ixMC_IO_DEBUG_UP_58 0x3a
#define ixMC_IO_DEBUG_UP_59 0x3b
#define ixMC_IO_DEBUG_UP_60 0x3c
#define ixMC_IO_DEBUG_UP_61 0x3d
#define ixMC_IO_DEBUG_UP_62 0x3e
#define ixMC_IO_DEBUG_UP_63 0x3f
#define ixMC_IO_DEBUG_UP_64 0x40
#define ixMC_IO_DEBUG_UP_65 0x41
#define ixMC_IO_DEBUG_UP_66 0x42
#define ixMC_IO_DEBUG_UP_67 0x43
#define ixMC_IO_DEBUG_UP_68 0x44
#define ixMC_IO_DEBUG_UP_69 0x45
#define ixMC_IO_DEBUG_UP_70 0x46
#define ixMC_IO_DEBUG_UP_71 0x47
#define ixMC_IO_DEBUG_UP_72 0x48
#define ixMC_IO_DEBUG_UP_73 0x49
#define ixMC_IO_DEBUG_UP_74 0x4a
#define ixMC_IO_DEBUG_UP_75 0x4b
#define ixMC_IO_DEBUG_UP_76 0x4c
#define ixMC_IO_DEBUG_UP_77 0x4d
#define ixMC_IO_DEBUG_UP_78 0x4e
#define ixMC_IO_DEBUG_UP_79 0x4f
#define ixMC_IO_DEBUG_UP_80 0x50
#define ixMC_IO_DEBUG_UP_81 0x51
#define ixMC_IO_DEBUG_UP_82 0x52
#define ixMC_IO_DEBUG_UP_83 0x53
#define ixMC_IO_DEBUG_UP_84 0x54
#define ixMC_IO_DEBUG_UP_85 0x55
#define ixMC_IO_DEBUG_UP_86 0x56
#define ixMC_IO_DEBUG_UP_87 0x57
#define ixMC_IO_DEBUG_UP_88 0x58
#define ixMC_IO_DEBUG_UP_89 0x59
#define ixMC_IO_DEBUG_UP_90 0x5a
#define ixMC_IO_DEBUG_UP_91 0x5b
#define ixMC_IO_DEBUG_UP_92 0x5c
#define ixMC_IO_DEBUG_UP_93 0x5d
#define ixMC_IO_DEBUG_UP_94 0x5e
#define ixMC_IO_DEBUG_UP_95 0x5f
#define ixMC_IO_DEBUG_UP_96 0x60
#define ixMC_IO_DEBUG_UP_97 0x61
#define ixMC_IO_DEBUG_UP_98 0x62
#define ixMC_IO_DEBUG_UP_99 0x63
#define ixMC_IO_DEBUG_UP_100 0x64
#define ixMC_IO_DEBUG_UP_101 0x65
#define ixMC_IO_DEBUG_UP_102 0x66
#define ixMC_IO_DEBUG_UP_103 0x67
#define ixMC_IO_DEBUG_UP_104 0x68
#define ixMC_IO_DEBUG_UP_105 0x69
#define ixMC_IO_DEBUG_UP_106 0x6a
#define ixMC_IO_DEBUG_UP_107 0x6b
#define ixMC_IO_DEBUG_UP_108 0x6c
#define ixMC_IO_DEBUG_UP_109 0x6d
#define ixMC_IO_DEBUG_UP_110 0x6e
#define ixMC_IO_DEBUG_UP_111 0x6f
#define ixMC_IO_DEBUG_UP_112 0x70
#define ixMC_IO_DEBUG_UP_113 0x71
#define ixMC_IO_DEBUG_UP_114 0x72
#define ixMC_IO_DEBUG_UP_115 0x73
#define ixMC_IO_DEBUG_UP_116 0x74
#define ixMC_IO_DEBUG_UP_117 0x75
#define ixMC_IO_DEBUG_UP_118 0x76
#define ixMC_IO_DEBUG_UP_119 0x77
#define ixMC_IO_DEBUG_UP_120 0x78
#define ixMC_IO_DEBUG_UP_121 0x79
#define ixMC_IO_DEBUG_UP_122 0x7a
#define ixMC_IO_DEBUG_UP_123 0x7b
#define ixMC_IO_DEBUG_UP_124 0x7c
#define ixMC_IO_DEBUG_UP_125 0x7d
#define ixMC_IO_DEBUG_UP_126 0x7e
#define ixMC_IO_DEBUG_UP_127 0x7f
#define ixMC_IO_DEBUG_UP_128 0x80
#define ixMC_IO_DEBUG_UP_129 0x81
#define ixMC_IO_DEBUG_UP_130 0x82
#define ixMC_IO_DEBUG_UP_131 0x83
#define ixMC_IO_DEBUG_UP_132 0x84
#define ixMC_IO_DEBUG_UP_133 0x85
#define ixMC_IO_DEBUG_UP_134 0x86
#define ixMC_IO_DEBUG_UP_135 0x87
#define ixMC_IO_DEBUG_UP_136 0x88
#define ixMC_IO_DEBUG_UP_137 0x89
#define ixMC_IO_DEBUG_UP_138 0x8a
#define ixMC_IO_DEBUG_UP_139 0x8b
#define ixMC_IO_DEBUG_UP_140 0x8c
#define ixMC_IO_DEBUG_UP_141 0x8d
#define ixMC_IO_DEBUG_UP_142 0x8e
#define ixMC_IO_DEBUG_UP_143 0x8f
#define ixMC_IO_DEBUG_UP_144 0x90
#define ixMC_IO_DEBUG_UP_145 0x91
#define ixMC_IO_DEBUG_UP_146 0x92
#define ixMC_IO_DEBUG_UP_147 0x93
#define ixMC_IO_DEBUG_UP_148 0x94
#define ixMC_IO_DEBUG_UP_149 0x95
#define ixMC_IO_DEBUG_UP_150 0x96
#define ixMC_IO_DEBUG_UP_151 0x97
#define ixMC_IO_DEBUG_UP_152 0x98
#define ixMC_IO_DEBUG_UP_153 0x99
#define ixMC_IO_DEBUG_UP_154 0x9a
#define ixMC_IO_DEBUG_UP_155 0x9b
#define ixMC_IO_DEBUG_UP_156 0x9c
#define ixMC_IO_DEBUG_UP_157 0x9d
#define ixMC_IO_DEBUG_UP_158 0x9e
#define ixMC_IO_DEBUG_UP_159 0x9f
#define ixMC_IO_DEBUG_DQB0L_MISC_D0 0xa0
#define ixMC_IO_DEBUG_DQB0H_MISC_D0 0xa1
#define ixMC_IO_DEBUG_DQB1L_MISC_D0 0xa2
#define ixMC_IO_DEBUG_DQB1H_MISC_D0 0xa3
#define ixMC_IO_DEBUG_DQB2L_MISC_D0 0xa4
#define ixMC_IO_DEBUG_DQB2H_MISC_D0 0xa5
#define ixMC_IO_DEBUG_DQB3L_MISC_D0 0xa6
#define ixMC_IO_DEBUG_DQB3H_MISC_D0 0xa7
#define ixMC_IO_DEBUG_DBI_MISC_D0 0xa8
#define ixMC_IO_DEBUG_EDC_MISC_D0 0xa9
#define ixMC_IO_DEBUG_WCK_MISC_D0 0xaa
#define ixMC_IO_DEBUG_CK_MISC_D0 0xab
#define ixMC_IO_DEBUG_ADDRL_MISC_D0 0xac
#define ixMC_IO_DEBUG_ADDRH_MISC_D0 0xad
#define ixMC_IO_DEBUG_ACMD_MISC_D0 0xae
#define ixMC_IO_DEBUG_CMD_MISC_D0 0xaf
#define ixMC_IO_DEBUG_DQB0L_MISC_D1 0xb0
#define ixMC_IO_DEBUG_DQB0H_MISC_D1 0xb1
#define ixMC_IO_DEBUG_DQB1L_MISC_D1 0xb2
#define ixMC_IO_DEBUG_DQB1H_MISC_D1 0xb3
#define ixMC_IO_DEBUG_DQB2L_MISC_D1 0xb4
#define ixMC_IO_DEBUG_DQB2H_MISC_D1 0xb5
#define ixMC_IO_DEBUG_DQB3L_MISC_D1 0xb6
#define ixMC_IO_DEBUG_DQB3H_MISC_D1 0xb7
#define ixMC_IO_DEBUG_DBI_MISC_D1 0xb8
#define ixMC_IO_DEBUG_EDC_MISC_D1 0xb9
#define ixMC_IO_DEBUG_WCK_MISC_D1 0xba
#define ixMC_IO_DEBUG_CK_MISC_D1 0xbb
#define ixMC_IO_DEBUG_ADDRL_MISC_D1 0xbc
#define ixMC_IO_DEBUG_ADDRH_MISC_D1 0xbd
#define ixMC_IO_DEBUG_ACMD_MISC_D1 0xbe
#define ixMC_IO_DEBUG_CMD_MISC_D1 0xbf
#define ixMC_IO_DEBUG_DQB0L_CLKSEL_D0 0xc0
#define ixMC_IO_DEBUG_DQB0H_CLKSEL_D0 0xc1
#define ixMC_IO_DEBUG_DQB1L_CLKSEL_D0 0xc2
#define ixMC_IO_DEBUG_DQB1H_CLKSEL_D0 0xc3
#define ixMC_IO_DEBUG_DQB2L_CLKSEL_D0 0xc4
#define ixMC_IO_DEBUG_DQB2H_CLKSEL_D0 0xc5
#define ixMC_IO_DEBUG_DQB3L_CLKSEL_D0 0xc6
#define ixMC_IO_DEBUG_DQB3H_CLKSEL_D0 0xc7
#define ixMC_IO_DEBUG_DBI_CLKSEL_D0 0xc8
#define ixMC_IO_DEBUG_EDC_CLKSEL_D0 0xc9
#define ixMC_IO_DEBUG_WCK_CLKSEL_D0 0xca
#define ixMC_IO_DEBUG_CK_CLKSEL_D0 0xcb
#define ixMC_IO_DEBUG_ADDRL_CLKSEL_D0 0xcc
#define ixMC_IO_DEBUG_ADDRH_CLKSEL_D0 0xcd
#define ixMC_IO_DEBUG_ACMD_CLKSEL_D0 0xce
#define ixMC_IO_DEBUG_CMD_CLKSEL_D0 0xcf
#define ixMC_IO_DEBUG_DQB0L_CLKSEL_D1 0xd0
#define ixMC_IO_DEBUG_DQB0H_CLKSEL_D1 0xd1
#define ixMC_IO_DEBUG_DQB1L_CLKSEL_D1 0xd2
#define ixMC_IO_DEBUG_DQB1H_CLKSEL_D1 0xd3
#define ixMC_IO_DEBUG_DQB2L_CLKSEL_D1 0xd4
#define ixMC_IO_DEBUG_DQB2H_CLKSEL_D1 0xd5
#define ixMC_IO_DEBUG_DQB3L_CLKSEL_D1 0xd6
#define ixMC_IO_DEBUG_DQB3H_CLKSEL_D1 0xd7
#define ixMC_IO_DEBUG_DBI_CLKSEL_D1 0xd8
#define ixMC_IO_DEBUG_EDC_CLKSEL_D1 0xd9
#define ixMC_IO_DEBUG_WCK_CLKSEL_D1 0xda
#define ixMC_IO_DEBUG_CK_CLKSEL_D1 0xdb
#define ixMC_IO_DEBUG_ADDRL_CLKSEL_D1 0xdc
#define ixMC_IO_DEBUG_ADDRH_CLKSEL_D1 0xdd
#define ixMC_IO_DEBUG_ACMD_CLKSEL_D1 0xde
#define ixMC_IO_DEBUG_CMD_CLKSEL_D1 0xdf
#define ixMC_IO_DEBUG_DQB0L_OFSCAL_D0 0xe0
#define ixMC_IO_DEBUG_DQB0H_OFSCAL_D0 0xe1
#define ixMC_IO_DEBUG_DQB1L_OFSCAL_D0 0xe2
#define ixMC_IO_DEBUG_DQB1H_OFSCAL_D0 0xe3
#define ixMC_IO_DEBUG_DQB2L_OFSCAL_D0 0xe4
#define ixMC_IO_DEBUG_DQB2H_OFSCAL_D0 0xe5
#define ixMC_IO_DEBUG_DQB3L_OFSCAL_D0 0xe6
#define ixMC_IO_DEBUG_DQB3H_OFSCAL_D0 0xe7
#define ixMC_IO_DEBUG_DBI_OFSCAL_D0 0xe8
#define ixMC_IO_DEBUG_EDC_OFSCAL_D0 0xe9
#define ixMC_IO_DEBUG_WCK_OFSCAL_D0 0xea
#define ixMC_IO_DEBUG_EDC_RX_EQ_PM_D0 0xeb
#define ixMC_IO_DEBUG_EDC_RX_DYN_PM_D0 0xec
#define ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D0 0xed
#define ixMC_IO_DEBUG_ACMD_OFSCAL_D0 0xee
#define ixMC_IO_DEBUG_CMD_OFSCAL_D0 0xef
#define ixMC_IO_DEBUG_DQB0L_OFSCAL_D1 0xf0
#define ixMC_IO_DEBUG_DQB0H_OFSCAL_D1 0xf1
#define ixMC_IO_DEBUG_DQB1L_OFSCAL_D1 0xf2
#define ixMC_IO_DEBUG_DQB1H_OFSCAL_D1 0xf3
#define ixMC_IO_DEBUG_DQB2L_OFSCAL_D1 0xf4
#define ixMC_IO_DEBUG_DQB2H_OFSCAL_D1 0xf5
#define ixMC_IO_DEBUG_DQB3L_OFSCAL_D1 0xf6
#define ixMC_IO_DEBUG_DQB3H_OFSCAL_D1 0xf7
#define ixMC_IO_DEBUG_DBI_OFSCAL_D1 0xf8
#define ixMC_IO_DEBUG_EDC_OFSCAL_D1 0xf9
#define ixMC_IO_DEBUG_WCK_OFSCAL_D1 0xfa
#define ixMC_IO_DEBUG_EDC_RX_EQ_PM_D1 0xfb
#define ixMC_IO_DEBUG_EDC_RX_DYN_PM_D1 0xfc
#define ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D1 0xfd
#define ixMC_IO_DEBUG_ACMD_OFSCAL_D1 0xfe
#define ixMC_IO_DEBUG_CMD_OFSCAL_D1 0xff
#define ixMC_IO_DEBUG_DQB0L_RXPHASE_D0 0x100
#define ixMC_IO_DEBUG_DQB0H_RXPHASE_D0 0x101
#define ixMC_IO_DEBUG_DQB1L_RXPHASE_D0 0x102
#define ixMC_IO_DEBUG_DQB1H_RXPHASE_D0 0x103
#define ixMC_IO_DEBUG_DQB2L_RXPHASE_D0 0x104
#define ixMC_IO_DEBUG_DQB2H_RXPHASE_D0 0x105
#define ixMC_IO_DEBUG_DQB3L_RXPHASE_D0 0x106
#define ixMC_IO_DEBUG_DQB3H_RXPHASE_D0 0x107
#define ixMC_IO_DEBUG_DBI_RXPHASE_D0 0x108
#define ixMC_IO_DEBUG_EDC_RXPHASE_D0 0x109
#define ixMC_IO_DEBUG_WCK_RXPHASE_D0 0x10a
#define ixMC_IO_DEBUG_CK_RXPHASE_D0 0x10b
#define ixMC_IO_DEBUG_ADDRL_RXPHASE_D0 0x10c
#define ixMC_IO_DEBUG_ADDRH_RXPHASE_D0 0x10d
#define ixMC_IO_DEBUG_ACMD_RXPHASE_D0 0x10e
#define ixMC_IO_DEBUG_CMD_RXPHASE_D0 0x10f
#define ixMC_IO_DEBUG_DQB0L_RXPHASE_D1 0x110
#define ixMC_IO_DEBUG_DQB0H_RXPHASE_D1 0x111
#define ixMC_IO_DEBUG_DQB1L_RXPHASE_D1 0x112
#define ixMC_IO_DEBUG_DQB1H_RXPHASE_D1 0x113
#define ixMC_IO_DEBUG_DQB2L_RXPHASE_D1 0x114
#define ixMC_IO_DEBUG_DQB2H_RXPHASE_D1 0x115
#define ixMC_IO_DEBUG_DQB3L_RXPHASE_D1 0x116
#define ixMC_IO_DEBUG_DQB3H_RXPHASE_D1 0x117
#define ixMC_IO_DEBUG_DBI_RXPHASE_D1 0x118
#define ixMC_IO_DEBUG_EDC_RXPHASE_D1 0x119
#define ixMC_IO_DEBUG_WCK_RXPHASE_D1 0x11a
#define ixMC_IO_DEBUG_CK_RXPHASE_D1 0x11b
#define ixMC_IO_DEBUG_ADDRL_RXPHASE_D1 0x11c
#define ixMC_IO_DEBUG_ADDRH_RXPHASE_D1 0x11d
#define ixMC_IO_DEBUG_ACMD_RXPHASE_D1 0x11e
#define ixMC_IO_DEBUG_CMD_RXPHASE_D1 0x11f
#define ixMC_IO_DEBUG_DQB0L_TXPHASE_D0 0x120
#define ixMC_IO_DEBUG_DQB0H_TXPHASE_D0 0x121
#define ixMC_IO_DEBUG_DQB1L_TXPHASE_D0 0x122
#define ixMC_IO_DEBUG_DQB1H_TXPHASE_D0 0x123
#define ixMC_IO_DEBUG_DQB2L_TXPHASE_D0 0x124
#define ixMC_IO_DEBUG_DQB2H_TXPHASE_D0 0x125
#define ixMC_IO_DEBUG_DQB3L_TXPHASE_D0 0x126
#define ixMC_IO_DEBUG_DQB3H_TXPHASE_D0 0x127
#define ixMC_IO_DEBUG_DBI_TXPHASE_D0 0x128
#define ixMC_IO_DEBUG_EDC_TXPHASE_D0 0x129
#define ixMC_IO_DEBUG_WCK_TXPHASE_D0 0x12a
#define ixMC_IO_DEBUG_CK_TXPHASE_D0 0x12b
#define ixMC_IO_DEBUG_ADDRL_TXPHASE_D0 0x12c
#define ixMC_IO_DEBUG_ADDRH_TXPHASE_D0 0x12d
#define ixMC_IO_DEBUG_ACMD_TXPHASE_D0 0x12e
#define ixMC_IO_DEBUG_CMD_TXPHASE_D0 0x12f
#define ixMC_IO_DEBUG_DQB0L_TXPHASE_D1 0x130
#define ixMC_IO_DEBUG_DQB0H_TXPHASE_D1 0x131
#define ixMC_IO_DEBUG_DQB1L_TXPHASE_D1 0x132
#define ixMC_IO_DEBUG_DQB1H_TXPHASE_D1 0x133
#define ixMC_IO_DEBUG_DQB2L_TXPHASE_D1 0x134
#define ixMC_IO_DEBUG_DQB2H_TXPHASE_D1 0x135
#define ixMC_IO_DEBUG_DQB3L_TXPHASE_D1 0x136
#define ixMC_IO_DEBUG_DQB3H_TXPHASE_D1 0x137
#define ixMC_IO_DEBUG_DBI_TXPHASE_D1 0x138
#define ixMC_IO_DEBUG_EDC_TXPHASE_D1 0x139
#define ixMC_IO_DEBUG_WCK_TXPHASE_D1 0x13a
#define ixMC_IO_DEBUG_CK_TXPHASE_D1 0x13b
#define ixMC_IO_DEBUG_ADDRL_TXPHASE_D1 0x13c
#define ixMC_IO_DEBUG_ADDRH_TXPHASE_D1 0x13d
#define ixMC_IO_DEBUG_ACMD_TXPHASE_D1 0x13e
#define ixMC_IO_DEBUG_CMD_TXPHASE_D1 0x13f
#define ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0 0x140
#define ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0 0x141
#define ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0 0x142
#define ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0 0x143
#define ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0 0x144
#define ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0 0x145
#define ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0 0x146
#define ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0 0x147
#define ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D0 0x148
#define ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D0 0x149
#define ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D0 0x14a
#define ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D0 0x14b
#define ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D0 0x14c
#define ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D0 0x14d
#define ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D0 0x14e
#define ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D0 0x14f
#define ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1 0x150
#define ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1 0x151
#define ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1 0x152
#define ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1 0x153
#define ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1 0x154
#define ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1 0x155
#define ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1 0x156
#define ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1 0x157
#define ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D1 0x158
#define ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D1 0x159
#define ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D1 0x15a
#define ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D1 0x15b
#define ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D1 0x15c
#define ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D1 0x15d
#define ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D1 0x15e
#define ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D1 0x15f
#define ixMC_IO_DEBUG_DQB0L_TXSLF_D0 0x160
#define ixMC_IO_DEBUG_DQB0H_TXSLF_D0 0x161
#define ixMC_IO_DEBUG_DQB1L_TXSLF_D0 0x162
#define ixMC_IO_DEBUG_DQB1H_TXSLF_D0 0x163
#define ixMC_IO_DEBUG_DQB2L_TXSLF_D0 0x164
#define ixMC_IO_DEBUG_DQB2H_TXSLF_D0 0x165
#define ixMC_IO_DEBUG_DQB3L_TXSLF_D0 0x166
#define ixMC_IO_DEBUG_DQB3H_TXSLF_D0 0x167
#define ixMC_IO_DEBUG_DBI_TXSLF_D0 0x168
#define ixMC_IO_DEBUG_EDC_TXSLF_D0 0x169
#define ixMC_IO_DEBUG_WCK_TXSLF_D0 0x16a
#define ixMC_IO_DEBUG_CK_TXSLF_D0 0x16b
#define ixMC_IO_DEBUG_ADDRL_TXSLF_D0 0x16c
#define ixMC_IO_DEBUG_ADDRH_TXSLF_D0 0x16d
#define ixMC_IO_DEBUG_ACMD_TXSLF_D0 0x16e
#define ixMC_IO_DEBUG_CMD_TXSLF_D0 0x16f
#define ixMC_IO_DEBUG_DQB0L_TXSLF_D1 0x170
#define ixMC_IO_DEBUG_DQB0H_TXSLF_D1 0x171
#define ixMC_IO_DEBUG_DQB1L_TXSLF_D1 0x172
#define ixMC_IO_DEBUG_DQB1H_TXSLF_D1 0x173
#define ixMC_IO_DEBUG_DQB2L_TXSLF_D1 0x174
#define ixMC_IO_DEBUG_DQB2H_TXSLF_D1 0x175
#define ixMC_IO_DEBUG_DQB3L_TXSLF_D1 0x176
#define ixMC_IO_DEBUG_DQB3H_TXSLF_D1 0x177
#define ixMC_IO_DEBUG_DBI_TXSLF_D1 0x178
#define ixMC_IO_DEBUG_EDC_TXSLF_D1 0x179
#define ixMC_IO_DEBUG_WCK_TXSLF_D1 0x17a
#define ixMC_IO_DEBUG_CK_TXSLF_D1 0x17b
#define ixMC_IO_DEBUG_ADDRL_TXSLF_D1 0x17c
#define ixMC_IO_DEBUG_ADDRH_TXSLF_D1 0x17d
#define ixMC_IO_DEBUG_ACMD_TXSLF_D1 0x17e
#define ixMC_IO_DEBUG_CMD_TXSLF_D1 0x17f
#define ixMC_IO_DEBUG_DQB0L_TXBST_PD_D0 0x180
#define ixMC_IO_DEBUG_DQB0H_TXBST_PD_D0 0x181
#define ixMC_IO_DEBUG_DQB1L_TXBST_PD_D0 0x182
#define ixMC_IO_DEBUG_DQB1H_TXBST_PD_D0 0x183
#define ixMC_IO_DEBUG_DQB2L_TXBST_PD_D0 0x184
#define ixMC_IO_DEBUG_DQB2H_TXBST_PD_D0 0x185
#define ixMC_IO_DEBUG_DQB3L_TXBST_PD_D0 0x186
#define ixMC_IO_DEBUG_DQB3H_TXBST_PD_D0 0x187
#define ixMC_IO_DEBUG_DBI_TXBST_PD_D0 0x188
#define ixMC_IO_DEBUG_EDC_TXBST_PD_D0 0x189
#define ixMC_IO_DEBUG_WCK_TXBST_PD_D0 0x18a
#define ixMC_IO_DEBUG_CK_TXBST_PD_D0 0x18b
#define ixMC_IO_DEBUG_ADDRL_TXBST_PD_D0 0x18c
#define ixMC_IO_DEBUG_ADDRH_TXBST_PD_D0 0x18d
#define ixMC_IO_DEBUG_ACMD_TXBST_PD_D0 0x18e
#define ixMC_IO_DEBUG_CMD_TXBST_PD_D0 0x18f
#define ixMC_IO_DEBUG_DQB0L_TXBST_PD_D1 0x190
#define ixMC_IO_DEBUG_DQB0H_TXBST_PD_D1 0x191
#define ixMC_IO_DEBUG_DQB1L_TXBST_PD_D1 0x192
#define ixMC_IO_DEBUG_DQB1H_TXBST_PD_D1 0x193
#define ixMC_IO_DEBUG_DQB2L_TXBST_PD_D1 0x194
#define ixMC_IO_DEBUG_DQB2H_TXBST_PD_D1 0x195
#define ixMC_IO_DEBUG_DQB3L_TXBST_PD_D1 0x196
#define ixMC_IO_DEBUG_DQB3H_TXBST_PD_D1 0x197
#define ixMC_IO_DEBUG_DBI_TXBST_PD_D1 0x198
#define ixMC_IO_DEBUG_EDC_TXBST_PD_D1 0x199
#define ixMC_IO_DEBUG_WCK_TXBST_PD_D1 0x19a
#define ixMC_IO_DEBUG_CK_TXBST_PD_D1 0x19b
#define ixMC_IO_DEBUG_ADDRL_TXBST_PD_D1 0x19c
#define ixMC_IO_DEBUG_ADDRH_TXBST_PD_D1 0x19d
#define ixMC_IO_DEBUG_ACMD_TXBST_PD_D1 0x19e
#define ixMC_IO_DEBUG_CMD_TXBST_PD_D1 0x19f
#define ixMC_IO_DEBUG_DQB0L_TXBST_PU_D0 0x1a0
#define ixMC_IO_DEBUG_DQB0H_TXBST_PU_D0 0x1a1
#define ixMC_IO_DEBUG_DQB1L_TXBST_PU_D0 0x1a2
#define ixMC_IO_DEBUG_DQB1H_TXBST_PU_D0 0x1a3
#define ixMC_IO_DEBUG_DQB2L_TXBST_PU_D0 0x1a4
#define ixMC_IO_DEBUG_DQB2H_TXBST_PU_D0 0x1a5
#define ixMC_IO_DEBUG_DQB3L_TXBST_PU_D0 0x1a6
#define ixMC_IO_DEBUG_DQB3H_TXBST_PU_D0 0x1a7
#define ixMC_IO_DEBUG_DBI_TXBST_PU_D0 0x1a8
#define ixMC_IO_DEBUG_EDC_TXBST_PU_D0 0x1a9
#define ixMC_IO_DEBUG_WCK_TXBST_PU_D0 0x1aa
#define ixMC_IO_DEBUG_CK_TXBST_PU_D0 0x1ab
#define ixMC_IO_DEBUG_ADDRL_TXBST_PU_D0 0x1ac
#define ixMC_IO_DEBUG_ADDRH_TXBST_PU_D0 0x1ad
#define ixMC_IO_DEBUG_ACMD_TXBST_PU_D0 0x1ae
#define ixMC_IO_DEBUG_CMD_TXBST_PU_D0 0x1af
#define ixMC_IO_DEBUG_DQB0L_TXBST_PU_D1 0x1b0
#define ixMC_IO_DEBUG_DQB0H_TXBST_PU_D1 0x1b1
#define ixMC_IO_DEBUG_DQB1L_TXBST_PU_D1 0x1b2
#define ixMC_IO_DEBUG_DQB1H_TXBST_PU_D1 0x1b3
#define ixMC_IO_DEBUG_DQB2L_TXBST_PU_D1 0x1b4
#define ixMC_IO_DEBUG_DQB2H_TXBST_PU_D1 0x1b5
#define ixMC_IO_DEBUG_DQB3L_TXBST_PU_D1 0x1b6
#define ixMC_IO_DEBUG_DQB3H_TXBST_PU_D1 0x1b7
#define ixMC_IO_DEBUG_DBI_TXBST_PU_D1 0x1b8
#define ixMC_IO_DEBUG_EDC_TXBST_PU_D1 0x1b9
#define ixMC_IO_DEBUG_WCK_TXBST_PU_D1 0x1ba
#define ixMC_IO_DEBUG_CK_TXBST_PU_D1 0x1bb
#define ixMC_IO_DEBUG_ADDRL_TXBST_PU_D1 0x1bc
#define ixMC_IO_DEBUG_ADDRH_TXBST_PU_D1 0x1bd
#define ixMC_IO_DEBUG_ACMD_TXBST_PU_D1 0x1be
#define ixMC_IO_DEBUG_CMD_TXBST_PU_D1 0x1bf
#define ixMC_IO_DEBUG_DQB0L_RX_EQ_D0 0x1c0
#define ixMC_IO_DEBUG_DQB0H_RX_EQ_D0 0x1c1
#define ixMC_IO_DEBUG_DQB1L_RX_EQ_D0 0x1c2
#define ixMC_IO_DEBUG_DQB1H_RX_EQ_D0 0x1c3
#define ixMC_IO_DEBUG_DQB2L_RX_EQ_D0 0x1c4
#define ixMC_IO_DEBUG_DQB2H_RX_EQ_D0 0x1c5
#define ixMC_IO_DEBUG_DQB3L_RX_EQ_D0 0x1c6
#define ixMC_IO_DEBUG_DQB3H_RX_EQ_D0 0x1c7
#define ixMC_IO_DEBUG_DBI_RX_EQ_D0 0x1c8
#define ixMC_IO_DEBUG_EDC_RX_EQ_D0 0x1c9
#define ixMC_IO_DEBUG_WCK_RX_EQ_D0 0x1ca
#define ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D0 0x1cb
#define ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D0 0x1cc
#define ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D0 0x1cd
#define ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D0 0x1ce
#define ixMC_IO_DEBUG_CMD_RX_EQ_D0 0x1cf
#define ixMC_IO_DEBUG_DQB0L_RX_EQ_D1 0x1d0
#define ixMC_IO_DEBUG_DQB0H_RX_EQ_D1 0x1d1
#define ixMC_IO_DEBUG_DQB1L_RX_EQ_D1 0x1d2
#define ixMC_IO_DEBUG_DQB1H_RX_EQ_D1 0x1d3
#define ixMC_IO_DEBUG_DQB2L_RX_EQ_D1 0x1d4
#define ixMC_IO_DEBUG_DQB2H_RX_EQ_D1 0x1d5
#define ixMC_IO_DEBUG_DQB3L_RX_EQ_D1 0x1d6
#define ixMC_IO_DEBUG_DQB3H_RX_EQ_D1 0x1d7
#define ixMC_IO_DEBUG_DBI_RX_EQ_D1 0x1d8
#define ixMC_IO_DEBUG_EDC_RX_EQ_D1 0x1d9
#define ixMC_IO_DEBUG_WCK_RX_EQ_D1 0x1da
#define ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D1 0x1db
#define ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D1 0x1dc
#define ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D1 0x1dd
#define ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D1 0x1de
#define ixMC_IO_DEBUG_CMD_RX_EQ_D1 0x1df
#define ixMC_IO_DEBUG_WCDR_MISC_D0 0x1e0
#define ixMC_IO_DEBUG_WCDR_CLKSEL_D0 0x1e1
#define ixMC_IO_DEBUG_WCDR_OFSCAL_D0 0x1e2
#define ixMC_IO_DEBUG_WCDR_RXPHASE_D0 0x1e3
#define ixMC_IO_DEBUG_WCDR_TXPHASE_D0 0x1e4
#define ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D0 0x1e5
#define ixMC_IO_DEBUG_WCDR_TXSLF_D0 0x1e6
#define ixMC_IO_DEBUG_WCDR_TXBST_PD_D0 0x1e7
#define ixMC_IO_DEBUG_WCDR_TXBST_PU_D0 0x1e8
#define ixMC_IO_DEBUG_WCDR_RX_EQ_D0 0x1e9
#define ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D0 0x1ea
#define ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D0 0x1eb
#define ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D0 0x1ec
#define ixMC_IO_DEBUG_WCDR_MISC_D1 0x1f0
#define ixMC_IO_DEBUG_WCDR_CLKSEL_D1 0x1f1
#define ixMC_IO_DEBUG_WCDR_OFSCAL_D1 0x1f2
#define ixMC_IO_DEBUG_WCDR_RXPHASE_D1 0x1f3
#define ixMC_IO_DEBUG_WCDR_TXPHASE_D1 0x1f4
#define ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D1 0x1f5
#define ixMC_IO_DEBUG_WCDR_TXSLF_D1 0x1f6
#define ixMC_IO_DEBUG_WCDR_TXBST_PD_D1 0x1f7
#define ixMC_IO_DEBUG_WCDR_TXBST_PU_D1 0x1f8
#define ixMC_IO_DEBUG_WCDR_RX_EQ_D1 0x1f9
#define ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D1 0x1fa
#define ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D1 0x1fb
#define ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D1 0x1fc
#define mmMC_SEQ_CNTL_3 0xd80
#define mmMC_SEQ_G5PDX_CTRL 0xd81
#define mmMC_SEQ_G5PDX_CTRL_LP 0xd82
#define mmMC_SEQ_G5PDX_CMD0 0xd83
#define mmMC_SEQ_G5PDX_CMD0_LP 0xd84
#define mmMC_SEQ_G5PDX_CMD1 0xd85
#define mmMC_SEQ_G5PDX_CMD1_LP 0xd86
#define mmMC_SEQ_SREG_READ 0xd87
#define mmMC_SEQ_SREG_STATUS 0xd88
#define mmMC_SEQ_PHYREG_BCAST 0xd89
#define mmMC_SEQ_PMG_DVS_CTL 0xd8a
#define mmMC_SEQ_PMG_DVS_CTL_LP 0xd8b
#define mmMC_SEQ_PMG_DVS_CMD 0xd8c
#define mmMC_SEQ_PMG_DVS_CMD_LP 0xd8d
#define mmMC_SEQ_DLL_STBY 0xd8e
#define mmMC_SEQ_DLL_STBY_LP 0xd8f
#define mmMC_DLB_MISCCTRL0 0xd90
#define mmMC_DLB_MISCCTRL1 0xd91
#define mmMC_DLB_MISCCTRL2 0xd92
#define mmMC_DLB_CONFIG0 0xd93
#define mmMC_DLB_CONFIG1 0xd94
#define mmMC_DLB_SETUP 0xd95
#define mmMC_DLB_SETUPSWEEP 0xd96
#define mmMC_DLB_SETUPFIFO 0xd97
#define mmMC_DLB_WRITE_MASK 0xd98
#define mmMC_DLB_STATUS 0xd99
#define mmMC_DLB_STATUS_MISC0 0xd9a
#define mmMC_DLB_STATUS_MISC1 0xd9b
#define mmMC_DLB_STATUS_MISC2 0xd9c
#define mmMC_DLB_STATUS_MISC3 0xd9d
#define mmMC_DLB_STATUS_MISC4 0xd9e
#define mmMC_DLB_STATUS_MISC5 0xd9f
#define mmMC_DLB_STATUS_MISC6 0xda0
#define mmMC_DLB_STATUS_MISC7 0xda1
#define mmMC_ARB_HARSH_EN_RD 0xdc0
#define mmMC_ARB_HARSH_EN_WR 0xdc1
#define mmMC_ARB_HARSH_TX_HI0_RD 0xdc2
#define mmMC_ARB_HARSH_TX_HI0_WR 0xdc3
#define mmMC_ARB_HARSH_TX_HI1_RD 0xdc4
#define mmMC_ARB_HARSH_TX_HI1_WR 0xdc5
#define mmMC_ARB_HARSH_TX_LO0_RD 0xdc6
#define mmMC_ARB_HARSH_TX_LO0_WR 0xdc7
#define mmMC_ARB_HARSH_TX_LO1_RD 0xdc8
#define mmMC_ARB_HARSH_TX_LO1_WR 0xdc9
#define mmMC_ARB_HARSH_BWPERIOD0_RD 0xdca
#define mmMC_ARB_HARSH_BWPERIOD0_WR 0xdcb
#define mmMC_ARB_HARSH_BWPERIOD1_RD 0xdcc
#define mmMC_ARB_HARSH_BWPERIOD1_WR 0xdcd
#define mmMC_ARB_HARSH_BWCNT0_RD 0xdce
#define mmMC_ARB_HARSH_BWCNT0_WR 0xdcf
#define mmMC_ARB_HARSH_BWCNT1_RD 0xdd0
#define mmMC_ARB_HARSH_BWCNT1_WR 0xdd1
#define mmMC_ARB_HARSH_SAT0_RD 0xdd2
#define mmMC_ARB_HARSH_SAT0_WR 0xdd3
#define mmMC_ARB_HARSH_SAT1_RD 0xdd4
#define mmMC_ARB_HARSH_SAT1_WR 0xdd5
#define mmMC_ARB_HARSH_CTL_RD 0xdd6
#define mmMC_ARB_HARSH_CTL_WR 0xdd7
#define mmMC_ARB_GRUB_PRIORITY1_RD 0xdd8
#define mmMC_ARB_GRUB_PRIORITY1_WR 0xdd9
#define mmMC_ARB_GRUB_PRIORITY2_RD 0xdda
#define mmMC_ARB_GRUB_PRIORITY2_WR 0xddb
#define mmMCIF_WB_BUFMGR_SW_CONTROL 0x5e78
#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL 0x5e78
#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL 0x5eb8
#define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL 0x5ef8
#define mmMCIF_WB_BUFMGR_CUR_LINE_R 0x5e79
#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R 0x5e79
#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R 0x5eb9
#define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R 0x5ef9
#define mmMCIF_WB_BUFMGR_STATUS 0x5e7a
#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS 0x5e7a
#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS 0x5eba
#define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS 0x5efa
#define mmMCIF_WB_BUF_PITCH 0x5e7b
#define mmMCIF_WB0_MCIF_WB_BUF_PITCH 0x5e7b
#define mmMCIF_WB1_MCIF_WB_BUF_PITCH 0x5ebb
#define mmMCIF_WB2_MCIF_WB_BUF_PITCH 0x5efb
#define mmMCIF_WB_BUF_1_STATUS 0x5e7c
#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS 0x5e7c
#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS 0x5ebc
#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS 0x5efc
#define mmMCIF_WB_BUF_1_STATUS2 0x5e7d
#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2 0x5e7d
#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2 0x5ebd
#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2 0x5efd
#define mmMCIF_WB_BUF_2_STATUS 0x5e7e
#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS 0x5e7e
#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS 0x5ebe
#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS 0x5efe
#define mmMCIF_WB_BUF_2_STATUS2 0x5e7f
#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2 0x5e7f
#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2 0x5ebf
#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2 0x5eff
#define mmMCIF_WB_BUF_3_STATUS 0x5e80
#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS 0x5e80
#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS 0x5ec0
#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS 0x5f00
#define mmMCIF_WB_BUF_3_STATUS2 0x5e81
#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2 0x5e81
#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2 0x5ec1
#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2 0x5f01
#define mmMCIF_WB_BUF_4_STATUS 0x5e82
#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS 0x5e82
#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS 0x5ec2
#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS 0x5f02
#define mmMCIF_WB_BUF_4_STATUS2 0x5e83
#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2 0x5e83
#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2 0x5ec3
#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2 0x5f03
#define mmMCIF_WB_ARBITRATION_CONTROL 0x5e84
#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL 0x5e84
#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL 0x5ec4
#define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL 0x5f04
#define mmMCIF_WB_URGENCY_WATERMARK 0x5e85
#define mmMCIF_WB0_MCIF_WB_URGENCY_WATERMARK 0x5e85
#define mmMCIF_WB1_MCIF_WB_URGENCY_WATERMARK 0x5ec5
#define mmMCIF_WB2_MCIF_WB_URGENCY_WATERMARK 0x5f05
#define mmMCIF_WB_TEST_DEBUG_INDEX 0x5e86
#define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX 0x5e86
#define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX 0x5ec6
#define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX 0x5f06
#define mmMCIF_WB_TEST_DEBUG_DATA 0x5e87
#define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_DATA 0x5e87
#define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_DATA 0x5ec7
#define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_DATA 0x5f07
#define mmMCIF_WB_BUF_1_ADDR_Y 0x5e88
#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y 0x5e88
#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y 0x5ec8
#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y 0x5f08
#define mmMCIF_WB_BUF_1_ADDR_Y_OFFSET 0x5e89
#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x5e89
#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x5ec9
#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x5f09
#define mmMCIF_WB_BUF_1_ADDR_C 0x5e8a
#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C 0x5e8a
#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C 0x5eca
#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C 0x5f0a
#define mmMCIF_WB_BUF_1_ADDR_C_OFFSET 0x5e8b
#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x5e8b
#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x5ecb
#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x5f0b
#define mmMCIF_WB_BUF_2_ADDR_Y 0x5e8c
#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y 0x5e8c
#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y 0x5ecc
#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y 0x5f0c
#define mmMCIF_WB_BUF_2_ADDR_Y_OFFSET 0x5e8d
#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x5e8d
#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x5ecd
#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x5f0d
#define mmMCIF_WB_BUF_2_ADDR_C 0x5e8e
#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C 0x5e8e
#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C 0x5ece
#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C 0x5f0e
#define mmMCIF_WB_BUF_2_ADDR_C_OFFSET 0x5e8f
#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x5e8f
#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x5ecf
#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x5f0f
#define mmMCIF_WB_BUF_3_ADDR_Y 0x5e90
#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y 0x5e90
#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y 0x5ed0
#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y 0x5f10
#define mmMCIF_WB_BUF_3_ADDR_Y_OFFSET 0x5e91
#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x5e91
#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x5ed1
#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x5f11
#define mmMCIF_WB_BUF_3_ADDR_C 0x5e92
#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C 0x5e92
#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C 0x5ed2
#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C 0x5f12
#define mmMCIF_WB_BUF_3_ADDR_C_OFFSET 0x5e93
#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x5e93
#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x5ed3
#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x5f13
#define mmMCIF_WB_BUF_4_ADDR_Y 0x5e94
#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y 0x5e94
#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y 0x5ed4
#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y 0x5f14
#define mmMCIF_WB_BUF_4_ADDR_Y_OFFSET 0x5e95
#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x5e95
#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x5ed5
#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x5f15
#define mmMCIF_WB_BUF_4_ADDR_C 0x5e96
#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C 0x5e96
#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C 0x5ed6
#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C 0x5f16
#define mmMCIF_WB_BUF_4_ADDR_C_OFFSET 0x5e97
#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x5e97
#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x5ed7
#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x5f17
#define mmMCIF_WB_BUFMGR_VCE_CONTROL 0x5e98
#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL 0x5e98
#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL 0x5ed8
#define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL 0x5f18
#define mmMCIF_WB_HVVMID_CONTROL 0x5e99
#define mmMCIF_WB0_MCIF_WB_HVVMID_CONTROL 0x5e99
#define mmMCIF_WB1_MCIF_WB_HVVMID_CONTROL 0x5ed9
#define mmMCIF_WB2_MCIF_WB_HVVMID_CONTROL 0x5f19
#endif /* GMC_8_1_D_H */
drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_enum.h 0 → 100644
浏览文件 @ bd6a6b43
/*
* GMC_8_1 Register documentation
*
* Copyright (C) 2014 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef GMC_8_1_ENUM_H
#define GMC_8_1_ENUM_H
typedef enum SurfaceEndian {
ENDIAN_NONE = 0x0,
ENDIAN_8IN16 = 0x1,
ENDIAN_8IN32 = 0x2,
ENDIAN_8IN64 = 0x3,
} SurfaceEndian;
typedef enum ArrayMode {
ARRAY_LINEAR_GENERAL = 0x0,
ARRAY_LINEAR_ALIGNED = 0x1,
ARRAY_1D_TILED_THIN1 = 0x2,
ARRAY_1D_TILED_THICK = 0x3,
ARRAY_2D_TILED_THIN1 = 0x4,
ARRAY_PRT_TILED_THIN1 = 0x5,
ARRAY_PRT_2D_TILED_THIN1 = 0x6,
ARRAY_2D_TILED_THICK = 0x7,
ARRAY_2D_TILED_XTHICK = 0x8,
ARRAY_PRT_TILED_THICK = 0x9,
ARRAY_PRT_2D_TILED_THICK = 0xa,
ARRAY_PRT_3D_TILED_THIN1 = 0xb,
ARRAY_3D_TILED_THIN1 = 0xc,
ARRAY_3D_TILED_THICK = 0xd,
ARRAY_3D_TILED_XTHICK = 0xe,
ARRAY_PRT_3D_TILED_THICK = 0xf,
} ArrayMode;
typedef enum PipeTiling {
CONFIG_1_PIPE = 0x0,
CONFIG_2_PIPE = 0x1,
CONFIG_4_PIPE = 0x2,
CONFIG_8_PIPE = 0x3,
} PipeTiling;
typedef enum BankTiling {
CONFIG_4_BANK = 0x0,
CONFIG_8_BANK = 0x1,
} BankTiling;
typedef enum GroupInterleave {
CONFIG_256B_GROUP = 0x0,
CONFIG_512B_GROUP = 0x1,
} GroupInterleave;
typedef enum RowTiling {
CONFIG_1KB_ROW = 0x0,
CONFIG_2KB_ROW = 0x1,
CONFIG_4KB_ROW = 0x2,
CONFIG_8KB_ROW = 0x3,
CONFIG_1KB_ROW_OPT = 0x4,
CONFIG_2KB_ROW_OPT = 0x5,
CONFIG_4KB_ROW_OPT = 0x6,
CONFIG_8KB_ROW_OPT = 0x7,
} RowTiling;
typedef enum BankSwapBytes {
CONFIG_128B_SWAPS = 0x0,
CONFIG_256B_SWAPS = 0x1,
CONFIG_512B_SWAPS = 0x2,
CONFIG_1KB_SWAPS = 0x3,
} BankSwapBytes;
typedef enum SampleSplitBytes {
CONFIG_1KB_SPLIT = 0x0,
CONFIG_2KB_SPLIT = 0x1,
CONFIG_4KB_SPLIT = 0x2,
CONFIG_8KB_SPLIT = 0x3,
} SampleSplitBytes;
typedef enum NumPipes {
ADDR_CONFIG_1_PIPE = 0x0,
ADDR_CONFIG_2_PIPE = 0x1,
ADDR_CONFIG_4_PIPE = 0x2,
ADDR_CONFIG_8_PIPE = 0x3,
} NumPipes;
typedef enum PipeInterleaveSize {
ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0,
ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1,
} PipeInterleaveSize;
typedef enum BankInterleaveSize {
ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0,
ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1,
ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3,
} BankInterleaveSize;
typedef enum NumShaderEngines {
ADDR_CONFIG_1_SHADER_ENGINE = 0x0,
ADDR_CONFIG_2_SHADER_ENGINE = 0x1,
} NumShaderEngines;
typedef enum ShaderEngineTileSize {
ADDR_CONFIG_SE_TILE_16 = 0x0,
ADDR_CONFIG_SE_TILE_32 = 0x1,
} ShaderEngineTileSize;
typedef enum NumGPUs {
ADDR_CONFIG_1_GPU = 0x0,
ADDR_CONFIG_2_GPU = 0x1,
ADDR_CONFIG_4_GPU = 0x2,
} NumGPUs;
typedef enum MultiGPUTileSize {
ADDR_CONFIG_GPU_TILE_16 = 0x0,
ADDR_CONFIG_GPU_TILE_32 = 0x1,
ADDR_CONFIG_GPU_TILE_64 = 0x2,
ADDR_CONFIG_GPU_TILE_128 = 0x3,
} MultiGPUTileSize;
typedef enum RowSize {
ADDR_CONFIG_1KB_ROW = 0x0,
ADDR_CONFIG_2KB_ROW = 0x1,
ADDR_CONFIG_4KB_ROW = 0x2,
} RowSize;
typedef enum NumLowerPipes {
ADDR_CONFIG_1_LOWER_PIPES = 0x0,
ADDR_CONFIG_2_LOWER_PIPES = 0x1,
} NumLowerPipes;
typedef enum DebugBlockId {
DBG_CLIENT_BLKID_RESERVED = 0x0,
DBG_CLIENT_BLKID_dbg = 0x1,
DBG_CLIENT_BLKID_scf2 = 0x2,
DBG_CLIENT_BLKID_mcd5 = 0x3,
DBG_CLIENT_BLKID_vmc = 0x4,
DBG_CLIENT_BLKID_sx30 = 0x5,
DBG_CLIENT_BLKID_mcd2 = 0x6,
DBG_CLIENT_BLKID_bci1 = 0x7,
DBG_CLIENT_BLKID_xdma_dbg_client_wrapper = 0x8,
DBG_CLIENT_BLKID_mcc0 = 0x9,
DBG_CLIENT_BLKID_uvdf_0 = 0xa,
DBG_CLIENT_BLKID_uvdf_1 = 0xb,
DBG_CLIENT_BLKID_uvdf_2 = 0xc,
DBG_CLIENT_BLKID_uvdi_0 = 0xd,
DBG_CLIENT_BLKID_bci0 = 0xe,
DBG_CLIENT_BLKID_vcec0_0 = 0xf,
DBG_CLIENT_BLKID_cb100 = 0x10,
DBG_CLIENT_BLKID_cb001 = 0x11,
DBG_CLIENT_BLKID_mcd4 = 0x12,
DBG_CLIENT_BLKID_tmonw00 = 0x13,
DBG_CLIENT_BLKID_cb101 = 0x14,
DBG_CLIENT_BLKID_sx10 = 0x15,
DBG_CLIENT_BLKID_cb301 = 0x16,
DBG_CLIENT_BLKID_tmonw01 = 0x17,
DBG_CLIENT_BLKID_vcea0_0 = 0x18,
DBG_CLIENT_BLKID_vcea0_1 = 0x19,
DBG_CLIENT_BLKID_vcea0_2 = 0x1a,
DBG_CLIENT_BLKID_vcea0_3 = 0x1b,
DBG_CLIENT_BLKID_scf1 = 0x1c,
DBG_CLIENT_BLKID_sx20 = 0x1d,
DBG_CLIENT_BLKID_spim1 = 0x1e,
DBG_CLIENT_BLKID_pa10 = 0x1f,
DBG_CLIENT_BLKID_pa00 = 0x20,
DBG_CLIENT_BLKID_gmcon = 0x21,
DBG_CLIENT_BLKID_mcb = 0x22,
DBG_CLIENT_BLKID_vgt0 = 0x23,
DBG_CLIENT_BLKID_pc0 = 0x24,
DBG_CLIENT_BLKID_bci2 = 0x25,
DBG_CLIENT_BLKID_uvdb_0 = 0x26,
DBG_CLIENT_BLKID_spim3 = 0x27,
DBG_CLIENT_BLKID_cpc_0 = 0x28,
DBG_CLIENT_BLKID_cpc_1 = 0x29,
DBG_CLIENT_BLKID_uvdm_0 = 0x2a,
DBG_CLIENT_BLKID_uvdm_1 = 0x2b,
DBG_CLIENT_BLKID_uvdm_2 = 0x2c,
DBG_CLIENT_BLKID_uvdm_3 = 0x2d,
DBG_CLIENT_BLKID_cb000 = 0x2e,
DBG_CLIENT_BLKID_spim0 = 0x2f,
DBG_CLIENT_BLKID_mcc2 = 0x30,
DBG_CLIENT_BLKID_ds0 = 0x31,
DBG_CLIENT_BLKID_srbm = 0x32,
DBG_CLIENT_BLKID_ih = 0x33,
DBG_CLIENT_BLKID_sem = 0x34,
DBG_CLIENT_BLKID_sdma_0 = 0x35,
DBG_CLIENT_BLKID_sdma_1 = 0x36,
DBG_CLIENT_BLKID_hdp = 0x37,
DBG_CLIENT_BLKID_acp_0 = 0x38,
DBG_CLIENT_BLKID_acp_1 = 0x39,
DBG_CLIENT_BLKID_cb200 = 0x3a,
DBG_CLIENT_BLKID_scf3 = 0x3b,
DBG_CLIENT_BLKID_vceb1_0 = 0x3c,
DBG_CLIENT_BLKID_vcea1_0 = 0x3d,
DBG_CLIENT_BLKID_vcea1_1 = 0x3e,
DBG_CLIENT_BLKID_vcea1_2 = 0x3f,
DBG_CLIENT_BLKID_vcea1_3 = 0x40,
DBG_CLIENT_BLKID_bci3 = 0x41,
DBG_CLIENT_BLKID_mcd0 = 0x42,
DBG_CLIENT_BLKID_pa11 = 0x43,
DBG_CLIENT_BLKID_pa01 = 0x44,
DBG_CLIENT_BLKID_cb201 = 0x45,
DBG_CLIENT_BLKID_spim2 = 0x46,
DBG_CLIENT_BLKID_vgt2 = 0x47,
DBG_CLIENT_BLKID_pc2 = 0x48,
DBG_CLIENT_BLKID_smu_0 = 0x49,
DBG_CLIENT_BLKID_smu_1 = 0x4a,
DBG_CLIENT_BLKID_smu_2 = 0x4b,
DBG_CLIENT_BLKID_cb1 = 0x4c,
DBG_CLIENT_BLKID_ia0 = 0x4d,
DBG_CLIENT_BLKID_wd = 0x4e,
DBG_CLIENT_BLKID_ia1 = 0x4f,
DBG_CLIENT_BLKID_vcec1_0 = 0x50,
DBG_CLIENT_BLKID_scf0 = 0x51,
DBG_CLIENT_BLKID_vgt1 = 0x52,
DBG_CLIENT_BLKID_pc1 = 0x53,
DBG_CLIENT_BLKID_cb0 = 0x54,
DBG_CLIENT_BLKID_gdc_one_0 = 0x55,
DBG_CLIENT_BLKID_gdc_one_1 = 0x56,
DBG_CLIENT_BLKID_gdc_one_2 = 0x57,
DBG_CLIENT_BLKID_gdc_one_3 = 0x58,
DBG_CLIENT_BLKID_gdc_one_4 = 0x59,
DBG_CLIENT_BLKID_gdc_one_5 = 0x5a,
DBG_CLIENT_BLKID_gdc_one_6 = 0x5b,
DBG_CLIENT_BLKID_gdc_one_7 = 0x5c,
DBG_CLIENT_BLKID_gdc_one_8 = 0x5d,
DBG_CLIENT_BLKID_gdc_one_9 = 0x5e,
DBG_CLIENT_BLKID_gdc_one_10 = 0x5f,
DBG_CLIENT_BLKID_gdc_one_11 = 0x60,
DBG_CLIENT_BLKID_gdc_one_12 = 0x61,
DBG_CLIENT_BLKID_gdc_one_13 = 0x62,
DBG_CLIENT_BLKID_gdc_one_14 = 0x63,
DBG_CLIENT_BLKID_gdc_one_15 = 0x64,
DBG_CLIENT_BLKID_gdc_one_16 = 0x65,
DBG_CLIENT_BLKID_gdc_one_17 = 0x66,
DBG_CLIENT_BLKID_gdc_one_18 = 0x67,
DBG_CLIENT_BLKID_gdc_one_19 = 0x68,
DBG_CLIENT_BLKID_gdc_one_20 = 0x69,
DBG_CLIENT_BLKID_gdc_one_21 = 0x6a,
DBG_CLIENT_BLKID_gdc_one_22 = 0x6b,
DBG_CLIENT_BLKID_gdc_one_23 = 0x6c,
DBG_CLIENT_BLKID_gdc_one_24 = 0x6d,
DBG_CLIENT_BLKID_gdc_one_25 = 0x6e,
DBG_CLIENT_BLKID_gdc_one_26 = 0x6f,
DBG_CLIENT_BLKID_gdc_one_27 = 0x70,
DBG_CLIENT_BLKID_gdc_one_28 = 0x71,
DBG_CLIENT_BLKID_gdc_one_29 = 0x72,
DBG_CLIENT_BLKID_gdc_one_30 = 0x73,
DBG_CLIENT_BLKID_gdc_one_31 = 0x74,
DBG_CLIENT_BLKID_gdc_one_32 = 0x75,
DBG_CLIENT_BLKID_gdc_one_33 = 0x76,
DBG_CLIENT_BLKID_gdc_one_34 = 0x77,
DBG_CLIENT_BLKID_gdc_one_35 = 0x78,
DBG_CLIENT_BLKID_vceb0_0 = 0x79,
DBG_CLIENT_BLKID_vgt3 = 0x7a,
DBG_CLIENT_BLKID_pc3 = 0x7b,
DBG_CLIENT_BLKID_mcd3 = 0x7c,
DBG_CLIENT_BLKID_uvdu_0 = 0x7d,
DBG_CLIENT_BLKID_uvdu_1 = 0x7e,
DBG_CLIENT_BLKID_uvdu_2 = 0x7f,
DBG_CLIENT_BLKID_uvdu_3 = 0x80,
DBG_CLIENT_BLKID_uvdu_4 = 0x81,
DBG_CLIENT_BLKID_uvdu_5 = 0x82,
DBG_CLIENT_BLKID_uvdu_6 = 0x83,
DBG_CLIENT_BLKID_cb300 = 0x84,
DBG_CLIENT_BLKID_mcd1 = 0x85,
DBG_CLIENT_BLKID_sx00 = 0x86,
DBG_CLIENT_BLKID_uvdc_0 = 0x87,
DBG_CLIENT_BLKID_uvdc_1 = 0x88,
DBG_CLIENT_BLKID_mcc3 = 0x89,
DBG_CLIENT_BLKID_cpg_0 = 0x8a,
DBG_CLIENT_BLKID_cpg_1 = 0x8b,
DBG_CLIENT_BLKID_gck = 0x8c,
DBG_CLIENT_BLKID_mcc1 = 0x8d,
DBG_CLIENT_BLKID_cpf_0 = 0x8e,
DBG_CLIENT_BLKID_cpf_1 = 0x8f,
DBG_CLIENT_BLKID_rlc = 0x90,
DBG_CLIENT_BLKID_grbm = 0x91,
DBG_CLIENT_BLKID_sammsp = 0x92,
DBG_CLIENT_BLKID_dci_pg = 0x93,
DBG_CLIENT_BLKID_dci_0 = 0x94,
DBG_CLIENT_BLKID_dccg0_0 = 0x95,
DBG_CLIENT_BLKID_dccg0_1 = 0x96,
DBG_CLIENT_BLKID_dcfe01_0 = 0x97,
DBG_CLIENT_BLKID_dcfe02_0 = 0x98,
DBG_CLIENT_BLKID_dcfe03_0 = 0x99,
DBG_CLIENT_BLKID_dcfe04_0 = 0x9a,
DBG_CLIENT_BLKID_dcfe05_0 = 0x9b,
DBG_CLIENT_BLKID_dcfe06_0 = 0x9c,
DBG_CLIENT_BLKID_RESERVED_LAST = 0x9d,
} DebugBlockId;
typedef enum DebugBlockId_OLD {
DBG_BLOCK_ID_RESERVED = 0x0,
DBG_BLOCK_ID_DBG = 0x1,
DBG_BLOCK_ID_VMC = 0x2,
DBG_BLOCK_ID_PDMA = 0x3,
DBG_BLOCK_ID_CG = 0x4,
DBG_BLOCK_ID_SRBM = 0x5,
DBG_BLOCK_ID_GRBM = 0x6,
DBG_BLOCK_ID_RLC = 0x7,
DBG_BLOCK_ID_CSC = 0x8,
DBG_BLOCK_ID_SEM = 0x9,
DBG_BLOCK_ID_IH = 0xa,
DBG_BLOCK_ID_SC = 0xb,
DBG_BLOCK_ID_SQ = 0xc,
DBG_BLOCK_ID_AVP = 0xd,
DBG_BLOCK_ID_GMCON = 0xe,
DBG_BLOCK_ID_SMU = 0xf,
DBG_BLOCK_ID_DMA0 = 0x10,
DBG_BLOCK_ID_DMA1 = 0x11,
DBG_BLOCK_ID_SPIM = 0x12,
DBG_BLOCK_ID_GDS = 0x13,
DBG_BLOCK_ID_SPIS = 0x14,
DBG_BLOCK_ID_UNUSED0 = 0x15,
DBG_BLOCK_ID_PA0 = 0x16,
DBG_BLOCK_ID_PA1 = 0x17,
DBG_BLOCK_ID_CP0 = 0x18,
DBG_BLOCK_ID_CP1 = 0x19,
DBG_BLOCK_ID_CP2 = 0x1a,
DBG_BLOCK_ID_UNUSED1 = 0x1b,
DBG_BLOCK_ID_UVDU = 0x1c,
DBG_BLOCK_ID_UVDM = 0x1d,
DBG_BLOCK_ID_VCE = 0x1e,
DBG_BLOCK_ID_UNUSED2 = 0x1f,
DBG_BLOCK_ID_VGT0 = 0x20,
DBG_BLOCK_ID_VGT1 = 0x21,
DBG_BLOCK_ID_IA = 0x22,
DBG_BLOCK_ID_UNUSED3 = 0x23,
DBG_BLOCK_ID_SCT0 = 0x24,
DBG_BLOCK_ID_SCT1 = 0x25,
DBG_BLOCK_ID_SPM0 = 0x26,
DBG_BLOCK_ID_SPM1 = 0x27,
DBG_BLOCK_ID_TCAA = 0x28,
DBG_BLOCK_ID_TCAB = 0x29,
DBG_BLOCK_ID_TCCA = 0x2a,
DBG_BLOCK_ID_TCCB = 0x2b,
DBG_BLOCK_ID_MCC0 = 0x2c,
DBG_BLOCK_ID_MCC1 = 0x2d,
DBG_BLOCK_ID_MCC2 = 0x2e,
DBG_BLOCK_ID_MCC3 = 0x2f,
DBG_BLOCK_ID_SX0 = 0x30,
DBG_BLOCK_ID_SX1 = 0x31,
DBG_BLOCK_ID_SX2 = 0x32,
DBG_BLOCK_ID_SX3 = 0x33,
DBG_BLOCK_ID_UNUSED4 = 0x34,
DBG_BLOCK_ID_UNUSED5 = 0x35,
DBG_BLOCK_ID_UNUSED6 = 0x36,
DBG_BLOCK_ID_UNUSED7 = 0x37,
DBG_BLOCK_ID_PC0 = 0x38,
DBG_BLOCK_ID_PC1 = 0x39,
DBG_BLOCK_ID_UNUSED8 = 0x3a,
DBG_BLOCK_ID_UNUSED9 = 0x3b,
DBG_BLOCK_ID_UNUSED10 = 0x3c,
DBG_BLOCK_ID_UNUSED11 = 0x3d,
DBG_BLOCK_ID_MCB = 0x3e,
DBG_BLOCK_ID_UNUSED12 = 0x3f,
DBG_BLOCK_ID_SCB0 = 0x40,
DBG_BLOCK_ID_SCB1 = 0x41,
DBG_BLOCK_ID_UNUSED13 = 0x42,
DBG_BLOCK_ID_UNUSED14 = 0x43,
DBG_BLOCK_ID_SCF0 = 0x44,
DBG_BLOCK_ID_SCF1 = 0x45,
DBG_BLOCK_ID_UNUSED15 = 0x46,
DBG_BLOCK_ID_UNUSED16 = 0x47,
DBG_BLOCK_ID_BCI0 = 0x48,
DBG_BLOCK_ID_BCI1 = 0x49,
DBG_BLOCK_ID_BCI2 = 0x4a,
DBG_BLOCK_ID_BCI3 = 0x4b,
DBG_BLOCK_ID_UNUSED17 = 0x4c,
DBG_BLOCK_ID_UNUSED18 = 0x4d,
DBG_BLOCK_ID_UNUSED19 = 0x4e,
DBG_BLOCK_ID_UNUSED20 = 0x4f,
DBG_BLOCK_ID_CB00 = 0x50,
DBG_BLOCK_ID_CB01 = 0x51,
DBG_BLOCK_ID_CB02 = 0x52,
DBG_BLOCK_ID_CB03 = 0x53,
DBG_BLOCK_ID_CB04 = 0x54,
DBG_BLOCK_ID_UNUSED21 = 0x55,
DBG_BLOCK_ID_UNUSED22 = 0x56,
DBG_BLOCK_ID_UNUSED23 = 0x57,
DBG_BLOCK_ID_CB10 = 0x58,
DBG_BLOCK_ID_CB11 = 0x59,
DBG_BLOCK_ID_CB12 = 0x5a,
DBG_BLOCK_ID_CB13 = 0x5b,
DBG_BLOCK_ID_CB14 = 0x5c,
DBG_BLOCK_ID_UNUSED24 = 0x5d,
DBG_BLOCK_ID_UNUSED25 = 0x5e,
DBG_BLOCK_ID_UNUSED26 = 0x5f,
DBG_BLOCK_ID_TCP0 = 0x60,
DBG_BLOCK_ID_TCP1 = 0x61,
DBG_BLOCK_ID_TCP2 = 0x62,
DBG_BLOCK_ID_TCP3 = 0x63,
DBG_BLOCK_ID_TCP4 = 0x64,
DBG_BLOCK_ID_TCP5 = 0x65,
DBG_BLOCK_ID_TCP6 = 0x66,
DBG_BLOCK_ID_TCP7 = 0x67,
DBG_BLOCK_ID_TCP8 = 0x68,
DBG_BLOCK_ID_TCP9 = 0x69,
DBG_BLOCK_ID_TCP10 = 0x6a,
DBG_BLOCK_ID_TCP11 = 0x6b,
DBG_BLOCK_ID_TCP12 = 0x6c,
DBG_BLOCK_ID_TCP13 = 0x6d,
DBG_BLOCK_ID_TCP14 = 0x6e,
DBG_BLOCK_ID_TCP15 = 0x6f,
DBG_BLOCK_ID_TCP16 = 0x70,
DBG_BLOCK_ID_TCP17 = 0x71,
DBG_BLOCK_ID_TCP18 = 0x72,
DBG_BLOCK_ID_TCP19 = 0x73,
DBG_BLOCK_ID_TCP20 = 0x74,
DBG_BLOCK_ID_TCP21 = 0x75,
DBG_BLOCK_ID_TCP22 = 0x76,
DBG_BLOCK_ID_TCP23 = 0x77,
DBG_BLOCK_ID_TCP_RESERVED0 = 0x78,
DBG_BLOCK_ID_TCP_RESERVED1 = 0x79,
DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a,
DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b,
DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c,
DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d,
DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e,
DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f,
DBG_BLOCK_ID_DB00 = 0x80,
DBG_BLOCK_ID_DB01 = 0x81,
DBG_BLOCK_ID_DB02 = 0x82,
DBG_BLOCK_ID_DB03 = 0x83,
DBG_BLOCK_ID_DB04 = 0x84,
DBG_BLOCK_ID_UNUSED27 = 0x85,
DBG_BLOCK_ID_UNUSED28 = 0x86,
DBG_BLOCK_ID_UNUSED29 = 0x87,
DBG_BLOCK_ID_DB10 = 0x88,
DBG_BLOCK_ID_DB11 = 0x89,
DBG_BLOCK_ID_DB12 = 0x8a,
DBG_BLOCK_ID_DB13 = 0x8b,
DBG_BLOCK_ID_DB14 = 0x8c,
DBG_BLOCK_ID_UNUSED30 = 0x8d,
DBG_BLOCK_ID_UNUSED31 = 0x8e,
DBG_BLOCK_ID_UNUSED32 = 0x8f,
DBG_BLOCK_ID_TCC0 = 0x90,
DBG_BLOCK_ID_TCC1 = 0x91,
DBG_BLOCK_ID_TCC2 = 0x92,
DBG_BLOCK_ID_TCC3 = 0x93,
DBG_BLOCK_ID_TCC4 = 0x94,
DBG_BLOCK_ID_TCC5 = 0x95,
DBG_BLOCK_ID_TCC6 = 0x96,
DBG_BLOCK_ID_TCC7 = 0x97,
DBG_BLOCK_ID_SPS00 = 0x98,
DBG_BLOCK_ID_SPS01 = 0x99,
DBG_BLOCK_ID_SPS02 = 0x9a,
DBG_BLOCK_ID_SPS10 = 0x9b,
DBG_BLOCK_ID_SPS11 = 0x9c,
DBG_BLOCK_ID_SPS12 = 0x9d,
DBG_BLOCK_ID_UNUSED33 = 0x9e,
DBG_BLOCK_ID_UNUSED34 = 0x9f,
DBG_BLOCK_ID_TA00 = 0xa0,
DBG_BLOCK_ID_TA01 = 0xa1,
DBG_BLOCK_ID_TA02 = 0xa2,
DBG_BLOCK_ID_TA03 = 0xa3,
DBG_BLOCK_ID_TA04 = 0xa4,
DBG_BLOCK_ID_TA05 = 0xa5,
DBG_BLOCK_ID_TA06 = 0xa6,
DBG_BLOCK_ID_TA07 = 0xa7,
DBG_BLOCK_ID_TA08 = 0xa8,
DBG_BLOCK_ID_TA09 = 0xa9,
DBG_BLOCK_ID_TA0A = 0xaa,
DBG_BLOCK_ID_TA0B = 0xab,
DBG_BLOCK_ID_UNUSED35 = 0xac,
DBG_BLOCK_ID_UNUSED36 = 0xad,
DBG_BLOCK_ID_UNUSED37 = 0xae,
DBG_BLOCK_ID_UNUSED38 = 0xaf,
DBG_BLOCK_ID_TA10 = 0xb0,
DBG_BLOCK_ID_TA11 = 0xb1,
DBG_BLOCK_ID_TA12 = 0xb2,
DBG_BLOCK_ID_TA13 = 0xb3,
DBG_BLOCK_ID_TA14 = 0xb4,
DBG_BLOCK_ID_TA15 = 0xb5,
DBG_BLOCK_ID_TA16 = 0xb6,
DBG_BLOCK_ID_TA17 = 0xb7,
DBG_BLOCK_ID_TA18 = 0xb8,
DBG_BLOCK_ID_TA19 = 0xb9,
DBG_BLOCK_ID_TA1A = 0xba,
DBG_BLOCK_ID_TA1B = 0xbb,
DBG_BLOCK_ID_UNUSED39 = 0xbc,
DBG_BLOCK_ID_UNUSED40 = 0xbd,
DBG_BLOCK_ID_UNUSED41 = 0xbe,
DBG_BLOCK_ID_UNUSED42 = 0xbf,
DBG_BLOCK_ID_TD00 = 0xc0,
DBG_BLOCK_ID_TD01 = 0xc1,
DBG_BLOCK_ID_TD02 = 0xc2,
DBG_BLOCK_ID_TD03 = 0xc3,
DBG_BLOCK_ID_TD04 = 0xc4,
DBG_BLOCK_ID_TD05 = 0xc5,
DBG_BLOCK_ID_TD06 = 0xc6,
DBG_BLOCK_ID_TD07 = 0xc7,
DBG_BLOCK_ID_TD08 = 0xc8,
DBG_BLOCK_ID_TD09 = 0xc9,
DBG_BLOCK_ID_TD0A = 0xca,
DBG_BLOCK_ID_TD0B = 0xcb,
DBG_BLOCK_ID_UNUSED43 = 0xcc,
DBG_BLOCK_ID_UNUSED44 = 0xcd,
DBG_BLOCK_ID_UNUSED45 = 0xce,
DBG_BLOCK_ID_UNUSED46 = 0xcf,
DBG_BLOCK_ID_TD10 = 0xd0,
DBG_BLOCK_ID_TD11 = 0xd1,
DBG_BLOCK_ID_TD12 = 0xd2,
DBG_BLOCK_ID_TD13 = 0xd3,
DBG_BLOCK_ID_TD14 = 0xd4,
DBG_BLOCK_ID_TD15 = 0xd5,
DBG_BLOCK_ID_TD16 = 0xd6,
DBG_BLOCK_ID_TD17 = 0xd7,
DBG_BLOCK_ID_TD18 = 0xd8,
DBG_BLOCK_ID_TD19 = 0xd9,
DBG_BLOCK_ID_TD1A = 0xda,
DBG_BLOCK_ID_TD1B = 0xdb,
DBG_BLOCK_ID_UNUSED47 = 0xdc,
DBG_BLOCK_ID_UNUSED48 = 0xdd,
DBG_BLOCK_ID_UNUSED49 = 0xde,
DBG_BLOCK_ID_UNUSED50 = 0xdf,
DBG_BLOCK_ID_MCD0 = 0xe0,
DBG_BLOCK_ID_MCD1 = 0xe1,
DBG_BLOCK_ID_MCD2 = 0xe2,
DBG_BLOCK_ID_MCD3 = 0xe3,
DBG_BLOCK_ID_MCD4 = 0xe4,
DBG_BLOCK_ID_MCD5 = 0xe5,
DBG_BLOCK_ID_UNUSED51 = 0xe6,
DBG_BLOCK_ID_UNUSED52 = 0xe7,
} DebugBlockId_OLD;
typedef enum DebugBlockId_BY2 {
DBG_BLOCK_ID_RESERVED_BY2 = 0x0,
DBG_BLOCK_ID_VMC_BY2 = 0x1,
DBG_BLOCK_ID_CG_BY2 = 0x2,
DBG_BLOCK_ID_GRBM_BY2 = 0x3,
DBG_BLOCK_ID_CSC_BY2 = 0x4,
DBG_BLOCK_ID_IH_BY2 = 0x5,
DBG_BLOCK_ID_SQ_BY2 = 0x6,
DBG_BLOCK_ID_GMCON_BY2 = 0x7,
DBG_BLOCK_ID_DMA0_BY2 = 0x8,
DBG_BLOCK_ID_SPIM_BY2 = 0x9,
DBG_BLOCK_ID_SPIS_BY2 = 0xa,
DBG_BLOCK_ID_PA0_BY2 = 0xb,
DBG_BLOCK_ID_CP0_BY2 = 0xc,
DBG_BLOCK_ID_CP2_BY2 = 0xd,
DBG_BLOCK_ID_UVDU_BY2 = 0xe,
DBG_BLOCK_ID_VCE_BY2 = 0xf,
DBG_BLOCK_ID_VGT0_BY2 = 0x10,
DBG_BLOCK_ID_IA_BY2 = 0x11,
DBG_BLOCK_ID_SCT0_BY2 = 0x12,
DBG_BLOCK_ID_SPM0_BY2 = 0x13,
DBG_BLOCK_ID_TCAA_BY2 = 0x14,
DBG_BLOCK_ID_TCCA_BY2 = 0x15,
DBG_BLOCK_ID_MCC0_BY2 = 0x16,
DBG_BLOCK_ID_MCC2_BY2 = 0x17,
DBG_BLOCK_ID_SX0_BY2 = 0x18,
DBG_BLOCK_ID_SX2_BY2 = 0x19,
DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a,
DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b,
DBG_BLOCK_ID_PC0_BY2 = 0x1c,
DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d,
DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e,
DBG_BLOCK_ID_MCB_BY2 = 0x1f,
DBG_BLOCK_ID_SCB0_BY2 = 0x20,
DBG_BLOCK_ID_UNUSED13_BY2 = 0x21,
DBG_BLOCK_ID_SCF0_BY2 = 0x22,
DBG_BLOCK_ID_UNUSED15_BY2 = 0x23,
DBG_BLOCK_ID_BCI0_BY2 = 0x24,
DBG_BLOCK_ID_BCI2_BY2 = 0x25,
DBG_BLOCK_ID_UNUSED17_BY2 = 0x26,
DBG_BLOCK_ID_UNUSED19_BY2 = 0x27,
DBG_BLOCK_ID_CB00_BY2 = 0x28,
DBG_BLOCK_ID_CB02_BY2 = 0x29,
DBG_BLOCK_ID_CB04_BY2 = 0x2a,
DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b,
DBG_BLOCK_ID_CB10_BY2 = 0x2c,
DBG_BLOCK_ID_CB12_BY2 = 0x2d,
DBG_BLOCK_ID_CB14_BY2 = 0x2e,
DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f,
DBG_BLOCK_ID_TCP0_BY2 = 0x30,
DBG_BLOCK_ID_TCP2_BY2 = 0x31,
DBG_BLOCK_ID_TCP4_BY2 = 0x32,
DBG_BLOCK_ID_TCP6_BY2 = 0x33,
DBG_BLOCK_ID_TCP8_BY2 = 0x34,
DBG_BLOCK_ID_TCP10_BY2 = 0x35,
DBG_BLOCK_ID_TCP12_BY2 = 0x36,
DBG_BLOCK_ID_TCP14_BY2 = 0x37,
DBG_BLOCK_ID_TCP16_BY2 = 0x38,
DBG_BLOCK_ID_TCP18_BY2 = 0x39,
DBG_BLOCK_ID_TCP20_BY2 = 0x3a,
DBG_BLOCK_ID_TCP22_BY2 = 0x3b,
DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c,
DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d,
DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e,
DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f,
DBG_BLOCK_ID_DB00_BY2 = 0x40,
DBG_BLOCK_ID_DB02_BY2 = 0x41,
DBG_BLOCK_ID_DB04_BY2 = 0x42,
DBG_BLOCK_ID_UNUSED28_BY2 = 0x43,
DBG_BLOCK_ID_DB10_BY2 = 0x44,
DBG_BLOCK_ID_DB12_BY2 = 0x45,
DBG_BLOCK_ID_DB14_BY2 = 0x46,
DBG_BLOCK_ID_UNUSED31_BY2 = 0x47,
DBG_BLOCK_ID_TCC0_BY2 = 0x48,
DBG_BLOCK_ID_TCC2_BY2 = 0x49,
DBG_BLOCK_ID_TCC4_BY2 = 0x4a,
DBG_BLOCK_ID_TCC6_BY2 = 0x4b,
DBG_BLOCK_ID_SPS00_BY2 = 0x4c,
DBG_BLOCK_ID_SPS02_BY2 = 0x4d,
DBG_BLOCK_ID_SPS11_BY2 = 0x4e,
DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f,
DBG_BLOCK_ID_TA00_BY2 = 0x50,
DBG_BLOCK_ID_TA02_BY2 = 0x51,
DBG_BLOCK_ID_TA04_BY2 = 0x52,
DBG_BLOCK_ID_TA06_BY2 = 0x53,
DBG_BLOCK_ID_TA08_BY2 = 0x54,
DBG_BLOCK_ID_TA0A_BY2 = 0x55,
DBG_BLOCK_ID_UNUSED35_BY2 = 0x56,
DBG_BLOCK_ID_UNUSED37_BY2 = 0x57,
DBG_BLOCK_ID_TA10_BY2 = 0x58,
DBG_BLOCK_ID_TA12_BY2 = 0x59,
DBG_BLOCK_ID_TA14_BY2 = 0x5a,
DBG_BLOCK_ID_TA16_BY2 = 0x5b,
DBG_BLOCK_ID_TA18_BY2 = 0x5c,
DBG_BLOCK_ID_TA1A_BY2 = 0x5d,
DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e,
DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f,
DBG_BLOCK_ID_TD00_BY2 = 0x60,
DBG_BLOCK_ID_TD02_BY2 = 0x61,
DBG_BLOCK_ID_TD04_BY2 = 0x62,
DBG_BLOCK_ID_TD06_BY2 = 0x63,
DBG_BLOCK_ID_TD08_BY2 = 0x64,
DBG_BLOCK_ID_TD0A_BY2 = 0x65,
DBG_BLOCK_ID_UNUSED43_BY2 = 0x66,
DBG_BLOCK_ID_UNUSED45_BY2 = 0x67,
DBG_BLOCK_ID_TD10_BY2 = 0x68,
DBG_BLOCK_ID_TD12_BY2 = 0x69,
DBG_BLOCK_ID_TD14_BY2 = 0x6a,
DBG_BLOCK_ID_TD16_BY2 = 0x6b,
DBG_BLOCK_ID_TD18_BY2 = 0x6c,
DBG_BLOCK_ID_TD1A_BY2 = 0x6d,
DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e,
DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f,
DBG_BLOCK_ID_MCD0_BY2 = 0x70,
DBG_BLOCK_ID_MCD2_BY2 = 0x71,
DBG_BLOCK_ID_MCD4_BY2 = 0x72,
DBG_BLOCK_ID_UNUSED51_BY2 = 0x73,
} DebugBlockId_BY2;
typedef enum DebugBlockId_BY4 {
DBG_BLOCK_ID_RESERVED_BY4 = 0x0,
DBG_BLOCK_ID_CG_BY4 = 0x1,
DBG_BLOCK_ID_CSC_BY4 = 0x2,
DBG_BLOCK_ID_SQ_BY4 = 0x3,
DBG_BLOCK_ID_DMA0_BY4 = 0x4,
DBG_BLOCK_ID_SPIS_BY4 = 0x5,
DBG_BLOCK_ID_CP0_BY4 = 0x6,
DBG_BLOCK_ID_UVDU_BY4 = 0x7,
DBG_BLOCK_ID_VGT0_BY4 = 0x8,
DBG_BLOCK_ID_SCT0_BY4 = 0x9,
DBG_BLOCK_ID_TCAA_BY4 = 0xa,
DBG_BLOCK_ID_MCC0_BY4 = 0xb,
DBG_BLOCK_ID_SX0_BY4 = 0xc,
DBG_BLOCK_ID_UNUSED4_BY4 = 0xd,
DBG_BLOCK_ID_PC0_BY4 = 0xe,
DBG_BLOCK_ID_UNUSED10_BY4 = 0xf,
DBG_BLOCK_ID_SCB0_BY4 = 0x10,
DBG_BLOCK_ID_SCF0_BY4 = 0x11,
DBG_BLOCK_ID_BCI0_BY4 = 0x12,
DBG_BLOCK_ID_UNUSED17_BY4 = 0x13,
DBG_BLOCK_ID_CB00_BY4 = 0x14,
DBG_BLOCK_ID_CB04_BY4 = 0x15,
DBG_BLOCK_ID_CB10_BY4 = 0x16,
DBG_BLOCK_ID_CB14_BY4 = 0x17,
DBG_BLOCK_ID_TCP0_BY4 = 0x18,
DBG_BLOCK_ID_TCP4_BY4 = 0x19,
DBG_BLOCK_ID_TCP8_BY4 = 0x1a,
DBG_BLOCK_ID_TCP12_BY4 = 0x1b,
DBG_BLOCK_ID_TCP16_BY4 = 0x1c,
DBG_BLOCK_ID_TCP20_BY4 = 0x1d,
DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e,
DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f,
DBG_BLOCK_ID_DB_BY4 = 0x20,
DBG_BLOCK_ID_DB04_BY4 = 0x21,
DBG_BLOCK_ID_DB10_BY4 = 0x22,
DBG_BLOCK_ID_DB14_BY4 = 0x23,
DBG_BLOCK_ID_TCC0_BY4 = 0x24,
DBG_BLOCK_ID_TCC4_BY4 = 0x25,
DBG_BLOCK_ID_SPS00_BY4 = 0x26,
DBG_BLOCK_ID_SPS11_BY4 = 0x27,
DBG_BLOCK_ID_TA00_BY4 = 0x28,
DBG_BLOCK_ID_TA04_BY4 = 0x29,
DBG_BLOCK_ID_TA08_BY4 = 0x2a,
DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b,
DBG_BLOCK_ID_TA10_BY4 = 0x2c,
DBG_BLOCK_ID_TA14_BY4 = 0x2d,
DBG_BLOCK_ID_TA18_BY4 = 0x2e,
DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f,
DBG_BLOCK_ID_TD00_BY4 = 0x30,
DBG_BLOCK_ID_TD04_BY4 = 0x31,
DBG_BLOCK_ID_TD08_BY4 = 0x32,
DBG_BLOCK_ID_UNUSED43_BY4 = 0x33,
DBG_BLOCK_ID_TD10_BY4 = 0x34,
DBG_BLOCK_ID_TD14_BY4 = 0x35,
DBG_BLOCK_ID_TD18_BY4 = 0x36,
DBG_BLOCK_ID_UNUSED47_BY4 = 0x37,
DBG_BLOCK_ID_MCD0_BY4 = 0x38,
DBG_BLOCK_ID_MCD4_BY4 = 0x39,
} DebugBlockId_BY4;
typedef enum DebugBlockId_BY8 {
DBG_BLOCK_ID_RESERVED_BY8 = 0x0,
DBG_BLOCK_ID_CSC_BY8 = 0x1,
DBG_BLOCK_ID_DMA0_BY8 = 0x2,
DBG_BLOCK_ID_CP0_BY8 = 0x3,
DBG_BLOCK_ID_VGT0_BY8 = 0x4,
DBG_BLOCK_ID_TCAA_BY8 = 0x5,
DBG_BLOCK_ID_SX0_BY8 = 0x6,
DBG_BLOCK_ID_PC0_BY8 = 0x7,
DBG_BLOCK_ID_SCB0_BY8 = 0x8,
DBG_BLOCK_ID_BCI0_BY8 = 0x9,
DBG_BLOCK_ID_CB00_BY8 = 0xa,
DBG_BLOCK_ID_CB10_BY8 = 0xb,
DBG_BLOCK_ID_TCP0_BY8 = 0xc,
DBG_BLOCK_ID_TCP8_BY8 = 0xd,
DBG_BLOCK_ID_TCP16_BY8 = 0xe,
DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf,
DBG_BLOCK_ID_DB00_BY8 = 0x10,
DBG_BLOCK_ID_DB10_BY8 = 0x11,
DBG_BLOCK_ID_TCC0_BY8 = 0x12,
DBG_BLOCK_ID_SPS00_BY8 = 0x13,
DBG_BLOCK_ID_TA00_BY8 = 0x14,
DBG_BLOCK_ID_TA08_BY8 = 0x15,
DBG_BLOCK_ID_TA10_BY8 = 0x16,
DBG_BLOCK_ID_TA18_BY8 = 0x17,
DBG_BLOCK_ID_TD00_BY8 = 0x18,
DBG_BLOCK_ID_TD08_BY8 = 0x19,
DBG_BLOCK_ID_TD10_BY8 = 0x1a,
DBG_BLOCK_ID_TD18_BY8 = 0x1b,
DBG_BLOCK_ID_MCD0_BY8 = 0x1c,
} DebugBlockId_BY8;
typedef enum DebugBlockId_BY16 {
DBG_BLOCK_ID_RESERVED_BY16 = 0x0,
DBG_BLOCK_ID_DMA0_BY16 = 0x1,
DBG_BLOCK_ID_VGT0_BY16 = 0x2,
DBG_BLOCK_ID_SX0_BY16 = 0x3,
DBG_BLOCK_ID_SCB0_BY16 = 0x4,
DBG_BLOCK_ID_CB00_BY16 = 0x5,
DBG_BLOCK_ID_TCP0_BY16 = 0x6,
DBG_BLOCK_ID_TCP16_BY16 = 0x7,
DBG_BLOCK_ID_DB00_BY16 = 0x8,
DBG_BLOCK_ID_TCC0_BY16 = 0x9,
DBG_BLOCK_ID_TA00_BY16 = 0xa,
DBG_BLOCK_ID_TA10_BY16 = 0xb,
DBG_BLOCK_ID_TD00_BY16 = 0xc,
DBG_BLOCK_ID_TD10_BY16 = 0xd,
DBG_BLOCK_ID_MCD0_BY16 = 0xe,
} DebugBlockId_BY16;
typedef enum ColorTransform {
DCC_CT_AUTO = 0x0,
DCC_CT_NONE = 0x1,
ABGR_TO_A_BG_G_RB = 0x2,
BGRA_TO_BG_G_RB_A = 0x3,
} ColorTransform;
typedef enum CompareRef {
REF_NEVER = 0x0,
REF_LESS = 0x1,
REF_EQUAL = 0x2,
REF_LEQUAL = 0x3,
REF_GREATER = 0x4,
REF_NOTEQUAL = 0x5,
REF_GEQUAL = 0x6,
REF_ALWAYS = 0x7,
} CompareRef;
typedef enum ReadSize {
READ_256_BITS = 0x0,
READ_512_BITS = 0x1,
} ReadSize;
typedef enum DepthFormat {
DEPTH_INVALID = 0x0,
DEPTH_16 = 0x1,
DEPTH_X8_24 = 0x2,
DEPTH_8_24 = 0x3,
DEPTH_X8_24_FLOAT = 0x4,
DEPTH_8_24_FLOAT = 0x5,
DEPTH_32_FLOAT = 0x6,
DEPTH_X24_8_32_FLOAT = 0x7,
} DepthFormat;
typedef enum ZFormat {
Z_INVALID = 0x0,
Z_16 = 0x1,
Z_24 = 0x2,
Z_32_FLOAT = 0x3,
} ZFormat;
typedef enum StencilFormat {
STENCIL_INVALID = 0x0,
STENCIL_8 = 0x1,
} StencilFormat;
typedef enum CmaskMode {
CMASK_CLEAR_NONE = 0x0,
CMASK_CLEAR_ONE = 0x1,
CMASK_CLEAR_ALL = 0x2,
CMASK_ANY_EXPANDED = 0x3,
CMASK_ALPHA0_FRAG1 = 0x4,
CMASK_ALPHA0_FRAG2 = 0x5,
CMASK_ALPHA0_FRAG4 = 0x6,
CMASK_ALPHA0_FRAGS = 0x7,
CMASK_ALPHA1_FRAG1 = 0x8,
CMASK_ALPHA1_FRAG2 = 0x9,
CMASK_ALPHA1_FRAG4 = 0xa,
CMASK_ALPHA1_FRAGS = 0xb,
CMASK_ALPHAX_FRAG1 = 0xc,
CMASK_ALPHAX_FRAG2 = 0xd,
CMASK_ALPHAX_FRAG4 = 0xe,
CMASK_ALPHAX_FRAGS = 0xf,
} CmaskMode;
typedef enum QuadExportFormat {
EXPORT_UNUSED = 0x0,
EXPORT_32_R = 0x1,
EXPORT_32_GR = 0x2,
EXPORT_32_AR = 0x3,
EXPORT_FP16_ABGR = 0x4,
EXPORT_UNSIGNED16_ABGR = 0x5,
EXPORT_SIGNED16_ABGR = 0x6,
EXPORT_32_ABGR = 0x7,
} QuadExportFormat;
typedef enum QuadExportFormatOld {
EXPORT_4P_32BPC_ABGR = 0x0,
EXPORT_4P_16BPC_ABGR = 0x1,
EXPORT_4P_32BPC_GR = 0x2,
EXPORT_4P_32BPC_AR = 0x3,
EXPORT_2P_32BPC_ABGR = 0x4,
EXPORT_8P_32BPC_R = 0x5,
} QuadExportFormatOld;
typedef enum ColorFormat {
COLOR_INVALID = 0x0,
COLOR_8 = 0x1,
COLOR_16 = 0x2,
COLOR_8_8 = 0x3,
COLOR_32 = 0x4,
COLOR_16_16 = 0x5,
COLOR_10_11_11 = 0x6,
COLOR_11_11_10 = 0x7,
COLOR_10_10_10_2 = 0x8,
COLOR_2_10_10_10 = 0x9,
COLOR_8_8_8_8 = 0xa,
COLOR_32_32 = 0xb,
COLOR_16_16_16_16 = 0xc,
COLOR_RESERVED_13 = 0xd,
COLOR_32_32_32_32 = 0xe,
COLOR_RESERVED_15 = 0xf,
COLOR_5_6_5 = 0x10,
COLOR_1_5_5_5 = 0x11,
COLOR_5_5_5_1 = 0x12,
COLOR_4_4_4_4 = 0x13,
COLOR_8_24 = 0x14,
COLOR_24_8 = 0x15,
COLOR_X24_8_32_FLOAT = 0x16,
COLOR_RESERVED_23 = 0x17,
} ColorFormat;
typedef enum SurfaceFormat {
FMT_INVALID = 0x0,
FMT_8 = 0x1,
FMT_16 = 0x2,
FMT_8_8 = 0x3,
FMT_32 = 0x4,
FMT_16_16 = 0x5,
FMT_10_11_11 = 0x6,
FMT_11_11_10 = 0x7,
FMT_10_10_10_2 = 0x8,
FMT_2_10_10_10 = 0x9,
FMT_8_8_8_8 = 0xa,
FMT_32_32 = 0xb,
FMT_16_16_16_16 = 0xc,
FMT_32_32_32 = 0xd,
FMT_32_32_32_32 = 0xe,
FMT_RESERVED_4 = 0xf,
FMT_5_6_5 = 0x10,
FMT_1_5_5_5 = 0x11,
FMT_5_5_5_1 = 0x12,
FMT_4_4_4_4 = 0x13,
FMT_8_24 = 0x14,
FMT_24_8 = 0x15,
FMT_X24_8_32_FLOAT = 0x16,
FMT_RESERVED_33 = 0x17,
FMT_11_11_10_FLOAT = 0x18,
FMT_16_FLOAT = 0x19,
FMT_32_FLOAT = 0x1a,
FMT_16_16_FLOAT = 0x1b,
FMT_8_24_FLOAT = 0x1c,
FMT_24_8_FLOAT = 0x1d,
FMT_32_32_FLOAT = 0x1e,
FMT_10_11_11_FLOAT = 0x1f,
FMT_16_16_16_16_FLOAT = 0x20,
FMT_3_3_2 = 0x21,
FMT_6_5_5 = 0x22,
FMT_32_32_32_32_FLOAT = 0x23,
FMT_RESERVED_36 = 0x24,
FMT_1 = 0x25,
FMT_1_REVERSED = 0x26,
FMT_GB_GR = 0x27,
FMT_BG_RG = 0x28,
FMT_32_AS_8 = 0x29,
FMT_32_AS_8_8 = 0x2a,
FMT_5_9_9_9_SHAREDEXP = 0x2b,
FMT_8_8_8 = 0x2c,
FMT_16_16_16 = 0x2d,
FMT_16_16_16_FLOAT = 0x2e,
FMT_4_4 = 0x2f,
FMT_32_32_32_FLOAT = 0x30,
FMT_BC1 = 0x31,
FMT_BC2 = 0x32,
FMT_BC3 = 0x33,
FMT_BC4 = 0x34,
FMT_BC5 = 0x35,
FMT_BC6 = 0x36,
FMT_BC7 = 0x37,
FMT_32_AS_32_32_32_32 = 0x38,
FMT_APC3 = 0x39,
FMT_APC4 = 0x3a,
FMT_APC5 = 0x3b,
FMT_APC6 = 0x3c,
FMT_APC7 = 0x3d,
FMT_CTX1 = 0x3e,
FMT_RESERVED_63 = 0x3f,
} SurfaceFormat;
typedef enum BUF_DATA_FORMAT {
BUF_DATA_FORMAT_INVALID = 0x0,
BUF_DATA_FORMAT_8 = 0x1,
BUF_DATA_FORMAT_16 = 0x2,
BUF_DATA_FORMAT_8_8 = 0x3,
BUF_DATA_FORMAT_32 = 0x4,
BUF_DATA_FORMAT_16_16 = 0x5,
BUF_DATA_FORMAT_10_11_11 = 0x6,
BUF_DATA_FORMAT_11_11_10 = 0x7,
BUF_DATA_FORMAT_10_10_10_2 = 0x8,
BUF_DATA_FORMAT_2_10_10_10 = 0x9,
BUF_DATA_FORMAT_8_8_8_8 = 0xa,
BUF_DATA_FORMAT_32_32 = 0xb,
BUF_DATA_FORMAT_16_16_16_16 = 0xc,
BUF_DATA_FORMAT_32_32_32 = 0xd,
BUF_DATA_FORMAT_32_32_32_32 = 0xe,
BUF_DATA_FORMAT_RESERVED_15 = 0xf,
} BUF_DATA_FORMAT;
typedef enum IMG_DATA_FORMAT {
IMG_DATA_FORMAT_INVALID = 0x0,
IMG_DATA_FORMAT_8 = 0x1,
IMG_DATA_FORMAT_16 = 0x2,
IMG_DATA_FORMAT_8_8 = 0x3,
IMG_DATA_FORMAT_32 = 0x4,
IMG_DATA_FORMAT_16_16 = 0x5,
IMG_DATA_FORMAT_10_11_11 = 0x6,
IMG_DATA_FORMAT_11_11_10 = 0x7,
IMG_DATA_FORMAT_10_10_10_2 = 0x8,
IMG_DATA_FORMAT_2_10_10_10 = 0x9,
IMG_DATA_FORMAT_8_8_8_8 = 0xa,
IMG_DATA_FORMAT_32_32 = 0xb,
IMG_DATA_FORMAT_16_16_16_16 = 0xc,
IMG_DATA_FORMAT_32_32_32 = 0xd,
IMG_DATA_FORMAT_32_32_32_32 = 0xe,
IMG_DATA_FORMAT_RESERVED_15 = 0xf,
IMG_DATA_FORMAT_5_6_5 = 0x10,
IMG_DATA_FORMAT_1_5_5_5 = 0x11,
IMG_DATA_FORMAT_5_5_5_1 = 0x12,
IMG_DATA_FORMAT_4_4_4_4 = 0x13,
IMG_DATA_FORMAT_8_24 = 0x14,
IMG_DATA_FORMAT_24_8 = 0x15,
IMG_DATA_FORMAT_X24_8_32 = 0x16,
IMG_DATA_FORMAT_RESERVED_23 = 0x17,
IMG_DATA_FORMAT_RESERVED_24 = 0x18,
IMG_DATA_FORMAT_RESERVED_25 = 0x19,
IMG_DATA_FORMAT_RESERVED_26 = 0x1a,
IMG_DATA_FORMAT_RESERVED_27 = 0x1b,
IMG_DATA_FORMAT_RESERVED_28 = 0x1c,
IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
IMG_DATA_FORMAT_RESERVED_30 = 0x1e,
IMG_DATA_FORMAT_RESERVED_31 = 0x1f,
IMG_DATA_FORMAT_GB_GR = 0x20,
IMG_DATA_FORMAT_BG_RG = 0x21,
IMG_DATA_FORMAT_5_9_9_9 = 0x22,
IMG_DATA_FORMAT_BC1 = 0x23,
IMG_DATA_FORMAT_BC2 = 0x24,
IMG_DATA_FORMAT_BC3 = 0x25,
IMG_DATA_FORMAT_BC4 = 0x26,
IMG_DATA_FORMAT_BC5 = 0x27,
IMG_DATA_FORMAT_BC6 = 0x28,
IMG_DATA_FORMAT_BC7 = 0x29,
IMG_DATA_FORMAT_RESERVED_42 = 0x2a,
IMG_DATA_FORMAT_RESERVED_43 = 0x2b,
IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c,
IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d,
IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e,
IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f,
IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30,
IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31,
IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32,
IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33,
IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34,
IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35,
IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36,
IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37,
IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38,
IMG_DATA_FORMAT_4_4 = 0x39,
IMG_DATA_FORMAT_6_5_5 = 0x3a,
IMG_DATA_FORMAT_1 = 0x3b,
IMG_DATA_FORMAT_1_REVERSED = 0x3c,
IMG_DATA_FORMAT_32_AS_8 = 0x3d,
IMG_DATA_FORMAT_32_AS_8_8 = 0x3e,
IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f,
} IMG_DATA_FORMAT;
typedef enum BUF_NUM_FORMAT {
BUF_NUM_FORMAT_UNORM = 0x0,
BUF_NUM_FORMAT_SNORM = 0x1,
BUF_NUM_FORMAT_USCALED = 0x2,
BUF_NUM_FORMAT_SSCALED = 0x3,
BUF_NUM_FORMAT_UINT = 0x4,
BUF_NUM_FORMAT_SINT = 0x5,
BUF_NUM_FORMAT_RESERVED_6 = 0x6,
BUF_NUM_FORMAT_FLOAT = 0x7,
} BUF_NUM_FORMAT;
typedef enum IMG_NUM_FORMAT {
IMG_NUM_FORMAT_UNORM = 0x0,
IMG_NUM_FORMAT_SNORM = 0x1,
IMG_NUM_FORMAT_USCALED = 0x2,
IMG_NUM_FORMAT_SSCALED = 0x3,
IMG_NUM_FORMAT_UINT = 0x4,
IMG_NUM_FORMAT_SINT = 0x5,
IMG_NUM_FORMAT_RESERVED_6 = 0x6,
IMG_NUM_FORMAT_FLOAT = 0x7,
IMG_NUM_FORMAT_RESERVED_8 = 0x8,
IMG_NUM_FORMAT_SRGB = 0x9,
IMG_NUM_FORMAT_RESERVED_10 = 0xa,
IMG_NUM_FORMAT_RESERVED_11 = 0xb,
IMG_NUM_FORMAT_RESERVED_12 = 0xc,
IMG_NUM_FORMAT_RESERVED_13 = 0xd,
IMG_NUM_FORMAT_RESERVED_14 = 0xe,
IMG_NUM_FORMAT_RESERVED_15 = 0xf,
} IMG_NUM_FORMAT;
typedef enum TileType {
ARRAY_COLOR_TILE = 0x0,
ARRAY_DEPTH_TILE = 0x1,
} TileType;
typedef enum NonDispTilingOrder {
ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
} NonDispTilingOrder;
typedef enum MicroTileMode {
ADDR_SURF_DISPLAY_MICRO_TILING = 0x0,
ADDR_SURF_THIN_MICRO_TILING = 0x1,
ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
ADDR_SURF_ROTATED_MICRO_TILING = 0x3,
ADDR_SURF_THICK_MICRO_TILING = 0x4,
} MicroTileMode;
typedef enum TileSplit {
ADDR_SURF_TILE_SPLIT_64B = 0x0,
ADDR_SURF_TILE_SPLIT_128B = 0x1,
ADDR_SURF_TILE_SPLIT_256B = 0x2,
ADDR_SURF_TILE_SPLIT_512B = 0x3,
ADDR_SURF_TILE_SPLIT_1KB = 0x4,
ADDR_SURF_TILE_SPLIT_2KB = 0x5,
ADDR_SURF_TILE_SPLIT_4KB = 0x6,
} TileSplit;
typedef enum SampleSplit {
ADDR_SURF_SAMPLE_SPLIT_1 = 0x0,
ADDR_SURF_SAMPLE_SPLIT_2 = 0x1,
ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
ADDR_SURF_SAMPLE_SPLIT_8 = 0x3,
} SampleSplit;
typedef enum PipeConfig {
ADDR_SURF_P2 = 0x0,
ADDR_SURF_P2_RESERVED0 = 0x1,
ADDR_SURF_P2_RESERVED1 = 0x2,
ADDR_SURF_P2_RESERVED2 = 0x3,
ADDR_SURF_P4_8x16 = 0x4,
ADDR_SURF_P4_16x16 = 0x5,
ADDR_SURF_P4_16x32 = 0x6,
ADDR_SURF_P4_32x32 = 0x7,
ADDR_SURF_P8_16x16_8x16 = 0x8,
ADDR_SURF_P8_16x32_8x16 = 0x9,
ADDR_SURF_P8_32x32_8x16 = 0xa,
ADDR_SURF_P8_16x32_16x16 = 0xb,
ADDR_SURF_P8_32x32_16x16 = 0xc,
ADDR_SURF_P8_32x32_16x32 = 0xd,
ADDR_SURF_P8_32x64_32x32 = 0xe,
ADDR_SURF_P8_RESERVED0 = 0xf,
ADDR_SURF_P16_32x32_8x16 = 0x10,
ADDR_SURF_P16_32x32_16x16 = 0x11,
} PipeConfig;
typedef enum NumBanks {
ADDR_SURF_2_BANK = 0x0,
ADDR_SURF_4_BANK = 0x1,
ADDR_SURF_8_BANK = 0x2,
ADDR_SURF_16_BANK = 0x3,
} NumBanks;
typedef enum BankWidth {
ADDR_SURF_BANK_WIDTH_1 = 0x0,
ADDR_SURF_BANK_WIDTH_2 = 0x1,
ADDR_SURF_BANK_WIDTH_4 = 0x2,
ADDR_SURF_BANK_WIDTH_8 = 0x3,
} BankWidth;
typedef enum BankHeight {
ADDR_SURF_BANK_HEIGHT_1 = 0x0,
ADDR_SURF_BANK_HEIGHT_2 = 0x1,
ADDR_SURF_BANK_HEIGHT_4 = 0x2,
ADDR_SURF_BANK_HEIGHT_8 = 0x3,
} BankHeight;
typedef enum BankWidthHeight {
ADDR_SURF_BANK_WH_1 = 0x0,
ADDR_SURF_BANK_WH_2 = 0x1,
ADDR_SURF_BANK_WH_4 = 0x2,
ADDR_SURF_BANK_WH_8 = 0x3,
} BankWidthHeight;
typedef enum MacroTileAspect {
ADDR_SURF_MACRO_ASPECT_1 = 0x0,
ADDR_SURF_MACRO_ASPECT_2 = 0x1,
ADDR_SURF_MACRO_ASPECT_4 = 0x2,
ADDR_SURF_MACRO_ASPECT_8 = 0x3,
} MacroTileAspect;
typedef enum GATCL1RequestType {
GATCL1_TYPE_NORMAL = 0x0,
GATCL1_TYPE_SHOOTDOWN = 0x1,
GATCL1_TYPE_BYPASS = 0x2,
} GATCL1RequestType;
typedef enum TCC_CACHE_POLICIES {
TCC_CACHE_POLICY_LRU = 0x0,
TCC_CACHE_POLICY_STREAM = 0x1,
} TCC_CACHE_POLICIES;
typedef enum MTYPE {
MTYPE_NC_NV = 0x0,
MTYPE_NC = 0x1,
MTYPE_CC = 0x2,
MTYPE_UC = 0x3,
} MTYPE;
typedef enum PERFMON_COUNTER_MODE {
PERFMON_COUNTER_MODE_ACCUM = 0x0,
PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1,
PERFMON_COUNTER_MODE_MAX = 0x2,
PERFMON_COUNTER_MODE_DIRTY = 0x3,
PERFMON_COUNTER_MODE_SAMPLE = 0x4,
PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5,
PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6,
PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7,
PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8,
PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9,
PERFMON_COUNTER_MODE_RESERVED = 0xf,
} PERFMON_COUNTER_MODE;
typedef enum PERFMON_SPM_MODE {
PERFMON_SPM_MODE_OFF = 0x0,
PERFMON_SPM_MODE_16BIT_CLAMP = 0x1,
PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
PERFMON_SPM_MODE_32BIT_CLAMP = 0x3,
PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4,
PERFMON_SPM_MODE_RESERVED_5 = 0x5,
PERFMON_SPM_MODE_RESERVED_6 = 0x6,
PERFMON_SPM_MODE_RESERVED_7 = 0x7,
PERFMON_SPM_MODE_TEST_MODE_0 = 0x8,
PERFMON_SPM_MODE_TEST_MODE_1 = 0x9,
PERFMON_SPM_MODE_TEST_MODE_2 = 0xa,
} PERFMON_SPM_MODE;
typedef enum SurfaceTiling {
ARRAY_LINEAR = 0x0,
ARRAY_TILED = 0x1,
} SurfaceTiling;
typedef enum SurfaceArray {
ARRAY_1D = 0x0,
ARRAY_2D = 0x1,
ARRAY_3D = 0x2,
ARRAY_3D_SLICE = 0x3,
} SurfaceArray;
typedef enum ColorArray {
ARRAY_2D_ALT_COLOR = 0x0,
ARRAY_2D_COLOR = 0x1,
ARRAY_3D_SLICE_COLOR = 0x3,
} ColorArray;
typedef enum DepthArray {
ARRAY_2D_ALT_DEPTH = 0x0,
ARRAY_2D_DEPTH = 0x1,
} DepthArray;
typedef enum ENUM_NUM_SIMD_PER_CU {
NUM_SIMD_PER_CU = 0x4,
} ENUM_NUM_SIMD_PER_CU;
typedef enum MEM_PWR_FORCE_CTRL {
NO_FORCE_REQUEST = 0x0,
FORCE_LIGHT_SLEEP_REQUEST = 0x1,
FORCE_DEEP_SLEEP_REQUEST = 0x2,
FORCE_SHUT_DOWN_REQUEST = 0x3,
} MEM_PWR_FORCE_CTRL;
typedef enum MEM_PWR_FORCE_CTRL2 {
NO_FORCE_REQ = 0x0,
FORCE_LIGHT_SLEEP_REQ = 0x1,
} MEM_PWR_FORCE_CTRL2;
typedef enum MEM_PWR_DIS_CTRL {
ENABLE_MEM_PWR_CTRL = 0x0,
DISABLE_MEM_PWR_CTRL = 0x1,
} MEM_PWR_DIS_CTRL;
typedef enum MEM_PWR_SEL_CTRL {
DYNAMIC_SHUT_DOWN_ENABLE = 0x0,
DYNAMIC_DEEP_SLEEP_ENABLE = 0x1,
DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
} MEM_PWR_SEL_CTRL;
typedef enum MEM_PWR_SEL_CTRL2 {
DYNAMIC_DEEP_SLEEP_EN = 0x0,
DYNAMIC_LIGHT_SLEEP_EN = 0x1,
} MEM_PWR_SEL_CTRL2;
#endif /* GMC_8_1_ENUM_H */
drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h 0 → 100644
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