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kernel_linux
提交 b93a4afc 编写于 作者: R Russell King
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Merge branch 'for-rmk' of git://git.pengutronix.de/git/imx/linux-2.6 into devel-stable 

Conflicts:
	arch/arm/Makefile
上级 62c132a8 9b1489e9
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MAINTAINERS
浏览文件 @ b93a4afc
...@@ -662,6 +662,12 @@ T: git://git.pengutronix.de/git/imx/linux-2.6.git ...@@ -662,6 +662,12 @@ T: git://git.pengutronix.de/git/imx/linux-2.6.git
F: arch/arm/mach-mx*/ F: arch/arm/mach-mx*/
F: arch/arm/plat-mxc/ F: arch/arm/plat-mxc/
ARM/FREESCALE IMX51
M: Amit Kucheria <amit.kucheria@canonical.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: arch/arm/mach-mx5/
ARM/GLOMATION GESBC9312SX MACHINE SUPPORT ARM/GLOMATION GESBC9312SX MACHINE SUPPORT
M: Lennert Buytenhek <kernel@wantstofly.org> M: Lennert Buytenhek <kernel@wantstofly.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
......
arch/arm/Kconfig
浏览文件 @ b93a4afc
...@@ -310,10 +310,9 @@ config ARCH_MXC ...@@ -310,10 +310,9 @@ config ARCH_MXC
bool "Freescale MXC/iMX-based" bool "Freescale MXC/iMX-based"
select GENERIC_TIME select GENERIC_TIME
select GENERIC_CLOCKEVENTS select GENERIC_CLOCKEVENTS
select ARCH_MTD_XIP
select GENERIC_GPIO
select ARCH_REQUIRE_GPIOLIB select ARCH_REQUIRE_GPIOLIB
select HAVE_CLK select HAVE_CLK
select COMMON_CLKDEV
help help
Support for Freescale MXC/iMX-based family of processors Support for Freescale MXC/iMX-based family of processors
......
arch/arm/Makefile
浏览文件 @ b93a4afc
...@@ -146,6 +146,7 @@ machine-$(CONFIG_ARCH_MX1) := mx1 ...@@ -146,6 +146,7 @@ machine-$(CONFIG_ARCH_MX1) := mx1
machine-$(CONFIG_ARCH_MX2) := mx2 machine-$(CONFIG_ARCH_MX2) := mx2
machine-$(CONFIG_ARCH_MX25) := mx25 machine-$(CONFIG_ARCH_MX25) := mx25
machine-$(CONFIG_ARCH_MX3) := mx3 machine-$(CONFIG_ARCH_MX3) := mx3
machine-$(CONFIG_ARCH_MX5) := mx5
machine-$(CONFIG_ARCH_MXC91231) := mxc91231 machine-$(CONFIG_ARCH_MXC91231) := mxc91231
machine-$(CONFIG_ARCH_NETX) := netx machine-$(CONFIG_ARCH_NETX) := netx
machine-$(CONFIG_ARCH_NOMADIK) := nomadik machine-$(CONFIG_ARCH_NOMADIK) := nomadik
......
arch/arm/configs/mx1ads_defconfig 已删除 100644 → 0
浏览文件 @ 62c132a8
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.12-rc1-bk2
# Sun Mar 27 02:15:46 2005
#
CONFIG_ARM=y
CONFIG_MMU=y
CONFIG_UID16=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_GENERIC_IOMAP=y
#
# Code maturity level options
#
CONFIG_EXPERIMENTAL=y
CONFIG_CLEAN_COMPILE=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_LOCK_KERNEL=y
#
# General setup
#
CONFIG_LOCALVERSION=""
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
# CONFIG_POSIX_MQUEUE is not set
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_SYSCTL is not set
# CONFIG_AUDIT is not set
# CONFIG_HOTPLUG is not set
CONFIG_KOBJECT_UEVENT=y
# CONFIG_IKCONFIG is not set
CONFIG_EMBEDDED=y
# CONFIG_KALLSYMS is not set
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_EPOLL=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SHMEM=y
CONFIG_CC_ALIGN_FUNCTIONS=0
CONFIG_CC_ALIGN_LABELS=0
CONFIG_CC_ALIGN_LOOPS=0
CONFIG_CC_ALIGN_JUMPS=0
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0
#
# Loadable module support
#
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
CONFIG_OBSOLETE_MODPARM=y
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
CONFIG_KMOD=y
#
# System Type
#
# CONFIG_ARCH_CLPS7500 is not set
# CONFIG_ARCH_CLPS711X is not set
# CONFIG_ARCH_CO285 is not set
# CONFIG_ARCH_EBSA110 is not set
# CONFIG_ARCH_FOOTBRIDGE is not set
# CONFIG_ARCH_INTEGRATOR is not set
# CONFIG_ARCH_IOP3XX is not set
# CONFIG_ARCH_IXP4XX is not set
# CONFIG_ARCH_IXP2000 is not set
# CONFIG_ARCH_L7200 is not set
# CONFIG_ARCH_PXA is not set
# CONFIG_ARCH_RPC is not set
# CONFIG_ARCH_SA1100 is not set
# CONFIG_ARCH_S3C2410 is not set
# CONFIG_ARCH_SHARK is not set
# CONFIG_ARCH_LH7A40X is not set
# CONFIG_ARCH_OMAP is not set
# CONFIG_ARCH_VERSATILE is not set
CONFIG_ARCH_IMX=y
# CONFIG_ARCH_H720X is not set
#
# IMX Implementations
#
CONFIG_ARCH_MX1ADS=y
#
# Processor Type
#
CONFIG_CPU_ARM920T=y
CONFIG_CPU_32v4=y
CONFIG_CPU_ABRT_EV4T=y
CONFIG_CPU_CACHE_V4WT=y
CONFIG_CPU_CACHE_VIVT=y
CONFIG_CPU_COPY_V4WB=y
CONFIG_CPU_TLB_V4WBI=y
#
# Processor Features
#
# CONFIG_ARM_THUMB is not set
# CONFIG_CPU_ICACHE_DISABLE is not set
# CONFIG_CPU_DCACHE_DISABLE is not set
# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
#
# Bus support
#
CONFIG_ISA=y
#
# PCCARD (PCMCIA/CardBus) support
#
# CONFIG_PCCARD is not set
#
# Kernel Features
#
CONFIG_PREEMPT=y
# CONFIG_LEDS is not set
CONFIG_ALIGNMENT_TRAP=y
#
# Boot options
#
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="console=ttySMX0,57600n8 ip=bootp root=/dev/nfs"
# CONFIG_XIP_KERNEL is not set
#
# Floating point emulation
#
#
# At least one emulation must be selected
#
CONFIG_FPE_NWFPE=y
CONFIG_FPE_NWFPE_XP=y
CONFIG_FPE_FASTFPE=y
#
# Userspace binary formats
#
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_AOUT is not set
# CONFIG_BINFMT_MISC is not set
# CONFIG_ARTHUR is not set
#
# Power management options
#
# CONFIG_PM is not set
#
# Device Drivers
#
#
# Generic Driver Options
#
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
# CONFIG_FW_LOADER is not set
# CONFIG_DEBUG_DRIVER is not set
#
# Memory Technology Devices (MTD)
#
CONFIG_MTD=y
# CONFIG_MTD_DEBUG is not set
# CONFIG_MTD_CONCAT is not set
CONFIG_MTD_PARTITIONS=y
# CONFIG_MTD_REDBOOT_PARTS is not set
# CONFIG_MTD_CMDLINE_PARTS is not set
# CONFIG_MTD_AFS_PARTS is not set
#
# User Modules And Translation Layers
#
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
# CONFIG_INFTL is not set
#
# RAM/ROM/Flash chip drivers
#
# CONFIG_MTD_CFI is not set
# CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_CFI_I4 is not set
# CONFIG_MTD_CFI_I8 is not set
# CONFIG_MTD_RAM is not set
CONFIG_MTD_ROM=y
# CONFIG_MTD_ABSENT is not set
#
# Mapping drivers for chip access
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
#
# Self-contained MTD device drivers
#
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_PHRAM is not set
# CONFIG_MTD_MTDRAM is not set
# CONFIG_MTD_BLKMTD is not set
# CONFIG_MTD_BLOCK2MTD is not set
#
# Disk-On-Chip Device Drivers
#
# CONFIG_MTD_DOC2000 is not set
# CONFIG_MTD_DOC2001 is not set
# CONFIG_MTD_DOC2001PLUS is not set
#
# NAND Flash Device Drivers
#
# CONFIG_MTD_NAND is not set
#
# Parallel port support
#
# CONFIG_PARPORT is not set
#
# Plug and Play support
#
# CONFIG_PNP is not set
#
# Block devices
#
# CONFIG_BLK_DEV_FD is not set
# CONFIG_BLK_DEV_XD is not set
# CONFIG_BLK_DEV_COW_COMMON is not set
CONFIG_BLK_DEV_LOOP=y
# CONFIG_BLK_DEV_CRYPTOLOOP is not set
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_RAM is not set
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_INITRAMFS_SOURCE=""
# CONFIG_CDROM_PKTCDVD is not set
#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
# CONFIG_IOSCHED_AS is not set
CONFIG_IOSCHED_DEADLINE=y
CONFIG_IOSCHED_CFQ=y
# CONFIG_ATA_OVER_ETH is not set
#
# SCSI device support
#
# CONFIG_SCSI is not set
#
# Multi-device support (RAID and LVM)
#
# CONFIG_MD is not set
#
# Fusion MPT device support
#
#
# IEEE 1394 (FireWire) support
#
#
# I2O device support
#
#
# Networking support
#
CONFIG_NET=y
#
# Networking options
#
CONFIG_PACKET=m
CONFIG_PACKET_MMAP=y
# CONFIG_NETLINK_DEV is not set
CONFIG_UNIX=y
# CONFIG_NET_KEY is not set
CONFIG_INET=y
# CONFIG_IP_MULTICAST is not set
# CONFIG_IP_ADVANCED_ROUTER is not set
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
# CONFIG_IP_PNP_RARP is not set
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
# CONFIG_INET_TUNNEL is not set
CONFIG_IP_TCPDIAG=y
# CONFIG_IP_TCPDIAG_IPV6 is not set
# CONFIG_IPV6 is not set
# CONFIG_NETFILTER is not set
#
# SCTP Configuration (EXPERIMENTAL)
#
# CONFIG_IP_SCTP is not set
# CONFIG_ATM is not set
# CONFIG_BRIDGE is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_DECNET is not set
# CONFIG_LLC2 is not set
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_NET_DIVERT is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
#
# QoS and/or fair queueing
#
# CONFIG_NET_SCHED is not set
# CONFIG_NET_CLS_ROUTE is not set
#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
# CONFIG_HAMRADIO is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
CONFIG_NETDEVICES=y
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
#
# ARCnet devices
#
# CONFIG_ARCNET is not set
#
# Ethernet (10 or 100Mbit)
#
CONFIG_NET_ETHERNET=y
CONFIG_MII=y
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_LANCE is not set
# CONFIG_NET_VENDOR_SMC is not set
# CONFIG_SMC91X is not set
# CONFIG_NET_VENDOR_RACAL is not set
# CONFIG_AT1700 is not set
# CONFIG_DEPCA is not set
# CONFIG_HP100 is not set
# CONFIG_NET_ISA is not set
# CONFIG_NET_PCI is not set
# CONFIG_NET_POCKET is not set
#
# Ethernet (1000 Mbit)
#
#
# Ethernet (10000 Mbit)
#
#
# Token Ring devices
#
# CONFIG_TR is not set
#
# Wireless LAN (non-hamradio)
#
# CONFIG_NET_RADIO is not set
#
# Wan interfaces
#
# CONFIG_WAN is not set
CONFIG_PPP=y
# CONFIG_PPP_MULTILINK is not set
CONFIG_PPP_FILTER=y
CONFIG_PPP_ASYNC=y
# CONFIG_PPP_SYNC_TTY is not set
CONFIG_PPP_DEFLATE=y
CONFIG_PPP_BSDCOMP=y
# CONFIG_PPPOE is not set
# CONFIG_SLIP is not set
# CONFIG_SHAPER is not set
# CONFIG_NETCONSOLE is not set
#
# ISDN subsystem
#
# CONFIG_ISDN is not set
#
# Input device support
#
# CONFIG_INPUT is not set
#
# Hardware I/O ports
#
# CONFIG_SERIO is not set
# CONFIG_GAMEPORT is not set
CONFIG_SOUND_GAMEPORT=y
#
# Character devices
#
# CONFIG_VT is not set
# CONFIG_SERIAL_NONSTANDARD is not set
#
# Serial drivers
#
# CONFIG_SERIAL_8250 is not set
#
# Non-8250 serial port support
#
CONFIG_SERIAL_IMX=y
CONFIG_SERIAL_IMX_CONSOLE=y
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y
# CONFIG_LEGACY_PTYS is not set
#
# IPMI
#
# CONFIG_IPMI_HANDLER is not set
#
# Watchdog Cards
#
# CONFIG_WATCHDOG is not set
# CONFIG_NVRAM is not set
CONFIG_RTC=m
# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
#
# Ftape, the floppy tape device driver
#
# CONFIG_DRM is not set
# CONFIG_RAW_DRIVER is not set
#
# TPM devices
#
# CONFIG_TCG_TPM is not set
#
# I2C support
#
# CONFIG_I2C is not set
#
# Misc devices
#
#
# Multimedia devices
#
# CONFIG_VIDEO_DEV is not set
#
# Digital Video Broadcasting Devices
#
# CONFIG_DVB is not set
#
# Graphics support
#
# CONFIG_FB is not set
#
# Sound
#
# CONFIG_SOUND is not set
#
# USB support
#
CONFIG_USB_ARCH_HAS_HCD=y
# CONFIG_USB_ARCH_HAS_OHCI is not set
# CONFIG_USB is not set
#
# USB Gadget Support
#
# CONFIG_USB_GADGET is not set
#
# MMC/SD Card support
#
# CONFIG_MMC is not set
#
# File systems
#
# CONFIG_EXT2_FS is not set
# CONFIG_EXT3_FS is not set
# CONFIG_JBD is not set
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
#
# XFS support
#
# CONFIG_XFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_ROMFS_FS is not set
# CONFIG_QUOTA is not set
CONFIG_DNOTIFY=y
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set
#
# DOS/FAT/NT Filesystems
#
CONFIG_FAT_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
# CONFIG_NTFS_FS is not set
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_SYSFS=y
CONFIG_DEVFS_FS=y
CONFIG_DEVFS_MOUNT=y
# CONFIG_DEVFS_DEBUG is not set
# CONFIG_DEVPTS_FS_XATTR is not set
CONFIG_TMPFS=y
# CONFIG_TMPFS_XATTR is not set
# CONFIG_HUGETLB_PAGE is not set
CONFIG_RAMFS=y
#
# Miscellaneous filesystems
#
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_HFSPLUS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_JFFS_FS is not set
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_FS_DEBUG=0
# CONFIG_JFFS2_FS_NAND is not set
# CONFIG_JFFS2_FS_NOR_ECC is not set
# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
CONFIG_JFFS2_ZLIB=y
CONFIG_JFFS2_RTIME=y
# CONFIG_JFFS2_RUBIN is not set
CONFIG_CRAMFS=y
# CONFIG_VXFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
#
# Network File Systems
#
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
# CONFIG_NFS_V4 is not set
# CONFIG_NFS_DIRECTIO is not set
# CONFIG_NFSD is not set
CONFIG_ROOT_NFS=y
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
CONFIG_SUNRPC=y
# CONFIG_RPCSEC_GSS_KRB5 is not set
# CONFIG_RPCSEC_GSS_SPKM3 is not set
# CONFIG_SMB_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
#
# Native Language Support
#
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="iso8859-1"
# CONFIG_NLS_CODEPAGE_437 is not set
# CONFIG_NLS_CODEPAGE_737 is not set
# CONFIG_NLS_CODEPAGE_775 is not set
# CONFIG_NLS_CODEPAGE_850 is not set
# CONFIG_NLS_CODEPAGE_852 is not set
# CONFIG_NLS_CODEPAGE_855 is not set
# CONFIG_NLS_CODEPAGE_857 is not set
# CONFIG_NLS_CODEPAGE_860 is not set
# CONFIG_NLS_CODEPAGE_861 is not set
# CONFIG_NLS_CODEPAGE_862 is not set
# CONFIG_NLS_CODEPAGE_863 is not set
# CONFIG_NLS_CODEPAGE_864 is not set
# CONFIG_NLS_CODEPAGE_865 is not set
# CONFIG_NLS_CODEPAGE_866 is not set
# CONFIG_NLS_CODEPAGE_869 is not set
# CONFIG_NLS_CODEPAGE_936 is not set
# CONFIG_NLS_CODEPAGE_950 is not set
# CONFIG_NLS_CODEPAGE_932 is not set
# CONFIG_NLS_CODEPAGE_949 is not set
# CONFIG_NLS_CODEPAGE_874 is not set
# CONFIG_NLS_ISO8859_8 is not set
# CONFIG_NLS_CODEPAGE_1250 is not set
# CONFIG_NLS_CODEPAGE_1251 is not set
# CONFIG_NLS_ASCII is not set
# CONFIG_NLS_ISO8859_1 is not set
# CONFIG_NLS_ISO8859_2 is not set
# CONFIG_NLS_ISO8859_3 is not set
# CONFIG_NLS_ISO8859_4 is not set
# CONFIG_NLS_ISO8859_5 is not set
# CONFIG_NLS_ISO8859_6 is not set
# CONFIG_NLS_ISO8859_7 is not set
# CONFIG_NLS_ISO8859_9 is not set
# CONFIG_NLS_ISO8859_13 is not set
# CONFIG_NLS_ISO8859_14 is not set
# CONFIG_NLS_ISO8859_15 is not set
# CONFIG_NLS_KOI8_R is not set
# CONFIG_NLS_KOI8_U is not set
# CONFIG_NLS_UTF8 is not set
#
# Profiling support
#
# CONFIG_PROFILING is not set
#
# Kernel hacking
#
# CONFIG_PRINTK_TIME is not set
CONFIG_DEBUG_KERNEL=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_SCHEDSTATS is not set
# CONFIG_DEBUG_SLAB is not set
CONFIG_DEBUG_PREEMPT=y
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
# CONFIG_DEBUG_KOBJECT is not set
CONFIG_DEBUG_BUGVERBOSE=y
CONFIG_DEBUG_INFO=y
# CONFIG_DEBUG_FS is not set
CONFIG_FRAME_POINTER=y
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_ERRORS=y
# CONFIG_DEBUG_LL is not set
#
# Security options
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
#
# Cryptographic options
#
CONFIG_CRYPTO=y
# CONFIG_CRYPTO_HMAC is not set
# CONFIG_CRYPTO_NULL is not set
# CONFIG_CRYPTO_MD4 is not set
# CONFIG_CRYPTO_MD5 is not set
# CONFIG_CRYPTO_SHA1 is not set
# CONFIG_CRYPTO_SHA256 is not set
# CONFIG_CRYPTO_SHA512 is not set
# CONFIG_CRYPTO_WP512 is not set
# CONFIG_CRYPTO_TGR192 is not set
# CONFIG_CRYPTO_DES is not set
# CONFIG_CRYPTO_BLOWFISH is not set
# CONFIG_CRYPTO_TWOFISH is not set
# CONFIG_CRYPTO_SERPENT is not set
# CONFIG_CRYPTO_AES is not set
# CONFIG_CRYPTO_CAST5 is not set
# CONFIG_CRYPTO_CAST6 is not set
# CONFIG_CRYPTO_TEA is not set
# CONFIG_CRYPTO_ARC4 is not set
# CONFIG_CRYPTO_KHAZAD is not set
# CONFIG_CRYPTO_ANUBIS is not set
# CONFIG_CRYPTO_DEFLATE is not set
# CONFIG_CRYPTO_MICHAEL_MIC is not set
# CONFIG_CRYPTO_CRC32C is not set
# CONFIG_CRYPTO_TEST is not set
#
# Hardware crypto devices
#
#
# Library routines
#
CONFIG_CRC_CCITT=y
CONFIG_CRC32=y
# CONFIG_LIBCRC32C is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
arch/arm/configs/mx27_defconfig
浏览文件 @ b93a4afc
...@@ -200,7 +200,7 @@ CONFIG_MACH_MX27ADS=y ...@@ -200,7 +200,7 @@ CONFIG_MACH_MX27ADS=y
CONFIG_MACH_PCM038=y CONFIG_MACH_PCM038=y
CONFIG_MACH_PCM970_BASEBOARD=y CONFIG_MACH_PCM970_BASEBOARD=y
CONFIG_MACH_MX27_3DS=y CONFIG_MACH_MX27_3DS=y
CONFIG_MACH_MX27LITE=y CONFIG_MACH_IMX27LITE=y
CONFIG_MXC_IRQ_PRIOR=y CONFIG_MXC_IRQ_PRIOR=y
CONFIG_MXC_PWM=y CONFIG_MXC_PWM=y
......
arch/arm/configs/mx51_defconfig 0 → 100644
浏览文件 @ b93a4afc
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.33-rc6
# Tue Feb 2 15:20:48 2010
#
CONFIG_ARM=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_GENERIC_GPIO=y
CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_HAVE_LATENCYTOP_SUPPORT=y
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_ARCH_MTD_XIP=y
CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
CONFIG_VECTORS_BASE=0xffff0000
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
CONFIG_CONSTRUCTORS=y
#
# General setup
#
CONFIG_EXPERIMENTAL=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_LOCALVERSION=""
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_HAVE_KERNEL_GZIP=y
CONFIG_HAVE_KERNEL_LZO=y
CONFIG_KERNEL_GZIP=y
# CONFIG_KERNEL_BZIP2 is not set
# CONFIG_KERNEL_LZMA is not set
# CONFIG_KERNEL_LZO is not set
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
# CONFIG_POSIX_MQUEUE is not set
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_TASKSTATS is not set
# CONFIG_AUDIT is not set
#
# RCU Subsystem
#
CONFIG_TREE_RCU=y
# CONFIG_TREE_PREEMPT_RCU is not set
# CONFIG_TINY_RCU is not set
# CONFIG_RCU_TRACE is not set
CONFIG_RCU_FANOUT=32
# CONFIG_RCU_FANOUT_EXACT is not set
# CONFIG_TREE_RCU_TRACE is not set
# CONFIG_IKCONFIG is not set
CONFIG_LOG_BUF_SHIFT=18
# CONFIG_GROUP_SCHED is not set
# CONFIG_CGROUPS is not set
# CONFIG_SYSFS_DEPRECATED_V2 is not set
CONFIG_RELAY=y
# CONFIG_NAMESPACES is not set
# CONFIG_BLK_DEV_INITRD is not set
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SYSCTL=y
CONFIG_ANON_INODES=y
CONFIG_EMBEDDED=y
CONFIG_UID16=y
CONFIG_SYSCTL_SYSCALL=y
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_ALL is not set
# CONFIG_KALLSYMS_EXTRA_PASS is not set
CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_AIO=y
#
# Kernel Performance Events And Counters
#
CONFIG_VM_EVENT_COUNTERS=y
# CONFIG_SLUB_DEBUG is not set
# CONFIG_COMPAT_BRK is not set
# CONFIG_SLAB is not set
CONFIG_SLUB=y
# CONFIG_SLOB is not set
# CONFIG_PROFILING is not set
CONFIG_HAVE_OPROFILE=y
# CONFIG_KPROBES is not set
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_HAVE_CLK=y
#
# GCOV-based kernel profiling
#
# CONFIG_GCOV_KERNEL is not set
# CONFIG_SLOW_WORK is not set
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
# CONFIG_MODULE_FORCE_LOAD is not set
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
CONFIG_MODVERSIONS=y
CONFIG_MODULE_SRCVERSION_ALL=y
CONFIG_BLOCK=y
# CONFIG_LBDAF is not set
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_BLK_DEV_INTEGRITY is not set
#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_DEADLINE=y
CONFIG_IOSCHED_CFQ=y
# CONFIG_DEFAULT_DEADLINE is not set
CONFIG_DEFAULT_CFQ=y
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="cfq"
# CONFIG_INLINE_SPIN_TRYLOCK is not set
# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
# CONFIG_INLINE_SPIN_LOCK is not set
# CONFIG_INLINE_SPIN_LOCK_BH is not set
# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
CONFIG_INLINE_SPIN_UNLOCK=y
# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
# CONFIG_INLINE_READ_TRYLOCK is not set
# CONFIG_INLINE_READ_LOCK is not set
# CONFIG_INLINE_READ_LOCK_BH is not set
# CONFIG_INLINE_READ_LOCK_IRQ is not set
# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
CONFIG_INLINE_READ_UNLOCK=y
# CONFIG_INLINE_READ_UNLOCK_BH is not set
CONFIG_INLINE_READ_UNLOCK_IRQ=y
# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
# CONFIG_INLINE_WRITE_TRYLOCK is not set
# CONFIG_INLINE_WRITE_LOCK is not set
# CONFIG_INLINE_WRITE_LOCK_BH is not set
# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
CONFIG_INLINE_WRITE_UNLOCK=y
# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
# CONFIG_MUTEX_SPIN_ON_OWNER is not set
CONFIG_FREEZER=y
#
# System Type
#
CONFIG_MMU=y
# CONFIG_ARCH_AAEC2000 is not set
# CONFIG_ARCH_INTEGRATOR is not set
# CONFIG_ARCH_REALVIEW is not set
# CONFIG_ARCH_VERSATILE is not set
# CONFIG_ARCH_AT91 is not set
# CONFIG_ARCH_CLPS711X is not set
# CONFIG_ARCH_GEMINI is not set
# CONFIG_ARCH_EBSA110 is not set
# CONFIG_ARCH_EP93XX is not set
# CONFIG_ARCH_FOOTBRIDGE is not set
CONFIG_ARCH_MXC=y
# CONFIG_ARCH_STMP3XXX is not set
# CONFIG_ARCH_NETX is not set
# CONFIG_ARCH_H720X is not set
# CONFIG_ARCH_NOMADIK is not set
# CONFIG_ARCH_IOP13XX is not set
# CONFIG_ARCH_IOP32X is not set
# CONFIG_ARCH_IOP33X is not set
# CONFIG_ARCH_IXP23XX is not set
# CONFIG_ARCH_IXP2000 is not set
# CONFIG_ARCH_IXP4XX is not set
# CONFIG_ARCH_L7200 is not set
# CONFIG_ARCH_DOVE is not set
# CONFIG_ARCH_KIRKWOOD is not set
# CONFIG_ARCH_LOKI is not set
# CONFIG_ARCH_MV78XX0 is not set
# CONFIG_ARCH_ORION5X is not set
# CONFIG_ARCH_MMP is not set
# CONFIG_ARCH_KS8695 is not set
# CONFIG_ARCH_NS9XXX is not set
# CONFIG_ARCH_W90X900 is not set
# CONFIG_ARCH_PNX4008 is not set
# CONFIG_ARCH_PXA is not set
# CONFIG_ARCH_MSM is not set
# CONFIG_ARCH_RPC is not set
# CONFIG_ARCH_SA1100 is not set
# CONFIG_ARCH_S3C2410 is not set
# CONFIG_ARCH_S3C64XX is not set
# CONFIG_ARCH_S5PC1XX is not set
# CONFIG_ARCH_SHARK is not set
# CONFIG_ARCH_LH7A40X is not set
# CONFIG_ARCH_U300 is not set
# CONFIG_ARCH_DAVINCI is not set
# CONFIG_ARCH_OMAP is not set
# CONFIG_ARCH_BCMRING is not set
# CONFIG_ARCH_U8500 is not set
#
# Freescale MXC Implementations
#
# CONFIG_ARCH_MX1 is not set
# CONFIG_ARCH_MX2 is not set
# CONFIG_ARCH_MX25 is not set
# CONFIG_ARCH_MX3 is not set
# CONFIG_ARCH_MXC91231 is not set
CONFIG_ARCH_MX5=y
CONFIG_ARCH_MX51=y
#
# MX5 platforms:
#
CONFIG_MACH_MX51_BABBAGE=y
# CONFIG_MXC_IRQ_PRIOR is not set
CONFIG_MXC_TZIC=y
# CONFIG_MXC_PWM is not set
CONFIG_ARCH_MXC_IOMUX_V3=y
#
# Processor Type
#
CONFIG_CPU_32v6K=y
CONFIG_CPU_V7=y
CONFIG_CPU_32v7=y
CONFIG_CPU_ABRT_EV7=y
CONFIG_CPU_PABRT_V7=y
CONFIG_CPU_CACHE_V7=y
CONFIG_CPU_CACHE_VIPT=y
CONFIG_CPU_COPY_V6=y
CONFIG_CPU_TLB_V7=y
CONFIG_CPU_HAS_ASID=y
CONFIG_CPU_CP15=y
CONFIG_CPU_CP15_MMU=y
#
# Processor Features
#
CONFIG_ARM_THUMB=y
# CONFIG_ARM_THUMBEE is not set
# CONFIG_CPU_ICACHE_DISABLE is not set
# CONFIG_CPU_DCACHE_DISABLE is not set
# CONFIG_CPU_BPREDICT_DISABLE is not set
CONFIG_HAS_TLS_REG=y
CONFIG_ARM_L1_CACHE_SHIFT=5
# CONFIG_ARM_ERRATA_430973 is not set
# CONFIG_ARM_ERRATA_458693 is not set
# CONFIG_ARM_ERRATA_460075 is not set
CONFIG_COMMON_CLKDEV=y
#
# Bus support
#
# CONFIG_PCI_SYSCALL is not set
# CONFIG_ARCH_SUPPORTS_MSI is not set
# CONFIG_PCCARD is not set
#
# Kernel Features
#
CONFIG_TICK_ONESHOT=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
CONFIG_VMSPLIT_3G=y
# CONFIG_VMSPLIT_2G is not set
# CONFIG_VMSPLIT_1G is not set
CONFIG_PAGE_OFFSET=0xC0000000
# CONFIG_PREEMPT_NONE is not set
CONFIG_PREEMPT_VOLUNTARY=y
# CONFIG_PREEMPT is not set
CONFIG_HZ=100
# CONFIG_THUMB2_KERNEL is not set
CONFIG_AEABI=y
# CONFIG_OABI_COMPAT is not set
# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
# CONFIG_HIGHMEM is not set
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
# CONFIG_DISCONTIGMEM_MANUAL is not set
# CONFIG_SPARSEMEM_MANUAL is not set
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
CONFIG_PAGEFLAGS_EXTENDED=y
CONFIG_SPLIT_PTLOCK_CPUS=4
# CONFIG_PHYS_ADDR_T_64BIT is not set
CONFIG_ZONE_DMA_FLAG=0
CONFIG_VIRT_TO_BUS=y
# CONFIG_KSM is not set
CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
CONFIG_ALIGNMENT_TRAP=y
# CONFIG_UACCESS_WITH_MEMCPY is not set
#
# Boot options
#
CONFIG_ZBOOT_ROM_TEXT=0
CONFIG_ZBOOT_ROM_BSS=0
CONFIG_CMDLINE="noinitrd console=ttymxc0,115200 root=/dev/nfs nfsroot=192.168.0.101:/shared/nfs ip=dhcp"
# CONFIG_XIP_KERNEL is not set
# CONFIG_KEXEC is not set
#
# CPU Power Management
#
# CONFIG_CPU_IDLE is not set
#
# Floating point emulation
#
#
# At least one emulation must be selected
#
CONFIG_VFP=y
CONFIG_VFPv3=y
CONFIG_NEON=y
#
# Userspace binary formats
#
CONFIG_BINFMT_ELF=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_HAVE_AOUT=y
# CONFIG_BINFMT_AOUT is not set
CONFIG_BINFMT_MISC=m
#
# Power management options
#
CONFIG_PM=y
CONFIG_PM_DEBUG=y
# CONFIG_PM_VERBOSE is not set
CONFIG_CAN_PM_TRACE=y
CONFIG_PM_SLEEP=y
CONFIG_SUSPEND=y
CONFIG_PM_TEST_SUSPEND=y
CONFIG_SUSPEND_FREEZER=y
# CONFIG_APM_EMULATION is not set
# CONFIG_PM_RUNTIME is not set
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_NET=y
#
# Networking options
#
CONFIG_PACKET=y
CONFIG_PACKET_MMAP=y
CONFIG_UNIX=y
# CONFIG_NET_KEY is not set
CONFIG_INET=y
# CONFIG_IP_MULTICAST is not set
# CONFIG_IP_ADVANCED_ROUTER is not set
CONFIG_IP_FIB_HASH=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
# CONFIG_IP_PNP_BOOTP is not set
# CONFIG_IP_PNP_RARP is not set
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
# CONFIG_INET_XFRM_TUNNEL is not set
# CONFIG_INET_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
# CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_TCP_CONG_CUBIC=y
CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_TCP_MD5SIG is not set
# CONFIG_IPV6 is not set
# CONFIG_NETWORK_SECMARK is not set
# CONFIG_NETFILTER is not set
# CONFIG_IP_DCCP is not set
# CONFIG_IP_SCTP is not set
# CONFIG_RDS is not set
# CONFIG_TIPC is not set
# CONFIG_ATM is not set
# CONFIG_BRIDGE is not set
# CONFIG_NET_DSA is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_DECNET is not set
# CONFIG_LLC2 is not set
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
# CONFIG_PHONET is not set
# CONFIG_IEEE802154 is not set
# CONFIG_NET_SCHED is not set
# CONFIG_DCB is not set
#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
# CONFIG_HAMRADIO is not set
# CONFIG_CAN is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
# CONFIG_AF_RXRPC is not set
# CONFIG_WIRELESS is not set
# CONFIG_WIMAX is not set
# CONFIG_RFKILL is not set
# CONFIG_NET_9P is not set
#
# Device Drivers
#
#
# Generic Driver Options
#
CONFIG_UEVENT_HELPER_PATH=""
# CONFIG_STANDALONE is not set
CONFIG_PREVENT_FIRMWARE_BUILD=y
CONFIG_FW_LOADER=y
CONFIG_FIRMWARE_IN_KERNEL=y
CONFIG_EXTRA_FIRMWARE=""
# CONFIG_DEBUG_DRIVER is not set
# CONFIG_DEBUG_DEVRES is not set
# CONFIG_SYS_HYPERVISOR is not set
CONFIG_CONNECTOR=y
CONFIG_PROC_EVENTS=y
# CONFIG_MTD is not set
# CONFIG_PARPORT is not set
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_COW_COMMON is not set
CONFIG_BLK_DEV_LOOP=y
# CONFIG_BLK_DEV_CRYPTOLOOP is not set
# CONFIG_BLK_DEV_DRBD is not set
# CONFIG_BLK_DEV_NBD is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=65536
# CONFIG_BLK_DEV_XIP is not set
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
# CONFIG_MG_DISK is not set
# CONFIG_MISC_DEVICES is not set
CONFIG_HAVE_IDE=y
# CONFIG_IDE is not set
#
# SCSI device support
#
# CONFIG_RAID_ATTRS is not set
CONFIG_SCSI=y
CONFIG_SCSI_DMA=y
# CONFIG_SCSI_TGT is not set
# CONFIG_SCSI_NETLINK is not set
# CONFIG_SCSI_PROC_FS is not set
#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=y
# CONFIG_CHR_DEV_ST is not set
# CONFIG_CHR_DEV_OSST is not set
# CONFIG_BLK_DEV_SR is not set
# CONFIG_CHR_DEV_SG is not set
# CONFIG_CHR_DEV_SCH is not set
CONFIG_SCSI_MULTI_LUN=y
CONFIG_SCSI_CONSTANTS=y
CONFIG_SCSI_LOGGING=y
CONFIG_SCSI_SCAN_ASYNC=y
CONFIG_SCSI_WAIT_SCAN=m
#
# SCSI Transports
#
# CONFIG_SCSI_SPI_ATTRS is not set
# CONFIG_SCSI_FC_ATTRS is not set
# CONFIG_SCSI_ISCSI_ATTRS is not set
# CONFIG_SCSI_SAS_LIBSAS is not set
# CONFIG_SCSI_SRP_ATTRS is not set
# CONFIG_SCSI_LOWLEVEL is not set
# CONFIG_SCSI_DH is not set
# CONFIG_SCSI_OSD_INITIATOR is not set
CONFIG_ATA=m
# CONFIG_ATA_NONSTANDARD is not set
CONFIG_ATA_VERBOSE_ERROR=y
CONFIG_SATA_PMP=y
CONFIG_ATA_SFF=y
# CONFIG_SATA_MV is not set
# CONFIG_PATA_PLATFORM is not set
# CONFIG_MD is not set
CONFIG_NETDEVICES=y
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
# CONFIG_MACVLAN is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
# CONFIG_VETH is not set
CONFIG_PHYLIB=y
#
# MII PHY device drivers
#
CONFIG_MARVELL_PHY=y
CONFIG_DAVICOM_PHY=y
CONFIG_QSEMI_PHY=y
CONFIG_LXT_PHY=y
CONFIG_CICADA_PHY=y
CONFIG_VITESSE_PHY=y
CONFIG_SMSC_PHY=y
CONFIG_BROADCOM_PHY=y
CONFIG_ICPLUS_PHY=y
CONFIG_REALTEK_PHY=y
CONFIG_NATIONAL_PHY=y
CONFIG_STE10XP=y
CONFIG_LSI_ET1011C_PHY=y
CONFIG_FIXED_PHY=y
CONFIG_MDIO_BITBANG=y
CONFIG_MDIO_GPIO=y
CONFIG_NET_ETHERNET=y
CONFIG_MII=m
# CONFIG_AX88796 is not set
# CONFIG_SMC91X is not set
# CONFIG_DM9000 is not set
# CONFIG_ETHOC is not set
# CONFIG_SMC911X is not set
# CONFIG_SMSC911X is not set
# CONFIG_DNET is not set
# CONFIG_IBM_NEW_EMAC_ZMII is not set
# CONFIG_IBM_NEW_EMAC_RGMII is not set
# CONFIG_IBM_NEW_EMAC_TAH is not set
# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
# CONFIG_B44 is not set
# CONFIG_KS8842 is not set
# CONFIG_KS8851_MLL is not set
CONFIG_FEC=y
# CONFIG_FEC2 is not set
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
# CONFIG_WLAN is not set
#
# Enable WiMAX (Networking options) to see the WiMAX drivers
#
# CONFIG_WAN is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
# CONFIG_NETCONSOLE is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
# CONFIG_ISDN is not set
# CONFIG_PHONE is not set
#
# Input device support
#
CONFIG_INPUT=y
CONFIG_INPUT_FF_MEMLESS=m
# CONFIG_INPUT_POLLDEV is not set
# CONFIG_INPUT_SPARSEKMAP is not set
#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=y
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
# CONFIG_INPUT_JOYDEV is not set
CONFIG_INPUT_EVDEV=y
CONFIG_INPUT_EVBUG=m
#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
# CONFIG_KEYBOARD_ADP5588 is not set
CONFIG_KEYBOARD_ATKBD=y
# CONFIG_QT2160 is not set
# CONFIG_KEYBOARD_LKKBD is not set
# CONFIG_KEYBOARD_GPIO is not set
# CONFIG_KEYBOARD_MATRIX is not set
# CONFIG_KEYBOARD_LM8323 is not set
# CONFIG_KEYBOARD_MAX7359 is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_KEYBOARD_OPENCORES is not set
# CONFIG_KEYBOARD_STOWAWAY is not set
# CONFIG_KEYBOARD_SUNKBD is not set
# CONFIG_KEYBOARD_XTKBD is not set
CONFIG_INPUT_MOUSE=y
CONFIG_MOUSE_PS2=m
CONFIG_MOUSE_PS2_ALPS=y
CONFIG_MOUSE_PS2_LOGIPS2PP=y
CONFIG_MOUSE_PS2_SYNAPTICS=y
CONFIG_MOUSE_PS2_TRACKPOINT=y
CONFIG_MOUSE_PS2_ELANTECH=y
# CONFIG_MOUSE_PS2_SENTELIC is not set
# CONFIG_MOUSE_PS2_TOUCHKIT is not set
# CONFIG_MOUSE_SERIAL is not set
# CONFIG_MOUSE_VSXXXAA is not set
# CONFIG_MOUSE_GPIO is not set
# CONFIG_MOUSE_SYNAPTICS_I2C is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TABLET is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_MISC is not set
#
# Hardware I/O ports
#
CONFIG_SERIO=y
CONFIG_SERIO_SERPORT=m
CONFIG_SERIO_LIBPS2=y
# CONFIG_SERIO_RAW is not set
# CONFIG_SERIO_ALTERA_PS2 is not set
# CONFIG_GAMEPORT is not set
#
# Character devices
#
CONFIG_VT=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_VT_CONSOLE=y
CONFIG_HW_CONSOLE=y
CONFIG_VT_HW_CONSOLE_BINDING=y
# CONFIG_DEVKMEM is not set
# CONFIG_SERIAL_NONSTANDARD is not set
#
# Serial drivers
#
# CONFIG_SERIAL_8250 is not set
#
# Non-8250 serial port support
#
CONFIG_SERIAL_IMX=y
CONFIG_SERIAL_IMX_CONSOLE=y
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y
# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
# CONFIG_LEGACY_PTYS is not set
# CONFIG_IPMI_HANDLER is not set
CONFIG_HW_RANDOM=y
# CONFIG_HW_RANDOM_TIMERIOMEM is not set
# CONFIG_R3964 is not set
# CONFIG_RAW_DRIVER is not set
# CONFIG_TCG_TPM is not set
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
# CONFIG_I2C_COMPAT is not set
CONFIG_I2C_CHARDEV=m
# CONFIG_I2C_HELPER_AUTO is not set
#
# I2C Algorithms
#
CONFIG_I2C_ALGOBIT=m
CONFIG_I2C_ALGOPCF=m
CONFIG_I2C_ALGOPCA=m
#
# I2C Hardware Bus support
#
#
# I2C system bus drivers (mostly embedded / system-on-chip)
#
# CONFIG_I2C_DESIGNWARE is not set
# CONFIG_I2C_GPIO is not set
# CONFIG_I2C_IMX is not set
# CONFIG_I2C_OCORES is not set
# CONFIG_I2C_SIMTEC is not set
#
# External I2C/SMBus adapter drivers
#
# CONFIG_I2C_PARPORT_LIGHT is not set
# CONFIG_I2C_TAOS_EVM is not set
#
# Other I2C/SMBus bus drivers
#
# CONFIG_I2C_PCA_PLATFORM is not set
# CONFIG_I2C_STUB is not set
#
# Miscellaneous I2C Chip support
#
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# CONFIG_I2C_DEBUG_CHIP is not set
# CONFIG_SPI is not set
#
# PPS support
#
# CONFIG_PPS is not set
CONFIG_ARCH_REQUIRE_GPIOLIB=y
CONFIG_GPIOLIB=y
# CONFIG_DEBUG_GPIO is not set
CONFIG_GPIO_SYSFS=y
#
# Memory mapped GPIO expanders:
#
#
# I2C GPIO expanders:
#
# CONFIG_GPIO_MAX732X is not set
# CONFIG_GPIO_PCA953X is not set
# CONFIG_GPIO_PCF857X is not set
# CONFIG_GPIO_ADP5588 is not set
#
# PCI GPIO expanders:
#
#
# SPI GPIO expanders:
#
#
# AC97 GPIO expanders:
#
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
# CONFIG_HWMON is not set
# CONFIG_THERMAL is not set
# CONFIG_WATCHDOG is not set
CONFIG_SSB_POSSIBLE=y
#
# Sonics Silicon Backplane
#
# CONFIG_SSB is not set
#
# Multifunction device drivers
#
# CONFIG_MFD_CORE is not set
# CONFIG_MFD_SM501 is not set
# CONFIG_MFD_ASIC3 is not set
# CONFIG_HTC_EGPIO is not set
# CONFIG_HTC_PASIC3 is not set
# CONFIG_TPS65010 is not set
# CONFIG_TWL4030_CORE is not set
# CONFIG_MFD_TMIO is not set
# CONFIG_MFD_T7L66XB is not set
# CONFIG_MFD_TC6387XB is not set
# CONFIG_MFD_TC6393XB is not set
# CONFIG_PMIC_DA903X is not set
# CONFIG_PMIC_ADP5520 is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM831X is not set
# CONFIG_MFD_WM8350_I2C is not set
# CONFIG_MFD_PCF50633 is not set
# CONFIG_AB3100_CORE is not set
# CONFIG_MFD_88PM8607 is not set
# CONFIG_REGULATOR is not set
# CONFIG_MEDIA_SUPPORT is not set
#
# Graphics support
#
# CONFIG_VGASTATE is not set
# CONFIG_VIDEO_OUTPUT_CONTROL is not set
# CONFIG_FB is not set
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
#
# Display device support
#
# CONFIG_DISPLAY_SUPPORT is not set
#
# Console display driver support
#
# CONFIG_VGA_CONSOLE is not set
CONFIG_DUMMY_CONSOLE=y
# CONFIG_SOUND is not set
# CONFIG_HID_SUPPORT is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_MMC=y
# CONFIG_MMC_DEBUG is not set
# CONFIG_MMC_UNSAFE_RESUME is not set
#
# MMC/SD/SDIO Card Drivers
#
CONFIG_MMC_BLOCK=m
CONFIG_MMC_BLOCK_BOUNCE=y
# CONFIG_SDIO_UART is not set
# CONFIG_MMC_TEST is not set
#
# MMC/SD/SDIO Host Controller Drivers
#
CONFIG_MMC_SDHCI=m
# CONFIG_MMC_SDHCI_PLTFM is not set
# CONFIG_MMC_AT91 is not set
# CONFIG_MMC_ATMELMCI is not set
# CONFIG_MMC_MXC is not set
# CONFIG_MEMSTICK is not set
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=m
#
# LED drivers
#
# CONFIG_LEDS_PCA9532 is not set
# CONFIG_LEDS_GPIO is not set
# CONFIG_LEDS_LP3944 is not set
# CONFIG_LEDS_PCA955X is not set
# CONFIG_LEDS_BD2802 is not set
# CONFIG_LEDS_LT3593 is not set
#
# LED Triggers
#
# CONFIG_LEDS_TRIGGERS is not set
# CONFIG_ACCESSIBILITY is not set
CONFIG_RTC_LIB=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_HCTOSYS=y
CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
# CONFIG_RTC_DEBUG is not set
#
# RTC interfaces
#
CONFIG_RTC_INTF_SYSFS=y
CONFIG_RTC_INTF_PROC=y
CONFIG_RTC_INTF_DEV=y
CONFIG_RTC_INTF_DEV_UIE_EMUL=y
# CONFIG_RTC_DRV_TEST is not set
#
# I2C RTC drivers
#
# CONFIG_RTC_DRV_DS1307 is not set
# CONFIG_RTC_DRV_DS1374 is not set
# CONFIG_RTC_DRV_DS1672 is not set
# CONFIG_RTC_DRV_MAX6900 is not set
# CONFIG_RTC_DRV_RS5C372 is not set
# CONFIG_RTC_DRV_ISL1208 is not set
# CONFIG_RTC_DRV_X1205 is not set
# CONFIG_RTC_DRV_PCF8563 is not set
# CONFIG_RTC_DRV_PCF8583 is not set
# CONFIG_RTC_DRV_M41T80 is not set
# CONFIG_RTC_DRV_BQ32K is not set
# CONFIG_RTC_DRV_S35390A is not set
# CONFIG_RTC_DRV_FM3130 is not set
# CONFIG_RTC_DRV_RX8581 is not set
# CONFIG_RTC_DRV_RX8025 is not set
#
# SPI RTC drivers
#
#
# Platform RTC drivers
#
# CONFIG_RTC_DRV_CMOS is not set
# CONFIG_RTC_DRV_DS1286 is not set
# CONFIG_RTC_DRV_DS1511 is not set
# CONFIG_RTC_DRV_DS1553 is not set
# CONFIG_RTC_DRV_DS1742 is not set
# CONFIG_RTC_DRV_STK17TA8 is not set
# CONFIG_RTC_DRV_M48T86 is not set
# CONFIG_RTC_DRV_M48T35 is not set
# CONFIG_RTC_DRV_M48T59 is not set
# CONFIG_RTC_DRV_MSM6242 is not set
# CONFIG_RTC_MXC is not set
# CONFIG_RTC_DRV_BQ4802 is not set
# CONFIG_RTC_DRV_RP5C01 is not set
# CONFIG_RTC_DRV_V3020 is not set
#
# on-CPU RTC drivers
#
# CONFIG_DMADEVICES is not set
# CONFIG_AUXDISPLAY is not set
# CONFIG_UIO is not set
#
# TI VLYNQ
#
# CONFIG_STAGING is not set
#
# File systems
#
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_POSIX_ACL=y
CONFIG_EXT2_FS_SECURITY=y
# CONFIG_EXT2_FS_XIP is not set
CONFIG_EXT3_FS=y
CONFIG_EXT3_DEFAULTS_TO_ORDERED=y
CONFIG_EXT3_FS_XATTR=y
CONFIG_EXT3_FS_POSIX_ACL=y
CONFIG_EXT3_FS_SECURITY=y
CONFIG_EXT4_FS=y
CONFIG_EXT4_FS_XATTR=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y
# CONFIG_EXT4_DEBUG is not set
CONFIG_JBD=y
# CONFIG_JBD_DEBUG is not set
CONFIG_JBD2=y
# CONFIG_JBD2_DEBUG is not set
CONFIG_FS_MBCACHE=y
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
CONFIG_FS_POSIX_ACL=y
# CONFIG_XFS_FS is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_BTRFS_FS is not set
# CONFIG_NILFS2_FS is not set
CONFIG_FILE_LOCKING=y
CONFIG_FSNOTIFY=y
CONFIG_DNOTIFY=y
CONFIG_INOTIFY=y
CONFIG_INOTIFY_USER=y
CONFIG_QUOTA=y
CONFIG_QUOTA_NETLINK_INTERFACE=y
# CONFIG_PRINT_QUOTA_WARNING is not set
# CONFIG_QFMT_V1 is not set
# CONFIG_QFMT_V2 is not set
CONFIG_QUOTACTL=y
CONFIG_AUTOFS_FS=y
CONFIG_AUTOFS4_FS=y
CONFIG_FUSE_FS=y
# CONFIG_CUSE is not set
#
# Caches
#
# CONFIG_FSCACHE is not set
#
# CD-ROM/DVD Filesystems
#
CONFIG_ISO9660_FS=m
CONFIG_JOLIET=y
CONFIG_ZISOFS=y
CONFIG_UDF_FS=m
CONFIG_UDF_NLS=y
#
# DOS/FAT/NT Filesystems
#
CONFIG_FAT_FS=y
CONFIG_MSDOS_FS=m
CONFIG_VFAT_FS=y
CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
# CONFIG_NTFS_FS is not set
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_SYSCTL=y
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_SYSFS=y
# CONFIG_TMPFS is not set
# CONFIG_HUGETLB_PAGE is not set
CONFIG_CONFIGFS_FS=m
CONFIG_MISC_FILESYSTEMS=y
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_ECRYPT_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_HFSPLUS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_CRAMFS is not set
# CONFIG_SQUASHFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_OMFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_ROMFS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=y
# CONFIG_NFS_V4_1 is not set
CONFIG_ROOT_NFS=y
# CONFIG_NFSD is not set
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
CONFIG_NFS_ACL_SUPPORT=y
CONFIG_NFS_COMMON=y
CONFIG_SUNRPC=y
CONFIG_SUNRPC_GSS=y
CONFIG_RPCSEC_GSS_KRB5=y
# CONFIG_RPCSEC_GSS_SPKM3 is not set
# CONFIG_SMB_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="cp437"
CONFIG_NLS_CODEPAGE_437=y
# CONFIG_NLS_CODEPAGE_737 is not set
# CONFIG_NLS_CODEPAGE_775 is not set
# CONFIG_NLS_CODEPAGE_850 is not set
# CONFIG_NLS_CODEPAGE_852 is not set
# CONFIG_NLS_CODEPAGE_855 is not set
# CONFIG_NLS_CODEPAGE_857 is not set
# CONFIG_NLS_CODEPAGE_860 is not set
# CONFIG_NLS_CODEPAGE_861 is not set
# CONFIG_NLS_CODEPAGE_862 is not set
# CONFIG_NLS_CODEPAGE_863 is not set
# CONFIG_NLS_CODEPAGE_864 is not set
# CONFIG_NLS_CODEPAGE_865 is not set
# CONFIG_NLS_CODEPAGE_866 is not set
# CONFIG_NLS_CODEPAGE_869 is not set
# CONFIG_NLS_CODEPAGE_936 is not set
# CONFIG_NLS_CODEPAGE_950 is not set
# CONFIG_NLS_CODEPAGE_932 is not set
# CONFIG_NLS_CODEPAGE_949 is not set
# CONFIG_NLS_CODEPAGE_874 is not set
# CONFIG_NLS_ISO8859_8 is not set
# CONFIG_NLS_CODEPAGE_1250 is not set
# CONFIG_NLS_CODEPAGE_1251 is not set
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=m
# CONFIG_NLS_ISO8859_2 is not set
# CONFIG_NLS_ISO8859_3 is not set
# CONFIG_NLS_ISO8859_4 is not set
# CONFIG_NLS_ISO8859_5 is not set
# CONFIG_NLS_ISO8859_6 is not set
# CONFIG_NLS_ISO8859_7 is not set
# CONFIG_NLS_ISO8859_9 is not set
# CONFIG_NLS_ISO8859_13 is not set
# CONFIG_NLS_ISO8859_14 is not set
CONFIG_NLS_ISO8859_15=m
# CONFIG_NLS_KOI8_R is not set
# CONFIG_NLS_KOI8_U is not set
CONFIG_NLS_UTF8=y
# CONFIG_DLM is not set
#
# Kernel hacking
#
# CONFIG_PRINTK_TIME is not set
CONFIG_ENABLE_WARN_DEPRECATED=y
CONFIG_ENABLE_MUST_CHECK=y
CONFIG_FRAME_WARN=1024
CONFIG_MAGIC_SYSRQ=y
# CONFIG_STRIP_ASM_SYMS is not set
# CONFIG_UNUSED_SYMBOLS is not set
CONFIG_DEBUG_FS=y
# CONFIG_HEADERS_CHECK is not set
CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_SHIRQ is not set
# CONFIG_DETECT_SOFTLOCKUP is not set
# CONFIG_DETECT_HUNG_TASK is not set
# CONFIG_SCHED_DEBUG is not set
# CONFIG_SCHEDSTATS is not set
# CONFIG_TIMER_STATS is not set
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_DEBUG_KMEMLEAK is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_RT_MUTEX_TESTER is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_LOCK_ALLOC is not set
# CONFIG_PROVE_LOCKING is not set
# CONFIG_LOCK_STAT is not set
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_DEBUG_KOBJECT is not set
# CONFIG_DEBUG_BUGVERBOSE is not set
# CONFIG_DEBUG_INFO is not set
# CONFIG_DEBUG_VM is not set
# CONFIG_DEBUG_WRITECOUNT is not set
# CONFIG_DEBUG_MEMORY_INIT is not set
# CONFIG_DEBUG_LIST is not set
# CONFIG_DEBUG_SG is not set
# CONFIG_DEBUG_NOTIFIERS is not set
# CONFIG_DEBUG_CREDENTIALS is not set
CONFIG_FRAME_POINTER=y
# CONFIG_BOOT_PRINTK_DELAY is not set
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
# CONFIG_FAULT_INJECTION is not set
# CONFIG_LATENCYTOP is not set
# CONFIG_SYSCTL_SYSCALL_CHECK is not set
# CONFIG_PAGE_POISONING is not set
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_TRACING_SUPPORT=y
# CONFIG_FTRACE is not set
# CONFIG_DYNAMIC_DEBUG is not set
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_KGDB is not set
# CONFIG_ARM_UNWIND is not set
# CONFIG_DEBUG_USER is not set
# CONFIG_DEBUG_ERRORS is not set
# CONFIG_DEBUG_STACK_USAGE is not set
CONFIG_DEBUG_LL=y
CONFIG_EARLY_PRINTK=y
# CONFIG_DEBUG_ICEDCC is not set
# CONFIG_OC_ETM is not set
#
# Security options
#
CONFIG_KEYS=y
# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
# CONFIG_SECURITY is not set
CONFIG_SECURITYFS=y
# CONFIG_DEFAULT_SECURITY_SELINUX is not set
# CONFIG_DEFAULT_SECURITY_SMACK is not set
# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
CONFIG_DEFAULT_SECURITY_DAC=y
CONFIG_DEFAULT_SECURITY=""
CONFIG_CRYPTO=y
#
# Crypto core or helper
#
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_ALGAPI2=y
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_BLKCIPHER=y
CONFIG_CRYPTO_BLKCIPHER2=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_PCOMP=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
# CONFIG_CRYPTO_GF128MUL is not set
# CONFIG_CRYPTO_NULL is not set
CONFIG_CRYPTO_WORKQUEUE=y
# CONFIG_CRYPTO_CRYPTD is not set
# CONFIG_CRYPTO_AUTHENC is not set
# CONFIG_CRYPTO_TEST is not set
#
# Authenticated Encryption with Associated Data
#
# CONFIG_CRYPTO_CCM is not set
# CONFIG_CRYPTO_GCM is not set
# CONFIG_CRYPTO_SEQIV is not set
#
# Block modes
#
CONFIG_CRYPTO_CBC=y
# CONFIG_CRYPTO_CTR is not set
# CONFIG_CRYPTO_CTS is not set
# CONFIG_CRYPTO_ECB is not set
# CONFIG_CRYPTO_LRW is not set
# CONFIG_CRYPTO_PCBC is not set
# CONFIG_CRYPTO_XTS is not set
#
# Hash modes
#
# CONFIG_CRYPTO_HMAC is not set
# CONFIG_CRYPTO_XCBC is not set
# CONFIG_CRYPTO_VMAC is not set
#
# Digest
#
CONFIG_CRYPTO_CRC32C=m
# CONFIG_CRYPTO_GHASH is not set
# CONFIG_CRYPTO_MD4 is not set
CONFIG_CRYPTO_MD5=y
# CONFIG_CRYPTO_MICHAEL_MIC is not set
# CONFIG_CRYPTO_RMD128 is not set
# CONFIG_CRYPTO_RMD160 is not set
# CONFIG_CRYPTO_RMD256 is not set
# CONFIG_CRYPTO_RMD320 is not set
# CONFIG_CRYPTO_SHA1 is not set
# CONFIG_CRYPTO_SHA256 is not set
# CONFIG_CRYPTO_SHA512 is not set
# CONFIG_CRYPTO_TGR192 is not set
# CONFIG_CRYPTO_WP512 is not set
#
# Ciphers
#
# CONFIG_CRYPTO_AES is not set
# CONFIG_CRYPTO_ANUBIS is not set
# CONFIG_CRYPTO_ARC4 is not set
# CONFIG_CRYPTO_BLOWFISH is not set
# CONFIG_CRYPTO_CAMELLIA is not set
# CONFIG_CRYPTO_CAST5 is not set
# CONFIG_CRYPTO_CAST6 is not set
CONFIG_CRYPTO_DES=y
# CONFIG_CRYPTO_FCRYPT is not set
# CONFIG_CRYPTO_KHAZAD is not set
# CONFIG_CRYPTO_SALSA20 is not set
# CONFIG_CRYPTO_SEED is not set
# CONFIG_CRYPTO_SERPENT is not set
# CONFIG_CRYPTO_TEA is not set
# CONFIG_CRYPTO_TWOFISH is not set
#
# Compression
#
CONFIG_CRYPTO_DEFLATE=y
# CONFIG_CRYPTO_ZLIB is not set
CONFIG_CRYPTO_LZO=y
#
# Random Number Generation
#
# CONFIG_CRYPTO_ANSI_CPRNG is not set
# CONFIG_CRYPTO_HW is not set
# CONFIG_BINARY_PRINTF is not set
#
# Library routines
#
CONFIG_BITREVERSE=y
CONFIG_RATIONAL=y
CONFIG_GENERIC_FIND_LAST_BIT=y
CONFIG_CRC_CCITT=m
CONFIG_CRC16=y
CONFIG_CRC_T10DIF=y
CONFIG_CRC_ITU_T=m
CONFIG_CRC32=y
CONFIG_CRC7=m
CONFIG_LIBCRC32C=m
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y
CONFIG_NLATTR=y
arch/arm/mach-mx1/Makefile
浏览文件 @ b93a4afc
...@@ -4,11 +4,12 @@ ...@@ -4,11 +4,12 @@
# Object file lists. # Object file lists.
EXTRA_CFLAGS += -DIMX_NEEDS_DEPRECATED_SYMBOLS
obj-y += generic.o clock.o devices.o obj-y += generic.o clock.o devices.o
# Support for CMOS sensor interface # Support for CMOS sensor interface
obj-$(CONFIG_MX1_VIDEO) += ksym_mx1.o mx1_camera_fiq.o obj-$(CONFIG_MX1_VIDEO) += ksym_mx1.o mx1_camera_fiq.o
# Specific board support # Specific board support
obj-$(CONFIG_ARCH_MX1ADS) += mx1ads.o obj-$(CONFIG_ARCH_MX1ADS) += mach-mx1ads.o
obj-$(CONFIG_MACH_SCB9328) += scb9328.o obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o
\ No newline at end of file
arch/arm/mach-mx1/mx1ads.c → arch/arm/mach-mx1/mach-mx1ads.c
浏览文件 @ b93a4afc
/* /*
* arch/arm/mach-imx/mx1ads.c * arch/arm/mach-imx/mach-mx1ads.c
* *
* Initially based on: * Initially based on:
* linux-2.6.7-imx/arch/arm/mach-imx/scb9328.c * linux-2.6.7-imx/arch/arm/mach-imx/scb9328.c
...@@ -27,7 +27,7 @@ ...@@ -27,7 +27,7 @@
#include <mach/hardware.h> #include <mach/hardware.h>
#include <mach/i2c.h> #include <mach/i2c.h>
#include <mach/imx-uart.h> #include <mach/imx-uart.h>
#include <mach/iomux.h> #include <mach/iomux-mx1.h>
#include <mach/irqs.h> #include <mach/irqs.h>
#include "devices.h" #include "devices.h"
...@@ -147,7 +147,7 @@ MACHINE_START(MX1ADS, "Freescale MX1ADS") ...@@ -147,7 +147,7 @@ MACHINE_START(MX1ADS, "Freescale MX1ADS")
/* Maintainer: Sascha Hauer, Pengutronix */ /* Maintainer: Sascha Hauer, Pengutronix */
.phys_io = IMX_IO_PHYS, .phys_io = IMX_IO_PHYS,
.io_pg_offst = (IMX_IO_BASE >> 18) & 0xfffc, .io_pg_offst = (IMX_IO_BASE >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100, .boot_params = MX1_PHYS_OFFSET + 0x100,
.map_io = mx1_map_io, .map_io = mx1_map_io,
.init_irq = mx1_init_irq, .init_irq = mx1_init_irq,
.timer = &mx1ads_timer, .timer = &mx1ads_timer,
...@@ -157,7 +157,7 @@ MACHINE_END ...@@ -157,7 +157,7 @@ MACHINE_END
MACHINE_START(MXLADS, "Freescale MXLADS") MACHINE_START(MXLADS, "Freescale MXLADS")
.phys_io = IMX_IO_PHYS, .phys_io = IMX_IO_PHYS,
.io_pg_offst = (IMX_IO_BASE >> 18) & 0xfffc, .io_pg_offst = (IMX_IO_BASE >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100, .boot_params = MX1_PHYS_OFFSET + 0x100,
.map_io = mx1_map_io, .map_io = mx1_map_io,
.init_irq = mx1_init_irq, .init_irq = mx1_init_irq,
.timer = &mx1ads_timer, .timer = &mx1ads_timer,
......
arch/arm/mach-mx1/scb9328.c → arch/arm/mach-mx1/mach-scb9328.c
浏览文件 @ b93a4afc
/* /*
* linux/arch/arm/mach-mx1/scb9328.c * linux/arch/arm/mach-mx1/mach-scb9328.c
* *
* Copyright (c) 2004 Sascha Hauer <saschahauer@web.de> * Copyright (c) 2004 Sascha Hauer <saschahauer@web.de>
* Copyright (c) 2006-2008 Juergen Beisert <jbeisert@netscape.net> * Copyright (c) 2006-2008 Juergen Beisert <jbeisert@netscape.net>
...@@ -23,7 +23,7 @@ ...@@ -23,7 +23,7 @@
#include <mach/hardware.h> #include <mach/hardware.h>
#include <mach/irqs.h> #include <mach/irqs.h>
#include <mach/imx-uart.h> #include <mach/imx-uart.h>
#include <mach/iomux.h> #include <mach/iomux-mx1.h>
#include "devices.h" #include "devices.h"
......
arch/arm/mach-mx2/Kconfig
浏览文件 @ b93a4afc
...@@ -37,6 +37,7 @@ config MACH_MX27ADS ...@@ -37,6 +37,7 @@ config MACH_MX27ADS
config MACH_PCM038 config MACH_PCM038
bool "Phytec phyCORE-i.MX27 CPU module (pcm038)" bool "Phytec phyCORE-i.MX27 CPU module (pcm038)"
depends on MACH_MX27 depends on MACH_MX27
select MXC_ULPI if USB_ULPI
help help
Include support for phyCORE-i.MX27 (aka pcm038) platform. This Include support for phyCORE-i.MX27 (aka pcm038) platform. This
includes specific configurations for the module and its peripherals. includes specific configurations for the module and its peripherals.
...@@ -55,7 +56,7 @@ config MACH_PCM970_BASEBOARD ...@@ -55,7 +56,7 @@ config MACH_PCM970_BASEBOARD
endchoice endchoice
config MACH_EUKREA_CPUIMX27 config MACH_CPUIMX27
bool "Eukrea CPUIMX27 module" bool "Eukrea CPUIMX27 module"
depends on MACH_MX27 depends on MACH_MX27
help help
...@@ -64,14 +65,14 @@ config MACH_EUKREA_CPUIMX27 ...@@ -64,14 +65,14 @@ config MACH_EUKREA_CPUIMX27
config MACH_EUKREA_CPUIMX27_USESDHC2 config MACH_EUKREA_CPUIMX27_USESDHC2
bool "CPUIMX27 integrates SDHC2 module" bool "CPUIMX27 integrates SDHC2 module"
depends on MACH_EUKREA_CPUIMX27 depends on MACH_CPUIMX27
help help
This adds support for the internal SDHC2 used on CPUIMX27 used This adds support for the internal SDHC2 used on CPUIMX27 used
for wifi or eMMC. for wifi or eMMC.
choice choice
prompt "Baseboard" prompt "Baseboard"
depends on MACH_EUKREA_CPUIMX27 depends on MACH_CPUIMX27
default MACH_EUKREA_MBIMX27_BASEBOARD default MACH_EUKREA_MBIMX27_BASEBOARD
config MACH_EUKREA_MBIMX27_BASEBOARD config MACH_EUKREA_MBIMX27_BASEBOARD
...@@ -90,7 +91,7 @@ config MACH_MX27_3DS ...@@ -90,7 +91,7 @@ config MACH_MX27_3DS
Include support for MX27PDK platform. This includes specific Include support for MX27PDK platform. This includes specific
configurations for the board and its peripherals. configurations for the board and its peripherals.
config MACH_MX27LITE config MACH_IMX27LITE
bool "LogicPD MX27 LITEKIT platform" bool "LogicPD MX27 LITEKIT platform"
depends on MACH_MX27 depends on MACH_MX27
help help
...@@ -100,6 +101,7 @@ config MACH_MX27LITE ...@@ -100,6 +101,7 @@ config MACH_MX27LITE
config MACH_PCA100 config MACH_PCA100
bool "Phytec phyCARD-s (pca100)" bool "Phytec phyCARD-s (pca100)"
depends on MACH_MX27 depends on MACH_MX27
select MXC_ULPI if USB_ULPI
help help
Include support for phyCARD-s (aka pca100) platform. This Include support for phyCARD-s (aka pca100) platform. This
includes specific configurations for the module and its peripherals. includes specific configurations for the module and its peripherals.
......
arch/arm/mach-mx2/Makefile
浏览文件 @ b93a4afc
...@@ -4,21 +4,20 @@ ...@@ -4,21 +4,20 @@
# Object file lists. # Object file lists.
obj-y := generic.o devices.o serial.o obj-y := devices.o serial.o
obj-$(CONFIG_MACH_MX21) += clock_imx21.o obj-$(CONFIG_MACH_MX21) += clock_imx21.o mm-imx21.o
obj-$(CONFIG_MACH_MX27) += cpu_imx27.o obj-$(CONFIG_MACH_MX27) += cpu_imx27.o
obj-$(CONFIG_MACH_MX27) += clock_imx27.o obj-$(CONFIG_MACH_MX27) += clock_imx27.o mm-imx27.o
obj-$(CONFIG_MACH_MX21ADS) += mx21ads.o obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o
obj-$(CONFIG_MACH_MX27ADS) += mx27ads.o obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o
obj-$(CONFIG_MACH_PCM038) += pcm038.o obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o
obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o
obj-$(CONFIG_MACH_MX27_3DS) += mx27pdk.o obj-$(CONFIG_MACH_MX27_3DS) += mach-mx27_3ds.o
obj-$(CONFIG_MACH_MX27LITE) += mx27lite.o obj-$(CONFIG_MACH_IMX27LITE) += mach-imx27lite.o
obj-$(CONFIG_MACH_EUKREA_CPUIMX27) += eukrea_cpuimx27.o obj-$(CONFIG_MACH_CPUIMX27) += mach-cpuimx27.o
obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o
obj-$(CONFIG_MACH_PCA100) += pca100.o obj-$(CONFIG_MACH_PCA100) += mach-pca100.o
obj-$(CONFIG_MACH_MXT_TD60) += mxt_td60.o obj-$(CONFIG_MACH_MXT_TD60) += mach-mxt_td60.o
arch/arm/mach-mx2/clock_imx21.c
浏览文件 @ b93a4afc
...@@ -23,11 +23,242 @@ ...@@ -23,11 +23,242 @@
#include <linux/module.h> #include <linux/module.h>
#include <mach/clock.h> #include <mach/clock.h>
#include <mach/hardware.h>
#include <mach/common.h> #include <mach/common.h>
#include <asm/clkdev.h> #include <asm/clkdev.h>
#include <asm/div64.h> #include <asm/div64.h>
#include "crm_regs.h" #define IO_ADDR_CCM(off) (MX21_IO_ADDRESS(MX21_CCM_BASE_ADDR + (off)))
/* Register offsets */
#define CCM_CSCR IO_ADDR_CCM(0x0)
#define CCM_MPCTL0 IO_ADDR_CCM(0x4)
#define CCM_MPCTL1 IO_ADDR_CCM(0x8)
#define CCM_SPCTL0 IO_ADDR_CCM(0xc)
#define CCM_SPCTL1 IO_ADDR_CCM(0x10)
#define CCM_OSC26MCTL IO_ADDR_CCM(0x14)
#define CCM_PCDR0 IO_ADDR_CCM(0x18)
#define CCM_PCDR1 IO_ADDR_CCM(0x1c)
#define CCM_PCCR0 IO_ADDR_CCM(0x20)
#define CCM_PCCR1 IO_ADDR_CCM(0x24)
#define CCM_CCSR IO_ADDR_CCM(0x28)
#define CCM_PMCTL IO_ADDR_CCM(0x2c)
#define CCM_PMCOUNT IO_ADDR_CCM(0x30)
#define CCM_WKGDCTL IO_ADDR_CCM(0x34)
#define CCM_CSCR_PRESC_OFFSET 29
#define CCM_CSCR_PRESC_MASK (0x7 << CCM_CSCR_PRESC_OFFSET)
#define CCM_CSCR_USB_OFFSET 26
#define CCM_CSCR_USB_MASK (0x7 << CCM_CSCR_USB_OFFSET)
#define CCM_CSCR_SD_OFFSET 24
#define CCM_CSCR_SD_MASK (0x3 << CCM_CSCR_SD_OFFSET)
#define CCM_CSCR_SPLLRES (1 << 22)
#define CCM_CSCR_MPLLRES (1 << 21)
#define CCM_CSCR_SSI2_OFFSET 20
#define CCM_CSCR_SSI2 (1 << CCM_CSCR_SSI2_OFFSET)
#define CCM_CSCR_SSI1_OFFSET 19
#define CCM_CSCR_SSI1 (1 << CCM_CSCR_SSI1_OFFSET)
#define CCM_CSCR_FIR_OFFSET 18
#define CCM_CSCR_FIR (1 << CCM_CSCR_FIR_OFFSET)
#define CCM_CSCR_SP (1 << 17)
#define CCM_CSCR_MCU (1 << 16)
#define CCM_CSCR_BCLK_OFFSET 10
#define CCM_CSCR_BCLK_MASK (0xf << CCM_CSCR_BCLK_OFFSET)
#define CCM_CSCR_IPDIV_OFFSET 9
#define CCM_CSCR_IPDIV (1 << CCM_CSCR_IPDIV_OFFSET)
#define CCM_CSCR_OSC26MDIV (1 << 4)
#define CCM_CSCR_OSC26M (1 << 3)
#define CCM_CSCR_FPM (1 << 2)
#define CCM_CSCR_SPEN (1 << 1)
#define CCM_CSCR_MPEN 1
#define CCM_MPCTL0_CPLM (1 << 31)
#define CCM_MPCTL0_PD_OFFSET 26
#define CCM_MPCTL0_PD_MASK (0xf << 26)
#define CCM_MPCTL0_MFD_OFFSET 16
#define CCM_MPCTL0_MFD_MASK (0x3ff << 16)
#define CCM_MPCTL0_MFI_OFFSET 10
#define CCM_MPCTL0_MFI_MASK (0xf << 10)
#define CCM_MPCTL0_MFN_OFFSET 0
#define CCM_MPCTL0_MFN_MASK 0x3ff
#define CCM_MPCTL1_LF (1 << 15)
#define CCM_MPCTL1_BRMO (1 << 6)
#define CCM_SPCTL0_CPLM (1 << 31)
#define CCM_SPCTL0_PD_OFFSET 26
#define CCM_SPCTL0_PD_MASK (0xf << 26)
#define CCM_SPCTL0_MFD_OFFSET 16
#define CCM_SPCTL0_MFD_MASK (0x3ff << 16)
#define CCM_SPCTL0_MFI_OFFSET 10
#define CCM_SPCTL0_MFI_MASK (0xf << 10)
#define CCM_SPCTL0_MFN_OFFSET 0
#define CCM_SPCTL0_MFN_MASK 0x3ff
#define CCM_SPCTL1_LF (1 << 15)
#define CCM_SPCTL1_BRMO (1 << 6)
#define CCM_OSC26MCTL_PEAK_OFFSET 16
#define CCM_OSC26MCTL_PEAK_MASK (0x3 << 16)
#define CCM_OSC26MCTL_AGC_OFFSET 8
#define CCM_OSC26MCTL_AGC_MASK (0x3f << 8)
#define CCM_OSC26MCTL_ANATEST_OFFSET 0
#define CCM_OSC26MCTL_ANATEST_MASK 0x3f
#define CCM_PCDR0_SSI2BAUDDIV_OFFSET 26
#define CCM_PCDR0_SSI2BAUDDIV_MASK (0x3f << 26)
#define CCM_PCDR0_SSI1BAUDDIV_OFFSET 16
#define CCM_PCDR0_SSI1BAUDDIV_MASK (0x3f << 16)
#define CCM_PCDR0_NFCDIV_OFFSET 12
#define CCM_PCDR0_NFCDIV_MASK (0xf << 12)
#define CCM_PCDR0_48MDIV_OFFSET 5
#define CCM_PCDR0_48MDIV_MASK (0x7 << CCM_PCDR0_48MDIV_OFFSET)
#define CCM_PCDR0_FIRIDIV_OFFSET 0
#define CCM_PCDR0_FIRIDIV_MASK 0x1f
#define CCM_PCDR1_PERDIV4_OFFSET 24
#define CCM_PCDR1_PERDIV4_MASK (0x3f << 24)
#define CCM_PCDR1_PERDIV3_OFFSET 16
#define CCM_PCDR1_PERDIV3_MASK (0x3f << 16)
#define CCM_PCDR1_PERDIV2_OFFSET 8
#define CCM_PCDR1_PERDIV2_MASK (0x3f << 8)
#define CCM_PCDR1_PERDIV1_OFFSET 0
#define CCM_PCDR1_PERDIV1_MASK 0x3f
#define CCM_PCCR_HCLK_CSI_OFFSET 31
#define CCM_PCCR_HCLK_CSI_REG CCM_PCCR0
#define CCM_PCCR_HCLK_DMA_OFFSET 30
#define CCM_PCCR_HCLK_DMA_REG CCM_PCCR0
#define CCM_PCCR_HCLK_BROM_OFFSET 28
#define CCM_PCCR_HCLK_BROM_REG CCM_PCCR0
#define CCM_PCCR_HCLK_EMMA_OFFSET 27
#define CCM_PCCR_HCLK_EMMA_REG CCM_PCCR0
#define CCM_PCCR_HCLK_LCDC_OFFSET 26
#define CCM_PCCR_HCLK_LCDC_REG CCM_PCCR0
#define CCM_PCCR_HCLK_SLCDC_OFFSET 25
#define CCM_PCCR_HCLK_SLCDC_REG CCM_PCCR0
#define CCM_PCCR_HCLK_USBOTG_OFFSET 24
#define CCM_PCCR_HCLK_USBOTG_REG CCM_PCCR0
#define CCM_PCCR_HCLK_BMI_OFFSET 23
#define CCM_PCCR_BMI_MASK (1 << CCM_PCCR_BMI_MASK)
#define CCM_PCCR_HCLK_BMI_REG CCM_PCCR0
#define CCM_PCCR_PERCLK4_OFFSET 22
#define CCM_PCCR_PERCLK4_REG CCM_PCCR0
#define CCM_PCCR_SLCDC_OFFSET 21
#define CCM_PCCR_SLCDC_REG CCM_PCCR0
#define CCM_PCCR_FIRI_BAUD_OFFSET 20
#define CCM_PCCR_FIRI_BAUD_MASK (1 << CCM_PCCR_FIRI_BAUD_MASK)
#define CCM_PCCR_FIRI_BAUD_REG CCM_PCCR0
#define CCM_PCCR_NFC_OFFSET 19
#define CCM_PCCR_NFC_REG CCM_PCCR0
#define CCM_PCCR_LCDC_OFFSET 18
#define CCM_PCCR_LCDC_REG CCM_PCCR0
#define CCM_PCCR_SSI1_BAUD_OFFSET 17
#define CCM_PCCR_SSI1_BAUD_REG CCM_PCCR0
#define CCM_PCCR_SSI2_BAUD_OFFSET 16
#define CCM_PCCR_SSI2_BAUD_REG CCM_PCCR0
#define CCM_PCCR_EMMA_OFFSET 15
#define CCM_PCCR_EMMA_REG CCM_PCCR0
#define CCM_PCCR_USBOTG_OFFSET 14
#define CCM_PCCR_USBOTG_REG CCM_PCCR0
#define CCM_PCCR_DMA_OFFSET 13
#define CCM_PCCR_DMA_REG CCM_PCCR0
#define CCM_PCCR_I2C1_OFFSET 12
#define CCM_PCCR_I2C1_REG CCM_PCCR0
#define CCM_PCCR_GPIO_OFFSET 11
#define CCM_PCCR_GPIO_REG CCM_PCCR0
#define CCM_PCCR_SDHC2_OFFSET 10
#define CCM_PCCR_SDHC2_REG CCM_PCCR0
#define CCM_PCCR_SDHC1_OFFSET 9
#define CCM_PCCR_SDHC1_REG CCM_PCCR0
#define CCM_PCCR_FIRI_OFFSET 8
#define CCM_PCCR_FIRI_MASK (1 << CCM_PCCR_BAUD_MASK)
#define CCM_PCCR_FIRI_REG CCM_PCCR0
#define CCM_PCCR_SSI2_IPG_OFFSET 7
#define CCM_PCCR_SSI2_REG CCM_PCCR0
#define CCM_PCCR_SSI1_IPG_OFFSET 6
#define CCM_PCCR_SSI1_REG CCM_PCCR0
#define CCM_PCCR_CSPI2_OFFSET 5
#define CCM_PCCR_CSPI2_REG CCM_PCCR0
#define CCM_PCCR_CSPI1_OFFSET 4
#define CCM_PCCR_CSPI1_REG CCM_PCCR0
#define CCM_PCCR_UART4_OFFSET 3
#define CCM_PCCR_UART4_REG CCM_PCCR0
#define CCM_PCCR_UART3_OFFSET 2
#define CCM_PCCR_UART3_REG CCM_PCCR0
#define CCM_PCCR_UART2_OFFSET 1
#define CCM_PCCR_UART2_REG CCM_PCCR0
#define CCM_PCCR_UART1_OFFSET 0
#define CCM_PCCR_UART1_REG CCM_PCCR0
#define CCM_PCCR_OWIRE_OFFSET 31
#define CCM_PCCR_OWIRE_REG CCM_PCCR1
#define CCM_PCCR_KPP_OFFSET 30
#define CCM_PCCR_KPP_REG CCM_PCCR1
#define CCM_PCCR_RTC_OFFSET 29
#define CCM_PCCR_RTC_REG CCM_PCCR1
#define CCM_PCCR_PWM_OFFSET 28
#define CCM_PCCR_PWM_REG CCM_PCCR1
#define CCM_PCCR_GPT3_OFFSET 27
#define CCM_PCCR_GPT3_REG CCM_PCCR1
#define CCM_PCCR_GPT2_OFFSET 26
#define CCM_PCCR_GPT2_REG CCM_PCCR1
#define CCM_PCCR_GPT1_OFFSET 25
#define CCM_PCCR_GPT1_REG CCM_PCCR1
#define CCM_PCCR_WDT_OFFSET 24
#define CCM_PCCR_WDT_REG CCM_PCCR1
#define CCM_PCCR_CSPI3_OFFSET 23
#define CCM_PCCR_CSPI3_REG CCM_PCCR1
#define CCM_PCCR_CSPI1_MASK (1 << CCM_PCCR_CSPI1_OFFSET)
#define CCM_PCCR_CSPI2_MASK (1 << CCM_PCCR_CSPI2_OFFSET)
#define CCM_PCCR_CSPI3_MASK (1 << CCM_PCCR_CSPI3_OFFSET)
#define CCM_PCCR_DMA_MASK (1 << CCM_PCCR_DMA_OFFSET)
#define CCM_PCCR_EMMA_MASK (1 << CCM_PCCR_EMMA_OFFSET)
#define CCM_PCCR_GPIO_MASK (1 << CCM_PCCR_GPIO_OFFSET)
#define CCM_PCCR_GPT1_MASK (1 << CCM_PCCR_GPT1_OFFSET)
#define CCM_PCCR_GPT2_MASK (1 << CCM_PCCR_GPT2_OFFSET)
#define CCM_PCCR_GPT3_MASK (1 << CCM_PCCR_GPT3_OFFSET)
#define CCM_PCCR_HCLK_BROM_MASK (1 << CCM_PCCR_HCLK_BROM_OFFSET)
#define CCM_PCCR_HCLK_CSI_MASK (1 << CCM_PCCR_HCLK_CSI_OFFSET)
#define CCM_PCCR_HCLK_DMA_MASK (1 << CCM_PCCR_HCLK_DMA_OFFSET)
#define CCM_PCCR_HCLK_EMMA_MASK (1 << CCM_PCCR_HCLK_EMMA_OFFSET)
#define CCM_PCCR_HCLK_LCDC_MASK (1 << CCM_PCCR_HCLK_LCDC_OFFSET)
#define CCM_PCCR_HCLK_SLCDC_MASK (1 << CCM_PCCR_HCLK_SLCDC_OFFSET)
#define CCM_PCCR_HCLK_USBOTG_MASK (1 << CCM_PCCR_HCLK_USBOTG_OFFSET)
#define CCM_PCCR_I2C1_MASK (1 << CCM_PCCR_I2C1_OFFSET)
#define CCM_PCCR_KPP_MASK (1 << CCM_PCCR_KPP_OFFSET)
#define CCM_PCCR_LCDC_MASK (1 << CCM_PCCR_LCDC_OFFSET)
#define CCM_PCCR_NFC_MASK (1 << CCM_PCCR_NFC_OFFSET)
#define CCM_PCCR_OWIRE_MASK (1 << CCM_PCCR_OWIRE_OFFSET)
#define CCM_PCCR_PERCLK4_MASK (1 << CCM_PCCR_PERCLK4_OFFSET)
#define CCM_PCCR_PWM_MASK (1 << CCM_PCCR_PWM_OFFSET)
#define CCM_PCCR_RTC_MASK (1 << CCM_PCCR_RTC_OFFSET)
#define CCM_PCCR_SDHC1_MASK (1 << CCM_PCCR_SDHC1_OFFSET)
#define CCM_PCCR_SDHC2_MASK (1 << CCM_PCCR_SDHC2_OFFSET)
#define CCM_PCCR_SLCDC_MASK (1 << CCM_PCCR_SLCDC_OFFSET)
#define CCM_PCCR_SSI1_BAUD_MASK (1 << CCM_PCCR_SSI1_BAUD_OFFSET)
#define CCM_PCCR_SSI1_IPG_MASK (1 << CCM_PCCR_SSI1_IPG_OFFSET)
#define CCM_PCCR_SSI2_BAUD_MASK (1 << CCM_PCCR_SSI2_BAUD_OFFSET)
#define CCM_PCCR_SSI2_IPG_MASK (1 << CCM_PCCR_SSI2_IPG_OFFSET)
#define CCM_PCCR_UART1_MASK (1 << CCM_PCCR_UART1_OFFSET)
#define CCM_PCCR_UART2_MASK (1 << CCM_PCCR_UART2_OFFSET)
#define CCM_PCCR_UART3_MASK (1 << CCM_PCCR_UART3_OFFSET)
#define CCM_PCCR_UART4_MASK (1 << CCM_PCCR_UART4_OFFSET)
#define CCM_PCCR_USBOTG_MASK (1 << CCM_PCCR_USBOTG_OFFSET)
#define CCM_PCCR_WDT_MASK (1 << CCM_PCCR_WDT_OFFSET)
#define CCM_CCSR_32KSR (1 << 15)
#define CCM_CCSR_CLKMODE1 (1 << 9)
#define CCM_CCSR_CLKMODE0 (1 << 8)
#define CCM_CCSR_CLKOSEL_OFFSET 0
#define CCM_CCSR_CLKOSEL_MASK 0x1f
#define SYS_FMCR 0x14 /* Functional Muxing Control Reg */
#define SYS_CHIP_ID 0x00 /* The offset of CHIP ID register */
static int _clk_enable(struct clk *clk) static int _clk_enable(struct clk *clk)
{ {
...@@ -1004,6 +1235,7 @@ int __init mx21_clocks_init(unsigned long lref, unsigned long href) ...@@ -1004,6 +1235,7 @@ int __init mx21_clocks_init(unsigned long lref, unsigned long href)
clk_enable(&uart_clk[0]); clk_enable(&uart_clk[0]);
#endif #endif
mxc_timer_init(&gpt_clk[0], IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT1); mxc_timer_init(&gpt_clk[0], MX21_IO_ADDRESS(MX21_GPT1_BASE_ADDR),
MX21_INT_GPT1);
return 0; return 0;
} }
arch/arm/mach-mx2/clock_imx27.c
浏览文件 @ b93a4afc
...@@ -29,21 +29,23 @@ ...@@ -29,21 +29,23 @@
#include <mach/common.h> #include <mach/common.h>
#include <mach/hardware.h> #include <mach/hardware.h>
#define IO_ADDR_CCM(off) (MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR + (off)))
/* Register offsets */ /* Register offsets */
#define CCM_CSCR (IO_ADDRESS(CCM_BASE_ADDR) + 0x0) #define CCM_CSCR IO_ADDR_CCM(0x0)
#define CCM_MPCTL0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x4) #define CCM_MPCTL0 IO_ADDR_CCM(0x4)
#define CCM_MPCTL1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x8) #define CCM_MPCTL1 IO_ADDR_CCM(0x8)
#define CCM_SPCTL0 (IO_ADDRESS(CCM_BASE_ADDR) + 0xC) #define CCM_SPCTL0 IO_ADDR_CCM(0xc)
#define CCM_SPCTL1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x10) #define CCM_SPCTL1 IO_ADDR_CCM(0x10)
#define CCM_OSC26MCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x14) #define CCM_OSC26MCTL IO_ADDR_CCM(0x14)
#define CCM_PCDR0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x18) #define CCM_PCDR0 IO_ADDR_CCM(0x18)
#define CCM_PCDR1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x1c) #define CCM_PCDR1 IO_ADDR_CCM(0x1c)
#define CCM_PCCR0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x20) #define CCM_PCCR0 IO_ADDR_CCM(0x20)
#define CCM_PCCR1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x24) #define CCM_PCCR1 IO_ADDR_CCM(0x24)
#define CCM_CCSR (IO_ADDRESS(CCM_BASE_ADDR) + 0x28) #define CCM_CCSR IO_ADDR_CCM(0x28)
#define CCM_PMCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x2c) #define CCM_PMCTL IO_ADDR_CCM(0x2c)
#define CCM_PMCOUNT (IO_ADDRESS(CCM_BASE_ADDR) + 0x30) #define CCM_PMCOUNT IO_ADDR_CCM(0x30)
#define CCM_WKGDCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x34) #define CCM_WKGDCTL IO_ADDR_CCM(0x34)
#define CCM_CSCR_UPDATE_DIS (1 << 31) #define CCM_CSCR_UPDATE_DIS (1 << 31)
#define CCM_CSCR_SSI2 (1 << 23) #define CCM_CSCR_SSI2 (1 << 23)
...@@ -755,7 +757,8 @@ int __init mx27_clocks_init(unsigned long fref) ...@@ -755,7 +757,8 @@ int __init mx27_clocks_init(unsigned long fref)
clk_enable(&uart1_clk); clk_enable(&uart1_clk);
#endif #endif
mxc_timer_init(&gpt1_clk, IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT1); mxc_timer_init(&gpt1_clk, MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR),
MX27_INT_GPT1);
return 0; return 0;
} }
......
arch/arm/mach-mx2/cpu_imx27.c
浏览文件 @ b93a4afc
...@@ -39,7 +39,8 @@ static void query_silicon_parameter(void) ...@@ -39,7 +39,8 @@ static void query_silicon_parameter(void)
* the silicon revision very early we read it here to * the silicon revision very early we read it here to
* avoid any further hooks * avoid any further hooks
*/ */
val = __raw_readl(IO_ADDRESS(SYSCTRL_BASE_ADDR) + SYS_CHIP_ID); val = __raw_readl(MX27_IO_ADDRESS(MX27_SYSCTRL_BASE_ADDR
+ SYS_CHIP_ID));
cpu_silicon_rev = (int)(val >> 28); cpu_silicon_rev = (int)(val >> 28);
cpu_partnumber = (int)((val >> 12) & 0xFFFF); cpu_partnumber = (int)((val >> 12) & 0xFFFF);
......
arch/arm/mach-mx2/crm_regs.h 已删除 100644 → 0
浏览文件 @ 62c132a8
/*
* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#ifndef __ARCH_ARM_MACH_MX2_CRM_REGS_H__
#define __ARCH_ARM_MACH_MX2_CRM_REGS_H__
#include <mach/hardware.h>
/* Register offsets */
#define CCM_CSCR (IO_ADDRESS(CCM_BASE_ADDR) + 0x0)
#define CCM_MPCTL0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x4)
#define CCM_MPCTL1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x8)
#define CCM_SPCTL0 (IO_ADDRESS(CCM_BASE_ADDR) + 0xC)
#define CCM_SPCTL1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x10)
#define CCM_OSC26MCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x14)
#define CCM_PCDR0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x18)
#define CCM_PCDR1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x1c)
#define CCM_PCCR0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x20)
#define CCM_PCCR1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x24)
#define CCM_CCSR (IO_ADDRESS(CCM_BASE_ADDR) + 0x28)
#define CCM_PMCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x2c)
#define CCM_PMCOUNT (IO_ADDRESS(CCM_BASE_ADDR) + 0x30)
#define CCM_WKGDCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x34)
#define CCM_CSCR_PRESC_OFFSET 29
#define CCM_CSCR_PRESC_MASK (0x7 << CCM_CSCR_PRESC_OFFSET)
#define CCM_CSCR_USB_OFFSET 26
#define CCM_CSCR_USB_MASK (0x7 << CCM_CSCR_USB_OFFSET)
#define CCM_CSCR_SD_OFFSET 24
#define CCM_CSCR_SD_MASK (0x3 << CCM_CSCR_SD_OFFSET)
#define CCM_CSCR_SPLLRES (1 << 22)
#define CCM_CSCR_MPLLRES (1 << 21)
#define CCM_CSCR_SSI2_OFFSET 20
#define CCM_CSCR_SSI2 (1 << CCM_CSCR_SSI2_OFFSET)
#define CCM_CSCR_SSI1_OFFSET 19
#define CCM_CSCR_SSI1 (1 << CCM_CSCR_SSI1_OFFSET)
#define CCM_CSCR_FIR_OFFSET 18
#define CCM_CSCR_FIR (1 << CCM_CSCR_FIR_OFFSET)
#define CCM_CSCR_SP (1 << 17)
#define CCM_CSCR_MCU (1 << 16)
#define CCM_CSCR_BCLK_OFFSET 10
#define CCM_CSCR_BCLK_MASK (0xf << CCM_CSCR_BCLK_OFFSET)
#define CCM_CSCR_IPDIV_OFFSET 9
#define CCM_CSCR_IPDIV (1 << CCM_CSCR_IPDIV_OFFSET)
#define CCM_CSCR_OSC26MDIV (1 << 4)
#define CCM_CSCR_OSC26M (1 << 3)
#define CCM_CSCR_FPM (1 << 2)
#define CCM_CSCR_SPEN (1 << 1)
#define CCM_CSCR_MPEN 1
#define CCM_MPCTL0_CPLM (1 << 31)
#define CCM_MPCTL0_PD_OFFSET 26
#define CCM_MPCTL0_PD_MASK (0xf << 26)
#define CCM_MPCTL0_MFD_OFFSET 16
#define CCM_MPCTL0_MFD_MASK (0x3ff << 16)
#define CCM_MPCTL0_MFI_OFFSET 10
#define CCM_MPCTL0_MFI_MASK (0xf << 10)
#define CCM_MPCTL0_MFN_OFFSET 0
#define CCM_MPCTL0_MFN_MASK 0x3ff
#define CCM_MPCTL1_LF (1 << 15)
#define CCM_MPCTL1_BRMO (1 << 6)
#define CCM_SPCTL0_CPLM (1 << 31)
#define CCM_SPCTL0_PD_OFFSET 26
#define CCM_SPCTL0_PD_MASK (0xf << 26)
#define CCM_SPCTL0_MFD_OFFSET 16
#define CCM_SPCTL0_MFD_MASK (0x3ff << 16)
#define CCM_SPCTL0_MFI_OFFSET 10
#define CCM_SPCTL0_MFI_MASK (0xf << 10)
#define CCM_SPCTL0_MFN_OFFSET 0
#define CCM_SPCTL0_MFN_MASK 0x3ff
#define CCM_SPCTL1_LF (1 << 15)
#define CCM_SPCTL1_BRMO (1 << 6)
#define CCM_OSC26MCTL_PEAK_OFFSET 16
#define CCM_OSC26MCTL_PEAK_MASK (0x3 << 16)
#define CCM_OSC26MCTL_AGC_OFFSET 8
#define CCM_OSC26MCTL_AGC_MASK (0x3f << 8)
#define CCM_OSC26MCTL_ANATEST_OFFSET 0
#define CCM_OSC26MCTL_ANATEST_MASK 0x3f
#define CCM_PCDR0_SSI2BAUDDIV_OFFSET 26
#define CCM_PCDR0_SSI2BAUDDIV_MASK (0x3f << 26)
#define CCM_PCDR0_SSI1BAUDDIV_OFFSET 16
#define CCM_PCDR0_SSI1BAUDDIV_MASK (0x3f << 16)
#define CCM_PCDR0_NFCDIV_OFFSET 12
#define CCM_PCDR0_NFCDIV_MASK (0xf << 12)
#define CCM_PCDR0_48MDIV_OFFSET 5
#define CCM_PCDR0_48MDIV_MASK (0x7 << CCM_PCDR0_48MDIV_OFFSET)
#define CCM_PCDR0_FIRIDIV_OFFSET 0
#define CCM_PCDR0_FIRIDIV_MASK 0x1f
#define CCM_PCDR1_PERDIV4_OFFSET 24
#define CCM_PCDR1_PERDIV4_MASK (0x3f << 24)
#define CCM_PCDR1_PERDIV3_OFFSET 16
#define CCM_PCDR1_PERDIV3_MASK (0x3f << 16)
#define CCM_PCDR1_PERDIV2_OFFSET 8
#define CCM_PCDR1_PERDIV2_MASK (0x3f << 8)
#define CCM_PCDR1_PERDIV1_OFFSET 0
#define CCM_PCDR1_PERDIV1_MASK 0x3f
#define CCM_PCCR_HCLK_CSI_OFFSET 31
#define CCM_PCCR_HCLK_CSI_REG CCM_PCCR0
#define CCM_PCCR_HCLK_DMA_OFFSET 30
#define CCM_PCCR_HCLK_DMA_REG CCM_PCCR0
#define CCM_PCCR_HCLK_BROM_OFFSET 28
#define CCM_PCCR_HCLK_BROM_REG CCM_PCCR0
#define CCM_PCCR_HCLK_EMMA_OFFSET 27
#define CCM_PCCR_HCLK_EMMA_REG CCM_PCCR0
#define CCM_PCCR_HCLK_LCDC_OFFSET 26
#define CCM_PCCR_HCLK_LCDC_REG CCM_PCCR0
#define CCM_PCCR_HCLK_SLCDC_OFFSET 25
#define CCM_PCCR_HCLK_SLCDC_REG CCM_PCCR0
#define CCM_PCCR_HCLK_USBOTG_OFFSET 24
#define CCM_PCCR_HCLK_USBOTG_REG CCM_PCCR0
#define CCM_PCCR_HCLK_BMI_OFFSET 23
#define CCM_PCCR_BMI_MASK (1 << CCM_PCCR_BMI_MASK)
#define CCM_PCCR_HCLK_BMI_REG CCM_PCCR0
#define CCM_PCCR_PERCLK4_OFFSET 22
#define CCM_PCCR_PERCLK4_REG CCM_PCCR0
#define CCM_PCCR_SLCDC_OFFSET 21
#define CCM_PCCR_SLCDC_REG CCM_PCCR0
#define CCM_PCCR_FIRI_BAUD_OFFSET 20
#define CCM_PCCR_FIRI_BAUD_MASK (1 << CCM_PCCR_FIRI_BAUD_MASK)
#define CCM_PCCR_FIRI_BAUD_REG CCM_PCCR0
#define CCM_PCCR_NFC_OFFSET 19
#define CCM_PCCR_NFC_REG CCM_PCCR0
#define CCM_PCCR_LCDC_OFFSET 18
#define CCM_PCCR_LCDC_REG CCM_PCCR0
#define CCM_PCCR_SSI1_BAUD_OFFSET 17
#define CCM_PCCR_SSI1_BAUD_REG CCM_PCCR0
#define CCM_PCCR_SSI2_BAUD_OFFSET 16
#define CCM_PCCR_SSI2_BAUD_REG CCM_PCCR0
#define CCM_PCCR_EMMA_OFFSET 15
#define CCM_PCCR_EMMA_REG CCM_PCCR0
#define CCM_PCCR_USBOTG_OFFSET 14
#define CCM_PCCR_USBOTG_REG CCM_PCCR0
#define CCM_PCCR_DMA_OFFSET 13
#define CCM_PCCR_DMA_REG CCM_PCCR0
#define CCM_PCCR_I2C1_OFFSET 12
#define CCM_PCCR_I2C1_REG CCM_PCCR0
#define CCM_PCCR_GPIO_OFFSET 11
#define CCM_PCCR_GPIO_REG CCM_PCCR0
#define CCM_PCCR_SDHC2_OFFSET 10
#define CCM_PCCR_SDHC2_REG CCM_PCCR0
#define CCM_PCCR_SDHC1_OFFSET 9
#define CCM_PCCR_SDHC1_REG CCM_PCCR0
#define CCM_PCCR_FIRI_OFFSET 8
#define CCM_PCCR_FIRI_MASK (1 << CCM_PCCR_BAUD_MASK)
#define CCM_PCCR_FIRI_REG CCM_PCCR0
#define CCM_PCCR_SSI2_IPG_OFFSET 7
#define CCM_PCCR_SSI2_REG CCM_PCCR0
#define CCM_PCCR_SSI1_IPG_OFFSET 6
#define CCM_PCCR_SSI1_REG CCM_PCCR0
#define CCM_PCCR_CSPI2_OFFSET 5
#define CCM_PCCR_CSPI2_REG CCM_PCCR0
#define CCM_PCCR_CSPI1_OFFSET 4
#define CCM_PCCR_CSPI1_REG CCM_PCCR0
#define CCM_PCCR_UART4_OFFSET 3
#define CCM_PCCR_UART4_REG CCM_PCCR0
#define CCM_PCCR_UART3_OFFSET 2
#define CCM_PCCR_UART3_REG CCM_PCCR0
#define CCM_PCCR_UART2_OFFSET 1
#define CCM_PCCR_UART2_REG CCM_PCCR0
#define CCM_PCCR_UART1_OFFSET 0
#define CCM_PCCR_UART1_REG CCM_PCCR0
#define CCM_PCCR_OWIRE_OFFSET 31
#define CCM_PCCR_OWIRE_REG CCM_PCCR1
#define CCM_PCCR_KPP_OFFSET 30
#define CCM_PCCR_KPP_REG CCM_PCCR1
#define CCM_PCCR_RTC_OFFSET 29
#define CCM_PCCR_RTC_REG CCM_PCCR1
#define CCM_PCCR_PWM_OFFSET 28
#define CCM_PCCR_PWM_REG CCM_PCCR1
#define CCM_PCCR_GPT3_OFFSET 27
#define CCM_PCCR_GPT3_REG CCM_PCCR1
#define CCM_PCCR_GPT2_OFFSET 26
#define CCM_PCCR_GPT2_REG CCM_PCCR1
#define CCM_PCCR_GPT1_OFFSET 25
#define CCM_PCCR_GPT1_REG CCM_PCCR1
#define CCM_PCCR_WDT_OFFSET 24
#define CCM_PCCR_WDT_REG CCM_PCCR1
#define CCM_PCCR_CSPI3_OFFSET 23
#define CCM_PCCR_CSPI3_REG CCM_PCCR1
#define CCM_PCCR_CSPI1_MASK (1 << CCM_PCCR_CSPI1_OFFSET)
#define CCM_PCCR_CSPI2_MASK (1 << CCM_PCCR_CSPI2_OFFSET)
#define CCM_PCCR_CSPI3_MASK (1 << CCM_PCCR_CSPI3_OFFSET)
#define CCM_PCCR_DMA_MASK (1 << CCM_PCCR_DMA_OFFSET)
#define CCM_PCCR_EMMA_MASK (1 << CCM_PCCR_EMMA_OFFSET)
#define CCM_PCCR_GPIO_MASK (1 << CCM_PCCR_GPIO_OFFSET)
#define CCM_PCCR_GPT1_MASK (1 << CCM_PCCR_GPT1_OFFSET)
#define CCM_PCCR_GPT2_MASK (1 << CCM_PCCR_GPT2_OFFSET)
#define CCM_PCCR_GPT3_MASK (1 << CCM_PCCR_GPT3_OFFSET)
#define CCM_PCCR_HCLK_BROM_MASK (1 << CCM_PCCR_HCLK_BROM_OFFSET)
#define CCM_PCCR_HCLK_CSI_MASK (1 << CCM_PCCR_HCLK_CSI_OFFSET)
#define CCM_PCCR_HCLK_DMA_MASK (1 << CCM_PCCR_HCLK_DMA_OFFSET)
#define CCM_PCCR_HCLK_EMMA_MASK (1 << CCM_PCCR_HCLK_EMMA_OFFSET)
#define CCM_PCCR_HCLK_LCDC_MASK (1 << CCM_PCCR_HCLK_LCDC_OFFSET)
#define CCM_PCCR_HCLK_SLCDC_MASK (1 << CCM_PCCR_HCLK_SLCDC_OFFSET)
#define CCM_PCCR_HCLK_USBOTG_MASK (1 << CCM_PCCR_HCLK_USBOTG_OFFSET)
#define CCM_PCCR_I2C1_MASK (1 << CCM_PCCR_I2C1_OFFSET)
#define CCM_PCCR_KPP_MASK (1 << CCM_PCCR_KPP_OFFSET)
#define CCM_PCCR_LCDC_MASK (1 << CCM_PCCR_LCDC_OFFSET)
#define CCM_PCCR_NFC_MASK (1 << CCM_PCCR_NFC_OFFSET)
#define CCM_PCCR_OWIRE_MASK (1 << CCM_PCCR_OWIRE_OFFSET)
#define CCM_PCCR_PERCLK4_MASK (1 << CCM_PCCR_PERCLK4_OFFSET)
#define CCM_PCCR_PWM_MASK (1 << CCM_PCCR_PWM_OFFSET)
#define CCM_PCCR_RTC_MASK (1 << CCM_PCCR_RTC_OFFSET)
#define CCM_PCCR_SDHC1_MASK (1 << CCM_PCCR_SDHC1_OFFSET)
#define CCM_PCCR_SDHC2_MASK (1 << CCM_PCCR_SDHC2_OFFSET)
#define CCM_PCCR_SLCDC_MASK (1 << CCM_PCCR_SLCDC_OFFSET)
#define CCM_PCCR_SSI1_BAUD_MASK (1 << CCM_PCCR_SSI1_BAUD_OFFSET)
#define CCM_PCCR_SSI1_IPG_MASK (1 << CCM_PCCR_SSI1_IPG_OFFSET)
#define CCM_PCCR_SSI2_BAUD_MASK (1 << CCM_PCCR_SSI2_BAUD_OFFSET)
#define CCM_PCCR_SSI2_IPG_MASK (1 << CCM_PCCR_SSI2_IPG_OFFSET)
#define CCM_PCCR_UART1_MASK (1 << CCM_PCCR_UART1_OFFSET)
#define CCM_PCCR_UART2_MASK (1 << CCM_PCCR_UART2_OFFSET)
#define CCM_PCCR_UART3_MASK (1 << CCM_PCCR_UART3_OFFSET)
#define CCM_PCCR_UART4_MASK (1 << CCM_PCCR_UART4_OFFSET)
#define CCM_PCCR_USBOTG_MASK (1 << CCM_PCCR_USBOTG_OFFSET)
#define CCM_PCCR_WDT_MASK (1 << CCM_PCCR_WDT_OFFSET)
#define CCM_CCSR_32KSR (1 << 15)
#define CCM_CCSR_CLKMODE1 (1 << 9)
#define CCM_CCSR_CLKMODE0 (1 << 8)
#define CCM_CCSR_CLKOSEL_OFFSET 0
#define CCM_CCSR_CLKOSEL_MASK 0x1f
#define SYS_FMCR 0x14 /* Functional Muxing Control Reg */
#define SYS_CHIP_ID 0x00 /* The offset of CHIP ID register */
#endif /* __ARCH_ARM_MACH_MX2_CRM_REGS_H__ */
arch/arm/mach-mx2/devices.c
浏览文件 @ b93a4afc
...@@ -46,65 +46,31 @@ ...@@ -46,65 +46,31 @@
* - i.MX21: 2 channel * - i.MX21: 2 channel
* - i.MX27: 3 channel * - i.MX27: 3 channel
*/ */
static struct resource mxc_spi_resources0[] = { #define DEFINE_IMX_SPI_DEVICE(n, baseaddr, irq) \
{ static struct resource mxc_spi_resources ## n[] = { \
.start = CSPI1_BASE_ADDR, { \
.end = CSPI1_BASE_ADDR + SZ_4K - 1, .start = baseaddr, \
.flags = IORESOURCE_MEM, .end = baseaddr + SZ_4K - 1, \
}, { .flags = IORESOURCE_MEM, \
.start = MXC_INT_CSPI1, }, { \
.end = MXC_INT_CSPI1, .start = irq, \
.flags = IORESOURCE_IRQ, .end = irq, \
}, .flags = IORESOURCE_IRQ, \
}; }, \
}; \
static struct resource mxc_spi_resources1[] = { \
{ struct platform_device mxc_spi_device ## n = { \
.start = CSPI2_BASE_ADDR, .name = "spi_imx", \
.end = CSPI2_BASE_ADDR + SZ_4K - 1, .id = n, \
.flags = IORESOURCE_MEM, .num_resources = ARRAY_SIZE(mxc_spi_resources ## n), \
}, { .resource = mxc_spi_resources ## n, \
.start = MXC_INT_CSPI2, }
.end = MXC_INT_CSPI2,
.flags = IORESOURCE_IRQ,
},
};
#ifdef CONFIG_MACH_MX27
static struct resource mxc_spi_resources2[] = {
{
.start = CSPI3_BASE_ADDR,
.end = CSPI3_BASE_ADDR + SZ_4K - 1,
.flags = IORESOURCE_MEM,
}, {
.start = MXC_INT_CSPI3,
.end = MXC_INT_CSPI3,
.flags = IORESOURCE_IRQ,
},
};
#endif
struct platform_device mxc_spi_device0 = {
.name = "spi_imx",
.id = 0,
.num_resources = ARRAY_SIZE(mxc_spi_resources0),
.resource = mxc_spi_resources0,
};
struct platform_device mxc_spi_device1 = { DEFINE_IMX_SPI_DEVICE(0, MX2x_CSPI1_BASE_ADDR, MX2x_INT_CSPI1);
.name = "spi_imx", DEFINE_IMX_SPI_DEVICE(1, MX2x_CSPI2_BASE_ADDR, MX2x_INT_CSPI2);
.id = 1,
.num_resources = ARRAY_SIZE(mxc_spi_resources1),
.resource = mxc_spi_resources1,
};
#ifdef CONFIG_MACH_MX27 #ifdef CONFIG_MACH_MX27
struct platform_device mxc_spi_device2 = { DEFINE_IMX_SPI_DEVICE(2, MX27_CSPI3_BASE_ADDR, MX27_INT_CSPI3);
.name = "spi_imx",
.id = 2,
.num_resources = ARRAY_SIZE(mxc_spi_resources2),
.resource = mxc_spi_resources2,
};
#endif #endif
/* /*
...@@ -112,104 +78,34 @@ struct platform_device mxc_spi_device2 = { ...@@ -112,104 +78,34 @@ struct platform_device mxc_spi_device2 = {
* - i.MX21: 3 timers * - i.MX21: 3 timers
* - i.MX27: 6 timers * - i.MX27: 6 timers
*/ */
#define DEFINE_IMX_GPT_DEVICE(n, baseaddr, irq) \
/* We use gpt0 as system timer, so do not add a device for this one */ static struct resource timer ## n ##_resources[] = { \
{ \
static struct resource timer1_resources[] = { .start = baseaddr, \
{ .end = baseaddr + SZ_4K - 1, \
.start = GPT2_BASE_ADDR, .flags = IORESOURCE_MEM, \
.end = GPT2_BASE_ADDR + 0x17, }, { \
.flags = IORESOURCE_MEM, .start = irq, \
}, { .end = irq, \
.start = MXC_INT_GPT2, .flags = IORESOURCE_IRQ, \
.end = MXC_INT_GPT2, } \
.flags = IORESOURCE_IRQ, }; \
} \
}; struct platform_device mxc_gpt ## n = { \
.name = "imx_gpt", \
struct platform_device mxc_gpt1 = { .id = n, \
.name = "imx_gpt", .num_resources = ARRAY_SIZE(timer ## n ## _resources), \
.id = 1, .resource = timer ## n ## _resources, \
.num_resources = ARRAY_SIZE(timer1_resources),
.resource = timer1_resources,
};
static struct resource timer2_resources[] = {
{
.start = GPT3_BASE_ADDR,
.end = GPT3_BASE_ADDR + 0x17,
.flags = IORESOURCE_MEM,
}, {
.start = MXC_INT_GPT3,
.end = MXC_INT_GPT3,
.flags = IORESOURCE_IRQ,
} }
};
struct platform_device mxc_gpt2 = { /* We use gpt1 as system timer, so do not add a device for this one */
.name = "imx_gpt", DEFINE_IMX_GPT_DEVICE(1, MX2x_GPT2_BASE_ADDR, MX2x_INT_GPT2);
.id = 2, DEFINE_IMX_GPT_DEVICE(2, MX2x_GPT3_BASE_ADDR, MX2x_INT_GPT3);
.num_resources = ARRAY_SIZE(timer2_resources),
.resource = timer2_resources,
};
#ifdef CONFIG_MACH_MX27 #ifdef CONFIG_MACH_MX27
static struct resource timer3_resources[] = { DEFINE_IMX_GPT_DEVICE(3, MX27_GPT4_BASE_ADDR, MX27_INT_GPT4);
{ DEFINE_IMX_GPT_DEVICE(4, MX27_GPT5_BASE_ADDR, MX27_INT_GPT5);
.start = GPT4_BASE_ADDR, DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR, MX27_INT_GPT6);
.end = GPT4_BASE_ADDR + 0x17,
.flags = IORESOURCE_MEM,
}, {
.start = MXC_INT_GPT4,
.end = MXC_INT_GPT4,
.flags = IORESOURCE_IRQ,
}
};
struct platform_device mxc_gpt3 = {
.name = "imx_gpt",
.id = 3,
.num_resources = ARRAY_SIZE(timer3_resources),
.resource = timer3_resources,
};
static struct resource timer4_resources[] = {
{
.start = GPT5_BASE_ADDR,
.end = GPT5_BASE_ADDR + 0x17,
.flags = IORESOURCE_MEM,
}, {
.start = MXC_INT_GPT5,
.end = MXC_INT_GPT5,
.flags = IORESOURCE_IRQ,
}
};
struct platform_device mxc_gpt4 = {
.name = "imx_gpt",
.id = 4,
.num_resources = ARRAY_SIZE(timer4_resources),
.resource = timer4_resources,
};
static struct resource timer5_resources[] = {
{
.start = GPT6_BASE_ADDR,
.end = GPT6_BASE_ADDR + 0x17,
.flags = IORESOURCE_MEM,
}, {
.start = MXC_INT_GPT6,
.end = MXC_INT_GPT6,
.flags = IORESOURCE_IRQ,
}
};
struct platform_device mxc_gpt5 = {
.name = "imx_gpt",
.id = 5,
.num_resources = ARRAY_SIZE(timer5_resources),
.resource = timer5_resources,
};
#endif #endif
/* /*
...@@ -220,8 +116,8 @@ struct platform_device mxc_gpt5 = { ...@@ -220,8 +116,8 @@ struct platform_device mxc_gpt5 = {
*/ */
static struct resource mxc_wdt_resources[] = { static struct resource mxc_wdt_resources[] = {
{ {
.start = WDOG_BASE_ADDR, .start = MX2x_WDOG_BASE_ADDR,
.end = WDOG_BASE_ADDR + 0x30, .end = MX2x_WDOG_BASE_ADDR + SZ_4K - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
}; };
...@@ -235,8 +131,8 @@ struct platform_device mxc_wdt = { ...@@ -235,8 +131,8 @@ struct platform_device mxc_wdt = {
static struct resource mxc_w1_master_resources[] = { static struct resource mxc_w1_master_resources[] = {
{ {
.start = OWIRE_BASE_ADDR, .start = MX2x_OWIRE_BASE_ADDR,
.end = OWIRE_BASE_ADDR + SZ_4K - 1, .end = MX2x_OWIRE_BASE_ADDR + SZ_4K - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
}; };
...@@ -248,24 +144,33 @@ struct platform_device mxc_w1_master_device = { ...@@ -248,24 +144,33 @@ struct platform_device mxc_w1_master_device = {
.resource = mxc_w1_master_resources, .resource = mxc_w1_master_resources,
}; };
static struct resource mxc_nand_resources[] = { #define DEFINE_MXC_NAND_DEVICE(pfx, baseaddr, irq) \
{ static struct resource pfx ## _nand_resources[] = { \
.start = NFC_BASE_ADDR, { \
.end = NFC_BASE_ADDR + 0xfff, .start = baseaddr, \
.flags = IORESOURCE_MEM, .end = baseaddr + SZ_4K - 1, \
}, { .flags = IORESOURCE_MEM, \
.start = MXC_INT_NANDFC, }, { \
.end = MXC_INT_NANDFC, .start = irq, \
.flags = IORESOURCE_IRQ, .end = irq, \
}, .flags = IORESOURCE_IRQ, \
}; }, \
}; \
\
struct platform_device pfx ## _nand_device = { \
.name = "mxc_nand", \
.id = 0, \
.num_resources = ARRAY_SIZE(pfx ## _nand_resources), \
.resource = pfx ## _nand_resources, \
}
struct platform_device mxc_nand_device = { #ifdef CONFIG_MACH_MX21
.name = "mxc_nand", DEFINE_MXC_NAND_DEVICE(imx21, MX21_NFC_BASE_ADDR, MX21_INT_NANDFC);
.id = 0, #endif
.num_resources = ARRAY_SIZE(mxc_nand_resources),
.resource = mxc_nand_resources, #ifdef CONFIG_MACH_MX27
}; DEFINE_MXC_NAND_DEVICE(imx27, MX27_NFC_BASE_ADDR, MX27_INT_NANDFC);
#endif
/* /*
* lcdc: * lcdc:
...@@ -275,12 +180,12 @@ struct platform_device mxc_nand_device = { ...@@ -275,12 +180,12 @@ struct platform_device mxc_nand_device = {
*/ */
static struct resource mxc_fb[] = { static struct resource mxc_fb[] = {
{ {
.start = LCDC_BASE_ADDR, .start = MX2x_LCDC_BASE_ADDR,
.end = LCDC_BASE_ADDR + 0xFFF, .end = MX2x_LCDC_BASE_ADDR + SZ_4K - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, { }, {
.start = MXC_INT_LCDC, .start = MX2x_INT_LCDC,
.end = MXC_INT_LCDC, .end = MX2x_INT_LCDC,
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
} }
}; };
...@@ -299,12 +204,12 @@ struct platform_device mxc_fb_device = { ...@@ -299,12 +204,12 @@ struct platform_device mxc_fb_device = {
#ifdef CONFIG_MACH_MX27 #ifdef CONFIG_MACH_MX27
static struct resource mxc_fec_resources[] = { static struct resource mxc_fec_resources[] = {
{ {
.start = FEC_BASE_ADDR, .start = MX27_FEC_BASE_ADDR,
.end = FEC_BASE_ADDR + 0xfff, .end = MX27_FEC_BASE_ADDR + SZ_4K - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, { }, {
.start = MXC_INT_FEC, .start = MX27_INT_FEC,
.end = MXC_INT_FEC, .end = MX27_INT_FEC,
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
}, },
}; };
...@@ -317,54 +222,40 @@ struct platform_device mxc_fec_device = { ...@@ -317,54 +222,40 @@ struct platform_device mxc_fec_device = {
}; };
#endif #endif
static struct resource mxc_i2c_1_resources[] = { #define DEFINE_IMX_I2C_DEVICE(n, baseaddr, irq) \
{ static struct resource mxc_i2c_resources ## n[] = { \
.start = I2C_BASE_ADDR, { \
.end = I2C_BASE_ADDR + 0x0fff, .start = baseaddr, \
.flags = IORESOURCE_MEM, .end = baseaddr + SZ_4K - 1, \
}, { .flags = IORESOURCE_MEM, \
.start = MXC_INT_I2C, }, { \
.end = MXC_INT_I2C, .start = irq, \
.flags = IORESOURCE_IRQ, .end = irq, \
.flags = IORESOURCE_IRQ, \
} \
}; \
\
struct platform_device mxc_i2c_device ## n = { \
.name = "imx-i2c", \
.id = n, \
.num_resources = ARRAY_SIZE(mxc_i2c_resources ## n), \
.resource = mxc_i2c_resources ## n, \
} }
};
struct platform_device mxc_i2c_device0 = { DEFINE_IMX_I2C_DEVICE(0, MX2x_I2C_BASE_ADDR, MX2x_INT_I2C);
.name = "imx-i2c",
.id = 0,
.num_resources = ARRAY_SIZE(mxc_i2c_1_resources),
.resource = mxc_i2c_1_resources,
};
#ifdef CONFIG_MACH_MX27 #ifdef CONFIG_MACH_MX27
static struct resource mxc_i2c_2_resources[] = { DEFINE_IMX_I2C_DEVICE(1, MX27_I2C2_BASE_ADDR, MX27_INT_I2C2);
{
.start = I2C2_BASE_ADDR,
.end = I2C2_BASE_ADDR + 0x0fff,
.flags = IORESOURCE_MEM,
}, {
.start = MXC_INT_I2C2,
.end = MXC_INT_I2C2,
.flags = IORESOURCE_IRQ,
}
};
struct platform_device mxc_i2c_device1 = {
.name = "imx-i2c",
.id = 1,
.num_resources = ARRAY_SIZE(mxc_i2c_2_resources),
.resource = mxc_i2c_2_resources,
};
#endif #endif
static struct resource mxc_pwm_resources[] = { static struct resource mxc_pwm_resources[] = {
{ {
.start = PWM_BASE_ADDR, .start = MX2x_PWM_BASE_ADDR,
.end = PWM_BASE_ADDR + 0x0fff, .end = MX2x_PWM_BASE_ADDR + SZ_4K - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, { }, {
.start = MXC_INT_PWM, .start = MX2x_INT_PWM,
.end = MXC_INT_PWM, .end = MX2x_INT_PWM,
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
} }
}; };
...@@ -379,73 +270,48 @@ struct platform_device mxc_pwm_device = { ...@@ -379,73 +270,48 @@ struct platform_device mxc_pwm_device = {
/* /*
* Resource definition for the MXC SDHC * Resource definition for the MXC SDHC
*/ */
static struct resource mxc_sdhc1_resources[] = { #define DEFINE_MXC_MMC_DEVICE(n, baseaddr, irq, dmareq) \
{ static struct resource mxc_sdhc_resources ## n[] = { \
.start = SDHC1_BASE_ADDR, { \
.end = SDHC1_BASE_ADDR + SZ_4K - 1, .start = baseaddr, \
.flags = IORESOURCE_MEM, .end = baseaddr + SZ_4K - 1, \
}, { .flags = IORESOURCE_MEM, \
.start = MXC_INT_SDHC1, }, { \
.end = MXC_INT_SDHC1, .start = irq, \
.flags = IORESOURCE_IRQ, .end = irq, \
}, { .flags = IORESOURCE_IRQ, \
.start = DMA_REQ_SDHC1, }, { \
.end = DMA_REQ_SDHC1, .start = dmareq, \
.flags = IORESOURCE_DMA, .end = dmareq, \
}, .flags = IORESOURCE_DMA, \
}; }, \
}; \
static u64 mxc_sdhc1_dmamask = 0xffffffffUL; \
static u64 mxc_sdhc ## n ## _dmamask = 0xffffffffUL; \
struct platform_device mxc_sdhc_device0 = { \
.name = "mxc-mmc", struct platform_device mxc_sdhc_device ## n = { \
.id = 0, .name = "mxc-mmc", \
.dev = { .id = n, \
.dma_mask = &mxc_sdhc1_dmamask, .dev = { \
.coherent_dma_mask = 0xffffffff, .dma_mask = &mxc_sdhc ## n ## _dmamask, \
}, .coherent_dma_mask = 0xffffffff, \
.num_resources = ARRAY_SIZE(mxc_sdhc1_resources), }, \
.resource = mxc_sdhc1_resources, .num_resources = ARRAY_SIZE(mxc_sdhc_resources ## n), \
}; .resource = mxc_sdhc_resources ## n, \
}
static struct resource mxc_sdhc2_resources[] = {
{
.start = SDHC2_BASE_ADDR,
.end = SDHC2_BASE_ADDR + SZ_4K - 1,
.flags = IORESOURCE_MEM,
}, {
.start = MXC_INT_SDHC2,
.end = MXC_INT_SDHC2,
.flags = IORESOURCE_IRQ,
}, {
.start = DMA_REQ_SDHC2,
.end = DMA_REQ_SDHC2,
.flags = IORESOURCE_DMA,
},
};
static u64 mxc_sdhc2_dmamask = 0xffffffffUL; DEFINE_MXC_MMC_DEVICE(0, MX2x_SDHC1_BASE_ADDR, MX2x_INT_SDHC1, MX2x_DMA_REQ_SDHC1);
DEFINE_MXC_MMC_DEVICE(1, MX2x_SDHC2_BASE_ADDR, MX2x_INT_SDHC2, MX2x_DMA_REQ_SDHC2);
struct platform_device mxc_sdhc_device1 = {
.name = "mxc-mmc",
.id = 1,
.dev = {
.dma_mask = &mxc_sdhc2_dmamask,
.coherent_dma_mask = 0xffffffff,
},
.num_resources = ARRAY_SIZE(mxc_sdhc2_resources),
.resource = mxc_sdhc2_resources,
};
#ifdef CONFIG_MACH_MX27 #ifdef CONFIG_MACH_MX27
static struct resource otg_resources[] = { static struct resource otg_resources[] = {
{ {
.start = OTG_BASE_ADDR, .start = MX27_USBOTG_BASE_ADDR,
.end = OTG_BASE_ADDR + 0x1ff, .end = MX27_USBOTG_BASE_ADDR + 0x1ff,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, { }, {
.start = MXC_INT_USB3, .start = MX27_INT_USB3,
.end = MXC_INT_USB3, .end = MX27_INT_USB3,
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
}, },
}; };
...@@ -482,12 +348,12 @@ static u64 usbh1_dmamask = 0xffffffffUL; ...@@ -482,12 +348,12 @@ static u64 usbh1_dmamask = 0xffffffffUL;
static struct resource mxc_usbh1_resources[] = { static struct resource mxc_usbh1_resources[] = {
{ {
.start = OTG_BASE_ADDR + 0x200, .start = MX27_USBOTG_BASE_ADDR + 0x200,
.end = OTG_BASE_ADDR + 0x3ff, .end = MX27_USBOTG_BASE_ADDR + 0x3ff,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, { }, {
.start = MXC_INT_USB1, .start = MX27_INT_USB1,
.end = MXC_INT_USB1, .end = MX27_INT_USB1,
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
}, },
}; };
...@@ -508,12 +374,12 @@ static u64 usbh2_dmamask = 0xffffffffUL; ...@@ -508,12 +374,12 @@ static u64 usbh2_dmamask = 0xffffffffUL;
static struct resource mxc_usbh2_resources[] = { static struct resource mxc_usbh2_resources[] = {
{ {
.start = OTG_BASE_ADDR + 0x400, .start = MX27_USBOTG_BASE_ADDR + 0x400,
.end = OTG_BASE_ADDR + 0x5ff, .end = MX27_USBOTG_BASE_ADDR + 0x5ff,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, { }, {
.start = MXC_INT_USB2, .start = MX27_INT_USB2,
.end = MXC_INT_USB2, .end = MX27_INT_USB2,
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
}, },
}; };
...@@ -530,115 +396,88 @@ struct platform_device mxc_usbh2 = { ...@@ -530,115 +396,88 @@ struct platform_device mxc_usbh2 = {
}; };
#endif #endif
static struct resource imx_ssi_resources0[] = { #define DEFINE_IMX_SSI_DMARES(_name, ssin, suffix) \
{ { \
.start = SSI1_BASE_ADDR, .name = _name, \
.end = SSI1_BASE_ADDR + 0x6F, .start = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
.flags = IORESOURCE_MEM, .end = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
}, { .flags = IORESOURCE_DMA, \
.start = MXC_INT_SSI1, }
.end = MXC_INT_SSI1,
.flags = IORESOURCE_IRQ,
}, {
.name = "tx0",
.start = DMA_REQ_SSI1_TX0,
.end = DMA_REQ_SSI1_TX0,
.flags = IORESOURCE_DMA,
}, {
.name = "rx0",
.start = DMA_REQ_SSI1_RX0,
.end = DMA_REQ_SSI1_RX0,
.flags = IORESOURCE_DMA,
}, {
.name = "tx1",
.start = DMA_REQ_SSI1_TX1,
.end = DMA_REQ_SSI1_TX1,
.flags = IORESOURCE_DMA,
}, {
.name = "rx1",
.start = DMA_REQ_SSI1_RX1,
.end = DMA_REQ_SSI1_RX1,
.flags = IORESOURCE_DMA,
},
};
static struct resource imx_ssi_resources1[] = {
{
.start = SSI2_BASE_ADDR,
.end = SSI2_BASE_ADDR + 0x6F,
.flags = IORESOURCE_MEM,
}, {
.start = MXC_INT_SSI2,
.end = MXC_INT_SSI2,
.flags = IORESOURCE_IRQ,
}, {
.name = "tx0",
.start = DMA_REQ_SSI2_TX0,
.end = DMA_REQ_SSI2_TX0,
.flags = IORESOURCE_DMA,
}, {
.name = "rx0",
.start = DMA_REQ_SSI2_RX0,
.end = DMA_REQ_SSI2_RX0,
.flags = IORESOURCE_DMA,
}, {
.name = "tx1",
.start = DMA_REQ_SSI2_TX1,
.end = DMA_REQ_SSI2_TX1,
.flags = IORESOURCE_DMA,
}, {
.name = "rx1",
.start = DMA_REQ_SSI2_RX1,
.end = DMA_REQ_SSI2_RX1,
.flags = IORESOURCE_DMA,
},
};
struct platform_device imx_ssi_device0 = { #define DEFINE_IMX_SSI_DEVICE(n, ssin, baseaddr, irq) \
.name = "imx-ssi", static struct resource imx_ssi_resources ## n[] = { \
.id = 0, { \
.num_resources = ARRAY_SIZE(imx_ssi_resources0), .start = MX2x_SSI ## ssin ## _BASE_ADDR, \
.resource = imx_ssi_resources0, .end = MX2x_SSI ## ssin ## _BASE_ADDR + 0x6f, \
}; .flags = IORESOURCE_MEM, \
}, { \
.start = MX2x_INT_SSI1, \
.end = MX2x_INT_SSI1, \
.flags = IORESOURCE_IRQ, \
}, \
DEFINE_IMX_SSI_DMARES("tx0", ssin, TX0), \
DEFINE_IMX_SSI_DMARES("rx0", ssin, RX0), \
DEFINE_IMX_SSI_DMARES("tx1", ssin, TX1), \
DEFINE_IMX_SSI_DMARES("rx1", ssin, RX1), \
}; \
\
struct platform_device imx_ssi_device ## n = { \
.name = "imx-ssi", \
.id = n, \
.num_resources = ARRAY_SIZE(imx_ssi_resources ## n), \
.resource = imx_ssi_resources ## n, \
}
struct platform_device imx_ssi_device1 = { DEFINE_IMX_SSI_DEVICE(0, 1, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
.name = "imx-ssi", DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
.id = 1,
.num_resources = ARRAY_SIZE(imx_ssi_resources1),
.resource = imx_ssi_resources1,
};
/* GPIO port description */ /* GPIO port description */
static struct mxc_gpio_port imx_gpio_ports[] = { #define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq) \
{ { \
.chip.label = "gpio-0", .chip.label = "gpio-" #n, \
.irq = MXC_INT_GPIO, .irq = _irq, \
.base = IO_ADDRESS(GPIO_BASE_ADDR), .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
.virtual_irq_start = MXC_GPIO_IRQ_START, n * 0x100), \
}, { .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
.chip.label = "gpio-1", }
.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
.virtual_irq_start = MXC_GPIO_IRQ_START + 32, #define DEFINE_MXC_GPIO_PORT(SOC, n) \
}, { { \
.chip.label = "gpio-2", .chip.label = "gpio-" #n, \
.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200), .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
.virtual_irq_start = MXC_GPIO_IRQ_START + 64, n * 0x100), \
}, { .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
.chip.label = "gpio-3", }
.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
.virtual_irq_start = MXC_GPIO_IRQ_START + 96, #define DEFINE_MXC_GPIO_PORTS(SOC, pfx) \
}, { static struct mxc_gpio_port pfx ## _gpio_ports[] = { \
.chip.label = "gpio-4", DEFINE_MXC_GPIO_PORT_IRQ(SOC, 0, SOC ## _INT_GPIO), \
.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400), DEFINE_MXC_GPIO_PORT(SOC, 1), \
.virtual_irq_start = MXC_GPIO_IRQ_START + 128, DEFINE_MXC_GPIO_PORT(SOC, 2), \
}, { DEFINE_MXC_GPIO_PORT(SOC, 3), \
.chip.label = "gpio-5", DEFINE_MXC_GPIO_PORT(SOC, 4), \
.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500), DEFINE_MXC_GPIO_PORT(SOC, 5), \
.virtual_irq_start = MXC_GPIO_IRQ_START + 160,
} }
};
#ifdef CONFIG_MACH_MX21
DEFINE_MXC_GPIO_PORTS(MX21, imx21);
#endif
#ifdef CONFIG_MACH_MX27
DEFINE_MXC_GPIO_PORTS(MX27, imx27);
#endif
int __init mxc_register_gpios(void) int __init mxc_register_gpios(void)
{ {
return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports)); #ifdef CONFIG_MACH_MX21
if (cpu_is_mx21())
return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports));
else
#endif
#ifdef CONFIG_MACH_MX27
if (cpu_is_mx27())
return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
else
#endif
return 0;
} }
arch/arm/mach-mx2/devices.h
浏览文件 @ b93a4afc
extern struct platform_device mxc_gpt1; extern struct platform_device mxc_gpt1;
extern struct platform_device mxc_gpt2; extern struct platform_device mxc_gpt2;
#ifdef CONFIG_MACH_MX27
extern struct platform_device mxc_gpt3; extern struct platform_device mxc_gpt3;
extern struct platform_device mxc_gpt4; extern struct platform_device mxc_gpt4;
extern struct platform_device mxc_gpt5; extern struct platform_device mxc_gpt5;
#endif
extern struct platform_device mxc_wdt; extern struct platform_device mxc_wdt;
extern struct platform_device mxc_uart_device0; extern struct platform_device mxc_uart_device0;
extern struct platform_device mxc_uart_device1; extern struct platform_device mxc_uart_device1;
...@@ -11,12 +13,19 @@ extern struct platform_device mxc_uart_device3; ...@@ -11,12 +13,19 @@ extern struct platform_device mxc_uart_device3;
extern struct platform_device mxc_uart_device4; extern struct platform_device mxc_uart_device4;
extern struct platform_device mxc_uart_device5; extern struct platform_device mxc_uart_device5;
extern struct platform_device mxc_w1_master_device; extern struct platform_device mxc_w1_master_device;
extern struct platform_device mxc_nand_device; #ifdef CONFIG_MACH_MX21
extern struct platform_device imx21_nand_device;
#endif
#ifdef CONFIG_MACH_MX27
extern struct platform_device imx27_nand_device;
#endif
extern struct platform_device mxc_fb_device; extern struct platform_device mxc_fb_device;
extern struct platform_device mxc_fec_device; extern struct platform_device mxc_fec_device;
extern struct platform_device mxc_pwm_device; extern struct platform_device mxc_pwm_device;
extern struct platform_device mxc_i2c_device0; extern struct platform_device mxc_i2c_device0;
#ifdef CONFIG_MACH_MX27
extern struct platform_device mxc_i2c_device1; extern struct platform_device mxc_i2c_device1;
#endif
extern struct platform_device mxc_sdhc_device0; extern struct platform_device mxc_sdhc_device0;
extern struct platform_device mxc_sdhc_device1; extern struct platform_device mxc_sdhc_device1;
extern struct platform_device mxc_otg_udc_device; extern struct platform_device mxc_otg_udc_device;
...@@ -25,6 +34,8 @@ extern struct platform_device mxc_usbh1; ...@@ -25,6 +34,8 @@ extern struct platform_device mxc_usbh1;
extern struct platform_device mxc_usbh2; extern struct platform_device mxc_usbh2;
extern struct platform_device mxc_spi_device0; extern struct platform_device mxc_spi_device0;
extern struct platform_device mxc_spi_device1; extern struct platform_device mxc_spi_device1;
#ifdef CONFIG_MACH_MX27
extern struct platform_device mxc_spi_device2; extern struct platform_device mxc_spi_device2;
#endif
extern struct platform_device imx_ssi_device0; extern struct platform_device imx_ssi_device0;
extern struct platform_device imx_ssi_device1; extern struct platform_device imx_ssi_device1;
arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c
浏览文件 @ b93a4afc
...@@ -28,7 +28,7 @@ ...@@ -28,7 +28,7 @@
#include <asm/mach/arch.h> #include <asm/mach/arch.h>
#include <mach/common.h> #include <mach/common.h>
#include <mach/iomux.h> #include <mach/iomux-mx27.h>
#include <mach/imxfb.h> #include <mach/imxfb.h>
#include <mach/hardware.h> #include <mach/hardware.h>
#include <mach/mmc.h> #include <mach/mmc.h>
......
arch/arm/mach-mx2/eukrea_cpuimx27.c → arch/arm/mach-mx2/mach-cpuimx27.c
浏览文件 @ b93a4afc
...@@ -36,7 +36,7 @@ ...@@ -36,7 +36,7 @@
#include <mach/common.h> #include <mach/common.h>
#include <mach/hardware.h> #include <mach/hardware.h>
#include <mach/i2c.h> #include <mach/i2c.h>
#include <mach/iomux.h> #include <mach/iomux-mx27.h>
#include <mach/imx-uart.h> #include <mach/imx-uart.h>
#include <mach/mxc_nand.h> #include <mach/mxc_nand.h>
...@@ -142,28 +142,28 @@ static struct i2c_board_info eukrea_cpuimx27_i2c_devices[] = { ...@@ -142,28 +142,28 @@ static struct i2c_board_info eukrea_cpuimx27_i2c_devices[] = {
#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
static struct plat_serial8250_port serial_platform_data[] = { static struct plat_serial8250_port serial_platform_data[] = {
{ {
.mapbase = (unsigned long)(CS3_BASE_ADDR + 0x200000), .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x200000),
.irq = IRQ_GPIOB(23), .irq = IRQ_GPIOB(23),
.uartclk = 14745600, .uartclk = 14745600,
.regshift = 1, .regshift = 1,
.iotype = UPIO_MEM, .iotype = UPIO_MEM,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
}, { }, {
.mapbase = (unsigned long)(CS3_BASE_ADDR + 0x400000), .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x400000),
.irq = IRQ_GPIOB(22), .irq = IRQ_GPIOB(22),
.uartclk = 14745600, .uartclk = 14745600,
.regshift = 1, .regshift = 1,
.iotype = UPIO_MEM, .iotype = UPIO_MEM,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
}, { }, {
.mapbase = (unsigned long)(CS3_BASE_ADDR + 0x800000), .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x800000),
.irq = IRQ_GPIOB(27), .irq = IRQ_GPIOB(27),
.uartclk = 14745600, .uartclk = 14745600,
.regshift = 1, .regshift = 1,
.iotype = UPIO_MEM, .iotype = UPIO_MEM,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
}, { }, {
.mapbase = (unsigned long)(CS3_BASE_ADDR + 0x1000000), .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x1000000),
.irq = IRQ_GPIOB(30), .irq = IRQ_GPIOB(30),
.uartclk = 14745600, .uartclk = 14745600,
.regshift = 1, .regshift = 1,
...@@ -189,7 +189,8 @@ static void __init eukrea_cpuimx27_init(void) ...@@ -189,7 +189,8 @@ static void __init eukrea_cpuimx27_init(void)
mxc_register_device(&mxc_uart_device0, &uart_pdata[0]); mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
mxc_register_device(&mxc_nand_device, &eukrea_cpuimx27_nand_board_info); mxc_register_device(&imx27_nand_device,
&eukrea_cpuimx27_nand_board_info);
i2c_register_board_info(0, eukrea_cpuimx27_i2c_devices, i2c_register_board_info(0, eukrea_cpuimx27_i2c_devices,
ARRAY_SIZE(eukrea_cpuimx27_i2c_devices)); ARRAY_SIZE(eukrea_cpuimx27_i2c_devices));
...@@ -224,9 +225,9 @@ static struct sys_timer eukrea_cpuimx27_timer = { ...@@ -224,9 +225,9 @@ static struct sys_timer eukrea_cpuimx27_timer = {
}; };
MACHINE_START(CPUIMX27, "EUKREA CPUIMX27") MACHINE_START(CPUIMX27, "EUKREA CPUIMX27")
.phys_io = AIPI_BASE_ADDR, .phys_io = MX27_AIPI_BASE_ADDR,
.io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100, .boot_params = MX27_PHYS_OFFSET + 0x100,
.map_io = mx27_map_io, .map_io = mx27_map_io,
.init_irq = mx27_init_irq, .init_irq = mx27_init_irq,
.init_machine = eukrea_cpuimx27_init, .init_machine = eukrea_cpuimx27_init,
......
arch/arm/mach-mx2/mx27lite.c → arch/arm/mach-mx2/mach-imx27lite.c
浏览文件 @ b93a4afc
...@@ -27,7 +27,7 @@ ...@@ -27,7 +27,7 @@
#include <mach/hardware.h> #include <mach/hardware.h>
#include <mach/common.h> #include <mach/common.h>
#include <mach/imx-uart.h> #include <mach/imx-uart.h>
#include <mach/iomux.h> #include <mach/iomux-mx27.h>
#include <mach/board-mx27lite.h> #include <mach/board-mx27lite.h>
#include "devices.h" #include "devices.h"
...@@ -85,9 +85,9 @@ static struct sys_timer mx27lite_timer = { ...@@ -85,9 +85,9 @@ static struct sys_timer mx27lite_timer = {
}; };
MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE") MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE")
.phys_io = AIPI_BASE_ADDR, .phys_io = MX27_AIPI_BASE_ADDR,
.io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100, .boot_params = MX27_PHYS_OFFSET + 0x100,
.map_io = mx27_map_io, .map_io = mx27_map_io,
.init_irq = mx27_init_irq, .init_irq = mx27_init_irq,
.init_machine = mx27lite_init, .init_machine = mx27lite_init,
......
arch/arm/mach-mx2/mx21ads.c → arch/arm/mach-mx2/mach-mx21ads.c
浏览文件 @ b93a4afc
...@@ -30,7 +30,7 @@ ...@@ -30,7 +30,7 @@
#include <asm/mach/map.h> #include <asm/mach/map.h>
#include <mach/imx-uart.h> #include <mach/imx-uart.h>
#include <mach/imxfb.h> #include <mach/imxfb.h>
#include <mach/iomux.h> #include <mach/iomux-mx21.h>
#include <mach/mxc_nand.h> #include <mach/mxc_nand.h>
#include <mach/mmc.h> #include <mach/mmc.h>
#include <mach/board-mx21ads.h> #include <mach/board-mx21ads.h>
...@@ -118,8 +118,8 @@ static struct physmap_flash_data mx21ads_flash_data = { ...@@ -118,8 +118,8 @@ static struct physmap_flash_data mx21ads_flash_data = {
}; };
static struct resource mx21ads_flash_resource = { static struct resource mx21ads_flash_resource = {
.start = CS0_BASE_ADDR, .start = MX21_CS0_BASE_ADDR,
.end = CS0_BASE_ADDR + 0x02000000 - 1, .end = MX21_CS0_BASE_ADDR + 0x02000000 - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}; };
...@@ -242,7 +242,7 @@ static struct map_desc mx21ads_io_desc[] __initdata = { ...@@ -242,7 +242,7 @@ static struct map_desc mx21ads_io_desc[] __initdata = {
*/ */
{ {
.virtual = MX21ADS_MMIO_BASE_ADDR, .virtual = MX21ADS_MMIO_BASE_ADDR,
.pfn = __phys_to_pfn(CS1_BASE_ADDR), .pfn = __phys_to_pfn(MX21_CS1_BASE_ADDR),
.length = MX21ADS_MMIO_SIZE, .length = MX21ADS_MMIO_SIZE,
.type = MT_DEVICE, .type = MT_DEVICE,
}, },
...@@ -268,7 +268,7 @@ static void __init mx21ads_board_init(void) ...@@ -268,7 +268,7 @@ static void __init mx21ads_board_init(void)
mxc_register_device(&mxc_uart_device3, &uart_pdata); mxc_register_device(&mxc_uart_device3, &uart_pdata);
mxc_register_device(&mxc_fb_device, &mx21ads_fb_data); mxc_register_device(&mxc_fb_device, &mx21ads_fb_data);
mxc_register_device(&mxc_sdhc_device0, &mx21ads_sdhc_pdata); mxc_register_device(&mxc_sdhc_device0, &mx21ads_sdhc_pdata);
mxc_register_device(&mxc_nand_device, &mx21ads_nand_board_info); mxc_register_device(&imx21_nand_device, &mx21ads_nand_board_info);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
} }
...@@ -284,9 +284,9 @@ static struct sys_timer mx21ads_timer = { ...@@ -284,9 +284,9 @@ static struct sys_timer mx21ads_timer = {
MACHINE_START(MX21ADS, "Freescale i.MX21ADS") MACHINE_START(MX21ADS, "Freescale i.MX21ADS")
/* maintainer: Freescale Semiconductor, Inc. */ /* maintainer: Freescale Semiconductor, Inc. */
.phys_io = AIPI_BASE_ADDR, .phys_io = MX21_AIPI_BASE_ADDR,
.io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, .io_pg_offst = ((MX21_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100, .boot_params = MX21_PHYS_OFFSET + 0x100,
.map_io = mx21ads_map_io, .map_io = mx21ads_map_io,
.init_irq = mx21_init_irq, .init_irq = mx21_init_irq,
.init_machine = mx21ads_board_init, .init_machine = mx21ads_board_init,
......
arch/arm/mach-mx2/mx27pdk.c → arch/arm/mach-mx2/mach-mx27_3ds.c
浏览文件 @ b93a4afc
...@@ -26,7 +26,7 @@ ...@@ -26,7 +26,7 @@
#include <mach/hardware.h> #include <mach/hardware.h>
#include <mach/common.h> #include <mach/common.h>
#include <mach/imx-uart.h> #include <mach/imx-uart.h>
#include <mach/iomux.h> #include <mach/iomux-mx27.h>
#include <mach/board-mx27pdk.h> #include <mach/board-mx27pdk.h>
#include "devices.h" #include "devices.h"
...@@ -85,9 +85,9 @@ static struct sys_timer mx27pdk_timer = { ...@@ -85,9 +85,9 @@ static struct sys_timer mx27pdk_timer = {
MACHINE_START(MX27_3DS, "Freescale MX27PDK") MACHINE_START(MX27_3DS, "Freescale MX27PDK")
/* maintainer: Freescale Semiconductor, Inc. */ /* maintainer: Freescale Semiconductor, Inc. */
.phys_io = AIPI_BASE_ADDR, .phys_io = MX27_AIPI_BASE_ADDR,
.io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100, .boot_params = MX27_PHYS_OFFSET + 0x100,
.map_io = mx27_map_io, .map_io = mx27_map_io,
.init_irq = mx27_init_irq, .init_irq = mx27_init_irq,
.init_machine = mx27pdk_init, .init_machine = mx27pdk_init,
......
arch/arm/mach-mx2/mx27ads.c → arch/arm/mach-mx2/mach-mx27ads.c
浏览文件 @ b93a4afc
...@@ -33,7 +33,7 @@ ...@@ -33,7 +33,7 @@
#include <asm/mach/map.h> #include <asm/mach/map.h>
#include <mach/gpio.h> #include <mach/gpio.h>
#include <mach/imx-uart.h> #include <mach/imx-uart.h>
#include <mach/iomux.h> #include <mach/iomux-mx27.h>
#include <mach/board-mx27ads.h> #include <mach/board-mx27ads.h>
#include <mach/mxc_nand.h> #include <mach/mxc_nand.h>
#include <mach/i2c.h> #include <mach/i2c.h>
...@@ -290,7 +290,7 @@ static void __init mx27ads_board_init(void) ...@@ -290,7 +290,7 @@ static void __init mx27ads_board_init(void)
mxc_register_device(&mxc_uart_device3, &uart_pdata[3]); mxc_register_device(&mxc_uart_device3, &uart_pdata[3]);
mxc_register_device(&mxc_uart_device4, &uart_pdata[4]); mxc_register_device(&mxc_uart_device4, &uart_pdata[4]);
mxc_register_device(&mxc_uart_device5, &uart_pdata[5]); mxc_register_device(&mxc_uart_device5, &uart_pdata[5]);
mxc_register_device(&mxc_nand_device, &mx27ads_nand_board_info); mxc_register_device(&imx27_nand_device, &mx27ads_nand_board_info);
/* only the i2c master 1 is used on this CPU card */ /* only the i2c master 1 is used on this CPU card */
i2c_register_board_info(1, mx27ads_i2c_devices, i2c_register_board_info(1, mx27ads_i2c_devices,
...@@ -320,7 +320,7 @@ static struct sys_timer mx27ads_timer = { ...@@ -320,7 +320,7 @@ static struct sys_timer mx27ads_timer = {
static struct map_desc mx27ads_io_desc[] __initdata = { static struct map_desc mx27ads_io_desc[] __initdata = {
{ {
.virtual = PBC_BASE_ADDRESS, .virtual = PBC_BASE_ADDRESS,
.pfn = __phys_to_pfn(CS4_BASE_ADDR), .pfn = __phys_to_pfn(MX27_CS4_BASE_ADDR),
.length = SZ_1M, .length = SZ_1M,
.type = MT_DEVICE, .type = MT_DEVICE,
}, },
...@@ -334,9 +334,9 @@ static void __init mx27ads_map_io(void) ...@@ -334,9 +334,9 @@ static void __init mx27ads_map_io(void)
MACHINE_START(MX27ADS, "Freescale i.MX27ADS") MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
/* maintainer: Freescale Semiconductor, Inc. */ /* maintainer: Freescale Semiconductor, Inc. */
.phys_io = AIPI_BASE_ADDR, .phys_io = MX27_AIPI_BASE_ADDR,
.io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100, .boot_params = MX27_PHYS_OFFSET + 0x100,
.map_io = mx27ads_map_io, .map_io = mx27ads_map_io,
.init_irq = mx27_init_irq, .init_irq = mx27_init_irq,
.init_machine = mx27ads_board_init, .init_machine = mx27ads_board_init,
......
arch/arm/mach-mx2/mxt_td60.c → arch/arm/mach-mx2/mach-mxt_td60.c
浏览文件 @ b93a4afc
...@@ -33,7 +33,7 @@ ...@@ -33,7 +33,7 @@
#include <asm/mach/map.h> #include <asm/mach/map.h>
#include <linux/gpio.h> #include <linux/gpio.h>
#include <mach/imx-uart.h> #include <mach/imx-uart.h>
#include <mach/iomux.h> #include <mach/iomux-mx27.h>
#include <mach/mxc_nand.h> #include <mach/mxc_nand.h>
#include <mach/i2c.h> #include <mach/i2c.h>
#include <linux/i2c/pca953x.h> #include <linux/i2c/pca953x.h>
...@@ -257,7 +257,7 @@ static void __init mxt_td60_board_init(void) ...@@ -257,7 +257,7 @@ static void __init mxt_td60_board_init(void)
mxc_register_device(&mxc_uart_device0, &uart_pdata[0]); mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
mxc_register_device(&mxc_uart_device1, &uart_pdata[1]); mxc_register_device(&mxc_uart_device1, &uart_pdata[1]);
mxc_register_device(&mxc_uart_device2, &uart_pdata[2]); mxc_register_device(&mxc_uart_device2, &uart_pdata[2]);
mxc_register_device(&mxc_nand_device, &mxt_td60_nand_board_info); mxc_register_device(&imx27_nand_device, &mxt_td60_nand_board_info);
i2c_register_board_info(0, mxt_td60_i2c_devices, i2c_register_board_info(0, mxt_td60_i2c_devices,
ARRAY_SIZE(mxt_td60_i2c_devices)); ARRAY_SIZE(mxt_td60_i2c_devices));
...@@ -284,9 +284,9 @@ static struct sys_timer mxt_td60_timer = { ...@@ -284,9 +284,9 @@ static struct sys_timer mxt_td60_timer = {
MACHINE_START(MXT_TD60, "Maxtrack i-MXT TD60") MACHINE_START(MXT_TD60, "Maxtrack i-MXT TD60")
/* maintainer: Maxtrack Industrial */ /* maintainer: Maxtrack Industrial */
.phys_io = AIPI_BASE_ADDR, .phys_io = MX27_AIPI_BASE_ADDR,
.io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100, .boot_params = MX27_PHYS_OFFSET + 0x100,
.map_io = mx27_map_io, .map_io = mx27_map_io,
.init_irq = mx27_init_irq, .init_irq = mx27_init_irq,
.init_machine = mxt_td60_board_init, .init_machine = mxt_td60_board_init,
......
arch/arm/mach-mx2/pca100.c → arch/arm/mach-mx2/mach-pca100.c
浏览文件 @ b93a4afc
...@@ -25,25 +25,36 @@ ...@@ -25,25 +25,36 @@
#include <linux/spi/spi.h> #include <linux/spi/spi.h>
#include <linux/spi/eeprom.h> #include <linux/spi/eeprom.h>
#include <linux/irq.h> #include <linux/irq.h>
#include <linux/delay.h>
#include <linux/gpio.h> #include <linux/gpio.h>
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
#include <linux/fsl_devices.h>
#include <asm/mach/arch.h> #include <asm/mach/arch.h>
#include <asm/mach-types.h> #include <asm/mach-types.h>
#include <mach/common.h> #include <mach/common.h>
#include <mach/hardware.h> #include <mach/hardware.h>
#include <mach/iomux.h> #include <mach/iomux-mx27.h>
#include <mach/i2c.h> #include <mach/i2c.h>
#include <asm/mach/time.h> #include <asm/mach/time.h>
#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE) #if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
#include <mach/spi.h> #include <mach/spi.h>
#endif #endif
#include <mach/imx-uart.h> #include <mach/imx-uart.h>
#include <mach/audmux.h>
#include <mach/ssi.h>
#include <mach/mxc_nand.h> #include <mach/mxc_nand.h>
#include <mach/irqs.h> #include <mach/irqs.h>
#include <mach/mmc.h> #include <mach/mmc.h>
#include <mach/mxc_ehci.h>
#include <mach/ulpi.h>
#include "devices.h" #include "devices.h"
#define OTG_PHY_CS_GPIO (GPIO_PORTB + 23)
#define USBH2_PHY_CS_GPIO (GPIO_PORTB + 24)
static int pca100_pins[] = { static int pca100_pins[] = {
/* UART1 */ /* UART1 */
PE12_PF_UART1_TXD, PE12_PF_UART1_TXD,
...@@ -92,6 +103,34 @@ static int pca100_pins[] = { ...@@ -92,6 +103,34 @@ static int pca100_pins[] = {
PD29_PF_CSPI1_SCLK, PD29_PF_CSPI1_SCLK,
PD30_PF_CSPI1_MISO, PD30_PF_CSPI1_MISO,
PD31_PF_CSPI1_MOSI, PD31_PF_CSPI1_MOSI,
/* OTG */
OTG_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT,
PC7_PF_USBOTG_DATA5,
PC8_PF_USBOTG_DATA6,
PC9_PF_USBOTG_DATA0,
PC10_PF_USBOTG_DATA2,
PC11_PF_USBOTG_DATA1,
PC12_PF_USBOTG_DATA4,
PC13_PF_USBOTG_DATA3,
PE0_PF_USBOTG_NXT,
PE1_PF_USBOTG_STP,
PE2_PF_USBOTG_DIR,
PE24_PF_USBOTG_CLK,
PE25_PF_USBOTG_DATA7,
/* USBH2 */
USBH2_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT,
PA0_PF_USBH2_CLK,
PA1_PF_USBH2_DIR,
PA2_PF_USBH2_DATA7,
PA3_PF_USBH2_NXT,
PA4_PF_USBH2_STP,
PD19_AF_USBH2_DATA4,
PD20_AF_USBH2_DATA3,
PD21_AF_USBH2_DATA6,
PD22_AF_USBH2_DATA0,
PD23_AF_USBH2_DATA2,
PD24_AF_USBH2_DATA1,
PD26_AF_USBH2_DATA5,
}; };
static struct imxuart_platform_data uart_pdata = { static struct imxuart_platform_data uart_pdata = {
...@@ -157,6 +196,37 @@ static struct spi_imx_master pca100_spi_0_data = { ...@@ -157,6 +196,37 @@ static struct spi_imx_master pca100_spi_0_data = {
}; };
#endif #endif
static void pca100_ac97_warm_reset(struct snd_ac97 *ac97)
{
mxc_gpio_mode(GPIO_PORTC | 20 | GPIO_GPIO | GPIO_OUT);
gpio_set_value(GPIO_PORTC + 20, 1);
udelay(2);
gpio_set_value(GPIO_PORTC + 20, 0);
mxc_gpio_mode(PC20_PF_SSI1_FS);
msleep(2);
}
static void pca100_ac97_cold_reset(struct snd_ac97 *ac97)
{
mxc_gpio_mode(GPIO_PORTC | 20 | GPIO_GPIO | GPIO_OUT); /* FS */
gpio_set_value(GPIO_PORTC + 20, 0);
mxc_gpio_mode(GPIO_PORTC | 22 | GPIO_GPIO | GPIO_OUT); /* TX */
gpio_set_value(GPIO_PORTC + 22, 0);
mxc_gpio_mode(GPIO_PORTC | 28 | GPIO_GPIO | GPIO_OUT); /* reset */
gpio_set_value(GPIO_PORTC + 28, 0);
udelay(10);
gpio_set_value(GPIO_PORTC + 28, 1);
mxc_gpio_mode(PC20_PF_SSI1_FS);
mxc_gpio_mode(PC22_PF_SSI1_TXD);
msleep(2);
}
static struct imx_ssi_platform_data pca100_ssi_pdata = {
.ac97_reset = pca100_ac97_cold_reset,
.ac97_warm_reset = pca100_ac97_warm_reset,
.flags = IMX_SSI_USE_AC97,
};
static int pca100_sdhc2_init(struct device *dev, irq_handler_t detect_irq, static int pca100_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
void *data) void *data)
{ {
...@@ -182,21 +252,79 @@ static struct imxmmc_platform_data sdhc_pdata = { ...@@ -182,21 +252,79 @@ static struct imxmmc_platform_data sdhc_pdata = {
.exit = pca100_sdhc2_exit, .exit = pca100_sdhc2_exit,
}; };
static int otg_phy_init(struct platform_device *pdev)
{
gpio_set_value(OTG_PHY_CS_GPIO, 0);
return 0;
}
static struct mxc_usbh_platform_data otg_pdata = {
.init = otg_phy_init,
.portsc = MXC_EHCI_MODE_ULPI,
.flags = MXC_EHCI_INTERFACE_DIFF_UNI,
};
static int usbh2_phy_init(struct platform_device *pdev)
{
gpio_set_value(USBH2_PHY_CS_GPIO, 0);
return 0;
}
static struct mxc_usbh_platform_data usbh2_pdata = {
.init = usbh2_phy_init,
.portsc = MXC_EHCI_MODE_ULPI,
.flags = MXC_EHCI_INTERFACE_DIFF_UNI,
};
static struct fsl_usb2_platform_data otg_device_pdata = {
.operating_mode = FSL_USB2_DR_DEVICE,
.phy_mode = FSL_USB2_PHY_ULPI,
};
static int otg_mode_host;
static int __init pca100_otg_mode(char *options)
{
if (!strcmp(options, "host"))
otg_mode_host = 1;
else if (!strcmp(options, "device"))
otg_mode_host = 0;
else
pr_info("otg_mode neither \"host\" nor \"device\". "
"Defaulting to device\n");
return 0;
}
__setup("otg_mode=", pca100_otg_mode);
static void __init pca100_init(void) static void __init pca100_init(void)
{ {
int ret; int ret;
/* SSI unit */
mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
MXC_AUDMUX_V1_PCR_SYN | /* 4wire mode */
MXC_AUDMUX_V1_PCR_TFCSEL(3) |
MXC_AUDMUX_V1_PCR_TCLKDIR | /* clock is output */
MXC_AUDMUX_V1_PCR_RXDSEL(3));
mxc_audmux_v1_configure_port(3,
MXC_AUDMUX_V1_PCR_SYN | /* 4wire mode */
MXC_AUDMUX_V1_PCR_TFCSEL(0) |
MXC_AUDMUX_V1_PCR_TFSDIR |
MXC_AUDMUX_V1_PCR_RXDSEL(0));
ret = mxc_gpio_setup_multiple_pins(pca100_pins, ret = mxc_gpio_setup_multiple_pins(pca100_pins,
ARRAY_SIZE(pca100_pins), "PCA100"); ARRAY_SIZE(pca100_pins), "PCA100");
if (ret) if (ret)
printk(KERN_ERR "pca100: Failed to setup pins (%d)\n", ret); printk(KERN_ERR "pca100: Failed to setup pins (%d)\n", ret);
mxc_register_device(&imx_ssi_device0, &pca100_ssi_pdata);
mxc_register_device(&mxc_uart_device0, &uart_pdata); mxc_register_device(&mxc_uart_device0, &uart_pdata);
mxc_gpio_mode(GPIO_PORTC | 29 | GPIO_GPIO | GPIO_IN); mxc_gpio_mode(GPIO_PORTC | 29 | GPIO_GPIO | GPIO_IN);
mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata); mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata);
mxc_register_device(&mxc_nand_device, &pca100_nand_board_info); mxc_register_device(&imx27_nand_device, &pca100_nand_board_info);
/* only the i2c master 1 is used on this CPU card */ /* only the i2c master 1 is used on this CPU card */
i2c_register_board_info(1, pca100_i2c_devices, i2c_register_board_info(1, pca100_i2c_devices,
...@@ -220,6 +348,29 @@ static void __init pca100_init(void) ...@@ -220,6 +348,29 @@ static void __init pca100_init(void)
mxc_register_device(&mxc_spi_device0, &pca100_spi_0_data); mxc_register_device(&mxc_spi_device0, &pca100_spi_0_data);
#endif #endif
gpio_request(OTG_PHY_CS_GPIO, "usb-otg-cs");
gpio_direction_output(OTG_PHY_CS_GPIO, 1);
gpio_request(USBH2_PHY_CS_GPIO, "usb-host2-cs");
gpio_direction_output(USBH2_PHY_CS_GPIO, 1);
#if defined(CONFIG_USB_ULPI)
if (otg_mode_host) {
otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
mxc_register_device(&mxc_otg_host, &otg_pdata);
}
usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
mxc_register_device(&mxc_usbh2, &usbh2_pdata);
#endif
if (!otg_mode_host) {
gpio_set_value(OTG_PHY_CS_GPIO, 0);
mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
}
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
} }
...@@ -233,9 +384,9 @@ static struct sys_timer pca100_timer = { ...@@ -233,9 +384,9 @@ static struct sys_timer pca100_timer = {
}; };
MACHINE_START(PCA100, "phyCARD-i.MX27") MACHINE_START(PCA100, "phyCARD-i.MX27")
.phys_io = AIPI_BASE_ADDR, .phys_io = MX27_AIPI_BASE_ADDR,
.io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100, .boot_params = MX27_PHYS_OFFSET + 0x100,
.map_io = mx27_map_io, .map_io = mx27_map_io,
.init_irq = mx27_init_irq, .init_irq = mx27_init_irq,
.init_machine = pca100_init, .init_machine = pca100_init,
......
arch/arm/mach-mx2/pcm038.c → arch/arm/mach-mx2/mach-pcm038.c
浏览文件 @ b93a4afc
...@@ -36,10 +36,12 @@ ...@@ -36,10 +36,12 @@
#include <mach/common.h> #include <mach/common.h>
#include <mach/hardware.h> #include <mach/hardware.h>
#include <mach/i2c.h> #include <mach/i2c.h>
#include <mach/iomux.h> #include <mach/iomux-mx27.h>
#include <mach/imx-uart.h> #include <mach/imx-uart.h>
#include <mach/mxc_nand.h> #include <mach/mxc_nand.h>
#include <mach/spi.h> #include <mach/spi.h>
#include <mach/mxc_ehci.h>
#include <mach/ulpi.h>
#include "devices.h" #include "devices.h"
...@@ -96,6 +98,19 @@ static int pcm038_pins[] = { ...@@ -96,6 +98,19 @@ static int pcm038_pins[] = {
PC17_PF_SSI4_RXD, PC17_PF_SSI4_RXD,
PC18_PF_SSI4_TXD, PC18_PF_SSI4_TXD,
PC19_PF_SSI4_CLK, PC19_PF_SSI4_CLK,
/* USB host */
PA0_PF_USBH2_CLK,
PA1_PF_USBH2_DIR,
PA2_PF_USBH2_DATA7,
PA3_PF_USBH2_NXT,
PA4_PF_USBH2_STP,
PD19_AF_USBH2_DATA4,
PD20_AF_USBH2_DATA3,
PD21_AF_USBH2_DATA6,
PD22_AF_USBH2_DATA0,
PD23_AF_USBH2_DATA2,
PD24_AF_USBH2_DATA1,
PD26_AF_USBH2_DATA5,
}; };
/* /*
...@@ -108,8 +123,8 @@ static struct platdata_mtd_ram pcm038_sram_data = { ...@@ -108,8 +123,8 @@ static struct platdata_mtd_ram pcm038_sram_data = {
}; };
static struct resource pcm038_sram_resource = { static struct resource pcm038_sram_resource = {
.start = CS1_BASE_ADDR, .start = MX27_CS1_BASE_ADDR,
.end = CS1_BASE_ADDR + 512 * 1024 - 1, .end = MX27_CS1_BASE_ADDR + 512 * 1024 - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}; };
...@@ -173,9 +188,7 @@ static struct platform_device *platform_devices[] __initdata = { ...@@ -173,9 +188,7 @@ static struct platform_device *platform_devices[] __initdata = {
* setup other stuffs to access the sram. */ * setup other stuffs to access the sram. */
static void __init pcm038_init_sram(void) static void __init pcm038_init_sram(void)
{ {
__raw_writel(0x0000d843, CSCR_U(1)); mx27_setup_weimcs(1, 0x0000d843, 0x22252521, 0x22220a00);
__raw_writel(0x22252521, CSCR_L(1));
__raw_writel(0x22220a00, CSCR_A(1));
} }
static struct imxi2c_platform_data pcm038_i2c_1_data = { static struct imxi2c_platform_data pcm038_i2c_1_data = {
...@@ -279,6 +292,11 @@ static struct spi_board_info pcm038_spi_board_info[] __initdata = { ...@@ -279,6 +292,11 @@ static struct spi_board_info pcm038_spi_board_info[] __initdata = {
} }
}; };
static struct mxc_usbh_platform_data usbh2_pdata = {
.portsc = MXC_EHCI_MODE_ULPI,
.flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI,
};
static void __init pcm038_init(void) static void __init pcm038_init(void)
{ {
mxc_gpio_setup_multiple_pins(pcm038_pins, ARRAY_SIZE(pcm038_pins), mxc_gpio_setup_multiple_pins(pcm038_pins, ARRAY_SIZE(pcm038_pins),
...@@ -291,7 +309,7 @@ static void __init pcm038_init(void) ...@@ -291,7 +309,7 @@ static void __init pcm038_init(void)
mxc_register_device(&mxc_uart_device2, &uart_pdata[2]); mxc_register_device(&mxc_uart_device2, &uart_pdata[2]);
mxc_gpio_mode(PE16_AF_OWIRE); mxc_gpio_mode(PE16_AF_OWIRE);
mxc_register_device(&mxc_nand_device, &pcm038_nand_board_info); mxc_register_device(&imx27_nand_device, &pcm038_nand_board_info);
/* only the i2c master 1 is used on this CPU card */ /* only the i2c master 1 is used on this CPU card */
i2c_register_board_info(1, pcm038_i2c_devices, i2c_register_board_info(1, pcm038_i2c_devices,
...@@ -311,6 +329,8 @@ static void __init pcm038_init(void) ...@@ -311,6 +329,8 @@ static void __init pcm038_init(void)
spi_register_board_info(pcm038_spi_board_info, spi_register_board_info(pcm038_spi_board_info,
ARRAY_SIZE(pcm038_spi_board_info)); ARRAY_SIZE(pcm038_spi_board_info));
mxc_register_device(&mxc_usbh2, &usbh2_pdata);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
#ifdef CONFIG_MACH_PCM970_BASEBOARD #ifdef CONFIG_MACH_PCM970_BASEBOARD
...@@ -328,9 +348,9 @@ static struct sys_timer pcm038_timer = { ...@@ -328,9 +348,9 @@ static struct sys_timer pcm038_timer = {
}; };
MACHINE_START(PCM038, "phyCORE-i.MX27") MACHINE_START(PCM038, "phyCORE-i.MX27")
.phys_io = AIPI_BASE_ADDR, .phys_io = MX27_AIPI_BASE_ADDR,
.io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100, .boot_params = MX27_PHYS_OFFSET + 0x100,
.map_io = mx27_map_io, .map_io = mx27_map_io,
.init_irq = mx27_init_irq, .init_irq = mx27_init_irq,
.init_machine = pcm038_init, .init_machine = pcm038_init,
......
arch/arm/mach-mx2/mm-imx21.c 0 → 100644
浏览文件 @ b93a4afc
/*
* arch/arm/mach-mx2/mm-imx21.c
*
* Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#include <linux/mm.h>
#include <linux/init.h>
#include <mach/hardware.h>
#include <mach/common.h>
#include <asm/pgtable.h>
#include <asm/mach/map.h>
/* MX21 memory map definition */
static struct map_desc imx21_io_desc[] __initdata = {
/*
* this fixed mapping covers:
* - AIPI1
* - AIPI2
* - AITC
* - ROM Patch
* - and some reserved space
*/
{
.virtual = MX21_AIPI_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX21_AIPI_BASE_ADDR),
.length = MX21_AIPI_SIZE,
.type = MT_DEVICE
},
/*
* this fixed mapping covers:
* - CSI
* - ATA
*/
{
.virtual = MX21_SAHB1_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX21_SAHB1_BASE_ADDR),
.length = MX21_SAHB1_SIZE,
.type = MT_DEVICE
},
/*
* this fixed mapping covers:
* - EMI
*/
{
.virtual = MX21_X_MEMC_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX21_X_MEMC_BASE_ADDR),
.length = MX21_X_MEMC_SIZE,
.type = MT_DEVICE
},
};
/*
* Initialize the memory map. It is called during the
* system startup to create static physical to virtual
* memory map for the IO modules.
*/
void __init mx21_map_io(void)
{
mxc_set_cpu_type(MXC_CPU_MX21);
mxc_arch_reset_init(MX21_IO_ADDRESS(MX21_WDOG_BASE_ADDR));
iotable_init(imx21_io_desc, ARRAY_SIZE(imx21_io_desc));
}
void __init mx21_init_irq(void)
{
mxc_init_irq(MX21_IO_ADDRESS(MX21_AVIC_BASE_ADDR));
}
arch/arm/mach-mx2/generic.c → arch/arm/mach-mx2/mm-imx27.c
浏览文件 @ b93a4afc
/* /*
* generic.c * arch/arm/mach-mx2/mm-imx27.c
* *
* Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
* *
...@@ -26,7 +26,7 @@ ...@@ -26,7 +26,7 @@
#include <asm/mach/map.h> #include <asm/mach/map.h>
/* MX27 memory map definition */ /* MX27 memory map definition */
static struct map_desc mxc_io_desc[] __initdata = { static struct map_desc imx27_io_desc[] __initdata = {
/* /*
* this fixed mapping covers: * this fixed mapping covers:
* - AIPI1 * - AIPI1
...@@ -36,9 +36,9 @@ static struct map_desc mxc_io_desc[] __initdata = { ...@@ -36,9 +36,9 @@ static struct map_desc mxc_io_desc[] __initdata = {
* - and some reserved space * - and some reserved space
*/ */
{ {
.virtual = AIPI_BASE_ADDR_VIRT, .virtual = MX27_AIPI_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(AIPI_BASE_ADDR), .pfn = __phys_to_pfn(MX27_AIPI_BASE_ADDR),
.length = AIPI_SIZE, .length = MX27_AIPI_SIZE,
.type = MT_DEVICE .type = MT_DEVICE
}, },
/* /*
...@@ -47,9 +47,9 @@ static struct map_desc mxc_io_desc[] __initdata = { ...@@ -47,9 +47,9 @@ static struct map_desc mxc_io_desc[] __initdata = {
* - ATA * - ATA
*/ */
{ {
.virtual = SAHB1_BASE_ADDR_VIRT, .virtual = MX27_SAHB1_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(SAHB1_BASE_ADDR), .pfn = __phys_to_pfn(MX27_SAHB1_BASE_ADDR),
.length = SAHB1_SIZE, .length = MX27_SAHB1_SIZE,
.type = MT_DEVICE .type = MT_DEVICE
}, },
/* /*
...@@ -57,11 +57,11 @@ static struct map_desc mxc_io_desc[] __initdata = { ...@@ -57,11 +57,11 @@ static struct map_desc mxc_io_desc[] __initdata = {
* - EMI * - EMI
*/ */
{ {
.virtual = X_MEMC_BASE_ADDR_VIRT, .virtual = MX27_X_MEMC_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(X_MEMC_BASE_ADDR), .pfn = __phys_to_pfn(MX27_X_MEMC_BASE_ADDR),
.length = X_MEMC_SIZE, .length = MX27_X_MEMC_SIZE,
.type = MT_DEVICE .type = MT_DEVICE
} },
}; };
/* /*
...@@ -69,29 +69,15 @@ static struct map_desc mxc_io_desc[] __initdata = { ...@@ -69,29 +69,15 @@ static struct map_desc mxc_io_desc[] __initdata = {
* system startup to create static physical to virtual * system startup to create static physical to virtual
* memory map for the IO modules. * memory map for the IO modules.
*/ */
void __init mx21_map_io(void)
{
mxc_set_cpu_type(MXC_CPU_MX21);
mxc_arch_reset_init(IO_ADDRESS(WDOG_BASE_ADDR));
iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
}
void __init mx27_map_io(void) void __init mx27_map_io(void)
{ {
mxc_set_cpu_type(MXC_CPU_MX27); mxc_set_cpu_type(MXC_CPU_MX27);
mxc_arch_reset_init(IO_ADDRESS(WDOG_BASE_ADDR)); mxc_arch_reset_init(MX27_IO_ADDRESS(MX27_WDOG_BASE_ADDR));
iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); iotable_init(imx27_io_desc, ARRAY_SIZE(imx27_io_desc));
} }
void __init mx27_init_irq(void) void __init mx27_init_irq(void)
{ {
mxc_init_irq(IO_ADDRESS(AVIC_BASE_ADDR)); mxc_init_irq(MX27_IO_ADDRESS(MX27_AVIC_BASE_ADDR));
} }
void __init mx21_init_irq(void)
{
mx27_init_irq();
}
arch/arm/mach-mx2/pcm970-baseboard.c
浏览文件 @ b93a4afc
...@@ -24,7 +24,7 @@ ...@@ -24,7 +24,7 @@
#include <asm/mach/arch.h> #include <asm/mach/arch.h>
#include <mach/common.h> #include <mach/common.h>
#include <mach/iomux.h> #include <mach/iomux-mx27.h>
#include <mach/imxfb.h> #include <mach/imxfb.h>
#include <mach/hardware.h> #include <mach/hardware.h>
#include <mach/mmc.h> #include <mach/mmc.h>
...@@ -190,8 +190,8 @@ static struct imx_fb_platform_data pcm038_fb_data = { ...@@ -190,8 +190,8 @@ static struct imx_fb_platform_data pcm038_fb_data = {
static struct resource pcm970_sja1000_resources[] = { static struct resource pcm970_sja1000_resources[] = {
{ {
.start = CS4_BASE_ADDR, .start = MX27_CS4_BASE_ADDR,
.end = CS4_BASE_ADDR + 0x100 - 1, .end = MX27_CS4_BASE_ADDR + 0x100 - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, { }, {
.start = IRQ_GPIOE(19), .start = IRQ_GPIOE(19),
......
arch/arm/mach-mx2/serial.c
浏览文件 @ b93a4afc
...@@ -26,12 +26,12 @@ ...@@ -26,12 +26,12 @@
static struct resource uart0[] = { static struct resource uart0[] = {
{ {
.start = UART1_BASE_ADDR, .start = MX2x_UART1_BASE_ADDR,
.end = UART1_BASE_ADDR + 0x0B5, .end = MX2x_UART1_BASE_ADDR + 0x0B5,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, { }, {
.start = MXC_INT_UART1, .start = MX2x_INT_UART1,
.end = MXC_INT_UART1, .end = MX2x_INT_UART1,
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
}, },
}; };
...@@ -45,12 +45,12 @@ struct platform_device mxc_uart_device0 = { ...@@ -45,12 +45,12 @@ struct platform_device mxc_uart_device0 = {
static struct resource uart1[] = { static struct resource uart1[] = {
{ {
.start = UART2_BASE_ADDR, .start = MX2x_UART2_BASE_ADDR,
.end = UART2_BASE_ADDR + 0x0B5, .end = MX2x_UART2_BASE_ADDR + 0x0B5,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, { }, {
.start = MXC_INT_UART2, .start = MX2x_INT_UART2,
.end = MXC_INT_UART2, .end = MX2x_INT_UART2,
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
}, },
}; };
...@@ -64,12 +64,12 @@ struct platform_device mxc_uart_device1 = { ...@@ -64,12 +64,12 @@ struct platform_device mxc_uart_device1 = {
static struct resource uart2[] = { static struct resource uart2[] = {
{ {
.start = UART3_BASE_ADDR, .start = MX2x_UART3_BASE_ADDR,
.end = UART3_BASE_ADDR + 0x0B5, .end = MX2x_UART3_BASE_ADDR + 0x0B5,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, { }, {
.start = MXC_INT_UART3, .start = MX2x_INT_UART3,
.end = MXC_INT_UART3, .end = MX2x_INT_UART3,
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
}, },
}; };
...@@ -83,12 +83,12 @@ struct platform_device mxc_uart_device2 = { ...@@ -83,12 +83,12 @@ struct platform_device mxc_uart_device2 = {
static struct resource uart3[] = { static struct resource uart3[] = {
{ {
.start = UART4_BASE_ADDR, .start = MX2x_UART4_BASE_ADDR,
.end = UART4_BASE_ADDR + 0x0B5, .end = MX2x_UART4_BASE_ADDR + 0x0B5,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, { }, {
.start = MXC_INT_UART4, .start = MX2x_INT_UART4,
.end = MXC_INT_UART4, .end = MX2x_INT_UART4,
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
}, },
}; };
...@@ -103,12 +103,12 @@ struct platform_device mxc_uart_device3 = { ...@@ -103,12 +103,12 @@ struct platform_device mxc_uart_device3 = {
#ifdef CONFIG_MACH_MX27 #ifdef CONFIG_MACH_MX27
static struct resource uart4[] = { static struct resource uart4[] = {
{ {
.start = UART5_BASE_ADDR, .start = MX27_UART5_BASE_ADDR,
.end = UART5_BASE_ADDR + 0x0B5, .end = MX27_UART5_BASE_ADDR + 0x0B5,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, { }, {
.start = MXC_INT_UART5, .start = MX27_INT_UART5,
.end = MXC_INT_UART5, .end = MX27_INT_UART5,
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
}, },
}; };
...@@ -122,12 +122,12 @@ struct platform_device mxc_uart_device4 = { ...@@ -122,12 +122,12 @@ struct platform_device mxc_uart_device4 = {
static struct resource uart5[] = { static struct resource uart5[] = {
{ {
.start = UART6_BASE_ADDR, .start = MX27_UART6_BASE_ADDR,
.end = UART6_BASE_ADDR + 0x0B5, .end = MX27_UART6_BASE_ADDR + 0x0B5,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, { }, {
.start = MXC_INT_UART6, .start = MX27_INT_UART6,
.end = MXC_INT_UART6, .end = MX27_INT_UART6,
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
}, },
}; };
......
arch/arm/mach-mx25/Kconfig
浏览文件 @ b93a4afc
...@@ -3,7 +3,6 @@ if ARCH_MX25 ...@@ -3,7 +3,6 @@ if ARCH_MX25
comment "MX25 platforms:" comment "MX25 platforms:"
config MACH_MX25_3DS config MACH_MX25_3DS
select ARCH_MXC_IOMUX_V3
bool "Support MX25PDK (3DS) Platform" bool "Support MX25PDK (3DS) Platform"
endif endif
arch/arm/mach-mx25/Makefile
浏览文件 @ b93a4afc
obj-y := mm.o devices.o obj-y := mm.o devices.o
obj-$(CONFIG_ARCH_MX25) += clock.o obj-$(CONFIG_ARCH_MX25) += clock.o
obj-$(CONFIG_MACH_MX25_3DS) += mx25pdk.o obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25pdk.o
arch/arm/mach-mx25/clock.c
浏览文件 @ b93a4afc
...@@ -124,6 +124,11 @@ static unsigned long get_rate_gpt(struct clk *clk) ...@@ -124,6 +124,11 @@ static unsigned long get_rate_gpt(struct clk *clk)
return get_rate_per(5); return get_rate_per(5);
} }
static unsigned long get_rate_lcdc(struct clk *clk)
{
return get_rate_per(7);
}
static unsigned long get_rate_otg(struct clk *clk) static unsigned long get_rate_otg(struct clk *clk)
{ {
return 48000000; /* FIXME */ return 48000000; /* FIXME */
...@@ -167,6 +172,8 @@ DEFINE_CLOCK(cspi1_clk, 0, CCM_CGCR1, 5, get_rate_ipg, NULL, NULL); ...@@ -167,6 +172,8 @@ DEFINE_CLOCK(cspi1_clk, 0, CCM_CGCR1, 5, get_rate_ipg, NULL, NULL);
DEFINE_CLOCK(cspi2_clk, 0, CCM_CGCR1, 6, get_rate_ipg, NULL, NULL); DEFINE_CLOCK(cspi2_clk, 0, CCM_CGCR1, 6, get_rate_ipg, NULL, NULL);
DEFINE_CLOCK(cspi3_clk, 0, CCM_CGCR1, 7, get_rate_ipg, NULL, NULL); DEFINE_CLOCK(cspi3_clk, 0, CCM_CGCR1, 7, get_rate_ipg, NULL, NULL);
DEFINE_CLOCK(fec_ahb_clk, 0, CCM_CGCR0, 23, NULL, NULL, NULL); DEFINE_CLOCK(fec_ahb_clk, 0, CCM_CGCR0, 23, NULL, NULL, NULL);
DEFINE_CLOCK(lcdc_ahb_clk, 0, CCM_CGCR0, 24, NULL, NULL, NULL);
DEFINE_CLOCK(lcdc_per_clk, 0, CCM_CGCR0, 7, NULL, NULL, &lcdc_ahb_clk);
DEFINE_CLOCK(uart1_clk, 0, CCM_CGCR2, 14, get_rate_uart, NULL, &uart_per_clk); DEFINE_CLOCK(uart1_clk, 0, CCM_CGCR2, 14, get_rate_uart, NULL, &uart_per_clk);
DEFINE_CLOCK(uart2_clk, 0, CCM_CGCR2, 15, get_rate_uart, NULL, &uart_per_clk); DEFINE_CLOCK(uart2_clk, 0, CCM_CGCR2, 15, get_rate_uart, NULL, &uart_per_clk);
DEFINE_CLOCK(uart3_clk, 0, CCM_CGCR2, 16, get_rate_uart, NULL, &uart_per_clk); DEFINE_CLOCK(uart3_clk, 0, CCM_CGCR2, 16, get_rate_uart, NULL, &uart_per_clk);
...@@ -182,6 +189,8 @@ DEFINE_CLOCK(kpp_clk, 0, CCM_CGCR1, 28, get_rate_ipg, NULL, NULL); ...@@ -182,6 +189,8 @@ DEFINE_CLOCK(kpp_clk, 0, CCM_CGCR1, 28, get_rate_ipg, NULL, NULL);
DEFINE_CLOCK(tsc_clk, 0, CCM_CGCR2, 13, get_rate_ipg, NULL, NULL); DEFINE_CLOCK(tsc_clk, 0, CCM_CGCR2, 13, get_rate_ipg, NULL, NULL);
DEFINE_CLOCK(i2c_clk, 0, CCM_CGCR0, 6, get_rate_i2c, NULL, NULL); DEFINE_CLOCK(i2c_clk, 0, CCM_CGCR0, 6, get_rate_i2c, NULL, NULL);
DEFINE_CLOCK(fec_clk, 0, CCM_CGCR1, 15, get_rate_ipg, NULL, &fec_ahb_clk); DEFINE_CLOCK(fec_clk, 0, CCM_CGCR1, 15, get_rate_ipg, NULL, &fec_ahb_clk);
DEFINE_CLOCK(dryice_clk, 0, CCM_CGCR1, 8, get_rate_ipg, NULL, NULL);
DEFINE_CLOCK(lcdc_clk, 0, CCM_CGCR1, 29, get_rate_lcdc, NULL, &lcdc_per_clk);
#define _REGISTER_CLOCK(d, n, c) \ #define _REGISTER_CLOCK(d, n, c) \
{ \ { \
...@@ -214,6 +223,8 @@ static struct clk_lookup lookups[] = { ...@@ -214,6 +223,8 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK("imx-i2c.1", NULL, i2c_clk) _REGISTER_CLOCK("imx-i2c.1", NULL, i2c_clk)
_REGISTER_CLOCK("imx-i2c.2", NULL, i2c_clk) _REGISTER_CLOCK("imx-i2c.2", NULL, i2c_clk)
_REGISTER_CLOCK("fec.0", NULL, fec_clk) _REGISTER_CLOCK("fec.0", NULL, fec_clk)
_REGISTER_CLOCK("imxdi_rtc.0", NULL, dryice_clk)
_REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
}; };
int __init mx25_clocks_init(void) int __init mx25_clocks_init(void)
...@@ -231,6 +242,9 @@ int __init mx25_clocks_init(void) ...@@ -231,6 +242,9 @@ int __init mx25_clocks_init(void)
__raw_writel((0xf << 16) | (3 << 26), CRM_BASE + CCM_CGCR1); __raw_writel((0xf << 16) | (3 << 26), CRM_BASE + CCM_CGCR1);
__raw_writel((1 << 5), CRM_BASE + CCM_CGCR2); __raw_writel((1 << 5), CRM_BASE + CCM_CGCR2);
/* Clock source for lcdc is upll */
__raw_writel(__raw_readl(CRM_BASE+0x64) | (1 << 7), CRM_BASE + 0x64);
mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54); mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54);
return 0; return 0;
......
arch/arm/mach-mx25/devices.c
浏览文件 @ b93a4afc
...@@ -438,3 +438,65 @@ struct platform_device mx25_fec_device = { ...@@ -438,3 +438,65 @@ struct platform_device mx25_fec_device = {
.num_resources = ARRAY_SIZE(mx25_fec_resources), .num_resources = ARRAY_SIZE(mx25_fec_resources),
.resource = mx25_fec_resources, .resource = mx25_fec_resources,
}; };
static struct resource mxc_nand_resources[] = {
{
.start = MX25_NFC_BASE_ADDR,
.end = MX25_NFC_BASE_ADDR + 0x1fff,
.flags = IORESOURCE_MEM,
},
{
.start = MX25_INT_NANDFC,
.end = MX25_INT_NANDFC,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_nand_device = {
.name = "mxc_nand",
.id = 0,
.num_resources = ARRAY_SIZE(mxc_nand_resources),
.resource = mxc_nand_resources,
};
static struct resource mx25_rtc_resources[] = {
{
.start = MX25_DRYICE_BASE_ADDR,
.end = MX25_DRYICE_BASE_ADDR + 0x40,
.flags = IORESOURCE_MEM,
},
{
.start = MX25_INT_DRYICE,
.flags = IORESOURCE_IRQ
},
};
struct platform_device mx25_rtc_device = {
.name = "imxdi_rtc",
.id = 0,
.num_resources = ARRAY_SIZE(mx25_rtc_resources),
.resource = mx25_rtc_resources,
};
static struct resource mx25_fb_resources[] = {
{
.start = MX25_LCDC_BASE_ADDR,
.end = MX25_LCDC_BASE_ADDR + 0xfff,
.flags = IORESOURCE_MEM,
},
{
.start = MX25_INT_LCDC,
.end = MX25_INT_LCDC,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mx25_fb_device = {
.name = "imx-fb",
.id = 0,
.resource = mx25_fb_resources,
.num_resources = ARRAY_SIZE(mx25_fb_resources),
.dev = {
.coherent_dma_mask = 0xFFFFFFFF,
},
};
arch/arm/mach-mx25/devices.h
浏览文件 @ b93a4afc
...@@ -18,3 +18,6 @@ extern struct platform_device mxc_i2c_device0; ...@@ -18,3 +18,6 @@ extern struct platform_device mxc_i2c_device0;
extern struct platform_device mxc_i2c_device1; extern struct platform_device mxc_i2c_device1;
extern struct platform_device mxc_i2c_device2; extern struct platform_device mxc_i2c_device2;
extern struct platform_device mx25_fec_device; extern struct platform_device mx25_fec_device;
extern struct platform_device mxc_nand_device;
extern struct platform_device mx25_rtc_device;
extern struct platform_device mx25_fb_device;
arch/arm/mach-mx25/mx25pdk.c → arch/arm/mach-mx25/mach-mx25pdk.c
浏览文件 @ b93a4afc
...@@ -35,8 +35,9 @@ ...@@ -35,8 +35,9 @@
#include <mach/imx-uart.h> #include <mach/imx-uart.h>
#include <mach/mx25.h> #include <mach/mx25.h>
#include <mach/mxc_nand.h> #include <mach/mxc_nand.h>
#include <mach/imxfb.h>
#include "devices.h" #include "devices.h"
#include <mach/iomux.h> #include <mach/iomux-mx25.h>
static struct imxuart_platform_data uart_pdata = { static struct imxuart_platform_data uart_pdata = {
.flags = IMXUART_HAVE_RTSCTS, .flags = IMXUART_HAVE_RTSCTS,
...@@ -54,6 +55,31 @@ static struct pad_desc mx25pdk_pads[] = { ...@@ -54,6 +55,31 @@ static struct pad_desc mx25pdk_pads[] = {
MX25_PAD_FEC_TX_CLK__FEC_TX_CLK, MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
MX25_PAD_A17__GPIO_2_3, /* FEC_EN, GPIO 35 */ MX25_PAD_A17__GPIO_2_3, /* FEC_EN, GPIO 35 */
MX25_PAD_D12__GPIO_4_8, /* FEC_RESET_B, GPIO 104 */ MX25_PAD_D12__GPIO_4_8, /* FEC_RESET_B, GPIO 104 */
/* LCD */
MX25_PAD_LD0__LD0,
MX25_PAD_LD1__LD1,
MX25_PAD_LD2__LD2,
MX25_PAD_LD3__LD3,
MX25_PAD_LD4__LD4,
MX25_PAD_LD5__LD5,
MX25_PAD_LD6__LD6,
MX25_PAD_LD7__LD7,
MX25_PAD_LD8__LD8,
MX25_PAD_LD9__LD9,
MX25_PAD_LD10__LD10,
MX25_PAD_LD11__LD11,
MX25_PAD_LD12__LD12,
MX25_PAD_LD13__LD13,
MX25_PAD_LD14__LD14,
MX25_PAD_LD15__LD15,
MX25_PAD_GPIO_E__LD16,
MX25_PAD_GPIO_F__LD17,
MX25_PAD_HSYNC__HSYNC,
MX25_PAD_VSYNC__VSYNC,
MX25_PAD_LSCLK__LSCLK,
MX25_PAD_OE_ACD__OE_ACD,
MX25_PAD_CONTRAST__CONTRAST,
}; };
static struct fec_platform_data mx25_fec_pdata = { static struct fec_platform_data mx25_fec_pdata = {
...@@ -77,6 +103,40 @@ static void __init mx25pdk_fec_reset(void) ...@@ -77,6 +103,40 @@ static void __init mx25pdk_fec_reset(void)
gpio_set_value(FEC_RESET_B_GPIO, 1); gpio_set_value(FEC_RESET_B_GPIO, 1);
} }
static struct mxc_nand_platform_data mx25pdk_nand_board_info = {
.width = 1,
.hw_ecc = 1,
.flash_bbt = 1,
};
static struct imx_fb_videomode mx25pdk_modes[] = {
{
.mode = {
.name = "CRT-VGA",
.refresh = 60,
.xres = 640,
.yres = 480,
.pixclock = 39683,
.left_margin = 45,
.right_margin = 114,
.upper_margin = 33,
.lower_margin = 11,
.hsync_len = 1,
.vsync_len = 1,
},
.bpp = 16,
.pcr = 0xFA208B80,
},
};
static struct imx_fb_platform_data mx25pdk_fb_pdata = {
.mode = mx25pdk_modes,
.num_modes = ARRAY_SIZE(mx25pdk_modes),
.pwmr = 0x00A903FF,
.lscr1 = 0x00120300,
.dmacr = 0x00020010,
};
static void __init mx25pdk_init(void) static void __init mx25pdk_init(void)
{ {
mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads, mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads,
...@@ -84,6 +144,9 @@ static void __init mx25pdk_init(void) ...@@ -84,6 +144,9 @@ static void __init mx25pdk_init(void)
mxc_register_device(&mxc_uart_device0, &uart_pdata); mxc_register_device(&mxc_uart_device0, &uart_pdata);
mxc_register_device(&mxc_usbh2, NULL); mxc_register_device(&mxc_usbh2, NULL);
mxc_register_device(&mxc_nand_device, &mx25pdk_nand_board_info);
mxc_register_device(&mx25_rtc_device, NULL);
mxc_register_device(&mx25_fb_device, &mx25pdk_fb_pdata);
mx25pdk_fec_reset(); mx25pdk_fec_reset();
mxc_register_device(&mx25_fec_device, &mx25_fec_pdata); mxc_register_device(&mx25_fec_device, &mx25_fec_pdata);
...@@ -102,7 +165,7 @@ MACHINE_START(MX25_3DS, "Freescale MX25PDK (3DS)") ...@@ -102,7 +165,7 @@ MACHINE_START(MX25_3DS, "Freescale MX25PDK (3DS)")
/* Maintainer: Freescale Semiconductor, Inc. */ /* Maintainer: Freescale Semiconductor, Inc. */
.phys_io = MX25_AIPS1_BASE_ADDR, .phys_io = MX25_AIPS1_BASE_ADDR,
.io_pg_offst = ((MX25_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, .io_pg_offst = ((MX25_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100, .boot_params = MX25_PHYS_OFFSET + 0x100,
.map_io = mx25_map_io, .map_io = mx25_map_io,
.init_irq = mx25_init_irq, .init_irq = mx25_init_irq,
.init_machine = mx25pdk_init, .init_machine = mx25pdk_init,
......
arch/arm/mach-mx3/Kconfig
浏览文件 @ b93a4afc
...@@ -34,6 +34,7 @@ config MACH_MX31ADS_WM1133_EV1 ...@@ -34,6 +34,7 @@ config MACH_MX31ADS_WM1133_EV1
config MACH_PCM037 config MACH_PCM037
bool "Support Phytec pcm037 (i.MX31) platforms" bool "Support Phytec pcm037 (i.MX31) platforms"
select ARCH_MX31 select ARCH_MX31
select MXC_ULPI if USB_ULPI
help help
Include support for Phytec pcm037 platform. This includes Include support for Phytec pcm037 platform. This includes
specific configurations for the board and its peripherals. specific configurations for the board and its peripherals.
...@@ -86,6 +87,7 @@ config MACH_QONG ...@@ -86,6 +87,7 @@ config MACH_QONG
config MACH_PCM043 config MACH_PCM043
bool "Support Phytec pcm043 (i.MX35) platforms" bool "Support Phytec pcm043 (i.MX35) platforms"
select ARCH_MX35 select ARCH_MX35
select MXC_ULPI if USB_ULPI
help help
Include support for Phytec pcm043 platform. This includes Include support for Phytec pcm043 platform. This includes
specific configurations for the board and its peripherals. specific configurations for the board and its peripherals.
......
arch/arm/mach-mx3/Makefile
浏览文件 @ b93a4afc
...@@ -5,18 +5,22 @@ ...@@ -5,18 +5,22 @@
# Object file lists. # Object file lists.
obj-y := mm.o devices.o cpu.o obj-y := mm.o devices.o cpu.o
obj-$(CONFIG_ARCH_MX31) += clock.o iomux.o CFLAGS_mm.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS
CFLAGS_devices.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS
CFLAGS_cpu.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS
obj-$(CONFIG_ARCH_MX31) += clock-imx31.o iomux-imx31.o
obj-$(CONFIG_ARCH_MX35) += clock-imx35.o obj-$(CONFIG_ARCH_MX35) += clock-imx35.o
obj-$(CONFIG_MACH_MX31ADS) += mx31ads.o obj-$(CONFIG_MACH_MX31ADS) += mach-mx31ads.o
obj-$(CONFIG_MACH_MX31LILLY) += mx31lilly.o mx31lilly-db.o obj-$(CONFIG_MACH_MX31LILLY) += mach-mx31lilly.o mx31lilly-db.o
obj-$(CONFIG_MACH_MX31LITE) += mx31lite.o mx31lite-db.o obj-$(CONFIG_MACH_MX31LITE) += mach-mx31lite.o mx31lite-db.o
obj-$(CONFIG_MACH_PCM037) += pcm037.o obj-$(CONFIG_MACH_PCM037) += mach-pcm037.o
obj-$(CONFIG_MACH_PCM037_EET) += pcm037_eet.o obj-$(CONFIG_MACH_PCM037_EET) += mach-pcm037_eet.o
obj-$(CONFIG_MACH_MX31_3DS) += mx31pdk.o obj-$(CONFIG_MACH_MX31_3DS) += mach-mx31_3ds.o
obj-$(CONFIG_MACH_MX31MOBOARD) += mx31moboard.o mx31moboard-devboard.o \ CFLAGS_mach-mx31_3ds.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS
mx31moboard-marxbot.o obj-$(CONFIG_MACH_MX31MOBOARD) += mach-mx31moboard.o mx31moboard-devboard.o \
obj-$(CONFIG_MACH_QONG) += qong.o mx31moboard-marxbot.o mx31moboard-smartbot.o
obj-$(CONFIG_MACH_PCM043) += pcm043.o obj-$(CONFIG_MACH_QONG) += mach-qong.o
obj-$(CONFIG_MACH_ARMADILLO5X0) += armadillo5x0.o obj-$(CONFIG_MACH_PCM043) += mach-pcm043.o
obj-$(CONFIG_MACH_MX35_3DS) += mx35pdk.o obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o
obj-$(CONFIG_MACH_KZM_ARM11_01) += kzmarm11.o obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35pdk.o
obj-$(CONFIG_MACH_KZM_ARM11_01) += mach-kzm_arm11_01.o
arch/arm/mach-mx3/clock.c → arch/arm/mach-mx3/clock-imx31.c
浏览文件 @ b93a4afc
...@@ -618,14 +618,15 @@ int __init mx31_clocks_init(unsigned long fref) ...@@ -618,14 +618,15 @@ int __init mx31_clocks_init(unsigned long fref)
mx31_read_cpu_rev(); mx31_read_cpu_rev();
if (mx31_revision() >= CHIP_REV_2_0) { if (mx31_revision() >= MX31_CHIP_REV_2_0) {
reg = __raw_readl(MXC_CCM_PMCR1); reg = __raw_readl(MXC_CCM_PMCR1);
/* No PLL restart on DVFS switch; enable auto EMI handshake */ /* No PLL restart on DVFS switch; enable auto EMI handshake */
reg |= MXC_CCM_PMCR1_PLLRDIS | MXC_CCM_PMCR1_EMIRQ_EN; reg |= MXC_CCM_PMCR1_PLLRDIS | MXC_CCM_PMCR1_EMIRQ_EN;
__raw_writel(reg, MXC_CCM_PMCR1); __raw_writel(reg, MXC_CCM_PMCR1);
} }
mxc_timer_init(&ipg_clk, IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT); mxc_timer_init(&ipg_clk, MX31_IO_ADDRESS(MX31_GPT1_BASE_ADDR),
MX31_INT_GPT);
return 0; return 0;
} }
......
arch/arm/mach-mx3/clock-imx35.c
浏览文件 @ b93a4afc
...@@ -28,7 +28,7 @@ ...@@ -28,7 +28,7 @@
#include <mach/hardware.h> #include <mach/hardware.h>
#include <mach/common.h> #include <mach/common.h>
#define CCM_BASE IO_ADDRESS(CCM_BASE_ADDR) #define CCM_BASE MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR)
#define CCM_CCMR 0x00 #define CCM_CCMR 0x00
#define CCM_PDR0 0x04 #define CCM_PDR0 0x04
...@@ -504,7 +504,8 @@ int __init mx35_clocks_init() ...@@ -504,7 +504,8 @@ int __init mx35_clocks_init()
__raw_writel((3 << 26) | ll, CCM_BASE + CCM_CGR2); __raw_writel((3 << 26) | ll, CCM_BASE + CCM_CGR2);
__raw_writel(0, CCM_BASE + CCM_CGR3); __raw_writel(0, CCM_BASE + CCM_CGR3);
mxc_timer_init(&gpt_clk, IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT); mxc_timer_init(&gpt_clk,
MX35_IO_ADDRESS(MX35_GPT1_BASE_ADDR), MX35_INT_GPT);
return 0; return 0;
} }
......
arch/arm/mach-mx3/cpu.c
浏览文件 @ b93a4afc
...@@ -41,7 +41,7 @@ void __init mx31_read_cpu_rev(void) ...@@ -41,7 +41,7 @@ void __init mx31_read_cpu_rev(void)
u32 i, srev; u32 i, srev;
/* read SREV register from IIM module */ /* read SREV register from IIM module */
srev = __raw_readl(IO_ADDRESS(IIM_BASE_ADDR) + MXC_IIMSREV); srev = __raw_readl(IO_ADDRESS(IIM_BASE_ADDR + MXC_IIMSREV));
for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++) for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
if (srev == mx31_cpu_type[i].srev) { if (srev == mx31_cpu_type[i].srev) {
......
arch/arm/mach-mx3/crm_regs.h
浏览文件 @ b93a4afc
...@@ -24,7 +24,7 @@ ...@@ -24,7 +24,7 @@
#define CKIH_CLK_FREQ_27MHZ 27000000 #define CKIH_CLK_FREQ_27MHZ 27000000
#define CKIL_CLK_FREQ 32768 #define CKIL_CLK_FREQ 32768
#define MXC_CCM_BASE IO_ADDRESS(CCM_BASE_ADDR) #define MXC_CCM_BASE MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR)
/* Register addresses */ /* Register addresses */
#define MXC_CCM_CCMR (MXC_CCM_BASE + 0x00) #define MXC_CCM_CCMR (MXC_CCM_BASE + 0x00)
......
arch/arm/mach-mx3/iomux.c → arch/arm/mach-mx3/iomux-imx31.c
浏览文件 @ b93a4afc
...@@ -29,7 +29,7 @@ ...@@ -29,7 +29,7 @@
/* /*
* IOMUX register (base) addresses * IOMUX register (base) addresses
*/ */
#define IOMUX_BASE IO_ADDRESS(IOMUXC_BASE_ADDR) #define IOMUX_BASE MX31_IO_ADDRESS(MX31_IOMUXC_BASE_ADDR)
#define IOMUXINT_OBS1 (IOMUX_BASE + 0x000) #define IOMUXINT_OBS1 (IOMUX_BASE + 0x000)
#define IOMUXINT_OBS2 (IOMUX_BASE + 0x004) #define IOMUXINT_OBS2 (IOMUX_BASE + 0x004)
#define IOMUXGPR (IOMUX_BASE + 0x008) #define IOMUXGPR (IOMUX_BASE + 0x008)
......
arch/arm/mach-mx3/armadillo5x0.c → arch/arm/mach-mx3/mach-armadillo5x0.c
浏览文件 @ b93a4afc
...@@ -182,8 +182,8 @@ static struct physmap_flash_data armadillo5x0_nor_flash_pdata = { ...@@ -182,8 +182,8 @@ static struct physmap_flash_data armadillo5x0_nor_flash_pdata = {
static struct resource armadillo5x0_nor_flash_resource = { static struct resource armadillo5x0_nor_flash_resource = {
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
.start = CS0_BASE_ADDR, .start = MX31_CS0_BASE_ADDR,
.end = CS0_BASE_ADDR + SZ_64M - 1, .end = MX31_CS0_BASE_ADDR + SZ_64M - 1,
}; };
static struct platform_device armadillo5x0_nor_flash = { static struct platform_device armadillo5x0_nor_flash = {
...@@ -311,8 +311,8 @@ static struct imxmmc_platform_data sdhc_pdata = { ...@@ -311,8 +311,8 @@ static struct imxmmc_platform_data sdhc_pdata = {
*/ */
static struct resource armadillo5x0_smc911x_resources[] = { static struct resource armadillo5x0_smc911x_resources[] = {
{ {
.start = CS3_BASE_ADDR, .start = MX31_CS3_BASE_ADDR,
.end = CS3_BASE_ADDR + SZ_32M - 1, .end = MX31_CS3_BASE_ADDR + SZ_32M - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, { }, {
.start = IOMUX_TO_IRQ(MX31_PIN_GPIO1_0), .start = IOMUX_TO_IRQ(MX31_PIN_GPIO1_0),
...@@ -406,9 +406,9 @@ static struct sys_timer armadillo5x0_timer = { ...@@ -406,9 +406,9 @@ static struct sys_timer armadillo5x0_timer = {
MACHINE_START(ARMADILLO5X0, "Armadillo-500") MACHINE_START(ARMADILLO5X0, "Armadillo-500")
/* Maintainer: Alberto Panizzo */ /* Maintainer: Alberto Panizzo */
.phys_io = AIPS1_BASE_ADDR, .phys_io = MX31_AIPS1_BASE_ADDR,
.io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x00000100, .boot_params = MX3x_PHYS_OFFSET + 0x100,
.map_io = mx31_map_io, .map_io = mx31_map_io,
.init_irq = mx31_init_irq, .init_irq = mx31_init_irq,
.timer = &armadillo5x0_timer, .timer = &armadillo5x0_timer,
......
arch/arm/mach-mx3/kzmarm11.c → arch/arm/mach-mx3/mach-kzm_arm11_01.c
浏览文件 @ b93a4afc
...@@ -46,13 +46,18 @@ ...@@ -46,13 +46,18 @@
#include "devices.h" #include "devices.h"
#define KZM_ARM11_IO_ADDRESS(x) ( \
IMX_IO_ADDRESS(x, MX31_CS4) ?: \
IMX_IO_ADDRESS(x, MX31_CS5) ?: \
MX31_IO_ADDRESS(x))
#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
/* /*
* KZM-ARM11-01 has an external UART on FPGA * KZM-ARM11-01 has an external UART on FPGA
*/ */
static struct plat_serial8250_port serial_platform_data[] = { static struct plat_serial8250_port serial_platform_data[] = {
{ {
.membase = IO_ADDRESS(KZM_ARM11_16550), .membase = KZM_ARM11_IO_ADDRESS(KZM_ARM11_16550),
.mapbase = KZM_ARM11_16550, .mapbase = KZM_ARM11_16550,
.irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_1),
.irqflags = IRQ_TYPE_EDGE_RISING, .irqflags = IRQ_TYPE_EDGE_RISING,
...@@ -102,9 +107,9 @@ static int __init kzm_init_ext_uart(void) ...@@ -102,9 +107,9 @@ static int __init kzm_init_ext_uart(void)
/* /*
* Unmask UART interrupt * Unmask UART interrupt
*/ */
tmp = __raw_readb(IO_ADDRESS(KZM_ARM11_CTL1)); tmp = __raw_readb(KZM_ARM11_IO_ADDRESS(KZM_ARM11_CTL1));
tmp |= 0x2; tmp |= 0x2;
__raw_writeb(tmp, IO_ADDRESS(KZM_ARM11_CTL1)); __raw_writeb(tmp, KZM_ARM11_IO_ADDRESS(KZM_ARM11_CTL1));
return platform_device_register(&serial_device); return platform_device_register(&serial_device);
} }
...@@ -128,8 +133,8 @@ static struct smsc911x_platform_config kzm_smsc9118_config = { ...@@ -128,8 +133,8 @@ static struct smsc911x_platform_config kzm_smsc9118_config = {
static struct resource kzm_smsc9118_resources[] = { static struct resource kzm_smsc9118_resources[] = {
{ {
.start = CS5_BASE_ADDR, .start = MX31_CS5_BASE_ADDR,
.end = CS5_BASE_ADDR + SZ_128K - 1, .end = MX31_CS5_BASE_ADDR + SZ_128K - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
{ {
...@@ -222,15 +227,15 @@ static void __init kzm_board_init(void) ...@@ -222,15 +227,15 @@ static void __init kzm_board_init(void)
*/ */
static struct map_desc kzm_io_desc[] __initdata = { static struct map_desc kzm_io_desc[] __initdata = {
{ {
.virtual = CS4_BASE_ADDR_VIRT, .virtual = MX31_CS4_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(CS4_BASE_ADDR), .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
.length = CS4_SIZE, .length = MX31_CS4_SIZE,
.type = MT_DEVICE .type = MT_DEVICE
}, },
{ {
.virtual = CS5_BASE_ADDR_VIRT, .virtual = MX31_CS5_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(CS5_BASE_ADDR), .pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR),
.length = CS5_SIZE, .length = MX31_CS5_SIZE,
.type = MT_DEVICE .type = MT_DEVICE
}, },
}; };
...@@ -258,9 +263,9 @@ static struct sys_timer kzm_timer = { ...@@ -258,9 +263,9 @@ static struct sys_timer kzm_timer = {
* initialize __mach_desc_KZM_ARM11_01 data structure. * initialize __mach_desc_KZM_ARM11_01 data structure.
*/ */
MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01") MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01")
.phys_io = AIPS1_BASE_ADDR, .phys_io = MX31_AIPS1_BASE_ADDR,
.io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100, .boot_params = MX3x_PHYS_OFFSET + 0x100,
.map_io = kzm_map_io, .map_io = kzm_map_io,
.init_irq = mx31_init_irq, .init_irq = mx31_init_irq,
.init_machine = kzm_board_init, .init_machine = kzm_board_init,
......
arch/arm/mach-mx3/mx31pdk.c → arch/arm/mach-mx3/mach-mx31_3ds.c
浏览文件 @ b93a4afc
...@@ -211,9 +211,9 @@ static int __init mx31pdk_init_expio(void) ...@@ -211,9 +211,9 @@ static int __init mx31pdk_init_expio(void)
*/ */
static struct map_desc mx31pdk_io_desc[] __initdata = { static struct map_desc mx31pdk_io_desc[] __initdata = {
{ {
.virtual = CS5_BASE_ADDR_VIRT, .virtual = MX31_CS5_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(CS5_BASE_ADDR), .pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR),
.length = CS5_SIZE, .length = MX31_CS5_SIZE,
.type = MT_DEVICE, .type = MT_DEVICE,
}, },
}; };
...@@ -256,9 +256,9 @@ static struct sys_timer mx31pdk_timer = { ...@@ -256,9 +256,9 @@ static struct sys_timer mx31pdk_timer = {
*/ */
MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)") MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
/* Maintainer: Freescale Semiconductor, Inc. */ /* Maintainer: Freescale Semiconductor, Inc. */
.phys_io = AIPS1_BASE_ADDR, .phys_io = MX31_AIPS1_BASE_ADDR,
.io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100, .boot_params = MX3x_PHYS_OFFSET + 0x100,
.map_io = mx31pdk_map_io, .map_io = mx31pdk_map_io,
.init_irq = mx31_init_irq, .init_irq = mx31_init_irq,
.init_machine = mxc_board_init, .init_machine = mxc_board_init,
......
arch/arm/mach-mx3/mx31ads.c → arch/arm/mach-mx3/mach-mx31ads.c
浏览文件 @ b93a4afc
...@@ -60,7 +60,7 @@ ...@@ -60,7 +60,7 @@
static struct plat_serial8250_port serial_platform_data[] = { static struct plat_serial8250_port serial_platform_data[] = {
{ {
.membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA), .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA),
.mapbase = (unsigned long)(CS4_BASE_ADDR + PBC_SC16C652_UARTA), .mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTA),
.irq = EXPIO_INT_XUART_INTA, .irq = EXPIO_INT_XUART_INTA,
.uartclk = 14745600, .uartclk = 14745600,
.regshift = 0, .regshift = 0,
...@@ -68,7 +68,7 @@ static struct plat_serial8250_port serial_platform_data[] = { ...@@ -68,7 +68,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ, .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
}, { }, {
.membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB), .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB),
.mapbase = (unsigned long)(CS4_BASE_ADDR + PBC_SC16C652_UARTB), .mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTB),
.irq = EXPIO_INT_XUART_INTB, .irq = EXPIO_INT_XUART_INTB,
.uartclk = 14745600, .uartclk = 14745600,
.regshift = 0, .regshift = 0,
...@@ -309,12 +309,8 @@ static struct regulator_init_data ldo1_data = { ...@@ -309,12 +309,8 @@ static struct regulator_init_data ldo1_data = {
}; };
static struct regulator_consumer_supply ldo2_consumers[] = { static struct regulator_consumer_supply ldo2_consumers[] = {
{ { .supply = "AVDD", .dev_name = "1-001a" },
.supply = "AVDD", { .supply = "HPVDD", .dev_name = "1-001a" },
},
{
.supply = "HPVDD",
},
}; };
/* CODEC and SIM */ /* CODEC and SIM */
...@@ -385,8 +381,6 @@ static struct wm8350_audio_platform_data imx32ads_wm8350_setup = { ...@@ -385,8 +381,6 @@ static struct wm8350_audio_platform_data imx32ads_wm8350_setup = {
static int mx31_wm8350_init(struct wm8350 *wm8350) static int mx31_wm8350_init(struct wm8350 *wm8350)
{ {
int i;
wm8350_gpio_config(wm8350, 0, WM8350_GPIO_DIR_IN, wm8350_gpio_config(wm8350, 0, WM8350_GPIO_DIR_IN,
WM8350_GPIO0_PWR_ON_IN, WM8350_GPIO_ACTIVE_LOW, WM8350_GPIO0_PWR_ON_IN, WM8350_GPIO_ACTIVE_LOW,
WM8350_GPIO_PULL_UP, WM8350_GPIO_INVERT_OFF, WM8350_GPIO_PULL_UP, WM8350_GPIO_INVERT_OFF,
...@@ -422,10 +416,6 @@ static int mx31_wm8350_init(struct wm8350 *wm8350) ...@@ -422,10 +416,6 @@ static int mx31_wm8350_init(struct wm8350 *wm8350)
WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF, WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
WM8350_GPIO_DEBOUNCE_OFF); WM8350_GPIO_DEBOUNCE_OFF);
/* Fix up for our own supplies. */
for (i = 0; i < ARRAY_SIZE(ldo2_consumers); i++)
ldo2_consumers[i].dev = wm8350->dev;
wm8350_register_regulator(wm8350, WM8350_DCDC_1, &sw1a_data); wm8350_register_regulator(wm8350, WM8350_DCDC_1, &sw1a_data);
wm8350_register_regulator(wm8350, WM8350_DCDC_3, &viohi_data); wm8350_register_regulator(wm8350, WM8350_DCDC_3, &viohi_data);
wm8350_register_regulator(wm8350, WM8350_DCDC_4, &violo_data); wm8350_register_regulator(wm8350, WM8350_DCDC_4, &violo_data);
...@@ -493,14 +483,27 @@ static void mxc_init_i2c(void) ...@@ -493,14 +483,27 @@ static void mxc_init_i2c(void)
} }
#endif #endif
static unsigned int ssi_pins[] = {
MX31_PIN_SFS5__SFS5,
MX31_PIN_SCK5__SCK5,
MX31_PIN_SRXD5__SRXD5,
MX31_PIN_STXD5__STXD5,
};
static void mxc_init_audio(void)
{
mxc_register_device(&imx_ssi_device0, NULL);
mxc_iomux_setup_multiple_pins(ssi_pins, ARRAY_SIZE(ssi_pins), "ssi");
}
/*! /*!
* This structure defines static mappings for the i.MX31ADS board. * This structure defines static mappings for the i.MX31ADS board.
*/ */
static struct map_desc mx31ads_io_desc[] __initdata = { static struct map_desc mx31ads_io_desc[] __initdata = {
{ {
.virtual = CS4_BASE_ADDR_VIRT, .virtual = MX31_CS4_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(CS4_BASE_ADDR), .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
.length = CS4_SIZE / 2, .length = MX31_CS4_SIZE / 2,
.type = MT_DEVICE .type = MT_DEVICE
}, },
}; };
...@@ -528,6 +531,7 @@ static void __init mxc_board_init(void) ...@@ -528,6 +531,7 @@ static void __init mxc_board_init(void)
mxc_init_extuart(); mxc_init_extuart();
mxc_init_imx_uart(); mxc_init_imx_uart();
mxc_init_i2c(); mxc_init_i2c();
mxc_init_audio();
} }
static void __init mx31ads_timer_init(void) static void __init mx31ads_timer_init(void)
...@@ -545,9 +549,9 @@ static struct sys_timer mx31ads_timer = { ...@@ -545,9 +549,9 @@ static struct sys_timer mx31ads_timer = {
*/ */
MACHINE_START(MX31ADS, "Freescale MX31ADS") MACHINE_START(MX31ADS, "Freescale MX31ADS")
/* Maintainer: Freescale Semiconductor, Inc. */ /* Maintainer: Freescale Semiconductor, Inc. */
.phys_io = AIPS1_BASE_ADDR, .phys_io = MX31_AIPS1_BASE_ADDR,
.io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100, .boot_params = MX3x_PHYS_OFFSET + 0x100,
.map_io = mx31ads_map_io, .map_io = mx31ads_map_io,
.init_irq = mx31ads_init_irq, .init_irq = mx31ads_init_irq,
.init_machine = mxc_board_init, .init_machine = mxc_board_init,
......
arch/arm/mach-mx3/mx31lilly.c → arch/arm/mach-mx3/mach-mx31lilly.c
浏览文件 @ b93a4afc
...@@ -57,8 +57,8 @@ ...@@ -57,8 +57,8 @@
static struct resource smsc91x_resources[] = { static struct resource smsc91x_resources[] = {
{ {
.start = CS4_BASE_ADDR, .start = MX31_CS4_BASE_ADDR,
.end = CS4_BASE_ADDR + 0xffff, .end = MX31_CS4_BASE_ADDR + 0xffff,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
{ {
...@@ -195,9 +195,9 @@ static struct sys_timer mx31lilly_timer = { ...@@ -195,9 +195,9 @@ static struct sys_timer mx31lilly_timer = {
}; };
MACHINE_START(LILLY1131, "INCO startec LILLY-1131") MACHINE_START(LILLY1131, "INCO startec LILLY-1131")
.phys_io = AIPS1_BASE_ADDR, .phys_io = MX31_AIPS1_BASE_ADDR,
.io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100, .boot_params = MX3x_PHYS_OFFSET + 0x100,
.map_io = mx31_map_io, .map_io = mx31_map_io,
.init_irq = mx31_init_irq, .init_irq = mx31_init_irq,
.init_machine = mx31lilly_board_init, .init_machine = mx31lilly_board_init,
......
arch/arm/mach-mx3/mx31lite.c → arch/arm/mach-mx3/mach-mx31lite.c
浏览文件 @ b93a4afc
...@@ -82,8 +82,8 @@ static struct smsc911x_platform_config smsc911x_config = { ...@@ -82,8 +82,8 @@ static struct smsc911x_platform_config smsc911x_config = {
static struct resource smsc911x_resources[] = { static struct resource smsc911x_resources[] = {
{ {
.start = CS4_BASE_ADDR, .start = MX31_CS4_BASE_ADDR,
.end = CS4_BASE_ADDR + 0x100, .end = MX31_CS4_BASE_ADDR + 0x100,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, { }, {
.start = IOMUX_TO_IRQ(MX31_PIN_SFS6), .start = IOMUX_TO_IRQ(MX31_PIN_SFS6),
...@@ -214,9 +214,9 @@ static struct platform_device physmap_flash_device = { ...@@ -214,9 +214,9 @@ static struct platform_device physmap_flash_device = {
*/ */
static struct map_desc mx31lite_io_desc[] __initdata = { static struct map_desc mx31lite_io_desc[] __initdata = {
{ {
.virtual = CS4_BASE_ADDR_VIRT, .virtual = MX31_CS4_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(CS4_BASE_ADDR), .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
.length = CS4_SIZE, .length = MX31_CS4_SIZE,
.type = MT_DEVICE .type = MT_DEVICE
} }
}; };
...@@ -287,9 +287,9 @@ struct sys_timer mx31lite_timer = { ...@@ -287,9 +287,9 @@ struct sys_timer mx31lite_timer = {
MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM") MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM")
/* Maintainer: Freescale Semiconductor, Inc. */ /* Maintainer: Freescale Semiconductor, Inc. */
.phys_io = AIPS1_BASE_ADDR, .phys_io = MX31_AIPS1_BASE_ADDR,
.io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100, .boot_params = MX3x_PHYS_OFFSET + 0x100,
.map_io = mx31lite_map_io, .map_io = mx31lite_map_io,
.init_irq = mx31_init_irq, .init_irq = mx31_init_irq,
.init_machine = mxc_board_init, .init_machine = mxc_board_init,
......
arch/arm/mach-mx3/mx31moboard.c → arch/arm/mach-mx3/mach-mx31moboard.c
浏览文件 @ b93a4afc
...@@ -96,9 +96,6 @@ static unsigned int moboard_pins[] = { ...@@ -96,9 +96,6 @@ static unsigned int moboard_pins[] = {
/* LEDs */ /* LEDs */
MX31_PIN_SVEN0__GPIO2_0, MX31_PIN_STX0__GPIO2_1, MX31_PIN_SVEN0__GPIO2_0, MX31_PIN_STX0__GPIO2_1,
MX31_PIN_SRX0__GPIO2_2, MX31_PIN_SIMPD0__GPIO2_3, MX31_PIN_SRX0__GPIO2_2, MX31_PIN_SIMPD0__GPIO2_3,
/* SEL */
MX31_PIN_DTR_DCE1__GPIO2_8, MX31_PIN_DSR_DCE1__GPIO2_9,
MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11,
/* SPI1 */ /* SPI1 */
MX31_PIN_CSPI2_MOSI__MOSI, MX31_PIN_CSPI2_MISO__MISO, MX31_PIN_CSPI2_MOSI__MOSI, MX31_PIN_CSPI2_MISO__MISO,
MX31_PIN_CSPI2_SCLK__SCLK, MX31_PIN_CSPI2_SPI_RDY__SPI_RDY, MX31_PIN_CSPI2_SCLK__SCLK, MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
...@@ -352,9 +349,7 @@ static struct fsl_usb2_platform_data usb_pdata = { ...@@ -352,9 +349,7 @@ static struct fsl_usb2_platform_data usb_pdata = {
static int moboard_usbh2_hw_init(struct platform_device *pdev) static int moboard_usbh2_hw_init(struct platform_device *pdev)
{ {
int ret = gpio_request(USBH2_EN_B, "usbh2-en"); int ret;
if (ret)
return ret;
mxc_iomux_set_gpr(MUX_PGP_UH2, true); mxc_iomux_set_gpr(MUX_PGP_UH2, true);
...@@ -371,6 +366,9 @@ static int moboard_usbh2_hw_init(struct platform_device *pdev) ...@@ -371,6 +366,9 @@ static int moboard_usbh2_hw_init(struct platform_device *pdev)
mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG);
ret = gpio_request(USBH2_EN_B, "usbh2-en");
if (ret)
return ret;
gpio_direction_output(USBH2_EN_B, 0); gpio_direction_output(USBH2_EN_B, 0);
return 0; return 0;
...@@ -431,34 +429,6 @@ static struct platform_device mx31moboard_leds_device = { ...@@ -431,34 +429,6 @@ static struct platform_device mx31moboard_leds_device = {
}, },
}; };
#define SEL0 IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1)
#define SEL1 IOMUX_TO_GPIO(MX31_PIN_DSR_DCE1)
#define SEL2 IOMUX_TO_GPIO(MX31_PIN_RI_DCE1)
#define SEL3 IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1)
static void mx31moboard_init_sel_gpios(void)
{
if (!gpio_request(SEL0, "sel0")) {
gpio_direction_input(SEL0);
gpio_export(SEL0, true);
}
if (!gpio_request(SEL1, "sel1")) {
gpio_direction_input(SEL1);
gpio_export(SEL1, true);
}
if (!gpio_request(SEL2, "sel2")) {
gpio_direction_input(SEL2);
gpio_export(SEL2, true);
}
if (!gpio_request(SEL3, "sel3")) {
gpio_direction_input(SEL3);
gpio_export(SEL3, true);
}
}
static struct ipu_platform_data mx3_ipu_data = { static struct ipu_platform_data mx3_ipu_data = {
.irq_base = MXC_IPU_IRQ_START, .irq_base = MXC_IPU_IRQ_START,
}; };
...@@ -518,8 +488,6 @@ static void __init mxc_board_init(void) ...@@ -518,8 +488,6 @@ static void __init mxc_board_init(void)
mxc_register_device(&mxc_uart_device4, &uart4_pdata); mxc_register_device(&mxc_uart_device4, &uart4_pdata);
mx31moboard_init_sel_gpios();
mxc_register_device(&mxc_i2c_device0, &moboard_i2c0_pdata); mxc_register_device(&mxc_i2c_device0, &moboard_i2c0_pdata);
mxc_register_device(&mxc_i2c_device1, &moboard_i2c1_pdata); mxc_register_device(&mxc_i2c_device1, &moboard_i2c1_pdata);
...@@ -552,6 +520,9 @@ static void __init mxc_board_init(void) ...@@ -552,6 +520,9 @@ static void __init mxc_board_init(void)
case MX31MARXBOT: case MX31MARXBOT:
mx31moboard_marxbot_init(); mx31moboard_marxbot_init();
break; break;
case MX31SMARTBOT:
mx31moboard_smartbot_init();
break;
default: default:
printk(KERN_ERR "Illegal mx31moboard_baseboard type %d\n", printk(KERN_ERR "Illegal mx31moboard_baseboard type %d\n",
mx31moboard_baseboard); mx31moboard_baseboard);
...@@ -569,9 +540,9 @@ struct sys_timer mx31moboard_timer = { ...@@ -569,9 +540,9 @@ struct sys_timer mx31moboard_timer = {
MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard") MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard")
/* Maintainer: Valentin Longchamp, EPFL Mobots group */ /* Maintainer: Valentin Longchamp, EPFL Mobots group */
.phys_io = AIPS1_BASE_ADDR, .phys_io = MX31_AIPS1_BASE_ADDR,
.io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100, .boot_params = MX3x_PHYS_OFFSET + 0x100,
.map_io = mx31_map_io, .map_io = mx31_map_io,
.init_irq = mx31_init_irq, .init_irq = mx31_init_irq,
.init_machine = mxc_board_init, .init_machine = mxc_board_init,
......
arch/arm/mach-mx3/mx35pdk.c → arch/arm/mach-mx3/mach-mx35pdk.c
浏览文件 @ b93a4afc
...@@ -106,9 +106,9 @@ struct sys_timer mx35pdk_timer = { ...@@ -106,9 +106,9 @@ struct sys_timer mx35pdk_timer = {
MACHINE_START(MX35_3DS, "Freescale MX35PDK") MACHINE_START(MX35_3DS, "Freescale MX35PDK")
/* Maintainer: Freescale Semiconductor, Inc */ /* Maintainer: Freescale Semiconductor, Inc */
.phys_io = AIPS1_BASE_ADDR, .phys_io = MX35_AIPS1_BASE_ADDR,
.io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, .io_pg_offst = ((MX35_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100, .boot_params = MX3x_PHYS_OFFSET + 0x100,
.map_io = mx35_map_io, .map_io = mx35_map_io,
.init_irq = mx35_init_irq, .init_irq = mx35_init_irq,
.init_machine = mxc_board_init, .init_machine = mxc_board_init,
......
arch/arm/mach-mx3/pcm037.c → arch/arm/mach-mx3/mach-pcm037.c
浏览文件 @ b93a4afc
...@@ -33,6 +33,9 @@ ...@@ -33,6 +33,9 @@
#include <linux/irq.h> #include <linux/irq.h>
#include <linux/fsl_devices.h> #include <linux/fsl_devices.h>
#include <linux/can/platform/sja1000.h> #include <linux/can/platform/sja1000.h>
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
#include <linux/fsl_devices.h>
#include <media/soc_camera.h> #include <media/soc_camera.h>
...@@ -51,6 +54,8 @@ ...@@ -51,6 +54,8 @@
#include <mach/mx3_camera.h> #include <mach/mx3_camera.h>
#include <mach/mx3fb.h> #include <mach/mx3fb.h>
#include <mach/mxc_nand.h> #include <mach/mxc_nand.h>
#include <mach/mxc_ehci.h>
#include <mach/ulpi.h>
#include "devices.h" #include "devices.h"
#include "pcm037.h" #include "pcm037.h"
...@@ -172,19 +177,7 @@ static unsigned int pcm037_pins[] = { ...@@ -172,19 +177,7 @@ static unsigned int pcm037_pins[] = {
MX31_PIN_CSI_VSYNC__CSI_VSYNC, MX31_PIN_CSI_VSYNC__CSI_VSYNC,
/* GPIO */ /* GPIO */
IOMUX_MODE(MX31_PIN_ATA_DMACK, IOMUX_CONFIG_GPIO), IOMUX_MODE(MX31_PIN_ATA_DMACK, IOMUX_CONFIG_GPIO),
}; /* OTG */
static struct physmap_flash_data pcm037_flash_data = {
.width = 2,
};
static struct resource pcm037_flash_resource = {
.start = 0xa0000000,
.end = 0xa1ffffff,
.flags = IORESOURCE_MEM,
};
static int usbotg_pins[] = {
MX31_PIN_USBOTG_DATA0__USBOTG_DATA0, MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
MX31_PIN_USBOTG_DATA1__USBOTG_DATA1, MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
MX31_PIN_USBOTG_DATA2__USBOTG_DATA2, MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
...@@ -197,39 +190,29 @@ static int usbotg_pins[] = { ...@@ -197,39 +190,29 @@ static int usbotg_pins[] = {
MX31_PIN_USBOTG_DIR__USBOTG_DIR, MX31_PIN_USBOTG_DIR__USBOTG_DIR,
MX31_PIN_USBOTG_NXT__USBOTG_NXT, MX31_PIN_USBOTG_NXT__USBOTG_NXT,
MX31_PIN_USBOTG_STP__USBOTG_STP, MX31_PIN_USBOTG_STP__USBOTG_STP,
/* USB host 2 */
IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC),
IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC),
IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC),
IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC),
IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC),
IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC),
IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC),
IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC),
IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC),
IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC),
IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC),
IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC),
}; };
/* USB OTG HS port */ static struct physmap_flash_data pcm037_flash_data = {
static int __init gpio_usbotg_hs_activate(void) .width = 2,
{ };
int ret = mxc_iomux_setup_multiple_pins(usbotg_pins,
ARRAY_SIZE(usbotg_pins), "usbotg");
if (ret < 0) {
printk(KERN_ERR "Cannot set up OTG pins\n");
return ret;
}
mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
return 0;
}
/* OTG config */ static struct resource pcm037_flash_resource = {
static struct fsl_usb2_platform_data usb_pdata = { .start = 0xa0000000,
.operating_mode = FSL_USB2_DR_DEVICE, .end = 0xa1ffffff,
.phy_mode = FSL_USB2_PHY_ULPI, .flags = IORESOURCE_MEM,
}; };
static struct platform_device pcm037_flash = { static struct platform_device pcm037_flash = {
...@@ -248,8 +231,8 @@ static struct imxuart_platform_data uart_pdata = { ...@@ -248,8 +231,8 @@ static struct imxuart_platform_data uart_pdata = {
static struct resource smsc911x_resources[] = { static struct resource smsc911x_resources[] = {
{ {
.start = CS1_BASE_ADDR + 0x300, .start = MX31_CS1_BASE_ADDR + 0x300,
.end = CS1_BASE_ADDR + 0x300 + SZ_64K - 1, .end = MX31_CS1_BASE_ADDR + 0x300 + SZ_64K - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, { }, {
.start = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1), .start = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
...@@ -281,8 +264,8 @@ static struct platdata_mtd_ram pcm038_sram_data = { ...@@ -281,8 +264,8 @@ static struct platdata_mtd_ram pcm038_sram_data = {
}; };
static struct resource pcm038_sram_resource = { static struct resource pcm038_sram_resource = {
.start = CS4_BASE_ADDR, .start = MX31_CS4_BASE_ADDR,
.end = CS4_BASE_ADDR + 512 * 1024 - 1, .end = MX31_CS4_BASE_ADDR + 512 * 1024 - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}; };
...@@ -536,8 +519,8 @@ static struct mx3fb_platform_data mx3fb_pdata = { ...@@ -536,8 +519,8 @@ static struct mx3fb_platform_data mx3fb_pdata = {
static struct resource pcm970_sja1000_resources[] = { static struct resource pcm970_sja1000_resources[] = {
{ {
.start = CS5_BASE_ADDR, .start = MX31_CS5_BASE_ADDR,
.end = CS5_BASE_ADDR + 0x100 - 1, .end = MX31_CS5_BASE_ADDR + 0x100 - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, { }, {
.start = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)), .start = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)),
...@@ -561,16 +544,65 @@ static struct platform_device pcm970_sja1000 = { ...@@ -561,16 +544,65 @@ static struct platform_device pcm970_sja1000 = {
.num_resources = ARRAY_SIZE(pcm970_sja1000_resources), .num_resources = ARRAY_SIZE(pcm970_sja1000_resources),
}; };
static struct mxc_usbh_platform_data otg_pdata = {
.portsc = MXC_EHCI_MODE_ULPI,
.flags = MXC_EHCI_INTERFACE_DIFF_UNI,
};
static struct mxc_usbh_platform_data usbh2_pdata = {
.portsc = MXC_EHCI_MODE_ULPI,
.flags = MXC_EHCI_INTERFACE_DIFF_UNI,
};
static struct fsl_usb2_platform_data otg_device_pdata = {
.operating_mode = FSL_USB2_DR_DEVICE,
.phy_mode = FSL_USB2_PHY_ULPI,
};
static int otg_mode_host;
static int __init pcm037_otg_mode(char *options)
{
if (!strcmp(options, "host"))
otg_mode_host = 1;
else if (!strcmp(options, "device"))
otg_mode_host = 0;
else
pr_info("otg_mode neither \"host\" nor \"device\". "
"Defaulting to device\n");
return 0;
}
__setup("otg_mode=", pcm037_otg_mode);
/* /*
* Board specific initialization. * Board specific initialization.
*/ */
static void __init mxc_board_init(void) static void __init mxc_board_init(void)
{ {
int ret; int ret;
u32 tmp;
mxc_iomux_set_gpr(MUX_PGP_UH2, 1);
mxc_iomux_setup_multiple_pins(pcm037_pins, ARRAY_SIZE(pcm037_pins), mxc_iomux_setup_multiple_pins(pcm037_pins, ARRAY_SIZE(pcm037_pins),
"pcm037"); "pcm037");
#define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS \
| PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */
mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */
mxc_iomux_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG); /* USBH2_DATA2 */
mxc_iomux_set_pad(MX31_PIN_STXD6, H2_PAD_CFG); /* USBH2_DATA3 */
mxc_iomux_set_pad(MX31_PIN_SFS3, H2_PAD_CFG); /* USBH2_DATA4 */
mxc_iomux_set_pad(MX31_PIN_SCK3, H2_PAD_CFG); /* USBH2_DATA5 */
mxc_iomux_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */
mxc_iomux_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */
if (pcm037_variant() == PCM037_EET) if (pcm037_variant() == PCM037_EET)
mxc_iomux_setup_multiple_pins(pcm037_uart1_pins, mxc_iomux_setup_multiple_pins(pcm037_uart1_pins,
ARRAY_SIZE(pcm037_uart1_pins), "pcm037_uart1"); ARRAY_SIZE(pcm037_uart1_pins), "pcm037_uart1");
...@@ -608,8 +640,6 @@ static void __init mxc_board_init(void) ...@@ -608,8 +640,6 @@ static void __init mxc_board_init(void)
mxc_register_device(&mxcsdhc_device0, &sdhc_pdata); mxc_register_device(&mxcsdhc_device0, &sdhc_pdata);
mxc_register_device(&mx3_ipu, &mx3_ipu_data); mxc_register_device(&mx3_ipu, &mx3_ipu_data);
mxc_register_device(&mx3_fb, &mx3fb_pdata); mxc_register_device(&mx3_fb, &mx3fb_pdata);
if (!gpio_usbotg_hs_activate())
mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
/* CSI */ /* CSI */
/* Camera power: default - off */ /* Camera power: default - off */
...@@ -623,6 +653,23 @@ static void __init mxc_board_init(void) ...@@ -623,6 +653,23 @@ static void __init mxc_board_init(void)
mxc_register_device(&mx3_camera, &camera_pdata); mxc_register_device(&mx3_camera, &camera_pdata);
platform_device_register(&pcm970_sja1000); platform_device_register(&pcm970_sja1000);
#if defined(CONFIG_USB_ULPI)
if (otg_mode_host) {
otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
mxc_register_device(&mxc_otg_host, &otg_pdata);
}
usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
mxc_register_device(&mxc_usbh2, &usbh2_pdata);
#endif
if (!otg_mode_host)
mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
} }
static void __init pcm037_timer_init(void) static void __init pcm037_timer_init(void)
...@@ -636,9 +683,9 @@ struct sys_timer pcm037_timer = { ...@@ -636,9 +683,9 @@ struct sys_timer pcm037_timer = {
MACHINE_START(PCM037, "Phytec Phycore pcm037") MACHINE_START(PCM037, "Phytec Phycore pcm037")
/* Maintainer: Pengutronix */ /* Maintainer: Pengutronix */
.phys_io = AIPS1_BASE_ADDR, .phys_io = MX31_AIPS1_BASE_ADDR,
.io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100, .boot_params = MX3x_PHYS_OFFSET + 0x100,
.map_io = mx31_map_io, .map_io = mx31_map_io,
.init_irq = mx31_init_irq, .init_irq = mx31_init_irq,
.init_machine = mxc_board_init, .init_machine = mxc_board_init,
......
arch/arm/mach-mx3/pcm043.c → arch/arm/mach-mx3/mach-pcm043.c
浏览文件 @ b93a4afc
...@@ -26,8 +26,12 @@ ...@@ -26,8 +26,12 @@
#include <linux/gpio.h> #include <linux/gpio.h>
#include <linux/smc911x.h> #include <linux/smc911x.h>
#include <linux/interrupt.h> #include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/i2c.h> #include <linux/i2c.h>
#include <linux/i2c/at24.h> #include <linux/i2c/at24.h>
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
#include <linux/fsl_devices.h>
#include <asm/mach-types.h> #include <asm/mach-types.h>
#include <asm/mach/arch.h> #include <asm/mach/arch.h>
...@@ -44,6 +48,10 @@ ...@@ -44,6 +48,10 @@
#include <mach/ipu.h> #include <mach/ipu.h>
#include <mach/mx3fb.h> #include <mach/mx3fb.h>
#include <mach/mxc_nand.h> #include <mach/mxc_nand.h>
#include <mach/mxc_ehci.h>
#include <mach/ulpi.h>
#include <mach/audmux.h>
#include <mach/ssi.h>
#include "devices.h" #include "devices.h"
...@@ -205,6 +213,94 @@ static struct pad_desc pcm043_pads[] = { ...@@ -205,6 +213,94 @@ static struct pad_desc pcm043_pads[] = {
MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS, MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS,
/* gpio */ /* gpio */
MX35_PAD_ATA_CS0__GPIO2_6, MX35_PAD_ATA_CS0__GPIO2_6,
/* USB host */
MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR,
MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC,
/* SSI */
MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS,
MX35_PAD_STXD4__AUDMUX_AUD4_TXD,
MX35_PAD_SRXD4__AUDMUX_AUD4_RXD,
MX35_PAD_SCK4__AUDMUX_AUD4_TXC,
};
#define AC97_GPIO_TXFS (1 * 32 + 31)
#define AC97_GPIO_TXD (1 * 32 + 28)
#define AC97_GPIO_RESET (1 * 32 + 0)
static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97)
{
struct pad_desc txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
struct pad_desc txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
int ret;
ret = gpio_request(AC97_GPIO_TXFS, "SSI");
if (ret) {
printk("failed to get GPIO_TXFS: %d\n", ret);
return;
}
mxc_iomux_v3_setup_pad(&txfs_gpio);
/* warm reset */
gpio_direction_output(AC97_GPIO_TXFS, 1);
udelay(2);
gpio_set_value(AC97_GPIO_TXFS, 0);
gpio_free(AC97_GPIO_TXFS);
mxc_iomux_v3_setup_pad(&txfs);
}
static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97)
{
struct pad_desc txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
struct pad_desc txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
struct pad_desc txd_gpio = MX35_PAD_STXD4__GPIO2_28;
struct pad_desc txd = MX35_PAD_STXD4__AUDMUX_AUD4_TXD;
struct pad_desc reset_gpio = MX35_PAD_SD2_CMD__GPIO2_0;
int ret;
ret = gpio_request(AC97_GPIO_TXFS, "SSI");
if (ret)
goto err1;
ret = gpio_request(AC97_GPIO_TXD, "SSI");
if (ret)
goto err2;
ret = gpio_request(AC97_GPIO_RESET, "SSI");
if (ret)
goto err3;
mxc_iomux_v3_setup_pad(&txfs_gpio);
mxc_iomux_v3_setup_pad(&txd_gpio);
mxc_iomux_v3_setup_pad(&reset_gpio);
gpio_direction_output(AC97_GPIO_TXFS, 0);
gpio_direction_output(AC97_GPIO_TXD, 0);
/* cold reset */
gpio_direction_output(AC97_GPIO_RESET, 0);
udelay(10);
gpio_direction_output(AC97_GPIO_RESET, 1);
mxc_iomux_v3_setup_pad(&txd);
mxc_iomux_v3_setup_pad(&txfs);
gpio_free(AC97_GPIO_RESET);
err3:
gpio_free(AC97_GPIO_TXD);
err2:
gpio_free(AC97_GPIO_TXFS);
err1:
if (ret)
printk("%s failed with %d\n", __func__, ret);
mdelay(1);
}
static struct imx_ssi_platform_data pcm043_ssi_pdata = {
.ac97_reset = pcm043_ac97_cold_reset,
.ac97_warm_reset = pcm043_ac97_warm_reset,
.flags = IMX_SSI_USE_AC97,
}; };
static struct mxc_nand_platform_data pcm037_nand_board_info = { static struct mxc_nand_platform_data pcm037_nand_board_info = {
...@@ -212,6 +308,37 @@ static struct mxc_nand_platform_data pcm037_nand_board_info = { ...@@ -212,6 +308,37 @@ static struct mxc_nand_platform_data pcm037_nand_board_info = {
.hw_ecc = 1, .hw_ecc = 1,
}; };
static struct mxc_usbh_platform_data otg_pdata = {
.portsc = MXC_EHCI_MODE_UTMI,
.flags = MXC_EHCI_INTERFACE_DIFF_UNI,
};
static struct mxc_usbh_platform_data usbh1_pdata = {
.portsc = MXC_EHCI_MODE_SERIAL,
.flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
MXC_EHCI_IPPUE_DOWN,
};
static struct fsl_usb2_platform_data otg_device_pdata = {
.operating_mode = FSL_USB2_DR_DEVICE,
.phy_mode = FSL_USB2_PHY_UTMI,
};
static int otg_mode_host;
static int __init pcm043_otg_mode(char *options)
{
if (!strcmp(options, "host"))
otg_mode_host = 1;
else if (!strcmp(options, "device"))
otg_mode_host = 0;
else
pr_info("otg_mode neither \"host\" nor \"device\". "
"Defaulting to device\n");
return 0;
}
__setup("otg_mode=", pcm043_otg_mode);
/* /*
* Board specific initialization. * Board specific initialization.
*/ */
...@@ -219,10 +346,23 @@ static void __init mxc_board_init(void) ...@@ -219,10 +346,23 @@ static void __init mxc_board_init(void)
{ {
mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads)); mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads));
mxc_audmux_v2_configure_port(3,
MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
MXC_AUDMUX_V2_PTCR_TFSEL(0) |
MXC_AUDMUX_V2_PTCR_TFSDIR,
MXC_AUDMUX_V2_PDCR_RXDSEL(0));
mxc_audmux_v2_configure_port(0,
MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
MXC_AUDMUX_V2_PTCR_TCSEL(3) |
MXC_AUDMUX_V2_PTCR_TCLKDIR, /* clock is output */
MXC_AUDMUX_V2_PDCR_RXDSEL(3));
platform_add_devices(devices, ARRAY_SIZE(devices)); platform_add_devices(devices, ARRAY_SIZE(devices));
mxc_register_device(&mxc_uart_device0, &uart_pdata); mxc_register_device(&mxc_uart_device0, &uart_pdata);
mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info); mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info);
mxc_register_device(&imx_ssi_device0, &pcm043_ssi_pdata);
mxc_register_device(&mxc_uart_device1, &uart_pdata); mxc_register_device(&mxc_uart_device1, &uart_pdata);
...@@ -235,6 +375,20 @@ static void __init mxc_board_init(void) ...@@ -235,6 +375,20 @@ static void __init mxc_board_init(void)
mxc_register_device(&mx3_ipu, &mx3_ipu_data); mxc_register_device(&mx3_ipu, &mx3_ipu_data);
mxc_register_device(&mx3_fb, &mx3fb_pdata); mxc_register_device(&mx3_fb, &mx3fb_pdata);
#if defined(CONFIG_USB_ULPI)
if (otg_mode_host) {
otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
mxc_register_device(&mxc_otg_host, &otg_pdata);
}
mxc_register_device(&mxc_usbh1, &usbh1_pdata);
#endif
if (!otg_mode_host)
mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
} }
static void __init pcm043_timer_init(void) static void __init pcm043_timer_init(void)
...@@ -248,9 +402,9 @@ struct sys_timer pcm043_timer = { ...@@ -248,9 +402,9 @@ struct sys_timer pcm043_timer = {
MACHINE_START(PCM043, "Phytec Phycore pcm043") MACHINE_START(PCM043, "Phytec Phycore pcm043")
/* Maintainer: Pengutronix */ /* Maintainer: Pengutronix */
.phys_io = AIPS1_BASE_ADDR, .phys_io = MX35_AIPS1_BASE_ADDR,
.io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, .io_pg_offst = ((MX35_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100, .boot_params = MX3x_PHYS_OFFSET + 0x100,
.map_io = mx35_map_io, .map_io = mx35_map_io,
.init_irq = mx35_init_irq, .init_irq = mx35_init_irq,
.init_machine = mxc_board_init, .init_machine = mxc_board_init,
......
arch/arm/mach-mx3/qong.c → arch/arm/mach-mx3/mach-qong.c
浏览文件 @ b93a4afc
...@@ -43,7 +43,7 @@ ...@@ -43,7 +43,7 @@
#define QONG_FPGA_VERSION(major, minor, rev) \ #define QONG_FPGA_VERSION(major, minor, rev) \
(((major & 0xF) << 12) | ((minor & 0xF) << 8) | (rev & 0xFF)) (((major & 0xF) << 12) | ((minor & 0xF) << 8) | (rev & 0xFF))
#define QONG_FPGA_BASEADDR CS1_BASE_ADDR #define QONG_FPGA_BASEADDR MX31_CS1_BASE_ADDR
#define QONG_FPGA_PERIPH_SIZE (1 << 24) #define QONG_FPGA_PERIPH_SIZE (1 << 24)
#define QONG_FPGA_CTRL_BASEADDR QONG_FPGA_BASEADDR #define QONG_FPGA_CTRL_BASEADDR QONG_FPGA_BASEADDR
...@@ -115,8 +115,8 @@ static struct physmap_flash_data qong_flash_data = { ...@@ -115,8 +115,8 @@ static struct physmap_flash_data qong_flash_data = {
}; };
static struct resource qong_flash_resource = { static struct resource qong_flash_resource = {
.start = CS0_BASE_ADDR, .start = MX31_CS0_BASE_ADDR,
.end = CS0_BASE_ADDR + QONG_NOR_SIZE - 1, .end = MX31_CS0_BASE_ADDR + QONG_NOR_SIZE - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}; };
...@@ -180,8 +180,8 @@ static struct platform_nand_data qong_nand_data = { ...@@ -180,8 +180,8 @@ static struct platform_nand_data qong_nand_data = {
}; };
static struct resource qong_nand_resource = { static struct resource qong_nand_resource = {
.start = CS3_BASE_ADDR, .start = MX31_CS3_BASE_ADDR,
.end = CS3_BASE_ADDR + SZ_32M - 1, .end = MX31_CS3_BASE_ADDR + SZ_32M - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}; };
...@@ -198,9 +198,7 @@ static struct platform_device qong_nand_device = { ...@@ -198,9 +198,7 @@ static struct platform_device qong_nand_device = {
static void __init qong_init_nand_mtd(void) static void __init qong_init_nand_mtd(void)
{ {
/* init CS */ /* init CS */
__raw_writel(0x00004f00, CSCR_U(3)); mx31_setup_weimcs(3, 0x00004f00, 0x20013b31, 0x00020800);
__raw_writel(0x20013b31, CSCR_L(3));
__raw_writel(0x00020800, CSCR_A(3));
mxc_iomux_set_gpr(MUX_SDCTL_CSD1_SEL, true); mxc_iomux_set_gpr(MUX_SDCTL_CSD1_SEL, true);
/* enable pin */ /* enable pin */
...@@ -275,9 +273,9 @@ static struct sys_timer qong_timer = { ...@@ -275,9 +273,9 @@ static struct sys_timer qong_timer = {
MACHINE_START(QONG, "Dave/DENX QongEVB-LITE") MACHINE_START(QONG, "Dave/DENX QongEVB-LITE")
/* Maintainer: DENX Software Engineering GmbH */ /* Maintainer: DENX Software Engineering GmbH */
.phys_io = AIPS1_BASE_ADDR, .phys_io = MX31_AIPS1_BASE_ADDR,
.io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100, .boot_params = MX3x_PHYS_OFFSET + 0x100,
.map_io = mx31_map_io, .map_io = mx31_map_io,
.init_irq = mx31_init_irq, .init_irq = mx31_init_irq,
.init_machine = mxc_board_init, .init_machine = mxc_board_init,
......
arch/arm/mach-mx3/mx31lite-db.c
浏览文件 @ b93a4afc
...@@ -67,6 +67,13 @@ static unsigned int litekit_db_board_pins[] __initdata = { ...@@ -67,6 +67,13 @@ static unsigned int litekit_db_board_pins[] __initdata = {
MX31_PIN_CSPI1_SS0__SS0, MX31_PIN_CSPI1_SS0__SS0,
MX31_PIN_CSPI1_SS1__SS1, MX31_PIN_CSPI1_SS1__SS1,
MX31_PIN_CSPI1_SS2__SS2, MX31_PIN_CSPI1_SS2__SS2,
/* SDHC1 */
MX31_PIN_SD1_DATA0__SD1_DATA0,
MX31_PIN_SD1_DATA1__SD1_DATA1,
MX31_PIN_SD1_DATA2__SD1_DATA2,
MX31_PIN_SD1_DATA3__SD1_DATA3,
MX31_PIN_SD1_CLK__SD1_CLK,
MX31_PIN_SD1_CMD__SD1_CMD,
}; };
/* UART */ /* UART */
...@@ -79,11 +86,11 @@ static struct imxuart_platform_data uart_pdata __initdata = { ...@@ -79,11 +86,11 @@ static struct imxuart_platform_data uart_pdata __initdata = {
static int gpio_det, gpio_wp; static int gpio_det, gpio_wp;
#define MMC_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ #define MMC_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) PAD_CTL_ODE_CMOS)
static int mxc_mmc1_get_ro(struct device *dev) static int mxc_mmc1_get_ro(struct device *dev)
{ {
return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_LCS0)); return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_GPIO1_6));
} }
static int mxc_mmc1_init(struct device *dev, static int mxc_mmc1_init(struct device *dev,
...@@ -94,12 +101,17 @@ static int mxc_mmc1_init(struct device *dev, ...@@ -94,12 +101,17 @@ static int mxc_mmc1_init(struct device *dev,
gpio_det = IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1); gpio_det = IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1);
gpio_wp = IOMUX_TO_GPIO(MX31_PIN_GPIO1_6); gpio_wp = IOMUX_TO_GPIO(MX31_PIN_GPIO1_6);
mxc_iomux_set_pad(MX31_PIN_SD1_DATA0, MMC_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_SD1_DATA0,
mxc_iomux_set_pad(MX31_PIN_SD1_DATA1, MMC_PAD_CFG); MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
mxc_iomux_set_pad(MX31_PIN_SD1_DATA2, MMC_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_SD1_DATA1,
mxc_iomux_set_pad(MX31_PIN_SD1_DATA3, MMC_PAD_CFG); MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
mxc_iomux_set_pad(MX31_PIN_SD1_DATA2,
MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
mxc_iomux_set_pad(MX31_PIN_SD1_DATA3,
MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
mxc_iomux_set_pad(MX31_PIN_SD1_CMD,
MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
mxc_iomux_set_pad(MX31_PIN_SD1_CLK, MMC_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_SD1_CLK, MMC_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_SD1_CMD, MMC_PAD_CFG);
ret = gpio_request(gpio_det, "MMC detect"); ret = gpio_request(gpio_det, "MMC detect");
if (ret) if (ret)
...@@ -113,7 +125,7 @@ static int mxc_mmc1_init(struct device *dev, ...@@ -113,7 +125,7 @@ static int mxc_mmc1_init(struct device *dev,
gpio_direction_input(gpio_wp); gpio_direction_input(gpio_wp);
ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_DCD_DCE1), detect_irq, ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_DCD_DCE1), detect_irq,
IRQF_DISABLED | IRQF_TRIGGER_FALLING, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
"MMC detect", data); "MMC detect", data);
if (ret) if (ret)
goto exit_free_wp; goto exit_free_wp;
...@@ -133,7 +145,7 @@ static void mxc_mmc1_exit(struct device *dev, void *data) ...@@ -133,7 +145,7 @@ static void mxc_mmc1_exit(struct device *dev, void *data)
{ {
gpio_free(gpio_det); gpio_free(gpio_det);
gpio_free(gpio_wp); gpio_free(gpio_wp);
free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), data); free_irq(IOMUX_TO_IRQ(MX31_PIN_DCD_DCE1), data);
} }
static struct imxmmc_platform_data mmc_pdata = { static struct imxmmc_platform_data mmc_pdata = {
......
arch/arm/mach-mx3/mx31moboard-devboard.c
浏览文件 @ b93a4afc
...@@ -49,6 +49,9 @@ static unsigned int devboard_pins[] = { ...@@ -49,6 +49,9 @@ static unsigned int devboard_pins[] = {
MX31_PIN_CSPI1_SS2__USBH1_RCV, MX31_PIN_CSPI1_SCLK__USBH1_OEB, MX31_PIN_CSPI1_SS2__USBH1_RCV, MX31_PIN_CSPI1_SCLK__USBH1_OEB,
MX31_PIN_CSPI1_SPI_RDY__USBH1_FS, MX31_PIN_SFS6__USBH1_SUSPEND, MX31_PIN_CSPI1_SPI_RDY__USBH1_FS, MX31_PIN_SFS6__USBH1_SUSPEND,
MX31_PIN_NFRE_B__GPIO1_11, MX31_PIN_NFALE__GPIO1_12, MX31_PIN_NFRE_B__GPIO1_11, MX31_PIN_NFALE__GPIO1_12,
/* SEL */
MX31_PIN_DTR_DCE1__GPIO2_8, MX31_PIN_DSR_DCE1__GPIO2_9,
MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11,
}; };
static struct imxuart_platform_data uart_pdata = { static struct imxuart_platform_data uart_pdata = {
...@@ -108,6 +111,33 @@ static struct imxmmc_platform_data sdhc2_pdata = { ...@@ -108,6 +111,33 @@ static struct imxmmc_platform_data sdhc2_pdata = {
.exit = devboard_sdhc2_exit, .exit = devboard_sdhc2_exit,
}; };
#define SEL0 IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1)
#define SEL1 IOMUX_TO_GPIO(MX31_PIN_DSR_DCE1)
#define SEL2 IOMUX_TO_GPIO(MX31_PIN_RI_DCE1)
#define SEL3 IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1)
static void devboard_init_sel_gpios(void)
{
if (!gpio_request(SEL0, "sel0")) {
gpio_direction_input(SEL0);
gpio_export(SEL0, true);
}
if (!gpio_request(SEL1, "sel1")) {
gpio_direction_input(SEL1);
gpio_export(SEL1, true);
}
if (!gpio_request(SEL2, "sel2")) {
gpio_direction_input(SEL2);
gpio_export(SEL2, true);
}
if (!gpio_request(SEL3, "sel3")) {
gpio_direction_input(SEL3);
gpio_export(SEL3, true);
}
}
#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ #define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
...@@ -196,5 +226,7 @@ void __init mx31moboard_devboard_init(void) ...@@ -196,5 +226,7 @@ void __init mx31moboard_devboard_init(void)
mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata); mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata);
devboard_init_sel_gpios();
devboard_usbh1_init(); devboard_usbh1_init();
} }
arch/arm/mach-mx3/mx31moboard-marxbot.c
浏览文件 @ b93a4afc
...@@ -66,6 +66,9 @@ static unsigned int marxbot_pins[] = { ...@@ -66,6 +66,9 @@ static unsigned int marxbot_pins[] = {
MX31_PIN_CSPI1_SS2__USBH1_RCV, MX31_PIN_CSPI1_SCLK__USBH1_OEB, MX31_PIN_CSPI1_SS2__USBH1_RCV, MX31_PIN_CSPI1_SCLK__USBH1_OEB,
MX31_PIN_CSPI1_SPI_RDY__USBH1_FS, MX31_PIN_SFS6__USBH1_SUSPEND, MX31_PIN_CSPI1_SPI_RDY__USBH1_FS, MX31_PIN_SFS6__USBH1_SUSPEND,
MX31_PIN_NFRE_B__GPIO1_11, MX31_PIN_NFALE__GPIO1_12, MX31_PIN_NFRE_B__GPIO1_11, MX31_PIN_NFALE__GPIO1_12,
/* SEL */
MX31_PIN_DTR_DCE1__GPIO2_8, MX31_PIN_DSR_DCE1__GPIO2_9,
MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11,
}; };
#define SDHC2_CD IOMUX_TO_GPIO(MX31_PIN_ATA_DIOR) #define SDHC2_CD IOMUX_TO_GPIO(MX31_PIN_ATA_DIOR)
...@@ -127,12 +130,12 @@ static struct imxmmc_platform_data sdhc2_pdata = { ...@@ -127,12 +130,12 @@ static struct imxmmc_platform_data sdhc2_pdata = {
static void dspics_resets_init(void) static void dspics_resets_init(void)
{ {
if (!gpio_request(TRSLAT_RST_B, "translator-rst")) { if (!gpio_request(TRSLAT_RST_B, "translator-rst")) {
gpio_direction_output(TRSLAT_RST_B, 1); gpio_direction_output(TRSLAT_RST_B, 0);
gpio_export(TRSLAT_RST_B, false); gpio_export(TRSLAT_RST_B, false);
} }
if (!gpio_request(DSPICS_RST_B, "dspics-rst")) { if (!gpio_request(DSPICS_RST_B, "dspics-rst")) {
gpio_direction_output(DSPICS_RST_B, 1); gpio_direction_output(DSPICS_RST_B, 0);
gpio_export(DSPICS_RST_B, false); gpio_export(DSPICS_RST_B, false);
} }
} }
...@@ -200,7 +203,7 @@ static int __init marxbot_cam_init(void) ...@@ -200,7 +203,7 @@ static int __init marxbot_cam_init(void)
int ret = gpio_request(CAM_CHOICE, "cam-choice"); int ret = gpio_request(CAM_CHOICE, "cam-choice");
if (ret) if (ret)
return ret; return ret;
gpio_direction_output(CAM_CHOICE, 1); gpio_direction_output(CAM_CHOICE, 0);
ret = gpio_request(BASECAM_RST_B, "basecam-reset"); ret = gpio_request(BASECAM_RST_B, "basecam-reset");
if (ret) if (ret)
...@@ -223,6 +226,34 @@ static int __init marxbot_cam_init(void) ...@@ -223,6 +226,34 @@ static int __init marxbot_cam_init(void)
return 0; return 0;
} }
#define SEL0 IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1)
#define SEL1 IOMUX_TO_GPIO(MX31_PIN_DSR_DCE1)
#define SEL2 IOMUX_TO_GPIO(MX31_PIN_RI_DCE1)
#define SEL3 IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1)
static void marxbot_init_sel_gpios(void)
{
if (!gpio_request(SEL0, "sel0")) {
gpio_direction_input(SEL0);
gpio_export(SEL0, true);
}
if (!gpio_request(SEL1, "sel1")) {
gpio_direction_input(SEL1);
gpio_export(SEL1, true);
}
if (!gpio_request(SEL2, "sel2")) {
gpio_direction_input(SEL2);
gpio_export(SEL2, true);
}
if (!gpio_request(SEL3, "sel3")) {
gpio_direction_input(SEL3);
gpio_export(SEL3, true);
}
}
#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ #define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
...@@ -307,6 +338,8 @@ void __init mx31moboard_marxbot_init(void) ...@@ -307,6 +338,8 @@ void __init mx31moboard_marxbot_init(void)
mxc_iomux_setup_multiple_pins(marxbot_pins, ARRAY_SIZE(marxbot_pins), mxc_iomux_setup_multiple_pins(marxbot_pins, ARRAY_SIZE(marxbot_pins),
"marxbot"); "marxbot");
marxbot_init_sel_gpios();
dspics_resets_init(); dspics_resets_init();
mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata); mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata);
......
arch/arm/mach-mx3/mx31moboard-smartbot.c 0 → 100644
浏览文件 @ b93a4afc
/*
* Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <linux/types.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/imx-uart.h>
#include <mach/iomux-mx3.h>
#include <media/soc_camera.h>
#include "devices.h"
static unsigned int smartbot_pins[] = {
/* UART1 */
MX31_PIN_CTS2__CTS2, MX31_PIN_RTS2__RTS2,
MX31_PIN_TXD2__TXD2, MX31_PIN_RXD2__RXD2,
/* CSI */
MX31_PIN_CSI_D4__CSI_D4, MX31_PIN_CSI_D5__CSI_D5,
MX31_PIN_CSI_D6__CSI_D6, MX31_PIN_CSI_D7__CSI_D7,
MX31_PIN_CSI_D8__CSI_D8, MX31_PIN_CSI_D9__CSI_D9,
MX31_PIN_CSI_D10__CSI_D10, MX31_PIN_CSI_D11__CSI_D11,
MX31_PIN_CSI_D12__CSI_D12, MX31_PIN_CSI_D13__CSI_D13,
MX31_PIN_CSI_D14__CSI_D14, MX31_PIN_CSI_D15__CSI_D15,
MX31_PIN_CSI_HSYNC__CSI_HSYNC, MX31_PIN_CSI_MCLK__CSI_MCLK,
MX31_PIN_CSI_PIXCLK__CSI_PIXCLK, MX31_PIN_CSI_VSYNC__CSI_VSYNC,
MX31_PIN_GPIO3_0__GPIO3_0, MX31_PIN_GPIO3_1__GPIO3_1,
/* ENABLES */
MX31_PIN_DTR_DCE1__GPIO2_8, MX31_PIN_DSR_DCE1__GPIO2_9,
MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11,
};
static struct imxuart_platform_data uart_pdata = {
.flags = IMXUART_HAVE_RTSCTS,
};
#define CAM_POWER IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)
#define CAM_RST_B IOMUX_TO_GPIO(MX31_PIN_GPIO3_0)
static int smartbot_cam_power(struct device *dev, int on)
{
gpio_set_value(CAM_POWER, !on);
return 0;
}
static int smartbot_cam_reset(struct device *dev)
{
gpio_set_value(CAM_RST_B, 0);
udelay(100);
gpio_set_value(CAM_RST_B, 1);
return 0;
}
static struct i2c_board_info smartbot_i2c_devices[] = {
{
I2C_BOARD_INFO("mt9t031", 0x5d),
},
};
static struct soc_camera_link base_iclink = {
.bus_id = 0, /* Must match with the camera ID */
.power = smartbot_cam_power,
.reset = smartbot_cam_reset,
.board_info = &smartbot_i2c_devices[0],
.i2c_adapter_id = 0,
.module_name = "mt9t031",
};
static struct platform_device smartbot_camera[] = {
{
.name = "soc-camera-pdrv",
.id = 0,
.dev = {
.platform_data = &base_iclink,
},
},
};
static struct platform_device *smartbot_cameras[] __initdata = {
&smartbot_camera[0],
};
static int __init smartbot_cam_init(void)
{
int ret = gpio_request(CAM_RST_B, "cam-reset");
if (ret)
return ret;
gpio_direction_output(CAM_RST_B, 1);
ret = gpio_request(CAM_POWER, "cam-standby");
if (ret)
return ret;
gpio_direction_output(CAM_POWER, 0);
return 0;
}
#define POWER_EN IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1)
#define DSPIC_RST_B IOMUX_TO_GPIO(MX31_PIN_DSR_DCE1)
#define TRSLAT_RST_B IOMUX_TO_GPIO(MX31_PIN_RI_DCE1)
#define SEL3 IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1)
static void smartbot_resets_init(void)
{
if (!gpio_request(POWER_EN, "power-enable")) {
gpio_direction_output(POWER_EN, 0);
gpio_export(POWER_EN, false);
}
if (!gpio_request(DSPIC_RST_B, "dspic-rst")) {
gpio_direction_output(DSPIC_RST_B, 0);
gpio_export(DSPIC_RST_B, false);
}
if (!gpio_request(TRSLAT_RST_B, "translator-rst")) {
gpio_direction_output(TRSLAT_RST_B, 0);
gpio_export(TRSLAT_RST_B, false);
}
if (!gpio_request(SEL3, "sel3")) {
gpio_direction_input(SEL3);
gpio_export(SEL3, true);
}
}
/*
* system init for baseboard usage. Will be called by mx31moboard init.
*/
void __init mx31moboard_smartbot_init(void)
{
printk(KERN_INFO "Initializing mx31smartbot peripherals\n");
mxc_iomux_setup_multiple_pins(smartbot_pins, ARRAY_SIZE(smartbot_pins),
"smartbot");
mxc_register_device(&mxc_uart_device1, &uart_pdata);
smartbot_resets_init();
smartbot_cam_init();
platform_add_devices(smartbot_cameras, ARRAY_SIZE(smartbot_cameras));
}
arch/arm/mach-mx5/Kconfig 0 → 100644
浏览文件 @ b93a4afc
if ARCH_MX5
config ARCH_MX51
bool
default y
select MXC_TZIC
select ARCH_MXC_IOMUX_V3
comment "MX5 platforms:"
config MACH_MX51_BABBAGE
bool "Support MX51 BABBAGE platforms"
help
Include support for MX51 Babbage platform, also known as MX51EVK in
u-boot. This includes specific configurations for the board and its
peripherals.
endif
arch/arm/mach-mx5/Makefile 0 → 100644
浏览文件 @ b93a4afc
#
# Makefile for the linux kernel.
#
# Object file lists.
obj-y := cpu.o mm.o clock-mx51.o devices.o
obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o
arch/arm/mach-mx5/Makefile.boot 0 → 100644
浏览文件 @ b93a4afc
zreladdr-y := 0x90008000
params_phys-y := 0x90000100
initrd_phys-y := 0x90800000
arch/arm/mach-mx5/board-mx51_babbage.c 0 → 100644
浏览文件 @ b93a4afc
/*
* Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/imx-uart.h>
#include <mach/iomux-mx51.h>
#include <asm/irq.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include "devices.h"
static struct platform_device *devices[] __initdata = {
&mxc_fec_device,
};
static struct pad_desc mx51babbage_pads[] = {
/* UART1 */
MX51_PAD_UART1_RXD__UART1_RXD,
MX51_PAD_UART1_TXD__UART1_TXD,
MX51_PAD_UART1_RTS__UART1_RTS,
MX51_PAD_UART1_CTS__UART1_CTS,
/* UART2 */
MX51_PAD_UART2_RXD__UART2_RXD,
MX51_PAD_UART2_TXD__UART2_TXD,
/* UART3 */
MX51_PAD_EIM_D25__UART3_RXD,
MX51_PAD_EIM_D26__UART3_TXD,
MX51_PAD_EIM_D27__UART3_RTS,
MX51_PAD_EIM_D24__UART3_CTS,
};
/* Serial ports */
#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
static struct imxuart_platform_data uart_pdata = {
.flags = IMXUART_HAVE_RTSCTS,
};
static inline void mxc_init_imx_uart(void)
{
mxc_register_device(&mxc_uart_device0, &uart_pdata);
mxc_register_device(&mxc_uart_device1, &uart_pdata);
mxc_register_device(&mxc_uart_device2, &uart_pdata);
}
#else /* !SERIAL_IMX */
static inline void mxc_init_imx_uart(void)
{
}
#endif /* SERIAL_IMX */
/*
* Board specific initialization.
*/
static void __init mxc_board_init(void)
{
mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads,
ARRAY_SIZE(mx51babbage_pads));
mxc_init_imx_uart();
platform_add_devices(devices, ARRAY_SIZE(devices));
}
static void __init mx51_babbage_timer_init(void)
{
mx51_clocks_init(32768, 24000000, 22579200, 0);
}
static struct sys_timer mxc_timer = {
.init = mx51_babbage_timer_init,
};
MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board")
/* Maintainer: Amit Kucheria <amit.kucheria@canonical.com> */
.phys_io = MX51_AIPS1_BASE_ADDR,
.io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100,
.map_io = mx51_map_io,
.init_irq = mx51_init_irq,
.init_machine = mxc_board_init,
.timer = &mxc_timer,
MACHINE_END
arch/arm/mach-mx5/clock-mx51.c 0 → 100644
浏览文件 @ b93a4afc
/*
* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <asm/clkdev.h>
#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/clock.h>
#include "crm_regs.h"
/* External clock values passed-in by the board code */
static unsigned long external_high_reference, external_low_reference;
static unsigned long oscillator_reference, ckih2_reference;
static struct clk osc_clk;
static struct clk pll1_main_clk;
static struct clk pll1_sw_clk;
static struct clk pll2_sw_clk;
static struct clk pll3_sw_clk;
static struct clk lp_apm_clk;
static struct clk periph_apm_clk;
static struct clk ahb_clk;
static struct clk ipg_clk;
#define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */
static int _clk_ccgr_enable(struct clk *clk)
{
u32 reg;
reg = __raw_readl(clk->enable_reg);
reg |= MXC_CCM_CCGRx_MOD_ON << clk->enable_shift;
__raw_writel(reg, clk->enable_reg);
return 0;
}
static void _clk_ccgr_disable(struct clk *clk)
{
u32 reg;
reg = __raw_readl(clk->enable_reg);
reg &= ~(MXC_CCM_CCGRx_MOD_OFF << clk->enable_shift);
__raw_writel(reg, clk->enable_reg);
}
static void _clk_ccgr_disable_inwait(struct clk *clk)
{
u32 reg;
reg = __raw_readl(clk->enable_reg);
reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
reg |= MXC_CCM_CCGRx_MOD_IDLE << clk->enable_shift;
__raw_writel(reg, clk->enable_reg);
}
/*
* For the 4-to-1 muxed input clock
*/
static inline u32 _get_mux(struct clk *parent, struct clk *m0,
struct clk *m1, struct clk *m2, struct clk *m3)
{
if (parent == m0)
return 0;
else if (parent == m1)
return 1;
else if (parent == m2)
return 2;
else if (parent == m3)
return 3;
else
BUG();
return -EINVAL;
}
static inline void __iomem *_get_pll_base(struct clk *pll)
{
if (pll == &pll1_main_clk)
return MX51_DPLL1_BASE;
else if (pll == &pll2_sw_clk)
return MX51_DPLL2_BASE;
else if (pll == &pll3_sw_clk)
return MX51_DPLL3_BASE;
else
BUG();
return NULL;
}
static unsigned long clk_pll_get_rate(struct clk *clk)
{
long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl;
void __iomem *pllbase;
s64 temp;
unsigned long parent_rate;
parent_rate = clk_get_rate(clk->parent);
pllbase = _get_pll_base(clk);
dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN;
if (pll_hfsm == 0) {
dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);
dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);
dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);
} else {
dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP);
dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD);
dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN);
}
pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK;
mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET;
mfi = (mfi <= 5) ? 5 : mfi;
mfd = dp_mfd & MXC_PLL_DP_MFD_MASK;
mfn = mfn_abs = dp_mfn & MXC_PLL_DP_MFN_MASK;
/* Sign extend to 32-bits */
if (mfn >= 0x04000000) {
mfn |= 0xFC000000;
mfn_abs = -mfn;
}
ref_clk = 2 * parent_rate;
if (dbl != 0)
ref_clk *= 2;
ref_clk /= (pdf + 1);
temp = (u64) ref_clk * mfn_abs;
do_div(temp, mfd + 1);
if (mfn < 0)
temp = -temp;
temp = (ref_clk * mfi) + temp;
return temp;
}
static int _clk_pll_set_rate(struct clk *clk, unsigned long rate)
{
u32 reg;
void __iomem *pllbase;
long mfi, pdf, mfn, mfd = 999999;
s64 temp64;
unsigned long quad_parent_rate;
unsigned long pll_hfsm, dp_ctl;
unsigned long parent_rate;
parent_rate = clk_get_rate(clk->parent);
pllbase = _get_pll_base(clk);
quad_parent_rate = 4 * parent_rate;
pdf = mfi = -1;
while (++pdf < 16 && mfi < 5)
mfi = rate * (pdf+1) / quad_parent_rate;
if (mfi > 15)
return -EINVAL;
pdf--;
temp64 = rate * (pdf+1) - quad_parent_rate * mfi;
do_div(temp64, quad_parent_rate/1000000);
mfn = (long)temp64;
dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
/* use dpdck0_2 */
__raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL);
pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
if (pll_hfsm == 0) {
reg = mfi << 4 | pdf;
__raw_writel(reg, pllbase + MXC_PLL_DP_OP);
__raw_writel(mfd, pllbase + MXC_PLL_DP_MFD);
__raw_writel(mfn, pllbase + MXC_PLL_DP_MFN);
} else {
reg = mfi << 4 | pdf;
__raw_writel(reg, pllbase + MXC_PLL_DP_HFS_OP);
__raw_writel(mfd, pllbase + MXC_PLL_DP_HFS_MFD);
__raw_writel(mfn, pllbase + MXC_PLL_DP_HFS_MFN);
}
return 0;
}
static int _clk_pll_enable(struct clk *clk)
{
u32 reg;
void __iomem *pllbase;
int i = 0;
pllbase = _get_pll_base(clk);
reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN;
__raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
/* Wait for lock */
do {
reg = __raw_readl(pllbase + MXC_PLL_DP_CTL);
if (reg & MXC_PLL_DP_CTL_LRF)
break;
udelay(1);
} while (++i < MAX_DPLL_WAIT_TRIES);
if (i == MAX_DPLL_WAIT_TRIES) {
pr_err("MX5: pll locking failed\n");
return -EINVAL;
}
return 0;
}
static void _clk_pll_disable(struct clk *clk)
{
u32 reg;
void __iomem *pllbase;
pllbase = _get_pll_base(clk);
reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN;
__raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
}
static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent)
{
u32 reg, step;
reg = __raw_readl(MXC_CCM_CCSR);
/* When switching from pll_main_clk to a bypass clock, first select a
* multiplexed clock in 'step_sel', then shift the glitchless mux
* 'pll1_sw_clk_sel'.
*
* When switching back, do it in reverse order
*/
if (parent == &pll1_main_clk) {
/* Switch to pll1_main_clk */
reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
__raw_writel(reg, MXC_CCM_CCSR);
/* step_clk mux switched to lp_apm, to save power. */
reg = __raw_readl(MXC_CCM_CCSR);
reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK;
reg |= (MXC_CCM_CCSR_STEP_SEL_LP_APM <<
MXC_CCM_CCSR_STEP_SEL_OFFSET);
} else {
if (parent == &lp_apm_clk) {
step = MXC_CCM_CCSR_STEP_SEL_LP_APM;
} else if (parent == &pll2_sw_clk) {
step = MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED;
} else if (parent == &pll3_sw_clk) {
step = MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED;
} else
return -EINVAL;
reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK;
reg |= (step << MXC_CCM_CCSR_STEP_SEL_OFFSET);
__raw_writel(reg, MXC_CCM_CCSR);
/* Switch to step_clk */
reg = __raw_readl(MXC_CCM_CCSR);
reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
}
__raw_writel(reg, MXC_CCM_CCSR);
return 0;
}
static unsigned long clk_pll1_sw_get_rate(struct clk *clk)
{
u32 reg, div;
unsigned long parent_rate;
parent_rate = clk_get_rate(clk->parent);
reg = __raw_readl(MXC_CCM_CCSR);
if (clk->parent == &pll2_sw_clk) {
div = ((reg & MXC_CCM_CCSR_PLL2_PODF_MASK) >>
MXC_CCM_CCSR_PLL2_PODF_OFFSET) + 1;
} else if (clk->parent == &pll3_sw_clk) {
div = ((reg & MXC_CCM_CCSR_PLL3_PODF_MASK) >>
MXC_CCM_CCSR_PLL3_PODF_OFFSET) + 1;
} else
div = 1;
return parent_rate / div;
}
static int _clk_pll2_sw_set_parent(struct clk *clk, struct clk *parent)
{
u32 reg;
reg = __raw_readl(MXC_CCM_CCSR);
if (parent == &pll2_sw_clk)
reg &= ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL;
else
reg |= MXC_CCM_CCSR_PLL2_SW_CLK_SEL;
__raw_writel(reg, MXC_CCM_CCSR);
return 0;
}
static int _clk_lp_apm_set_parent(struct clk *clk, struct clk *parent)
{
u32 reg;
if (parent == &osc_clk)
reg = __raw_readl(MXC_CCM_CCSR) & ~MXC_CCM_CCSR_LP_APM_SEL;
else
return -EINVAL;
__raw_writel(reg, MXC_CCM_CCSR);
return 0;
}
static unsigned long clk_arm_get_rate(struct clk *clk)
{
u32 cacrr, div;
unsigned long parent_rate;
parent_rate = clk_get_rate(clk->parent);
cacrr = __raw_readl(MXC_CCM_CACRR);
div = (cacrr & MXC_CCM_CACRR_ARM_PODF_MASK) + 1;
return parent_rate / div;
}
static int _clk_periph_apm_set_parent(struct clk *clk, struct clk *parent)
{
u32 reg, mux;
int i = 0;
mux = _get_mux(parent, &pll1_sw_clk, &pll3_sw_clk, &lp_apm_clk, NULL);
reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK;
reg |= mux << MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET;
__raw_writel(reg, MXC_CCM_CBCMR);
/* Wait for lock */
do {
reg = __raw_readl(MXC_CCM_CDHIPR);
if (!(reg & MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY))
break;
udelay(1);
} while (++i < MAX_DPLL_WAIT_TRIES);
if (i == MAX_DPLL_WAIT_TRIES) {
pr_err("MX5: Set parent for periph_apm clock failed\n");
return -EINVAL;
}
return 0;
}
static int _clk_main_bus_set_parent(struct clk *clk, struct clk *parent)
{
u32 reg;
reg = __raw_readl(MXC_CCM_CBCDR);
if (parent == &pll2_sw_clk)
reg &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL;
else if (parent == &periph_apm_clk)
reg |= MXC_CCM_CBCDR_PERIPH_CLK_SEL;
else
return -EINVAL;
__raw_writel(reg, MXC_CCM_CBCDR);
return 0;
}
static struct clk main_bus_clk = {
.parent = &pll2_sw_clk,
.set_parent = _clk_main_bus_set_parent,
};
static unsigned long clk_ahb_get_rate(struct clk *clk)
{
u32 reg, div;
unsigned long parent_rate;
parent_rate = clk_get_rate(clk->parent);
reg = __raw_readl(MXC_CCM_CBCDR);
div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1;
return parent_rate / div;
}
static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate)
{
u32 reg, div;
unsigned long parent_rate;
int i = 0;
parent_rate = clk_get_rate(clk->parent);
div = parent_rate / rate;
if (div > 8 || div < 1 || ((parent_rate / div) != rate))
return -EINVAL;
reg = __raw_readl(MXC_CCM_CBCDR);
reg &= ~MXC_CCM_CBCDR_AHB_PODF_MASK;
reg |= (div - 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET;
__raw_writel(reg, MXC_CCM_CBCDR);
/* Wait for lock */
do {
reg = __raw_readl(MXC_CCM_CDHIPR);
if (!(reg & MXC_CCM_CDHIPR_AHB_PODF_BUSY))
break;
udelay(1);
} while (++i < MAX_DPLL_WAIT_TRIES);
if (i == MAX_DPLL_WAIT_TRIES) {
pr_err("MX5: clk_ahb_set_rate failed\n");
return -EINVAL;
}
return 0;
}
static unsigned long _clk_ahb_round_rate(struct clk *clk,
unsigned long rate)
{
u32 div;
unsigned long parent_rate;
parent_rate = clk_get_rate(clk->parent);
div = parent_rate / rate;
if (div > 8)
div = 8;
else if (div == 0)
div++;
return parent_rate / div;
}
static int _clk_max_enable(struct clk *clk)
{
u32 reg;
_clk_ccgr_enable(clk);
/* Handshake with MAX when LPM is entered. */
reg = __raw_readl(MXC_CCM_CLPCR);
reg &= ~MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS;
__raw_writel(reg, MXC_CCM_CLPCR);
return 0;
}
static void _clk_max_disable(struct clk *clk)
{
u32 reg;
_clk_ccgr_disable_inwait(clk);
/* No Handshake with MAX when LPM is entered as its disabled. */
reg = __raw_readl(MXC_CCM_CLPCR);
reg |= MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS;
__raw_writel(reg, MXC_CCM_CLPCR);
}
static unsigned long clk_ipg_get_rate(struct clk *clk)
{
u32 reg, div;
unsigned long parent_rate;
parent_rate = clk_get_rate(clk->parent);
reg = __raw_readl(MXC_CCM_CBCDR);
div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1;
return parent_rate / div;
}
static unsigned long clk_ipg_per_get_rate(struct clk *clk)
{
u32 reg, prediv1, prediv2, podf;
unsigned long parent_rate;
parent_rate = clk_get_rate(clk->parent);
if (clk->parent == &main_bus_clk || clk->parent == &lp_apm_clk) {
/* the main_bus_clk is the one before the DVFS engine */
reg = __raw_readl(MXC_CCM_CBCDR);
prediv1 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>
MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET) + 1;
prediv2 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>
MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET) + 1;
podf = ((reg & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>
MXC_CCM_CBCDR_PERCLK_PODF_OFFSET) + 1;
return parent_rate / (prediv1 * prediv2 * podf);
} else if (clk->parent == &ipg_clk)
return parent_rate;
else
BUG();
}
static int _clk_ipg_per_set_parent(struct clk *clk, struct clk *parent)
{
u32 reg;
reg = __raw_readl(MXC_CCM_CBCMR);
reg &= ~MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL;
reg &= ~MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL;
if (parent == &ipg_clk)
reg |= MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL;
else if (parent == &lp_apm_clk)
reg |= MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL;
else if (parent != &main_bus_clk)
return -EINVAL;
__raw_writel(reg, MXC_CCM_CBCMR);
return 0;
}
static unsigned long clk_uart_get_rate(struct clk *clk)
{
u32 reg, prediv, podf;
unsigned long parent_rate;
parent_rate = clk_get_rate(clk->parent);
reg = __raw_readl(MXC_CCM_CSCDR1);
prediv = ((reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET) + 1;
podf = ((reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1;
return parent_rate / (prediv * podf);
}
static int _clk_uart_set_parent(struct clk *clk, struct clk *parent)
{
u32 reg, mux;
mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
&lp_apm_clk);
reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_UART_CLK_SEL_MASK;
reg |= mux << MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET;
__raw_writel(reg, MXC_CCM_CSCMR1);
return 0;
}
static unsigned long get_high_reference_clock_rate(struct clk *clk)
{
return external_high_reference;
}
static unsigned long get_low_reference_clock_rate(struct clk *clk)
{
return external_low_reference;
}
static unsigned long get_oscillator_reference_clock_rate(struct clk *clk)
{
return oscillator_reference;
}
static unsigned long get_ckih2_reference_clock_rate(struct clk *clk)
{
return ckih2_reference;
}
/* External high frequency clock */
static struct clk ckih_clk = {
.get_rate = get_high_reference_clock_rate,
};
static struct clk ckih2_clk = {
.get_rate = get_ckih2_reference_clock_rate,
};
static struct clk osc_clk = {
.get_rate = get_oscillator_reference_clock_rate,
};
/* External low frequency (32kHz) clock */
static struct clk ckil_clk = {
.get_rate = get_low_reference_clock_rate,
};
static struct clk pll1_main_clk = {
.parent = &osc_clk,
.get_rate = clk_pll_get_rate,
.enable = _clk_pll_enable,
.disable = _clk_pll_disable,
};
/* Clock tree block diagram (WIP):
* CCM: Clock Controller Module
*
* PLL output -> |
* | CCM Switcher -> CCM_CLK_ROOT_GEN ->
* PLL bypass -> |
*
*/
/* PLL1 SW supplies to ARM core */
static struct clk pll1_sw_clk = {
.parent = &pll1_main_clk,
.set_parent = _clk_pll1_sw_set_parent,
.get_rate = clk_pll1_sw_get_rate,
};
/* PLL2 SW supplies to AXI/AHB/IP buses */
static struct clk pll2_sw_clk = {
.parent = &osc_clk,
.get_rate = clk_pll_get_rate,
.set_rate = _clk_pll_set_rate,
.set_parent = _clk_pll2_sw_set_parent,
.enable = _clk_pll_enable,
.disable = _clk_pll_disable,
};
/* PLL3 SW supplies to serial clocks like USB, SSI, etc. */
static struct clk pll3_sw_clk = {
.parent = &osc_clk,
.set_rate = _clk_pll_set_rate,
.get_rate = clk_pll_get_rate,
.enable = _clk_pll_enable,
.disable = _clk_pll_disable,
};
/* Low-power Audio Playback Mode clock */
static struct clk lp_apm_clk = {
.parent = &osc_clk,
.set_parent = _clk_lp_apm_set_parent,
};
static struct clk periph_apm_clk = {
.parent = &pll1_sw_clk,
.set_parent = _clk_periph_apm_set_parent,
};
static struct clk cpu_clk = {
.parent = &pll1_sw_clk,
.get_rate = clk_arm_get_rate,
};
static struct clk ahb_clk = {
.parent = &main_bus_clk,
.get_rate = clk_ahb_get_rate,
.set_rate = _clk_ahb_set_rate,
.round_rate = _clk_ahb_round_rate,
};
/* Main IP interface clock for access to registers */
static struct clk ipg_clk = {
.parent = &ahb_clk,
.get_rate = clk_ipg_get_rate,
};
static struct clk ipg_perclk = {
.parent = &lp_apm_clk,
.get_rate = clk_ipg_per_get_rate,
.set_parent = _clk_ipg_per_set_parent,
};
static struct clk uart_root_clk = {
.parent = &pll2_sw_clk,
.get_rate = clk_uart_get_rate,
.set_parent = _clk_uart_set_parent,
};
static struct clk ahb_max_clk = {
.parent = &ahb_clk,
.enable_reg = MXC_CCM_CCGR0,
.enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
.enable = _clk_max_enable,
.disable = _clk_max_disable,
};
static struct clk aips_tz1_clk = {
.parent = &ahb_clk,
.secondary = &ahb_max_clk,
.enable_reg = MXC_CCM_CCGR0,
.enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
.enable = _clk_ccgr_enable,
.disable = _clk_ccgr_disable_inwait,
};
static struct clk aips_tz2_clk = {
.parent = &ahb_clk,
.secondary = &ahb_max_clk,
.enable_reg = MXC_CCM_CCGR0,
.enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
.enable = _clk_ccgr_enable,
.disable = _clk_ccgr_disable_inwait,
};
static struct clk gpt_32k_clk = {
.id = 0,
.parent = &ckil_clk,
};
#define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s) \
static struct clk name = { \
.id = i, \
.enable_reg = er, \
.enable_shift = es, \
.get_rate = gr, \
.set_rate = sr, \
.enable = _clk_ccgr_enable, \
.disable = _clk_ccgr_disable, \
.parent = p, \
.secondary = s, \
}
/* DEFINE_CLOCK(name, id, enable_reg, enable_shift,
get_rate, set_rate, parent, secondary); */
/* Shared peripheral bus arbiter */
DEFINE_CLOCK(spba_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG0_OFFSET,
NULL, NULL, &ipg_clk, NULL);
/* UART */
DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG4_OFFSET,
NULL, NULL, &uart_root_clk, NULL);
DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG6_OFFSET,
NULL, NULL, &uart_root_clk, NULL);
DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG8_OFFSET,
NULL, NULL, &uart_root_clk, NULL);
DEFINE_CLOCK(uart1_ipg_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG3_OFFSET,
NULL, NULL, &ipg_clk, &aips_tz1_clk);
DEFINE_CLOCK(uart2_ipg_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG5_OFFSET,
NULL, NULL, &ipg_clk, &aips_tz1_clk);
DEFINE_CLOCK(uart3_ipg_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG7_OFFSET,
NULL, NULL, &ipg_clk, &spba_clk);
/* GPT */
DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET,
NULL, NULL, &ipg_perclk, NULL);
DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET,
NULL, NULL, &ipg_clk, NULL);
/* FEC */
DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET,
NULL, NULL, &ipg_clk, NULL);
#define _REGISTER_CLOCK(d, n, c) \
{ \
.dev_id = d, \
.con_id = n, \
.clk = &c, \
},
static struct clk_lookup lookups[] = {
_REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
_REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
_REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
_REGISTER_CLOCK(NULL, "gpt", gpt_clk)
_REGISTER_CLOCK("fec.0", NULL, fec_clk)
};
static void clk_tree_init(void)
{
u32 reg;
ipg_perclk.set_parent(&ipg_perclk, &lp_apm_clk);
/*
* Initialise the IPG PER CLK dividers to 3. IPG_PER_CLK should be at
* 8MHz, its derived from lp_apm.
*
* FIXME: Verify if true for all boards
*/
reg = __raw_readl(MXC_CCM_CBCDR);
reg &= ~MXC_CCM_CBCDR_PERCLK_PRED1_MASK;
reg &= ~MXC_CCM_CBCDR_PERCLK_PRED2_MASK;
reg &= ~MXC_CCM_CBCDR_PERCLK_PODF_MASK;
reg |= (2 << MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET);
__raw_writel(reg, MXC_CCM_CBCDR);
}
int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
unsigned long ckih1, unsigned long ckih2)
{
int i;
external_low_reference = ckil;
external_high_reference = ckih1;
ckih2_reference = ckih2;
oscillator_reference = osc;
for (i = 0; i < ARRAY_SIZE(lookups); i++)
clkdev_add(&lookups[i]);
clk_tree_init();
clk_enable(&cpu_clk);
clk_enable(&main_bus_clk);
/* System timer */
mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),
MX51_MXC_INT_GPT);
return 0;
}
arch/arm/mach-mx5/cpu.c 0 → 100644
浏览文件 @ b93a4afc
/*
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*
* This file contains the CPU initialization code.
*/
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <mach/hardware.h>
#include <asm/io.h>
static int __init post_cpu_init(void)
{
unsigned int reg;
void __iomem *base;
if (!cpu_is_mx51())
return 0;
base = MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR);
__raw_writel(0x0, base + 0x40);
__raw_writel(0x0, base + 0x44);
__raw_writel(0x0, base + 0x48);
__raw_writel(0x0, base + 0x4C);
reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
__raw_writel(reg, base + 0x50);
base = MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR);
__raw_writel(0x0, base + 0x40);
__raw_writel(0x0, base + 0x44);
__raw_writel(0x0, base + 0x48);
__raw_writel(0x0, base + 0x4C);
reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
__raw_writel(reg, base + 0x50);
return 0;
}
postcore_initcall(post_cpu_init);
arch/arm/mach-mx5/crm_regs.h 0 → 100644
浏览文件 @ b93a4afc
/*
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__
#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__
#define MX51_CCM_BASE MX51_IO_ADDRESS(MX51_CCM_BASE_ADDR)
#define MX51_DPLL1_BASE MX51_IO_ADDRESS(MX51_PLL1_BASE_ADDR)
#define MX51_DPLL2_BASE MX51_IO_ADDRESS(MX51_PLL2_BASE_ADDR)
#define MX51_DPLL3_BASE MX51_IO_ADDRESS(MX51_PLL3_BASE_ADDR)
#define MX51_CORTEXA8_BASE MX51_IO_ADDRESS(MX51_ARM_BASE_ADDR)
#define MX51_GPC_BASE MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR)
/* PLL Register Offsets */
#define MXC_PLL_DP_CTL 0x00
#define MXC_PLL_DP_CONFIG 0x04
#define MXC_PLL_DP_OP 0x08
#define MXC_PLL_DP_MFD 0x0C
#define MXC_PLL_DP_MFN 0x10
#define MXC_PLL_DP_MFNMINUS 0x14
#define MXC_PLL_DP_MFNPLUS 0x18
#define MXC_PLL_DP_HFS_OP 0x1C
#define MXC_PLL_DP_HFS_MFD 0x20
#define MXC_PLL_DP_HFS_MFN 0x24
#define MXC_PLL_DP_MFN_TOGC 0x28
#define MXC_PLL_DP_DESTAT 0x2c
/* PLL Register Bit definitions */
#define MXC_PLL_DP_CTL_MUL_CTRL 0x2000
#define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000
#define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12
#define MXC_PLL_DP_CTL_ADE 0x800
#define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400
#define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8)
#define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8
#define MXC_PLL_DP_CTL_HFSM 0x80
#define MXC_PLL_DP_CTL_PRE 0x40
#define MXC_PLL_DP_CTL_UPEN 0x20
#define MXC_PLL_DP_CTL_RST 0x10
#define MXC_PLL_DP_CTL_RCP 0x8
#define MXC_PLL_DP_CTL_PLM 0x4
#define MXC_PLL_DP_CTL_BRM0 0x2
#define MXC_PLL_DP_CTL_LRF 0x1
#define MXC_PLL_DP_CONFIG_BIST 0x8
#define MXC_PLL_DP_CONFIG_SJC_CE 0x4
#define MXC_PLL_DP_CONFIG_AREN 0x2
#define MXC_PLL_DP_CONFIG_LDREQ 0x1
#define MXC_PLL_DP_OP_MFI_OFFSET 4
#define MXC_PLL_DP_OP_MFI_MASK (0xF << 4)
#define MXC_PLL_DP_OP_PDF_OFFSET 0
#define MXC_PLL_DP_OP_PDF_MASK 0xF
#define MXC_PLL_DP_MFD_OFFSET 0
#define MXC_PLL_DP_MFD_MASK 0x07FFFFFF
#define MXC_PLL_DP_MFN_OFFSET 0x0
#define MXC_PLL_DP_MFN_MASK 0x07FFFFFF
#define MXC_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17)
#define MXC_PLL_DP_MFN_TOGC_TOG_EN (1 << 16)
#define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0
#define MXC_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF
#define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31)
#define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF
/* Register addresses of CCM*/
#define MXC_CCM_CCR (MX51_CCM_BASE + 0x00)
#define MXC_CCM_CCDR (MX51_CCM_BASE + 0x04)
#define MXC_CCM_CSR (MX51_CCM_BASE + 0x08)
#define MXC_CCM_CCSR (MX51_CCM_BASE + 0x0C)
#define MXC_CCM_CACRR (MX51_CCM_BASE + 0x10)
#define MXC_CCM_CBCDR (MX51_CCM_BASE + 0x14)
#define MXC_CCM_CBCMR (MX51_CCM_BASE + 0x18)
#define MXC_CCM_CSCMR1 (MX51_CCM_BASE + 0x1C)
#define MXC_CCM_CSCMR2 (MX51_CCM_BASE + 0x20)
#define MXC_CCM_CSCDR1 (MX51_CCM_BASE + 0x24)
#define MXC_CCM_CS1CDR (MX51_CCM_BASE + 0x28)
#define MXC_CCM_CS2CDR (MX51_CCM_BASE + 0x2C)
#define MXC_CCM_CDCDR (MX51_CCM_BASE + 0x30)
#define MXC_CCM_CHSCDR (MX51_CCM_BASE + 0x34)
#define MXC_CCM_CSCDR2 (MX51_CCM_BASE + 0x38)
#define MXC_CCM_CSCDR3 (MX51_CCM_BASE + 0x3C)
#define MXC_CCM_CSCDR4 (MX51_CCM_BASE + 0x40)
#define MXC_CCM_CWDR (MX51_CCM_BASE + 0x44)
#define MXC_CCM_CDHIPR (MX51_CCM_BASE + 0x48)
#define MXC_CCM_CDCR (MX51_CCM_BASE + 0x4C)
#define MXC_CCM_CTOR (MX51_CCM_BASE + 0x50)
#define MXC_CCM_CLPCR (MX51_CCM_BASE + 0x54)
#define MXC_CCM_CISR (MX51_CCM_BASE + 0x58)
#define MXC_CCM_CIMR (MX51_CCM_BASE + 0x5C)
#define MXC_CCM_CCOSR (MX51_CCM_BASE + 0x60)
#define MXC_CCM_CGPR (MX51_CCM_BASE + 0x64)
#define MXC_CCM_CCGR0 (MX51_CCM_BASE + 0x68)
#define MXC_CCM_CCGR1 (MX51_CCM_BASE + 0x6C)
#define MXC_CCM_CCGR2 (MX51_CCM_BASE + 0x70)
#define MXC_CCM_CCGR3 (MX51_CCM_BASE + 0x74)
#define MXC_CCM_CCGR4 (MX51_CCM_BASE + 0x78)
#define MXC_CCM_CCGR5 (MX51_CCM_BASE + 0x7C)
#define MXC_CCM_CCGR6 (MX51_CCM_BASE + 0x80)
#define MXC_CCM_CMEOR (MX51_CCM_BASE + 0x84)
/* Define the bits in register CCR */
#define MXC_CCM_CCR_COSC_EN (1 << 12)
#define MXC_CCM_CCR_FPM_MULT_MASK (1 << 11)
#define MXC_CCM_CCR_CAMP2_EN (1 << 10)
#define MXC_CCM_CCR_CAMP1_EN (1 << 9)
#define MXC_CCM_CCR_FPM_EN (1 << 8)
#define MXC_CCM_CCR_OSCNT_OFFSET (0)
#define MXC_CCM_CCR_OSCNT_MASK (0xFF)
/* Define the bits in register CCDR */
#define MXC_CCM_CCDR_HSC_HS_MASK (0x1 << 18)
#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17)
#define MXC_CCM_CCDR_EMI_HS_MASK (0x1 << 16)
/* Define the bits in register CSR */
#define MXC_CCM_CSR_COSR_READY (1 << 5)
#define MXC_CCM_CSR_LVS_VALUE (1 << 4)
#define MXC_CCM_CSR_CAMP2_READY (1 << 3)
#define MXC_CCM_CSR_CAMP1_READY (1 << 2)
#define MXC_CCM_CSR_FPM_READY (1 << 1)
#define MXC_CCM_CSR_REF_EN_B (1 << 0)
/* Define the bits in register CCSR */
#define MXC_CCM_CCSR_LP_APM_SEL (0x1 << 9)
#define MXC_CCM_CCSR_STEP_SEL_OFFSET (7)
#define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7)
#define MXC_CCM_CCSR_STEP_SEL_LP_APM 0
#define MXC_CCM_CCSR_STEP_SEL_PLL1_BYPASS 1 /* Only when JTAG connected? */
#define MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED 2
#define MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED 3
#define MXC_CCM_CCSR_PLL2_PODF_OFFSET (5)
#define MXC_CCM_CCSR_PLL2_PODF_MASK (0x3 << 5)
#define MXC_CCM_CCSR_PLL3_PODF_OFFSET (3)
#define MXC_CCM_CCSR_PLL3_PODF_MASK (0x3 << 3)
#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2) /* 0: pll1_main_clk,
1: step_clk */
#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1)
#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
/* Define the bits in register CACRR */
#define MXC_CCM_CACRR_ARM_PODF_OFFSET (0)
#define MXC_CCM_CACRR_ARM_PODF_MASK (0x7)
/* Define the bits in register CBCDR */
#define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26)
#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25)
#define MXC_CCM_CBCDR_DDR_HF_SEL_OFFSET (30)
#define MXC_CCM_CBCDR_DDR_HF_SEL (0x1 << 30)
#define MXC_CCM_CBCDR_DDR_PODF_OFFSET (27)
#define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27)
#define MXC_CCM_CBCDR_EMI_PODF_OFFSET (22)
#define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22)
#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET (19)
#define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19)
#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET (16)
#define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16)
#define MXC_CCM_CBCDR_NFC_PODF_OFFSET (13)
#define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13)
#define MXC_CCM_CBCDR_AHB_PODF_OFFSET (10)
#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
#define MXC_CCM_CBCDR_IPG_PODF_OFFSET (8)
#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET (6)
#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6)
#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET (3)
#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3)
#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET (0)
#define MXC_CCM_CBCDR_PERCLK_PODF_MASK (0x7)
/* Define the bits in register CBCMR */
#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET (14)
#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET (12)
#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12)
#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET (10)
#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10)
#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET (8)
#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8)
#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET (6)
#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6)
#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET (4)
#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4)
#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET (14)
#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 14)
#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1)
#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0)
/* Define the bits in register CSCMR1 */
#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET (30)
#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30)
#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET (28)
#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28)
#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET (26)
#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26)
#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET (24)
#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24)
#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET (22)
#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22)
#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20)
#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20)
#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19)
#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18)
#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET (16)
#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16)
#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14)
#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14)
#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12)
#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
#define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11)
#define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10)
#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET (8)
#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8)
#define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7)
#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6)
#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET (4)
#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4)
#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET (2)
#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2)
#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1)
#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL (0x1)
/* Define the bits in register CSCMR2 */
#define MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(n) (26+n*3)
#define MXC_CCM_CSCMR2_DI_CLK_SEL_MASK(n) (0x7 << (26+n*3))
#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET (24)
#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK (0x3 << 24)
#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET (22)
#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK (0x3 << 22)
#define MXC_CCM_CSCMR2_ESC_CLK_SEL_OFFSET (20)
#define MXC_CCM_CSCMR2_ESC_CLK_SEL_MASK (0x3 << 20)
#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_OFFSET (18)
#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_MASK (0x3 << 18)
#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_OFFSET (16)
#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_MASK (0x3 << 16)
#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_OFFSET (14)
#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_MASK (0x3 << 14)
#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET (12)
#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_MASK (0x3 << 12)
#define MXC_CCM_CSCMR2_SIM_CLK_SEL_OFFSET (10)
#define MXC_CCM_CSCMR2_SIM_CLK_SEL_MASK (0x3 << 10)
#define MXC_CCM_CSCMR2_SLIMBUS_COM (0x1 << 9)
#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET (6)
#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_MASK (0x7 << 6)
#define MXC_CCM_CSCMR2_SPDIF1_COM (1 << 5)
#define MXC_CCM_CSCMR2_SPDIF0_COM (1 << 4)
#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET (2)
#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK (0x3 << 2)
#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET (0)
#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK (0x3)
/* Define the bits in register CSCDR1 */
#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET (22)
#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22)
#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET (19)
#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19)
#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16)
#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16)
#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14)
#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14)
#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET (11)
#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11)
#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET (8)
#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET (6)
#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET (3)
#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3)
#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET (0)
#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x7)
/* Define the bits in register CS1CDR and CS2CDR */
#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET (22)
#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK (0x7 << 22)
#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET (16)
#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK (0x3F << 16)
#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET (6)
#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6)
#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET (0)
#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F)
#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET (22)
#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK (0x7 << 22)
#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET (16)
#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK (0x3F << 16)
#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET (6)
#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6)
#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET (0)
#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F)
/* Define the bits in register CDCDR */
#define MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET (28)
#define MXC_CCM_CDCDR_TVE_CLK_PRED_MASK (0x7 << 28)
#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET (25)
#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25)
#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET (19)
#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x3F << 19)
#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET (16)
#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 16)
#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET (9)
#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x3F << 9)
#define MXC_CCM_CDCDR_DI_CLK_PRED_OFFSET (6)
#define MXC_CCM_CDCDR_DI_CLK_PRED_MASK (0x7 << 6)
#define MXC_CCM_CDCDR_USB_PHY_PRED_OFFSET (3)
#define MXC_CCM_CDCDR_USB_PHY_PRED_MASK (0x7 << 3)
#define MXC_CCM_CDCDR_USB_PHY_PODF_OFFSET (0)
#define MXC_CCM_CDCDR_USB_PHY_PODF_MASK (0x7)
/* Define the bits in register CHSCCDR */
#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_OFFSET (12)
#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_MASK (0x7 << 12)
#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_OFFSET (6)
#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_MASK (0x3F << 6)
#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_OFFSET (3)
#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_MASK (0x7 << 3)
#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_OFFSET (0)
#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_MASK (0x7)
/* Define the bits in register CSCDR2 */
#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET (25)
#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25)
#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET (19)
#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19)
#define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET (16)
#define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16)
#define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET (9)
#define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9)
#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET (6)
#define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK (0x7 << 6)
#define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET (0)
#define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK (0x3F)
/* Define the bits in register CSCDR3 */
#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET (16)
#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_MASK (0x7 << 16)
#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET (9)
#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_MASK (0x3F << 9)
#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET (6)
#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_MASK (0x7 << 6)
#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_OFFSET (0)
#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_MASK (0x3F)
/* Define the bits in register CSCDR4 */
#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET (16)
#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK (0x7 << 16)
#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET (9)
#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK (0x3F << 9)
#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET (6)
#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK (0x7 << 6)
#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET (0)
#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK (0x3F)
/* Define the bits in register CDHIPR */
#define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
#define MXC_CCM_CDHIPR_DDR_HF_CLK_SEL_BUSY (1 << 8)
#define MXC_CCM_CDHIPR_DDR_PODF_BUSY (1 << 7)
#define MXC_CCM_CDHIPR_EMI_CLK_SEL_BUSY (1 << 6)
#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
#define MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY (1 << 4)
#define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 3)
#define MXC_CCM_CDHIPR_EMI_PODF_BUSY (1 << 2)
#define MXC_CCM_CDHIPR_AXI_B_PODF_BUSY (1 << 1)
#define MXC_CCM_CDHIPR_AXI_A_PODF_BUSY (1 << 0)
/* Define the bits in register CDCR */
#define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER (0x1 << 2)
#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET (0)
#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK (0x3)
/* Define the bits in register CLPCR */
#define MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS (0x1 << 23)
#define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS (0x1 << 22)
#define MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 21)
#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 20)
#define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS (0x1 << 19)
#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18)
#define MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS (0x1 << 17)
#define MXC_CCM_CLPCR_BYPASS_RNGC_LPM_HS (0x1 << 16)
#define MXC_CCM_CLPCR_COSC_PWRDOWN (0x1 << 11)
#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET (9)
#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9)
#define MXC_CCM_CLPCR_VSTBY (0x1 << 8)
#define MXC_CCM_CLPCR_DIS_REF_OSC (0x1 << 7)
#define MXC_CCM_CLPCR_SBYOS (0x1 << 6)
#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)
#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET (3)
#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3)
#define MXC_CCM_CLPCR_LPM_OFFSET (0)
#define MXC_CCM_CLPCR_LPM_MASK (0x3)
/* Define the bits in register CISR */
#define MXC_CCM_CISR_ARM_PODF_LOADED (0x1 << 25)
#define MXC_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21)
#define MXC_CCM_CISR_AHB_PODF_LOADED (0x1 << 20)
#define MXC_CCM_CISR_EMI_PODF_LOADED (0x1 << 19)
#define MXC_CCM_CISR_AXI_B_PODF_LOADED (0x1 << 18)
#define MXC_CCM_CISR_AXI_A_PODF_LOADED (0x1 << 17)
#define MXC_CCM_CISR_DIVIDER_LOADED (0x1 << 16)
#define MXC_CCM_CISR_COSC_READY (0x1 << 6)
#define MXC_CCM_CISR_CKIH2_READY (0x1 << 5)
#define MXC_CCM_CISR_CKIH_READY (0x1 << 4)
#define MXC_CCM_CISR_FPM_READY (0x1 << 3)
#define MXC_CCM_CISR_LRF_PLL3 (0x1 << 2)
#define MXC_CCM_CISR_LRF_PLL2 (0x1 << 1)
#define MXC_CCM_CISR_LRF_PLL1 (0x1)
/* Define the bits in register CIMR */
#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (0x1 << 25)
#define MXC_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21)
#define MXC_CCM_CIMR_MASK_EMI_PODF_LOADED (0x1 << 20)
#define MXC_CCM_CIMR_MASK_AXI_C_PODF_LOADED (0x1 << 19)
#define MXC_CCM_CIMR_MASK_AXI_B_PODF_LOADED (0x1 << 18)
#define MXC_CCM_CIMR_MASK_AXI_A_PODF_LOADED (0x1 << 17)
#define MXC_CCM_CIMR_MASK_DIVIDER_LOADED (0x1 << 16)
#define MXC_CCM_CIMR_MASK_COSC_READY (0x1 << 5)
#define MXC_CCM_CIMR_MASK_CKIH_READY (0x1 << 4)
#define MXC_CCM_CIMR_MASK_FPM_READY (0x1 << 3)
#define MXC_CCM_CIMR_MASK_LRF_PLL3 (0x1 << 2)
#define MXC_CCM_CIMR_MASK_LRF_PLL2 (0x1 << 1)
#define MXC_CCM_CIMR_MASK_LRF_PLL1 (0x1)
/* Define the bits in register CCOSR */
#define MXC_CCM_CCOSR_CKO2_EN_OFFSET (0x1 << 24)
#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET (21)
#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21)
#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET (16)
#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16)
#define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7)
#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET (4)
#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4)
#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET (0)
#define MXC_CCM_CCOSR_CKOL_SEL_MASK (0xF)
/* Define the bits in registers CGPR */
#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (0x1 << 4)
#define MXC_CCM_CGPR_FPM_SEL (0x1 << 3)
#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET (0)
#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_MASK (0x7)
/* Define the bits in registers CCGRx */
#define MXC_CCM_CCGRx_CG_MASK 0x3
#define MXC_CCM_CCGRx_MOD_OFF 0x0
#define MXC_CCM_CCGRx_MOD_ON 0x3
#define MXC_CCM_CCGRx_MOD_IDLE 0x1
#define MXC_CCM_CCGRx_CG15_MASK (0x3 << 30)
#define MXC_CCM_CCGRx_CG14_MASK (0x3 << 28)
#define MXC_CCM_CCGRx_CG13_MASK (0x3 << 26)
#define MXC_CCM_CCGRx_CG12_MASK (0x3 << 24)
#define MXC_CCM_CCGRx_CG11_MASK (0x3 << 22)
#define MXC_CCM_CCGRx_CG10_MASK (0x3 << 20)
#define MXC_CCM_CCGRx_CG9_MASK (0x3 << 18)
#define MXC_CCM_CCGRx_CG8_MASK (0x3 << 16)
#define MXC_CCM_CCGRx_CG5_MASK (0x3 << 10)
#define MXC_CCM_CCGRx_CG4_MASK (0x3 << 8)
#define MXC_CCM_CCGRx_CG3_MASK (0x3 << 6)
#define MXC_CCM_CCGRx_CG2_MASK (0x3 << 4)
#define MXC_CCM_CCGRx_CG1_MASK (0x3 << 2)
#define MXC_CCM_CCGRx_CG0_MASK (0x3 << 0)
#define MXC_CCM_CCGRx_CG15_OFFSET 30
#define MXC_CCM_CCGRx_CG14_OFFSET 28
#define MXC_CCM_CCGRx_CG13_OFFSET 26
#define MXC_CCM_CCGRx_CG12_OFFSET 24
#define MXC_CCM_CCGRx_CG11_OFFSET 22
#define MXC_CCM_CCGRx_CG10_OFFSET 20
#define MXC_CCM_CCGRx_CG9_OFFSET 18
#define MXC_CCM_CCGRx_CG8_OFFSET 16
#define MXC_CCM_CCGRx_CG7_OFFSET 14
#define MXC_CCM_CCGRx_CG6_OFFSET 12
#define MXC_CCM_CCGRx_CG5_OFFSET 10
#define MXC_CCM_CCGRx_CG4_OFFSET 8
#define MXC_CCM_CCGRx_CG3_OFFSET 6
#define MXC_CCM_CCGRx_CG2_OFFSET 4
#define MXC_CCM_CCGRx_CG1_OFFSET 2
#define MXC_CCM_CCGRx_CG0_OFFSET 0
#define MXC_DPTC_LP_BASE (MX51_GPC_BASE + 0x80)
#define MXC_DPTC_GP_BASE (MX51_GPC_BASE + 0x100)
#define MXC_DVFS_CORE_BASE (MX51_GPC_BASE + 0x180)
#define MXC_DPTC_PER_BASE (MX51_GPC_BASE + 0x1C0)
#define MXC_PGC_IPU_BASE (MX51_GPC_BASE + 0x220)
#define MXC_PGC_VPU_BASE (MX51_GPC_BASE + 0x240)
#define MXC_PGC_GPU_BASE (MX51_GPC_BASE + 0x260)
#define MXC_SRPG_NEON_BASE (MX51_GPC_BASE + 0x280)
#define MXC_SRPG_ARM_BASE (MX51_GPC_BASE + 0x2A0)
#define MXC_SRPG_EMPGC0_BASE (MX51_GPC_BASE + 0x2C0)
#define MXC_SRPG_EMPGC1_BASE (MX51_GPC_BASE + 0x2D0)
#define MXC_SRPG_MEGAMIX_BASE (MX51_GPC_BASE + 0x2E0)
#define MXC_SRPG_EMI_BASE (MX51_GPC_BASE + 0x300)
/* CORTEXA8 platform */
#define MXC_CORTEXA8_PLAT_PVID (MX51_CORTEXA8_BASE + 0x0)
#define MXC_CORTEXA8_PLAT_GPC (MX51_CORTEXA8_BASE + 0x4)
#define MXC_CORTEXA8_PLAT_PIC (MX51_CORTEXA8_BASE + 0x8)
#define MXC_CORTEXA8_PLAT_LPC (MX51_CORTEXA8_BASE + 0xC)
#define MXC_CORTEXA8_PLAT_NEON_LPC (MX51_CORTEXA8_BASE + 0x10)
#define MXC_CORTEXA8_PLAT_ICGC (MX51_CORTEXA8_BASE + 0x14)
#define MXC_CORTEXA8_PLAT_AMC (MX51_CORTEXA8_BASE + 0x18)
#define MXC_CORTEXA8_PLAT_NMC (MX51_CORTEXA8_BASE + 0x20)
#define MXC_CORTEXA8_PLAT_NMS (MX51_CORTEXA8_BASE + 0x24)
/* DVFS CORE */
#define MXC_DVFSTHRS (MXC_DVFS_CORE_BASE + 0x00)
#define MXC_DVFSCOUN (MXC_DVFS_CORE_BASE + 0x04)
#define MXC_DVFSSIG1 (MXC_DVFS_CORE_BASE + 0x08)
#define MXC_DVFSSIG0 (MXC_DVFS_CORE_BASE + 0x0C)
#define MXC_DVFSGPC0 (MXC_DVFS_CORE_BASE + 0x10)
#define MXC_DVFSGPC1 (MXC_DVFS_CORE_BASE + 0x14)
#define MXC_DVFSGPBT (MXC_DVFS_CORE_BASE + 0x18)
#define MXC_DVFSEMAC (MXC_DVFS_CORE_BASE + 0x1C)
#define MXC_DVFSCNTR (MXC_DVFS_CORE_BASE + 0x20)
#define MXC_DVFSLTR0_0 (MXC_DVFS_CORE_BASE + 0x24)
#define MXC_DVFSLTR0_1 (MXC_DVFS_CORE_BASE + 0x28)
#define MXC_DVFSLTR1_0 (MXC_DVFS_CORE_BASE + 0x2C)
#define MXC_DVFSLTR1_1 (MXC_DVFS_CORE_BASE + 0x30)
#define MXC_DVFSPT0 (MXC_DVFS_CORE_BASE + 0x34)
#define MXC_DVFSPT1 (MXC_DVFS_CORE_BASE + 0x38)
#define MXC_DVFSPT2 (MXC_DVFS_CORE_BASE + 0x3C)
#define MXC_DVFSPT3 (MXC_DVFS_CORE_BASE + 0x40)
/* GPC */
#define MXC_GPC_CNTR (MX51_GPC_BASE + 0x0)
#define MXC_GPC_PGR (MX51_GPC_BASE + 0x4)
#define MXC_GPC_VCR (MX51_GPC_BASE + 0x8)
#define MXC_GPC_ALL_PU (MX51_GPC_BASE + 0xC)
#define MXC_GPC_NEON (MX51_GPC_BASE + 0x10)
#define MXC_GPC_PGR_ARMPG_OFFSET 8
#define MXC_GPC_PGR_ARMPG_MASK (3 << 8)
/* PGC */
#define MXC_PGC_IPU_PGCR (MXC_PGC_IPU_BASE + 0x0)
#define MXC_PGC_IPU_PGSR (MXC_PGC_IPU_BASE + 0xC)
#define MXC_PGC_VPU_PGCR (MXC_PGC_VPU_BASE + 0x0)
#define MXC_PGC_VPU_PGSR (MXC_PGC_VPU_BASE + 0xC)
#define MXC_PGC_GPU_PGCR (MXC_PGC_GPU_BASE + 0x0)
#define MXC_PGC_GPU_PGSR (MXC_PGC_GPU_BASE + 0xC)
#define MXC_PGCR_PCR 1
#define MXC_SRPGCR_PCR 1
#define MXC_EMPGCR_PCR 1
#define MXC_PGSR_PSR 1
#define MXC_CORTEXA8_PLAT_LPC_DSM (1 << 0)
#define MXC_CORTEXA8_PLAT_LPC_DBG_DSM (1 << 1)
/* SRPG */
#define MXC_SRPG_NEON_SRPGCR (MXC_SRPG_NEON_BASE + 0x0)
#define MXC_SRPG_NEON_PUPSCR (MXC_SRPG_NEON_BASE + 0x4)
#define MXC_SRPG_NEON_PDNSCR (MXC_SRPG_NEON_BASE + 0x8)
#define MXC_SRPG_ARM_SRPGCR (MXC_SRPG_ARM_BASE + 0x0)
#define MXC_SRPG_ARM_PUPSCR (MXC_SRPG_ARM_BASE + 0x4)
#define MXC_SRPG_ARM_PDNSCR (MXC_SRPG_ARM_BASE + 0x8)
#define MXC_SRPG_EMPGC0_SRPGCR (MXC_SRPG_EMPGC0_BASE + 0x0)
#define MXC_SRPG_EMPGC0_PUPSCR (MXC_SRPG_EMPGC0_BASE + 0x4)
#define MXC_SRPG_EMPGC0_PDNSCR (MXC_SRPG_EMPGC0_BASE + 0x8)
#define MXC_SRPG_EMPGC1_SRPGCR (MXC_SRPG_EMPGC1_BASE + 0x0)
#define MXC_SRPG_EMPGC1_PUPSCR (MXC_SRPG_EMPGC1_BASE + 0x4)
#define MXC_SRPG_EMPGC1_PDNSCR (MXC_SRPG_EMPGC1_BASE + 0x8)
#define MXC_SRPG_MEGAMIX_SRPGCR (MXC_SRPG_MEGAMIX_BASE + 0x0)
#define MXC_SRPG_MEGAMIX_PUPSCR (MXC_SRPG_MEGAMIX_BASE + 0x4)
#define MXC_SRPG_MEGAMIX_PDNSCR (MXC_SRPG_MEGAMIX_BASE + 0x8)
#define MXC_SRPGC_EMI_SRPGCR (MXC_SRPGC_EMI_BASE + 0x0)
#define MXC_SRPGC_EMI_PUPSCR (MXC_SRPGC_EMI_BASE + 0x4)
#define MXC_SRPGC_EMI_PDNSCR (MXC_SRPGC_EMI_BASE + 0x8)
#endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */
arch/arm/mach-mx5/devices.c 0 → 100644
浏览文件 @ b93a4afc
/*
* Copyright 2009 Amit Kucheria <amit.kucheria@canonical.com>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/platform_device.h>
#include <mach/hardware.h>
#include <mach/imx-uart.h>
static struct resource uart0[] = {
{
.start = MX51_UART1_BASE_ADDR,
.end = MX51_UART1_BASE_ADDR + 0xfff,
.flags = IORESOURCE_MEM,
}, {
.start = MX51_MXC_INT_UART1,
.end = MX51_MXC_INT_UART1,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_uart_device0 = {
.name = "imx-uart",
.id = 0,
.resource = uart0,
.num_resources = ARRAY_SIZE(uart0),
};
static struct resource uart1[] = {
{
.start = MX51_UART2_BASE_ADDR,
.end = MX51_UART2_BASE_ADDR + 0xfff,
.flags = IORESOURCE_MEM,
}, {
.start = MX51_MXC_INT_UART2,
.end = MX51_MXC_INT_UART2,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_uart_device1 = {
.name = "imx-uart",
.id = 1,
.resource = uart1,
.num_resources = ARRAY_SIZE(uart1),
};
static struct resource uart2[] = {
{
.start = MX51_UART3_BASE_ADDR,
.end = MX51_UART3_BASE_ADDR + 0xfff,
.flags = IORESOURCE_MEM,
}, {
.start = MX51_MXC_INT_UART3,
.end = MX51_MXC_INT_UART3,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_uart_device2 = {
.name = "imx-uart",
.id = 2,
.resource = uart2,
.num_resources = ARRAY_SIZE(uart2),
};
static struct resource mxc_fec_resources[] = {
{
.start = MX51_MXC_FEC_BASE_ADDR,
.end = MX51_MXC_FEC_BASE_ADDR + 0xfff,
.flags = IORESOURCE_MEM,
}, {
.start = MX51_MXC_INT_FEC,
.end = MX51_MXC_INT_FEC,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_fec_device = {
.name = "fec",
.id = 0,
.num_resources = ARRAY_SIZE(mxc_fec_resources),
.resource = mxc_fec_resources,
};
/* Dummy definition to allow compiling in AVIC and TZIC simultaneously */
int __init mxc_register_gpios(void)
{
return 0;
}
arch/arm/mach-mx5/devices.h 0 → 100644
浏览文件 @ b93a4afc
extern struct platform_device mxc_uart_device0;
extern struct platform_device mxc_uart_device1;
extern struct platform_device mxc_uart_device2;
extern struct platform_device mxc_fec_device;
arch/arm/mach-mx5/mm.c 0 → 100644
浏览文件 @ b93a4afc
/*
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*
* Create static mapping between physical to virtual memory.
*/
#include <linux/mm.h>
#include <linux/init.h>
#include <asm/mach/map.h>
#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/iomux-v3.h>
/*
* Define the MX51 memory map.
*/
static struct map_desc mxc_io_desc[] __initdata = {
{
.virtual = MX51_IRAM_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX51_IRAM_BASE_ADDR),
.length = MX51_IRAM_SIZE,
.type = MT_DEVICE
}, {
.virtual = MX51_DEBUG_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX51_DEBUG_BASE_ADDR),
.length = MX51_DEBUG_SIZE,
.type = MT_DEVICE
}, {
.virtual = MX51_TZIC_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX51_TZIC_BASE_ADDR),
.length = MX51_TZIC_SIZE,
.type = MT_DEVICE
}, {
.virtual = MX51_AIPS1_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX51_AIPS1_BASE_ADDR),
.length = MX51_AIPS1_SIZE,
.type = MT_DEVICE
}, {
.virtual = MX51_SPBA0_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX51_SPBA0_BASE_ADDR),
.length = MX51_SPBA0_SIZE,
.type = MT_DEVICE
}, {
.virtual = MX51_AIPS2_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX51_AIPS2_BASE_ADDR),
.length = MX51_AIPS2_SIZE,
.type = MT_DEVICE
}, {
.virtual = MX51_NFC_AXI_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX51_NFC_AXI_BASE_ADDR),
.length = MX51_NFC_AXI_SIZE,
.type = MT_DEVICE
},
};
/*
* This function initializes the memory map. It is called during the
* system startup to create static physical to virtual memory mappings
* for the IO modules.
*/
void __init mx51_map_io(void)
{
u32 tzic_addr;
if (mx51_revision() < MX51_CHIP_REV_2_0)
tzic_addr = 0x8FFFC000;
else
tzic_addr = 0xE0003000;
mxc_io_desc[2].pfn = __phys_to_pfn(tzic_addr);
mxc_set_cpu_type(MXC_CPU_MX51);
mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG_BASE_ADDR));
iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
}
void __init mx51_init_irq(void)
{
tzic_init_irq(MX51_IO_ADDRESS(MX51_TZIC_BASE_ADDR));
}
arch/arm/mach-mxc91231/magx-zn5.c
浏览文件 @ b93a4afc
...@@ -55,7 +55,7 @@ struct sys_timer zn5_timer = { ...@@ -55,7 +55,7 @@ struct sys_timer zn5_timer = {
MACHINE_START(MAGX_ZN5, "Motorola Zn5") MACHINE_START(MAGX_ZN5, "Motorola Zn5")
.phys_io = MXC91231_AIPS1_BASE_ADDR, .phys_io = MXC91231_AIPS1_BASE_ADDR,
.io_pg_offst = ((MXC91231_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, .io_pg_offst = ((MXC91231_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100, .boot_params = MXC91231_PHYS_OFFSET + 0x100,
.map_io = mxc91231_map_io, .map_io = mxc91231_map_io,
.init_irq = mxc91231_init_irq, .init_irq = mxc91231_init_irq,
.timer = &zn5_timer, .timer = &zn5_timer,
......
arch/arm/plat-mxc/Kconfig
浏览文件 @ b93a4afc
...@@ -9,38 +9,43 @@ choice ...@@ -9,38 +9,43 @@ choice
config ARCH_MX1 config ARCH_MX1
bool "MX1-based" bool "MX1-based"
select CPU_ARM920T select CPU_ARM920T
select COMMON_CLKDEV select IMX_HAVE_IOMUX_V1
help help
This enables support for systems based on the Freescale i.MX1 family This enables support for systems based on the Freescale i.MX1 family
config ARCH_MX2 config ARCH_MX2
bool "MX2-based" bool "MX2-based"
select CPU_ARM926T select CPU_ARM926T
select COMMON_CLKDEV select IMX_HAVE_IOMUX_V1
help help
This enables support for systems based on the Freescale i.MX2 family This enables support for systems based on the Freescale i.MX2 family
config ARCH_MX25 config ARCH_MX25
bool "MX25-based" bool "MX25-based"
select CPU_ARM926T select CPU_ARM926T
select COMMON_CLKDEV select ARCH_MXC_IOMUX_V3
select HAVE_FB_IMX
help help
This enables support for systems based on the Freescale i.MX25 family This enables support for systems based on the Freescale i.MX25 family
config ARCH_MX3 config ARCH_MX3
bool "MX3-based" bool "MX3-based"
select CPU_V6 select CPU_V6
select COMMON_CLKDEV
help help
This enables support for systems based on the Freescale i.MX3 family This enables support for systems based on the Freescale i.MX3 family
config ARCH_MXC91231 config ARCH_MXC91231
bool "MXC91231-based" bool "MXC91231-based"
select CPU_V6 select CPU_V6
select COMMON_CLKDEV
help help
This enables support for systems based on the Freescale MXC91231 family This enables support for systems based on the Freescale MXC91231 family
config ARCH_MX5
bool "MX5-based"
select CPU_V7
help
This enables support for systems based on the Freescale i.MX51 family
endchoice endchoice
source "arch/arm/mach-mx1/Kconfig" source "arch/arm/mach-mx1/Kconfig"
...@@ -48,12 +53,12 @@ source "arch/arm/mach-mx2/Kconfig" ...@@ -48,12 +53,12 @@ source "arch/arm/mach-mx2/Kconfig"
source "arch/arm/mach-mx3/Kconfig" source "arch/arm/mach-mx3/Kconfig"
source "arch/arm/mach-mx25/Kconfig" source "arch/arm/mach-mx25/Kconfig"
source "arch/arm/mach-mxc91231/Kconfig" source "arch/arm/mach-mxc91231/Kconfig"
source "arch/arm/mach-mx5/Kconfig"
endmenu endmenu
config MXC_IRQ_PRIOR config MXC_IRQ_PRIOR
bool "Use IRQ priority" bool "Use IRQ priority"
depends on ARCH_MXC
help help
Select this if you want to use prioritized IRQ handling. Select this if you want to use prioritized IRQ handling.
This feature prevents higher priority ISR to be interrupted This feature prevents higher priority ISR to be interrupted
...@@ -62,9 +67,16 @@ config MXC_IRQ_PRIOR ...@@ -62,9 +67,16 @@ config MXC_IRQ_PRIOR
requirements for timing. requirements for timing.
Say N here, unless you have a specialized requirement. Say N here, unless you have a specialized requirement.
config MXC_TZIC
bool "Enable TrustZone Interrupt Controller"
depends on ARCH_MX51
help
This will be automatically selected for all processors
containing this interrupt controller.
Say N here only if you are really sure.
config MXC_PWM config MXC_PWM
tristate "Enable PWM driver" tristate "Enable PWM driver"
depends on ARCH_MXC
select HAVE_PWM select HAVE_PWM
help help
Enable support for the i.MX PWM controller(s). Enable support for the i.MX PWM controller(s).
...@@ -74,7 +86,9 @@ config MXC_ULPI ...@@ -74,7 +86,9 @@ config MXC_ULPI
config ARCH_HAS_RNGA config ARCH_HAS_RNGA
bool bool
depends on ARCH_MXC
config IMX_HAVE_IOMUX_V1
bool
config ARCH_MXC_IOMUX_V3 config ARCH_MXC_IOMUX_V3
bool bool
......
arch/arm/plat-mxc/Makefile
浏览文件 @ b93a4afc
...@@ -5,8 +5,12 @@ ...@@ -5,8 +5,12 @@
# Common support # Common support
obj-y := irq.o clock.o gpio.o time.o devices.o cpu.o system.o obj-y := irq.o clock.o gpio.o time.o devices.o cpu.o system.o
obj-$(CONFIG_ARCH_MX1) += iomux-mx1-mx2.o dma-mx1-mx2.o # MX51 uses the TZIC interrupt controller, older platforms use AVIC (irq.o)
obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o dma-mx1-mx2.o obj-$(CONFIG_MXC_TZIC) += tzic.o
obj-$(CONFIG_ARCH_MX1) += dma-mx1-mx2.o
obj-$(CONFIG_ARCH_MX2) += dma-mx1-mx2.o
obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o
obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
obj-$(CONFIG_MXC_PWM) += pwm.o obj-$(CONFIG_MXC_PWM) += pwm.o
obj-$(CONFIG_USB_EHCI_MXC) += ehci.o obj-$(CONFIG_USB_EHCI_MXC) += ehci.o
......
arch/arm/plat-mxc/audmux-v1.c
浏览文件 @ b93a4afc
...@@ -50,8 +50,18 @@ EXPORT_SYMBOL_GPL(mxc_audmux_v1_configure_port); ...@@ -50,8 +50,18 @@ EXPORT_SYMBOL_GPL(mxc_audmux_v1_configure_port);
static int mxc_audmux_v1_init(void) static int mxc_audmux_v1_init(void)
{ {
if (cpu_is_mx27() || cpu_is_mx21()) #ifdef CONFIG_MACH_MX21
audmux_base = IO_ADDRESS(AUDMUX_BASE_ADDR); if (cpu_is_mx21())
audmux_base = MX21_IO_ADDRESS(MX21_AUDMUX_BASE_ADDR);
else
#endif
#ifdef CONFIG_MACH_MX27
if (cpu_is_mx27())
audmux_base = MX27_IO_ADDRESS(MX27_AUDMUX_BASE_ADDR);
else
#endif
(void)0;
return 0; return 0;
} }
......
arch/arm/plat-mxc/audmux-v2.c
浏览文件 @ b93a4afc
...@@ -190,7 +190,10 @@ static int mxc_audmux_v2_init(void) ...@@ -190,7 +190,10 @@ static int mxc_audmux_v2_init(void)
{ {
int ret; int ret;
if (cpu_is_mx35()) { if (cpu_is_mx31())
audmux_base = MX31_IO_ADDRESS(MX31_AUDMUX_BASE_ADDR);
else if (cpu_is_mx35()) {
audmux_clk = clk_get(NULL, "audmux"); audmux_clk = clk_get(NULL, "audmux");
if (IS_ERR(audmux_clk)) { if (IS_ERR(audmux_clk)) {
ret = PTR_ERR(audmux_clk); ret = PTR_ERR(audmux_clk);
...@@ -198,11 +201,9 @@ static int mxc_audmux_v2_init(void) ...@@ -198,11 +201,9 @@ static int mxc_audmux_v2_init(void)
ret); ret);
return ret; return ret;
} }
audmux_base = MX35_IO_ADDRESS(MX35_AUDMUX_BASE_ADDR);
} }
if (cpu_is_mx31() || cpu_is_mx35())
audmux_base = IO_ADDRESS(AUDMUX_BASE_ADDR);
audmux_debugfs_init(); audmux_debugfs_init();
return 0; return 0;
......
arch/arm/plat-mxc/clock.c
浏览文件 @ b93a4afc
...@@ -56,6 +56,7 @@ static void __clk_disable(struct clk *clk) ...@@ -56,6 +56,7 @@ static void __clk_disable(struct clk *clk)
__clk_disable(clk->parent); __clk_disable(clk->parent);
__clk_disable(clk->secondary); __clk_disable(clk->secondary);
WARN_ON(!clk->usecount);
if (!(--clk->usecount) && clk->disable) if (!(--clk->usecount) && clk->disable)
clk->disable(clk); clk->disable(clk);
} }
......
arch/arm/plat-mxc/dma-mx1-mx2.c
浏览文件 @ b93a4afc
...@@ -128,6 +128,18 @@ struct imx_dma_channel { ...@@ -128,6 +128,18 @@ struct imx_dma_channel {
int hw_chaining; int hw_chaining;
}; };
static void __iomem *imx_dmav1_baseaddr;
static void imx_dmav1_writel(unsigned val, unsigned offset)
{
__raw_writel(val, imx_dmav1_baseaddr + offset);
}
static unsigned imx_dmav1_readl(unsigned offset)
{
return __raw_readl(imx_dmav1_baseaddr + offset);
}
static struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS]; static struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS];
static struct clk *dma_clk; static struct clk *dma_clk;
...@@ -140,7 +152,6 @@ static int imx_dma_hw_chain(struct imx_dma_channel *imxdma) ...@@ -140,7 +152,6 @@ static int imx_dma_hw_chain(struct imx_dma_channel *imxdma)
return 0; return 0;
} }
/* /*
* imx_dma_sg_next - prepare next chunk for scatter-gather DMA emulation * imx_dma_sg_next - prepare next chunk for scatter-gather DMA emulation
*/ */
...@@ -160,17 +171,17 @@ static inline int imx_dma_sg_next(int channel, struct scatterlist *sg) ...@@ -160,17 +171,17 @@ static inline int imx_dma_sg_next(int channel, struct scatterlist *sg)
imxdma->resbytes -= now; imxdma->resbytes -= now;
if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ) if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ)
__raw_writel(sg->dma_address, DMA_BASE + DMA_DAR(channel)); imx_dmav1_writel(sg->dma_address, DMA_DAR(channel));
else else
__raw_writel(sg->dma_address, DMA_BASE + DMA_SAR(channel)); imx_dmav1_writel(sg->dma_address, DMA_SAR(channel));
__raw_writel(now, DMA_BASE + DMA_CNTR(channel)); imx_dmav1_writel(now, DMA_CNTR(channel));
pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, " pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, "
"size 0x%08x\n", channel, "size 0x%08x\n", channel,
__raw_readl(DMA_BASE + DMA_DAR(channel)), imx_dmav1_readl(DMA_DAR(channel)),
__raw_readl(DMA_BASE + DMA_SAR(channel)), imx_dmav1_readl(DMA_SAR(channel)),
__raw_readl(DMA_BASE + DMA_CNTR(channel))); imx_dmav1_readl(DMA_CNTR(channel)));
return now; return now;
} }
...@@ -218,27 +229,26 @@ imx_dma_setup_single(int channel, dma_addr_t dma_address, ...@@ -218,27 +229,26 @@ imx_dma_setup_single(int channel, dma_addr_t dma_address,
channel, __func__, (unsigned int)dma_address, channel, __func__, (unsigned int)dma_address,
dma_length, dev_addr); dma_length, dev_addr);
__raw_writel(dev_addr, DMA_BASE + DMA_SAR(channel)); imx_dmav1_writel(dev_addr, DMA_SAR(channel));
__raw_writel(dma_address, DMA_BASE + DMA_DAR(channel)); imx_dmav1_writel(dma_address, DMA_DAR(channel));
__raw_writel(imxdma->ccr_from_device, imx_dmav1_writel(imxdma->ccr_from_device, DMA_CCR(channel));
DMA_BASE + DMA_CCR(channel));
} else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) { } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d " pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
"dev_addr=0x%08x for write\n", "dev_addr=0x%08x for write\n",
channel, __func__, (unsigned int)dma_address, channel, __func__, (unsigned int)dma_address,
dma_length, dev_addr); dma_length, dev_addr);
__raw_writel(dma_address, DMA_BASE + DMA_SAR(channel)); imx_dmav1_writel(dma_address, DMA_SAR(channel));
__raw_writel(dev_addr, DMA_BASE + DMA_DAR(channel)); imx_dmav1_writel(dev_addr, DMA_DAR(channel));
__raw_writel(imxdma->ccr_to_device, imx_dmav1_writel(imxdma->ccr_to_device,
DMA_BASE + DMA_CCR(channel)); DMA_CCR(channel));
} else { } else {
printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n", printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n",
channel); channel);
return -EINVAL; return -EINVAL;
} }
__raw_writel(dma_length, DMA_BASE + DMA_CNTR(channel)); imx_dmav1_writel(dma_length, DMA_CNTR(channel));
return 0; return 0;
} }
...@@ -316,17 +326,15 @@ imx_dma_setup_sg(int channel, ...@@ -316,17 +326,15 @@ imx_dma_setup_sg(int channel,
"dev_addr=0x%08x for read\n", "dev_addr=0x%08x for read\n",
channel, __func__, sg, sgcount, dma_length, dev_addr); channel, __func__, sg, sgcount, dma_length, dev_addr);
__raw_writel(dev_addr, DMA_BASE + DMA_SAR(channel)); imx_dmav1_writel(dev_addr, DMA_SAR(channel));
__raw_writel(imxdma->ccr_from_device, imx_dmav1_writel(imxdma->ccr_from_device, DMA_CCR(channel));
DMA_BASE + DMA_CCR(channel));
} else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) { } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d " pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
"dev_addr=0x%08x for write\n", "dev_addr=0x%08x for write\n",
channel, __func__, sg, sgcount, dma_length, dev_addr); channel, __func__, sg, sgcount, dma_length, dev_addr);
__raw_writel(dev_addr, DMA_BASE + DMA_DAR(channel)); imx_dmav1_writel(dev_addr, DMA_DAR(channel));
__raw_writel(imxdma->ccr_to_device, imx_dmav1_writel(imxdma->ccr_to_device, DMA_CCR(channel));
DMA_BASE + DMA_CCR(channel));
} else { } else {
printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n", printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n",
channel); channel);
...@@ -360,7 +368,7 @@ imx_dma_config_channel(int channel, unsigned int config_port, ...@@ -360,7 +368,7 @@ imx_dma_config_channel(int channel, unsigned int config_port,
imxdma->ccr_from_device = config_port | (config_mem << 2) | dreq; imxdma->ccr_from_device = config_port | (config_mem << 2) | dreq;
imxdma->ccr_to_device = config_mem | (config_port << 2) | dreq; imxdma->ccr_to_device = config_mem | (config_port << 2) | dreq;
__raw_writel(dmareq, DMA_BASE + DMA_RSSR(channel)); imx_dmav1_writel(dmareq, DMA_RSSR(channel));
return 0; return 0;
} }
...@@ -368,7 +376,7 @@ EXPORT_SYMBOL(imx_dma_config_channel); ...@@ -368,7 +376,7 @@ EXPORT_SYMBOL(imx_dma_config_channel);
void imx_dma_config_burstlen(int channel, unsigned int burstlen) void imx_dma_config_burstlen(int channel, unsigned int burstlen)
{ {
__raw_writel(burstlen, DMA_BASE + DMA_BLR(channel)); imx_dmav1_writel(burstlen, DMA_BLR(channel));
} }
EXPORT_SYMBOL(imx_dma_config_burstlen); EXPORT_SYMBOL(imx_dma_config_burstlen);
...@@ -398,7 +406,7 @@ imx_dma_setup_handlers(int channel, ...@@ -398,7 +406,7 @@ imx_dma_setup_handlers(int channel,
} }
local_irq_save(flags); local_irq_save(flags);
__raw_writel(1 << channel, DMA_BASE + DMA_DISR); imx_dmav1_writel(1 << channel, DMA_DISR);
imxdma->irq_handler = irq_handler; imxdma->irq_handler = irq_handler;
imxdma->err_handler = err_handler; imxdma->err_handler = err_handler;
imxdma->data = data; imxdma->data = data;
...@@ -462,22 +470,21 @@ void imx_dma_enable(int channel) ...@@ -462,22 +470,21 @@ void imx_dma_enable(int channel)
local_irq_save(flags); local_irq_save(flags);
__raw_writel(1 << channel, DMA_BASE + DMA_DISR); imx_dmav1_writel(1 << channel, DMA_DISR);
__raw_writel(__raw_readl(DMA_BASE + DMA_DIMR) & ~(1 << channel), imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) & ~(1 << channel), DMA_DIMR);
DMA_BASE + DMA_DIMR); imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) | CCR_CEN |
__raw_writel(__raw_readl(DMA_BASE + DMA_CCR(channel)) | CCR_CEN | CCR_ACRPT, DMA_CCR(channel));
CCR_ACRPT,
DMA_BASE + DMA_CCR(channel));
#ifdef CONFIG_ARCH_MX2 #ifdef CONFIG_ARCH_MX2
if (imxdma->sg && imx_dma_hw_chain(imxdma)) { if ((cpu_is_mx21() || cpu_is_mx27()) &&
imxdma->sg && imx_dma_hw_chain(imxdma)) {
imxdma->sg = sg_next(imxdma->sg); imxdma->sg = sg_next(imxdma->sg);
if (imxdma->sg) { if (imxdma->sg) {
u32 tmp; u32 tmp;
imx_dma_sg_next(channel, imxdma->sg); imx_dma_sg_next(channel, imxdma->sg);
tmp = __raw_readl(DMA_BASE + DMA_CCR(channel)); tmp = imx_dmav1_readl(DMA_CCR(channel));
__raw_writel(tmp | CCR_RPT | CCR_ACRPT, imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
DMA_BASE + DMA_CCR(channel)); DMA_CCR(channel));
} }
} }
#endif #endif
...@@ -502,11 +509,10 @@ void imx_dma_disable(int channel) ...@@ -502,11 +509,10 @@ void imx_dma_disable(int channel)
del_timer(&imxdma->watchdog); del_timer(&imxdma->watchdog);
local_irq_save(flags); local_irq_save(flags);
__raw_writel(__raw_readl(DMA_BASE + DMA_DIMR) | (1 << channel), imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) | (1 << channel), DMA_DIMR);
DMA_BASE + DMA_DIMR); imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) & ~CCR_CEN,
__raw_writel(__raw_readl(DMA_BASE + DMA_CCR(channel)) & ~CCR_CEN, DMA_CCR(channel));
DMA_BASE + DMA_CCR(channel)); imx_dmav1_writel(1 << channel, DMA_DISR);
__raw_writel(1 << channel, DMA_BASE + DMA_DISR);
imxdma->in_use = 0; imxdma->in_use = 0;
local_irq_restore(flags); local_irq_restore(flags);
} }
...@@ -517,7 +523,7 @@ static void imx_dma_watchdog(unsigned long chno) ...@@ -517,7 +523,7 @@ static void imx_dma_watchdog(unsigned long chno)
{ {
struct imx_dma_channel *imxdma = &imx_dma_channels[chno]; struct imx_dma_channel *imxdma = &imx_dma_channels[chno];
__raw_writel(0, DMA_BASE + DMA_CCR(chno)); imx_dmav1_writel(0, DMA_CCR(chno));
imxdma->in_use = 0; imxdma->in_use = 0;
imxdma->sg = NULL; imxdma->sg = NULL;
...@@ -533,17 +539,17 @@ static irqreturn_t dma_err_handler(int irq, void *dev_id) ...@@ -533,17 +539,17 @@ static irqreturn_t dma_err_handler(int irq, void *dev_id)
unsigned int err_mask; unsigned int err_mask;
int errcode; int errcode;
disr = __raw_readl(DMA_BASE + DMA_DISR); disr = imx_dmav1_readl(DMA_DISR);
err_mask = __raw_readl(DMA_BASE + DMA_DBTOSR) | err_mask = imx_dmav1_readl(DMA_DBTOSR) |
__raw_readl(DMA_BASE + DMA_DRTOSR) | imx_dmav1_readl(DMA_DRTOSR) |
__raw_readl(DMA_BASE + DMA_DSESR) | imx_dmav1_readl(DMA_DSESR) |
__raw_readl(DMA_BASE + DMA_DBOSR); imx_dmav1_readl(DMA_DBOSR);
if (!err_mask) if (!err_mask)
return IRQ_HANDLED; return IRQ_HANDLED;
__raw_writel(disr & err_mask, DMA_BASE + DMA_DISR); imx_dmav1_writel(disr & err_mask, DMA_DISR);
for (i = 0; i < IMX_DMA_CHANNELS; i++) { for (i = 0; i < IMX_DMA_CHANNELS; i++) {
if (!(err_mask & (1 << i))) if (!(err_mask & (1 << i)))
...@@ -551,20 +557,20 @@ static irqreturn_t dma_err_handler(int irq, void *dev_id) ...@@ -551,20 +557,20 @@ static irqreturn_t dma_err_handler(int irq, void *dev_id)
imxdma = &imx_dma_channels[i]; imxdma = &imx_dma_channels[i];
errcode = 0; errcode = 0;
if (__raw_readl(DMA_BASE + DMA_DBTOSR) & (1 << i)) { if (imx_dmav1_readl(DMA_DBTOSR) & (1 << i)) {
__raw_writel(1 << i, DMA_BASE + DMA_DBTOSR); imx_dmav1_writel(1 << i, DMA_DBTOSR);
errcode |= IMX_DMA_ERR_BURST; errcode |= IMX_DMA_ERR_BURST;
} }
if (__raw_readl(DMA_BASE + DMA_DRTOSR) & (1 << i)) { if (imx_dmav1_readl(DMA_DRTOSR) & (1 << i)) {
__raw_writel(1 << i, DMA_BASE + DMA_DRTOSR); imx_dmav1_writel(1 << i, DMA_DRTOSR);
errcode |= IMX_DMA_ERR_REQUEST; errcode |= IMX_DMA_ERR_REQUEST;
} }
if (__raw_readl(DMA_BASE + DMA_DSESR) & (1 << i)) { if (imx_dmav1_readl(DMA_DSESR) & (1 << i)) {
__raw_writel(1 << i, DMA_BASE + DMA_DSESR); imx_dmav1_writel(1 << i, DMA_DSESR);
errcode |= IMX_DMA_ERR_TRANSFER; errcode |= IMX_DMA_ERR_TRANSFER;
} }
if (__raw_readl(DMA_BASE + DMA_DBOSR) & (1 << i)) { if (imx_dmav1_readl(DMA_DBOSR) & (1 << i)) {
__raw_writel(1 << i, DMA_BASE + DMA_DBOSR); imx_dmav1_writel(1 << i, DMA_DBOSR);
errcode |= IMX_DMA_ERR_BUFFER; errcode |= IMX_DMA_ERR_BUFFER;
} }
if (imxdma->name && imxdma->err_handler) { if (imxdma->name && imxdma->err_handler) {
...@@ -607,7 +613,7 @@ static void dma_irq_handle_channel(int chno) ...@@ -607,7 +613,7 @@ static void dma_irq_handle_channel(int chno)
if (imxdma->sg) { if (imxdma->sg) {
imx_dma_sg_next(chno, imxdma->sg); imx_dma_sg_next(chno, imxdma->sg);
tmp = __raw_readl(DMA_BASE + DMA_CCR(chno)); tmp = imx_dmav1_readl(DMA_CCR(chno));
if (imx_dma_hw_chain(imxdma)) { if (imx_dma_hw_chain(imxdma)) {
/* FIXME: The timeout should probably be /* FIXME: The timeout should probably be
...@@ -617,15 +623,13 @@ static void dma_irq_handle_channel(int chno) ...@@ -617,15 +623,13 @@ static void dma_irq_handle_channel(int chno)
jiffies + msecs_to_jiffies(500)); jiffies + msecs_to_jiffies(500));
tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT; tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
__raw_writel(tmp, DMA_BASE + imx_dmav1_writel(tmp, DMA_CCR(chno));
DMA_CCR(chno));
} else { } else {
__raw_writel(tmp & ~CCR_CEN, DMA_BASE + imx_dmav1_writel(tmp & ~CCR_CEN, DMA_CCR(chno));
DMA_CCR(chno));
tmp |= CCR_CEN; tmp |= CCR_CEN;
} }
__raw_writel(tmp, DMA_BASE + DMA_CCR(chno)); imx_dmav1_writel(tmp, DMA_CCR(chno));
if (imxdma->prog_handler) if (imxdma->prog_handler)
imxdma->prog_handler(chno, imxdma->data, imxdma->prog_handler(chno, imxdma->data,
...@@ -640,7 +644,7 @@ static void dma_irq_handle_channel(int chno) ...@@ -640,7 +644,7 @@ static void dma_irq_handle_channel(int chno)
} }
} }
__raw_writel(0, DMA_BASE + DMA_CCR(chno)); imx_dmav1_writel(0, DMA_CCR(chno));
imxdma->in_use = 0; imxdma->in_use = 0;
if (imxdma->irq_handler) if (imxdma->irq_handler)
imxdma->irq_handler(chno, imxdma->data); imxdma->irq_handler(chno, imxdma->data);
...@@ -651,15 +655,16 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id) ...@@ -651,15 +655,16 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id)
int i, disr; int i, disr;
#ifdef CONFIG_ARCH_MX2 #ifdef CONFIG_ARCH_MX2
if (cpu_is_mx21() || cpu_is_mx27())
dma_err_handler(irq, dev_id); dma_err_handler(irq, dev_id);
#endif #endif
disr = __raw_readl(DMA_BASE + DMA_DISR); disr = imx_dmav1_readl(DMA_DISR);
pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n", pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
disr); disr);
__raw_writel(disr, DMA_BASE + DMA_DISR); imx_dmav1_writel(disr, DMA_DISR);
for (i = 0; i < IMX_DMA_CHANNELS; i++) { for (i = 0; i < IMX_DMA_CHANNELS; i++) {
if (disr & (1 << i)) if (disr & (1 << i))
dma_irq_handle_channel(i); dma_irq_handle_channel(i);
...@@ -699,17 +704,19 @@ int imx_dma_request(int channel, const char *name) ...@@ -699,17 +704,19 @@ int imx_dma_request(int channel, const char *name)
local_irq_restore(flags); /* request_irq() can block */ local_irq_restore(flags); /* request_irq() can block */
#ifdef CONFIG_ARCH_MX2 #ifdef CONFIG_ARCH_MX2
ret = request_irq(MXC_INT_DMACH0 + channel, dma_irq_handler, 0, "DMA", if (cpu_is_mx21() || cpu_is_mx27()) {
NULL); ret = request_irq(MX2x_INT_DMACH0 + channel,
dma_irq_handler, 0, "DMA", NULL);
if (ret) { if (ret) {
imxdma->name = NULL; imxdma->name = NULL;
printk(KERN_CRIT "Can't register IRQ %d for DMA channel %d\n", pr_crit("Can't register IRQ %d for DMA channel %d\n",
MXC_INT_DMACH0 + channel, channel); MX2x_INT_DMACH0 + channel, channel);
return ret; return ret;
} }
init_timer(&imxdma->watchdog); init_timer(&imxdma->watchdog);
imxdma->watchdog.function = &imx_dma_watchdog; imxdma->watchdog.function = &imx_dma_watchdog;
imxdma->watchdog.data = channel; imxdma->watchdog.data = channel;
}
#endif #endif
return ret; return ret;
...@@ -738,7 +745,8 @@ void imx_dma_free(int channel) ...@@ -738,7 +745,8 @@ void imx_dma_free(int channel)
imxdma->name = NULL; imxdma->name = NULL;
#ifdef CONFIG_ARCH_MX2 #ifdef CONFIG_ARCH_MX2
free_irq(MXC_INT_DMACH0 + channel, NULL); if (cpu_is_mx21() || cpu_is_mx27())
free_irq(MX2x_INT_DMACH0 + channel, NULL);
#endif #endif
local_irq_restore(flags); local_irq_restore(flags);
...@@ -796,34 +804,53 @@ static int __init imx_dma_init(void) ...@@ -796,34 +804,53 @@ static int __init imx_dma_init(void)
int ret = 0; int ret = 0;
int i; int i;
#ifdef CONFIG_ARCH_MX1
if (cpu_is_mx1())
imx_dmav1_baseaddr = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
else
#endif
#ifdef CONFIG_MACH_MX21
if (cpu_is_mx21())
imx_dmav1_baseaddr = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
else
#endif
#ifdef CONFIG_MACH_MX27
if (cpu_is_mx27())
imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
else
#endif
BUG();
dma_clk = clk_get(NULL, "dma"); dma_clk = clk_get(NULL, "dma");
clk_enable(dma_clk); clk_enable(dma_clk);
/* reset DMA module */ /* reset DMA module */
__raw_writel(DCR_DRST, DMA_BASE + DMA_DCR); imx_dmav1_writel(DCR_DRST, DMA_DCR);
#ifdef CONFIG_ARCH_MX1 #ifdef CONFIG_ARCH_MX1
ret = request_irq(DMA_INT, dma_irq_handler, 0, "DMA", NULL); if (cpu_is_mx1()) {
ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", NULL);
if (ret) { if (ret) {
printk(KERN_CRIT "Wow! Can't register IRQ for DMA\n"); pr_crit("Wow! Can't register IRQ for DMA\n");
return ret; return ret;
} }
ret = request_irq(DMA_ERR, dma_err_handler, 0, "DMA", NULL); ret = request_irq(MX1_DMA_ERR, dma_err_handler, 0, "DMA", NULL);
if (ret) { if (ret) {
printk(KERN_CRIT "Wow! Can't register ERRIRQ for DMA\n"); pr_crit("Wow! Can't register ERRIRQ for DMA\n");
free_irq(DMA_INT, NULL); free_irq(MX1_DMA_INT, NULL);
return ret; return ret;
} }
}
#endif #endif
/* enable DMA module */ /* enable DMA module */
__raw_writel(DCR_DEN, DMA_BASE + DMA_DCR); imx_dmav1_writel(DCR_DEN, DMA_DCR);
/* clear all interrupts */ /* clear all interrupts */
__raw_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_BASE + DMA_DISR); imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
/* disable interrupts */ /* disable interrupts */
__raw_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_BASE + DMA_DIMR); imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
for (i = 0; i < IMX_DMA_CHANNELS; i++) { for (i = 0; i < IMX_DMA_CHANNELS; i++) {
imx_dma_channels[i].sg = NULL; imx_dma_channels[i].sg = NULL;
......
arch/arm/plat-mxc/ehci.c
浏览文件 @ b93a4afc
...@@ -25,25 +25,37 @@ ...@@ -25,25 +25,37 @@
#define USBCTRL_OTGBASE_OFFSET 0x600 #define USBCTRL_OTGBASE_OFFSET 0x600
#define MX31_OTG_SIC_SHIFT 29 #define MX31_OTG_SIC_SHIFT 29
#define MX31_OTG_SIC_MASK (0xf << MX31_OTG_SIC_SHIFT) #define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT)
#define MX31_OTG_PM_BIT (1 << 24) #define MX31_OTG_PM_BIT (1 << 24)
#define MX31_H2_SIC_SHIFT 21 #define MX31_H2_SIC_SHIFT 21
#define MX31_H2_SIC_MASK (0xf << MX31_H2_SIC_SHIFT) #define MX31_H2_SIC_MASK (0x3 << MX31_H2_SIC_SHIFT)
#define MX31_H2_PM_BIT (1 << 16) #define MX31_H2_PM_BIT (1 << 16)
#define MX31_H2_DT_BIT (1 << 5) #define MX31_H2_DT_BIT (1 << 5)
#define MX31_H1_SIC_SHIFT 13 #define MX31_H1_SIC_SHIFT 13
#define MX31_H1_SIC_MASK (0xf << MX31_H1_SIC_SHIFT) #define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT)
#define MX31_H1_PM_BIT (1 << 8) #define MX31_H1_PM_BIT (1 << 8)
#define MX31_H1_DT_BIT (1 << 4) #define MX31_H1_DT_BIT (1 << 4)
#define MX35_OTG_SIC_SHIFT 29
#define MX35_OTG_SIC_MASK (0x3 << MX35_OTG_SIC_SHIFT)
#define MX35_OTG_PM_BIT (1 << 24)
#define MX35_H1_SIC_SHIFT 21
#define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT)
#define MX35_H1_PM_BIT (1 << 8)
#define MX35_H1_IPPUE_UP_BIT (1 << 7)
#define MX35_H1_IPPUE_DOWN_BIT (1 << 6)
#define MX35_H1_TLL_BIT (1 << 5)
#define MX35_H1_USBTE_BIT (1 << 4)
int mxc_set_usbcontrol(int port, unsigned int flags) int mxc_set_usbcontrol(int port, unsigned int flags)
{ {
unsigned int v; unsigned int v;
#ifdef CONFIG_ARCH_MX3
if (cpu_is_mx31()) { if (cpu_is_mx31()) {
v = readl(IO_ADDRESS(MX31_OTG_BASE_ADDR + v = readl(MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR +
USBCTRL_OTGBASE_OFFSET)); USBCTRL_OTGBASE_OFFSET));
switch (port) { switch (port) {
...@@ -51,15 +63,15 @@ int mxc_set_usbcontrol(int port, unsigned int flags) ...@@ -51,15 +63,15 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT); v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
v |= (flags & MXC_EHCI_INTERFACE_MASK) v |= (flags & MXC_EHCI_INTERFACE_MASK)
<< MX31_OTG_SIC_SHIFT; << MX31_OTG_SIC_SHIFT;
if (flags & MXC_EHCI_POWER_PINS_ENABLED) if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
v |= MX31_OTG_PM_BIT; v |= MX31_OTG_PM_BIT;
break; break;
case 1: /* H1 port */ case 1: /* H1 port */
v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT); v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT);
v |= (flags & MXC_EHCI_INTERFACE_MASK) v |= (flags & MXC_EHCI_INTERFACE_MASK)
<< MX31_H1_SIC_SHIFT; << MX31_H1_SIC_SHIFT;
if (flags & MXC_EHCI_POWER_PINS_ENABLED) if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
v |= MX31_H1_PM_BIT; v |= MX31_H1_PM_BIT;
if (!(flags & MXC_EHCI_TTL_ENABLED)) if (!(flags & MXC_EHCI_TTL_ENABLED))
...@@ -67,7 +79,7 @@ int mxc_set_usbcontrol(int port, unsigned int flags) ...@@ -67,7 +79,7 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
break; break;
case 2: /* H2 port */ case 2: /* H2 port */
v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT); v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT);
v |= (flags & MXC_EHCI_INTERFACE_MASK) v |= (flags & MXC_EHCI_INTERFACE_MASK)
<< MX31_H2_SIC_SHIFT; << MX31_H2_SIC_SHIFT;
if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
...@@ -77,13 +89,103 @@ int mxc_set_usbcontrol(int port, unsigned int flags) ...@@ -77,13 +89,103 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
v |= MX31_H2_DT_BIT; v |= MX31_H2_DT_BIT;
break; break;
default:
return -EINVAL;
} }
writel(v, IO_ADDRESS(MX31_OTG_BASE_ADDR + writel(v, MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR +
USBCTRL_OTGBASE_OFFSET)); USBCTRL_OTGBASE_OFFSET));
return 0; return 0;
} }
if (cpu_is_mx35()) {
v = readl(MX35_IO_ADDRESS(MX35_OTG_BASE_ADDR +
USBCTRL_OTGBASE_OFFSET));
switch (port) {
case 0: /* OTG port */
v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT);
v |= (flags & MXC_EHCI_INTERFACE_MASK)
<< MX35_OTG_SIC_SHIFT;
if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
v |= MX35_OTG_PM_BIT;
break;
case 1: /* H1 port */
v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT |
MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
v |= (flags & MXC_EHCI_INTERFACE_MASK)
<< MX35_H1_SIC_SHIFT;
if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
v |= MX35_H1_PM_BIT;
if (!(flags & MXC_EHCI_TTL_ENABLED))
v |= MX35_H1_TLL_BIT;
if (flags & MXC_EHCI_INTERNAL_PHY)
v |= MX35_H1_USBTE_BIT;
if (flags & MXC_EHCI_IPPUE_DOWN)
v |= MX35_H1_IPPUE_DOWN_BIT;
if (flags & MXC_EHCI_IPPUE_UP)
v |= MX35_H1_IPPUE_UP_BIT;
break;
default:
return -EINVAL;
}
writel(v, MX35_IO_ADDRESS(MX35_OTG_BASE_ADDR +
USBCTRL_OTGBASE_OFFSET));
return 0;
}
#endif /* CONFIG_ARCH_MX3 */
#ifdef CONFIG_MACH_MX27
if (cpu_is_mx27()) {
/* On i.MX27 we can use the i.MX31 USBCTRL bits, they
* are identical
*/
v = readl(MX27_IO_ADDRESS(MX27_OTG_BASE_ADDR +
USBCTRL_OTGBASE_OFFSET));
switch (port) {
case 0: /* OTG port */
v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
v |= (flags & MXC_EHCI_INTERFACE_MASK)
<< MX31_OTG_SIC_SHIFT;
if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
v |= MX31_OTG_PM_BIT;
break;
case 1: /* H1 port */
v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT);
v |= (flags & MXC_EHCI_INTERFACE_MASK)
<< MX31_H1_SIC_SHIFT;
if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
v |= MX31_H1_PM_BIT;
if (!(flags & MXC_EHCI_TTL_ENABLED))
v |= MX31_H1_DT_BIT;
break;
case 2: /* H2 port */
v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT);
v |= (flags & MXC_EHCI_INTERFACE_MASK)
<< MX31_H2_SIC_SHIFT;
if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
v |= MX31_H2_PM_BIT;
if (!(flags & MXC_EHCI_TTL_ENABLED))
v |= MX31_H2_DT_BIT;
break;
default:
return -EINVAL;
}
writel(v, MX27_IO_ADDRESS(MX27_OTG_BASE_ADDR +
USBCTRL_OTGBASE_OFFSET));
return 0;
}
#endif /* CONFIG_MACH_MX27 */
printk(KERN_WARNING printk(KERN_WARNING
"%s() unable to setup USBCONTROL for this CPU\n", __func__); "%s() unable to setup USBCONTROL for this CPU\n", __func__);
return -EINVAL; return -EINVAL;
......
arch/arm/plat-mxc/gpio.c
浏览文件 @ b93a4afc
...@@ -140,16 +140,13 @@ static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio) ...@@ -140,16 +140,13 @@ static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
val = __raw_readl(reg); val = __raw_readl(reg);
edge = (val >> (bit << 1)) & 3; edge = (val >> (bit << 1)) & 3;
val &= ~(0x3 << (bit << 1)); val &= ~(0x3 << (bit << 1));
switch (edge) { if (edge == GPIO_INT_HIGH_LEV) {
case GPIO_INT_HIGH_LEV:
edge = GPIO_INT_LOW_LEV; edge = GPIO_INT_LOW_LEV;
pr_debug("mxc: switch GPIO %d to low trigger\n", gpio); pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
break; } else if (edge == GPIO_INT_LOW_LEV) {
case GPIO_INT_LOW_LEV:
edge = GPIO_INT_HIGH_LEV; edge = GPIO_INT_HIGH_LEV;
pr_debug("mxc: switch GPIO %d to high trigger\n", gpio); pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
break; } else {
default:
pr_err("mxc: invalid configuration for GPIO %d: %x\n", pr_err("mxc: invalid configuration for GPIO %d: %x\n",
gpio, edge); gpio, edge);
return; return;
...@@ -157,25 +154,20 @@ static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio) ...@@ -157,25 +154,20 @@ static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
__raw_writel(val | (edge << (bit << 1)), reg); __raw_writel(val | (edge << (bit << 1)), reg);
} }
/* handle n interrupts in one status register */ /* handle 32 interrupts in one status register */
static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat) static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
{ {
u32 gpio_irq_no; u32 gpio_irq_no_base = port->virtual_irq_start;
gpio_irq_no = port->virtual_irq_start;
for (; irq_stat != 0; irq_stat >>= 1, gpio_irq_no++) {
u32 gpio = irq_to_gpio(gpio_irq_no);
if ((irq_stat & 1) == 0) while (irq_stat != 0) {
continue; int irqoffset = fls(irq_stat) - 1;
BUG_ON(!(irq_desc[gpio_irq_no].handle_irq)); if (port->both_edges & (1 << irqoffset))
mxc_flip_edge(port, irqoffset);
if (port->both_edges & (1 << (gpio & 31))) generic_handle_irq(gpio_irq_no_base + irqoffset);
mxc_flip_edge(port, gpio);
irq_desc[gpio_irq_no].handle_irq(gpio_irq_no, irq_stat &= ~(1 << irqoffset);
&irq_desc[gpio_irq_no]);
} }
} }
......
arch/arm/plat-mxc/include/mach/board-kzmarm11.h
浏览文件 @ b93a4afc
...@@ -21,19 +21,19 @@ ...@@ -21,19 +21,19 @@
/* /*
* KZM-ARM11-01 Board Control Registers on FPGA * KZM-ARM11-01 Board Control Registers on FPGA
*/ */
#define KZM_ARM11_CTL1 (CS4_BASE_ADDR + 0x1000) #define KZM_ARM11_CTL1 (MX31_CS4_BASE_ADDR + 0x1000)
#define KZM_ARM11_CTL2 (CS4_BASE_ADDR + 0x1001) #define KZM_ARM11_CTL2 (MX31_CS4_BASE_ADDR + 0x1001)
#define KZM_ARM11_RSW1 (CS4_BASE_ADDR + 0x1002) #define KZM_ARM11_RSW1 (MX31_CS4_BASE_ADDR + 0x1002)
#define KZM_ARM11_BACK_LIGHT (CS4_BASE_ADDR + 0x1004) #define KZM_ARM11_BACK_LIGHT (MX31_CS4_BASE_ADDR + 0x1004)
#define KZM_ARM11_FPGA_REV (CS4_BASE_ADDR + 0x1008) #define KZM_ARM11_FPGA_REV (MX31_CS4_BASE_ADDR + 0x1008)
#define KZM_ARM11_7SEG_LED (CS4_BASE_ADDR + 0x1010) #define KZM_ARM11_7SEG_LED (MX31_CS4_BASE_ADDR + 0x1010)
#define KZM_ARM11_LEDS (CS4_BASE_ADDR + 0x1020) #define KZM_ARM11_LEDS (MX31_CS4_BASE_ADDR + 0x1020)
#define KZM_ARM11_DIPSW2 (CS4_BASE_ADDR + 0x1003) #define KZM_ARM11_DIPSW2 (MX31_CS4_BASE_ADDR + 0x1003)
/* /*
* External UART for touch panel on FPGA * External UART for touch panel on FPGA
*/ */
#define KZM_ARM11_16550 (CS4_BASE_ADDR + 0x1050) #define KZM_ARM11_16550 (MX31_CS4_BASE_ADDR + 0x1050)
#endif /* __ARM_ARCH_BOARD_KZM_ARM11_H */ #endif /* __ARM_ARCH_BOARD_KZM_ARM11_H */
arch/arm/plat-mxc/include/mach/board-mx31ads.h
浏览文件 @ b93a4afc
...@@ -14,7 +14,7 @@ ...@@ -14,7 +14,7 @@
#include <mach/hardware.h> #include <mach/hardware.h>
/* Base address of PBC controller */ /* Base address of PBC controller */
#define PBC_BASE_ADDRESS IO_ADDRESS(CS4_BASE_ADDR) #define PBC_BASE_ADDRESS MX31_CS4_BASE_ADDR_VIRT
/* Offsets for the PBC Controller register */ /* Offsets for the PBC Controller register */
/* PBC Board status register offset */ /* PBC Board status register offset */
......
arch/arm/plat-mxc/include/mach/board-mx31moboard.h
浏览文件 @ b93a4afc
...@@ -25,6 +25,7 @@ enum mx31moboard_boards { ...@@ -25,6 +25,7 @@ enum mx31moboard_boards {
MX31NOBOARD = 0, MX31NOBOARD = 0,
MX31DEVBOARD = 1, MX31DEVBOARD = 1,
MX31MARXBOT = 2, MX31MARXBOT = 2,
MX31SMARTBOT = 3,
}; };
/* /*
...@@ -34,6 +35,7 @@ enum mx31moboard_boards { ...@@ -34,6 +35,7 @@ enum mx31moboard_boards {
extern void mx31moboard_devboard_init(void); extern void mx31moboard_devboard_init(void);
extern void mx31moboard_marxbot_init(void); extern void mx31moboard_marxbot_init(void);
extern void mx31moboard_smartbot_init(void);
#endif #endif
......
arch/arm/plat-mxc/include/mach/clock.h
浏览文件 @ b93a4afc
...@@ -26,13 +26,6 @@ ...@@ -26,13 +26,6 @@
struct module; struct module;
struct clk { struct clk {
#ifndef CONFIG_COMMON_CLKDEV
/* As soon as i.MX1 and i.MX31 switched to clkdev, this
* block can go away */
struct list_head node;
struct module *owner;
const char *name;
#endif
int id; int id;
/* Source clock this clk depends on */ /* Source clock this clk depends on */
struct clk *parent; struct clk *parent;
......
arch/arm/plat-mxc/include/mach/common.h
浏览文件 @ b93a4afc
...@@ -20,14 +20,17 @@ extern void mx25_map_io(void); ...@@ -20,14 +20,17 @@ extern void mx25_map_io(void);
extern void mx27_map_io(void); extern void mx27_map_io(void);
extern void mx31_map_io(void); extern void mx31_map_io(void);
extern void mx35_map_io(void); extern void mx35_map_io(void);
extern void mx51_map_io(void);
extern void mxc91231_map_io(void); extern void mxc91231_map_io(void);
extern void mxc_init_irq(void __iomem *); extern void mxc_init_irq(void __iomem *);
extern void tzic_init_irq(void __iomem *);
extern void mx1_init_irq(void); extern void mx1_init_irq(void);
extern void mx21_init_irq(void); extern void mx21_init_irq(void);
extern void mx25_init_irq(void); extern void mx25_init_irq(void);
extern void mx27_init_irq(void); extern void mx27_init_irq(void);
extern void mx31_init_irq(void); extern void mx31_init_irq(void);
extern void mx35_init_irq(void); extern void mx35_init_irq(void);
extern void mx51_init_irq(void);
extern void mxc91231_init_irq(void); extern void mxc91231_init_irq(void);
extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int); extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int);
extern int mx1_clocks_init(unsigned long fref); extern int mx1_clocks_init(unsigned long fref);
...@@ -36,6 +39,8 @@ extern int mx25_clocks_init(void); ...@@ -36,6 +39,8 @@ extern int mx25_clocks_init(void);
extern int mx27_clocks_init(unsigned long fref); extern int mx27_clocks_init(unsigned long fref);
extern int mx31_clocks_init(unsigned long fref); extern int mx31_clocks_init(unsigned long fref);
extern int mx35_clocks_init(void); extern int mx35_clocks_init(void);
extern int mx51_clocks_init(unsigned long ckil, unsigned long osc,
unsigned long ckih1, unsigned long ckih2);
extern int mxc91231_clocks_init(unsigned long fref); extern int mxc91231_clocks_init(unsigned long fref);
extern int mxc_register_gpios(void); extern int mxc_register_gpios(void);
extern int mxc_register_device(struct platform_device *pdev, void *data); extern int mxc_register_device(struct platform_device *pdev, void *data);
......
arch/arm/plat-mxc/include/mach/debug-macro.S
浏览文件 @ b93a4afc
...@@ -10,6 +10,7 @@ ...@@ -10,6 +10,7 @@
* published by the Free Software Foundation. * published by the Free Software Foundation.
* *
*/ */
#define IMX_NEEDS_DEPRECATED_SYMBOLS
#ifdef CONFIG_ARCH_MX1 #ifdef CONFIG_ARCH_MX1
#include <mach/mx1.h> #include <mach/mx1.h>
...@@ -44,13 +45,22 @@ ...@@ -44,13 +45,22 @@
#define UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) #define UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
#endif #endif
#ifdef CONFIG_ARCH_MX5
#ifdef UART_PADDR
#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
#endif
#include <mach/mx51.h>
#define UART_PADDR MX51_UART1_BASE_ADDR
#define UART_VADDR MX51_AIPS1_IO_ADDRESS(MX51_UART1_BASE_ADDR)
#endif
#ifdef CONFIG_ARCH_MXC91231 #ifdef CONFIG_ARCH_MXC91231
#ifdef UART_PADDR #ifdef UART_PADDR
#error "CONFIG_DEBUG_LL is incompatible with multiple archs" #error "CONFIG_DEBUG_LL is incompatible with multiple archs"
#endif #endif
#include <mach/mxc91231.h> #include <mach/mxc91231.h>
#define UART_PADDR MXC91231_UART2_BASE_ADDR #define UART_PADDR MXC91231_UART2_BASE_ADDR
#define UART_VADDR MXC91231_AIPS1_IO_ADDRESS(MXC91231_UART2_BASE_ADDR) #define UART_VADDR MXC91231_IO_ADDRESS(MXC91231_UART2_BASE_ADDR)
#endif #endif
.macro addruart,rx .macro addruart,rx
mrc p15, 0, \rx, c1, c0 mrc p15, 0, \rx, c1, c0
......
arch/arm/plat-mxc/include/mach/entry-macro.S
浏览文件 @ b93a4afc
/* /*
* Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org> * Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org>
* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/ */
/* /*
...@@ -18,11 +18,16 @@ ...@@ -18,11 +18,16 @@
.endm .endm
.macro get_irqnr_preamble, base, tmp .macro get_irqnr_preamble, base, tmp
#ifndef CONFIG_MXC_TZIC
ldr \base, =avic_base ldr \base, =avic_base
ldr \base, [\base] ldr \base, [\base]
#ifdef CONFIG_MXC_IRQ_PRIOR #ifdef CONFIG_MXC_IRQ_PRIOR
ldr r4, [\base, #AVIC_NIMASK] ldr r4, [\base, #AVIC_NIMASK]
#endif #endif
#elif defined CONFIG_MXC_TZIC
ldr \base, =tzic_base
ldr \base, [\base]
#endif /* CONFIG_MXC_TZIC */
.endm .endm
.macro arch_ret_to_user, tmp1, tmp2 .macro arch_ret_to_user, tmp1, tmp2
...@@ -32,6 +37,7 @@ ...@@ -32,6 +37,7 @@
@ and returns its number in irqnr @ and returns its number in irqnr
@ and returns if an interrupt occured in irqstat @ and returns if an interrupt occured in irqstat
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
#ifndef CONFIG_MXC_TZIC
@ Load offset & priority of the highest priority @ Load offset & priority of the highest priority
@ interrupt pending from AVIC_NIVECSR @ interrupt pending from AVIC_NIVECSR
ldr \irqstat, [\base, #0x40] ldr \irqstat, [\base, #0x40]
...@@ -44,6 +50,32 @@ ...@@ -44,6 +50,32 @@
bicne \tmp, \irqstat, #0xFFFFFFE0 bicne \tmp, \irqstat, #0xFFFFFFE0
strne \tmp, [\base, #AVIC_NIMASK] strne \tmp, [\base, #AVIC_NIMASK]
streq r4, [\base, #AVIC_NIMASK] streq r4, [\base, #AVIC_NIMASK]
#endif
#elif defined CONFIG_MXC_TZIC
@ Load offset & priority of the highest priority
@ interrupt pending.
@ 0xD80 is HIPND0 register
mov \irqnr, #0
mov \irqstat, #0x0D80
1000:
ldr \tmp, [\irqstat, \base]
cmp \tmp, #0
bne 1001f
addeq \irqnr, \irqnr, #32
addeq \irqstat, \irqstat, #4
cmp \irqnr, #128
blo 1000b
b 2001f
1001: mov \irqstat, #1
1002: tst \tmp, \irqstat
bne 2002f
movs \tmp, \tmp, lsr #1
addne \irqnr, \irqnr, #1
bne 1002b
2001:
mov \irqnr, #0
2002:
movs \irqnr, \irqnr
#endif #endif
.endm .endm
......
arch/arm/plat-mxc/include/mach/hardware.h
浏览文件 @ b93a4afc
...@@ -22,6 +22,15 @@ ...@@ -22,6 +22,15 @@
#include <asm/sizes.h> #include <asm/sizes.h>
#define IMX_IO_ADDRESS(addr, module) \
((void __force __iomem *) \
(((unsigned long)((addr) - (module ## _BASE_ADDR)) < module ## _SIZE) ?\
(addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0))
#ifdef CONFIG_ARCH_MX5
#include <mach/mx51.h>
#endif
#ifdef CONFIG_ARCH_MX3 #ifdef CONFIG_ARCH_MX3
#include <mach/mx3x.h> #include <mach/mx3x.h>
#include <mach/mx31.h> #include <mach/mx31.h>
......
arch/arm/plat-mxc/include/mach/iomux-mx1.h
浏览文件 @ b93a4afc
/* /*
* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
* *
* This program is free software; you can redistribute it and/or * This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License * modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2 * as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version. * of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful, * This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of * but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. * GNU General Public License for more details.
* *
* You should have received a copy of the GNU General Public License * You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software * along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA. * MA 02110-1301, USA.
*/ */
#ifndef __MACH_IOMUX_MX1_H__
#define __MACH_IOMUX_MX1_H__
#ifndef _MXC_IOMUX_MX1_H #include <mach/iomux-v1.h>
#define _MXC_IOMUX_MX1_H
#ifndef GPIO_PORTA
#error Please include mach/iomux.h
#endif
/* FIXME: This list is not completed. The correct directions are
* missing on some (many) pins
*/
/* Primary GPIO pin functions */
#define PA0_AIN_SPI2_CLK (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 0) #define PA0_AIN_SPI2_CLK (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 0)
#define PA0_AF_ETMTRACESYNC (GPIO_PORTA | GPIO_AF | 0) #define PA0_AF_ETMTRACESYNC (GPIO_PORTA | GPIO_AF | 0)
...@@ -162,5 +152,4 @@ ...@@ -162,5 +152,4 @@
#define PD31_PF_TMR2OUT (GPIO_PORTD | GPIO_PF | 31) #define PD31_PF_TMR2OUT (GPIO_PORTD | GPIO_PF | 31)
#define PD31_BIN_SPI2_TXD (GPIO_PORTD | GPIO_BIN | 31) #define PD31_BIN_SPI2_TXD (GPIO_PORTD | GPIO_BIN | 31)
#endif /* ifndef __MACH_IOMUX_MX1_H__ */
#endif
arch/arm/plat-mxc/include/mach/iomux-mx21.h
浏览文件 @ b93a4afc
/* /*
* Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de> * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de>
* *
* This program is free software; you can redistribute it and/or * This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License * modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2 * as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version. * of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful, * This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of * but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. * GNU General Public License for more details.
* *
* You should have received a copy of the GNU General Public License * You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software * along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA. * MA 02110-1301, USA.
*/ */
#ifndef __MACH_IOMUX_MX21_H__
#ifndef _MXC_IOMUX_MX21_H #define __MACH_IOMUX_MX21_H__
#define _MXC_IOMUX_MX21_H
#include <mach/iomux-mx2x.h>
#ifndef GPIO_PORTA #include <mach/iomux-v1.h>
#error Please include mach/iomux.h
#endif
/* Primary GPIO pin functions */ /* Primary GPIO pin functions */
...@@ -122,5 +119,4 @@ ...@@ -122,5 +119,4 @@
#define PF13_AOUT_PC_CD2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 13) #define PF13_AOUT_PC_CD2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 13)
#define PF14_AOUT_PC_CD1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 14) #define PF14_AOUT_PC_CD1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 14)
#endif /* ifndef __MACH_IOMUX_MX21_H__ */
#endif
arch/arm/plat-mxc/include/mach/iomux-mx25.h
浏览文件 @ b93a4afc
...@@ -7,7 +7,7 @@ ...@@ -7,7 +7,7 @@
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* and * and
* arch/arm/plat-mxc/include/mach/iomux-mx35.h * arch/arm/plat-mxc/include/mach/iomux-mx35.h
* Copyright (C, NO_PAD_CTRL) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de> * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de>
* *
* The code contained herein is licensed under the GNU General Public * The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License * License. You may obtain a copy of the GNU General Public License
...@@ -16,24 +16,11 @@ ...@@ -16,24 +16,11 @@
* http://www.opensource.org/licenses/gpl-license.html * http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html * http://www.gnu.org/copyleft/gpl.html
*/ */
#ifndef __IOMUX_MX25_H__ #ifndef __MACH_IOMUX_MX25_H__
#define __IOMUX_MX25_H__ #define __MACH_IOMUX_MX25_H__
#include <mach/iomux-v3.h> #include <mach/iomux-v3.h>
#ifndef GPIO_PORTA
#error Please include mach/iomux.h
#endif
/*
*
* @brief MX25 I/O Pin List
*
* @ingroup GPIO_MX25
*/
#ifndef __ASSEMBLY__
/* /*
* IOMUX/PAD Bit field definitions * IOMUX/PAD Bit field definitions
*/ */
...@@ -462,9 +449,11 @@ ...@@ -462,9 +449,11 @@
#define MX25_PAD_GPIO_C__CAN2_TX IOMUX_PAD(0x3f8, 0x1fc, 0x16, 0, 0, PAD_CTL_PUS_22K_UP) #define MX25_PAD_GPIO_C__CAN2_TX IOMUX_PAD(0x3f8, 0x1fc, 0x16, 0, 0, PAD_CTL_PUS_22K_UP)
#define MX25_PAD_GPIO_D__GPIO_D IOMUX_PAD(0x3fc, 0x200, 0x10, 0, 0, NO_PAD_CTRL) #define MX25_PAD_GPIO_D__GPIO_D IOMUX_PAD(0x3fc, 0x200, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_GPIO_E__LD16 IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_GPIO_D__CAN2_RX IOMUX_PAD(0x3fc, 0x200, 0x16, 0x484, 1, PAD_CTL_PUS_22K_UP) #define MX25_PAD_GPIO_D__CAN2_RX IOMUX_PAD(0x3fc, 0x200, 0x16, 0x484, 1, PAD_CTL_PUS_22K_UP)
#define MX25_PAD_GPIO_E__GPIO_E IOMUX_PAD(0x400, 0x204, 0x10, 0, 0, NO_PAD_CTRL) #define MX25_PAD_GPIO_E__GPIO_E IOMUX_PAD(0x400, 0x204, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_GPIO_F__LD17 IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_GPIO_E__AUD7_TXD IOMUX_PAD(0x400, 0x204, 0x14, 0, 0, NO_PAD_CTRL) #define MX25_PAD_GPIO_E__AUD7_TXD IOMUX_PAD(0x400, 0x204, 0x14, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_GPIO_F__GPIO_F IOMUX_PAD(0x404, 0x208, 0x10, 0, 0, NO_PAD_CTRL) #define MX25_PAD_GPIO_F__GPIO_F IOMUX_PAD(0x404, 0x208, 0x10, 0, 0, NO_PAD_CTRL)
...@@ -513,5 +502,4 @@ ...@@ -513,5 +502,4 @@
#define MX25_PAD_CTL_GRP_DVS_SDHC1 IOMUX_PAD(0x458, 0x000, 0, 0, 0, NO_PAD_CTRL) #define MX25_PAD_CTL_GRP_DVS_SDHC1 IOMUX_PAD(0x458, 0x000, 0, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CTL_GRP_DVS_LCD IOMUX_PAD(0x45c, 0x000, 0, 0, 0, NO_PAD_CTRL) #define MX25_PAD_CTL_GRP_DVS_LCD IOMUX_PAD(0x45c, 0x000, 0, 0, 0, NO_PAD_CTRL)
#endif // __ASSEMBLY__ #endif /* __MACH_IOMUX_MX25_H__ */
#endif // __IOMUX_MX25_H__
arch/arm/plat-mxc/include/mach/iomux-mx27.h
浏览文件 @ b93a4afc
/* /*
* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
* Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de> * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de>
* *
* This program is free software; you can redistribute it and/or * This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License * modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2 * as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version. * of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful, * This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of * but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. * GNU General Public License for more details.
* *
* You should have received a copy of the GNU General Public License * You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software * along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA. * MA 02110-1301, USA.
*/ */
#ifndef __MACH_IOMUX_MX27_H__
#ifndef _MXC_IOMUX_MX27_H #define __MACH_IOMUX_MX27_H__
#define _MXC_IOMUX_MX27_H
#include <mach/iomux-mx2x.h>
#ifndef GPIO_PORTA #include <mach/iomux-v1.h>
#error Please include mach/iomux.h
#endif
/* Primary GPIO pin functions */ /* Primary GPIO pin functions */
...@@ -47,8 +44,6 @@ ...@@ -47,8 +44,6 @@
#define PC17_PF_SSI4_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 17) #define PC17_PF_SSI4_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 17)
#define PC18_PF_SSI4_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 18) #define PC18_PF_SSI4_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 18)
#define PC19_PF_SSI4_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 19) #define PC19_PF_SSI4_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 19)
#define PC25_AF_GPT5_TIN (GPIO_PORTC | GPIO_AF | 25)
#define PC27_AF_GPT4_TIN (GPIO_PORTC | GPIO_AF | 27)
#define PD0_PF_SD3_CMD (GPIO_PORTD | GPIO_PF | 0) #define PD0_PF_SD3_CMD (GPIO_PORTD | GPIO_PF | 0)
#define PD1_PF_SD3_CLK (GPIO_PORTD | GPIO_PF | 1) #define PD1_PF_SD3_CLK (GPIO_PORTD | GPIO_PF | 1)
#define PD2_PF_ATA_DATA0 (GPIO_PORTD | GPIO_PF | 2) #define PD2_PF_ATA_DATA0 (GPIO_PORTD | GPIO_PF | 2)
...@@ -106,7 +101,9 @@ ...@@ -106,7 +101,9 @@
#define PB21_AF_UART5_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 21) #define PB21_AF_UART5_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 21)
#define PC8_AF_FEC_MDIO (GPIO_PORTC | GPIO_AF | GPIO_IN | 8) #define PC8_AF_FEC_MDIO (GPIO_PORTC | GPIO_AF | GPIO_IN | 8)
#define PC24_AF_GPT5_TOUT (GPIO_PORTC | GPIO_AF | 24) #define PC24_AF_GPT5_TOUT (GPIO_PORTC | GPIO_AF | 24)
#define PC25_AF_GPT5_TIN (GPIO_PORTC | GPIO_AF | 25)
#define PC26_AF_GPT4_TOUT (GPIO_PORTC | GPIO_AF | 26) #define PC26_AF_GPT4_TOUT (GPIO_PORTC | GPIO_AF | 26)
#define PC27_AF_GPT4_TIN (GPIO_PORTC | GPIO_AF | 27)
#define PD1_AF_ETMTRACE_PKT15 (GPIO_PORTD | GPIO_AF | 1) #define PD1_AF_ETMTRACE_PKT15 (GPIO_PORTD | GPIO_AF | 1)
#define PD6_AF_ETMTRACE_PKT14 (GPIO_PORTD | GPIO_AF | 6) #define PD6_AF_ETMTRACE_PKT14 (GPIO_PORTD | GPIO_AF | 6)
#define PD7_AF_ETMTRACE_PKT13 (GPIO_PORTD | GPIO_AF | 7) #define PD7_AF_ETMTRACE_PKT13 (GPIO_PORTD | GPIO_AF | 7)
...@@ -195,6 +192,8 @@ ...@@ -195,6 +192,8 @@
#define PD14_AOUT_FEC_RX_CLK (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 14) #define PD14_AOUT_FEC_RX_CLK (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 14)
#define PD15_AOUT_FEC_COL (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 15) #define PD15_AOUT_FEC_COL (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 15)
/* BOUT GPIO pin functions */
#define PC17_BOUT_PC_IOIS16 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 17) #define PC17_BOUT_PC_IOIS16 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 17)
#define PC18_BOUT_PC_BVD2 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 18) #define PC18_BOUT_PC_BVD2 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 18)
#define PC19_BOUT_PC_BVD1 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 19) #define PC19_BOUT_PC_BVD1 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 19)
...@@ -203,5 +202,4 @@ ...@@ -203,5 +202,4 @@
#define PC30_BOUT_PC_READY (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 30) #define PC30_BOUT_PC_READY (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 30)
#define PC31_BOUT_PC_WAIT (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 31) #define PC31_BOUT_PC_WAIT (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 31)
#endif /* __MACH_IOMUX_MX27_H__ */
#endif /* _MXC_GPIO_MX1_MX2_H */
arch/arm/plat-mxc/include/mach/iomux-mx2x.h
浏览文件 @ b93a4afc
/* /*
* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
* Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de> * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de>
* *
* This program is free software; you can redistribute it and/or * This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License * modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2 * as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version. * of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful, * This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of * but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. * GNU General Public License for more details.
* *
* You should have received a copy of the GNU General Public License * You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software * along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA. * MA 02110-1301, USA.
*/ */
#ifndef __MACH_IOMUX_MX2x_H__
#ifndef _MXC_IOMUX_MX2x_H #define __MACH_IOMUX_MX2x_H__
#define _MXC_IOMUX_MX2x_H
#ifndef GPIO_PORTA
#error Please include mach/iomux.h
#endif
/* Primary GPIO pin functions */ /* Primary GPIO pin functions */
...@@ -233,5 +227,4 @@ ...@@ -233,5 +227,4 @@
#define PC15_AOUT_WKGD (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 15) #define PC15_AOUT_WKGD (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 15)
#define PF21_AOUT_DTACK (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 21) #define PF21_AOUT_DTACK (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 21)
#endif /* ifndef __MACH_IOMUX_MX2x_H__ */
#endif
arch/arm/plat-mxc/include/mach/iomux-mx3.h
浏览文件 @ b93a4afc
...@@ -16,12 +16,10 @@ ...@@ -16,12 +16,10 @@
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA. * MA 02110-1301, USA.
*/ */
#ifndef __MACH_IOMUX_MX3_H__
#ifndef __MACH_MX31_IOMUX_H__ #define __MACH_IOMUX_MX3_H__
#define __MACH_MX31_IOMUX_H__
#include <linux/types.h> #include <linux/types.h>
/* /*
* various IOMUX output functions * various IOMUX output functions
*/ */
...@@ -166,11 +164,6 @@ int mxc_iomux_mode(unsigned int pin_mode); ...@@ -166,11 +164,6 @@ int mxc_iomux_mode(unsigned int pin_mode);
(((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT) + \ (((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT) + \
MXC_GPIO_IRQ_START) MXC_GPIO_IRQ_START)
/*
* The number of gpio devices among the pads
*/
#define GPIO_PORT_MAX 3
/* /*
* This enumeration is constructed based on the Section * This enumeration is constructed based on the Section
* "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated
...@@ -727,13 +720,14 @@ enum iomux_pins { ...@@ -727,13 +720,14 @@ enum iomux_pins {
#define MX31_PIN_SCK5__SCK5 IOMUX_MODE(MX31_PIN_SCK5, IOMUX_CONFIG_FUNC) #define MX31_PIN_SCK5__SCK5 IOMUX_MODE(MX31_PIN_SCK5, IOMUX_CONFIG_FUNC)
#define MX31_PIN_SFS5__SFS5 IOMUX_MODE(MX31_PIN_SFS5, IOMUX_CONFIG_FUNC) #define MX31_PIN_SFS5__SFS5 IOMUX_MODE(MX31_PIN_SFS5, IOMUX_CONFIG_FUNC)
/*XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed by cspi2_ss0, cspi2_ss1, cspi1_ss0 /*
* cspi1_ss1*/ * XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed with cspi2_ss0,
* cspi2_ss1, cspi1_ss0 cspi1_ss1
*/
/* /*
* This function configures the pad value for a IOMUX pin. * This function configures the pad value for a IOMUX pin.
*/ */
void mxc_iomux_set_pad(enum iomux_pins, u32); void mxc_iomux_set_pad(enum iomux_pins, u32);
#endif #endif /* ifndef __MACH_IOMUX_MX3_H__ */
arch/arm/plat-mxc/include/mach/iomux-mx35.h
浏览文件 @ b93a4afc
/* /*
* Copyright (C, NO_PAD_CTRL) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de> * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de>
* *
* This program is free software; you can redistribute it and/or * This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License * modify it under the terms of the GNU General Public License
......
arch/arm/plat-mxc/include/mach/iomux-mx51.h 0 → 100644
浏览文件 @ b93a4afc
/*
* Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __MACH_IOMUX_MX51_H__
#define __MACH_IOMUX_MX51_H__
#include <mach/iomux-v3.h>
/*
* various IOMUX alternate output functions (1-7)
*/
typedef enum iomux_config {
IOMUX_CONFIG_ALT0,
IOMUX_CONFIG_ALT1,
IOMUX_CONFIG_ALT2,
IOMUX_CONFIG_ALT3,
IOMUX_CONFIG_ALT4,
IOMUX_CONFIG_ALT5,
IOMUX_CONFIG_ALT6,
IOMUX_CONFIG_ALT7,
IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */
IOMUX_CONFIG_SION = 0x1 << 4, /* LOOPBACK:MUX SION bit */
} iomux_pin_cfg_t;
/* Pad control groupings */
#define MX51_UART1_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_DSE_HIGH)
#define MX51_UART2_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \
PAD_CTL_SRE_FAST)
#define MX51_UART3_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \
PAD_CTL_SRE_FAST)
/*
* The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
* If <padname> or <padmode> refers to a GPIO, it is named
* GPIO_<unit>_<num> see also iomux-v3.h
*/
/*
* FIXME: This was converted using scripts from existing Freescale code to
* this form used upstream. Need to verify the name format.
*/
/* PAD MUX ALT INPSE PATH PADCTRL */
#define MX51_PAD_GPIO_2_0__EIM_D16 IOMUX_PAD(0x3f0, 0x05c, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_2_1__EIM_D17 IOMUX_PAD(0x3f4, 0x060, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_2_2__EIM_D18 IOMUX_PAD(0x3f8, 0x064, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_2_3__EIM_D19 IOMUX_PAD(0x3fc, 0x068, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_2_4__EIM_D20 IOMUX_PAD(0x400, 0x06c, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_2_5__EIM_D21 IOMUX_PAD(0x404, 0x070, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_2_6__EIM_D22 IOMUX_PAD(0x408, 0x074, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_2_7__EIM_D23 IOMUX_PAD(0x40c, 0x078, 1, 0x0, 0, NO_PAD_CTRL)
/* Babbage UART3 */
#define MX51_PAD_EIM_D24__UART3_CTS IOMUX_PAD(0x410, 0x07c, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL)
#define MX51_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x414, 0x080, IOMUX_CONFIG_ALT3, 0x9f4, 0, MX51_UART3_PAD_CTRL)
#define MX51_PAD_EIM_D26__UART3_TXD IOMUX_PAD(0x418, 0x084, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL)
#define MX51_PAD_EIM_D27__UART3_RTS IOMUX_PAD(0x41c, 0x088, IOMUX_CONFIG_ALT3, 0x9f0, 0, MX51_UART3_PAD_CTRL)
#define MX51_PAD_EIM_D28__EIM_D28 IOMUX_PAD(0x420, 0x08c, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D29__EIM_D29 IOMUX_PAD(0x424, 0x090, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D30__EIM_D30 IOMUX_PAD(0x428, 0x094, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D31__EIM_D31 IOMUX_PAD(0x42c, 0x09c, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_2_10__EIM_A16 IOMUX_PAD(0x430, 0x09c, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_2_11__EIM_A17 IOMUX_PAD(0x434, 0x0a0, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_2_12__EIM_A18 IOMUX_PAD(0x438, 0x0a4, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_2_13__EIM_A19 IOMUX_PAD(0x43c, 0x0a8, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_2_14__EIM_A20 IOMUX_PAD(0x440, 0x0ac, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_2_15__EIM_A21 IOMUX_PAD(0x444, 0x0b0, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_2_16__EIM_A22 IOMUX_PAD(0x448, 0x0b4, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_2_17__EIM_A23 IOMUX_PAD(0x44c, 0x0b8, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_2_18__EIM_A24 IOMUX_PAD(0x450, 0x0bc, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_2_19__EIM_A25 IOMUX_PAD(0x454, 0x0c0, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_2_20__EIM_A26 IOMUX_PAD(0x458, 0x0c4, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_2_21__EIM_A27 IOMUX_PAD(0x45c, 0x0c8, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_EB0__EIM_EB0 IOMUX_PAD(0x460, 0x0cc, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_EB1__EIM_EB1 IOMUX_PAD(0x464, 0x0d0, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_2_22__EIM_EB2 IOMUX_PAD(0x468, 0x0d4, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_2_23__EIM_EB3 IOMUX_PAD(0x46c, 0x0d8, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_2_24__EIM_OE IOMUX_PAD(0x470, 0x0dc, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_2_25__EIM_CS0 IOMUX_PAD(0x474, 0x0e0, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_2_26__EIM_CS1 IOMUX_PAD(0x478, 0x0e4, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_2_27__EIM_CS2 IOMUX_PAD(0x47c, 0x0e8, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_2_28__EIM_CS3 IOMUX_PAD(0x480, 0x0ec, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_2_29__EIM_CS4 IOMUX_PAD(0x484, 0x0f0, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_2_30__EIM_CS5 IOMUX_PAD(0x488, 0x0f4, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_2_31__EIM_DTACK IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_3_1__EIM_LBA IOMUX_PAD(0x494, 0xFC, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_3_2__EIM_CRE IOMUX_PAD(0x4A0, 0x100, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4D0, 0x104, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_3_3__NANDF_WE_B IOMUX_PAD(0x4E4, 0x108, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_3_4__NANDF_RE_B IOMUX_PAD(0x4E8, 0x10C, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_3_5__NANDF_ALE IOMUX_PAD(0x4EC, 0x110, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_3_6__NANDF_CLE IOMUX_PAD(0x4F0, 0x114, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_3_7__NANDF_WP_B IOMUX_PAD(0x4F4, 0x118, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_3_8__NANDF_RB0 IOMUX_PAD(0x4F8, 0x11C, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_3_9__NANDF_RB1 IOMUX_PAD(0x4FC, 0x120, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_3_10__NANDF_RB2 IOMUX_PAD(0x500, 0x124, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_3_11__NANDF_RB3 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_3_12__GPIO_NAND IOMUX_PAD(0x514, 0x12C, 3, 0x0, 0, NO_PAD_CTRL)
/* REVISIT: Not sure of these values
#define MX51_PAD_GPIO_1___NANDF_RB4 IOMUX_PAD(, , , 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_3_13__NANDF_RB5 IOMUX_PAD(0x5D8, 0x130, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_3_15__NANDF_RB7 IOMUX_PAD(0x5E0, 0x138, 3, 0x0, 0, NO_PAD_CTRL)
*/
#define MX51_PAD_GPIO_3_14__NANDF_RB6 IOMUX_PAD(0x5DC, 0x134, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_3_16__NANDF_CS0 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_3_17__NANDF_CS1 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_3_18__NANDF_CS2 IOMUX_PAD(0x520, 0x138, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_3_19__NANDF_CS3 IOMUX_PAD(0x524, 0x13C, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_3_20__NANDF_CS4 IOMUX_PAD(0x528, 0x140, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_3_21__NANDF_CS5 IOMUX_PAD(0x52C, 0x144, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_3_22__NANDF_CS6 IOMUX_PAD(0x530, 0x148, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_3_23__NANDF_CS7 IOMUX_PAD(0x534, 0x14C, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_3_24__NANDF_RDY_INT IOMUX_PAD(0x538, 0x150, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_3_25__NANDF_D15 IOMUX_PAD(0x53C, 0x154, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_3_26__NANDF_D14 IOMUX_PAD(0x540, 0x158, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_3_27__NANDF_D13 IOMUX_PAD(0x544, 0x15C, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_3_28__NANDF_D12 IOMUX_PAD(0x548, 0x160, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_3_29__NANDF_D11 IOMUX_PAD(0x54C, 0x164, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_3_30__NANDF_D10 IOMUX_PAD(0x550, 0x168, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_3_31__NANDF_D9 IOMUX_PAD(0x554, 0x16C, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_4_0__NANDF_D8 IOMUX_PAD(0x558, 0x170, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_4_1__NANDF_D7 IOMUX_PAD(0x55C, 0x174, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_4_2__NANDF_D6 IOMUX_PAD(0x560, 0x178, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_4_3__NANDF_D5 IOMUX_PAD(0x564, 0x17C, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_4_4__NANDF_D4 IOMUX_PAD(0x568, 0x180, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_4_5__NANDF_D3 IOMUX_PAD(0x56C, 0x184, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_4_6__NANDF_D2 IOMUX_PAD(0x570, 0x188, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_4_7__NANDF_D1 IOMUX_PAD(0x574, 0x18C, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_4_8__NANDF_D0 IOMUX_PAD(0x578, 0x190, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_3_12__CSI1_D8 IOMUX_PAD(0x57C, 0x194, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_3_13__CSI1_D9 IOMUX_PAD(0x580, 0x198, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_D10__CSI1_D10 IOMUX_PAD(0x584, 0x19C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_D11__CSI1_D11 IOMUX_PAD(0x588, 0x1A0, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_D12__CSI1_D12 IOMUX_PAD(0x58C, 0x1A4, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_D13__CSI1_D13 IOMUX_PAD(0x590, 0x1A8, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_D14__CSI1_D14 IOMUX_PAD(0x594, 0x1AC, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_D15__CSI1_D15 IOMUX_PAD(0x598, 0x1B0, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_D16__CSI1_D16 IOMUX_PAD(0x59C, 0x1B4, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_D17__CSI1_D17 IOMUX_PAD(0x5A0, 0x1B8, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_D18__CSI1_D18 IOMUX_PAD(0x5A4, 0x1BC, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_D19__CSI1_D19 IOMUX_PAD(0x5A8, 0x1C0, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC IOMUX_PAD(0x5AC, 0x1C4, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC IOMUX_PAD(0x5B0, 0x1C8, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK IOMUX_PAD(0x5B4, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_MCLK__CSI1_MCLK IOMUX_PAD(0x5B8, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_PKE0__CSI1_PKE0 IOMUX_PAD(0x860, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_4_9__CSI2_D12 IOMUX_PAD(0x5BC, 0x1CC, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_4_10__CSI2_D13 IOMUX_PAD(0x5C0, 0x1D0, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_4_11__CSI2_D14 IOMUX_PAD(0x5C4, 0x1D4, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_4_12__CSI2_D15 IOMUX_PAD(0x5C8, 0x1D8, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_4_11__CSI2_D16 IOMUX_PAD(0x5CC, 0x1DC, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_4_12__CSI2_D17 IOMUX_PAD(0x5D0, 0x1E0, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_4_11__CSI2_D18 IOMUX_PAD(0x5D4, 0x1E4, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_4_12__CSI2_D19 IOMUX_PAD(0x5D8, 0x1E8, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_4_13__CSI2_VSYNC IOMUX_PAD(0x5DC, 0x1EC, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_4_14__CSI2_HSYNC IOMUX_PAD(0x5E0, 0x1F0, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_4_15__CSI2_PIXCLK IOMUX_PAD(0x5E4, 0x1F4, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI2_PKE0__CSI2_PKE0 IOMUX_PAD(0x81C, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_4_16__I2C1_CLK IOMUX_PAD(0x5E8, 0x1F8, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_4_17__I2C1_DAT IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_4_18__AUD3_BB_TXD IOMUX_PAD(0x5F0, 0x200, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_4_19__AUD3_BB_RXD IOMUX_PAD(0x5F4, 0x204, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_4_20__AUD3_BB_CK IOMUX_PAD(0x5F8, 0x208, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_4_21__AUD3_BB_FS IOMUX_PAD(0x5FC, 0x20C, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_4_22__CSPI1_MOSI IOMUX_PAD(0x600, 0x210, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_4_23__CSPI1_MISO IOMUX_PAD(0x604, 0x214, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_4_24__CSPI1_SS0 IOMUX_PAD(0x608, 0x218, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_4_25__CSPI1_SS1 IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_4_26__CSPI1_RDY IOMUX_PAD(0x610, 0x220, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_4_27__CSPI1_SCLK IOMUX_PAD(0x614, 0x224, 3, 0x0, 0, NO_PAD_CTRL)
/* Babbage UART1 */
#define MX51_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x618, 0x228, IOMUX_CONFIG_ALT0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
#define MX51_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x61C, 0x22C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
#define MX51_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x620, 0x230, IOMUX_CONFIG_ALT0, 0x9e0, 0, MX51_UART1_PAD_CTRL)
#define MX51_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x624, 0x234, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART1_PAD_CTRL)
/* Babbage UART2 */
#define MX51_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x628, 0x238, IOMUX_CONFIG_ALT0, 0x9ec, 2, MX51_UART2_PAD_CTRL)
#define MX51_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x62C, 0x23C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART2_PAD_CTRL)
#define MX51_PAD_GPIO_1_22__UART3_RXD IOMUX_PAD(0x630, 0x240, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_1_23__UART3_TXD IOMUX_PAD(0x634, 0x244, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_1_24__OWIRE_LINE IOMUX_PAD(0x638, 0x248, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x63C, 0x24C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x640, 0x250, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x644, 0x254, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x648, 0x258, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x64C, 0x25C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x650, 0x260, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x654, 0x264, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x658, 0x268, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_KEY_COL4__KEY_COL4 IOMUX_PAD(0x65C, 0x26C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_KEY_COL5__KEY_COL5 IOMUX_PAD(0x660, 0x270, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_1_25__USBH1_CLK IOMUX_PAD(0x678, 0x278, 2, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_1_26__USBH1_DIR IOMUX_PAD(0x67C, 0x27C, 2, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_1_27__USBH1_STP IOMUX_PAD(0x680, 0x280, 2, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_1_28__USBH1_NXT IOMUX_PAD(0x684, 0x284, 2, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_1_11__USBH1_DATA0 IOMUX_PAD(0x688, 0x288, 2, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_1_12__USBH1_DATA1 IOMUX_PAD(0x68C, 0x28C, 2, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_1_13__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, 2, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_1_14__USBH1_DATA3 IOMUX_PAD(0x694, 0x294, 2, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_1_15__USBH1_DATA4 IOMUX_PAD(0x698, 0x298, 2, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_1_16__USBH1_DATA5 IOMUX_PAD(0x69C, 0x29C, 2, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_1_17__USBH1_DATA6 IOMUX_PAD(0x6A0, 0x2A0, 2, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_1_18__USBH1_DATA7 IOMUX_PAD(0x6A4, 0x2A4, 2, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_3_0__DI1_PIN11 IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_3_1__DI1_PIN12 IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_3_2__DI1_PIN13 IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_3_3__DI1_D0_CS IOMUX_PAD(0x6B4, 0x2B4, 4, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_3_4__DI1_D1_CS IOMUX_PAD(0x6B8, 0x2B8, 4, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_3_5__DISPB2_SER_DIN IOMUX_PAD(0x6BC, 0x2BC, 4, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_3_6__DISPB2_SER_DIO IOMUX_PAD(0x6C0, 0x2C0, 4, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_3_7__DISPB2_SER_CLK IOMUX_PAD(0x6C4, 0x2C4, 4, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_3_8__DISPB2_SER_RS IOMUX_PAD(0x6C8, 0x2C8, 4, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 IOMUX_PAD(0x6D8, 0x2D8, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 IOMUX_PAD(0x6DC, 0x2DC, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 IOMUX_PAD(0x6E0, 0x2E0, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 IOMUX_PAD(0x6E4, 0x2E4, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 IOMUX_PAD(0x6E8, 0x2E8, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 IOMUX_PAD(0x6EC, 0x2EC, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 IOMUX_PAD(0x6F0, 0x2F0, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT10__DISP1_DAT10 IOMUX_PAD(0x6F4, 0x2F4, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT11__DISP1_DAT11 IOMUX_PAD(0x6F8, 0x2F8, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT12__DISP1_DAT12 IOMUX_PAD(0x6FC, 0x2FC, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT13__DISP1_DAT13 IOMUX_PAD(0x700, 0x300, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT14__DISP1_DAT14 IOMUX_PAD(0x704, 0x304, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT15__DISP1_DAT15 IOMUX_PAD(0x708, 0x308, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT16__DISP1_DAT16 IOMUX_PAD(0x70C, 0x30C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT17__DISP1_DAT17 IOMUX_PAD(0x710, 0x310, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT18__DISP1_DAT18 IOMUX_PAD(0x714, 0x314, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT19__DISP1_DAT19 IOMUX_PAD(0x718, 0x318, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT20__DISP1_DAT20 IOMUX_PAD(0x71C, 0x31C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT21__DISP1_DAT21 IOMUX_PAD(0x720, 0x320, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT22__DISP1_DAT22 IOMUX_PAD(0x724, 0x324, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT23__DISP1_DAT23 IOMUX_PAD(0x728, 0x328, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DI1_PIN3__DI1_PIN3 IOMUX_PAD(0x72C, 0x32C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DI1_PIN2__DI1_PIN2 IOMUX_PAD(0x734, 0x330, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DI_GP1__DI_GP1 IOMUX_PAD(0x73C, 0x334, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DI_GP2__DI_GP2 IOMUX_PAD(0x740, 0x338, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DI_GP3__DI_GP3 IOMUX_PAD(0x744, 0x33C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DI2_PIN4__DI2_PIN4 IOMUX_PAD(0x748, 0x340, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DI2_PIN2__DI2_PIN2 IOMUX_PAD(0x74C, 0x344, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DI2_PIN3__DI2_PIN3 IOMUX_PAD(0x750, 0x348, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK IOMUX_PAD(0x754, 0x34C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DI_GP4__DI_GP4 IOMUX_PAD(0x758, 0x350, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT0__DISP2_DAT0 IOMUX_PAD(0x75C, 0x354, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT1__DISP2_DAT1 IOMUX_PAD(0x760, 0x358, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT2__DISP2_DAT2 IOMUX_PAD(0x764, 0x35C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT3__DISP2_DAT3 IOMUX_PAD(0x768, 0x360, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT4__DISP2_DAT4 IOMUX_PAD(0x76C, 0x364, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT5__DISP2_DAT5 IOMUX_PAD(0x770, 0x368, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_1_19__DISP2_DAT6 IOMUX_PAD(0x774, 0x36C, 5, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_1_29__DISP2_DAT7 IOMUX_PAD(0x778, 0x370, 5, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_1_30__DISP2_DAT8 IOMUX_PAD(0x77C, 0x374, 5, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_1_31__DISP2_DAT9 IOMUX_PAD(0x780, 0x378, 5, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT10__DISP2_DAT10 IOMUX_PAD(0x784, 0x37C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT11__DISP2_DAT11 IOMUX_PAD(0x788, 0x380, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT12__DISP2_DAT12 IOMUX_PAD(0x78C, 0x384, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 IOMUX_PAD(0x790, 0x388, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 IOMUX_PAD(0x794, 0x38C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 IOMUX_PAD(0x798, 0x390, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79C, 0x394, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7A0, 0x398, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7A4, 0x39C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7A8, 0x3A0, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7AC, 0x3A4, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7B0, 0x3A8, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_1_0__GPIO1_0 IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_1_1__GPIO1_1 IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7BC, 0x3B4, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7C0, 0x3B8, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7C4, 0x3BC, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7C8, 0x3C0, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7CC, 0x3C4, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7D0, 0x3C8, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_1_2__GPIO1_2 IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_1_3__GPIO1_3 IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3D8, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_1_6__GPIO1_6 IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 1, \
(PAD_CTL_SRE_SLOW | PAD_CTL_DSE_MED | PAD_CTL_PUS_100K_UP | PAD_CTL_HYS))
#define MX51_PAD_GPIO_1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL)
/* EIM */
#define MX51_PAD_EIM_DA0__EIM_DA0 IOMUX_PAD(0x7a8, 0x01c, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_DA1__EIM_DA1 IOMUX_PAD(0x7a8, 0x020, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_DA2__EIM_DA2 IOMUX_PAD(0x7a8, 0x024, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_DA3__EIM_DA3 IOMUX_PAD(0x7a8, 0x028, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_DA4__EIM_DA4 IOMUX_PAD(0x7ac, 0x02c, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_DA5__EIM_DA5 IOMUX_PAD(0x7ac, 0x030, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_DA6__EIM_DA6 IOMUX_PAD(0x7ac, 0x034, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_DA7__EIM_DA7 IOMUX_PAD(0x7ac, 0x038, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_DA8__EIM_DA8 IOMUX_PAD(0x7b0, 0x03c, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_DA9__EIM_DA9 IOMUX_PAD(0x7b0, 0x040, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_DA10__EIM_DA10 IOMUX_PAD(0x7b0, 0x044, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_DA11__EIM_DA11 IOMUX_PAD(0x7b0, 0x048, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_DA12__EIM_DA12 IOMUX_PAD(0x7bc, 0x04c, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_DA13__EIM_DA13 IOMUX_PAD(0x7bc, 0x050, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_DA14__EIM_DA14 IOMUX_PAD(0x7bc, 0x054, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_DA15__EIM_DA15 IOMUX_PAD(0x7bc, 0x058, 0, 0x0, 0, NO_PAD_CTRL)
#endif /* __MACH_IOMUX_MX51_H__ */
arch/arm/plat-mxc/include/mach/iomux-v1.h 0 → 100644
浏览文件 @ b93a4afc
/*
* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
* Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#ifndef __MACH_IOMUX_V1_H__
#define __MACH_IOMUX_V1_H__
/*
* GPIO Module and I/O Multiplexer
* x = 0..3 for reg_A, reg_B, reg_C, reg_D
*/
#define MXC_DDIR(x) (0x00 + ((x) << 8))
#define MXC_OCR1(x) (0x04 + ((x) << 8))
#define MXC_OCR2(x) (0x08 + ((x) << 8))
#define MXC_ICONFA1(x) (0x0c + ((x) << 8))
#define MXC_ICONFA2(x) (0x10 + ((x) << 8))
#define MXC_ICONFB1(x) (0x14 + ((x) << 8))
#define MXC_ICONFB2(x) (0x18 + ((x) << 8))
#define MXC_DR(x) (0x1c + ((x) << 8))
#define MXC_GIUS(x) (0x20 + ((x) << 8))
#define MXC_SSR(x) (0x24 + ((x) << 8))
#define MXC_ICR1(x) (0x28 + ((x) << 8))
#define MXC_ICR2(x) (0x2c + ((x) << 8))
#define MXC_IMR(x) (0x30 + ((x) << 8))
#define MXC_ISR(x) (0x34 + ((x) << 8))
#define MXC_GPR(x) (0x38 + ((x) << 8))
#define MXC_SWR(x) (0x3c + ((x) << 8))
#define MXC_PUEN(x) (0x40 + ((x) << 8))
#define MX1_NUM_GPIO_PORT 4
#define MX21_NUM_GPIO_PORT 6
#define MX27_NUM_GPIO_PORT 6
#define GPIO_PIN_MASK 0x1f
#define GPIO_PORT_SHIFT 5
#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
#define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
#define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
#define GPIO_PORTC (2 << GPIO_PORT_SHIFT)
#define GPIO_PORTD (3 << GPIO_PORT_SHIFT)
#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
#define GPIO_OUT (1 << 8)
#define GPIO_IN (0 << 8)
#define GPIO_PUEN (1 << 9)
#define GPIO_PF (1 << 10)
#define GPIO_AF (1 << 11)
#define GPIO_OCR_SHIFT 12
#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT)
#define GPIO_AIN (0 << GPIO_OCR_SHIFT)
#define GPIO_BIN (1 << GPIO_OCR_SHIFT)
#define GPIO_CIN (2 << GPIO_OCR_SHIFT)
#define GPIO_GPIO (3 << GPIO_OCR_SHIFT)
#define GPIO_AOUT_SHIFT 14
#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT)
#define GPIO_AOUT (0 << GPIO_AOUT_SHIFT)
#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT)
#define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT)
#define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT)
#define GPIO_BOUT_SHIFT 16
#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT)
#define GPIO_BOUT (0 << GPIO_BOUT_SHIFT)
#define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT)
#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT)
#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT)
/* decode irq number to use with IMR(x), ISR(x) and friends */
#define IRQ_TO_REG(irq) ((irq - MXC_INTERNAL_IRQS) >> 5)
#define IRQ_GPIOA(x) (MXC_GPIO_IRQ_START + x)
#define IRQ_GPIOB(x) (IRQ_GPIOA(32) + x)
#define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x)
#define IRQ_GPIOD(x) (IRQ_GPIOC(32) + x)
#define IRQ_GPIOE(x) (IRQ_GPIOD(32) + x)
#define IRQ_GPIOF(x) (IRQ_GPIOE(32) + x)
extern int mxc_gpio_mode(int gpio_mode);
extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
const char *label);
extern void mxc_gpio_release_multiple_pins(const int *pin_list, int count);
#endif /* __MACH_IOMUX_V1_H__ */
arch/arm/plat-mxc/include/mach/iomux-v3.h
浏览文件 @ b93a4afc
...@@ -81,11 +81,13 @@ struct pad_desc { ...@@ -81,11 +81,13 @@ struct pad_desc {
#define PAD_CTL_ODE (1 << 3) #define PAD_CTL_ODE (1 << 3)
#define PAD_CTL_DSE_STANDARD (0 << 1) #define PAD_CTL_DSE_LOW (0 << 1)
#define PAD_CTL_DSE_HIGH (1 << 1) #define PAD_CTL_DSE_MED (1 << 1)
#define PAD_CTL_DSE_MAX (2 << 1) #define PAD_CTL_DSE_HIGH (2 << 1)
#define PAD_CTL_DSE_MAX (3 << 1)
#define PAD_CTL_SRE_FAST (1 << 0) #define PAD_CTL_SRE_FAST (1 << 0)
#define PAD_CTL_SRE_SLOW (0 << 0)
/* /*
* setups a single pad in the iomuxer * setups a single pad in the iomuxer
......
arch/arm/plat-mxc/include/mach/iomux.h
浏览文件 @ b93a4afc
/* /*
* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> * Copyright (C) 2010 Uwe Kleine-Koenig, Pengutronix
* Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de> *
* * This program is free software; you can redistribute it and/or modify it
* This program is free software; you can redistribute it and/or * under the terms of the GNU General Public License version 2 as published by
* modify it under the terms of the GNU General Public License * the Free Software Foundation.
* as published by the Free Software Foundation; either version 2 */
* of the License, or (at your option) any later version. #ifndef __MACH_IOMUX_H__
* This program is distributed in the hope that it will be useful, #define __MACH_IOMUX_H__
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#ifndef _MXC_IOMUX_H
#define _MXC_IOMUX_H
/*
* GPIO Module and I/O Multiplexer
* x = 0..3 for reg_A, reg_B, reg_C, reg_D
*/
#define VA_GPIO_BASE IO_ADDRESS(GPIO_BASE_ADDR)
#define MXC_DDIR(x) (0x00 + ((x) << 8))
#define MXC_OCR1(x) (0x04 + ((x) << 8))
#define MXC_OCR2(x) (0x08 + ((x) << 8))
#define MXC_ICONFA1(x) (0x0c + ((x) << 8))
#define MXC_ICONFA2(x) (0x10 + ((x) << 8))
#define MXC_ICONFB1(x) (0x14 + ((x) << 8))
#define MXC_ICONFB2(x) (0x18 + ((x) << 8))
#define MXC_DR(x) (0x1c + ((x) << 8))
#define MXC_GIUS(x) (0x20 + ((x) << 8))
#define MXC_SSR(x) (0x24 + ((x) << 8))
#define MXC_ICR1(x) (0x28 + ((x) << 8))
#define MXC_ICR2(x) (0x2c + ((x) << 8))
#define MXC_IMR(x) (0x30 + ((x) << 8))
#define MXC_ISR(x) (0x34 + ((x) << 8))
#define MXC_GPR(x) (0x38 + ((x) << 8))
#define MXC_SWR(x) (0x3c + ((x) << 8))
#define MXC_PUEN(x) (0x40 + ((x) << 8))
#ifdef CONFIG_ARCH_MX1
# define GPIO_PORT_MAX 3
#endif
#ifdef CONFIG_ARCH_MX2
# define GPIO_PORT_MAX 5
#endif
#ifdef CONFIG_ARCH_MX25
# define GPIO_PORT_MAX 3
#endif
#ifndef GPIO_PORT_MAX
# error "GPIO config port count unknown!"
#endif
#define GPIO_PIN_MASK 0x1f
#define GPIO_PORT_SHIFT 5
#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
#define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
#define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
#define GPIO_PORTC (2 << GPIO_PORT_SHIFT)
#define GPIO_PORTD (3 << GPIO_PORT_SHIFT)
#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
#define GPIO_OUT (1 << 8)
#define GPIO_IN (0 << 8)
#define GPIO_PUEN (1 << 9)
#define GPIO_PF (1 << 10)
#define GPIO_AF (1 << 11)
#define GPIO_OCR_SHIFT 12
#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT)
#define GPIO_AIN (0 << GPIO_OCR_SHIFT)
#define GPIO_BIN (1 << GPIO_OCR_SHIFT)
#define GPIO_CIN (2 << GPIO_OCR_SHIFT)
#define GPIO_GPIO (3 << GPIO_OCR_SHIFT)
#define GPIO_AOUT_SHIFT 14
#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT)
#define GPIO_AOUT (0 << GPIO_AOUT_SHIFT)
#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT)
#define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT)
#define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT)
#define GPIO_BOUT_SHIFT 16
#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT)
#define GPIO_BOUT (0 << GPIO_BOUT_SHIFT)
#define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT)
#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT)
#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT)
/* This file will go away, please include mach/iomux-mx... directly */
#ifdef CONFIG_ARCH_MX1 #ifdef CONFIG_ARCH_MX1
#include <mach/iomux-mx1.h> #include <mach/iomux-mx1.h>
...@@ -110,25 +22,5 @@ ...@@ -110,25 +22,5 @@
#include <mach/iomux-mx27.h> #include <mach/iomux-mx27.h>
#endif #endif
#endif #endif
#ifdef CONFIG_ARCH_MX25
#include <mach/iomux-mx25.h>
#endif
#endif /* __MACH_IOMUX_H__ */
/* decode irq number to use with IMR(x), ISR(x) and friends */
#define IRQ_TO_REG(irq) ((irq - MXC_INTERNAL_IRQS) >> 5)
#define IRQ_GPIOA(x) (MXC_GPIO_IRQ_START + x)
#define IRQ_GPIOB(x) (IRQ_GPIOA(32) + x)
#define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x)
#define IRQ_GPIOD(x) (IRQ_GPIOC(32) + x)
#define IRQ_GPIOE(x) (IRQ_GPIOD(32) + x)
#define IRQ_GPIOF(x) (IRQ_GPIOE(32) + x)
extern void mxc_gpio_mode(int gpio_mode);
extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
const char *label);
extern void mxc_gpio_release_multiple_pins(const int *pin_list, int count);
#endif
arch/arm/plat-mxc/include/mach/irqs.h
浏览文件 @ b93a4afc
...@@ -12,22 +12,29 @@ ...@@ -12,22 +12,29 @@
#define __ASM_ARCH_MXC_IRQS_H__ #define __ASM_ARCH_MXC_IRQS_H__
/* /*
* So far all i.MX SoCs have 64 internal interrupts * SoCs with TZIC interrupt controller have 128 IRQs, those with AVIC have 64
*/ */
#ifdef CONFIG_MXC_TZIC
#define MXC_INTERNAL_IRQS 128
#else
#define MXC_INTERNAL_IRQS 64 #define MXC_INTERNAL_IRQS 64
#endif
#define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS #define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS
#if defined CONFIG_ARCH_MX1 /* these are ordered by size to support multi-SoC kernels */
#define MXC_GPIO_IRQS (32 * 4) #if defined CONFIG_ARCH_MX2
#elif defined CONFIG_ARCH_MX2
#define MXC_GPIO_IRQS (32 * 6) #define MXC_GPIO_IRQS (32 * 6)
#elif defined CONFIG_ARCH_MX3 #elif defined CONFIG_ARCH_MX1
#define MXC_GPIO_IRQS (32 * 3) #define MXC_GPIO_IRQS (32 * 4)
#elif defined CONFIG_ARCH_MX25 #elif defined CONFIG_ARCH_MX25
#define MXC_GPIO_IRQS (32 * 4) #define MXC_GPIO_IRQS (32 * 4)
#elif defined CONFIG_ARCH_MX5
#define MXC_GPIO_IRQS (32 * 4)
#elif defined CONFIG_ARCH_MXC91231 #elif defined CONFIG_ARCH_MXC91231
#define MXC_GPIO_IRQS (32 * 4) #define MXC_GPIO_IRQS (32 * 4)
#elif defined CONFIG_ARCH_MX3
#define MXC_GPIO_IRQS (32 * 3)
#endif #endif
/* /*
...@@ -51,6 +58,7 @@ ...@@ -51,6 +58,7 @@
#else #else
#define MX3_IPU_IRQS 0 #define MX3_IPU_IRQS 0
#endif #endif
/* REVISIT: Add IPU irqs on IMX51 */
#define NR_IRQS (MXC_IPU_IRQ_START + MX3_IPU_IRQS) #define NR_IRQS (MXC_IPU_IRQ_START + MX3_IPU_IRQS)
......
arch/arm/plat-mxc/include/mach/memory.h
浏览文件 @ b93a4afc
...@@ -11,37 +11,45 @@ ...@@ -11,37 +11,45 @@
#ifndef __ASM_ARCH_MXC_MEMORY_H__ #ifndef __ASM_ARCH_MXC_MEMORY_H__
#define __ASM_ARCH_MXC_MEMORY_H__ #define __ASM_ARCH_MXC_MEMORY_H__
#if defined CONFIG_ARCH_MX1 #define MX1_PHYS_OFFSET UL(0x08000000)
#define PHYS_OFFSET UL(0x08000000) #define MX21_PHYS_OFFSET UL(0xc0000000)
#elif defined CONFIG_ARCH_MX2 #define MX25_PHYS_OFFSET UL(0x80000000)
#ifdef CONFIG_MACH_MX21 #define MX27_PHYS_OFFSET UL(0xa0000000)
#define PHYS_OFFSET UL(0xC0000000) #define MX3x_PHYS_OFFSET UL(0x80000000)
#endif #define MX51_PHYS_OFFSET UL(0x90000000)
#ifdef CONFIG_MACH_MX27 #define MXC91231_PHYS_OFFSET UL(0x90000000)
#define PHYS_OFFSET UL(0xA0000000)
#endif #if !defined(CONFIG_RUNTIME_PHYS_OFFSET)
#elif defined CONFIG_ARCH_MX3 # if defined CONFIG_ARCH_MX1
#define PHYS_OFFSET UL(0x80000000) # define PHYS_OFFSET MX1_PHYS_OFFSET
#elif defined CONFIG_ARCH_MX25 # elif defined CONFIG_MACH_MX21
#define PHYS_OFFSET UL(0x80000000) # define PHYS_OFFSET MX21_PHYS_OFFSET
#elif defined CONFIG_ARCH_MXC91231 # elif defined CONFIG_ARCH_MX25
#define PHYS_OFFSET UL(0x90000000) # define PHYS_OFFSET MX25_PHYS_OFFSET
# elif defined CONFIG_MACH_MX27
# define PHYS_OFFSET MX27_PHYS_OFFSET
# elif defined CONFIG_ARCH_MX3
# define PHYS_OFFSET MX3x_PHYS_OFFSET
# elif defined CONFIG_ARCH_MXC91231
# define PHYS_OFFSET MXC91231_PHYS_OFFSET
# elif defined CONFIG_ARCH_MX5
# define PHYS_OFFSET MX51_PHYS_OFFSET
# endif
#endif #endif
#if defined(CONFIG_MX1_VIDEO) #if defined(CONFIG_MX3_VIDEO)
/* /*
* Increase size of DMA-consistent memory region. * Increase size of DMA-consistent memory region.
* This is required for i.MX camera driver to capture at least four VGA frames. * This is required for mx3 camera driver to capture at least two QXGA frames.
*/ */
#define CONSISTENT_DMA_SIZE SZ_4M #define CONSISTENT_DMA_SIZE SZ_8M
#endif /* CONFIG_MX1_VIDEO */
#if defined(CONFIG_MX3_VIDEO) #elif defined(CONFIG_MX1_VIDEO)
/* /*
* Increase size of DMA-consistent memory region. * Increase size of DMA-consistent memory region.
* This is required for mx3 camera driver to capture at least two QXGA frames. * This is required for i.MX camera driver to capture at least four VGA frames.
*/ */
#define CONSISTENT_DMA_SIZE SZ_8M #define CONSISTENT_DMA_SIZE SZ_4M
#endif /* CONFIG_MX3_VIDEO */ #endif /* CONFIG_MX1_VIDEO */
#endif /* __ASM_ARCH_MXC_MEMORY_H__ */ #endif /* __ASM_ARCH_MXC_MEMORY_H__ */
arch/arm/plat-mxc/include/mach/mtd-xip.h 已删除 100644 → 0
浏览文件 @ 62c132a8
/*
* MTD primitives for XIP support. Architecture specific functions
*
* Do not include this file directly. It's included from linux/mtd/xip.h
*
* Copyright (C) 2008 Darius Augulis <augulis.darius@gmail.com>, Teltonika, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <mach/mxc_timer.h>
#ifndef __ARCH_IMX_MTD_XIP_H__
#define __ARCH_IMX_MTD_XIP_H__
#ifdef CONFIG_ARCH_MX1
/* AITC registers */
#define AITC_BASE IO_ADDRESS(AVIC_BASE_ADDR)
#define NIPNDH (AITC_BASE + 0x58)
#define NIPNDL (AITC_BASE + 0x5C)
#define INTENABLEH (AITC_BASE + 0x10)
#define INTENABLEL (AITC_BASE + 0x14)
/* MTD macros */
#define xip_irqpending() ((__raw_readl(INTENABLEH) & __raw_readl(NIPNDH)) \
|| (__raw_readl(INTENABLEL) & __raw_readl(NIPNDL)))
#define xip_currtime() (__raw_readl(TIMER_BASE + MXC_TCN))
#define xip_elapsed_since(x) (signed)((__raw_readl(TIMER_BASE + MXC_TCN) - (x)) / 96)
#define xip_cpu_idle() asm volatile ("mcr p15, 0, %0, c7, c0, 4" :: "r" (0))
#endif /* CONFIG_ARCH_MX1 */
#endif /* __ARCH_IMX_MTD_XIP_H__ */
arch/arm/plat-mxc/include/mach/mx1.h
浏览文件 @ b93a4afc
...@@ -9,156 +9,289 @@ ...@@ -9,156 +9,289 @@
* published by the Free Software Foundation. * published by the Free Software Foundation.
*/ */
#ifndef __ASM_ARCH_MXC_MX1_H__ #ifndef __MACH_MX1_H__
#define __ASM_ARCH_MXC_MX1_H__ #define __MACH_MX1_H__
#include <mach/vmalloc.h> #include <mach/vmalloc.h>
/* /*
* Memory map * Memory map
*/ */
#define IMX_IO_PHYS 0x00200000 #define MX1_IO_BASE_ADDR 0x00200000
#define IMX_IO_SIZE 0x00100000 #define MX1_IO_SIZE SZ_1M
#define IMX_IO_BASE VMALLOC_END #define MX1_IO_BASE_ADDR_VIRT VMALLOC_END
#define IMX_CS0_PHYS 0x10000000 #define MX1_CS0_PHYS 0x10000000
#define IMX_CS0_SIZE 0x02000000 #define MX1_CS0_SIZE 0x02000000
#define IMX_CS1_PHYS 0x12000000 #define MX1_CS1_PHYS 0x12000000
#define IMX_CS1_SIZE 0x01000000 #define MX1_CS1_SIZE 0x01000000
#define IMX_CS2_PHYS 0x13000000 #define MX1_CS2_PHYS 0x13000000
#define IMX_CS2_SIZE 0x01000000 #define MX1_CS2_SIZE 0x01000000
#define IMX_CS3_PHYS 0x14000000 #define MX1_CS3_PHYS 0x14000000
#define IMX_CS3_SIZE 0x01000000 #define MX1_CS3_SIZE 0x01000000
#define IMX_CS4_PHYS 0x15000000 #define MX1_CS4_PHYS 0x15000000
#define IMX_CS4_SIZE 0x01000000 #define MX1_CS4_SIZE 0x01000000
#define IMX_CS5_PHYS 0x16000000 #define MX1_CS5_PHYS 0x16000000
#define IMX_CS5_SIZE 0x01000000 #define MX1_CS5_SIZE 0x01000000
/* /*
* Register BASEs, based on OFFSETs * Register BASEs, based on OFFSETs
*/ */
#define AIPI1_BASE_ADDR (0x00000 + IMX_IO_PHYS) #define MX1_AIPI1_BASE_ADDR (0x00000 + MX1_IO_BASE_ADDR)
#define WDT_BASE_ADDR (0x01000 + IMX_IO_PHYS) #define MX1_WDT_BASE_ADDR (0x01000 + MX1_IO_BASE_ADDR)
#define TIM1_BASE_ADDR (0x02000 + IMX_IO_PHYS) #define MX1_TIM1_BASE_ADDR (0x02000 + MX1_IO_BASE_ADDR)
#define TIM2_BASE_ADDR (0x03000 + IMX_IO_PHYS) #define MX1_TIM2_BASE_ADDR (0x03000 + MX1_IO_BASE_ADDR)
#define RTC_BASE_ADDR (0x04000 + IMX_IO_PHYS) #define MX1_RTC_BASE_ADDR (0x04000 + MX1_IO_BASE_ADDR)
#define LCDC_BASE_ADDR (0x05000 + IMX_IO_PHYS) #define MX1_LCDC_BASE_ADDR (0x05000 + MX1_IO_BASE_ADDR)
#define UART1_BASE_ADDR (0x06000 + IMX_IO_PHYS) #define MX1_UART1_BASE_ADDR (0x06000 + MX1_IO_BASE_ADDR)
#define UART2_BASE_ADDR (0x07000 + IMX_IO_PHYS) #define MX1_UART2_BASE_ADDR (0x07000 + MX1_IO_BASE_ADDR)
#define PWM_BASE_ADDR (0x08000 + IMX_IO_PHYS) #define MX1_PWM_BASE_ADDR (0x08000 + MX1_IO_BASE_ADDR)
#define DMA_BASE_ADDR (0x09000 + IMX_IO_PHYS) #define MX1_DMA_BASE_ADDR (0x09000 + MX1_IO_BASE_ADDR)
#define AIPI2_BASE_ADDR (0x10000 + IMX_IO_PHYS) #define MX1_AIPI2_BASE_ADDR (0x10000 + MX1_IO_BASE_ADDR)
#define SIM_BASE_ADDR (0x11000 + IMX_IO_PHYS) #define MX1_SIM_BASE_ADDR (0x11000 + MX1_IO_BASE_ADDR)
#define USBD_BASE_ADDR (0x12000 + IMX_IO_PHYS) #define MX1_USBD_BASE_ADDR (0x12000 + MX1_IO_BASE_ADDR)
#define SPI1_BASE_ADDR (0x13000 + IMX_IO_PHYS) #define MX1_SPI1_BASE_ADDR (0x13000 + MX1_IO_BASE_ADDR)
#define MMC_BASE_ADDR (0x14000 + IMX_IO_PHYS) #define MX1_MMC_BASE_ADDR (0x14000 + MX1_IO_BASE_ADDR)
#define ASP_BASE_ADDR (0x15000 + IMX_IO_PHYS) #define MX1_ASP_BASE_ADDR (0x15000 + MX1_IO_BASE_ADDR)
#define BTA_BASE_ADDR (0x16000 + IMX_IO_PHYS) #define MX1_BTA_BASE_ADDR (0x16000 + MX1_IO_BASE_ADDR)
#define I2C_BASE_ADDR (0x17000 + IMX_IO_PHYS) #define MX1_I2C_BASE_ADDR (0x17000 + MX1_IO_BASE_ADDR)
#define SSI_BASE_ADDR (0x18000 + IMX_IO_PHYS) #define MX1_SSI_BASE_ADDR (0x18000 + MX1_IO_BASE_ADDR)
#define SPI2_BASE_ADDR (0x19000 + IMX_IO_PHYS) #define MX1_SPI2_BASE_ADDR (0x19000 + MX1_IO_BASE_ADDR)
#define MSHC_BASE_ADDR (0x1A000 + IMX_IO_PHYS) #define MX1_MSHC_BASE_ADDR (0x1A000 + MX1_IO_BASE_ADDR)
#define CCM_BASE_ADDR (0x1B000 + IMX_IO_PHYS) #define MX1_CCM_BASE_ADDR (0x1B000 + MX1_IO_BASE_ADDR)
#define SCM_BASE_ADDR (0x1B804 + IMX_IO_PHYS) #define MX1_SCM_BASE_ADDR (0x1B804 + MX1_IO_BASE_ADDR)
#define GPIO_BASE_ADDR (0x1C000 + IMX_IO_PHYS) #define MX1_GPIO_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR)
#define EIM_BASE_ADDR (0x20000 + IMX_IO_PHYS) #define MX1_EIM_BASE_ADDR (0x20000 + MX1_IO_BASE_ADDR)
#define SDRAMC_BASE_ADDR (0x21000 + IMX_IO_PHYS) #define MX1_SDRAMC_BASE_ADDR (0x21000 + MX1_IO_BASE_ADDR)
#define MMA_BASE_ADDR (0x22000 + IMX_IO_PHYS) #define MX1_MMA_BASE_ADDR (0x22000 + MX1_IO_BASE_ADDR)
#define AVIC_BASE_ADDR (0x23000 + IMX_IO_PHYS) #define MX1_AVIC_BASE_ADDR (0x23000 + MX1_IO_BASE_ADDR)
#define CSI_BASE_ADDR (0x24000 + IMX_IO_PHYS) #define MX1_CSI_BASE_ADDR (0x24000 + MX1_IO_BASE_ADDR)
/* macro to get at IO space when running virtually */ /* macro to get at IO space when running virtually */
#define IO_ADDRESS(x) ((x) - IMX_IO_PHYS + IMX_IO_BASE) #define MX1_IO_ADDRESS(x) ( \
IMX_IO_ADDRESS(x, MX1_IO))
/* define macros needed for entry-macro.S */
#define AVIC_IO_ADDRESS(x) IO_ADDRESS(x)
/* fixed interrput numbers */ /* fixed interrput numbers */
#define INT_SOFTINT 0 #define MX1_INT_SOFTINT 0
#define CSI_INT 6 #define MX1_CSI_INT 6
#define DSPA_MAC_INT 7 #define MX1_DSPA_MAC_INT 7
#define DSPA_INT 8 #define MX1_DSPA_INT 8
#define COMP_INT 9 #define MX1_COMP_INT 9
#define MSHC_XINT 10 #define MX1_MSHC_XINT 10
#define GPIO_INT_PORTA 11 #define MX1_GPIO_INT_PORTA 11
#define GPIO_INT_PORTB 12 #define MX1_GPIO_INT_PORTB 12
#define GPIO_INT_PORTC 13 #define MX1_GPIO_INT_PORTC 13
#define LCDC_INT 14 #define MX1_LCDC_INT 14
#define SIM_INT 15 #define MX1_SIM_INT 15
#define SIM_DATA_INT 16 #define MX1_SIM_DATA_INT 16
#define RTC_INT 17 #define MX1_RTC_INT 17
#define RTC_SAMINT 18 #define MX1_RTC_SAMINT 18
#define UART2_MINT_PFERR 19 #define MX1_UART2_MINT_PFERR 19
#define UART2_MINT_RTS 20 #define MX1_UART2_MINT_RTS 20
#define UART2_MINT_DTR 21 #define MX1_UART2_MINT_DTR 21
#define UART2_MINT_UARTC 22 #define MX1_UART2_MINT_UARTC 22
#define UART2_MINT_TX 23 #define MX1_UART2_MINT_TX 23
#define UART2_MINT_RX 24 #define MX1_UART2_MINT_RX 24
#define UART1_MINT_PFERR 25 #define MX1_UART1_MINT_PFERR 25
#define UART1_MINT_RTS 26 #define MX1_UART1_MINT_RTS 26
#define UART1_MINT_DTR 27 #define MX1_UART1_MINT_DTR 27
#define UART1_MINT_UARTC 28 #define MX1_UART1_MINT_UARTC 28
#define UART1_MINT_TX 29 #define MX1_UART1_MINT_TX 29
#define UART1_MINT_RX 30 #define MX1_UART1_MINT_RX 30
#define VOICE_DAC_INT 31 #define MX1_VOICE_DAC_INT 31
#define VOICE_ADC_INT 32 #define MX1_VOICE_ADC_INT 32
#define PEN_DATA_INT 33 #define MX1_PEN_DATA_INT 33
#define PWM_INT 34 #define MX1_PWM_INT 34
#define SDHC_INT 35 #define MX1_SDHC_INT 35
#define I2C_INT 39 #define MX1_I2C_INT 39
#define CSPI_INT 41 #define MX1_CSPI_INT 41
#define SSI_TX_INT 42 #define MX1_SSI_TX_INT 42
#define SSI_TX_ERR_INT 43 #define MX1_SSI_TX_ERR_INT 43
#define SSI_RX_INT 44 #define MX1_SSI_RX_INT 44
#define SSI_RX_ERR_INT 45 #define MX1_SSI_RX_ERR_INT 45
#define TOUCH_INT 46 #define MX1_TOUCH_INT 46
#define USBD_INT0 47 #define MX1_USBD_INT0 47
#define USBD_INT1 48 #define MX1_USBD_INT1 48
#define USBD_INT2 49 #define MX1_USBD_INT2 49
#define USBD_INT3 50 #define MX1_USBD_INT3 50
#define USBD_INT4 51 #define MX1_USBD_INT4 51
#define USBD_INT5 52 #define MX1_USBD_INT5 52
#define USBD_INT6 53 #define MX1_USBD_INT6 53
#define BTSYS_INT 55 #define MX1_BTSYS_INT 55
#define BTTIM_INT 56 #define MX1_BTTIM_INT 56
#define BTWUI_INT 57 #define MX1_BTWUI_INT 57
#define TIM2_INT 58 #define MX1_TIM2_INT 58
#define TIM1_INT 59 #define MX1_TIM1_INT 59
#define DMA_ERR 60 #define MX1_DMA_ERR 60
#define DMA_INT 61 #define MX1_DMA_INT 61
#define GPIO_INT_PORTD 62 #define MX1_GPIO_INT_PORTD 62
#define WDT_INT 63 #define MX1_WDT_INT 63
/* DMA */ /* DMA */
#define DMA_REQ_UART3_T 2 #define MX1_DMA_REQ_UART3_T 2
#define DMA_REQ_UART3_R 3 #define MX1_DMA_REQ_UART3_R 3
#define DMA_REQ_SSI2_T 4 #define MX1_DMA_REQ_SSI2_T 4
#define DMA_REQ_SSI2_R 5 #define MX1_DMA_REQ_SSI2_R 5
#define DMA_REQ_CSI_STAT 6 #define MX1_DMA_REQ_CSI_STAT 6
#define DMA_REQ_CSI_R 7 #define MX1_DMA_REQ_CSI_R 7
#define DMA_REQ_MSHC 8 #define MX1_DMA_REQ_MSHC 8
#define DMA_REQ_DSPA_DCT_DOUT 9 #define MX1_DMA_REQ_DSPA_DCT_DOUT 9
#define DMA_REQ_DSPA_DCT_DIN 10 #define MX1_DMA_REQ_DSPA_DCT_DIN 10
#define DMA_REQ_DSPA_MAC 11 #define MX1_DMA_REQ_DSPA_MAC 11
#define DMA_REQ_EXT 12 #define MX1_DMA_REQ_EXT 12
#define DMA_REQ_SDHC 13 #define MX1_DMA_REQ_SDHC 13
#define DMA_REQ_SPI1_R 14 #define MX1_DMA_REQ_SPI1_R 14
#define DMA_REQ_SPI1_T 15 #define MX1_DMA_REQ_SPI1_T 15
#define DMA_REQ_SSI_T 16 #define MX1_DMA_REQ_SSI_T 16
#define DMA_REQ_SSI_R 17 #define MX1_DMA_REQ_SSI_R 17
#define DMA_REQ_ASP_DAC 18 #define MX1_DMA_REQ_ASP_DAC 18
#define DMA_REQ_ASP_ADC 19 #define MX1_DMA_REQ_ASP_ADC 19
#define DMA_REQ_USP_EP(x) (20 + (x)) #define MX1_DMA_REQ_USP_EP(x) (20 + (x))
#define DMA_REQ_SPI2_R 26 #define MX1_DMA_REQ_SPI2_R 26
#define DMA_REQ_SPI2_T 27 #define MX1_DMA_REQ_SPI2_T 27
#define DMA_REQ_UART2_T 28 #define MX1_DMA_REQ_UART2_T 28
#define DMA_REQ_UART2_R 29 #define MX1_DMA_REQ_UART2_R 29
#define DMA_REQ_UART1_T 30 #define MX1_DMA_REQ_UART1_T 30
#define DMA_REQ_UART1_R 31 #define MX1_DMA_REQ_UART1_R 31
#endif /* __ASM_ARCH_MXC_MX1_H__ */ /*
* This doesn't depend on IMX_NEEDS_DEPRECATED_SYMBOLS
* to not break drivers/usb/gadget/imx_udc. Should go
* away after this driver uses the new name.
*/
#define USBD_INT0 MX1_USBD_INT0
#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
/* these should go away */
#define IMX_IO_PHYS MX1_IO_BASE_ADDR
#define IMX_IO_SIZE MX1_IO_SIZE
#define IMX_IO_BASE MX1_IO_BASE_ADDR_VIRT
#define IMX_CS0_PHYS MX1_CS0_PHYS
#define IMX_CS0_SIZE MX1_CS0_SIZE
#define IMX_CS1_PHYS MX1_CS1_PHYS
#define IMX_CS1_SIZE MX1_CS1_SIZE
#define IMX_CS2_PHYS MX1_CS2_PHYS
#define IMX_CS2_SIZE MX1_CS2_SIZE
#define IMX_CS3_PHYS MX1_CS3_PHYS
#define IMX_CS3_SIZE MX1_CS3_SIZE
#define IMX_CS4_PHYS MX1_CS4_PHYS
#define IMX_CS4_SIZE MX1_CS4_SIZE
#define IMX_CS5_PHYS MX1_CS5_PHYS
#define IMX_CS5_SIZE MX1_CS5_SIZE
#define AIPI1_BASE_ADDR MX1_AIPI1_BASE_ADDR
#define WDT_BASE_ADDR MX1_WDT_BASE_ADDR
#define TIM1_BASE_ADDR MX1_TIM1_BASE_ADDR
#define TIM2_BASE_ADDR MX1_TIM2_BASE_ADDR
#define RTC_BASE_ADDR MX1_RTC_BASE_ADDR
#define LCDC_BASE_ADDR MX1_LCDC_BASE_ADDR
#define UART1_BASE_ADDR MX1_UART1_BASE_ADDR
#define UART2_BASE_ADDR MX1_UART2_BASE_ADDR
#define PWM_BASE_ADDR MX1_PWM_BASE_ADDR
#define DMA_BASE_ADDR MX1_DMA_BASE_ADDR
#define AIPI2_BASE_ADDR MX1_AIPI2_BASE_ADDR
#define SIM_BASE_ADDR MX1_SIM_BASE_ADDR
#define USBD_BASE_ADDR MX1_USBD_BASE_ADDR
#define SPI1_BASE_ADDR MX1_SPI1_BASE_ADDR
#define MMC_BASE_ADDR MX1_MMC_BASE_ADDR
#define ASP_BASE_ADDR MX1_ASP_BASE_ADDR
#define BTA_BASE_ADDR MX1_BTA_BASE_ADDR
#define I2C_BASE_ADDR MX1_I2C_BASE_ADDR
#define SSI_BASE_ADDR MX1_SSI_BASE_ADDR
#define SPI2_BASE_ADDR MX1_SPI2_BASE_ADDR
#define MSHC_BASE_ADDR MX1_MSHC_BASE_ADDR
#define CCM_BASE_ADDR MX1_CCM_BASE_ADDR
#define SCM_BASE_ADDR MX1_SCM_BASE_ADDR
#define GPIO_BASE_ADDR MX1_GPIO_BASE_ADDR
#define EIM_BASE_ADDR MX1_EIM_BASE_ADDR
#define SDRAMC_BASE_ADDR MX1_SDRAMC_BASE_ADDR
#define MMA_BASE_ADDR MX1_MMA_BASE_ADDR
#define AVIC_BASE_ADDR MX1_AVIC_BASE_ADDR
#define CSI_BASE_ADDR MX1_CSI_BASE_ADDR
#define IO_ADDRESS(x) MX1_IO_ADDRESS(x)
#define AVIC_IO_ADDRESS(x) IO_ADDRESS(x)
#define INT_SOFTINT MX1_INT_SOFTINT
#define CSI_INT MX1_CSI_INT
#define DSPA_MAC_INT MX1_DSPA_MAC_INT
#define DSPA_INT MX1_DSPA_INT
#define COMP_INT MX1_COMP_INT
#define MSHC_XINT MX1_MSHC_XINT
#define GPIO_INT_PORTA MX1_GPIO_INT_PORTA
#define GPIO_INT_PORTB MX1_GPIO_INT_PORTB
#define GPIO_INT_PORTC MX1_GPIO_INT_PORTC
#define LCDC_INT MX1_LCDC_INT
#define SIM_INT MX1_SIM_INT
#define SIM_DATA_INT MX1_SIM_DATA_INT
#define RTC_INT MX1_RTC_INT
#define RTC_SAMINT MX1_RTC_SAMINT
#define UART2_MINT_PFERR MX1_UART2_MINT_PFERR
#define UART2_MINT_RTS MX1_UART2_MINT_RTS
#define UART2_MINT_DTR MX1_UART2_MINT_DTR
#define UART2_MINT_UARTC MX1_UART2_MINT_UARTC
#define UART2_MINT_TX MX1_UART2_MINT_TX
#define UART2_MINT_RX MX1_UART2_MINT_RX
#define UART1_MINT_PFERR MX1_UART1_MINT_PFERR
#define UART1_MINT_RTS MX1_UART1_MINT_RTS
#define UART1_MINT_DTR MX1_UART1_MINT_DTR
#define UART1_MINT_UARTC MX1_UART1_MINT_UARTC
#define UART1_MINT_TX MX1_UART1_MINT_TX
#define UART1_MINT_RX MX1_UART1_MINT_RX
#define VOICE_DAC_INT MX1_VOICE_DAC_INT
#define VOICE_ADC_INT MX1_VOICE_ADC_INT
#define PEN_DATA_INT MX1_PEN_DATA_INT
#define PWM_INT MX1_PWM_INT
#define SDHC_INT MX1_SDHC_INT
#define I2C_INT MX1_I2C_INT
#define CSPI_INT MX1_CSPI_INT
#define SSI_TX_INT MX1_SSI_TX_INT
#define SSI_TX_ERR_INT MX1_SSI_TX_ERR_INT
#define SSI_RX_INT MX1_SSI_RX_INT
#define SSI_RX_ERR_INT MX1_SSI_RX_ERR_INT
#define TOUCH_INT MX1_TOUCH_INT
#define USBD_INT1 MX1_USBD_INT1
#define USBD_INT2 MX1_USBD_INT2
#define USBD_INT3 MX1_USBD_INT3
#define USBD_INT4 MX1_USBD_INT4
#define USBD_INT5 MX1_USBD_INT5
#define USBD_INT6 MX1_USBD_INT6
#define BTSYS_INT MX1_BTSYS_INT
#define BTTIM_INT MX1_BTTIM_INT
#define BTWUI_INT MX1_BTWUI_INT
#define TIM2_INT MX1_TIM2_INT
#define TIM1_INT MX1_TIM1_INT
#define DMA_ERR MX1_DMA_ERR
#define DMA_INT MX1_DMA_INT
#define GPIO_INT_PORTD MX1_GPIO_INT_PORTD
#define WDT_INT MX1_WDT_INT
#define DMA_REQ_UART3_T MX1_DMA_REQ_UART3_T
#define DMA_REQ_UART3_R MX1_DMA_REQ_UART3_R
#define DMA_REQ_SSI2_T MX1_DMA_REQ_SSI2_T
#define DMA_REQ_SSI2_R MX1_DMA_REQ_SSI2_R
#define DMA_REQ_CSI_STAT MX1_DMA_REQ_CSI_STAT
#define DMA_REQ_CSI_R MX1_DMA_REQ_CSI_R
#define DMA_REQ_MSHC MX1_DMA_REQ_MSHC
#define DMA_REQ_DSPA_DCT_DOUT MX1_DMA_REQ_DSPA_DCT_DOUT
#define DMA_REQ_DSPA_DCT_DIN MX1_DMA_REQ_DSPA_DCT_DIN
#define DMA_REQ_DSPA_MAC MX1_DMA_REQ_DSPA_MAC
#define DMA_REQ_EXT MX1_DMA_REQ_EXT
#define DMA_REQ_SDHC MX1_DMA_REQ_SDHC
#define DMA_REQ_SPI1_R MX1_DMA_REQ_SPI1_R
#define DMA_REQ_SPI1_T MX1_DMA_REQ_SPI1_T
#define DMA_REQ_SSI_T MX1_DMA_REQ_SSI_T
#define DMA_REQ_SSI_R MX1_DMA_REQ_SSI_R
#define DMA_REQ_ASP_DAC MX1_DMA_REQ_ASP_DAC
#define DMA_REQ_ASP_ADC MX1_DMA_REQ_ASP_ADC
#define DMA_REQ_USP_EP(x) MX1_DMA_REQ_USP_EP(x)
#define DMA_REQ_SPI2_R MX1_DMA_REQ_SPI2_R
#define DMA_REQ_SPI2_T MX1_DMA_REQ_SPI2_T
#define DMA_REQ_UART2_T MX1_DMA_REQ_UART2_T
#define DMA_REQ_UART2_R MX1_DMA_REQ_UART2_R
#define DMA_REQ_UART1_T MX1_DMA_REQ_UART1_T
#define DMA_REQ_UART1_R MX1_DMA_REQ_UART1_R
#endif /* ifdef IMX_NEEDS_DEPRECATED_SYMBOLS */
#endif /* ifndef __MACH_MX1_H__ */
arch/arm/plat-mxc/include/mach/mx21.h
浏览文件 @ b93a4afc
...@@ -22,8 +22,8 @@ ...@@ -22,8 +22,8 @@
* MA 02110-1301, USA. * MA 02110-1301, USA.
*/ */
#ifndef __ASM_ARCH_MXC_MX21_H__ #ifndef __MACH_MX21_H__
#define __ASM_ARCH_MXC_MX21_H__ #define __MACH_MX21_H__
#define MX21_AIPI_BASE_ADDR 0x10000000 #define MX21_AIPI_BASE_ADDR 0x10000000
#define MX21_AIPI_BASE_ADDR_VIRT 0xf4000000 #define MX21_AIPI_BASE_ADDR_VIRT 0xf4000000
...@@ -92,6 +92,11 @@ ...@@ -92,6 +92,11 @@
#define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */ #define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */
#define MX21_IO_ADDRESS(x) ( \
IMX_IO_ADDRESS(x, MX21_AIPI) ?: \
IMX_IO_ADDRESS(x, MX21_SAHB1) ?: \
IMX_IO_ADDRESS(x, MX21_X_MEMC))
/* fixed interrupt numbers */ /* fixed interrupt numbers */
#define MX21_INT_CSPI3 6 #define MX21_INT_CSPI3 6
#define MX21_INT_GPIO 8 #define MX21_INT_GPIO 8
...@@ -179,6 +184,7 @@ ...@@ -179,6 +184,7 @@
#define MX21_DMA_REQ_CSI_STAT 30 #define MX21_DMA_REQ_CSI_STAT 30
#define MX21_DMA_REQ_CSI_RX 31 #define MX21_DMA_REQ_CSI_RX 31
#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
/* these should go away */ /* these should go away */
#define SDRAM_BASE_ADDR MX21_SDRAM_BASE_ADDR #define SDRAM_BASE_ADDR MX21_SDRAM_BASE_ADDR
#define CSD1_BASE_ADDR MX21_CSD1_BASE_ADDR #define CSD1_BASE_ADDR MX21_CSD1_BASE_ADDR
...@@ -211,5 +217,6 @@ ...@@ -211,5 +217,6 @@
#define DMA_REQ_FIRI_RX MX21_DMA_REQ_FIRI_RX #define DMA_REQ_FIRI_RX MX21_DMA_REQ_FIRI_RX
#define DMA_REQ_BMI_TX MX21_DMA_REQ_BMI_TX #define DMA_REQ_BMI_TX MX21_DMA_REQ_BMI_TX
#define DMA_REQ_BMI_RX MX21_DMA_REQ_BMI_RX #define DMA_REQ_BMI_RX MX21_DMA_REQ_BMI_RX
#endif
#endif /* __ASM_ARCH_MXC_MX21_H__ */ #endif /* ifndef __MACH_MX21_H__ */
arch/arm/plat-mxc/include/mach/mx25.h
浏览文件 @ b93a4afc
...@@ -22,27 +22,27 @@ ...@@ -22,27 +22,27 @@
#define MX25_GPIO3_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xa4000) #define MX25_GPIO3_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xa4000)
#define MX25_GPIO4_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0x9c000) #define MX25_GPIO4_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0x9c000)
#define MX25_AIPS1_IO_ADDRESS(x) \ #define MX25_IO_ADDRESS(x) ( \
(((x) - MX25_AIPS1_BASE_ADDR) + MX25_AIPS1_BASE_ADDR_VIRT) IMX_IO_ADDRESS(x, MX25_AIPS1) ?: \
#define MX25_AIPS2_IO_ADDRESS(x) \ IMX_IO_ADDRESS(x, MX25_AIPS2) ?: \
(((x) - MX25_AIPS2_BASE_ADDR) + MX25_AIPS2_BASE_ADDR_VIRT) IMX_IO_ADDRESS(x, MX25_AVIC))
#define MX25_AVIC_IO_ADDRESS(x) \
(((x) - MX25_AVIC_BASE_ADDR) + MX25_AVIC_BASE_ADDR_VIRT)
#define __in_range(addr, name) ((addr) >= name##_BASE_ADDR && (addr) < name##_BASE_ADDR + name##_SIZE) #define MX25_UART1_BASE_ADDR 0x43f90000
#define MX25_UART2_BASE_ADDR 0x43f94000
#define MX25_IO_ADDRESS(x) \
(void __force __iomem *) \
(__in_range(x, MX25_AIPS1) ? MX25_AIPS1_IO_ADDRESS(x) : \
__in_range(x, MX25_AIPS2) ? MX25_AIPS2_IO_ADDRESS(x) : \
__in_range(x, MX25_AVIC) ? MX25_AVIC_IO_ADDRESS(x) : \
0xDEADBEEF)
#define UART1_BASE_ADDR 0x43f90000
#define UART2_BASE_ADDR 0x43f94000
#define MX25_FEC_BASE_ADDR 0x50038000 #define MX25_FEC_BASE_ADDR 0x50038000
#define MX25_NFC_BASE_ADDR 0xbb000000
#define MX25_DRYICE_BASE_ADDR 0x53ffc000
#define MX25_LCDC_BASE_ADDR 0x53fbc000
#define MX25_INT_DRYICE 25
#define MX25_INT_FEC 57 #define MX25_INT_FEC 57
#define MX25_INT_NANDFC 33
#define MX25_INT_LCDC 39
#if defined(IMX_NEEDS_DEPRECATED_SYMBOLS)
#define UART1_BASE_ADDR MX25_UART1_BASE_ADDR
#define UART2_BASE_ADDR MX25_UART2_BASE_ADDR
#endif
#endif /* __MACH_MX25_H__ */ #endif /* ifndef __MACH_MX25_H__ */
arch/arm/plat-mxc/include/mach/mx27.h
浏览文件 @ b93a4afc
...@@ -21,8 +21,12 @@ ...@@ -21,8 +21,12 @@
* MA 02110-1301, USA. * MA 02110-1301, USA.
*/ */
#ifndef __ASM_ARCH_MXC_MX27_H__ #ifndef __MACH_MX27_H__
#define __ASM_ARCH_MXC_MX27_H__ #define __MACH_MX27_H__
#ifndef __ASSEMBLER__
#include <linux/io.h>
#endif
#define MX27_AIPI_BASE_ADDR 0x10000000 #define MX27_AIPI_BASE_ADDR 0x10000000
#define MX27_AIPI_BASE_ADDR_VIRT 0xf4000000 #define MX27_AIPI_BASE_ADDR_VIRT 0xf4000000
...@@ -109,11 +113,31 @@ ...@@ -109,11 +113,31 @@
#define MX27_M3IF_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x3000) #define MX27_M3IF_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x3000)
#define MX27_PCMCIA_CTL_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x4000) #define MX27_PCMCIA_CTL_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x4000)
#define MX27_WEIM_CSCRx_BASE_ADDR(cs) (MX27_WEIM_BASE_ADDR + (cs) * 0x10)
#define MX27_WEIM_CSCRxU(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs))
#define MX27_WEIM_CSCRxL(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x4)
#define MX27_WEIM_CSCRxA(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x8)
#define MX27_PCMCIA_MEM_BASE_ADDR 0xdc000000 #define MX27_PCMCIA_MEM_BASE_ADDR 0xdc000000
/* IRAM */ /* IRAM */
#define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */ #define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */
#define MX27_IO_ADDRESS(x) ( \
IMX_IO_ADDRESS(x, MX27_AIPI) ?: \
IMX_IO_ADDRESS(x, MX27_SAHB1) ?: \
IMX_IO_ADDRESS(x, MX27_X_MEMC))
#ifndef __ASSEMBLER__
static inline void mx27_setup_weimcs(size_t cs,
unsigned upper, unsigned lower, unsigned addional)
{
__raw_writel(upper, MX27_IO_ADDRESS(MX27_WEIM_CSCRxU(cs)));
__raw_writel(lower, MX27_IO_ADDRESS(MX27_WEIM_CSCRxL(cs)));
__raw_writel(addional, MX27_IO_ADDRESS(MX27_WEIM_CSCRxA(cs)));
}
#endif
/* fixed interrupt numbers */ /* fixed interrupt numbers */
#define MX27_INT_I2C2 1 #define MX27_INT_I2C2 1
#define MX27_INT_GPT6 2 #define MX27_INT_GPT6 2
...@@ -225,6 +249,7 @@ ...@@ -225,6 +249,7 @@
extern int mx27_revision(void); extern int mx27_revision(void);
#endif #endif
#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
/* these should go away */ /* these should go away */
#define MSHC_BASE_ADDR MX27_MSHC_BASE_ADDR #define MSHC_BASE_ADDR MX27_MSHC_BASE_ADDR
#define GPT5_BASE_ADDR MX27_GPT5_BASE_ADDR #define GPT5_BASE_ADDR MX27_GPT5_BASE_ADDR
...@@ -292,5 +317,6 @@ extern int mx27_revision(void); ...@@ -292,5 +317,6 @@ extern int mx27_revision(void);
#define DMA_REQ_UART6_RX MX27_DMA_REQ_UART6_RX #define DMA_REQ_UART6_RX MX27_DMA_REQ_UART6_RX
#define DMA_REQ_SDHC3 MX27_DMA_REQ_SDHC3 #define DMA_REQ_SDHC3 MX27_DMA_REQ_SDHC3
#define DMA_REQ_NFC MX27_DMA_REQ_NFC #define DMA_REQ_NFC MX27_DMA_REQ_NFC
#endif
#endif /* __ASM_ARCH_MXC_MX27_H__ */ #endif /* ifndef __MACH_MX27_H__ */
arch/arm/plat-mxc/include/mach/mx2x.h
浏览文件 @ b93a4afc
...@@ -20,8 +20,8 @@ ...@@ -20,8 +20,8 @@
* MA 02110-1301, USA. * MA 02110-1301, USA.
*/ */
#ifndef __ASM_ARCH_MXC_MX2x_H__ #ifndef __MACH_MX2x_H__
#define __ASM_ARCH_MXC_MX2x_H__ #define __MACH_MX2x_H__
/* The following addresses are common between i.MX21 and i.MX27 */ /* The following addresses are common between i.MX21 and i.MX27 */
...@@ -176,6 +176,7 @@ ...@@ -176,6 +176,7 @@
#define MX2x_DMA_REQ_CSI_STAT 30 #define MX2x_DMA_REQ_CSI_STAT 30
#define MX2x_DMA_REQ_CSI_RX 31 #define MX2x_DMA_REQ_CSI_RX 31
#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
/* these should go away */ /* these should go away */
#define AIPI_BASE_ADDR MX2x_AIPI_BASE_ADDR #define AIPI_BASE_ADDR MX2x_AIPI_BASE_ADDR
#define AIPI_BASE_ADDR_VIRT MX2x_AIPI_BASE_ADDR_VIRT #define AIPI_BASE_ADDR_VIRT MX2x_AIPI_BASE_ADDR_VIRT
...@@ -287,5 +288,6 @@ ...@@ -287,5 +288,6 @@
#define DMA_REQ_UART1_TX MX2x_DMA_REQ_UART1_TX #define DMA_REQ_UART1_TX MX2x_DMA_REQ_UART1_TX
#define DMA_REQ_CSI_STAT MX2x_DMA_REQ_CSI_STAT #define DMA_REQ_CSI_STAT MX2x_DMA_REQ_CSI_STAT
#define DMA_REQ_CSI_RX MX2x_DMA_REQ_CSI_RX #define DMA_REQ_CSI_RX MX2x_DMA_REQ_CSI_RX
#endif
#endif /* __ASM_ARCH_MXC_MX2x_H__ */ #endif /* ifndef __MACH_MX2x_H__ */
arch/arm/plat-mxc/include/mach/mx31.h
浏览文件 @ b93a4afc
#ifndef __MACH_MX31_H__
#define __MACH_MX31_H__
#ifndef __ASSEMBLER__
#include <linux/io.h>
#endif
/* /*
* IRAM * IRAM
*/ */
...@@ -107,8 +114,30 @@ ...@@ -107,8 +114,30 @@
#define MX31_EMI_CTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x4000) #define MX31_EMI_CTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x4000)
#define MX31_PCMCIA_CTL_BASE_ADDR MX31_EMI_CTL_BASE_ADDR #define MX31_PCMCIA_CTL_BASE_ADDR MX31_EMI_CTL_BASE_ADDR
#define MX31_WEIM_CSCRx_BASE_ADDR(cs) (MX31_WEIM_BASE_ADDR + (cs) * 0x10)
#define MX31_WEIM_CSCRxU(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs))
#define MX31_WEIM_CSCRxL(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x4)
#define MX31_WEIM_CSCRxA(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x8)
#define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000 #define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000
#define MX31_IO_ADDRESS(x) ( \
IMX_IO_ADDRESS(x, MX31_AIPS1) ?: \
IMX_IO_ADDRESS(x, MX31_AIPS2) ?: \
IMX_IO_ADDRESS(x, MX31_AVIC) ?: \
IMX_IO_ADDRESS(x, MX31_X_MEMC) ?: \
IMX_IO_ADDRESS(x, MX31_SPBA0))
#ifndef __ASSEMBLER__
static inline void mx31_setup_weimcs(size_t cs,
unsigned upper, unsigned lower, unsigned addional)
{
__raw_writel(upper, MX31_IO_ADDRESS(MX31_WEIM_CSCRxU(cs)));
__raw_writel(lower, MX31_IO_ADDRESS(MX31_WEIM_CSCRxL(cs)));
__raw_writel(addional, MX31_IO_ADDRESS(MX31_WEIM_CSCRxA(cs)));
}
#endif
#define MX31_INT_I2C3 3 #define MX31_INT_I2C3 3
#define MX31_INT_I2C2 4 #define MX31_INT_I2C2 4
#define MX31_INT_MPEG4_ENCODER 5 #define MX31_INT_MPEG4_ENCODER 5
...@@ -186,6 +215,7 @@ ...@@ -186,6 +215,7 @@
#define MX31_SYSTEM_REV_MIN MX31_CHIP_REV_1_0 #define MX31_SYSTEM_REV_MIN MX31_CHIP_REV_1_0
#define MX31_SYSTEM_REV_NUM 3 #define MX31_SYSTEM_REV_NUM 3
#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
/* these should go away */ /* these should go away */
#define ATA_BASE_ADDR MX31_ATA_BASE_ADDR #define ATA_BASE_ADDR MX31_ATA_BASE_ADDR
#define UART4_BASE_ADDR MX31_UART4_BASE_ADDR #define UART4_BASE_ADDR MX31_UART4_BASE_ADDR
...@@ -216,3 +246,6 @@ ...@@ -216,3 +246,6 @@
#define MXC_INT_UART5 MX31_INT_UART5 #define MXC_INT_UART5 MX31_INT_UART5
#define MXC_INT_CCM MX31_INT_CCM #define MXC_INT_CCM MX31_INT_CCM
#define MXC_INT_PCMCIA MX31_INT_PCMCIA #define MXC_INT_PCMCIA MX31_INT_PCMCIA
#endif
#endif /* ifndef __MACH_MX31_H__ */
arch/arm/plat-mxc/include/mach/mx35.h
浏览文件 @ b93a4afc
#ifndef __MACH_MX35_H__
#define __MACH_MX35_H__
/* /*
* IRAM * IRAM
*/ */
...@@ -104,6 +106,13 @@ ...@@ -104,6 +106,13 @@
#define MX35_NFC_BASE_ADDR 0xbb000000 #define MX35_NFC_BASE_ADDR 0xbb000000
#define MX35_PCMCIA_MEM_BASE_ADDR 0xbc000000 #define MX35_PCMCIA_MEM_BASE_ADDR 0xbc000000
#define MX35_IO_ADDRESS(x) ( \
IMX_IO_ADDRESS(x, MX35_AIPS1) ?: \
IMX_IO_ADDRESS(x, MX35_AIPS2) ?: \
IMX_IO_ADDRESS(x, MX35_AVIC) ?: \
IMX_IO_ADDRESS(x, MX35_X_MEMC) ?: \
IMX_IO_ADDRESS(x, MX35_SPBA0))
/* /*
* Interrupt numbers * Interrupt numbers
*/ */
...@@ -180,6 +189,7 @@ ...@@ -180,6 +189,7 @@
#define MX35_SYSTEM_REV_MIN MX35_CHIP_REV_1_0 #define MX35_SYSTEM_REV_MIN MX35_CHIP_REV_1_0
#define MX35_SYSTEM_REV_NUM 3 #define MX35_SYSTEM_REV_NUM 3
#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
/* these should go away */ /* these should go away */
#define MXC_FEC_BASE_ADDR MX35_FEC_BASE_ADDR #define MXC_FEC_BASE_ADDR MX35_FEC_BASE_ADDR
#define MXC_INT_OWIRE MX35_INT_OWIRE #define MXC_INT_OWIRE MX35_INT_OWIRE
...@@ -195,3 +205,6 @@ ...@@ -195,3 +205,6 @@
#define MXC_INT_MLB MX35_INT_MLB #define MXC_INT_MLB MX35_INT_MLB
#define MXC_INT_SPDIF MX35_INT_SPDIF #define MXC_INT_SPDIF MX35_INT_SPDIF
#define MXC_INT_FEC MX35_INT_FEC #define MXC_INT_FEC MX35_INT_FEC
#endif
#endif /* ifndef __MACH_MX35_H__ */
arch/arm/plat-mxc/include/mach/mx3x.h
浏览文件 @ b93a4afc
...@@ -8,8 +8,8 @@ ...@@ -8,8 +8,8 @@
* published by the Free Software Foundation. * published by the Free Software Foundation.
*/ */
#ifndef __ASM_ARCH_MXC_MX31_H__ #ifndef __MACH_MX3x_H__
#define __ASM_ARCH_MXC_MX31_H__ #define __MACH_MX3x_H__
/* /*
* MX31 memory map: * MX31 memory map:
...@@ -269,6 +269,7 @@ static inline int mx31_revision(void) ...@@ -269,6 +269,7 @@ static inline int mx31_revision(void)
} }
#endif #endif
#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
/* these should go away */ /* these should go away */
#define L2CC_BASE_ADDR MX3x_L2CC_BASE_ADDR #define L2CC_BASE_ADDR MX3x_L2CC_BASE_ADDR
#define L2CC_SIZE MX3x_L2CC_SIZE #define L2CC_SIZE MX3x_L2CC_SIZE
...@@ -401,5 +402,6 @@ static inline int mx31_revision(void) ...@@ -401,5 +402,6 @@ static inline int mx31_revision(void)
#define CHIP_REV_3_2 MX3x_CHIP_REV_3_2 #define CHIP_REV_3_2 MX3x_CHIP_REV_3_2
#define SYSTEM_REV_MIN MX3x_SYSTEM_REV_MIN #define SYSTEM_REV_MIN MX3x_SYSTEM_REV_MIN
#define SYSTEM_REV_NUM MX3x_SYSTEM_REV_NUM #define SYSTEM_REV_NUM MX3x_SYSTEM_REV_NUM
#endif
#endif /* __ASM_ARCH_MXC_MX31_H__ */ #endif /* ifndef __MACH_MX3x_H__ */
arch/arm/plat-mxc/include/mach/mx51.h 0 → 100644
浏览文件 @ b93a4afc
#ifndef __ASM_ARCH_MXC_MX51_H__
#define __ASM_ARCH_MXC_MX51_H__
/*
* MX51 memory map:
*
*
* Virt Phys Size What
* ---------------------------------------------------------------------------
* FA3E0000 1FFE0000 128K IRAM (SCCv2 RAM)
* 30000000 256M GPU
* 40000000 512M IPU
* FA200000 60000000 1M DEBUG
* FB100000 70000000 1M SPBA 0
* FB000000 73F00000 1M AIPS 1
* FB200000 83F00000 1M AIPS 2
* FA100000 8FFFC000 16K TZIC (interrupt controller)
* 90000000 256M CSD0 SDRAM/DDR
* A0000000 256M CSD1 SDRAM/DDR
* B0000000 128M CS0 Flash
* B8000000 128M CS1 Flash
* C0000000 128M CS2 Flash
* C8000000 64M CS3 Flash
* CC000000 32M CS4 SRAM
* CE000000 32M CS5 SRAM
* F9000000 CFFF0000 64K NFC (NAND Flash AXI)
*
*/
/*
* IRAM
*/
#define MX51_IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */
#define MX51_IRAM_BASE_ADDR_VIRT 0xFA3E0000
#define MX51_IRAM_PARTITIONS 16
#define MX51_IRAM_PARTITIONS_TO1 12
#define MX51_IRAM_SIZE (MX51_IRAM_PARTITIONS * SZ_8K) /* 128KB */
/*
* NFC
*/
#define MX51_NFC_AXI_BASE_ADDR 0xCFFF0000 /* NAND flash AXI */
#define MX51_NFC_AXI_BASE_ADDR_VIRT 0xF9000000
#define MX51_NFC_AXI_SIZE SZ_64K
/*
* Graphics Memory of GPU
*/
#define MX51_GPU_BASE_ADDR 0x20000000
#define MX51_GPU2D_BASE_ADDR 0xD0000000
#define MX51_TZIC_BASE_ADDR 0x8FFFC000
#define MX51_TZIC_BASE_ADDR_VIRT 0xFA100000
#define MX51_TZIC_SIZE SZ_16K
#define MX51_DEBUG_BASE_ADDR 0x60000000
#define MX51_DEBUG_BASE_ADDR_VIRT 0xFA200000
#define MX51_DEBUG_SIZE SZ_1M
#define MX51_ETB_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00001000)
#define MX51_ETM_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00002000)
#define MX51_TPIU_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00003000)
#define MX51_CTI0_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00004000)
#define MX51_CTI1_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00005000)
#define MX51_CTI2_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00006000)
#define MX51_CTI3_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00007000)
#define MX51_CORTEX_DBG_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00008000)
/*
* SPBA global module enabled #0
*/
#define MX51_SPBA0_BASE_ADDR 0x70000000
#define MX51_SPBA0_BASE_ADDR_VIRT 0xFB100000
#define MX51_SPBA0_SIZE SZ_1M
#define MX51_MMC_SDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00004000)
#define MX51_MMC_SDHC2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00008000)
#define MX51_UART3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0000C000)
#define MX51_CSPI1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00010000)
#define MX51_SSI2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00014000)
#define MX51_MMC_SDHC3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00020000)
#define MX51_MMC_SDHC4_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00024000)
#define MX51_SPDIF_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00028000)
#define MX51_ATA_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00030000)
#define MX51_SLIM_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00034000)
#define MX51_HSI2C_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00038000)
#define MX51_SPBA_CTRL_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0003C000)
/*
* defines for SPBA modules
*/
#define MX51_SPBA_SDHC1 0x04
#define MX51_SPBA_SDHC2 0x08
#define MX51_SPBA_UART3 0x0C
#define MX51_SPBA_CSPI1 0x10
#define MX51_SPBA_SSI2 0x14
#define MX51_SPBA_SDHC3 0x20
#define MX51_SPBA_SDHC4 0x24
#define MX51_SPBA_SPDIF 0x28
#define MX51_SPBA_ATA 0x30
#define MX51_SPBA_SLIM 0x34
#define MX51_SPBA_HSI2C 0x38
#define MX51_SPBA_CTRL 0x3C
/*
* AIPS 1
*/
#define MX51_AIPS1_BASE_ADDR 0x73F00000
#define MX51_AIPS1_BASE_ADDR_VIRT 0xFB000000
#define MX51_AIPS1_SIZE SZ_1M
#define MX51_OTG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00080000)
#define MX51_GPIO1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00084000)
#define MX51_GPIO2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00088000)
#define MX51_GPIO3_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x0008C000)
#define MX51_GPIO4_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00090000)
#define MX51_KPP_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00094000)
#define MX51_WDOG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00098000)
#define MX51_WDOG2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x0009C000)
#define MX51_GPT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A0000)
#define MX51_SRTC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A4000)
#define MX51_IOMUXC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A8000)
#define MX51_EPIT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000AC000)
#define MX51_EPIT2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B0000)
#define MX51_PWM1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B4000)
#define MX51_PWM2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B8000)
#define MX51_UART1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000BC000)
#define MX51_UART2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000C0000)
#define MX51_SRC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D0000)
#define MX51_CCM_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D4000)
#define MX51_GPC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D8000)
/*
* Defines for modules using static and dynamic DMA channels
*/
#define MX51_MXC_DMA_CHANNEL_IRAM 30
#define MX51_MXC_DMA_CHANNEL_SPDIF_TX MXC_DMA_DYNAMIC_CHANNEL
#define MX51_MXC_DMA_CHANNEL_UART1_RX MXC_DMA_DYNAMIC_CHANNEL
#define MX51_MXC_DMA_CHANNEL_UART1_TX MXC_DMA_DYNAMIC_CHANNEL
#define MX51_MXC_DMA_CHANNEL_UART2_RX MXC_DMA_DYNAMIC_CHANNEL
#define MX51_MXC_DMA_CHANNEL_UART2_TX MXC_DMA_DYNAMIC_CHANNEL
#define MX51_MXC_DMA_CHANNEL_UART3_RX MXC_DMA_DYNAMIC_CHANNEL
#define MX51_MXC_DMA_CHANNEL_UART3_TX MXC_DMA_DYNAMIC_CHANNEL
#define MX51_MXC_DMA_CHANNEL_MMC1 MXC_DMA_DYNAMIC_CHANNEL
#define MX51_MXC_DMA_CHANNEL_MMC2 MXC_DMA_DYNAMIC_CHANNEL
#define MX51_MXC_DMA_CHANNEL_SSI1_RX MXC_DMA_DYNAMIC_CHANNEL
#define MX51_MXC_DMA_CHANNEL_SSI1_TX MXC_DMA_DYNAMIC_CHANNEL
#define MX51_MXC_DMA_CHANNEL_SSI2_RX MXC_DMA_DYNAMIC_CHANNEL
#ifdef CONFIG_SDMA_IRAM
#define MX51_MXC_DMA_CHANNEL_SSI2_TX (MX51_MXC_DMA_CHANNEL_IRAM + 1)
#else /*CONFIG_SDMA_IRAM */
#define MX51_MXC_DMA_CHANNEL_SSI2_TX MXC_DMA_DYNAMIC_CHANNEL
#endif /*CONFIG_SDMA_IRAM */
#define MX51_MXC_DMA_CHANNEL_CSPI1_RX MXC_DMA_DYNAMIC_CHANNEL
#define MX51_MXC_DMA_CHANNEL_CSPI1_TX MXC_DMA_DYNAMIC_CHANNEL
#define MX51_MXC_DMA_CHANNEL_CSPI2_RX MXC_DMA_DYNAMIC_CHANNEL
#define MX51_MXC_DMA_CHANNEL_CSPI2_TX MXC_DMA_DYNAMIC_CHANNEL
#define MX51_MXC_DMA_CHANNEL_CSPI3_RX MXC_DMA_DYNAMIC_CHANNEL
#define MX51_MXC_DMA_CHANNEL_CSPI3_TX MXC_DMA_DYNAMIC_CHANNEL
#define MX51_MXC_DMA_CHANNEL_ATA_RX MXC_DMA_DYNAMIC_CHANNEL
#define MX51_MXC_DMA_CHANNEL_ATA_TX MXC_DMA_DYNAMIC_CHANNEL
#define MX51_MXC_DMA_CHANNEL_MEMORY MXC_DMA_DYNAMIC_CHANNEL
/*
* AIPS 2
*/
#define MX51_AIPS2_BASE_ADDR 0x83F00000
#define MX51_AIPS2_BASE_ADDR_VIRT 0xFB200000
#define MX51_AIPS2_SIZE SZ_1M
#define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00080000)
#define MX51_PLL2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00084000)
#define MX51_PLL3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00088000)
#define MX51_AHBMAX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00094000)
#define MX51_IIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00098000)
#define MX51_CSU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x0009C000)
#define MX51_ARM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A0000)
#define MX51_OWIRE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A4000)
#define MX51_FIRI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A8000)
#define MX51_CSPI2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000AC000)
#define MX51_SDMA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B0000)
#define MX51_SCC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B4000)
#define MX51_ROMCP_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B8000)
#define MX51_RTIC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000BC000)
#define MX51_CSPI3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C0000)
#define MX51_I2C2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C4000)
#define MX51_I2C1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C8000)
#define MX51_SSI1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000CC000)
#define MX51_AUDMUX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D0000)
#define MX51_M4IF_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D8000)
#define MX51_ESDCTL_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D9000)
#define MX51_WEIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DA000)
#define MX51_NFC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DB000)
#define MX51_EMI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DBF00)
#define MX51_MIPI_HSC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DC000)
#define MX51_ATA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E0000)
#define MX51_SIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E4000)
#define MX51_SSI3BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E8000)
#define MX51_MXC_FEC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000EC000)
#define MX51_TVE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F0000)
#define MX51_VPU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F4000)
#define MX51_SAHARA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F8000)
/*
* Memory regions and CS
*/
#define MX51_GPU_CTRL_BASE_ADDR 0x30000000
#define MX51_IPU_CTRL_BASE_ADDR 0x40000000
#define MX51_CSD0_BASE_ADDR 0x90000000
#define MX51_CSD1_BASE_ADDR 0xA0000000
#define MX51_CS0_BASE_ADDR 0xB0000000
#define MX51_CS1_BASE_ADDR 0xB8000000
#define MX51_CS2_BASE_ADDR 0xC0000000
#define MX51_CS3_BASE_ADDR 0xC8000000
#define MX51_CS4_BASE_ADDR 0xCC000000
#define MX51_CS5_BASE_ADDR 0xCE000000
/* Does given address belongs to the specified memory region? */
#define ADDRESS_IN_REGION(addr, start, size) \
(((addr) >= (start)) && ((addr) < (start)+(size)))
/* Does given address belongs to the specified named `module'? */
#define MX51_IS_MODULE(addr, module) \
ADDRESS_IN_REGION(addr, MX51_ ## module ## _BASE_ADDR, \
MX51_ ## module ## _SIZE)
/*
* This macro defines the physical to virtual address mapping for all the
* peripheral modules. It is used by passing in the physical address as x
* and returning the virtual address. If the physical address is not mapped,
* it returns 0xDEADBEEF
*/
#define MX51_IO_ADDRESS(x) \
(void __iomem *) \
(MX51_IS_MODULE(x, IRAM) ? MX51_IRAM_IO_ADDRESS(x) : \
MX51_IS_MODULE(x, TZIC) ? MX51_TZIC_IO_ADDRESS(x) : \
MX51_IS_MODULE(x, DEBUG) ? MX51_DEBUG_IO_ADDRESS(x) : \
MX51_IS_MODULE(x, SPBA0) ? MX51_SPBA0_IO_ADDRESS(x) : \
MX51_IS_MODULE(x, AIPS1) ? MX51_AIPS1_IO_ADDRESS(x) : \
MX51_IS_MODULE(x, AIPS2) ? MX51_AIPS2_IO_ADDRESS(x) : \
MX51_IS_MODULE(x, NFC_AXI) ? MX51_NFC_AXI_IO_ADDRESS(x) : \
0xDEADBEEF)
/*
* define the address mapping macros: in physical address order
*/
#define MX51_IRAM_IO_ADDRESS(x) \
(((x) - MX51_IRAM_BASE_ADDR) + MX51_IRAM_BASE_ADDR_VIRT)
#define MX51_TZIC_IO_ADDRESS(x) \
(((x) - MX51_TZIC_BASE_ADDR) + MX51_TZIC_BASE_ADDR_VIRT)
#define MX51_DEBUG_IO_ADDRESS(x) \
(((x) - MX51_DEBUG_BASE_ADDR) + MX51_DEBUG_BASE_ADDR_VIRT)
#define MX51_SPBA0_IO_ADDRESS(x) \
(((x) - MX51_SPBA0_BASE_ADDR) + MX51_SPBA0_BASE_ADDR_VIRT)
#define MX51_AIPS1_IO_ADDRESS(x) \
(((x) - MX51_AIPS1_BASE_ADDR) + MX51_AIPS1_BASE_ADDR_VIRT)
#define MX51_AIPS2_IO_ADDRESS(x) \
(((x) - MX51_AIPS2_BASE_ADDR) + MX51_AIPS2_BASE_ADDR_VIRT)
#define MX51_NFC_AXI_IO_ADDRESS(x) \
(((x) - MX51_NFC_AXI_BASE_ADDR) + MX51_NFC_AXI_BASE_ADDR_VIRT)
#define MX51_IS_MEM_DEVICE_NONSHARED(x) 0
/*
* DMA request assignments
*/
#define MX51_DMA_REQ_SSI3_TX1 47
#define MX51_DMA_REQ_SSI3_RX1 46
#define MX51_DMA_REQ_SPDIF 45
#define MX51_DMA_REQ_UART3_TX 44
#define MX51_DMA_REQ_UART3_RX 43
#define MX51_DMA_REQ_SLIM_B_TX 42
#define MX51_DMA_REQ_SDHC4 41
#define MX51_DMA_REQ_SDHC3 40
#define MX51_DMA_REQ_CSPI_TX 39
#define MX51_DMA_REQ_CSPI_RX 38
#define MX51_DMA_REQ_SSI3_TX2 37
#define MX51_DMA_REQ_IPU 36
#define MX51_DMA_REQ_SSI3_RX2 35
#define MX51_DMA_REQ_EPIT2 34
#define MX51_DMA_REQ_CTI2_1 33
#define MX51_DMA_REQ_EMI_WR 32
#define MX51_DMA_REQ_CTI2_0 31
#define MX51_DMA_REQ_EMI_RD 30
#define MX51_DMA_REQ_SSI1_TX1 29
#define MX51_DMA_REQ_SSI1_RX1 28
#define MX51_DMA_REQ_SSI1_TX2 27
#define MX51_DMA_REQ_SSI1_RX2 26
#define MX51_DMA_REQ_SSI2_TX1 25
#define MX51_DMA_REQ_SSI2_RX1 24
#define MX51_DMA_REQ_SSI2_TX2 23
#define MX51_DMA_REQ_SSI2_RX2 22
#define MX51_DMA_REQ_SDHC2 21
#define MX51_DMA_REQ_SDHC1 20
#define MX51_DMA_REQ_UART1_TX 19
#define MX51_DMA_REQ_UART1_RX 18
#define MX51_DMA_REQ_UART2_TX 17
#define MX51_DMA_REQ_UART2_RX 16
#define MX51_DMA_REQ_GPU 15
#define MX51_DMA_REQ_EXTREQ1 14
#define MX51_DMA_REQ_FIRI_TX 13
#define MX51_DMA_REQ_FIRI_RX 12
#define MX51_DMA_REQ_HS_I2C_RX 11
#define MX51_DMA_REQ_HS_I2C_TX 10
#define MX51_DMA_REQ_CSPI2_TX 9
#define MX51_DMA_REQ_CSPI2_RX 8
#define MX51_DMA_REQ_CSPI1_TX 7
#define MX51_DMA_REQ_CSPI1_RX 6
#define MX51_DMA_REQ_SLIM_B 5
#define MX51_DMA_REQ_ATA_TX_END 4
#define MX51_DMA_REQ_ATA_TX 3
#define MX51_DMA_REQ_ATA_RX 2
#define MX51_DMA_REQ_GPC 1
#define MX51_DMA_REQ_VPU 0
/*
* Interrupt numbers
*/
#define MX51_MXC_INT_BASE 0
#define MX51_MXC_INT_RESV0 0
#define MX51_MXC_INT_MMC_SDHC1 1
#define MX51_MXC_INT_MMC_SDHC2 2
#define MX51_MXC_INT_MMC_SDHC3 3
#define MX51_MXC_INT_MMC_SDHC4 4
#define MX51_MXC_INT_RESV5 5
#define MX51_MXC_INT_SDMA 6
#define MX51_MXC_INT_IOMUX 7
#define MX51_MXC_INT_NFC 8
#define MX51_MXC_INT_VPU 9
#define MX51_MXC_INT_IPU_ERR 10
#define MX51_MXC_INT_IPU_SYN 11
#define MX51_MXC_INT_GPU 12
#define MX51_MXC_INT_RESV13 13
#define MX51_MXC_INT_USB_H1 14
#define MX51_MXC_INT_EMI 15
#define MX51_MXC_INT_USB_H2 16
#define MX51_MXC_INT_USB_H3 17
#define MX51_MXC_INT_USB_OTG 18
#define MX51_MXC_INT_SAHARA_H0 19
#define MX51_MXC_INT_SAHARA_H1 20
#define MX51_MXC_INT_SCC_SMN 21
#define MX51_MXC_INT_SCC_STZ 22
#define MX51_MXC_INT_SCC_SCM 23
#define MX51_MXC_INT_SRTC_NTZ 24
#define MX51_MXC_INT_SRTC_TZ 25
#define MX51_MXC_INT_RTIC 26
#define MX51_MXC_INT_CSU 27
#define MX51_MXC_INT_SLIM_B 28
#define MX51_MXC_INT_SSI1 29
#define MX51_MXC_INT_SSI2 30
#define MX51_MXC_INT_UART1 31
#define MX51_MXC_INT_UART2 32
#define MX51_MXC_INT_UART3 33
#define MX51_MXC_INT_RESV34 34
#define MX51_MXC_INT_RESV35 35
#define MX51_MXC_INT_CSPI1 36
#define MX51_MXC_INT_CSPI2 37
#define MX51_MXC_INT_CSPI 38
#define MX51_MXC_INT_GPT 39
#define MX51_MXC_INT_EPIT1 40
#define MX51_MXC_INT_EPIT2 41
#define MX51_MXC_INT_GPIO1_INT7 42
#define MX51_MXC_INT_GPIO1_INT6 43
#define MX51_MXC_INT_GPIO1_INT5 44
#define MX51_MXC_INT_GPIO1_INT4 45
#define MX51_MXC_INT_GPIO1_INT3 46
#define MX51_MXC_INT_GPIO1_INT2 47
#define MX51_MXC_INT_GPIO1_INT1 48
#define MX51_MXC_INT_GPIO1_INT0 49
#define MX51_MXC_INT_GPIO1_LOW 50
#define MX51_MXC_INT_GPIO1_HIGH 51
#define MX51_MXC_INT_GPIO2_LOW 52
#define MX51_MXC_INT_GPIO2_HIGH 53
#define MX51_MXC_INT_GPIO3_LOW 54
#define MX51_MXC_INT_GPIO3_HIGH 55
#define MX51_MXC_INT_GPIO4_LOW 56
#define MX51_MXC_INT_GPIO4_HIGH 57
#define MX51_MXC_INT_WDOG1 58
#define MX51_MXC_INT_WDOG2 59
#define MX51_MXC_INT_KPP 60
#define MX51_MXC_INT_PWM1 61
#define MX51_MXC_INT_I2C1 62
#define MX51_MXC_INT_I2C2 63
#define MX51_MXC_INT_HS_I2C 64
#define MX51_MXC_INT_RESV65 65
#define MX51_MXC_INT_RESV66 66
#define MX51_MXC_INT_SIM_IPB 67
#define MX51_MXC_INT_SIM_DAT 68
#define MX51_MXC_INT_IIM 69
#define MX51_MXC_INT_ATA 70
#define MX51_MXC_INT_CCM1 71
#define MX51_MXC_INT_CCM2 72
#define MX51_MXC_INT_GPC1 73
#define MX51_MXC_INT_GPC2 74
#define MX51_MXC_INT_SRC 75
#define MX51_MXC_INT_NM 76
#define MX51_MXC_INT_PMU 77
#define MX51_MXC_INT_CTI_IRQ 78
#define MX51_MXC_INT_CTI1_TG0 79
#define MX51_MXC_INT_CTI1_TG1 80
#define MX51_MXC_INT_MCG_ERR 81
#define MX51_MXC_INT_MCG_TMR 82
#define MX51_MXC_INT_MCG_FUNC 83
#define MX51_MXC_INT_GPU2_IRQ 84
#define MX51_MXC_INT_GPU2_BUSY 85
#define MX51_MXC_INT_RESV86 86
#define MX51_MXC_INT_FEC 87
#define MX51_MXC_INT_OWIRE 88
#define MX51_MXC_INT_CTI1_TG2 89
#define MX51_MXC_INT_SJC 90
#define MX51_MXC_INT_SPDIF 91
#define MX51_MXC_INT_TVE 92
#define MX51_MXC_INT_FIRI 93
#define MX51_MXC_INT_PWM2 94
#define MX51_MXC_INT_SLIM_EXP 95
#define MX51_MXC_INT_SSI3 96
#define MX51_MXC_INT_EMI_BOOT 97
#define MX51_MXC_INT_CTI1_TG3 98
#define MX51_MXC_INT_SMC_RX 99
#define MX51_MXC_INT_VPU_IDLE 100
#define MX51_MXC_INT_EMI_NFC 101
#define MX51_MXC_INT_GPU_IDLE 102
/* silicon revisions specific to i.MX51 */
#define MX51_CHIP_REV_1_0 0x10
#define MX51_CHIP_REV_1_1 0x11
#define MX51_CHIP_REV_1_2 0x12
#define MX51_CHIP_REV_1_3 0x13
#define MX51_CHIP_REV_2_0 0x20
#define MX51_CHIP_REV_2_1 0x21
#define MX51_CHIP_REV_2_2 0x22
#define MX51_CHIP_REV_2_3 0x23
#define MX51_CHIP_REV_3_0 0x30
#define MX51_CHIP_REV_3_1 0x31
#define MX51_CHIP_REV_3_2 0x32
/* Mandatory defines used globally */
#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
extern unsigned int system_rev;
static inline unsigned int mx51_revision(void)
{
return system_rev;
}
#endif
#endif /* __ASM_ARCH_MXC_MX51_H__ */
arch/arm/plat-mxc/include/mach/mxc.h
浏览文件 @ b93a4afc
...@@ -30,6 +30,7 @@ ...@@ -30,6 +30,7 @@
#define MXC_CPU_MX27 27 #define MXC_CPU_MX27 27
#define MXC_CPU_MX31 31 #define MXC_CPU_MX31 31
#define MXC_CPU_MX35 35 #define MXC_CPU_MX35 35
#define MXC_CPU_MX51 51
#define MXC_CPU_MXC91231 91231 #define MXC_CPU_MXC91231 91231
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
...@@ -108,6 +109,18 @@ extern unsigned int __mxc_cpu_type; ...@@ -108,6 +109,18 @@ extern unsigned int __mxc_cpu_type;
# define cpu_is_mx35() (0) # define cpu_is_mx35() (0)
#endif #endif
#ifdef CONFIG_ARCH_MX5
# ifdef mxc_cpu_type
# undef mxc_cpu_type
# define mxc_cpu_type __mxc_cpu_type
# else
# define mxc_cpu_type MXC_CPU_MX51
# endif
# define cpu_is_mx51() (mxc_cpu_type == MXC_CPU_MX51)
#else
# define cpu_is_mx51() (0)
#endif
#ifdef CONFIG_ARCH_MXC91231 #ifdef CONFIG_ARCH_MXC91231
# ifdef mxc_cpu_type # ifdef mxc_cpu_type
# undef mxc_cpu_type # undef mxc_cpu_type
...@@ -121,9 +134,10 @@ extern unsigned int __mxc_cpu_type; ...@@ -121,9 +134,10 @@ extern unsigned int __mxc_cpu_type;
#endif #endif
#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2) #if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2)
#define CSCR_U(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10) /* These are deprecated, use mx[23][157]_setup_weimcs instead. */
#define CSCR_L(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10 + 0x4) #define CSCR_U(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10))
#define CSCR_A(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10 + 0x8) #define CSCR_L(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10 + 0x4))
#define CSCR_A(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10 + 0x8))
#endif #endif
#define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35() || cpu_is_mxc91231()) #define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35() || cpu_is_mxc91231())
......
arch/arm/plat-mxc/include/mach/mxc91231.h
浏览文件 @ b93a4afc
...@@ -184,60 +184,22 @@ ...@@ -184,60 +184,22 @@
#define MXC91231_CS4_BASE_ADDR 0xB4000000 #define MXC91231_CS4_BASE_ADDR 0xB4000000
#define MXC91231_CS5_BASE_ADDR 0xB6000000 #define MXC91231_CS5_BASE_ADDR 0xB6000000
/* Is given address belongs to the specified memory region? */
#define ADDRESS_IN_REGION(addr, start, size) \
(((addr) >= (start)) && ((addr) < (start)+(size)))
/* Is given address belongs to the specified named `module'? */
#define MXC91231_IS_MODULE(addr, module) \
ADDRESS_IN_REGION(addr, MXC91231_ ## module ## _BASE_ADDR, \
MXC91231_ ## module ## _SIZE)
/* /*
* This macro defines the physical to virtual address mapping for all the * This macro defines the physical to virtual address mapping for all the
* peripheral modules. It is used by passing in the physical address as x * peripheral modules. It is used by passing in the physical address as x
* and returning the virtual address. If the physical address is not mapped, * and returning the virtual address. If the physical address is not mapped,
* it returns 0xDEADBEEF * it returns 0.
*/
#define MXC91231_IO_ADDRESS(x) \
(void __iomem *) \
(MXC91231_IS_MODULE(x, L2CC) ? MXC91231_L2CC_IO_ADDRESS(x) : \
MXC91231_IS_MODULE(x, AIPS1) ? MXC91231_AIPS1_IO_ADDRESS(x) : \
MXC91231_IS_MODULE(x, AIPS2) ? MXC91231_AIPS2_IO_ADDRESS(x) : \
MXC91231_IS_MODULE(x, SPBA0) ? MXC91231_SPBA0_IO_ADDRESS(x) : \
MXC91231_IS_MODULE(x, SPBA1) ? MXC91231_SPBA1_IO_ADDRESS(x) : \
MXC91231_IS_MODULE(x, ROMP) ? MXC91231_ROMP_IO_ADDRESS(x) : \
MXC91231_IS_MODULE(x, AVIC) ? MXC91231_AVIC_IO_ADDRESS(x) : \
MXC91231_IS_MODULE(x, X_MEMC) ? MXC91231_X_MEMC_IO_ADDRESS(x) : \
0xDEADBEEF)
/*
* define the address mapping macros: in physical address order
*/ */
#define MXC91231_L2CC_IO_ADDRESS(x) \
(((x) - MXC91231_L2CC_BASE_ADDR) + MXC91231_L2CC_BASE_ADDR_VIRT)
#define MXC91231_AIPS1_IO_ADDRESS(x) \
(((x) - MXC91231_AIPS1_BASE_ADDR) + MXC91231_AIPS1_BASE_ADDR_VIRT)
#define MXC91231_SPBA0_IO_ADDRESS(x) \
(((x) - MXC91231_SPBA0_BASE_ADDR) + MXC91231_SPBA0_BASE_ADDR_VIRT)
#define MXC91231_SPBA1_IO_ADDRESS(x) \
(((x) - MXC91231_SPBA1_BASE_ADDR) + MXC91231_SPBA1_BASE_ADDR_VIRT)
#define MXC91231_AIPS2_IO_ADDRESS(x) \
(((x) - MXC91231_AIPS2_BASE_ADDR) + MXC91231_AIPS2_BASE_ADDR_VIRT)
#define MXC91231_ROMP_IO_ADDRESS(x) \
(((x) - MXC91231_ROMP_BASE_ADDR) + MXC91231_ROMP_BASE_ADDR_VIRT)
#define MXC91231_AVIC_IO_ADDRESS(x) \
(((x) - MXC91231_AVIC_BASE_ADDR) + MXC91231_AVIC_BASE_ADDR_VIRT)
#define MXC91231_X_MEMC_IO_ADDRESS(x) \ #define MXC91231_IO_ADDRESS(x) ( \
(((x) - MXC91231_X_MEMC_BASE_ADDR) + MXC91231_X_MEMC_BASE_ADDR_VIRT) IMX_IO_ADDRESS(x, MXC91231_L2CC) ?: \
IMX_IO_ADDRESS(x, MXC91231_X_MEMC) ?: \
IMX_IO_ADDRESS(x, MXC91231_ROMP) ?: \
IMX_IO_ADDRESS(x, MXC91231_AVIC) ?: \
IMX_IO_ADDRESS(x, MXC91231_AIPS1) ?: \
IMX_IO_ADDRESS(x, MXC91231_SPBA0) ?: \
IMX_IO_ADDRESS(x, MXC91231_SPBA1) ?: \
IMX_IO_ADDRESS(x, MXC91231_AIPS2))
/* /*
* Interrupt numbers * Interrupt numbers
......
arch/arm/plat-mxc/include/mach/mxc_ehci.h
浏览文件 @ b93a4afc
...@@ -22,6 +22,10 @@ ...@@ -22,6 +22,10 @@
#define MXC_EHCI_POWER_PINS_ENABLED (1 << 5) #define MXC_EHCI_POWER_PINS_ENABLED (1 << 5)
#define MXC_EHCI_TTL_ENABLED (1 << 6) #define MXC_EHCI_TTL_ENABLED (1 << 6)
#define MXC_EHCI_INTERNAL_PHY (1 << 7)
#define MXC_EHCI_IPPUE_DOWN (1 << 8)
#define MXC_EHCI_IPPUE_UP (1 << 9)
struct mxc_usbh_platform_data { struct mxc_usbh_platform_data {
int (*init)(struct platform_device *pdev); int (*init)(struct platform_device *pdev);
int (*exit)(struct platform_device *pdev); int (*exit)(struct platform_device *pdev);
......
arch/arm/plat-mxc/include/mach/ssi.h 0 → 100644
浏览文件 @ b93a4afc
#ifndef __MACH_SSI_H
#define __MACH_SSI_H
struct snd_ac97;
extern unsigned char imx_ssi_fiq_start, imx_ssi_fiq_end;
extern unsigned long imx_ssi_fiq_base, imx_ssi_fiq_tx_buffer, imx_ssi_fiq_rx_buffer;
struct imx_ssi_platform_data {
unsigned int flags;
#define IMX_SSI_DMA (1 << 0)
#define IMX_SSI_USE_AC97 (1 << 1)
void (*ac97_reset) (struct snd_ac97 *ac97);
void (*ac97_warm_reset)(struct snd_ac97 *ac97);
};
#endif /* __MACH_SSI_H */
arch/arm/plat-mxc/include/mach/timex.h
浏览文件 @ b93a4afc
...@@ -28,6 +28,8 @@ ...@@ -28,6 +28,8 @@
#define CLOCK_TICK_RATE 16625000 #define CLOCK_TICK_RATE 16625000
#elif defined CONFIG_ARCH_MX25 #elif defined CONFIG_ARCH_MX25
#define CLOCK_TICK_RATE 16000000 #define CLOCK_TICK_RATE 16000000
#elif defined CONFIG_ARCH_MX5
#define CLOCK_TICK_RATE 8000000
#elif defined CONFIG_ARCH_MXC91231 #elif defined CONFIG_ARCH_MXC91231
#define CLOCK_TICK_RATE 13000000 #define CLOCK_TICK_RATE 13000000
#endif #endif
......
arch/arm/plat-mxc/include/mach/uncompress.h
浏览文件 @ b93a4afc
/* /*
* arch/arm/plat-mxc/include/mach/uncompress.h * arch/arm/plat-mxc/include/mach/uncompress.h
* *
*
*
* Copyright (C) 1999 ARM Limited * Copyright (C) 1999 ARM Limited
* Copyright (C) Shane Nay (shane@minirl.com) * Copyright (C) Shane Nay (shane@minirl.com)
* *
...@@ -25,7 +23,6 @@ ...@@ -25,7 +23,6 @@
#define __MXC_BOOT_UNCOMPRESS #define __MXC_BOOT_UNCOMPRESS
#include <mach/hardware.h>
#include <asm/mach-types.h> #include <asm/mach-types.h>
static unsigned long uart_base; static unsigned long uart_base;
......
arch/arm/plat-mxc/iomux-mx1-mx2.c 已删除 100644 → 0
浏览文件 @ 62c132a8
/*
* arch/arm/mach-mxc/generic.c
*
* author: Sascha Hauer
* Created: april 20th, 2004
* Copyright: Synertronixx GmbH
*
* Common code for i.MX machines
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/gpio.h>
#include <mach/hardware.h>
#include <asm/mach/map.h>
#include <mach/iomux.h>
void mxc_gpio_mode(int gpio_mode)
{
unsigned int pin = gpio_mode & GPIO_PIN_MASK;
unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT;
unsigned int tmp;
/* Pullup enable */
tmp = __raw_readl(VA_GPIO_BASE + MXC_PUEN(port));
if (gpio_mode & GPIO_PUEN)
tmp |= (1 << pin);
else
tmp &= ~(1 << pin);
__raw_writel(tmp, VA_GPIO_BASE + MXC_PUEN(port));
/* Data direction */
tmp = __raw_readl(VA_GPIO_BASE + MXC_DDIR(port));
if (gpio_mode & GPIO_OUT)
tmp |= 1 << pin;
else
tmp &= ~(1 << pin);
__raw_writel(tmp, VA_GPIO_BASE + MXC_DDIR(port));
/* Primary / alternate function */
tmp = __raw_readl(VA_GPIO_BASE + MXC_GPR(port));
if (gpio_mode & GPIO_AF)
tmp |= (1 << pin);
else
tmp &= ~(1 << pin);
__raw_writel(tmp, VA_GPIO_BASE + MXC_GPR(port));
/* use as gpio? */
tmp = __raw_readl(VA_GPIO_BASE + MXC_GIUS(port));
if (gpio_mode & (GPIO_PF | GPIO_AF))
tmp &= ~(1 << pin);
else
tmp |= (1 << pin);
__raw_writel(tmp, VA_GPIO_BASE + MXC_GIUS(port));
if (pin < 16) {
tmp = __raw_readl(VA_GPIO_BASE + MXC_OCR1(port));
tmp &= ~(3 << (pin * 2));
tmp |= (ocr << (pin * 2));
__raw_writel(tmp, VA_GPIO_BASE + MXC_OCR1(port));
tmp = __raw_readl(VA_GPIO_BASE + MXC_ICONFA1(port));
tmp &= ~(3 << (pin * 2));
tmp |= ((gpio_mode >> GPIO_AOUT_SHIFT) & 3) << (pin * 2);
__raw_writel(tmp, VA_GPIO_BASE + MXC_ICONFA1(port));
tmp = __raw_readl(VA_GPIO_BASE + MXC_ICONFB1(port));
tmp &= ~(3 << (pin * 2));
tmp |= ((gpio_mode >> GPIO_BOUT_SHIFT) & 3) << (pin * 2);
__raw_writel(tmp, VA_GPIO_BASE + MXC_ICONFB1(port));
} else {
pin -= 16;
tmp = __raw_readl(VA_GPIO_BASE + MXC_OCR2(port));
tmp &= ~(3 << (pin * 2));
tmp |= (ocr << (pin * 2));
__raw_writel(tmp, VA_GPIO_BASE + MXC_OCR2(port));
tmp = __raw_readl(VA_GPIO_BASE + MXC_ICONFA2(port));
tmp &= ~(3 << (pin * 2));
tmp |= ((gpio_mode >> GPIO_AOUT_SHIFT) & 3) << (pin * 2);
__raw_writel(tmp, VA_GPIO_BASE + MXC_ICONFA2(port));
tmp = __raw_readl(VA_GPIO_BASE + MXC_ICONFB2(port));
tmp &= ~(3 << (pin * 2));
tmp |= ((gpio_mode >> GPIO_BOUT_SHIFT) & 3) << (pin * 2);
__raw_writel(tmp, VA_GPIO_BASE + MXC_ICONFB2(port));
}
}
EXPORT_SYMBOL(mxc_gpio_mode);
int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
const char *label)
{
const int *p = pin_list;
int i;
unsigned gpio;
unsigned mode;
int ret = -EINVAL;
for (i = 0; i < count; i++) {
gpio = *p & (GPIO_PIN_MASK | GPIO_PORT_MASK);
mode = *p & ~(GPIO_PIN_MASK | GPIO_PORT_MASK);
if (gpio >= (GPIO_PORT_MAX + 1) * 32)
goto setup_error;
ret = gpio_request(gpio, label);
if (ret)
goto setup_error;
mxc_gpio_mode(gpio | mode);
p++;
}
return 0;
setup_error:
mxc_gpio_release_multiple_pins(pin_list, i);
return ret;
}
EXPORT_SYMBOL(mxc_gpio_setup_multiple_pins);
void mxc_gpio_release_multiple_pins(const int *pin_list, int count)
{
const int *p = pin_list;
int i;
for (i = 0; i < count; i++) {
unsigned gpio = *p & (GPIO_PIN_MASK | GPIO_PORT_MASK);
gpio_free(gpio);
p++;
}
}
EXPORT_SYMBOL(mxc_gpio_release_multiple_pins);
arch/arm/plat-mxc/iomux-v1.c 0 → 100644
浏览文件 @ b93a4afc
/*
* arch/arm/plat-mxc/iomux-v1.c
*
* Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH
* Copyright (C) 2009 Uwe Kleine-Koenig, Pengutronix
*
* Common code for i.MX1, i.MX21 and i.MX27
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
*/
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/gpio.h>
#include <mach/hardware.h>
#include <asm/mach/map.h>
#include <mach/iomux-v1.h>
static void __iomem *imx_iomuxv1_baseaddr;
static unsigned imx_iomuxv1_numports;
static inline unsigned long imx_iomuxv1_readl(unsigned offset)
{
return __raw_readl(imx_iomuxv1_baseaddr + offset);
}
static inline void imx_iomuxv1_writel(unsigned long val, unsigned offset)
{
__raw_writel(val, imx_iomuxv1_baseaddr + offset);
}
static inline void imx_iomuxv1_rmwl(unsigned offset,
unsigned long mask, unsigned long value)
{
unsigned long reg = imx_iomuxv1_readl(offset);
reg &= ~mask;
reg |= value;
imx_iomuxv1_writel(reg, offset);
}
static inline void imx_iomuxv1_set_puen(
unsigned int port, unsigned int pin, int on)
{
unsigned long mask = 1 << pin;
imx_iomuxv1_rmwl(MXC_PUEN(port), mask, on ? mask : 0);
}
static inline void imx_iomuxv1_set_ddir(
unsigned int port, unsigned int pin, int out)
{
unsigned long mask = 1 << pin;
imx_iomuxv1_rmwl(MXC_DDIR(port), mask, out ? mask : 0);
}
static inline void imx_iomuxv1_set_gpr(
unsigned int port, unsigned int pin, int af)
{
unsigned long mask = 1 << pin;
imx_iomuxv1_rmwl(MXC_GPR(port), mask, af ? mask : 0);
}
static inline void imx_iomuxv1_set_gius(
unsigned int port, unsigned int pin, int inuse)
{
unsigned long mask = 1 << pin;
imx_iomuxv1_rmwl(MXC_GIUS(port), mask, inuse ? mask : 0);
}
static inline void imx_iomuxv1_set_ocr(
unsigned int port, unsigned int pin, unsigned int ocr)
{
unsigned long shift = (pin & 0xf) << 1;
unsigned long mask = 3 << shift;
unsigned long value = ocr << shift;
unsigned long offset = pin < 16 ? MXC_OCR1(port) : MXC_OCR2(port);
imx_iomuxv1_rmwl(offset, mask, value);
}
static inline void imx_iomuxv1_set_iconfa(
unsigned int port, unsigned int pin, unsigned int aout)
{
unsigned long shift = (pin & 0xf) << 1;
unsigned long mask = 3 << shift;
unsigned long value = aout << shift;
unsigned long offset = pin < 16 ? MXC_ICONFA1(port) : MXC_ICONFA2(port);
imx_iomuxv1_rmwl(offset, mask, value);
}
static inline void imx_iomuxv1_set_iconfb(
unsigned int port, unsigned int pin, unsigned int bout)
{
unsigned long shift = (pin & 0xf) << 1;
unsigned long mask = 3 << shift;
unsigned long value = bout << shift;
unsigned long offset = pin < 16 ? MXC_ICONFB1(port) : MXC_ICONFB2(port);
imx_iomuxv1_rmwl(offset, mask, value);
}
int mxc_gpio_mode(int gpio_mode)
{
unsigned int pin = gpio_mode & GPIO_PIN_MASK;
unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT;
unsigned int aout = (gpio_mode >> GPIO_AOUT_SHIFT) & 3;
unsigned int bout = (gpio_mode >> GPIO_BOUT_SHIFT) & 3;
if (port >= imx_iomuxv1_numports)
return -EINVAL;
/* Pullup enable */
imx_iomuxv1_set_puen(port, pin, gpio_mode & GPIO_PUEN);
/* Data direction */
imx_iomuxv1_set_ddir(port, pin, gpio_mode & GPIO_OUT);
/* Primary / alternate function */
imx_iomuxv1_set_gpr(port, pin, gpio_mode & GPIO_AF);
/* use as gpio? */
imx_iomuxv1_set_gius(port, pin, !(gpio_mode & (GPIO_PF | GPIO_AF)));
imx_iomuxv1_set_ocr(port, pin, ocr);
imx_iomuxv1_set_iconfa(port, pin, aout);
imx_iomuxv1_set_iconfb(port, pin, bout);
return 0;
}
EXPORT_SYMBOL(mxc_gpio_mode);
static int imx_iomuxv1_setup_multiple(const int *list, unsigned count)
{
size_t i;
int ret;
for (i = 0; i < count; ++i) {
ret = mxc_gpio_mode(list[i]);
if (ret)
return ret;
}
return ret;
}
int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
const char *label)
{
size_t i;
int ret;
for (i = 0; i < count; ++i) {
unsigned gpio = pin_list[i] & (GPIO_PIN_MASK | GPIO_PORT_MASK);
ret = gpio_request(gpio, label);
if (ret)
goto err_gpio_request;
}
ret = imx_iomuxv1_setup_multiple(pin_list, count);
if (ret)
goto err_setup;
return 0;
err_setup:
BUG_ON(i != count);
err_gpio_request:
mxc_gpio_release_multiple_pins(pin_list, i);
return ret;
}
EXPORT_SYMBOL(mxc_gpio_setup_multiple_pins);
void mxc_gpio_release_multiple_pins(const int *pin_list, int count)
{
size_t i;
for (i = 0; i < count; ++i) {
unsigned gpio = pin_list[i] & (GPIO_PIN_MASK | GPIO_PORT_MASK);
gpio_free(gpio);
}
}
EXPORT_SYMBOL(mxc_gpio_release_multiple_pins);
static int imx_iomuxv1_init(void)
{
#ifdef CONFIG_ARCH_MX1
if (cpu_is_mx1()) {
imx_iomuxv1_baseaddr = MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR);
imx_iomuxv1_numports = MX1_NUM_GPIO_PORT;
} else
#endif
#ifdef CONFIG_MACH_MX21
if (cpu_is_mx21()) {
imx_iomuxv1_baseaddr = MX21_IO_ADDRESS(MX21_GPIO_BASE_ADDR);
imx_iomuxv1_numports = MX21_NUM_GPIO_PORT;
} else
#endif
#ifdef CONFIG_MACH_MX27
if (cpu_is_mx27()) {
imx_iomuxv1_baseaddr = MX27_IO_ADDRESS(MX27_GPIO_BASE_ADDR);
imx_iomuxv1_numports = MX27_NUM_GPIO_PORT;
} else
#endif
return -ENODEV;
return 0;
}
pure_initcall(imx_iomuxv1_init);
arch/arm/plat-mxc/time.c
浏览文件 @ b93a4afc
...@@ -30,9 +30,15 @@ ...@@ -30,9 +30,15 @@
#include <asm/mach/time.h> #include <asm/mach/time.h>
#include <mach/common.h> #include <mach/common.h>
/*
* There are 2 versions of the timer hardware on Freescale MXC hardware.
* Version 1: MX1/MXL, MX21, MX27.
* Version 2: MX25, MX31, MX35, MX37, MX51
*/
/* defines common for all i.MX */ /* defines common for all i.MX */
#define MXC_TCTL 0x00 #define MXC_TCTL 0x00
#define MXC_TCTL_TEN (1 << 0) #define MXC_TCTL_TEN (1 << 0) /* Enable module */
#define MXC_TPRER 0x04 #define MXC_TPRER 0x04
/* MX1, MX21, MX27 */ /* MX1, MX21, MX27 */
...@@ -47,8 +53,8 @@ ...@@ -47,8 +53,8 @@
#define MX2_TSTAT_CAPT (1 << 1) #define MX2_TSTAT_CAPT (1 << 1)
#define MX2_TSTAT_COMP (1 << 0) #define MX2_TSTAT_COMP (1 << 0)
/* MX31, MX35, MX25, MXC91231 */ /* MX31, MX35, MX25, MXC91231, MX5 */
#define MX3_TCTL_WAITEN (1 << 3) #define MX3_TCTL_WAITEN (1 << 3) /* Wait enable mode */
#define MX3_TCTL_CLK_IPG (1 << 6) #define MX3_TCTL_CLK_IPG (1 << 6)
#define MX3_TCTL_FRR (1 << 9) #define MX3_TCTL_FRR (1 << 9)
#define MX3_IR 0x0c #define MX3_IR 0x0c
...@@ -57,6 +63,9 @@ ...@@ -57,6 +63,9 @@
#define MX3_TCN 0x24 #define MX3_TCN 0x24
#define MX3_TCMP 0x10 #define MX3_TCMP 0x10
#define timer_is_v1() (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
#define timer_is_v2() (!timer_is_v1())
static struct clock_event_device clockevent_mxc; static struct clock_event_device clockevent_mxc;
static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED; static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;
...@@ -66,7 +75,7 @@ static inline void gpt_irq_disable(void) ...@@ -66,7 +75,7 @@ static inline void gpt_irq_disable(void)
{ {
unsigned int tmp; unsigned int tmp;
if (cpu_is_mx3() || cpu_is_mx25()) if (timer_is_v2())
__raw_writel(0, timer_base + MX3_IR); __raw_writel(0, timer_base + MX3_IR);
else { else {
tmp = __raw_readl(timer_base + MXC_TCTL); tmp = __raw_readl(timer_base + MXC_TCTL);
...@@ -76,7 +85,7 @@ static inline void gpt_irq_disable(void) ...@@ -76,7 +85,7 @@ static inline void gpt_irq_disable(void)
static inline void gpt_irq_enable(void) static inline void gpt_irq_enable(void)
{ {
if (cpu_is_mx3() || cpu_is_mx25()) if (timer_is_v2())
__raw_writel(1<<0, timer_base + MX3_IR); __raw_writel(1<<0, timer_base + MX3_IR);
else { else {
__raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN, __raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN,
...@@ -86,11 +95,13 @@ static inline void gpt_irq_enable(void) ...@@ -86,11 +95,13 @@ static inline void gpt_irq_enable(void)
static void gpt_irq_acknowledge(void) static void gpt_irq_acknowledge(void)
{ {
if (timer_is_v1()) {
if (cpu_is_mx1()) if (cpu_is_mx1())
__raw_writel(0, timer_base + MX1_2_TSTAT); __raw_writel(0, timer_base + MX1_2_TSTAT);
if (cpu_is_mx2()) else
__raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, timer_base + MX1_2_TSTAT); __raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP,
if (cpu_is_mx3() || cpu_is_mx25()) timer_base + MX1_2_TSTAT);
} else if (timer_is_v2())
__raw_writel(MX3_TSTAT_OF1, timer_base + MX3_TSTAT); __raw_writel(MX3_TSTAT_OF1, timer_base + MX3_TSTAT);
} }
...@@ -117,7 +128,7 @@ static int __init mxc_clocksource_init(struct clk *timer_clk) ...@@ -117,7 +128,7 @@ static int __init mxc_clocksource_init(struct clk *timer_clk)
{ {
unsigned int c = clk_get_rate(timer_clk); unsigned int c = clk_get_rate(timer_clk);
if (cpu_is_mx3() || cpu_is_mx25()) if (timer_is_v2())
clocksource_mxc.read = mx3_get_cycles; clocksource_mxc.read = mx3_get_cycles;
clocksource_mxc.mult = clocksource_hz2mult(c, clocksource_mxc.mult = clocksource_hz2mult(c,
...@@ -180,7 +191,7 @@ static void mxc_set_mode(enum clock_event_mode mode, ...@@ -180,7 +191,7 @@ static void mxc_set_mode(enum clock_event_mode mode,
if (mode != clockevent_mode) { if (mode != clockevent_mode) {
/* Set event time into far-far future */ /* Set event time into far-far future */
if (cpu_is_mx3() || cpu_is_mx25()) if (timer_is_v2())
__raw_writel(__raw_readl(timer_base + MX3_TCN) - 3, __raw_writel(__raw_readl(timer_base + MX3_TCN) - 3,
timer_base + MX3_TCMP); timer_base + MX3_TCMP);
else else
...@@ -233,7 +244,7 @@ static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id) ...@@ -233,7 +244,7 @@ static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
struct clock_event_device *evt = &clockevent_mxc; struct clock_event_device *evt = &clockevent_mxc;
uint32_t tstat; uint32_t tstat;
if (cpu_is_mx3() || cpu_is_mx25()) if (timer_is_v2())
tstat = __raw_readl(timer_base + MX3_TSTAT); tstat = __raw_readl(timer_base + MX3_TSTAT);
else else
tstat = __raw_readl(timer_base + MX1_2_TSTAT); tstat = __raw_readl(timer_base + MX1_2_TSTAT);
...@@ -264,7 +275,7 @@ static int __init mxc_clockevent_init(struct clk *timer_clk) ...@@ -264,7 +275,7 @@ static int __init mxc_clockevent_init(struct clk *timer_clk)
{ {
unsigned int c = clk_get_rate(timer_clk); unsigned int c = clk_get_rate(timer_clk);
if (cpu_is_mx3() || cpu_is_mx25()) if (timer_is_v2())
clockevent_mxc.set_next_event = mx3_set_next_event; clockevent_mxc.set_next_event = mx3_set_next_event;
clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC, clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC,
...@@ -296,7 +307,7 @@ void __init mxc_timer_init(struct clk *timer_clk, void __iomem *base, int irq) ...@@ -296,7 +307,7 @@ void __init mxc_timer_init(struct clk *timer_clk, void __iomem *base, int irq)
__raw_writel(0, timer_base + MXC_TCTL); __raw_writel(0, timer_base + MXC_TCTL);
__raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */ __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */
if (cpu_is_mx3() || cpu_is_mx25()) if (timer_is_v2())
tctl_val = MX3_TCTL_CLK_IPG | MX3_TCTL_FRR | MX3_TCTL_WAITEN | MXC_TCTL_TEN; tctl_val = MX3_TCTL_CLK_IPG | MX3_TCTL_FRR | MX3_TCTL_WAITEN | MXC_TCTL_TEN;
else else
tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
......
arch/arm/plat-mxc/tzic.c 0 → 100644
浏览文件 @ b93a4afc
/*
* Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/io.h>
#include <asm/mach/irq.h>
#include <mach/hardware.h>
/*
*****************************************
* TZIC Registers *
*****************************************
*/
#define TZIC_INTCNTL 0x0000 /* Control register */
#define TZIC_INTTYPE 0x0004 /* Controller Type register */
#define TZIC_IMPID 0x0008 /* Distributor Implementer Identification */
#define TZIC_PRIOMASK 0x000C /* Priority Mask Reg */
#define TZIC_SYNCCTRL 0x0010 /* Synchronizer Control register */
#define TZIC_DSMINT 0x0014 /* DSM interrupt Holdoffregister */
#define TZIC_INTSEC0(i) (0x0080 + ((i) << 2)) /* Interrupt Security Reg 0 */
#define TZIC_ENSET0(i) (0x0100 + ((i) << 2)) /* Enable Set Reg 0 */
#define TZIC_ENCLEAR0(i) (0x0180 + ((i) << 2)) /* Enable Clear Reg 0 */
#define TZIC_SRCSET0 0x0200 /* Source Set Register 0 */
#define TZIC_SRCCLAR0 0x0280 /* Source Clear Register 0 */
#define TZIC_PRIORITY0 0x0400 /* Priority Register 0 */
#define TZIC_PND0 0x0D00 /* Pending Register 0 */
#define TZIC_HIPND0 0x0D80 /* High Priority Pending Register */
#define TZIC_WAKEUP0(i) (0x0E00 + ((i) << 2)) /* Wakeup Config Register */
#define TZIC_SWINT 0x0F00 /* Software Interrupt Rigger Register */
#define TZIC_ID0 0x0FD0 /* Indentification Register 0 */
void __iomem *tzic_base; /* Used as irq controller base in entry-macro.S */
/**
* tzic_mask_irq() - Disable interrupt number "irq" in the TZIC
*
* @param irq interrupt source number
*/
static void tzic_mask_irq(unsigned int irq)
{
int index, off;
index = irq >> 5;
off = irq & 0x1F;
__raw_writel(1 << off, tzic_base + TZIC_ENCLEAR0(index));
}
/**
* tzic_unmask_irq() - Enable interrupt number "irq" in the TZIC
*
* @param irq interrupt source number
*/
static void tzic_unmask_irq(unsigned int irq)
{
int index, off;
index = irq >> 5;
off = irq & 0x1F;
__raw_writel(1 << off, tzic_base + TZIC_ENSET0(index));
}
static unsigned int wakeup_intr[4];
/**
* tzic_set_wake_irq() - Set interrupt number "irq" in the TZIC as a wake-up source.
*
* @param irq interrupt source number
* @param enable enable as wake-up if equal to non-zero
* disble as wake-up if equal to zero
*
* @return This function returns 0 on success.
*/
static int tzic_set_wake_irq(unsigned int irq, unsigned int enable)
{
unsigned int index, off;
index = irq >> 5;
off = irq & 0x1F;
if (index > 3)
return -EINVAL;
if (enable)
wakeup_intr[index] |= (1 << off);
else
wakeup_intr[index] &= ~(1 << off);
return 0;
}
static struct irq_chip mxc_tzic_chip = {
.name = "MXC_TZIC",
.ack = tzic_mask_irq,
.mask = tzic_mask_irq,
.unmask = tzic_unmask_irq,
.set_wake = tzic_set_wake_irq,
};
/*
* This function initializes the TZIC hardware and disables all the
* interrupts. It registers the interrupt enable and disable functions
* to the kernel for each interrupt source.
*/
void __init tzic_init_irq(void __iomem *irqbase)
{
int i;
tzic_base = irqbase;
/* put the TZIC into the reset value with
* all interrupts disabled
*/
i = __raw_readl(tzic_base + TZIC_INTCNTL);
__raw_writel(0x80010001, tzic_base + TZIC_INTCNTL);
__raw_writel(0x1f, tzic_base + TZIC_PRIOMASK);
__raw_writel(0x02, tzic_base + TZIC_SYNCCTRL);
for (i = 0; i < 4; i++)
__raw_writel(0xFFFFFFFF, tzic_base + TZIC_INTSEC0(i));
/* disable all interrupts */
for (i = 0; i < 4; i++)
__raw_writel(0xFFFFFFFF, tzic_base + TZIC_ENCLEAR0(i));
/* all IRQ no FIQ Warning :: No selection */
for (i = 0; i < MXC_INTERNAL_IRQS; i++) {
set_irq_chip(i, &mxc_tzic_chip);
set_irq_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID);
}
pr_info("TrustZone Interrupt Controller (TZIC) initialized\n");
}
/**
* tzic_enable_wake() - enable wakeup interrupt
*
* @param is_idle 1 if called in idle loop (ENSET0 register);
* 0 to be used when called from low power entry
* @return 0 if successful; non-zero otherwise
*/
int tzic_enable_wake(int is_idle)
{
unsigned int i, v;
__raw_writel(1, tzic_base + TZIC_DSMINT);
if (unlikely(__raw_readl(tzic_base + TZIC_DSMINT) == 0))
return -EAGAIN;
for (i = 0; i < 4; i++) {
v = is_idle ? __raw_readl(TZIC_ENSET0(i)) : wakeup_intr[i];
__raw_writel(v, TZIC_WAKEUP0(i));
}
return 0;
}
drivers/mtd/nand/Kconfig
浏览文件 @ b93a4afc
...@@ -444,7 +444,7 @@ config MTD_NAND_FSL_UPM ...@@ -444,7 +444,7 @@ config MTD_NAND_FSL_UPM
config MTD_NAND_MXC config MTD_NAND_MXC
tristate "MXC NAND support" tristate "MXC NAND support"
depends on ARCH_MX2 || ARCH_MX3 depends on ARCH_MX2 || ARCH_MX25 || ARCH_MX3
help help
This enables the driver for the NAND flash controller on the This enables the driver for the NAND flash controller on the
MXC processors. MXC processors.
......
drivers/serial/imx.c
浏览文件 @ b93a4afc
...@@ -440,7 +440,7 @@ static irqreturn_t imx_rxint(int irq, void *dev_id) ...@@ -440,7 +440,7 @@ static irqreturn_t imx_rxint(int irq, void *dev_id)
temp = readl(sport->port.membase + USR2); temp = readl(sport->port.membase + USR2);
if (temp & USR2_BRCD) { if (temp & USR2_BRCD) {
writel(temp | USR2_BRCD, sport->port.membase + USR2); writel(USR2_BRCD, sport->port.membase + USR2);
if (uart_handle_break(&sport->port)) if (uart_handle_break(&sport->port))
continue; continue;
} }
......
drivers/usb/gadget/fsl_mx3_udc.c
浏览文件 @ b93a4afc
...@@ -17,6 +17,8 @@ ...@@ -17,6 +17,8 @@
#include <linux/fsl_devices.h> #include <linux/fsl_devices.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <mach/hardware.h>
static struct clk *mxc_ahb_clk; static struct clk *mxc_ahb_clk;
static struct clk *mxc_usb_clk; static struct clk *mxc_usb_clk;
...@@ -28,6 +30,7 @@ int fsl_udc_clk_init(struct platform_device *pdev) ...@@ -28,6 +30,7 @@ int fsl_udc_clk_init(struct platform_device *pdev)
pdata = pdev->dev.platform_data; pdata = pdev->dev.platform_data;
if (!cpu_is_mx35()) {
mxc_ahb_clk = clk_get(&pdev->dev, "usb_ahb"); mxc_ahb_clk = clk_get(&pdev->dev, "usb_ahb");
if (IS_ERR(mxc_ahb_clk)) if (IS_ERR(mxc_ahb_clk))
return PTR_ERR(mxc_ahb_clk); return PTR_ERR(mxc_ahb_clk);
...@@ -37,6 +40,7 @@ int fsl_udc_clk_init(struct platform_device *pdev) ...@@ -37,6 +40,7 @@ int fsl_udc_clk_init(struct platform_device *pdev)
dev_err(&pdev->dev, "clk_enable(\"usb_ahb\") failed\n"); dev_err(&pdev->dev, "clk_enable(\"usb_ahb\") failed\n");
goto eenahb; goto eenahb;
} }
}
/* make sure USB_CLK is running at 60 MHz +/- 1000 Hz */ /* make sure USB_CLK is running at 60 MHz +/- 1000 Hz */
mxc_usb_clk = clk_get(&pdev->dev, "usb"); mxc_usb_clk = clk_get(&pdev->dev, "usb");
...@@ -50,6 +54,7 @@ int fsl_udc_clk_init(struct platform_device *pdev) ...@@ -50,6 +54,7 @@ int fsl_udc_clk_init(struct platform_device *pdev)
if (pdata->phy_mode != FSL_USB2_PHY_ULPI && if (pdata->phy_mode != FSL_USB2_PHY_ULPI &&
(freq < 59999000 || freq > 60001000)) { (freq < 59999000 || freq > 60001000)) {
dev_err(&pdev->dev, "USB_CLK=%lu, should be 60MHz\n", freq); dev_err(&pdev->dev, "USB_CLK=%lu, should be 60MHz\n", freq);
ret = -EINVAL;
goto eclkrate; goto eclkrate;
} }
...@@ -66,8 +71,10 @@ int fsl_udc_clk_init(struct platform_device *pdev) ...@@ -66,8 +71,10 @@ int fsl_udc_clk_init(struct platform_device *pdev)
clk_put(mxc_usb_clk); clk_put(mxc_usb_clk);
mxc_usb_clk = NULL; mxc_usb_clk = NULL;
egusb: egusb:
if (!cpu_is_mx35())
clk_disable(mxc_ahb_clk); clk_disable(mxc_ahb_clk);
eenahb: eenahb:
if (!cpu_is_mx35())
clk_put(mxc_ahb_clk); clk_put(mxc_ahb_clk);
return ret; return ret;
} }
...@@ -90,6 +97,8 @@ void fsl_udc_clk_release(void) ...@@ -90,6 +97,8 @@ void fsl_udc_clk_release(void)
clk_disable(mxc_usb_clk); clk_disable(mxc_usb_clk);
clk_put(mxc_usb_clk); clk_put(mxc_usb_clk);
} }
if (!cpu_is_mx35()) {
clk_disable(mxc_ahb_clk); clk_disable(mxc_ahb_clk);
clk_put(mxc_ahb_clk); clk_put(mxc_ahb_clk);
}
} }
drivers/video/Kconfig
浏览文件 @ b93a4afc
...@@ -400,9 +400,12 @@ config FB_SA1100 ...@@ -400,9 +400,12 @@ config FB_SA1100
If you plan to use the LCD display with your SA-1100 system, say If you plan to use the LCD display with your SA-1100 system, say
Y here. Y here.
config HAVE_FB_IMX
bool
config FB_IMX config FB_IMX
tristate "Motorola i.MX LCD support" tristate "Motorola i.MX LCD support"
depends on FB && (ARCH_MX1 || ARCH_MX2) depends on FB && (HAVE_FB_IMX || ARCH_MX1 || ARCH_MX2)
select FB_CFB_FILLRECT select FB_CFB_FILLRECT
select FB_CFB_COPYAREA select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT select FB_CFB_IMAGEBLIT
......
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