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kernel_linux
提交 b360ada3 编写于 作者: M Michael Turquette
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Merge tag 'tegra-for-4.5-clk' of... 

Merge tag 'tegra-for-4.5-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next

clk: tegra: Changes for v4.5-rc1

This set of changes adds support for the Tegra210 SoC and contains a
couple fixes and cleanups.
上级 7ed88aa2 2d7f61f3
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Documentation/devicetree/bindings/clock/nvidia,tegra210-car.txt 0 → 100644
浏览文件 @ b360ada3
NVIDIA Tegra210 Clock And Reset Controller
This binding uses the common clock binding:
Documentation/devicetree/bindings/clock/clock-bindings.txt
The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
for muxing and gating Tegra's clocks, and setting their rates.
Required properties :
- compatible : Should be "nvidia,tegra210-car"
- reg : Should contain CAR registers location and length
- clocks : Should contain phandle and clock specifiers for two clocks:
the 32 KHz "32k_in".
- #clock-cells : Should be 1.
In clock consumers, this cell represents the clock ID exposed by the
CAR. The assignments may be found in header file
<dt-bindings/clock/tegra210-car.h>.
- #reset-cells : Should be 1.
In clock consumers, this cell represents the bit number in the CAR's
array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
Example SoC include file:
/ {
tegra_car: clock {
compatible = "nvidia,tegra210-car";
reg = <0x60006000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
usb@c5004000 {
clocks = <&tegra_car TEGRA210_CLK_USB2>;
};
};
Example board file:
/ {
clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
clk_32k: clock@1 {
compatible = "fixed-clock";
reg = <1>;
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
&tegra_car {
clocks = <&clk_32k>;
};
};
drivers/clk/tegra/Makefile
浏览文件 @ b360ada3
...@@ -20,3 +20,4 @@ obj-$(CONFIG_ARCH_TEGRA_124_SOC) += clk-tegra124.o ...@@ -20,3 +20,4 @@ obj-$(CONFIG_ARCH_TEGRA_124_SOC) += clk-tegra124.o
obj-$(CONFIG_ARCH_TEGRA_124_SOC) += clk-tegra124-dfll-fcpu.o obj-$(CONFIG_ARCH_TEGRA_124_SOC) += clk-tegra124-dfll-fcpu.o
obj-$(CONFIG_ARCH_TEGRA_132_SOC) += clk-tegra124.o obj-$(CONFIG_ARCH_TEGRA_132_SOC) += clk-tegra124.o
obj-y += cvb.o obj-y += cvb.o
obj-$(CONFIG_ARCH_TEGRA_210_SOC) += clk-tegra210.o
drivers/clk/tegra/clk-id.h
浏览文件 @ b360ada3
...@@ -13,6 +13,7 @@ enum clk_id { ...@@ -13,6 +13,7 @@ enum clk_id {
tegra_clk_amx1, tegra_clk_amx1,
tegra_clk_apbdma, tegra_clk_apbdma,
tegra_clk_apbif, tegra_clk_apbif,
tegra_clk_ape,
tegra_clk_audio0, tegra_clk_audio0,
tegra_clk_audio0_2x, tegra_clk_audio0_2x,
tegra_clk_audio0_mux, tegra_clk_audio0_mux,
...@@ -38,6 +39,7 @@ enum clk_id { ...@@ -38,6 +39,7 @@ enum clk_id {
tegra_clk_cile, tegra_clk_cile,
tegra_clk_clk_32k, tegra_clk_clk_32k,
tegra_clk_clk72Mhz, tegra_clk_clk72Mhz,
tegra_clk_clk72Mhz_8,
tegra_clk_clk_m, tegra_clk_clk_m,
tegra_clk_clk_m_div2, tegra_clk_clk_m_div2,
tegra_clk_clk_m_div4, tegra_clk_clk_m_div4,
...@@ -51,17 +53,21 @@ enum clk_id { ...@@ -51,17 +53,21 @@ enum clk_id {
tegra_clk_cml1, tegra_clk_cml1,
tegra_clk_csi, tegra_clk_csi,
tegra_clk_csite, tegra_clk_csite,
tegra_clk_csite_8,
tegra_clk_csus, tegra_clk_csus,
tegra_clk_cve, tegra_clk_cve,
tegra_clk_dam0, tegra_clk_dam0,
tegra_clk_dam1, tegra_clk_dam1,
tegra_clk_dam2, tegra_clk_dam2,
tegra_clk_d_audio, tegra_clk_d_audio,
tegra_clk_dbgapb,
tegra_clk_dds, tegra_clk_dds,
tegra_clk_dfll_ref, tegra_clk_dfll_ref,
tegra_clk_dfll_soc, tegra_clk_dfll_soc,
tegra_clk_disp1, tegra_clk_disp1,
tegra_clk_disp1_8,
tegra_clk_disp2, tegra_clk_disp2,
tegra_clk_disp2_8,
tegra_clk_dp2, tegra_clk_dp2,
tegra_clk_dpaux, tegra_clk_dpaux,
tegra_clk_dsialp, tegra_clk_dsialp,
...@@ -71,6 +77,7 @@ enum clk_id { ...@@ -71,6 +77,7 @@ enum clk_id {
tegra_clk_dtv, tegra_clk_dtv,
tegra_clk_emc, tegra_clk_emc,
tegra_clk_entropy, tegra_clk_entropy,
tegra_clk_entropy_8,
tegra_clk_epp, tegra_clk_epp,
tegra_clk_epp_8, tegra_clk_epp_8,
tegra_clk_extern1, tegra_clk_extern1,
...@@ -85,12 +92,16 @@ enum clk_id { ...@@ -85,12 +92,16 @@ enum clk_id {
tegra_clk_gr3d_8, tegra_clk_gr3d_8,
tegra_clk_hclk, tegra_clk_hclk,
tegra_clk_hda, tegra_clk_hda,
tegra_clk_hda_8,
tegra_clk_hda2codec_2x, tegra_clk_hda2codec_2x,
tegra_clk_hda2codec_2x_8,
tegra_clk_hda2hdmi, tegra_clk_hda2hdmi,
tegra_clk_hdmi, tegra_clk_hdmi,
tegra_clk_hdmi_audio, tegra_clk_hdmi_audio,
tegra_clk_host1x, tegra_clk_host1x,
tegra_clk_host1x_8, tegra_clk_host1x_8,
tegra_clk_host1x_9,
tegra_clk_hsic_trk,
tegra_clk_i2c1, tegra_clk_i2c1,
tegra_clk_i2c2, tegra_clk_i2c2,
tegra_clk_i2c3, tegra_clk_i2c3,
...@@ -110,11 +121,14 @@ enum clk_id { ...@@ -110,11 +121,14 @@ enum clk_id {
tegra_clk_i2s4_sync, tegra_clk_i2s4_sync,
tegra_clk_isp, tegra_clk_isp,
tegra_clk_isp_8, tegra_clk_isp_8,
tegra_clk_isp_9,
tegra_clk_ispb, tegra_clk_ispb,
tegra_clk_kbc, tegra_clk_kbc,
tegra_clk_kfuse, tegra_clk_kfuse,
tegra_clk_la, tegra_clk_la,
tegra_clk_maud,
tegra_clk_mipi, tegra_clk_mipi,
tegra_clk_mipibif,
tegra_clk_mipi_cal, tegra_clk_mipi_cal,
tegra_clk_mpe, tegra_clk_mpe,
tegra_clk_mselect, tegra_clk_mselect,
...@@ -124,15 +138,24 @@ enum clk_id { ...@@ -124,15 +138,24 @@ enum clk_id {
tegra_clk_ndspeed, tegra_clk_ndspeed,
tegra_clk_ndspeed_8, tegra_clk_ndspeed_8,
tegra_clk_nor, tegra_clk_nor,
tegra_clk_nvdec,
tegra_clk_nvenc,
tegra_clk_nvjpg,
tegra_clk_owr, tegra_clk_owr,
tegra_clk_owr_8,
tegra_clk_pcie, tegra_clk_pcie,
tegra_clk_pclk, tegra_clk_pclk,
tegra_clk_pll_a, tegra_clk_pll_a,
tegra_clk_pll_a_out0, tegra_clk_pll_a_out0,
tegra_clk_pll_a1,
tegra_clk_pll_c, tegra_clk_pll_c,
tegra_clk_pll_c2, tegra_clk_pll_c2,
tegra_clk_pll_c3, tegra_clk_pll_c3,
tegra_clk_pll_c4, tegra_clk_pll_c4,
tegra_clk_pll_c4_out0,
tegra_clk_pll_c4_out1,
tegra_clk_pll_c4_out2,
tegra_clk_pll_c4_out3,
tegra_clk_pll_c_out1, tegra_clk_pll_c_out1,
tegra_clk_pll_d, tegra_clk_pll_d,
tegra_clk_pll_d2, tegra_clk_pll_d2,
...@@ -140,19 +163,29 @@ enum clk_id { ...@@ -140,19 +163,29 @@ enum clk_id {
tegra_clk_pll_d_out0, tegra_clk_pll_d_out0,
tegra_clk_pll_dp, tegra_clk_pll_dp,
tegra_clk_pll_e_out0, tegra_clk_pll_e_out0,
tegra_clk_pll_g_ref,
tegra_clk_pll_m, tegra_clk_pll_m,
tegra_clk_pll_m_out1, tegra_clk_pll_m_out1,
tegra_clk_pll_mb,
tegra_clk_pll_p, tegra_clk_pll_p,
tegra_clk_pll_p_out1, tegra_clk_pll_p_out1,
tegra_clk_pll_p_out2, tegra_clk_pll_p_out2,
tegra_clk_pll_p_out2_int, tegra_clk_pll_p_out2_int,
tegra_clk_pll_p_out3, tegra_clk_pll_p_out3,
tegra_clk_pll_p_out4, tegra_clk_pll_p_out4,
tegra_clk_pll_p_out4_cpu,
tegra_clk_pll_p_out5, tegra_clk_pll_p_out5,
tegra_clk_pll_p_out_hsio,
tegra_clk_pll_p_out_xusb,
tegra_clk_pll_p_out_cpu,
tegra_clk_pll_p_out_adsp,
tegra_clk_pll_ref, tegra_clk_pll_ref,
tegra_clk_pll_re_out, tegra_clk_pll_re_out,
tegra_clk_pll_re_vco, tegra_clk_pll_re_vco,
tegra_clk_pll_u, tegra_clk_pll_u,
tegra_clk_pll_u_out,
tegra_clk_pll_u_out1,
tegra_clk_pll_u_out2,
tegra_clk_pll_u_12m, tegra_clk_pll_u_12m,
tegra_clk_pll_u_480m, tegra_clk_pll_u_480m,
tegra_clk_pll_u_48m, tegra_clk_pll_u_48m,
...@@ -160,53 +193,80 @@ enum clk_id { ...@@ -160,53 +193,80 @@ enum clk_id {
tegra_clk_pll_x, tegra_clk_pll_x,
tegra_clk_pll_x_out0, tegra_clk_pll_x_out0,
tegra_clk_pwm, tegra_clk_pwm,
tegra_clk_qspi,
tegra_clk_rtc, tegra_clk_rtc,
tegra_clk_sata, tegra_clk_sata,
tegra_clk_sata_8,
tegra_clk_sata_cold, tegra_clk_sata_cold,
tegra_clk_sata_oob, tegra_clk_sata_oob,
tegra_clk_sata_oob_8,
tegra_clk_sbc1, tegra_clk_sbc1,
tegra_clk_sbc1_8, tegra_clk_sbc1_8,
tegra_clk_sbc1_9,
tegra_clk_sbc2, tegra_clk_sbc2,
tegra_clk_sbc2_8, tegra_clk_sbc2_8,
tegra_clk_sbc2_9,
tegra_clk_sbc3, tegra_clk_sbc3,
tegra_clk_sbc3_8, tegra_clk_sbc3_8,
tegra_clk_sbc3_9,
tegra_clk_sbc4, tegra_clk_sbc4,
tegra_clk_sbc4_8, tegra_clk_sbc4_8,
tegra_clk_sbc4_9,
tegra_clk_sbc5, tegra_clk_sbc5,
tegra_clk_sbc5_8, tegra_clk_sbc5_8,
tegra_clk_sbc6, tegra_clk_sbc6,
tegra_clk_sbc6_8, tegra_clk_sbc6_8,
tegra_clk_sclk, tegra_clk_sclk,
tegra_clk_sdmmc_legacy,
tegra_clk_sdmmc1, tegra_clk_sdmmc1,
tegra_clk_sdmmc1_8, tegra_clk_sdmmc1_8,
tegra_clk_sdmmc1_9,
tegra_clk_sdmmc2, tegra_clk_sdmmc2,
tegra_clk_sdmmc2_8, tegra_clk_sdmmc2_8,
tegra_clk_sdmmc2_9,
tegra_clk_sdmmc3, tegra_clk_sdmmc3,
tegra_clk_sdmmc3_8, tegra_clk_sdmmc3_8,
tegra_clk_sdmmc3_9,
tegra_clk_sdmmc4, tegra_clk_sdmmc4,
tegra_clk_sdmmc4_8, tegra_clk_sdmmc4_8,
tegra_clk_sdmmc4_9,
tegra_clk_se, tegra_clk_se,
tegra_clk_soc_therm, tegra_clk_soc_therm,
tegra_clk_soc_therm_8,
tegra_clk_sor0, tegra_clk_sor0,
tegra_clk_sor0_lvds, tegra_clk_sor0_lvds,
tegra_clk_sor1,
tegra_clk_sor1_brick,
tegra_clk_sor1_src,
tegra_clk_spdif, tegra_clk_spdif,
tegra_clk_spdif_2x, tegra_clk_spdif_2x,
tegra_clk_spdif_in, tegra_clk_spdif_in,
tegra_clk_spdif_in_8,
tegra_clk_spdif_in_sync, tegra_clk_spdif_in_sync,
tegra_clk_spdif_mux, tegra_clk_spdif_mux,
tegra_clk_spdif_out, tegra_clk_spdif_out,
tegra_clk_timer, tegra_clk_timer,
tegra_clk_trace, tegra_clk_trace,
tegra_clk_tsec, tegra_clk_tsec,
tegra_clk_tsec_8,
tegra_clk_tsecb,
tegra_clk_tsensor, tegra_clk_tsensor,
tegra_clk_tvdac, tegra_clk_tvdac,
tegra_clk_tvo, tegra_clk_tvo,
tegra_clk_uarta, tegra_clk_uarta,
tegra_clk_uarta_8,
tegra_clk_uartb, tegra_clk_uartb,
tegra_clk_uartb_8,
tegra_clk_uartc, tegra_clk_uartc,
tegra_clk_uartc_8,
tegra_clk_uartd, tegra_clk_uartd,
tegra_clk_uartd_8,
tegra_clk_uarte, tegra_clk_uarte,
tegra_clk_uarte_8,
tegra_clk_uartape,
tegra_clk_usb2, tegra_clk_usb2,
tegra_clk_usb2_hsic_trk,
tegra_clk_usb2_trk,
tegra_clk_usb3, tegra_clk_usb3,
tegra_clk_usbd, tegra_clk_usbd,
tegra_clk_vcp, tegra_clk_vcp,
...@@ -216,22 +276,35 @@ enum clk_id { ...@@ -216,22 +276,35 @@ enum clk_id {
tegra_clk_vi, tegra_clk_vi,
tegra_clk_vi_8, tegra_clk_vi_8,
tegra_clk_vi_9, tegra_clk_vi_9,
tegra_clk_vi_10,
tegra_clk_vi_i2c,
tegra_clk_vic03, tegra_clk_vic03,
tegra_clk_vic03_8,
tegra_clk_vim2_clk, tegra_clk_vim2_clk,
tegra_clk_vimclk_sync, tegra_clk_vimclk_sync,
tegra_clk_vi_sensor, tegra_clk_vi_sensor,
tegra_clk_vi_sensor2,
tegra_clk_vi_sensor_8, tegra_clk_vi_sensor_8,
tegra_clk_vi_sensor_9,
tegra_clk_vi_sensor2,
tegra_clk_vi_sensor2_8,
tegra_clk_xusb_dev, tegra_clk_xusb_dev,
tegra_clk_xusb_dev_src, tegra_clk_xusb_dev_src,
tegra_clk_xusb_dev_src_8,
tegra_clk_xusb_falcon_src, tegra_clk_xusb_falcon_src,
tegra_clk_xusb_falcon_src_8,
tegra_clk_xusb_fs_src, tegra_clk_xusb_fs_src,
tegra_clk_xusb_gate,
tegra_clk_xusb_host, tegra_clk_xusb_host,
tegra_clk_xusb_host_src, tegra_clk_xusb_host_src,
tegra_clk_xusb_host_src_8,
tegra_clk_xusb_hs_src, tegra_clk_xusb_hs_src,
tegra_clk_xusb_hs_src_4,
tegra_clk_xusb_ss, tegra_clk_xusb_ss,
tegra_clk_xusb_ss_src, tegra_clk_xusb_ss_src,
tegra_clk_xusb_ss_src_8,
tegra_clk_xusb_ss_div2, tegra_clk_xusb_ss_div2,
tegra_clk_xusb_ssp_src,
tegra_clk_sclk_mux,
tegra_clk_max, tegra_clk_max,
}; };
......
drivers/clk/tegra/clk-pll.c
浏览文件 @ b360ada3
此差异已折叠。
drivers/clk/tegra/clk-tegra-super-gen4.c
浏览文件 @ b360ada3
...@@ -34,9 +34,25 @@ ...@@ -34,9 +34,25 @@
#define CCLKLP_BURST_POLICY 0x370 #define CCLKLP_BURST_POLICY 0x370
#define SCLK_BURST_POLICY 0x028 #define SCLK_BURST_POLICY 0x028
#define SYSTEM_CLK_RATE 0x030 #define SYSTEM_CLK_RATE 0x030
#define SCLK_DIVIDER 0x2c
static DEFINE_SPINLOCK(sysrate_lock); static DEFINE_SPINLOCK(sysrate_lock);
enum tegra_super_gen {
gen4 = 4,
gen5,
};
struct tegra_super_gen_info {
enum tegra_super_gen gen;
const char **sclk_parents;
const char **cclk_g_parents;
const char **cclk_lp_parents;
int num_sclk_parents;
int num_cclk_g_parents;
int num_cclk_lp_parents;
};
static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4", static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
"pll_p", "pll_p_out2", "unused", "pll_p", "pll_p_out2", "unused",
"clk_32k", "pll_m_out1" }; "clk_32k", "pll_m_out1" };
...@@ -51,22 +67,82 @@ static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", ...@@ -51,22 +67,82 @@ static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
"pll_p", "pll_p_out4", "unused", "pll_p", "pll_p_out4", "unused",
"unused", "pll_x", "pll_x_out0" }; "unused", "pll_x", "pll_x_out0" };
const struct tegra_super_gen_info tegra_super_gen_info_gen4 = {
.gen = gen4,
.sclk_parents = sclk_parents,
.cclk_g_parents = cclk_g_parents,
.cclk_lp_parents = cclk_lp_parents,
.num_sclk_parents = ARRAY_SIZE(sclk_parents),
.num_cclk_g_parents = ARRAY_SIZE(cclk_g_parents),
.num_cclk_lp_parents = ARRAY_SIZE(cclk_lp_parents),
};
static const char *sclk_parents_gen5[] = { "clk_m", "pll_c_out1", "pll_c4_out3",
"pll_p", "pll_p_out2", "pll_c4_out1",
"clk_32k", "pll_c4_out2" };
static const char *cclk_g_parents_gen5[] = { "clk_m", "unused", "clk_32k", "unused",
"pll_p", "pll_p_out4", "unused",
"unused", "pll_x", "unused", "unused",
"unused", "unused", "unused", "unused",
"dfllCPU_out" };
static const char *cclk_lp_parents_gen5[] = { "clk_m", "unused", "clk_32k", "unused",
"pll_p", "pll_p_out4", "unused",
"unused", "pll_x", "unused", "unused",
"unused", "unused", "unused", "unused",
"dfllCPU_out" };
const struct tegra_super_gen_info tegra_super_gen_info_gen5 = {
.gen = gen5,
.sclk_parents = sclk_parents_gen5,
.cclk_g_parents = cclk_g_parents_gen5,
.cclk_lp_parents = cclk_lp_parents_gen5,
.num_sclk_parents = ARRAY_SIZE(sclk_parents_gen5),
.num_cclk_g_parents = ARRAY_SIZE(cclk_g_parents_gen5),
.num_cclk_lp_parents = ARRAY_SIZE(cclk_lp_parents_gen5),
};
static void __init tegra_sclk_init(void __iomem *clk_base, static void __init tegra_sclk_init(void __iomem *clk_base,
struct tegra_clk *tegra_clks) struct tegra_clk *tegra_clks,
const struct tegra_super_gen_info *gen_info)
{ {
struct clk *clk; struct clk *clk;
struct clk **dt_clk; struct clk **dt_clk;
/* SCLK_MUX */
dt_clk = tegra_lookup_dt_id(tegra_clk_sclk_mux, tegra_clks);
if (dt_clk) {
clk = tegra_clk_register_super_mux("sclk_mux",
gen_info->sclk_parents,
gen_info->num_sclk_parents,
CLK_SET_RATE_PARENT,
clk_base + SCLK_BURST_POLICY,
0, 4, 0, 0, NULL);
*dt_clk = clk;
/* SCLK */ /* SCLK */
dt_clk = tegra_lookup_dt_id(tegra_clk_sclk, tegra_clks); dt_clk = tegra_lookup_dt_id(tegra_clk_sclk, tegra_clks);
if (dt_clk) { if (dt_clk) {
clk = tegra_clk_register_super_mux("sclk", sclk_parents, clk = clk_register_divider(NULL, "sclk", "sclk_mux", 0,
ARRAY_SIZE(sclk_parents), clk_base + SCLK_DIVIDER, 0, 8,
0, &sysrate_lock);
*dt_clk = clk;
}
} else {
/* SCLK */
dt_clk = tegra_lookup_dt_id(tegra_clk_sclk, tegra_clks);
if (dt_clk) {
clk = tegra_clk_register_super_mux("sclk",
gen_info->sclk_parents,
gen_info->num_sclk_parents,
CLK_SET_RATE_PARENT, CLK_SET_RATE_PARENT,
clk_base + SCLK_BURST_POLICY, clk_base + SCLK_BURST_POLICY,
0, 4, 0, 0, NULL); 0, 4, 0, 0, NULL);
*dt_clk = clk; *dt_clk = clk;
} }
}
/* HCLK */ /* HCLK */
dt_clk = tegra_lookup_dt_id(tegra_clk_hclk, tegra_clks); dt_clk = tegra_lookup_dt_id(tegra_clk_hclk, tegra_clks);
...@@ -95,10 +171,11 @@ static void __init tegra_sclk_init(void __iomem *clk_base, ...@@ -95,10 +171,11 @@ static void __init tegra_sclk_init(void __iomem *clk_base,
*dt_clk = clk; *dt_clk = clk;
} }
void __init tegra_super_clk_gen4_init(void __iomem *clk_base, void __init tegra_super_clk_init(void __iomem *clk_base,
void __iomem *pmc_base, void __iomem *pmc_base,
struct tegra_clk *tegra_clks, struct tegra_clk *tegra_clks,
struct tegra_clk_pll_params *params) struct tegra_clk_pll_params *params,
const struct tegra_super_gen_info *gen_info)
{ {
struct clk *clk; struct clk *clk;
struct clk **dt_clk; struct clk **dt_clk;
...@@ -106,28 +183,50 @@ void __init tegra_super_clk_gen4_init(void __iomem *clk_base, ...@@ -106,28 +183,50 @@ void __init tegra_super_clk_gen4_init(void __iomem *clk_base,
/* CCLKG */ /* CCLKG */
dt_clk = tegra_lookup_dt_id(tegra_clk_cclk_g, tegra_clks); dt_clk = tegra_lookup_dt_id(tegra_clk_cclk_g, tegra_clks);
if (dt_clk) { if (dt_clk) {
clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents, if (gen_info->gen == gen5) {
ARRAY_SIZE(cclk_g_parents), clk = tegra_clk_register_super_mux("cclk_g",
gen_info->cclk_g_parents,
gen_info->num_cclk_g_parents,
CLK_SET_RATE_PARENT,
clk_base + CCLKG_BURST_POLICY,
0, 4, 8, 0, NULL);
} else {
clk = tegra_clk_register_super_mux("cclk_g",
gen_info->cclk_g_parents,
gen_info->num_cclk_g_parents,
CLK_SET_RATE_PARENT, CLK_SET_RATE_PARENT,
clk_base + CCLKG_BURST_POLICY, clk_base + CCLKG_BURST_POLICY,
0, 4, 0, 0, NULL); 0, 4, 0, 0, NULL);
}
*dt_clk = clk; *dt_clk = clk;
} }
/* CCLKLP */ /* CCLKLP */
dt_clk = tegra_lookup_dt_id(tegra_clk_cclk_lp, tegra_clks); dt_clk = tegra_lookup_dt_id(tegra_clk_cclk_lp, tegra_clks);
if (dt_clk) { if (dt_clk) {
clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents, if (gen_info->gen == gen5) {
ARRAY_SIZE(cclk_lp_parents), clk = tegra_clk_register_super_mux("cclk_lp",
gen_info->cclk_lp_parents,
gen_info->num_cclk_lp_parents,
CLK_SET_RATE_PARENT,
clk_base + CCLKLP_BURST_POLICY,
0, 4, 8, 0, NULL);
} else {
clk = tegra_clk_register_super_mux("cclk_lp",
gen_info->cclk_lp_parents,
gen_info->num_cclk_lp_parents,
CLK_SET_RATE_PARENT, CLK_SET_RATE_PARENT,
clk_base + CCLKLP_BURST_POLICY, clk_base + CCLKLP_BURST_POLICY,
TEGRA_DIVIDER_2, 4, 8, 9, NULL); TEGRA_DIVIDER_2, 4, 8, 9, NULL);
}
*dt_clk = clk; *dt_clk = clk;
} }
tegra_sclk_init(clk_base, tegra_clks); tegra_sclk_init(clk_base, tegra_clks, gen_info);
#if defined(CONFIG_ARCH_TEGRA_114_SOC) || defined(CONFIG_ARCH_TEGRA_124_SOC) #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
defined(CONFIG_ARCH_TEGRA_124_SOC) || \
defined(CONFIG_ARCH_TEGRA_210_SOC)
/* PLLX */ /* PLLX */
dt_clk = tegra_lookup_dt_id(tegra_clk_pll_x, tegra_clks); dt_clk = tegra_lookup_dt_id(tegra_clk_pll_x, tegra_clks);
if (!dt_clk) if (!dt_clk)
...@@ -148,3 +247,20 @@ void __init tegra_super_clk_gen4_init(void __iomem *clk_base, ...@@ -148,3 +247,20 @@ void __init tegra_super_clk_gen4_init(void __iomem *clk_base,
#endif #endif
} }
void __init tegra_super_clk_gen4_init(void __iomem *clk_base,
void __iomem *pmc_base,
struct tegra_clk *tegra_clks,
struct tegra_clk_pll_params *params)
{
tegra_super_clk_init(clk_base, pmc_base, tegra_clks, params,
&tegra_super_gen_info_gen4);
}
void __init tegra_super_clk_gen5_init(void __iomem *clk_base,
void __iomem *pmc_base,
struct tegra_clk *tegra_clks,
struct tegra_clk_pll_params *params)
{
tegra_super_clk_init(clk_base, pmc_base, tegra_clks, params,
&tegra_super_gen_info_gen5);
}
drivers/clk/tegra/clk-tegra114.c
浏览文件 @ b360ada3
...@@ -182,7 +182,7 @@ static struct div_nmp pllxc_nmp = { ...@@ -182,7 +182,7 @@ static struct div_nmp pllxc_nmp = {
.divp_width = 4, .divp_width = 4,
}; };
static struct pdiv_map pllxc_p[] = { static const struct pdiv_map pllxc_p[] = {
{ .pdiv = 1, .hw_val = 0 }, { .pdiv = 1, .hw_val = 0 },
{ .pdiv = 2, .hw_val = 1 }, { .pdiv = 2, .hw_val = 1 },
{ .pdiv = 3, .hw_val = 2 }, { .pdiv = 3, .hw_val = 2 },
...@@ -202,12 +202,12 @@ static struct pdiv_map pllxc_p[] = { ...@@ -202,12 +202,12 @@ static struct pdiv_map pllxc_p[] = {
}; };
static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
{ 12000000, 624000000, 104, 0, 2}, { 12000000, 624000000, 104, 1, 2, 0 },
{ 12000000, 600000000, 100, 0, 2}, { 12000000, 600000000, 100, 1, 2, 0 },
{ 13000000, 600000000, 92, 0, 2}, /* actual: 598.0 MHz */ { 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */
{ 16800000, 600000000, 71, 0, 2}, /* actual: 596.4 MHz */ { 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */
{ 19200000, 600000000, 62, 0, 2}, /* actual: 595.2 MHz */ { 19200000, 600000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */
{ 26000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */ { 26000000, 600000000, 92, 2, 2, 0 }, /* actual: 598.0 MHz */
{ 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 },
}; };
...@@ -232,7 +232,7 @@ static struct tegra_clk_pll_params pll_c_params = { ...@@ -232,7 +232,7 @@ static struct tegra_clk_pll_params pll_c_params = {
.pdiv_tohw = pllxc_p, .pdiv_tohw = pllxc_p,
.div_nmp = &pllxc_nmp, .div_nmp = &pllxc_nmp,
.freq_table = pll_c_freq_table, .freq_table = pll_c_freq_table,
.flags = TEGRA_PLL_USE_LOCK, .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
}; };
static struct div_nmp pllcx_nmp = { static struct div_nmp pllcx_nmp = {
...@@ -244,7 +244,7 @@ static struct div_nmp pllcx_nmp = { ...@@ -244,7 +244,7 @@ static struct div_nmp pllcx_nmp = {
.divp_width = 3, .divp_width = 3,
}; };
static struct pdiv_map pllc_p[] = { static const struct pdiv_map pllc_p[] = {
{ .pdiv = 1, .hw_val = 0 }, { .pdiv = 1, .hw_val = 0 },
{ .pdiv = 2, .hw_val = 1 }, { .pdiv = 2, .hw_val = 1 },
{ .pdiv = 4, .hw_val = 3 }, { .pdiv = 4, .hw_val = 3 },
...@@ -254,12 +254,12 @@ static struct pdiv_map pllc_p[] = { ...@@ -254,12 +254,12 @@ static struct pdiv_map pllc_p[] = {
}; };
static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = { static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = {
{12000000, 600000000, 100, 0, 2}, { 12000000, 600000000, 100, 1, 2, 0 },
{13000000, 600000000, 92, 0, 2}, /* actual: 598.0 MHz */ { 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */
{16800000, 600000000, 71, 0, 2}, /* actual: 596.4 MHz */ { 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */
{19200000, 600000000, 62, 0, 2}, /* actual: 595.2 MHz */ { 19200000, 600000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */
{26000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */ { 26000000, 600000000, 92, 2, 2, 0 }, /* actual: 598.0 MHz */
{0, 0, 0, 0, 0, 0}, { 0, 0, 0, 0, 0, 0 },
}; };
static struct tegra_clk_pll_params pll_c2_params = { static struct tegra_clk_pll_params pll_c2_params = {
...@@ -318,19 +318,19 @@ static struct div_nmp pllm_nmp = { ...@@ -318,19 +318,19 @@ static struct div_nmp pllm_nmp = {
.override_divp_shift = 27, .override_divp_shift = 27,
}; };
static struct pdiv_map pllm_p[] = { static const struct pdiv_map pllm_p[] = {
{ .pdiv = 1, .hw_val = 0 }, { .pdiv = 1, .hw_val = 0 },
{ .pdiv = 2, .hw_val = 1 }, { .pdiv = 2, .hw_val = 1 },
{ .pdiv = 0, .hw_val = 0 }, { .pdiv = 0, .hw_val = 0 },
}; };
static struct tegra_clk_pll_freq_table pll_m_freq_table[] = { static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
{12000000, 800000000, 66, 0, 1}, /* actual: 792.0 MHz */ { 12000000, 800000000, 66, 1, 1, 0 }, /* actual: 792.0 MHz */
{13000000, 800000000, 61, 0, 1}, /* actual: 793.0 MHz */ { 13000000, 800000000, 61, 1, 1, 0 }, /* actual: 793.0 MHz */
{16800000, 800000000, 47, 0, 1}, /* actual: 789.6 MHz */ { 16800000, 800000000, 47, 1, 1, 0 }, /* actual: 789.6 MHz */
{19200000, 800000000, 41, 0, 1}, /* actual: 787.2 MHz */ { 19200000, 800000000, 41, 1, 1, 0 }, /* actual: 787.2 MHz */
{26000000, 800000000, 61, 1, 1}, /* actual: 793.0 MHz */ { 26000000, 800000000, 61, 2, 1, 0 }, /* actual: 793.0 MHz */
{0, 0, 0, 0, 0, 0}, { 0, 0, 0, 0, 0, 0 },
}; };
static struct tegra_clk_pll_params pll_m_params = { static struct tegra_clk_pll_params pll_m_params = {
...@@ -351,7 +351,8 @@ static struct tegra_clk_pll_params pll_m_params = { ...@@ -351,7 +351,8 @@ static struct tegra_clk_pll_params pll_m_params = {
.pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE, .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
.pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2, .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2,
.freq_table = pll_m_freq_table, .freq_table = pll_m_freq_table,
.flags = TEGRA_PLL_USE_LOCK, .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE |
TEGRA_PLL_FIXED,
}; };
static struct div_nmp pllp_nmp = { static struct div_nmp pllp_nmp = {
...@@ -364,12 +365,12 @@ static struct div_nmp pllp_nmp = { ...@@ -364,12 +365,12 @@ static struct div_nmp pllp_nmp = {
}; };
static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
{12000000, 216000000, 432, 12, 1, 8}, { 12000000, 216000000, 432, 12, 2, 8 },
{13000000, 216000000, 432, 13, 1, 8}, { 13000000, 216000000, 432, 13, 2, 8 },
{16800000, 216000000, 360, 14, 1, 8}, { 16800000, 216000000, 360, 14, 2, 8 },
{19200000, 216000000, 360, 16, 1, 8}, { 19200000, 216000000, 360, 16, 2, 8 },
{26000000, 216000000, 432, 26, 1, 8}, { 26000000, 216000000, 432, 26, 2, 8 },
{0, 0, 0, 0, 0, 0}, { 0, 0, 0, 0, 0, 0 },
}; };
static struct tegra_clk_pll_params pll_p_params = { static struct tegra_clk_pll_params pll_p_params = {
...@@ -386,19 +387,19 @@ static struct tegra_clk_pll_params pll_p_params = { ...@@ -386,19 +387,19 @@ static struct tegra_clk_pll_params pll_p_params = {
.lock_delay = 300, .lock_delay = 300,
.div_nmp = &pllp_nmp, .div_nmp = &pllp_nmp,
.freq_table = pll_p_freq_table, .freq_table = pll_p_freq_table,
.flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK, .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK |
TEGRA_PLL_HAS_LOCK_ENABLE,
.fixed_rate = 408000000, .fixed_rate = 408000000,
}; };
static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
{9600000, 282240000, 147, 5, 0, 4}, { 9600000, 282240000, 147, 5, 1, 4 },
{9600000, 368640000, 192, 5, 0, 4}, { 9600000, 368640000, 192, 5, 1, 4 },
{9600000, 240000000, 200, 8, 0, 8}, { 9600000, 240000000, 200, 8, 1, 8 },
{ 28800000, 282240000, 245, 25, 1, 8 },
{28800000, 282240000, 245, 25, 0, 8}, { 28800000, 368640000, 320, 25, 1, 8 },
{28800000, 368640000, 320, 25, 0, 8}, { 28800000, 240000000, 200, 24, 1, 8 },
{28800000, 240000000, 200, 24, 0, 8}, { 0, 0, 0, 0, 0, 0 },
{0, 0, 0, 0, 0, 0},
}; };
...@@ -416,28 +417,26 @@ static struct tegra_clk_pll_params pll_a_params = { ...@@ -416,28 +417,26 @@ static struct tegra_clk_pll_params pll_a_params = {
.lock_delay = 300, .lock_delay = 300,
.div_nmp = &pllp_nmp, .div_nmp = &pllp_nmp,
.freq_table = pll_a_freq_table, .freq_table = pll_a_freq_table,
.flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK, .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK |
TEGRA_PLL_HAS_LOCK_ENABLE,
}; };
static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
{12000000, 216000000, 864, 12, 2, 12}, { 12000000, 216000000, 864, 12, 4, 12 },
{13000000, 216000000, 864, 13, 2, 12}, { 13000000, 216000000, 864, 13, 4, 12 },
{16800000, 216000000, 720, 14, 2, 12}, { 16800000, 216000000, 720, 14, 4, 12 },
{19200000, 216000000, 720, 16, 2, 12}, { 19200000, 216000000, 720, 16, 4, 12 },
{26000000, 216000000, 864, 26, 2, 12}, { 26000000, 216000000, 864, 26, 4, 12 },
{ 12000000, 594000000, 594, 12, 1, 12 },
{12000000, 594000000, 594, 12, 0, 12}, { 13000000, 594000000, 594, 13, 1, 12 },
{13000000, 594000000, 594, 13, 0, 12}, { 16800000, 594000000, 495, 14, 1, 12 },
{16800000, 594000000, 495, 14, 0, 12}, { 19200000, 594000000, 495, 16, 1, 12 },
{19200000, 594000000, 495, 16, 0, 12}, { 26000000, 594000000, 594, 26, 1, 12 },
{26000000, 594000000, 594, 26, 0, 12}, { 12000000, 1000000000, 1000, 12, 1, 12 },
{ 13000000, 1000000000, 1000, 13, 1, 12 },
{12000000, 1000000000, 1000, 12, 0, 12}, { 19200000, 1000000000, 625, 12, 1, 12 },
{13000000, 1000000000, 1000, 13, 0, 12}, { 26000000, 1000000000, 1000, 26, 1, 12 },
{19200000, 1000000000, 625, 12, 0, 12}, { 0, 0, 0, 0, 0, 0 },
{26000000, 1000000000, 1000, 26, 0, 12},
{0, 0, 0, 0, 0, 0},
}; };
static struct tegra_clk_pll_params pll_d_params = { static struct tegra_clk_pll_params pll_d_params = {
...@@ -455,7 +454,7 @@ static struct tegra_clk_pll_params pll_d_params = { ...@@ -455,7 +454,7 @@ static struct tegra_clk_pll_params pll_d_params = {
.div_nmp = &pllp_nmp, .div_nmp = &pllp_nmp,
.freq_table = pll_d_freq_table, .freq_table = pll_d_freq_table,
.flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
TEGRA_PLL_USE_LOCK, TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
}; };
static struct tegra_clk_pll_params pll_d2_params = { static struct tegra_clk_pll_params pll_d2_params = {
...@@ -473,10 +472,10 @@ static struct tegra_clk_pll_params pll_d2_params = { ...@@ -473,10 +472,10 @@ static struct tegra_clk_pll_params pll_d2_params = {
.div_nmp = &pllp_nmp, .div_nmp = &pllp_nmp,
.freq_table = pll_d_freq_table, .freq_table = pll_d_freq_table,
.flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
TEGRA_PLL_USE_LOCK, TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
}; };
static struct pdiv_map pllu_p[] = { static const struct pdiv_map pllu_p[] = {
{ .pdiv = 1, .hw_val = 1 }, { .pdiv = 1, .hw_val = 1 },
{ .pdiv = 2, .hw_val = 0 }, { .pdiv = 2, .hw_val = 0 },
{ .pdiv = 0, .hw_val = 0 }, { .pdiv = 0, .hw_val = 0 },
...@@ -492,12 +491,12 @@ static struct div_nmp pllu_nmp = { ...@@ -492,12 +491,12 @@ static struct div_nmp pllu_nmp = {
}; };
static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
{12000000, 480000000, 960, 12, 0, 12}, { 12000000, 480000000, 960, 12, 2, 12 },
{13000000, 480000000, 960, 13, 0, 12}, { 13000000, 480000000, 960, 13, 2, 12 },
{16800000, 480000000, 400, 7, 0, 5}, { 16800000, 480000000, 400, 7, 2, 5 },
{19200000, 480000000, 200, 4, 0, 3}, { 19200000, 480000000, 200, 4, 2, 3 },
{26000000, 480000000, 960, 26, 0, 12}, { 26000000, 480000000, 960, 26, 2, 12 },
{0, 0, 0, 0, 0, 0}, { 0, 0, 0, 0, 0, 0 },
}; };
static struct tegra_clk_pll_params pll_u_params = { static struct tegra_clk_pll_params pll_u_params = {
...@@ -516,18 +515,17 @@ static struct tegra_clk_pll_params pll_u_params = { ...@@ -516,18 +515,17 @@ static struct tegra_clk_pll_params pll_u_params = {
.div_nmp = &pllu_nmp, .div_nmp = &pllu_nmp,
.freq_table = pll_u_freq_table, .freq_table = pll_u_freq_table,
.flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
TEGRA_PLL_USE_LOCK, TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
}; };
static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
/* 1 GHz */ /* 1 GHz */
{12000000, 1000000000, 83, 0, 1}, /* actual: 996.0 MHz */ { 12000000, 1000000000, 83, 1, 1, 0 }, /* actual: 996.0 MHz */
{13000000, 1000000000, 76, 0, 1}, /* actual: 988.0 MHz */ { 13000000, 1000000000, 76, 1, 1, 0 }, /* actual: 988.0 MHz */
{16800000, 1000000000, 59, 0, 1}, /* actual: 991.2 MHz */ { 16800000, 1000000000, 59, 1, 1, 0 }, /* actual: 991.2 MHz */
{19200000, 1000000000, 52, 0, 1}, /* actual: 998.4 MHz */ { 19200000, 1000000000, 52, 1, 1, 0 }, /* actual: 998.4 MHz */
{26000000, 1000000000, 76, 1, 1}, /* actual: 988.0 MHz */ { 26000000, 1000000000, 76, 2, 1, 0 }, /* actual: 988.0 MHz */
{ 0, 0, 0, 0, 0, 0 },
{0, 0, 0, 0, 0, 0},
}; };
static struct tegra_clk_pll_params pll_x_params = { static struct tegra_clk_pll_params pll_x_params = {
...@@ -551,15 +549,34 @@ static struct tegra_clk_pll_params pll_x_params = { ...@@ -551,15 +549,34 @@ static struct tegra_clk_pll_params pll_x_params = {
.pdiv_tohw = pllxc_p, .pdiv_tohw = pllxc_p,
.div_nmp = &pllxc_nmp, .div_nmp = &pllxc_nmp,
.freq_table = pll_x_freq_table, .freq_table = pll_x_freq_table,
.flags = TEGRA_PLL_USE_LOCK, .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
}; };
static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
/* PLLE special case: use cpcon field to store cml divider value */ /* PLLE special case: use cpcon field to store cml divider value */
{336000000, 100000000, 100, 21, 16, 11}, { 336000000, 100000000, 100, 21, 16, 11 },
{312000000, 100000000, 200, 26, 24, 13}, { 312000000, 100000000, 200, 26, 24, 13 },
{12000000, 100000000, 200, 1, 24, 13}, { 12000000, 100000000, 200, 1, 24, 13 },
{0, 0, 0, 0, 0, 0}, { 0, 0, 0, 0, 0, 0 },
};
static const struct pdiv_map plle_p[] = {
{ .pdiv = 1, .hw_val = 0 },
{ .pdiv = 2, .hw_val = 1 },
{ .pdiv = 3, .hw_val = 2 },
{ .pdiv = 4, .hw_val = 3 },
{ .pdiv = 5, .hw_val = 4 },
{ .pdiv = 6, .hw_val = 5 },
{ .pdiv = 8, .hw_val = 6 },
{ .pdiv = 10, .hw_val = 7 },
{ .pdiv = 12, .hw_val = 8 },
{ .pdiv = 16, .hw_val = 9 },
{ .pdiv = 12, .hw_val = 10 },
{ .pdiv = 16, .hw_val = 11 },
{ .pdiv = 20, .hw_val = 12 },
{ .pdiv = 24, .hw_val = 13 },
{ .pdiv = 32, .hw_val = 14 },
{ .pdiv = 0, .hw_val = 0 }
}; };
static struct div_nmp plle_nmp = { static struct div_nmp plle_nmp = {
...@@ -584,9 +601,10 @@ static struct tegra_clk_pll_params pll_e_params = { ...@@ -584,9 +601,10 @@ static struct tegra_clk_pll_params pll_e_params = {
.lock_mask = PLLE_MISC_LOCK, .lock_mask = PLLE_MISC_LOCK,
.lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
.lock_delay = 300, .lock_delay = 300,
.pdiv_tohw = plle_p,
.div_nmp = &plle_nmp, .div_nmp = &plle_nmp,
.freq_table = pll_e_freq_table, .freq_table = pll_e_freq_table,
.flags = TEGRA_PLL_FIXED, .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_LOCK_ENABLE,
.fixed_rate = 100000000, .fixed_rate = 100000000,
}; };
...@@ -614,18 +632,19 @@ static struct tegra_clk_pll_params pll_re_vco_params = { ...@@ -614,18 +632,19 @@ static struct tegra_clk_pll_params pll_re_vco_params = {
.iddq_reg = PLLRE_MISC, .iddq_reg = PLLRE_MISC,
.iddq_bit_idx = PLLRE_IDDQ_BIT, .iddq_bit_idx = PLLRE_IDDQ_BIT,
.div_nmp = &pllre_nmp, .div_nmp = &pllre_nmp,
.flags = TEGRA_PLL_USE_LOCK, .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE |
TEGRA_PLL_LOCK_MISC,
}; };
/* possible OSC frequencies in Hz */ /* possible OSC frequencies in Hz */
static unsigned long tegra114_input_freq[] = { static unsigned long tegra114_input_freq[] = {
[0] = 13000000, [ 0] = 13000000,
[1] = 16800000, [ 1] = 16800000,
[4] = 19200000, [ 4] = 19200000,
[5] = 38400000, [ 5] = 38400000,
[8] = 12000000, [ 8] = 12000000,
[9] = 48000000, [ 9] = 48000000,
[12] = 260000000, [12] = 26000000,
}; };
#define MASK(x) (BIT(x) - 1) #define MASK(x) (BIT(x) - 1)
...@@ -644,21 +663,27 @@ struct utmi_clk_param { ...@@ -644,21 +663,27 @@ struct utmi_clk_param {
}; };
static const struct utmi_clk_param utmi_parameters[] = { static const struct utmi_clk_param utmi_parameters[] = {
{.osc_frequency = 13000000, .enable_delay_count = 0x02, {
.osc_frequency = 13000000, .enable_delay_count = 0x02,
.stable_count = 0x33, .active_delay_count = 0x05, .stable_count = 0x33, .active_delay_count = 0x05,
.xtal_freq_count = 0x7F}, .xtal_freq_count = 0x7f
{.osc_frequency = 19200000, .enable_delay_count = 0x03, }, {
.stable_count = 0x4B, .active_delay_count = 0x06, .osc_frequency = 19200000, .enable_delay_count = 0x03,
.xtal_freq_count = 0xBB}, .stable_count = 0x4b, .active_delay_count = 0x06,
{.osc_frequency = 12000000, .enable_delay_count = 0x02, .xtal_freq_count = 0xbb
.stable_count = 0x2F, .active_delay_count = 0x04, }, {
.xtal_freq_count = 0x76}, .osc_frequency = 12000000, .enable_delay_count = 0x02,
{.osc_frequency = 26000000, .enable_delay_count = 0x04, .stable_count = 0x2f, .active_delay_count = 0x04,
.xtal_freq_count = 0x76
}, {
.osc_frequency = 26000000, .enable_delay_count = 0x04,
.stable_count = 0x66, .active_delay_count = 0x09, .stable_count = 0x66, .active_delay_count = 0x09,
.xtal_freq_count = 0xFE}, .xtal_freq_count = 0xfe
{.osc_frequency = 16800000, .enable_delay_count = 0x03, }, {
.stable_count = 0x41, .active_delay_count = 0x0A, .osc_frequency = 16800000, .enable_delay_count = 0x03,
.xtal_freq_count = 0xA4}, .stable_count = 0x41, .active_delay_count = 0x0a,
.xtal_freq_count = 0xa4
},
}; };
/* peripheral mux definitions */ /* peripheral mux definitions */
...@@ -965,8 +990,8 @@ static void __init tegra114_fixed_clk_init(void __iomem *clk_base) ...@@ -965,8 +990,8 @@ static void __init tegra114_fixed_clk_init(void __iomem *clk_base)
static __init void tegra114_utmi_param_configure(void __iomem *clk_base) static __init void tegra114_utmi_param_configure(void __iomem *clk_base)
{ {
unsigned int i;
u32 reg; u32 reg;
int i;
for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) { for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
if (osc_freq == utmi_parameters[i].osc_frequency) if (osc_freq == utmi_parameters[i].osc_frequency)
...@@ -1173,7 +1198,7 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base, ...@@ -1173,7 +1198,7 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base,
{ {
struct clk *clk; struct clk *clk;
struct tegra_periph_init_data *data; struct tegra_periph_init_data *data;
int i; unsigned int i;
/* xusb_ss_div2 */ /* xusb_ss_div2 */
clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0, clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0,
...@@ -1278,7 +1303,7 @@ static struct tegra_cpu_car_ops tegra114_cpu_car_ops = { ...@@ -1278,7 +1303,7 @@ static struct tegra_cpu_car_ops tegra114_cpu_car_ops = {
static const struct of_device_id pmc_match[] __initconst = { static const struct of_device_id pmc_match[] __initconst = {
{ .compatible = "nvidia,tegra114-pmc" }, { .compatible = "nvidia,tegra114-pmc" },
{}, { },
}; };
/* /*
...@@ -1286,37 +1311,37 @@ static const struct of_device_id pmc_match[] __initconst = { ...@@ -1286,37 +1311,37 @@ static const struct of_device_id pmc_match[] __initconst = {
* breaks * breaks
*/ */
static struct tegra_clk_init_table init_table[] __initdata = { static struct tegra_clk_init_table init_table[] __initdata = {
{TEGRA114_CLK_UARTA, TEGRA114_CLK_PLL_P, 408000000, 0}, { TEGRA114_CLK_UARTA, TEGRA114_CLK_PLL_P, 408000000, 0 },
{TEGRA114_CLK_UARTB, TEGRA114_CLK_PLL_P, 408000000, 0}, { TEGRA114_CLK_UARTB, TEGRA114_CLK_PLL_P, 408000000, 0 },
{TEGRA114_CLK_UARTC, TEGRA114_CLK_PLL_P, 408000000, 0}, { TEGRA114_CLK_UARTC, TEGRA114_CLK_PLL_P, 408000000, 0 },
{TEGRA114_CLK_UARTD, TEGRA114_CLK_PLL_P, 408000000, 0}, { TEGRA114_CLK_UARTD, TEGRA114_CLK_PLL_P, 408000000, 0 },
{TEGRA114_CLK_PLL_A, TEGRA114_CLK_CLK_MAX, 564480000, 1}, { TEGRA114_CLK_PLL_A, TEGRA114_CLK_CLK_MAX, 564480000, 1 },
{TEGRA114_CLK_PLL_A_OUT0, TEGRA114_CLK_CLK_MAX, 11289600, 1}, { TEGRA114_CLK_PLL_A_OUT0, TEGRA114_CLK_CLK_MAX, 11289600, 1 },
{TEGRA114_CLK_EXTERN1, TEGRA114_CLK_PLL_A_OUT0, 0, 1}, { TEGRA114_CLK_EXTERN1, TEGRA114_CLK_PLL_A_OUT0, 0, 1 },
{TEGRA114_CLK_CLK_OUT_1_MUX, TEGRA114_CLK_EXTERN1, 0, 1}, { TEGRA114_CLK_CLK_OUT_1_MUX, TEGRA114_CLK_EXTERN1, 0, 1 },
{TEGRA114_CLK_CLK_OUT_1, TEGRA114_CLK_CLK_MAX, 0, 1}, { TEGRA114_CLK_CLK_OUT_1, TEGRA114_CLK_CLK_MAX, 0, 1 },
{TEGRA114_CLK_I2S0, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0}, { TEGRA114_CLK_I2S0, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
{TEGRA114_CLK_I2S1, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0}, { TEGRA114_CLK_I2S1, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
{TEGRA114_CLK_I2S2, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0}, { TEGRA114_CLK_I2S2, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
{TEGRA114_CLK_I2S3, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0}, { TEGRA114_CLK_I2S3, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
{TEGRA114_CLK_I2S4, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0}, { TEGRA114_CLK_I2S4, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
{TEGRA114_CLK_HOST1X, TEGRA114_CLK_PLL_P, 136000000, 0}, { TEGRA114_CLK_HOST1X, TEGRA114_CLK_PLL_P, 136000000, 0 },
{TEGRA114_CLK_DFLL_SOC, TEGRA114_CLK_PLL_P, 51000000, 1}, { TEGRA114_CLK_DFLL_SOC, TEGRA114_CLK_PLL_P, 51000000, 1 },
{TEGRA114_CLK_DFLL_REF, TEGRA114_CLK_PLL_P, 51000000, 1}, { TEGRA114_CLK_DFLL_REF, TEGRA114_CLK_PLL_P, 51000000, 1 },
{TEGRA114_CLK_DISP1, TEGRA114_CLK_PLL_P, 0, 0}, { TEGRA114_CLK_DISP1, TEGRA114_CLK_PLL_P, 0, 0 },
{TEGRA114_CLK_DISP2, TEGRA114_CLK_PLL_P, 0, 0}, { TEGRA114_CLK_DISP2, TEGRA114_CLK_PLL_P, 0, 0 },
{TEGRA114_CLK_GR2D, TEGRA114_CLK_PLL_C2, 300000000, 0}, { TEGRA114_CLK_GR2D, TEGRA114_CLK_PLL_C2, 300000000, 0 },
{TEGRA114_CLK_GR3D, TEGRA114_CLK_PLL_C2, 300000000, 0}, { TEGRA114_CLK_GR3D, TEGRA114_CLK_PLL_C2, 300000000, 0 },
{TEGRA114_CLK_DSIALP, TEGRA114_CLK_PLL_P, 68000000, 0}, { TEGRA114_CLK_DSIALP, TEGRA114_CLK_PLL_P, 68000000, 0 },
{TEGRA114_CLK_DSIBLP, TEGRA114_CLK_PLL_P, 68000000, 0}, { TEGRA114_CLK_DSIBLP, TEGRA114_CLK_PLL_P, 68000000, 0 },
{TEGRA114_CLK_PLL_RE_VCO, TEGRA114_CLK_CLK_MAX, 612000000, 0}, { TEGRA114_CLK_PLL_RE_VCO, TEGRA114_CLK_CLK_MAX, 612000000, 0 },
{TEGRA114_CLK_XUSB_SS_SRC, TEGRA114_CLK_PLL_RE_OUT, 122400000, 0}, { TEGRA114_CLK_XUSB_SS_SRC, TEGRA114_CLK_PLL_RE_OUT, 122400000, 0 },
{TEGRA114_CLK_XUSB_FS_SRC, TEGRA114_CLK_PLL_U_48M, 48000000, 0}, { TEGRA114_CLK_XUSB_FS_SRC, TEGRA114_CLK_PLL_U_48M, 48000000, 0 },
{TEGRA114_CLK_XUSB_HS_SRC, TEGRA114_CLK_XUSB_SS_DIV2, 61200000, 0}, { TEGRA114_CLK_XUSB_HS_SRC, TEGRA114_CLK_XUSB_SS_DIV2, 61200000, 0 },
{TEGRA114_CLK_XUSB_FALCON_SRC, TEGRA114_CLK_PLL_P, 204000000, 0}, { TEGRA114_CLK_XUSB_FALCON_SRC, TEGRA114_CLK_PLL_P, 204000000, 0 },
{TEGRA114_CLK_XUSB_HOST_SRC, TEGRA114_CLK_PLL_P, 102000000, 0}, { TEGRA114_CLK_XUSB_HOST_SRC, TEGRA114_CLK_PLL_P, 102000000, 0 },
/* This MUST be the last entry. */ /* must be the last entry */
{TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_CLK_MAX, 0, 0}, { TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_CLK_MAX, 0, 0 },
}; };
static void __init tegra114_clock_apply_init_table(void) static void __init tegra114_clock_apply_init_table(void)
......
drivers/clk/tegra/clk-tegra124.c
浏览文件 @ b360ada3
此差异已折叠。
drivers/clk/tegra/clk-tegra20.c
浏览文件 @ b360ada3
...@@ -166,125 +166,119 @@ static DEFINE_SPINLOCK(emc_lock); ...@@ -166,125 +166,119 @@ static DEFINE_SPINLOCK(emc_lock);
static struct clk **clks; static struct clk **clks;
static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
{ 12000000, 600000000, 600, 12, 0, 8 }, { 12000000, 600000000, 600, 12, 1, 8 },
{ 13000000, 600000000, 600, 13, 0, 8 }, { 13000000, 600000000, 600, 13, 1, 8 },
{ 19200000, 600000000, 500, 16, 0, 6 }, { 19200000, 600000000, 500, 16, 1, 6 },
{ 26000000, 600000000, 600, 26, 0, 8 }, { 26000000, 600000000, 600, 26, 1, 8 },
{ 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 },
}; };
static struct tegra_clk_pll_freq_table pll_m_freq_table[] = { static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
{ 12000000, 666000000, 666, 12, 0, 8}, { 12000000, 666000000, 666, 12, 1, 8 },
{ 13000000, 666000000, 666, 13, 0, 8}, { 13000000, 666000000, 666, 13, 1, 8 },
{ 19200000, 666000000, 555, 16, 0, 8}, { 19200000, 666000000, 555, 16, 1, 8 },
{ 26000000, 666000000, 666, 26, 0, 8}, { 26000000, 666000000, 666, 26, 1, 8 },
{ 12000000, 600000000, 600, 12, 0, 8}, { 12000000, 600000000, 600, 12, 1, 8 },
{ 13000000, 600000000, 600, 13, 0, 8}, { 13000000, 600000000, 600, 13, 1, 8 },
{ 19200000, 600000000, 375, 12, 0, 6}, { 19200000, 600000000, 375, 12, 1, 6 },
{ 26000000, 600000000, 600, 26, 0, 8}, { 26000000, 600000000, 600, 26, 1, 8 },
{ 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 },
}; };
static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
{ 12000000, 216000000, 432, 12, 1, 8}, { 12000000, 216000000, 432, 12, 2, 8 },
{ 13000000, 216000000, 432, 13, 1, 8}, { 13000000, 216000000, 432, 13, 2, 8 },
{ 19200000, 216000000, 90, 4, 1, 1}, { 19200000, 216000000, 90, 4, 2, 1 },
{ 26000000, 216000000, 432, 26, 1, 8}, { 26000000, 216000000, 432, 26, 2, 8 },
{ 12000000, 432000000, 432, 12, 0, 8}, { 12000000, 432000000, 432, 12, 1, 8 },
{ 13000000, 432000000, 432, 13, 0, 8}, { 13000000, 432000000, 432, 13, 1, 8 },
{ 19200000, 432000000, 90, 4, 0, 1}, { 19200000, 432000000, 90, 4, 1, 1 },
{ 26000000, 432000000, 432, 26, 0, 8}, { 26000000, 432000000, 432, 26, 1, 8 },
{ 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 },
}; };
static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
{ 28800000, 56448000, 49, 25, 0, 1}, { 28800000, 56448000, 49, 25, 1, 1 },
{ 28800000, 73728000, 64, 25, 0, 1}, { 28800000, 73728000, 64, 25, 1, 1 },
{ 28800000, 24000000, 5, 6, 0, 1}, { 28800000, 24000000, 5, 6, 1, 1 },
{ 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 },
}; };
static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
{ 12000000, 216000000, 216, 12, 0, 4}, { 12000000, 216000000, 216, 12, 1, 4 },
{ 13000000, 216000000, 216, 13, 0, 4}, { 13000000, 216000000, 216, 13, 1, 4 },
{ 19200000, 216000000, 135, 12, 0, 3}, { 19200000, 216000000, 135, 12, 1, 3 },
{ 26000000, 216000000, 216, 26, 0, 4}, { 26000000, 216000000, 216, 26, 1, 4 },
{ 12000000, 594000000, 594, 12, 1, 8 },
{ 12000000, 594000000, 594, 12, 0, 8}, { 13000000, 594000000, 594, 13, 1, 8 },
{ 13000000, 594000000, 594, 13, 0, 8}, { 19200000, 594000000, 495, 16, 1, 8 },
{ 19200000, 594000000, 495, 16, 0, 8}, { 26000000, 594000000, 594, 26, 1, 8 },
{ 26000000, 594000000, 594, 26, 0, 8}, { 12000000, 1000000000, 1000, 12, 1, 12 },
{ 13000000, 1000000000, 1000, 13, 1, 12 },
{ 12000000, 1000000000, 1000, 12, 0, 12}, { 19200000, 1000000000, 625, 12, 1, 8 },
{ 13000000, 1000000000, 1000, 13, 0, 12}, { 26000000, 1000000000, 1000, 26, 1, 12 },
{ 19200000, 1000000000, 625, 12, 0, 8},
{ 26000000, 1000000000, 1000, 26, 0, 12},
{ 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 },
}; };
static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
{ 12000000, 480000000, 960, 12, 0, 0}, { 12000000, 480000000, 960, 12, 1, 0 },
{ 13000000, 480000000, 960, 13, 0, 0}, { 13000000, 480000000, 960, 13, 1, 0 },
{ 19200000, 480000000, 200, 4, 0, 0}, { 19200000, 480000000, 200, 4, 1, 0 },
{ 26000000, 480000000, 960, 26, 0, 0}, { 26000000, 480000000, 960, 26, 1, 0 },
{ 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 },
}; };
static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
/* 1 GHz */ /* 1 GHz */
{ 12000000, 1000000000, 1000, 12, 0, 12}, { 12000000, 1000000000, 1000, 12, 1, 12 },
{ 13000000, 1000000000, 1000, 13, 0, 12}, { 13000000, 1000000000, 1000, 13, 1, 12 },
{ 19200000, 1000000000, 625, 12, 0, 8}, { 19200000, 1000000000, 625, 12, 1, 8 },
{ 26000000, 1000000000, 1000, 26, 0, 12}, { 26000000, 1000000000, 1000, 26, 1, 12 },
/* 912 MHz */ /* 912 MHz */
{ 12000000, 912000000, 912, 12, 0, 12}, { 12000000, 912000000, 912, 12, 1, 12 },
{ 13000000, 912000000, 912, 13, 0, 12}, { 13000000, 912000000, 912, 13, 1, 12 },
{ 19200000, 912000000, 760, 16, 0, 8}, { 19200000, 912000000, 760, 16, 1, 8 },
{ 26000000, 912000000, 912, 26, 0, 12}, { 26000000, 912000000, 912, 26, 1, 12 },
/* 816 MHz */ /* 816 MHz */
{ 12000000, 816000000, 816, 12, 0, 12}, { 12000000, 816000000, 816, 12, 1, 12 },
{ 13000000, 816000000, 816, 13, 0, 12}, { 13000000, 816000000, 816, 13, 1, 12 },
{ 19200000, 816000000, 680, 16, 0, 8}, { 19200000, 816000000, 680, 16, 1, 8 },
{ 26000000, 816000000, 816, 26, 0, 12}, { 26000000, 816000000, 816, 26, 1, 12 },
/* 760 MHz */ /* 760 MHz */
{ 12000000, 760000000, 760, 12, 0, 12}, { 12000000, 760000000, 760, 12, 1, 12 },
{ 13000000, 760000000, 760, 13, 0, 12}, { 13000000, 760000000, 760, 13, 1, 12 },
{ 19200000, 760000000, 950, 24, 0, 8}, { 19200000, 760000000, 950, 24, 1, 8 },
{ 26000000, 760000000, 760, 26, 0, 12}, { 26000000, 760000000, 760, 26, 1, 12 },
/* 750 MHz */ /* 750 MHz */
{ 12000000, 750000000, 750, 12, 0, 12}, { 12000000, 750000000, 750, 12, 1, 12 },
{ 13000000, 750000000, 750, 13, 0, 12}, { 13000000, 750000000, 750, 13, 1, 12 },
{ 19200000, 750000000, 625, 16, 0, 8}, { 19200000, 750000000, 625, 16, 1, 8 },
{ 26000000, 750000000, 750, 26, 0, 12}, { 26000000, 750000000, 750, 26, 1, 12 },
/* 608 MHz */ /* 608 MHz */
{ 12000000, 608000000, 608, 12, 0, 12}, { 12000000, 608000000, 608, 12, 1, 12 },
{ 13000000, 608000000, 608, 13, 0, 12}, { 13000000, 608000000, 608, 13, 1, 12 },
{ 19200000, 608000000, 380, 12, 0, 8}, { 19200000, 608000000, 380, 12, 1, 8 },
{ 26000000, 608000000, 608, 26, 0, 12}, { 26000000, 608000000, 608, 26, 1, 12 },
/* 456 MHz */ /* 456 MHz */
{ 12000000, 456000000, 456, 12, 0, 12}, { 12000000, 456000000, 456, 12, 1, 12 },
{ 13000000, 456000000, 456, 13, 0, 12}, { 13000000, 456000000, 456, 13, 1, 12 },
{ 19200000, 456000000, 380, 16, 0, 8}, { 19200000, 456000000, 380, 16, 1, 8 },
{ 26000000, 456000000, 456, 26, 0, 12}, { 26000000, 456000000, 456, 26, 1, 12 },
/* 312 MHz */ /* 312 MHz */
{ 12000000, 312000000, 312, 12, 0, 12}, { 12000000, 312000000, 312, 12, 1, 12 },
{ 13000000, 312000000, 312, 13, 0, 12}, { 13000000, 312000000, 312, 13, 1, 12 },
{ 19200000, 312000000, 260, 16, 0, 8}, { 19200000, 312000000, 260, 16, 1, 8 },
{ 26000000, 312000000, 312, 26, 0, 12}, { 26000000, 312000000, 312, 26, 1, 12 },
{ 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 },
}; };
static const struct pdiv_map plle_p[] = {
{ .pdiv = 1, .hw_val = 1 },
{ .pdiv = 0, .hw_val = 0 },
};
static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
{ 12000000, 100000000, 200, 24, 0, 0 }, { 12000000, 100000000, 200, 24, 1, 0 },
{ 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 },
}; };
...@@ -302,7 +296,7 @@ static struct tegra_clk_pll_params pll_c_params = { ...@@ -302,7 +296,7 @@ static struct tegra_clk_pll_params pll_c_params = {
.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
.lock_delay = 300, .lock_delay = 300,
.freq_table = pll_c_freq_table, .freq_table = pll_c_freq_table,
.flags = TEGRA_PLL_HAS_CPCON, .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,
}; };
static struct tegra_clk_pll_params pll_m_params = { static struct tegra_clk_pll_params pll_m_params = {
...@@ -318,7 +312,7 @@ static struct tegra_clk_pll_params pll_m_params = { ...@@ -318,7 +312,7 @@ static struct tegra_clk_pll_params pll_m_params = {
.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
.lock_delay = 300, .lock_delay = 300,
.freq_table = pll_m_freq_table, .freq_table = pll_m_freq_table,
.flags = TEGRA_PLL_HAS_CPCON, .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,
}; };
static struct tegra_clk_pll_params pll_p_params = { static struct tegra_clk_pll_params pll_p_params = {
...@@ -334,7 +328,8 @@ static struct tegra_clk_pll_params pll_p_params = { ...@@ -334,7 +328,8 @@ static struct tegra_clk_pll_params pll_p_params = {
.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
.lock_delay = 300, .lock_delay = 300,
.freq_table = pll_p_freq_table, .freq_table = pll_p_freq_table,
.flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON, .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON |
TEGRA_PLL_HAS_LOCK_ENABLE,
.fixed_rate = 216000000, .fixed_rate = 216000000,
}; };
...@@ -351,7 +346,7 @@ static struct tegra_clk_pll_params pll_a_params = { ...@@ -351,7 +346,7 @@ static struct tegra_clk_pll_params pll_a_params = {
.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
.lock_delay = 300, .lock_delay = 300,
.freq_table = pll_a_freq_table, .freq_table = pll_a_freq_table,
.flags = TEGRA_PLL_HAS_CPCON, .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,
}; };
static struct tegra_clk_pll_params pll_d_params = { static struct tegra_clk_pll_params pll_d_params = {
...@@ -367,10 +362,10 @@ static struct tegra_clk_pll_params pll_d_params = { ...@@ -367,10 +362,10 @@ static struct tegra_clk_pll_params pll_d_params = {
.lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
.lock_delay = 1000, .lock_delay = 1000,
.freq_table = pll_d_freq_table, .freq_table = pll_d_freq_table,
.flags = TEGRA_PLL_HAS_CPCON, .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,
}; };
static struct pdiv_map pllu_p[] = { static const struct pdiv_map pllu_p[] = {
{ .pdiv = 1, .hw_val = 1 }, { .pdiv = 1, .hw_val = 1 },
{ .pdiv = 2, .hw_val = 0 }, { .pdiv = 2, .hw_val = 0 },
{ .pdiv = 0, .hw_val = 0 }, { .pdiv = 0, .hw_val = 0 },
...@@ -390,7 +385,7 @@ static struct tegra_clk_pll_params pll_u_params = { ...@@ -390,7 +385,7 @@ static struct tegra_clk_pll_params pll_u_params = {
.lock_delay = 1000, .lock_delay = 1000,
.pdiv_tohw = pllu_p, .pdiv_tohw = pllu_p,
.freq_table = pll_u_freq_table, .freq_table = pll_u_freq_table,
.flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON, .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,
}; };
static struct tegra_clk_pll_params pll_x_params = { static struct tegra_clk_pll_params pll_x_params = {
...@@ -406,7 +401,7 @@ static struct tegra_clk_pll_params pll_x_params = { ...@@ -406,7 +401,7 @@ static struct tegra_clk_pll_params pll_x_params = {
.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
.lock_delay = 300, .lock_delay = 300,
.freq_table = pll_x_freq_table, .freq_table = pll_x_freq_table,
.flags = TEGRA_PLL_HAS_CPCON, .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,
}; };
static struct tegra_clk_pll_params pll_e_params = { static struct tegra_clk_pll_params pll_e_params = {
...@@ -421,8 +416,10 @@ static struct tegra_clk_pll_params pll_e_params = { ...@@ -421,8 +416,10 @@ static struct tegra_clk_pll_params pll_e_params = {
.lock_mask = PLLE_MISC_LOCK, .lock_mask = PLLE_MISC_LOCK,
.lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
.lock_delay = 0, .lock_delay = 0,
.pdiv_tohw = plle_p,
.freq_table = pll_e_freq_table, .freq_table = pll_e_freq_table,
.flags = TEGRA_PLL_FIXED, .flags = TEGRA_PLL_FIXED | TEGRA_PLL_LOCK_MISC |
TEGRA_PLL_HAS_LOCK_ENABLE,
.fixed_rate = 100000000, .fixed_rate = 100000000,
}; };
...@@ -733,9 +730,9 @@ static void tegra20_super_clk_init(void) ...@@ -733,9 +730,9 @@ static void tegra20_super_clk_init(void)
clks[TEGRA20_CLK_TWD] = clk; clks[TEGRA20_CLK_TWD] = clk;
} }
static const char *audio_parents[] = {"spdif_in", "i2s1", "i2s2", "unused", static const char *audio_parents[] = { "spdif_in", "i2s1", "i2s2", "unused",
"pll_a_out0", "unused", "unused", "pll_a_out0", "unused", "unused",
"unused"}; "unused" };
static void __init tegra20_audio_clk_init(void) static void __init tegra20_audio_clk_init(void)
{ {
...@@ -759,19 +756,18 @@ static void __init tegra20_audio_clk_init(void) ...@@ -759,19 +756,18 @@ static void __init tegra20_audio_clk_init(void)
CLK_SET_RATE_PARENT, 89, CLK_SET_RATE_PARENT, 89,
periph_clk_enb_refcnt); periph_clk_enb_refcnt);
clks[TEGRA20_CLK_AUDIO_2X] = clk; clks[TEGRA20_CLK_AUDIO_2X] = clk;
} }
static const char *i2s1_parents[] = {"pll_a_out0", "audio_2x", "pll_p", static const char *i2s1_parents[] = { "pll_a_out0", "audio_2x", "pll_p",
"clk_m"}; "clk_m" };
static const char *i2s2_parents[] = {"pll_a_out0", "audio_2x", "pll_p", static const char *i2s2_parents[] = { "pll_a_out0", "audio_2x", "pll_p",
"clk_m"}; "clk_m" };
static const char *pwm_parents[] = {"pll_p", "pll_c", "audio", "clk_m", static const char *pwm_parents[] = { "pll_p", "pll_c", "audio", "clk_m",
"clk_32k"}; "clk_32k" };
static const char *mux_pllpcm_clkm[] = {"pll_p", "pll_c", "pll_m", "clk_m"}; static const char *mux_pllpcm_clkm[] = { "pll_p", "pll_c", "pll_m", "clk_m" };
static const char *mux_pllpdc_clkm[] = {"pll_p", "pll_d_out0", "pll_c", static const char *mux_pllpdc_clkm[] = { "pll_p", "pll_d_out0", "pll_c",
"clk_m"}; "clk_m" };
static const char *mux_pllmcp_clkm[] = {"pll_m", "pll_c", "pll_p", "clk_m"}; static const char *mux_pllmcp_clkm[] = { "pll_m", "pll_c", "pll_p", "clk_m" };
static struct tegra_periph_init_data tegra_periph_clk_list[] = { static struct tegra_periph_init_data tegra_periph_clk_list[] = {
TEGRA_INIT_DATA_MUX("i2s1", i2s1_parents, CLK_SOURCE_I2S1, 11, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2S1), TEGRA_INIT_DATA_MUX("i2s1", i2s1_parents, CLK_SOURCE_I2S1, 11, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2S1),
...@@ -802,7 +798,7 @@ static void __init tegra20_periph_clk_init(void) ...@@ -802,7 +798,7 @@ static void __init tegra20_periph_clk_init(void)
{ {
struct tegra_periph_init_data *data; struct tegra_periph_init_data *data;
struct clk *clk; struct clk *clk;
int i; unsigned int i;
/* ac97 */ /* ac97 */
clk = tegra_clk_register_periph_gate("ac97", "pll_a_out0", clk = tegra_clk_register_periph_gate("ac97", "pll_a_out0",
...@@ -1025,44 +1021,45 @@ static struct tegra_cpu_car_ops tegra20_cpu_car_ops = { ...@@ -1025,44 +1021,45 @@ static struct tegra_cpu_car_ops tegra20_cpu_car_ops = {
}; };
static struct tegra_clk_init_table init_table[] __initdata = { static struct tegra_clk_init_table init_table[] __initdata = {
{TEGRA20_CLK_PLL_P, TEGRA20_CLK_CLK_MAX, 216000000, 1}, { TEGRA20_CLK_PLL_P, TEGRA20_CLK_CLK_MAX, 216000000, 1 },
{TEGRA20_CLK_PLL_P_OUT1, TEGRA20_CLK_CLK_MAX, 28800000, 1}, { TEGRA20_CLK_PLL_P_OUT1, TEGRA20_CLK_CLK_MAX, 28800000, 1 },
{TEGRA20_CLK_PLL_P_OUT2, TEGRA20_CLK_CLK_MAX, 48000000, 1}, { TEGRA20_CLK_PLL_P_OUT2, TEGRA20_CLK_CLK_MAX, 48000000, 1 },
{TEGRA20_CLK_PLL_P_OUT3, TEGRA20_CLK_CLK_MAX, 72000000, 1}, { TEGRA20_CLK_PLL_P_OUT3, TEGRA20_CLK_CLK_MAX, 72000000, 1 },
{TEGRA20_CLK_PLL_P_OUT4, TEGRA20_CLK_CLK_MAX, 24000000, 1}, { TEGRA20_CLK_PLL_P_OUT4, TEGRA20_CLK_CLK_MAX, 24000000, 1 },
{TEGRA20_CLK_PLL_C, TEGRA20_CLK_CLK_MAX, 600000000, 1}, { TEGRA20_CLK_PLL_C, TEGRA20_CLK_CLK_MAX, 600000000, 1 },
{TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 120000000, 1}, { TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 120000000, 1 },
{TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 0, 1}, { TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 0, 1 },
{TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 0, 1}, { TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 0, 1 },
{TEGRA20_CLK_PCLK, TEGRA20_CLK_CLK_MAX, 60000000, 1}, { TEGRA20_CLK_PCLK, TEGRA20_CLK_CLK_MAX, 60000000, 1 },
{TEGRA20_CLK_CSITE, TEGRA20_CLK_CLK_MAX, 0, 1}, { TEGRA20_CLK_CSITE, TEGRA20_CLK_CLK_MAX, 0, 1 },
{TEGRA20_CLK_EMC, TEGRA20_CLK_CLK_MAX, 0, 1}, { TEGRA20_CLK_EMC, TEGRA20_CLK_CLK_MAX, 0, 1 },
{TEGRA20_CLK_CCLK, TEGRA20_CLK_CLK_MAX, 0, 1}, { TEGRA20_CLK_CCLK, TEGRA20_CLK_CLK_MAX, 0, 1 },
{TEGRA20_CLK_UARTA, TEGRA20_CLK_PLL_P, 0, 0}, { TEGRA20_CLK_UARTA, TEGRA20_CLK_PLL_P, 0, 0 },
{TEGRA20_CLK_UARTB, TEGRA20_CLK_PLL_P, 0, 0}, { TEGRA20_CLK_UARTB, TEGRA20_CLK_PLL_P, 0, 0 },
{TEGRA20_CLK_UARTC, TEGRA20_CLK_PLL_P, 0, 0}, { TEGRA20_CLK_UARTC, TEGRA20_CLK_PLL_P, 0, 0 },
{TEGRA20_CLK_UARTD, TEGRA20_CLK_PLL_P, 0, 0}, { TEGRA20_CLK_UARTD, TEGRA20_CLK_PLL_P, 0, 0 },
{TEGRA20_CLK_UARTE, TEGRA20_CLK_PLL_P, 0, 0}, { TEGRA20_CLK_UARTE, TEGRA20_CLK_PLL_P, 0, 0 },
{TEGRA20_CLK_PLL_A, TEGRA20_CLK_CLK_MAX, 56448000, 1}, { TEGRA20_CLK_PLL_A, TEGRA20_CLK_CLK_MAX, 56448000, 1 },
{TEGRA20_CLK_PLL_A_OUT0, TEGRA20_CLK_CLK_MAX, 11289600, 1}, { TEGRA20_CLK_PLL_A_OUT0, TEGRA20_CLK_CLK_MAX, 11289600, 1 },
{TEGRA20_CLK_CDEV1, TEGRA20_CLK_CLK_MAX, 0, 1}, { TEGRA20_CLK_CDEV1, TEGRA20_CLK_CLK_MAX, 0, 1 },
{TEGRA20_CLK_BLINK, TEGRA20_CLK_CLK_MAX, 32768, 1}, { TEGRA20_CLK_BLINK, TEGRA20_CLK_CLK_MAX, 32768, 1 },
{TEGRA20_CLK_I2S1, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0}, { TEGRA20_CLK_I2S1, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 },
{TEGRA20_CLK_I2S2, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0}, { TEGRA20_CLK_I2S2, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 },
{TEGRA20_CLK_SDMMC1, TEGRA20_CLK_PLL_P, 48000000, 0}, { TEGRA20_CLK_SDMMC1, TEGRA20_CLK_PLL_P, 48000000, 0 },
{TEGRA20_CLK_SDMMC3, TEGRA20_CLK_PLL_P, 48000000, 0}, { TEGRA20_CLK_SDMMC3, TEGRA20_CLK_PLL_P, 48000000, 0 },
{TEGRA20_CLK_SDMMC4, TEGRA20_CLK_PLL_P, 48000000, 0}, { TEGRA20_CLK_SDMMC4, TEGRA20_CLK_PLL_P, 48000000, 0 },
{TEGRA20_CLK_SPI, TEGRA20_CLK_PLL_P, 20000000, 0}, { TEGRA20_CLK_SPI, TEGRA20_CLK_PLL_P, 20000000, 0 },
{TEGRA20_CLK_SBC1, TEGRA20_CLK_PLL_P, 100000000, 0}, { TEGRA20_CLK_SBC1, TEGRA20_CLK_PLL_P, 100000000, 0 },
{TEGRA20_CLK_SBC2, TEGRA20_CLK_PLL_P, 100000000, 0}, { TEGRA20_CLK_SBC2, TEGRA20_CLK_PLL_P, 100000000, 0 },
{TEGRA20_CLK_SBC3, TEGRA20_CLK_PLL_P, 100000000, 0}, { TEGRA20_CLK_SBC3, TEGRA20_CLK_PLL_P, 100000000, 0 },
{TEGRA20_CLK_SBC4, TEGRA20_CLK_PLL_P, 100000000, 0}, { TEGRA20_CLK_SBC4, TEGRA20_CLK_PLL_P, 100000000, 0 },
{TEGRA20_CLK_HOST1X, TEGRA20_CLK_PLL_C, 150000000, 0}, { TEGRA20_CLK_HOST1X, TEGRA20_CLK_PLL_C, 150000000, 0 },
{TEGRA20_CLK_DISP1, TEGRA20_CLK_PLL_P, 600000000, 0}, { TEGRA20_CLK_DISP1, TEGRA20_CLK_PLL_P, 600000000, 0 },
{TEGRA20_CLK_DISP2, TEGRA20_CLK_PLL_P, 600000000, 0}, { TEGRA20_CLK_DISP2, TEGRA20_CLK_PLL_P, 600000000, 0 },
{TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 300000000, 0}, { TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 300000000, 0 },
{TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0}, { TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0 },
{TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0}, /* This MUST be the last entry */ /* must be the last entry */
{ TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0 },
}; };
static void __init tegra20_clock_apply_init_table(void) static void __init tegra20_clock_apply_init_table(void)
...@@ -1080,12 +1077,13 @@ static struct tegra_clk_duplicate tegra_clk_duplicates[] = { ...@@ -1080,12 +1077,13 @@ static struct tegra_clk_duplicate tegra_clk_duplicates[] = {
TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "tegra-ehci.0", NULL), TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "tegra-ehci.0", NULL),
TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "tegra-otg", NULL), TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "tegra-otg", NULL),
TEGRA_CLK_DUPLICATE(TEGRA20_CLK_CCLK, NULL, "cpu"), TEGRA_CLK_DUPLICATE(TEGRA20_CLK_CCLK, NULL, "cpu"),
TEGRA_CLK_DUPLICATE(TEGRA20_CLK_CLK_MAX, NULL, NULL), /* Must be the last entry */ /* must be the last entry */
TEGRA_CLK_DUPLICATE(TEGRA20_CLK_CLK_MAX, NULL, NULL),
}; };
static const struct of_device_id pmc_match[] __initconst = { static const struct of_device_id pmc_match[] __initconst = {
{ .compatible = "nvidia,tegra20-pmc" }, { .compatible = "nvidia,tegra20-pmc" },
{}, { },
}; };
static void __init tegra20_clock_init(struct device_node *np) static void __init tegra20_clock_init(struct device_node *np)
......
drivers/clk/tegra/clk-tegra210.c 0 → 100644
浏览文件 @ b360ada3
此差异已折叠。
drivers/clk/tegra/clk-tegra30.c
浏览文件 @ b360ada3
此差异已折叠。
drivers/clk/tegra/clk.h
浏览文件 @ b360ada3
...@@ -110,14 +110,16 @@ struct clk *tegra_clk_register_mc(const char *name, const char *parent_name, ...@@ -110,14 +110,16 @@ struct clk *tegra_clk_register_mc(const char *name, const char *parent_name,
* @m: input divider * @m: input divider
* @p: post divider * @p: post divider
* @cpcon: charge pump current * @cpcon: charge pump current
* @sdm_data: fraction divider setting (0 = disabled)
*/ */
struct tegra_clk_pll_freq_table { struct tegra_clk_pll_freq_table {
unsigned long input_rate; unsigned long input_rate;
unsigned long output_rate; unsigned long output_rate;
u16 n; u32 n;
u16 m; u16 m;
u8 p; u8 p;
u8 cpcon; u8 cpcon;
u16 sdm_data;
}; };
/** /**
...@@ -156,6 +158,10 @@ struct div_nmp { ...@@ -156,6 +158,10 @@ struct div_nmp {
u8 override_divp_shift; u8 override_divp_shift;
}; };
#define MAX_PLL_MISC_REG_COUNT 6
struct tegra_clk_pll;
/** /**
* struct tegra_clk_pll_params - PLL parameters * struct tegra_clk_pll_params - PLL parameters
* *
...@@ -172,6 +178,14 @@ struct div_nmp { ...@@ -172,6 +178,14 @@ struct div_nmp {
* @lock_enable_bit_idx: Bit index to enable PLL lock * @lock_enable_bit_idx: Bit index to enable PLL lock
* @iddq_reg: PLL IDDQ register offset * @iddq_reg: PLL IDDQ register offset
* @iddq_bit_idx: Bit index to enable PLL IDDQ * @iddq_bit_idx: Bit index to enable PLL IDDQ
* @reset_reg: Register offset of where RESET bit is
* @reset_bit_idx: Shift of reset bit in reset_reg
* @sdm_din_reg: Register offset where SDM settings are
* @sdm_din_mask: Mask of SDM divider bits
* @sdm_ctrl_reg: Register offset where SDM enable is
* @sdm_ctrl_en_mask: Mask of SDM enable bit
* @ssc_ctrl_reg: Register offset where SSC settings are
* @ssc_ctrl_en_mask: Mask of SSC enable bit
* @aux_reg: AUX register offset * @aux_reg: AUX register offset
* @dyn_ramp_reg: Dynamic ramp control register offset * @dyn_ramp_reg: Dynamic ramp control register offset
* @ext_misc_reg: Miscellaneous control register offsets * @ext_misc_reg: Miscellaneous control register offsets
...@@ -182,10 +196,27 @@ struct div_nmp { ...@@ -182,10 +196,27 @@ struct div_nmp {
* @stepb_shift: Dynamic ramp step B field shift * @stepb_shift: Dynamic ramp step B field shift
* @lock_delay: Delay in us if PLL lock is not used * @lock_delay: Delay in us if PLL lock is not used
* @max_p: maximum value for the p divider * @max_p: maximum value for the p divider
* @defaults_set: Boolean signaling all reg defaults for PLL set.
* @pdiv_tohw: mapping of p divider to register values * @pdiv_tohw: mapping of p divider to register values
* @div_nmp: offsets and widths on n, m and p fields * @div_nmp: offsets and widths on n, m and p fields
* @freq_table: array of frequencies supported by PLL * @freq_table: array of frequencies supported by PLL
* @fixed_rate: PLL rate if it is fixed * @fixed_rate: PLL rate if it is fixed
* @mdiv_default: Default value for fixed mdiv for this PLL
* @round_p_to_pdiv: Callback used to round p to the closed pdiv
* @set_gain: Callback to adjust N div for SDM enabled
* PLL's based on fractional divider value.
* @calc_rate: Callback used to change how out of table
* rates (dividers and multipler) are calculated.
* @adjust_vco: Callback to adjust the programming range of the
* divider range (if SDM is present)
* @set_defaults: Callback which will try to initialize PLL
* registers to sane default values. This is first
* tried during PLL registration, but if the PLL
* is already enabled, it will be done the first
* time the rate is changed while the PLL is
* disabled.
* @dyn_ramp: Callback which can be used to define a custom
* dynamic ramp function for a given PLL.
* *
* Flags: * Flags:
* TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for
...@@ -207,6 +238,11 @@ struct div_nmp { ...@@ -207,6 +238,11 @@ struct div_nmp {
* base register. * base register.
* TEGRA_PLL_BYPASS - PLL has bypass bit * TEGRA_PLL_BYPASS - PLL has bypass bit
* TEGRA_PLL_HAS_LOCK_ENABLE - PLL has bit to enable lock monitoring * TEGRA_PLL_HAS_LOCK_ENABLE - PLL has bit to enable lock monitoring
* TEGRA_MDIV_NEW - Switch to new method for calculating fixed mdiv
* it may be more accurate (especially if SDM present)
* TEGRA_PLLMB - PLLMB has should be treated similar to PLLM. This
* flag indicated that it is PLLMB.
* TEGRA_PLL_VCO_OUT - Used to indicate that the PLL has a VCO output
*/ */
struct tegra_clk_pll_params { struct tegra_clk_pll_params {
unsigned long input_min; unsigned long input_min;
...@@ -223,9 +259,17 @@ struct tegra_clk_pll_params { ...@@ -223,9 +259,17 @@ struct tegra_clk_pll_params {
u32 lock_enable_bit_idx; u32 lock_enable_bit_idx;
u32 iddq_reg; u32 iddq_reg;
u32 iddq_bit_idx; u32 iddq_bit_idx;
u32 reset_reg;
u32 reset_bit_idx;
u32 sdm_din_reg;
u32 sdm_din_mask;
u32 sdm_ctrl_reg;
u32 sdm_ctrl_en_mask;
u32 ssc_ctrl_reg;
u32 ssc_ctrl_en_mask;
u32 aux_reg; u32 aux_reg;
u32 dyn_ramp_reg; u32 dyn_ramp_reg;
u32 ext_misc_reg[3]; u32 ext_misc_reg[MAX_PLL_MISC_REG_COUNT];
u32 pmc_divnm_reg; u32 pmc_divnm_reg;
u32 pmc_divp_reg; u32 pmc_divp_reg;
u32 flags; u32 flags;
...@@ -233,10 +277,22 @@ struct tegra_clk_pll_params { ...@@ -233,10 +277,22 @@ struct tegra_clk_pll_params {
int stepb_shift; int stepb_shift;
int lock_delay; int lock_delay;
int max_p; int max_p;
struct pdiv_map *pdiv_tohw; bool defaults_set;
const struct pdiv_map *pdiv_tohw;
struct div_nmp *div_nmp; struct div_nmp *div_nmp;
struct tegra_clk_pll_freq_table *freq_table; struct tegra_clk_pll_freq_table *freq_table;
unsigned long fixed_rate; unsigned long fixed_rate;
u16 mdiv_default;
u32 (*round_p_to_pdiv)(u32 p, u32 *pdiv);
void (*set_gain)(struct tegra_clk_pll_freq_table *cfg);
int (*calc_rate)(struct clk_hw *hw,
struct tegra_clk_pll_freq_table *cfg,
unsigned long rate, unsigned long parent_rate);
unsigned long (*adjust_vco)(struct tegra_clk_pll_params *pll_params,
unsigned long parent_rate);
void (*set_defaults)(struct tegra_clk_pll *pll);
int (*dyn_ramp)(struct tegra_clk_pll *pll,
struct tegra_clk_pll_freq_table *cfg);
}; };
#define TEGRA_PLL_USE_LOCK BIT(0) #define TEGRA_PLL_USE_LOCK BIT(0)
...@@ -250,6 +306,9 @@ struct tegra_clk_pll_params { ...@@ -250,6 +306,9 @@ struct tegra_clk_pll_params {
#define TEGRA_PLL_LOCK_MISC BIT(8) #define TEGRA_PLL_LOCK_MISC BIT(8)
#define TEGRA_PLL_BYPASS BIT(9) #define TEGRA_PLL_BYPASS BIT(9)
#define TEGRA_PLL_HAS_LOCK_ENABLE BIT(10) #define TEGRA_PLL_HAS_LOCK_ENABLE BIT(10)
#define TEGRA_MDIV_NEW BIT(11)
#define TEGRA_PLLMB BIT(12)
#define TEGRA_PLL_VCO_OUT BIT(13)
/** /**
* struct tegra_clk_pll - Tegra PLL clock * struct tegra_clk_pll - Tegra PLL clock
...@@ -303,6 +362,12 @@ struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name, ...@@ -303,6 +362,12 @@ struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
struct tegra_clk_pll_params *pll_params, struct tegra_clk_pll_params *pll_params,
spinlock_t *lock); spinlock_t *lock);
struct clk *tegra_clk_register_pllxc_tegra210(const char *name,
const char *parent_name, void __iomem *clk_base,
void __iomem *pmc, unsigned long flags,
struct tegra_clk_pll_params *pll_params,
spinlock_t *lock);
struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name, struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
void __iomem *clk_base, void __iomem *pmc, void __iomem *clk_base, void __iomem *pmc,
unsigned long flags, unsigned long flags,
...@@ -327,11 +392,35 @@ struct clk *tegra_clk_register_plle_tegra114(const char *name, ...@@ -327,11 +392,35 @@ struct clk *tegra_clk_register_plle_tegra114(const char *name,
struct tegra_clk_pll_params *pll_params, struct tegra_clk_pll_params *pll_params,
spinlock_t *lock); spinlock_t *lock);
struct clk *tegra_clk_register_plle_tegra210(const char *name,
const char *parent_name,
void __iomem *clk_base, unsigned long flags,
struct tegra_clk_pll_params *pll_params,
spinlock_t *lock);
struct clk *tegra_clk_register_pllc_tegra210(const char *name,
const char *parent_name, void __iomem *clk_base,
void __iomem *pmc, unsigned long flags,
struct tegra_clk_pll_params *pll_params,
spinlock_t *lock);
struct clk *tegra_clk_register_pllss_tegra210(const char *name,
const char *parent_name, void __iomem *clk_base,
unsigned long flags,
struct tegra_clk_pll_params *pll_params,
spinlock_t *lock);
struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name, struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
void __iomem *clk_base, unsigned long flags, void __iomem *clk_base, unsigned long flags,
struct tegra_clk_pll_params *pll_params, struct tegra_clk_pll_params *pll_params,
spinlock_t *lock); spinlock_t *lock);
struct clk *tegra_clk_register_pllmb(const char *name, const char *parent_name,
void __iomem *clk_base, void __iomem *pmc,
unsigned long flags,
struct tegra_clk_pll_params *pll_params,
spinlock_t *lock);
/** /**
* struct tegra_clk_pll_out - PLL divider down clock * struct tegra_clk_pll_out - PLL divider down clock
* *
...@@ -653,6 +742,9 @@ int tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks, ...@@ -653,6 +742,9 @@ int tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
void tegra_super_clk_gen4_init(void __iomem *clk_base, void tegra_super_clk_gen4_init(void __iomem *clk_base,
void __iomem *pmc_base, struct tegra_clk *tegra_clks, void __iomem *pmc_base, struct tegra_clk *tegra_clks,
struct tegra_clk_pll_params *pll_params); struct tegra_clk_pll_params *pll_params);
void tegra_super_clk_gen5_init(void __iomem *clk_base,
void __iomem *pmc_base, struct tegra_clk *tegra_clks,
struct tegra_clk_pll_params *pll_params);
#ifdef CONFIG_TEGRA_CLK_EMC #ifdef CONFIG_TEGRA_CLK_EMC
struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np, struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np,
...@@ -674,5 +766,8 @@ void tegra114_clock_deassert_dfll_dvco_reset(void); ...@@ -674,5 +766,8 @@ void tegra114_clock_deassert_dfll_dvco_reset(void);
typedef void (*tegra_clk_apply_init_table_func)(void); typedef void (*tegra_clk_apply_init_table_func)(void);
extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table; extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll);
u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate);
int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div);
#endif /* TEGRA_CLK_H */ #endif /* TEGRA_CLK_H */
include/dt-bindings/clock/tegra210-car.h 0 → 100644
浏览文件 @ b360ada3
/*
* This header provides constants for binding nvidia,tegra210-car.
*
* The first 224 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
* registers. These IDs often match those in the CAR's RST_DEVICES registers,
* but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
* this case, those clocks are assigned IDs above 224 in order to highlight
* this issue. Implementations that interpret these clock IDs as bit values
* within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
* explicitly handle these special cases.
*
* The balance of the clocks controlled by the CAR are assigned IDs of 224 and
* above.
*/
#ifndef _DT_BINDINGS_CLOCK_TEGRA210_CAR_H
#define _DT_BINDINGS_CLOCK_TEGRA210_CAR_H
/* 0 */
/* 1 */
/* 2 */
#define TEGRA210_CLK_ISPB 3
#define TEGRA210_CLK_RTC 4
#define TEGRA210_CLK_TIMER 5
#define TEGRA210_CLK_UARTA 6
/* 7 (register bit affects uartb and vfir) */
#define TEGRA210_CLK_GPIO 8
#define TEGRA210_CLK_SDMMC2 9
/* 10 (register bit affects spdif_in and spdif_out) */
#define TEGRA210_CLK_I2S1 11
#define TEGRA210_CLK_I2C1 12
/* 13 */
#define TEGRA210_CLK_SDMMC1 14
#define TEGRA210_CLK_SDMMC4 15
/* 16 */
#define TEGRA210_CLK_PWM 17
#define TEGRA210_CLK_I2S2 18
/* 19 */
/* 20 (register bit affects vi and vi_sensor) */
/* 21 */
#define TEGRA210_CLK_USBD 22
#define TEGRA210_CLK_ISP 23
/* 24 */
/* 25 */
#define TEGRA210_CLK_DISP2 26
#define TEGRA210_CLK_DISP1 27
#define TEGRA210_CLK_HOST1X 28
/* 29 */
#define TEGRA210_CLK_I2S0 30
/* 31 */
#define TEGRA210_CLK_MC 32
#define TEGRA210_CLK_AHBDMA 33
#define TEGRA210_CLK_APBDMA 34
/* 35 */
/* 36 */
/* 37 */
#define TEGRA210_CLK_PMC 38
/* 39 (register bit affects fuse and fuse_burn) */
#define TEGRA210_CLK_KFUSE 40
#define TEGRA210_CLK_SBC1 41
/* 42 */
/* 43 */
#define TEGRA210_CLK_SBC2 44
/* 45 */
#define TEGRA210_CLK_SBC3 46
#define TEGRA210_CLK_I2C5 47
#define TEGRA210_CLK_DSIA 48
/* 49 */
/* 50 */
/* 51 */
#define TEGRA210_CLK_CSI 52
/* 53 */
#define TEGRA210_CLK_I2C2 54
#define TEGRA210_CLK_UARTC 55
#define TEGRA210_CLK_MIPI_CAL 56
#define TEGRA210_CLK_EMC 57
#define TEGRA210_CLK_USB2 58
/* 59 */
/* 60 */
/* 61 */
/* 62 */
#define TEGRA210_CLK_BSEV 63
/* 64 */
#define TEGRA210_CLK_UARTD 65
/* 66 */
#define TEGRA210_CLK_I2C3 67
#define TEGRA210_CLK_SBC4 68
#define TEGRA210_CLK_SDMMC3 69
#define TEGRA210_CLK_PCIE 70
#define TEGRA210_CLK_OWR 71
#define TEGRA210_CLK_AFI 72
#define TEGRA210_CLK_CSITE 73
/* 74 */
/* 75 */
/* 76 */
/* 77 */
#define TEGRA210_CLK_SOC_THERM 78
#define TEGRA210_CLK_DTV 79
/* 80 */
#define TEGRA210_CLK_I2CSLOW 81
#define TEGRA210_CLK_DSIB 82
#define TEGRA210_CLK_TSEC 83
/* 84 */
/* 85 */
/* 86 */
/* 87 */
/* 88 */
#define TEGRA210_CLK_XUSB_HOST 89
/* 90 */
/* 91 */
#define TEGRA210_CLK_CSUS 92
/* 93 */
/* 94 */
/* 95 (bit affects xusb_dev and xusb_dev_src) */
/* 96 */
/* 97 */
/* 98 */
#define TEGRA210_CLK_MSELECT 99
#define TEGRA210_CLK_TSENSOR 100
#define TEGRA210_CLK_I2S3 101
#define TEGRA210_CLK_I2S4 102
#define TEGRA210_CLK_I2C4 103
/* 104 */
/* 105 */
#define TEGRA210_CLK_D_AUDIO 106
/* 107 ( affects abp -> ape) */
/* 108 */
/* 109 */
/* 110 */
#define TEGRA210_CLK_HDA2CODEC_2X 111
/* 112 */
/* 113 */
/* 114 */
/* 115 */
/* 116 */
/* 117 */
#define TEGRA210_CLK_SPDIF_2X 118
#define TEGRA210_CLK_ACTMON 119
#define TEGRA210_CLK_EXTERN1 120
#define TEGRA210_CLK_EXTERN2 121
#define TEGRA210_CLK_EXTERN3 122
#define TEGRA210_CLK_SATA_OOB 123
#define TEGRA210_CLK_SATA 124
#define TEGRA210_CLK_HDA 125
/* 126 */
/* 127 */
#define TEGRA210_CLK_HDA2HDMI 128
/* 129 */
/* 130 */
/* 131 */
/* 132 */
/* 133 */
/* 134 */
/* 135 */
/* 136 */
/* 137 */
/* 138 */
/* 139 */
/* 140 */
/* 141 */
/* 142 */
/* (bit affects xusb_falcon_src, xusb_fs_src, xusb_host_src and xusb_ss_src) */
#define TEGRA210_CLK_XUSB_GATE 143
#define TEGRA210_CLK_CILAB 144
#define TEGRA210_CLK_CILCD 145
#define TEGRA210_CLK_CILE 146
#define TEGRA210_CLK_DSIALP 147
#define TEGRA210_CLK_DSIBLP 148
#define TEGRA210_CLK_ENTROPY 149
/* 150 */
/* 151 */
/* 152 */
/* 153 */
/* 154 */
/* 155 (bit affects dfll_ref and dfll_soc) */
#define TEGRA210_CLK_XUSB_SS 156
/* 157 */
/* 158 */
/* 159 */
/* 160 */
#define TEGRA210_CLK_DMIC1 161
#define TEGRA210_CLK_DMIC2 162
/* 163 */
/* 164 */
/* 165 */
#define TEGRA210_CLK_I2C6 166
/* 167 */
/* 168 */
/* 169 */
/* 170 */
#define TEGRA210_CLK_VIM2_CLK 171
/* 172 */
#define TEGRA210_CLK_MIPIBIF 173
/* 174 */
/* 175 */
/* 176 */
#define TEGRA210_CLK_CLK72MHZ 177
#define TEGRA210_CLK_VIC03 178
/* 179 */
/* 180 */
#define TEGRA210_CLK_DPAUX 181
#define TEGRA210_CLK_SOR0 182
#define TEGRA210_CLK_SOR1 183
#define TEGRA210_CLK_GPU 184
#define TEGRA210_CLK_DBGAPB 185
/* 186 */
#define TEGRA210_CLK_PLL_P_OUT_ADSP 187
/* 188 */
#define TEGRA210_CLK_PLL_G_REF 189
/* 190 */
/* 191 */
/* 192 */
#define TEGRA210_CLK_SDMMC_LEGACY 193
#define TEGRA210_CLK_NVDEC 194
#define TEGRA210_CLK_NVJPG 195
/* 196 */
#define TEGRA210_CLK_DMIC3 197
#define TEGRA210_CLK_APE 198
/* 199 */
/* 200 */
/* 201 */
#define TEGRA210_CLK_MAUD 202
/* 203 */
/* 204 */
/* 205 */
#define TEGRA210_CLK_TSECB 206
#define TEGRA210_CLK_DPAUX1 207
#define TEGRA210_CLK_VI_I2C 208
#define TEGRA210_CLK_HSIC_TRK 209
#define TEGRA210_CLK_USB2_TRK 210
#define TEGRA210_CLK_QSPI 211
#define TEGRA210_CLK_UARTAPE 212
/* 213 */
/* 214 */
/* 215 */
/* 216 */
/* 217 */
/* 218 */
#define TEGRA210_CLK_NVENC 219
/* 220 */
/* 221 */
#define TEGRA210_CLK_SOR_SAFE 222
#define TEGRA210_CLK_PLL_P_OUT_CPU 223
#define TEGRA210_CLK_UARTB 224
#define TEGRA210_CLK_VFIR 225
#define TEGRA210_CLK_SPDIF_IN 226
#define TEGRA210_CLK_SPDIF_OUT 227
#define TEGRA210_CLK_VI 228
#define TEGRA210_CLK_VI_SENSOR 229
#define TEGRA210_CLK_FUSE 230
#define TEGRA210_CLK_FUSE_BURN 231
#define TEGRA210_CLK_CLK_32K 232
#define TEGRA210_CLK_CLK_M 233
#define TEGRA210_CLK_CLK_M_DIV2 234
#define TEGRA210_CLK_CLK_M_DIV4 235
#define TEGRA210_CLK_PLL_REF 236
#define TEGRA210_CLK_PLL_C 237
#define TEGRA210_CLK_PLL_C_OUT1 238
#define TEGRA210_CLK_PLL_C2 239
#define TEGRA210_CLK_PLL_C3 240
#define TEGRA210_CLK_PLL_M 241
#define TEGRA210_CLK_PLL_M_OUT1 242
#define TEGRA210_CLK_PLL_P 243
#define TEGRA210_CLK_PLL_P_OUT1 244
#define TEGRA210_CLK_PLL_P_OUT2 245
#define TEGRA210_CLK_PLL_P_OUT3 246
#define TEGRA210_CLK_PLL_P_OUT4 247
#define TEGRA210_CLK_PLL_A 248
#define TEGRA210_CLK_PLL_A_OUT0 249
#define TEGRA210_CLK_PLL_D 250
#define TEGRA210_CLK_PLL_D_OUT0 251
#define TEGRA210_CLK_PLL_D2 252
#define TEGRA210_CLK_PLL_D2_OUT0 253
#define TEGRA210_CLK_PLL_U 254
#define TEGRA210_CLK_PLL_U_480M 255
#define TEGRA210_CLK_PLL_U_60M 256
#define TEGRA210_CLK_PLL_U_48M 257
/* 258 */
#define TEGRA210_CLK_PLL_X 259
#define TEGRA210_CLK_PLL_X_OUT0 260
#define TEGRA210_CLK_PLL_RE_VCO 261
#define TEGRA210_CLK_PLL_RE_OUT 262
#define TEGRA210_CLK_PLL_E 263
#define TEGRA210_CLK_SPDIF_IN_SYNC 264
#define TEGRA210_CLK_I2S0_SYNC 265
#define TEGRA210_CLK_I2S1_SYNC 266
#define TEGRA210_CLK_I2S2_SYNC 267
#define TEGRA210_CLK_I2S3_SYNC 268
#define TEGRA210_CLK_I2S4_SYNC 269
#define TEGRA210_CLK_VIMCLK_SYNC 270
#define TEGRA210_CLK_AUDIO0 271
#define TEGRA210_CLK_AUDIO1 272
#define TEGRA210_CLK_AUDIO2 273
#define TEGRA210_CLK_AUDIO3 274
#define TEGRA210_CLK_AUDIO4 275
#define TEGRA210_CLK_SPDIF 276
#define TEGRA210_CLK_CLK_OUT_1 277
#define TEGRA210_CLK_CLK_OUT_2 278
#define TEGRA210_CLK_CLK_OUT_3 279
#define TEGRA210_CLK_BLINK 280
/* 281 */
/* 282 */
/* 283 */
#define TEGRA210_CLK_XUSB_HOST_SRC 284
#define TEGRA210_CLK_XUSB_FALCON_SRC 285
#define TEGRA210_CLK_XUSB_FS_SRC 286
#define TEGRA210_CLK_XUSB_SS_SRC 287
#define TEGRA210_CLK_XUSB_DEV_SRC 288
#define TEGRA210_CLK_XUSB_DEV 289
#define TEGRA210_CLK_XUSB_HS_SRC 290
#define TEGRA210_CLK_SCLK 291
#define TEGRA210_CLK_HCLK 292
#define TEGRA210_CLK_PCLK 293
#define TEGRA210_CLK_CCLK_G 294
#define TEGRA210_CLK_CCLK_LP 295
#define TEGRA210_CLK_DFLL_REF 296
#define TEGRA210_CLK_DFLL_SOC 297
#define TEGRA210_CLK_VI_SENSOR2 298
#define TEGRA210_CLK_PLL_P_OUT5 299
#define TEGRA210_CLK_CML0 300
#define TEGRA210_CLK_CML1 301
#define TEGRA210_CLK_PLL_C4 302
#define TEGRA210_CLK_PLL_DP 303
#define TEGRA210_CLK_PLL_E_MUX 304
#define TEGRA210_CLK_PLL_MB 305
#define TEGRA210_CLK_PLL_A1 306
#define TEGRA210_CLK_PLL_D_DSI_OUT 307
#define TEGRA210_CLK_PLL_C4_OUT0 308
#define TEGRA210_CLK_PLL_C4_OUT1 309
#define TEGRA210_CLK_PLL_C4_OUT2 310
#define TEGRA210_CLK_PLL_C4_OUT3 311
#define TEGRA210_CLK_PLL_U_OUT 312
#define TEGRA210_CLK_PLL_U_OUT1 313
#define TEGRA210_CLK_PLL_U_OUT2 314
#define TEGRA210_CLK_USB2_HSIC_TRK 315
#define TEGRA210_CLK_PLL_P_OUT_HSIO 316
#define TEGRA210_CLK_PLL_P_OUT_XUSB 317
#define TEGRA210_CLK_XUSB_SSP_SRC 318
/* 319 */
/* 320 */
/* 321 */
/* 322 */
/* 323 */
/* 324 */
/* 325 */
/* 326 */
/* 327 */
/* 328 */
/* 329 */
/* 330 */
/* 331 */
/* 332 */
/* 333 */
/* 334 */
/* 335 */
/* 336 */
/* 337 */
/* 338 */
/* 339 */
/* 340 */
/* 341 */
/* 342 */
/* 343 */
/* 344 */
/* 345 */
/* 346 */
/* 347 */
/* 348 */
/* 349 */
#define TEGRA210_CLK_AUDIO0_MUX 350
#define TEGRA210_CLK_AUDIO1_MUX 351
#define TEGRA210_CLK_AUDIO2_MUX 352
#define TEGRA210_CLK_AUDIO3_MUX 353
#define TEGRA210_CLK_AUDIO4_MUX 354
#define TEGRA210_CLK_SPDIF_MUX 355
#define TEGRA210_CLK_CLK_OUT_1_MUX 356
#define TEGRA210_CLK_CLK_OUT_2_MUX 357
#define TEGRA210_CLK_CLK_OUT_3_MUX 358
#define TEGRA210_CLK_DSIA_MUX 359
#define TEGRA210_CLK_DSIB_MUX 360
#define TEGRA210_CLK_SOR0_LVDS 361
#define TEGRA210_CLK_XUSB_SS_DIV2 362
#define TEGRA210_CLK_PLL_M_UD 363
#define TEGRA210_CLK_PLL_C_UD 364
#define TEGRA210_CLK_SCLK_MUX 365
#define TEGRA210_CLK_CLK_MAX 366
#endif /* _DT_BINDINGS_CLOCK_TEGRA210_CAR_H */
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