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kernel_linux
提交 a69c7e01 编写于 作者: H Hawking Zhang 提交者： Alex Deucher
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drm/amdgpu: update pctl1 ram index/data for mmhub on raven 

Signed-off-by: NHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: NJunwei Zhang <Jerry.Zhang@amd.com>
上级 7504938f
隐藏空白更改
内联 并排
Showing with 48 addition and 41 deletion
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
浏览文件 @ a69c7e01
...@@ -245,28 +245,28 @@ static void mmhub_v1_0_program_invalidation(struct amdgpu_device *adev) ...@@ -245,28 +245,28 @@ static void mmhub_v1_0_program_invalidation(struct amdgpu_device *adev)
} }
struct pctl_data { struct pctl_data {
uint32_t index; uint32_t index;
uint32_t data; uint32_t data;
}; };
const struct pctl_data pctl0_data[] = { const struct pctl_data pctl0_data[] = {
{0x0, 0x7a640}, {0x0, 0x7a640},
{0x9, 0x2a64a}, {0x9, 0x2a64a},
{0xd, 0x2a680}, {0xd, 0x2a680},
{0x11, 0x6a684}, {0x11, 0x6a684},
{0x19, 0xea68e}, {0x19, 0xea68e},
{0x29, 0xa69e}, {0x29, 0xa69e},
{0x2b, 0x34a6c0}, {0x2b, 0x34a6c0},
{0x61, 0x83a707}, {0x61, 0x83a707},
{0xe6, 0x8a7a4}, {0xe6, 0x8a7a4},
{0xf0, 0x1a7b8}, {0xf0, 0x1a7b8},
{0xf3, 0xfa7cc}, {0xf3, 0xfa7cc},
{0x104, 0x17a7dd}, {0x104, 0x17a7dd},
{0x11d, 0xa7dc}, {0x11d, 0xa7dc},
{0x11f, 0x12a7f5}, {0x11f, 0x12a7f5},
{0x133, 0xa808}, {0x133, 0xa808},
{0x135, 0x12a810}, {0x135, 0x12a810},
{0x149, 0x7a82c} {0x149, 0x7a82c}
}; };
#define PCTL0_DATA_LEN (sizeof(pctl0_data)/sizeof(pctl0_data[0])) #define PCTL0_DATA_LEN (sizeof(pctl0_data)/sizeof(pctl0_data[0]))
...@@ -275,31 +275,38 @@ const struct pctl_data pctl0_data[] = { ...@@ -275,31 +275,38 @@ const struct pctl_data pctl0_data[] = {
#define PCTL0_STCTRL_REG_SAVE_RANGE0_LIMIT 0xa833 #define PCTL0_STCTRL_REG_SAVE_RANGE0_LIMIT 0xa833
const struct pctl_data pctl1_data[] = { const struct pctl_data pctl1_data[] = {
{0x0, 0x39a000}, {0x0, 0x39a000},
{0x3b, 0x44a040}, {0x3b, 0x44a040},
{0x81, 0x2a08d}, {0x81, 0x2a08d},
{0x85, 0x6ba094}, {0x85, 0x6ba094},
{0xf2, 0x18a100}, {0xf2, 0x18a100},
{0x10c, 0x4a132}, {0x10c, 0x4a132},
{0x112, 0xca141}, {0x112, 0xca141},
{0x120, 0x2fa158}, {0x120, 0x2fa158},
{0x151, 0x17a1d0}, {0x151, 0x17a1d0},
{0x16a, 0x1a1e9}, {0x16a, 0x1a1e9},
{0x16d, 0x13a1ec}, {0x16d, 0x13a1ec},
{0x182, 0x7a201}, {0x182, 0x7a201},
{0x18b, 0x3a20a}, {0x18b, 0x3a20a},
{0x190, 0x7a580}, {0x190, 0x7a580},
{0x199, 0xa590}, {0x199, 0xa590},
{0x19b, 0x4a594}, {0x19b, 0x4a594},
{0x1a1, 0x1a59c}, {0x1a1, 0x1a59c},
{0x1a4, 0x7a82c}, {0x1a4, 0x7a82c},
{0x1ad, 0xfa7cc}, {0x1ad, 0xfa7cc},
{0x1be, 0x17a7dd}, {0x1be, 0x17a7dd},
{0x1d7, 0x12a810} {0x1d7, 0x12a810},
{0x1eb, 0x4000a7e1},
{0x1ec, 0x5000a7f5},
{0x1ed, 0x4000a7e2},
{0x1ee, 0x5000a7dc},
{0x1ef, 0x4000a7e3},
{0x1f0, 0x5000a7f6},
{0x1f1, 0x5000a7e4}
}; };
#define PCTL1_DATA_LEN (sizeof(pctl1_data)/sizeof(pctl1_data[0])) #define PCTL1_DATA_LEN (sizeof(pctl1_data)/sizeof(pctl1_data[0]))
#define PCTL1_RENG_EXEC_END_PTR 0x1ea #define PCTL1_RENG_EXEC_END_PTR 0x1f1
#define PCTL1_STCTRL_REG_SAVE_RANGE0_BASE 0xa000 #define PCTL1_STCTRL_REG_SAVE_RANGE0_BASE 0xa000
#define PCTL1_STCTRL_REG_SAVE_RANGE0_LIMIT 0xa20d #define PCTL1_STCTRL_REG_SAVE_RANGE0_LIMIT 0xa20d
#define PCTL1_STCTRL_REG_SAVE_RANGE1_BASE 0xa580 #define PCTL1_STCTRL_REG_SAVE_RANGE1_BASE 0xa580
......
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