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kernel_linux
提交 a1b53446 编写于 作者: M Michael Ellerman
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Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/scottwood/linux into next 

Freescale updates from Scott:

"Highlights include 8xx optimizations, 32-bit checksum optimizations,
86xx consolidation, e5500/e6500 cpu hotplug, more fman and other dt
bits, and minor fixes/cleanup."
上级 d8c0282f fba4e9f9
隐藏空白更改
内联 并排
Showing with 5691 addition and 2826 deletion
Documentation/devicetree/bindings/powerpc/fsl/fman.txt
浏览文件 @ a1b53446
...@@ -315,6 +315,16 @@ PROPERTIES ...@@ -315,6 +315,16 @@ PROPERTIES
Value type: <phandle> Value type: <phandle>
Definition: A phandle for 1EEE1588 timer. Definition: A phandle for 1EEE1588 timer.
- pcsphy-handle
Usage required for "fsl,fman-memac" MACs
Value type: <phandle>
Definition: A phandle for pcsphy.
- tbi-handle
Usage required for "fsl,fman-dtsec" MACs
Value type: <phandle>
Definition: A phandle for tbiphy.
EXAMPLE EXAMPLE
fman1_tx28: port@a8000 { fman1_tx28: port@a8000 {
...@@ -340,6 +350,7 @@ ethernet@e0000 { ...@@ -340,6 +350,7 @@ ethernet@e0000 {
reg = <0xe0000 0x1000>; reg = <0xe0000 0x1000>;
fsl,fman-ports = <&fman1_rx8 &fman1_tx28>; fsl,fman-ports = <&fman1_rx8 &fman1_tx28>;
ptp-timer = <&ptp-timer>; ptp-timer = <&ptp-timer>;
tbi-handle = <&tbi0>;
}; };
============================================================================ ============================================================================
...@@ -415,6 +426,13 @@ PROPERTIES ...@@ -415,6 +426,13 @@ PROPERTIES
The settings and programming routines for internal/external The settings and programming routines for internal/external
MDIO are different. Must be included for internal MDIO. MDIO are different. Must be included for internal MDIO.
For internal PHY device on internal mdio bus, a PHY node should be created.
See the definition of the PHY node in booting-without-of.txt for an
example of how to define a PHY (Internal PHY has no interrupt line).
- For "fsl,fman-mdio" compatible internal mdio bus, the PHY is TBI PHY.
- For "fsl,fman-memac-mdio" compatible internal mdio bus, the PHY is PCS PHY,
PCS PHY addr must be '0'.
EXAMPLE EXAMPLE
Example for FMan v2 external MDIO: Example for FMan v2 external MDIO:
...@@ -425,12 +443,29 @@ mdio@f1000 { ...@@ -425,12 +443,29 @@ mdio@f1000 {
interrupts = <101 2 0 0>; interrupts = <101 2 0 0>;
}; };
Example for FMan v2 internal MDIO:
mdio@e3120 {
compatible = "fsl,fman-mdio";
reg = <0xe3120 0xee0>;
fsl,fman-internal-mdio;
tbi1: tbi-phy@8 {
reg = <0x8>;
device_type = "tbi-phy";
};
};
Example for FMan v3 internal MDIO: Example for FMan v3 internal MDIO:
mdio@f1000 { mdio@f1000 {
compatible = "fsl,fman-memac-mdio"; compatible = "fsl,fman-memac-mdio";
reg = <0xf1000 0x1000>; reg = <0xf1000 0x1000>;
fsl,fman-internal-mdio; fsl,fman-internal-mdio;
pcsphy6: ethernet-phy@0 {
reg = <0x0>;
};
}; };
============================================================================= =============================================================================
...@@ -568,6 +603,7 @@ fman@400000 { ...@@ -568,6 +603,7 @@ fman@400000 {
cell-index = <0>; cell-index = <0>;
reg = <0xe0000 0x1000>; reg = <0xe0000 0x1000>;
fsl,fman-ports = <&fman1_rx_0x8 &fman1_tx_0x28>; fsl,fman-ports = <&fman1_rx_0x8 &fman1_tx_0x28>;
tbi-handle = <&tbi5>;
}; };
ethernet@e2000 { ethernet@e2000 {
...@@ -575,6 +611,7 @@ fman@400000 { ...@@ -575,6 +611,7 @@ fman@400000 {
cell-index = <1>; cell-index = <1>;
reg = <0xe2000 0x1000>; reg = <0xe2000 0x1000>;
fsl,fman-ports = <&fman1_rx_0x9 &fman1_tx_0x29>; fsl,fman-ports = <&fman1_rx_0x9 &fman1_tx_0x29>;
tbi-handle = <&tbi6>;
}; };
ethernet@e4000 { ethernet@e4000 {
...@@ -582,6 +619,7 @@ fman@400000 { ...@@ -582,6 +619,7 @@ fman@400000 {
cell-index = <2>; cell-index = <2>;
reg = <0xe4000 0x1000>; reg = <0xe4000 0x1000>;
fsl,fman-ports = <&fman1_rx_0xa &fman1_tx_0x2a>; fsl,fman-ports = <&fman1_rx_0xa &fman1_tx_0x2a>;
tbi-handle = <&tbi7>;
}; };
ethernet@e6000 { ethernet@e6000 {
...@@ -589,6 +627,7 @@ fman@400000 { ...@@ -589,6 +627,7 @@ fman@400000 {
cell-index = <3>; cell-index = <3>;
reg = <0xe6000 0x1000>; reg = <0xe6000 0x1000>;
fsl,fman-ports = <&fman1_rx_0xb &fman1_tx_0x2b>; fsl,fman-ports = <&fman1_rx_0xb &fman1_tx_0x2b>;
tbi-handle = <&tbi8>;
}; };
ethernet@e8000 { ethernet@e8000 {
...@@ -596,6 +635,7 @@ fman@400000 { ...@@ -596,6 +635,7 @@ fman@400000 {
cell-index = <4>; cell-index = <4>;
reg = <0xf0000 0x1000>; reg = <0xf0000 0x1000>;
fsl,fman-ports = <&fman1_rx_0xc &fman1_tx_0x2c>; fsl,fman-ports = <&fman1_rx_0xc &fman1_tx_0x2c>;
tbi-handle = <&tbi9>;
ethernet@f0000 { ethernet@f0000 {
cell-index = <8>; cell-index = <8>;
......
Documentation/devicetree/bindings/soc/fsl/rcpm.txt 0 → 100644
浏览文件 @ a1b53446
* Run Control and Power Management
-------------------------------------------
The RCPM performs all device-level tasks associated with device run control
and power management.
Required properites:
- reg : Offset and length of the register set of the RCPM block.
- fsl,#rcpm-wakeup-cells : The number of IPPDEXPCR register cells in the
fsl,rcpm-wakeup property.
- compatible : Must contain a chip-specific RCPM block compatible string
and (if applicable) may contain a chassis-version RCPM compatible
string. Chip-specific strings are of the form "fsl,<chip>-rcpm",
such as:
* "fsl,p2041-rcpm"
* "fsl,p5020-rcpm"
* "fsl,t4240-rcpm"
Chassis-version strings are of the form "fsl,qoriq-rcpm-<version>",
such as:
* "fsl,qoriq-rcpm-1.0": for chassis 1.0 rcpm
* "fsl,qoriq-rcpm-2.0": for chassis 2.0 rcpm
* "fsl,qoriq-rcpm-2.1": for chassis 2.1 rcpm
All references to "1.0" and "2.0" refer to the QorIQ chassis version to
which the chip complies.
Chassis Version Example Chips
--------------- -------------------------------
1.0 p4080, p5020, p5040, p2041, p3041
2.0 t4240, b4860, b4420
2.1 t1040, ls1021
Example:
The RCPM node for T4240:
rcpm: global-utilities@e2000 {
compatible = "fsl,t4240-rcpm", "fsl,qoriq-rcpm-2.0";
reg = <0xe2000 0x1000>;
fsl,#rcpm-wakeup-cells = <2>;
};
* Freescale RCPM Wakeup Source Device Tree Bindings
-------------------------------------------
Required fsl,rcpm-wakeup property should be added to a device node if the device
can be used as a wakeup source.
- fsl,rcpm-wakeup: Consists of a phandle to the rcpm node and the IPPDEXPCR
register cells. The number of IPPDEXPCR register cells is defined in
"fsl,#rcpm-wakeup-cells" in the rcpm node. The first register cell is
the bit mask that should be set in IPPDEXPCR0, and the second register
cell is for IPPDEXPCR1, and so on.
Note: IPPDEXPCR(IP Powerdown Exception Control Register) provides a
mechanism for keeping certain blocks awake during STANDBY and MEM, in
order to use them as wake-up sources.
Example:
lpuart0: serial@2950000 {
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x2950000 0x0 0x1000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sysclk>;
clock-names = "ipg";
fsl,rcpm-wakeup = <&rcpm 0x0 0x40000000>;
};
Documentation/kernel-parameters.txt
浏览文件 @ a1b53446
...@@ -2582,7 +2582,7 @@ bytes respectively. Such letter suffixes can also be entirely omitted. ...@@ -2582,7 +2582,7 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
nolapic_timer [X86-32,APIC] Do not use the local APIC timer. nolapic_timer [X86-32,APIC] Do not use the local APIC timer.
noltlbs [PPC] Do not use large page/tlb entries for kernel noltlbs [PPC] Do not use large page/tlb entries for kernel
lowmem mapping on PPC40x. lowmem mapping on PPC40x and PPC8xx
nomca [IA-64] Disable machine check abort handling nomca [IA-64] Disable machine check abort handling
......
arch/powerpc/Kconfig
浏览文件 @ a1b53446
...@@ -408,7 +408,7 @@ config SWIOTLB ...@@ -408,7 +408,7 @@ config SWIOTLB
config HOTPLUG_CPU config HOTPLUG_CPU
bool "Support for enabling/disabling CPUs" bool "Support for enabling/disabling CPUs"
depends on SMP && (PPC_PSERIES || \ depends on SMP && (PPC_PSERIES || \
PPC_PMAC || PPC_POWERNV || (PPC_85xx && !PPC_E500MC)) PPC_PMAC || PPC_POWERNV || FSL_SOC_BOOKE)
---help--- ---help---
Say Y here to be able to disable and re-enable individual Say Y here to be able to disable and re-enable individual
CPUs at runtime on SMP machines. CPUs at runtime on SMP machines.
......
arch/powerpc/Makefile
浏览文件 @ a1b53446
...@@ -325,6 +325,16 @@ corenet64_smp_defconfig: ...@@ -325,6 +325,16 @@ corenet64_smp_defconfig:
$(call merge_into_defconfig,corenet_basic_defconfig,\ $(call merge_into_defconfig,corenet_basic_defconfig,\
85xx-64bit 85xx-smp altivec 85xx-hw fsl-emb-nonhw) 85xx-64bit 85xx-smp altivec 85xx-hw fsl-emb-nonhw)
PHONY += mpc86xx_defconfig
mpc86xx_defconfig:
$(call merge_into_defconfig,mpc86xx_basic_defconfig,\
86xx-hw fsl-emb-nonhw)
PHONY += mpc86xx_smp_defconfig
mpc86xx_smp_defconfig:
$(call merge_into_defconfig,mpc86xx_basic_defconfig,\
86xx-smp 86xx-hw fsl-emb-nonhw)
define archhelp define archhelp
@echo '* zImage - Build default images selected by kernel config' @echo '* zImage - Build default images selected by kernel config'
@echo ' zImage.* - Compressed kernel image (arch/$(ARCH)/boot/zImage.*)' @echo ' zImage.* - Compressed kernel image (arch/$(ARCH)/boot/zImage.*)'
......
arch/powerpc/boot/dts/fsl/b4860qds.dts
浏览文件 @ a1b53446
/* /*
* B4860DS Device Tree Source * B4860DS Device Tree Source
* *
* Copyright 2012 Freescale Semiconductor Inc. * Copyright 2012 - 2015 Freescale Semiconductor Inc.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -39,12 +39,69 @@ ...@@ -39,12 +39,69 @@
model = "fsl,B4860QDS"; model = "fsl,B4860QDS";
compatible = "fsl,B4860QDS"; compatible = "fsl,B4860QDS";
aliases {
phy_sgmii_1e = &phy_sgmii_1e;
phy_sgmii_1f = &phy_sgmii_1f;
phy_xaui_slot1 = &phy_xaui_slot1;
phy_xaui_slot2 = &phy_xaui_slot2;
};
ifc: localbus@ffe124000 { ifc: localbus@ffe124000 {
board-control@3,0 { board-control@3,0 {
compatible = "fsl,b4860qds-fpga", "fsl,fpga-qixis"; compatible = "fsl,b4860qds-fpga", "fsl,fpga-qixis";
}; };
}; };
soc@ffe000000 {
fman@400000 {
ethernet@e8000 {
phy-handle = <&phy_sgmii_1e>;
phy-connection-type = "sgmii";
};
ethernet@ea000 {
phy-handle = <&phy_sgmii_1f>;
phy-connection-type = "sgmii";
};
ethernet@f0000 {
phy-handle = <&phy_xaui_slot1>;
phy-connection-type = "xgmii";
};
ethernet@f2000 {
phy-handle = <&phy_xaui_slot2>;
phy-connection-type = "xgmii";
};
mdio@fc000 {
phy_sgmii_1e: ethernet-phy@1e {
reg = <0x1e>;
status = "disabled";
};
phy_sgmii_1f: ethernet-phy@1f {
reg = <0x1f>;
status = "disabled";
};
};
mdio@fd000 {
phy_xaui_slot1: xaui-phy@slot1 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x7>;
status = "disabled";
};
phy_xaui_slot2: xaui-phy@slot2 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x6>;
status = "disabled";
};
};
};
};
rio: rapidio@ffe0c0000 { rio: rapidio@ffe0c0000 {
reg = <0xf 0xfe0c0000 0 0x11000>; reg = <0xf 0xfe0c0000 0 0x11000>;
...@@ -55,7 +112,6 @@ ...@@ -55,7 +112,6 @@
ranges = <0 0 0xc 0x30000000 0 0x10000000>; ranges = <0 0 0xc 0x30000000 0 0x10000000>;
}; };
}; };
}; };
/include/ "b4860si-post.dtsi" /include/ "b4860si-post.dtsi"
arch/powerpc/boot/dts/fsl/b4qds.dtsi
浏览文件 @ a1b53446
/* /*
* B4420DS Device Tree Source * B4420DS Device Tree Source
* *
* Copyright 2012 - 2014 Freescale Semiconductor, Inc. * Copyright 2012 - 2015 Freescale Semiconductor, Inc.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -39,6 +39,13 @@ ...@@ -39,6 +39,13 @@
#size-cells = <2>; #size-cells = <2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
aliases {
phy_sgmii_10 = &phy_sgmii_10;
phy_sgmii_11 = &phy_sgmii_11;
phy_sgmii_1c = &phy_sgmii_1c;
phy_sgmii_1d = &phy_sgmii_1d;
};
ifc: localbus@ffe124000 { ifc: localbus@ffe124000 {
reg = <0xf 0xfe124000 0 0x2000>; reg = <0xf 0xfe124000 0 0x2000>;
ranges = <0 0 0xf 0xe8000000 0x08000000 ranges = <0 0 0xf 0xe8000000 0x08000000
...@@ -135,7 +142,7 @@ ...@@ -135,7 +142,7 @@
flash@0 { flash@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "sst,sst25wf040"; compatible = "sst,sst25wf040", "jedec,spi-nor";
reg = <0>; reg = <0>;
spi-max-frequency = <40000000>; /* input clock */ spi-max-frequency = <40000000>; /* input clock */
}; };
...@@ -210,6 +217,47 @@ ...@@ -210,6 +217,47 @@
phy_type = "ulpi"; phy_type = "ulpi";
}; };
fman@400000 {
ethernet@e0000 {
phy-handle = <&phy_sgmii_10>;
phy-connection-type = "sgmii";
};
ethernet@e2000 {
phy-handle = <&phy_sgmii_11>;
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-handle = <&phy_sgmii_1c>;
phy-connection-type = "sgmii";
};
ethernet@e6000 {
phy-handle = <&phy_sgmii_1d>;
phy-connection-type = "sgmii";
};
mdio@fc000 {
phy_sgmii_10: ethernet-phy@10 {
reg = <0x10>;
};
phy_sgmii_11: ethernet-phy@11 {
reg = <0x11>;
};
phy_sgmii_1c: ethernet-phy@1c {
reg = <0x1c>;
status = "disabled";
};
phy_sgmii_1d: ethernet-phy@1d {
reg = <0x1d>;
status = "disabled";
};
};
};
}; };
pci0: pcie@ffe200000 { pci0: pcie@ffe200000 {
...@@ -226,7 +274,6 @@ ...@@ -226,7 +274,6 @@
0 0x00010000>; 0 0x00010000>;
}; };
}; };
}; };
/include/ "b4si-post.dtsi" /include/ "b4si-post.dtsi"
arch/powerpc/boot/dts/fsl/bsc9131rdb.dtsi
浏览文件 @ a1b53446
...@@ -53,7 +53,7 @@ ...@@ -53,7 +53,7 @@
flash@0 { flash@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "spansion,s25sl12801"; compatible = "spansion,s25sl12801", "jedec,spi-nor";
reg = <0>; reg = <0>;
spi-max-frequency = <50000000>; spi-max-frequency = <50000000>;
......
arch/powerpc/boot/dts/fsl/bsc9132qds.dtsi
浏览文件 @ a1b53446
...@@ -55,7 +55,7 @@ ...@@ -55,7 +55,7 @@
flash@0 { flash@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "spansion,s25sl12801"; compatible = "spansion,s25sl12801", "jedec,spi-nor";
reg = <0>; reg = <0>;
spi-max-frequency = <30000000>; spi-max-frequency = <30000000>;
}; };
......
arch/powerpc/boot/dts/fsl/c293pcie.dts
浏览文件 @ a1b53446
...@@ -167,7 +167,7 @@ ...@@ -167,7 +167,7 @@
flash@0 { flash@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "spansion,s25sl12801"; compatible = "spansion,s25sl12801", "jedec,spi-nor";
reg = <0>; reg = <0>;
spi-max-frequency = <50000000>; spi-max-frequency = <50000000>;
......
arch/powerpc/boot/dts/gef_ppc9a.dts → arch/powerpc/boot/dts/fsl/gef_ppc9a.dts
浏览文件 @ a1b53446
...@@ -18,62 +18,19 @@ ...@@ -18,62 +18,19 @@
* Compiled with dtc -I dts -O dtb -o gef_ppc9a.dtb gef_ppc9a.dts * Compiled with dtc -I dts -O dtb -o gef_ppc9a.dtb gef_ppc9a.dts
*/ */
/dts-v1/; /include/ "mpc8641si-pre.dtsi"
/ { / {
model = "GEF_PPC9A"; model = "GEF_PPC9A";
compatible = "gef,ppc9a"; compatible = "gef,ppc9a";
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &enet0;
ethernet1 = &enet1;
serial0 = &serial0;
serial1 = &serial1;
pci0 = &pci0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8641@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <32768>; // L1, 32K
i-cache-size = <32768>; // L1, 32K
timebase-frequency = <0>; // From uboot
bus-frequency = <0>; // From uboot
clock-frequency = <0>; // From uboot
};
PowerPC,8641@1 {
device_type = "cpu";
reg = <1>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <32768>; // L1, 32K
i-cache-size = <32768>; // L1, 32K
timebase-frequency = <0>; // From uboot
bus-frequency = <0>; // From uboot
clock-frequency = <0>; // From uboot
};
};
memory { memory {
device_type = "memory"; device_type = "memory";
reg = <0x0 0x40000000>; // set by uboot reg = <0x0 0x40000000>; // set by uboot
}; };
localbus@fef05000 { lbc: localbus@fef05000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,mpc8641-localbus", "simple-bus";
reg = <0xfef05000 0x1000>; reg = <0xfef05000 0x1000>;
interrupts = <19 2>;
interrupt-parent = <&mpic>;
ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
1 0 0xe8000000 0x08000000 // Paged Flash 0 1 0 0xe8000000 0x08000000 // Paged Flash 0
...@@ -150,9 +107,7 @@ ...@@ -150,9 +107,7 @@
interrupt-controller; interrupt-controller;
compatible = "gef,ppc9a-fpga-pic", "gef,fpga-pic-1.00"; compatible = "gef,ppc9a-fpga-pic", "gef,fpga-pic-1.00";
reg = <0x4 0x4000 0x20>; reg = <0x4 0x4000 0x20>;
interrupts = <0x8 interrupts = <0x8 0x9 0 0>;
0x9>;
interrupt-parent = <&mpic>;
}; };
gef_gpio: gpio@7,14000 { gef_gpio: gpio@7,14000 {
...@@ -163,37 +118,10 @@ ...@@ -163,37 +118,10 @@
}; };
}; };
soc@fef00000 { soc: soc@fef00000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
compatible = "fsl,mpc8641-soc", "simple-bus";
ranges = <0x0 0xfef00000 0x00100000>; ranges = <0x0 0xfef00000 0x00100000>;
bus-frequency = <33333333>;
mcm-law@0 {
compatible = "fsl,mcm-law";
reg = <0x0 0x1000>;
fsl,num-laws = <10>;
};
mcm@1000 {
compatible = "fsl,mpc8641-mcm", "fsl,mcm";
reg = <0x1000 0x1000>;
interrupts = <17 2>;
interrupt-parent = <&mpic>;
};
i2c1: i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <0x2b 0x2>;
interrupt-parent = <&mpic>;
dfsrr;
i2c@3000 {
hwmon@48 { hwmon@48 {
compatible = "national,lm92"; compatible = "national,lm92";
reg = <0x48>; reg = <0x48>;
...@@ -215,204 +143,65 @@ ...@@ -215,204 +143,65 @@
}; };
}; };
i2c2: i2c@3100 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl-i2c";
reg = <0x3100 0x100>;
interrupts = <0x2b 0x2>;
interrupt-parent = <&mpic>;
dfsrr;
};
dma@21300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
reg = <0x21300 0x4>;
ranges = <0x0 0x21100 0x200>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,mpc8641-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
interrupt-parent = <&mpic>;
interrupts = <20 2>;
};
dma-channel@80 {
compatible = "fsl,mpc8641-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&mpic>;
interrupts = <21 2>;
};
dma-channel@100 {
compatible = "fsl,mpc8641-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&mpic>;
interrupts = <22 2>;
};
dma-channel@180 {
compatible = "fsl,mpc8641-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
interrupt-parent = <&mpic>;
interrupts = <23 2>;
};
};
enet0: ethernet@24000 { enet0: ethernet@24000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <0>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <0x24000 0x1000>;
ranges = <0x0 0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi0>; tbi-handle = <&tbi0>;
phy-handle = <&phy0>; phy-handle = <&phy0>;
phy-connection-type = "gmii"; phy-connection-type = "gmii";
};
mdio@520 { mdio@24520 {
#address-cells = <1>; phy0: ethernet-phy@0 {
#size-cells = <0>; interrupt-parent = <&gef_pic>;
compatible = "fsl,gianfar-mdio"; interrupts = <0x9 0x4>;
reg = <0x520 0x20>; reg = <1>;
};
phy0: ethernet-phy@0 { phy2: ethernet-phy@2 {
interrupt-parent = <&gef_pic>; interrupt-parent = <&gef_pic>;
interrupts = <0x9 0x4>; interrupts = <0x8 0x4>;
reg = <1>; reg = <3>;
}; };
phy2: ethernet-phy@2 { tbi0: tbi-phy@11 {
interrupt-parent = <&gef_pic>; reg = <0x11>;
interrupts = <0x8 0x4>; device_type = "tbi-phy";
reg = <3>;
};
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
}; };
}; };
enet1: ethernet@26000 { enet1: ethernet@26000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <2>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <0x26000 0x1000>;
ranges = <0x0 0x26000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <31 2 32 2 33 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi2>; tbi-handle = <&tbi2>;
phy-handle = <&phy2>; phy-handle = <&phy2>;
phy-connection-type = "gmii"; phy-connection-type = "gmii";
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x520 0x20>;
tbi2: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
}; };
serial0: serial@4500 { mdio@26520 {
cell-index = <0>; tbi2: tbi-phy@11 {
device_type = "serial"; reg = <0x11>;
compatible = "fsl,ns16550", "ns16550"; device_type = "tbi-phy";
reg = <0x4500 0x100>; };
clock-frequency = <0>;
interrupts = <0x2a 0x2>;
interrupt-parent = <&mpic>;
}; };
serial1: serial@4600 { enet2: ethernet@25000 {
cell-index = <1>; status = "disabled";
device_type = "serial";
compatible = "fsl,ns16550", "ns16550";
reg = <0x4600 0x100>;
clock-frequency = <0>;
interrupts = <0x1c 0x2>;
interrupt-parent = <&mpic>;
}; };
mpic: pic@40000 { mdio@25520 {
clock-frequency = <0>; status = "disabled";
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
}; };
msi@41600 { enet3: ethernet@27000 {
compatible = "fsl,mpc8641-msi", "fsl,mpic-msi"; status = "disabled";
reg = <0x41600 0x80>;
msi-available-ranges = <0 0x100>;
interrupts = <
0xe0 0
0xe1 0
0xe2 0
0xe3 0
0xe4 0
0xe5 0
0xe6 0
0xe7 0>;
interrupt-parent = <&mpic>;
}; };
global-utilities@e0000 { mdio@27520 {
compatible = "fsl,mpc8641-guts"; status = "disabled";
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
}; };
}; };
pci0: pcie@fef08000 { pci0: pcie@fef08000 {
compatible = "fsl,mpc8641-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0xfef08000 0x1000>; reg = <0xfef08000 0x1000>;
bus-range = <0x0 0xff>;
ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>; 0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <0x18 0x2>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
0x0000 0x0 0x0 0x1 &mpic 0x0 0x1
0x0000 0x0 0x0 0x2 &mpic 0x1 0x1
0x0000 0x0 0x0 0x3 &mpic 0x2 0x1
0x0000 0x0 0x0 0x4 &mpic 0x3 0x1
>;
pcie@0 { pcie@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <0x02000000 0x0 0x80000000 ranges = <0x02000000 0x0 0x80000000
0x02000000 0x0 0x80000000 0x02000000 0x0 0x80000000
0x0 0x40000000 0x0 0x40000000
...@@ -423,3 +212,5 @@ ...@@ -423,3 +212,5 @@
}; };
}; };
}; };
/include/ "mpc8641si-post.dtsi"
arch/powerpc/boot/dts/gef_sbc310.dts → arch/powerpc/boot/dts/fsl/gef_sbc310.dts
浏览文件 @ a1b53446
...@@ -18,63 +18,23 @@ ...@@ -18,63 +18,23 @@
* Compiled with dtc -I dts -O dtb -o gef_sbc310.dtb gef_sbc310.dts * Compiled with dtc -I dts -O dtb -o gef_sbc310.dtb gef_sbc310.dts
*/ */
/dts-v1/; /include/ "mpc8641si-pre.dtsi"
/ { / {
model = "GEF_SBC310"; model = "GEF_SBC310";
compatible = "gef,sbc310"; compatible = "gef,sbc310";
#address-cells = <1>;
#size-cells = <1>;
aliases { aliases {
ethernet0 = &enet0;
ethernet1 = &enet1;
serial0 = &serial0;
serial1 = &serial1;
pci0 = &pci0;
pci1 = &pci1; pci1 = &pci1;
}; };
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8641@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <32768>; // L1, 32K
i-cache-size = <32768>; // L1, 32K
timebase-frequency = <0>; // From uboot
bus-frequency = <0>; // From uboot
clock-frequency = <0>; // From uboot
};
PowerPC,8641@1 {
device_type = "cpu";
reg = <1>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <32768>; // L1, 32K
i-cache-size = <32768>; // L1, 32K
timebase-frequency = <0>; // From uboot
bus-frequency = <0>; // From uboot
clock-frequency = <0>; // From uboot
};
};
memory { memory {
device_type = "memory"; device_type = "memory";
reg = <0x0 0x40000000>; // set by uboot reg = <0x0 0x40000000>; // set by uboot
}; };
localbus@fef05000 { lbc: localbus@fef05000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,mpc8641-localbus", "simple-bus";
reg = <0xfef05000 0x1000>; reg = <0xfef05000 0x1000>;
interrupts = <19 2>;
interrupt-parent = <&mpic>;
ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
1 0 0xe0000000 0x08000000 // Paged Flash 0 1 0 0xe0000000 0x08000000 // Paged Flash 0
...@@ -148,9 +108,7 @@ ...@@ -148,9 +108,7 @@
interrupt-controller; interrupt-controller;
compatible = "gef,sbc310-fpga-pic", "gef,fpga-pic"; compatible = "gef,sbc310-fpga-pic", "gef,fpga-pic";
reg = <0x4 0x4000 0x20>; reg = <0x4 0x4000 0x20>;
interrupts = <0x8 interrupts = <0x8 0x9 0 0>;
0x9>;
interrupt-parent = <&mpic>;
}; };
gef_gpio: gpio@4,8000 { gef_gpio: gpio@4,8000 {
...@@ -161,52 +119,17 @@ ...@@ -161,52 +119,17 @@
}; };
}; };
soc@fef00000 { soc: soc@fef00000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
compatible = "fsl,mpc8641-soc", "simple-bus";
ranges = <0x0 0xfef00000 0x00100000>; ranges = <0x0 0xfef00000 0x00100000>;
bus-frequency = <33333333>;
mcm-law@0 {
compatible = "fsl,mcm-law";
reg = <0x0 0x1000>;
fsl,num-laws = <10>;
};
mcm@1000 {
compatible = "fsl,mpc8641-mcm", "fsl,mcm";
reg = <0x1000 0x1000>;
interrupts = <17 2>;
interrupt-parent = <&mpic>;
};
i2c1: i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <0x2b 0x2>;
interrupt-parent = <&mpic>;
dfsrr;
i2c@3000 {
rtc@51 { rtc@51 {
compatible = "epson,rx8581"; compatible = "epson,rx8581";
reg = <0x00000051>; reg = <0x00000051>;
}; };
}; };
i2c2: i2c@3100 { i2c@3100 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl-i2c";
reg = <0x3100 0x100>;
interrupts = <0x2b 0x2>;
interrupt-parent = <&mpic>;
dfsrr;
hwmon@48 { hwmon@48 {
compatible = "national,lm92"; compatible = "national,lm92";
reg = <0x48>; reg = <0x48>;
...@@ -223,181 +146,63 @@ ...@@ -223,181 +146,63 @@
}; };
}; };
dma@21300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
reg = <0x21300 0x4>;
ranges = <0x0 0x21100 0x200>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,mpc8641-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
interrupt-parent = <&mpic>;
interrupts = <20 2>;
};
dma-channel@80 {
compatible = "fsl,mpc8641-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&mpic>;
interrupts = <21 2>;
};
dma-channel@100 {
compatible = "fsl,mpc8641-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&mpic>;
interrupts = <22 2>;
};
dma-channel@180 {
compatible = "fsl,mpc8641-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
interrupt-parent = <&mpic>;
interrupts = <23 2>;
};
};
enet0: ethernet@24000 { enet0: ethernet@24000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <0>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <0x24000 0x1000>;
ranges = <0x0 0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi0>; tbi-handle = <&tbi0>;
phy-handle = <&phy0>; phy-handle = <&phy0>;
phy-connection-type = "gmii"; phy-connection-type = "gmii";
};
mdio@520 { mdio@24520 {
#address-cells = <1>; phy0: ethernet-phy@0 {
#size-cells = <0>; interrupt-parent = <&gef_pic>;
compatible = "fsl,gianfar-mdio"; interrupts = <0x9 0x4>;
reg = <0x520 0x20>; reg = <1>;
};
phy0: ethernet-phy@0 { phy2: ethernet-phy@2 {
interrupt-parent = <&gef_pic>; interrupt-parent = <&gef_pic>;
interrupts = <0x9 0x4>; interrupts = <0x8 0x4>;
reg = <1>; reg = <3>;
}; };
phy2: ethernet-phy@2 { tbi0: tbi-phy@11 {
interrupt-parent = <&gef_pic>; reg = <0x11>;
interrupts = <0x8 0x4>; device_type = "tbi-phy";
reg = <3>;
};
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
}; };
}; };
enet1: ethernet@26000 { enet1: ethernet@26000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <2>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <0x26000 0x1000>;
ranges = <0x0 0x26000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <31 2 32 2 33 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi2>; tbi-handle = <&tbi2>;
phy-handle = <&phy2>; phy-handle = <&phy2>;
phy-connection-type = "gmii"; phy-connection-type = "gmii";
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x520 0x20>;
tbi2: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
}; };
serial0: serial@4500 { mdio@26520 {
cell-index = <0>; tbi2: tbi-phy@11 {
device_type = "serial"; reg = <0x11>;
compatible = "fsl,ns16550", "ns16550"; device_type = "tbi-phy";
reg = <0x4500 0x100>; };
clock-frequency = <0>;
interrupts = <0x2a 0x2>;
interrupt-parent = <&mpic>;
}; };
serial1: serial@4600 { enet2: ethernet@25000 {
cell-index = <1>; status = "disabled";
device_type = "serial";
compatible = "fsl,ns16550", "ns16550";
reg = <0x4600 0x100>;
clock-frequency = <0>;
interrupts = <0x1c 0x2>;
interrupt-parent = <&mpic>;
}; };
mpic: pic@40000 { mdio@25520 {
clock-frequency = <0>; status = "disabled";
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
}; };
msi@41600 { enet3: ethernet@27000 {
compatible = "fsl,mpc8641-msi", "fsl,mpic-msi"; status = "disabled";
reg = <0x41600 0x80>;
msi-available-ranges = <0 0x100>;
interrupts = <
0xe0 0
0xe1 0
0xe2 0
0xe3 0
0xe4 0
0xe5 0
0xe6 0
0xe7 0>;
interrupt-parent = <&mpic>;
}; };
global-utilities@e0000 { mdio@27520 {
compatible = "fsl,mpc8641-guts"; status = "disabled";
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
}; };
}; };
pci0: pcie@fef08000 { pci0: pcie@fef08000 {
compatible = "fsl,mpc8641-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0xfef08000 0x1000>; reg = <0xfef08000 0x1000>;
bus-range = <0x0 0xff>;
ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>; 0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <0x18 0x2>;
interrupt-map-mask = <0xff00 0x0 0x0 0x7>; interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
interrupt-map = < interrupt-map = <
0x0000 0x0 0x0 0x1 &mpic 0x0 0x2 0x0000 0x0 0x0 0x1 &mpic 0x0 0x2
...@@ -407,10 +212,6 @@ ...@@ -407,10 +212,6 @@
>; >;
pcie@0 { pcie@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <0x02000000 0x0 0x80000000 ranges = <0x02000000 0x0 0x80000000
0x02000000 0x0 0x80000000 0x02000000 0x0 0x80000000
0x0 0x40000000 0x0 0x40000000
...@@ -424,16 +225,14 @@ ...@@ -424,16 +225,14 @@
pci1: pcie@fef09000 { pci1: pcie@fef09000 {
compatible = "fsl,mpc8641-pcie"; compatible = "fsl,mpc8641-pcie";
device_type = "pci"; device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
reg = <0xfef09000 0x1000>; reg = <0xfef09000 0x1000>;
bus-range = <0x0 0xff>; bus-range = <0x0 0xff>;
ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000 ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
0x01000000 0x0 0x00000000 0xfe400000 0x0 0x00400000>; 0x01000000 0x0 0x00000000 0xfe400000 0x0 0x00400000>;
clock-frequency = <33333333>; clock-frequency = <100000000>;
interrupt-parent = <&mpic>; interrupts = <0x19 0x2 0 0>;
interrupts = <0x19 0x2>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = < interrupt-map = <
0x0000 0x0 0x0 0x1 &mpic 0x4 0x2 0x0000 0x0 0x0 0x1 &mpic 0x4 0x2
...@@ -457,3 +256,5 @@ ...@@ -457,3 +256,5 @@
}; };
}; };
}; };
/include/ "mpc8641si-post.dtsi"
arch/powerpc/boot/dts/gef_sbc610.dts → arch/powerpc/boot/dts/fsl/gef_sbc610.dts
浏览文件 @ a1b53446
...@@ -18,62 +18,19 @@ ...@@ -18,62 +18,19 @@
* Compiled with dtc -I dts -O dtb -o gef_sbc610.dtb gef_sbc610.dts * Compiled with dtc -I dts -O dtb -o gef_sbc610.dtb gef_sbc610.dts
*/ */
/dts-v1/; /include/ "mpc8641si-pre.dtsi"
/ { / {
model = "GEF_SBC610"; model = "GEF_SBC610";
compatible = "gef,sbc610"; compatible = "gef,sbc610";
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &enet0;
ethernet1 = &enet1;
serial0 = &serial0;
serial1 = &serial1;
pci0 = &pci0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8641@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <32768>; // L1, 32K
i-cache-size = <32768>; // L1, 32K
timebase-frequency = <0>; // From uboot
bus-frequency = <0>; // From uboot
clock-frequency = <0>; // From uboot
};
PowerPC,8641@1 {
device_type = "cpu";
reg = <1>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <32768>; // L1, 32K
i-cache-size = <32768>; // L1, 32K
timebase-frequency = <0>; // From uboot
bus-frequency = <0>; // From uboot
clock-frequency = <0>; // From uboot
};
};
memory { memory {
device_type = "memory"; device_type = "memory";
reg = <0x0 0x40000000>; // set by uboot reg = <0x0 0x40000000>; // set by uboot
}; };
localbus@fef05000 { lbc: localbus@fef05000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,mpc8641-localbus", "simple-bus";
reg = <0xfef05000 0x1000>; reg = <0xfef05000 0x1000>;
interrupts = <19 2>;
interrupt-parent = <&mpic>;
ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
1 0 0xe8000000 0x08000000 // Paged Flash 0 1 0 0xe8000000 0x08000000 // Paged Flash 0
...@@ -148,9 +105,7 @@ ...@@ -148,9 +105,7 @@
interrupt-controller; interrupt-controller;
compatible = "gef,fpga-pic"; compatible = "gef,fpga-pic";
reg = <0x4 0x4000 0x20>; reg = <0x4 0x4000 0x20>;
interrupts = <0x8 interrupts = <0x8 0x9 0 0>;
0x9>;
interrupt-parent = <&mpic>;
}; };
gef_gpio: gpio@7,14000 { gef_gpio: gpio@7,14000 {
...@@ -161,37 +116,10 @@ ...@@ -161,37 +116,10 @@
}; };
}; };
soc@fef00000 { soc: soc@fef00000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
compatible = "simple-bus";
ranges = <0x0 0xfef00000 0x00100000>; ranges = <0x0 0xfef00000 0x00100000>;
bus-frequency = <33333333>;
mcm-law@0 {
compatible = "fsl,mcm-law";
reg = <0x0 0x1000>;
fsl,num-laws = <10>;
};
mcm@1000 {
compatible = "fsl,mpc8641-mcm", "fsl,mcm";
reg = <0x1000 0x1000>;
interrupts = <17 2>;
interrupt-parent = <&mpic>;
};
i2c1: i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <0x2b 0x2>;
interrupt-parent = <&mpic>;
dfsrr;
i2c@3000 {
hwmon@48 { hwmon@48 {
compatible = "national,lm92"; compatible = "national,lm92";
reg = <0x48>; reg = <0x48>;
...@@ -213,204 +141,65 @@ ...@@ -213,204 +141,65 @@
}; };
}; };
i2c2: i2c@3100 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl-i2c";
reg = <0x3100 0x100>;
interrupts = <0x2b 0x2>;
interrupt-parent = <&mpic>;
dfsrr;
};
dma@21300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
reg = <0x21300 0x4>;
ranges = <0x0 0x21100 0x200>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,mpc8641-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
interrupt-parent = <&mpic>;
interrupts = <20 2>;
};
dma-channel@80 {
compatible = "fsl,mpc8641-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&mpic>;
interrupts = <21 2>;
};
dma-channel@100 {
compatible = "fsl,mpc8641-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&mpic>;
interrupts = <22 2>;
};
dma-channel@180 {
compatible = "fsl,mpc8641-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
interrupt-parent = <&mpic>;
interrupts = <23 2>;
};
};
enet0: ethernet@24000 { enet0: ethernet@24000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <0>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <0x24000 0x1000>;
ranges = <0x0 0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi0>; tbi-handle = <&tbi0>;
phy-handle = <&phy0>; phy-handle = <&phy0>;
phy-connection-type = "gmii"; phy-connection-type = "gmii";
};
mdio@520 { mdio@24520 {
#address-cells = <1>; phy0: ethernet-phy@0 {
#size-cells = <0>; interrupt-parent = <&gef_pic>;
compatible = "fsl,gianfar-mdio"; interrupts = <0x9 0x4>;
reg = <0x520 0x20>; reg = <1>;
};
phy0: ethernet-phy@0 { phy2: ethernet-phy@2 {
interrupt-parent = <&gef_pic>; interrupt-parent = <&gef_pic>;
interrupts = <0x9 0x4>; interrupts = <0x8 0x4>;
reg = <1>; reg = <3>;
}; };
phy2: ethernet-phy@2 { tbi0: tbi-phy@11 {
interrupt-parent = <&gef_pic>; reg = <0x11>;
interrupts = <0x8 0x4>; device_type = "tbi-phy";
reg = <3>;
};
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
}; };
}; };
enet1: ethernet@26000 { enet1: ethernet@26000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <2>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <0x26000 0x1000>;
ranges = <0x0 0x26000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <31 2 32 2 33 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi2>; tbi-handle = <&tbi2>;
phy-handle = <&phy2>; phy-handle = <&phy2>;
phy-connection-type = "gmii"; phy-connection-type = "gmii";
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x520 0x20>;
tbi2: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
}; };
serial0: serial@4500 { mdio@26520 {
cell-index = <0>; tbi2: tbi-phy@11 {
device_type = "serial"; reg = <0x11>;
compatible = "fsl,ns16550", "ns16550"; device_type = "tbi-phy";
reg = <0x4500 0x100>; };
clock-frequency = <0>;
interrupts = <0x2a 0x2>;
interrupt-parent = <&mpic>;
}; };
serial1: serial@4600 { enet2: ethernet@25000 {
cell-index = <1>; status = "disabled";
device_type = "serial";
compatible = "fsl,ns16550", "ns16550";
reg = <0x4600 0x100>;
clock-frequency = <0>;
interrupts = <0x1c 0x2>;
interrupt-parent = <&mpic>;
}; };
mpic: pic@40000 { mdio@25520 {
clock-frequency = <0>; status = "disabled";
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
}; };
msi@41600 { enet3: ethernet@27000 {
compatible = "fsl,mpc8641-msi", "fsl,mpic-msi"; status = "disabled";
reg = <0x41600 0x80>;
msi-available-ranges = <0 0x100>;
interrupts = <
0xe0 0
0xe1 0
0xe2 0
0xe3 0
0xe4 0
0xe5 0
0xe6 0
0xe7 0>;
interrupt-parent = <&mpic>;
}; };
global-utilities@e0000 { mdio@27520 {
compatible = "fsl,mpc8641-guts"; status = "disabled";
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
}; };
}; };
pci0: pcie@fef08000 { pci0: pcie@fef08000 {
compatible = "fsl,mpc8641-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0xfef08000 0x1000>; reg = <0xfef08000 0x1000>;
bus-range = <0x0 0xff>;
ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>; 0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <0x18 0x2>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
0x0000 0x0 0x0 0x1 &mpic 0x0 0x1
0x0000 0x0 0x0 0x2 &mpic 0x1 0x1
0x0000 0x0 0x0 0x3 &mpic 0x2 0x1
0x0000 0x0 0x0 0x4 &mpic 0x3 0x1
>;
pcie@0 { pcie@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <0x02000000 0x0 0x80000000 ranges = <0x02000000 0x0 0x80000000
0x02000000 0x0 0x80000000 0x02000000 0x0 0x80000000
0x0 0x40000000 0x0 0x40000000
...@@ -421,3 +210,5 @@ ...@@ -421,3 +210,5 @@
}; };
}; };
}; };
/include/ "mpc8641si-post.dtsi"
arch/powerpc/boot/dts/fsl/kmcoge4.dts
浏览文件 @ a1b53446
...@@ -63,7 +63,7 @@ ...@@ -63,7 +63,7 @@
flash@0 { flash@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "spansion,s25fl256s1"; compatible = "spansion,s25fl256s1", "jedec,spi-nor";
reg = <0>; reg = <0>;
spi-max-frequency = <20000000>; /* input clock */ spi-max-frequency = <20000000>; /* input clock */
}; };
...@@ -77,7 +77,7 @@ ...@@ -77,7 +77,7 @@
flash@2 { flash@2 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "micron,m25p32"; compatible = "micron,m25p32", "jedec,spi-nor";
reg = <2>; reg = <2>;
spi-max-frequency = <15000000>; spi-max-frequency = <15000000>;
}; };
......
arch/powerpc/boot/dts/fsl/mpc8536ds.dtsi
浏览文件 @ a1b53446
...@@ -142,7 +142,7 @@ ...@@ -142,7 +142,7 @@
flash@0 { flash@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "spansion,s25sl12801"; compatible = "spansion,s25sl12801", "jedec,spi-nor";
reg = <0>; reg = <0>;
spi-max-frequency = <40000000>; spi-max-frequency = <40000000>;
partition@u-boot { partition@u-boot {
...@@ -166,17 +166,17 @@ ...@@ -166,17 +166,17 @@
}; };
}; };
flash@1 { flash@1 {
compatible = "spansion,s25sl12801"; compatible = "spansion,s25sl12801", "jedec,spi-nor";
reg = <1>; reg = <1>;
spi-max-frequency = <40000000>; spi-max-frequency = <40000000>;
}; };
flash@2 { flash@2 {
compatible = "spansion,s25sl12801"; compatible = "spansion,s25sl12801", "jedec,spi-nor";
reg = <2>; reg = <2>;
spi-max-frequency = <40000000>; spi-max-frequency = <40000000>;
}; };
flash@3 { flash@3 {
compatible = "spansion,s25sl12801"; compatible = "spansion,s25sl12801", "jedec,spi-nor";
reg = <3>; reg = <3>;
spi-max-frequency = <40000000>; spi-max-frequency = <40000000>;
}; };
......
arch/powerpc/boot/dts/mpc8641_hpcn.dts → arch/powerpc/boot/dts/fsl/mpc8641_hpcn.dts
浏览文件 @ a1b53446
...@@ -9,65 +9,23 @@ ...@@ -9,65 +9,23 @@
* option) any later version. * option) any later version.
*/ */
/dts-v1/; /include/ "mpc8641si-pre.dtsi"
/ { / {
model = "MPC8641HPCN"; model = "MPC8641HPCN";
compatible = "fsl,mpc8641hpcn"; compatible = "fsl,mpc8641hpcn";
#address-cells = <1>;
#size-cells = <1>;
aliases { aliases {
ethernet0 = &enet0;
ethernet1 = &enet1;
ethernet2 = &enet2;
ethernet3 = &enet3;
serial0 = &serial0;
serial1 = &serial1;
pci0 = &pci0;
pci1 = &pci1; pci1 = &pci1;
}; };
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8641@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <32>;
i-cache-line-size = <32>;
d-cache-size = <32768>; // L1
i-cache-size = <32768>; // L1
timebase-frequency = <0>; // From uboot
bus-frequency = <0>; // From uboot
clock-frequency = <0>; // From uboot
};
PowerPC,8641@1 {
device_type = "cpu";
reg = <1>;
d-cache-line-size = <32>;
i-cache-line-size = <32>;
d-cache-size = <32768>;
i-cache-size = <32768>;
timebase-frequency = <0>; // From uboot
bus-frequency = <0>; // From uboot
clock-frequency = <0>; // From uboot
};
};
memory { memory {
device_type = "memory"; device_type = "memory";
reg = <0x00000000 0x40000000>; // 1G at 0x0 reg = <0x00000000 0x40000000>; // 1G at 0x0
}; };
localbus@ffe05000 { lbc: localbus@ffe05000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,mpc8641-localbus", "simple-bus";
reg = <0xffe05000 0x1000>; reg = <0xffe05000 0x1000>;
interrupts = <19 2>;
interrupt-parent = <&mpic>;
ranges = <0 0 0xef800000 0x00800000 ranges = <0 0 0xef800000 0x00800000
2 0 0xffdf8000 0x00008000 2 0 0xffdf8000 0x00008000
...@@ -101,253 +59,75 @@ ...@@ -101,253 +59,75 @@
}; };
}; };
soc8641@ffe00000 { soc: soc8641@ffe00000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "simple-bus";
ranges = <0x00000000 0xffe00000 0x00100000>; ranges = <0x00000000 0xffe00000 0x00100000>;
bus-frequency = <0>;
mcm-law@0 {
compatible = "fsl,mcm-law";
reg = <0x0 0x1000>;
fsl,num-laws = <10>;
};
mcm@1000 {
compatible = "fsl,mpc8641-mcm", "fsl,mcm";
reg = <0x1000 0x1000>;
interrupts = <17 2>;
interrupt-parent = <&mpic>;
};
i2c@3000 { enet0: ethernet@24000 {
#address-cells = <1>; tbi-handle = <&tbi0>;
#size-cells = <0>; phy-handle = <&phy0>;
cell-index = <0>; phy-connection-type = "rgmii-id";
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
i2c@3100 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
compatible = "fsl-i2c";
reg = <0x3100 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
}; };
dma@21300 { mdio@24520 {
#address-cells = <1>; phy0: ethernet-phy@0 {
#size-cells = <1>; interrupts = <10 1 0 0>;
compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma"; reg = <0>;
reg = <0x21300 0x4>;
ranges = <0x0 0x21100 0x200>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,mpc8641-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
interrupt-parent = <&mpic>;
interrupts = <20 2>;
}; };
dma-channel@80 { phy1: ethernet-phy@1 {
compatible = "fsl,mpc8641-dma-channel", interrupts = <10 1 0 0>;
"fsl,eloplus-dma-channel"; reg = <1>;
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&mpic>;
interrupts = <21 2>;
}; };
dma-channel@100 { phy2: ethernet-phy@2 {
compatible = "fsl,mpc8641-dma-channel", interrupts = <10 1 0 0>;
"fsl,eloplus-dma-channel"; reg = <2>;
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&mpic>;
interrupts = <22 2>;
}; };
dma-channel@180 { phy3: ethernet-phy@3 {
compatible = "fsl,mpc8641-dma-channel", interrupts = <10 1 0 0>;
"fsl,eloplus-dma-channel"; reg = <3>;
reg = <0x180 0x80>;
cell-index = <3>;
interrupt-parent = <&mpic>;
interrupts = <23 2>;
}; };
}; tbi0: tbi-phy@11 {
reg = <0x11>;
enet0: ethernet@24000 { device_type = "tbi-phy";
#address-cells = <1>;
#size-cells = <1>;
cell-index = <0>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <0x24000 0x1000>;
ranges = <0x0 0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi0>;
phy-handle = <&phy0>;
phy-connection-type = "rgmii-id";
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <0x520 0x20>;
phy0: ethernet-phy@0 {
interrupt-parent = <&mpic>;
interrupts = <10 1>;
reg = <0>;
};
phy1: ethernet-phy@1 {
interrupt-parent = <&mpic>;
interrupts = <10 1>;
reg = <1>;
};
phy2: ethernet-phy@2 {
interrupt-parent = <&mpic>;
interrupts = <10 1>;
reg = <2>;
};
phy3: ethernet-phy@3 {
interrupt-parent = <&mpic>;
interrupts = <10 1>;
reg = <3>;
};
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
}; };
}; };
enet1: ethernet@25000 { enet1: ethernet@25000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <1>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <0x25000 0x1000>;
ranges = <0x0 0x25000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <35 2 36 2 40 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi1>; tbi-handle = <&tbi1>;
phy-handle = <&phy1>; phy-handle = <&phy1>;
phy-connection-type = "rgmii-id"; phy-connection-type = "rgmii-id";
};
mdio@520 { mdio@25520 {
#address-cells = <1>; tbi1: tbi-phy@11 {
#size-cells = <0>; reg = <0x11>;
compatible = "fsl,gianfar-tbi"; device_type = "tbi-phy";
reg = <0x520 0x20>;
tbi1: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
}; };
}; };
enet2: ethernet@26000 { enet2: ethernet@26000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <2>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <0x26000 0x1000>;
ranges = <0x0 0x26000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <31 2 32 2 33 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi2>; tbi-handle = <&tbi2>;
phy-handle = <&phy2>; phy-handle = <&phy2>;
phy-connection-type = "rgmii-id"; phy-connection-type = "rgmii-id";
};
mdio@520 { mdio@26520 {
#address-cells = <1>; tbi2: tbi-phy@11 {
#size-cells = <0>; reg = <0x11>;
compatible = "fsl,gianfar-tbi"; device_type = "tbi-phy";
reg = <0x520 0x20>;
tbi2: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
}; };
}; };
enet3: ethernet@27000 { enet3: ethernet@27000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <3>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <0x27000 0x1000>;
ranges = <0x0 0x27000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <37 2 38 2 39 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi3>; tbi-handle = <&tbi3>;
phy-handle = <&phy3>; phy-handle = <&phy3>;
phy-connection-type = "rgmii-id"; phy-connection-type = "rgmii-id";
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x520 0x20>;
tbi3: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
}; };
serial0: serial@4500 { mdio@27520 {
cell-index = <0>; tbi3: tbi-phy@11 {
device_type = "serial"; reg = <0x11>;
compatible = "fsl,ns16550", "ns16550"; device_type = "tbi-phy";
reg = <0x4500 0x100>; };
clock-frequency = <0>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
serial1: serial@4600 {
cell-index = <1>;
device_type = "serial";
compatible = "fsl,ns16550", "ns16550";
reg = <0x4600 0x100>;
clock-frequency = <0>;
interrupts = <28 2>;
interrupt-parent = <&mpic>;
};
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
}; };
rmu: rmu@d3000 { rmu: rmu@d3000 {
...@@ -361,50 +141,35 @@ ...@@ -361,50 +141,35 @@
compatible = "fsl,srio-msg-unit"; compatible = "fsl,srio-msg-unit";
reg = <0x0 0x100>; reg = <0x0 0x100>;
interrupts = < interrupts = <
53 2 /* msg1_tx_irq */ 53 2 0 0 /* msg1_tx_irq */
54 2>;/* msg1_rx_irq */ 54 2 0 0>;/* msg1_rx_irq */
}; };
message-unit@100 { message-unit@100 {
compatible = "fsl,srio-msg-unit"; compatible = "fsl,srio-msg-unit";
reg = <0x100 0x100>; reg = <0x100 0x100>;
interrupts = < interrupts = <
55 2 /* msg2_tx_irq */ 55 2 0 0 /* msg2_tx_irq */
56 2>;/* msg2_rx_irq */ 56 2 0 0>;/* msg2_rx_irq */
}; };
doorbell-unit@400 { doorbell-unit@400 {
compatible = "fsl,srio-dbell-unit"; compatible = "fsl,srio-dbell-unit";
reg = <0x400 0x80>; reg = <0x400 0x80>;
interrupts = < interrupts = <
49 2 /* bell_outb_irq */ 49 2 0 0 /* bell_outb_irq */
50 2>;/* bell_inb_irq */ 50 2 0 0>;/* bell_inb_irq */
}; };
port-write-unit@4e0 { port-write-unit@4e0 {
compatible = "fsl,srio-port-write-unit"; compatible = "fsl,srio-port-write-unit";
reg = <0x4e0 0x20>; reg = <0x4e0 0x20>;
interrupts = <48 2>; interrupts = <48 2 0 0>;
}; };
}; };
global-utilities@e0000 {
compatible = "fsl,mpc8641-guts";
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
}; };
pci0: pcie@ffe08000 { pci0: pcie@ffe08000 {
compatible = "fsl,mpc8641-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0xffe08000 0x1000>; reg = <0xffe08000 0x1000>;
bus-range = <0x0 0xff>;
ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
0x01000000 0x0 0x00000000 0xffc00000 0x0 0x00010000>; 0x01000000 0x0 0x00000000 0xffc00000 0x0 0x00010000>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <24 2>;
interrupt-map-mask = <0xff00 0 0 7>; interrupt-map-mask = <0xff00 0 0 7>;
interrupt-map = < interrupt-map = <
/* IDSEL 0x11 func 0 - PCI slot 1 */ /* IDSEL 0x11 func 0 - PCI slot 1 */
...@@ -522,10 +287,6 @@ ...@@ -522,10 +287,6 @@
>; >;
pcie@0 { pcie@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <0x02000000 0x0 0x80000000 ranges = <0x02000000 0x0 0x80000000
0x02000000 0x0 0x80000000 0x02000000 0x0 0x80000000
0x0 0x20000000 0x0 0x20000000
...@@ -545,7 +306,6 @@ ...@@ -545,7 +306,6 @@
0x0 0x00010000>; 0x0 0x00010000>;
isa@1e { isa@1e {
device_type = "isa"; device_type = "isa";
#interrupt-cells = <2>;
#size-cells = <1>; #size-cells = <1>;
#address-cells = <2>; #address-cells = <2>;
reg = <0xf000 0 0 0 0>; reg = <0xf000 0 0 0 0>;
...@@ -562,8 +322,7 @@ ...@@ -562,8 +322,7 @@
#address-cells = <0>; #address-cells = <0>;
#interrupt-cells = <2>; #interrupt-cells = <2>;
compatible = "chrp,iic"; compatible = "chrp,iic";
interrupts = <9 2>; interrupts = <9 2 0 0>;
interrupt-parent = <&mpic>;
}; };
i8042@60 { i8042@60 {
...@@ -571,8 +330,7 @@ ...@@ -571,8 +330,7 @@
#address-cells = <1>; #address-cells = <1>;
reg = <1 0x60 1 1 0x64 1>; reg = <1 0x60 1 1 0x64 1>;
interrupts = <1 3 12 3>; interrupts = <1 3 12 3>;
interrupt-parent = interrupt-parent = <&i8259>;
<&i8259>;
keyboard@0 { keyboard@0 {
reg = <0>; reg = <0>;
...@@ -603,16 +361,14 @@ ...@@ -603,16 +361,14 @@
pci1: pcie@ffe09000 { pci1: pcie@ffe09000 {
compatible = "fsl,mpc8641-pcie"; compatible = "fsl,mpc8641-pcie";
device_type = "pci"; device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
reg = <0xffe09000 0x1000>; reg = <0xffe09000 0x1000>;
bus-range = <0 0xff>; bus-range = <0 0xff>;
ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
0x01000000 0x0 0x00000000 0xffc10000 0x0 0x00010000>; 0x01000000 0x0 0x00000000 0xffc10000 0x0 0x00010000>;
clock-frequency = <33333333>; clock-frequency = <100000000>;
interrupt-parent = <&mpic>; interrupts = <25 2 0 0>;
interrupts = <25 2>;
interrupt-map-mask = <0xf800 0 0 7>; interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = < interrupt-map = <
/* IDSEL 0x0 */ /* IDSEL 0x0 */
...@@ -644,8 +400,7 @@ ...@@ -644,8 +400,7 @@
rapidio@ffec0000 { rapidio@ffec0000 {
reg = <0xffec0000 0x11000>; reg = <0xffec0000 0x11000>;
compatible = "fsl,srio"; compatible = "fsl,srio";
interrupt-parent = <&mpic>; interrupts = <48 2 0 0>;
interrupts = <48 2>;
#address-cells = <2>; #address-cells = <2>;
#size-cells = <2>; #size-cells = <2>;
fsl,srio-rmu-handle = <&rmu>; fsl,srio-rmu-handle = <&rmu>;
...@@ -661,3 +416,5 @@ ...@@ -661,3 +416,5 @@
*/ */
}; };
/include/ "mpc8641si-post.dtsi"
arch/powerpc/boot/dts/mpc8641_hpcn_36b.dts → arch/powerpc/boot/dts/fsl/mpc8641_hpcn_36b.dts
浏览文件 @ a1b53446
...@@ -9,7 +9,7 @@ ...@@ -9,7 +9,7 @@
* option) any later version. * option) any later version.
*/ */
/dts-v1/; /include/ "mpc8641si-pre.dtsi"
/ { / {
model = "MPC8641HPCN"; model = "MPC8641HPCN";
...@@ -18,56 +18,16 @@ ...@@ -18,56 +18,16 @@
#size-cells = <2>; #size-cells = <2>;
aliases { aliases {
ethernet0 = &enet0;
ethernet1 = &enet1;
ethernet2 = &enet2;
ethernet3 = &enet3;
serial0 = &serial0;
serial1 = &serial1;
pci0 = &pci0;
pci1 = &pci1; pci1 = &pci1;
}; };
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8641@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <32768>; // L1, 32K
i-cache-size = <32768>; // L1, 32K
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // From uboot
clock-frequency = <0>; // From uboot
};
PowerPC,8641@1 {
device_type = "cpu";
reg = <1>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <32768>; // L1, 32K
i-cache-size = <32768>; // L1, 32K
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // From uboot
clock-frequency = <0>; // From uboot
};
};
memory { memory {
device_type = "memory"; device_type = "memory";
reg = <0x0 0x00000000 0x0 0x40000000>; // 1G at 0x0 reg = <0x0 0x00000000 0x0 0x40000000>; // 1G at 0x0
}; };
localbus@fffe05000 { lbc: localbus@fffe05000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,mpc8641-localbus", "simple-bus";
reg = <0x0f 0xffe05000 0x0 0x1000>; reg = <0x0f 0xffe05000 0x0 0x1000>;
interrupts = <19 2>;
interrupt-parent = <&mpic>;
ranges = <0 0 0xf 0xef800000 0x00800000 ranges = <0 0 0xf 0xef800000 0x00800000
2 0 0xf 0xffdf8000 0x00008000 2 0 0xf 0xffdf8000 0x00008000
...@@ -101,276 +61,82 @@ ...@@ -101,276 +61,82 @@
}; };
}; };
soc8641@fffe00000 { soc: soc8641@fffe00000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "simple-bus";
ranges = <0x00000000 0x0f 0xffe00000 0x00100000>; ranges = <0x00000000 0x0f 0xffe00000 0x00100000>;
bus-frequency = <0>;
mcm-law@0 { enet0: ethernet@24000 {
compatible = "fsl,mcm-law"; tbi-handle = <&tbi0>;
reg = <0x0 0x1000>; phy-handle = <&phy0>;
fsl,num-laws = <10>; phy-connection-type = "rgmii-id";
};
mcm@1000 {
compatible = "fsl,mpc8641-mcm", "fsl,mcm";
reg = <0x1000 0x1000>;
interrupts = <17 2>;
interrupt-parent = <&mpic>;
};
i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
i2c@3100 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
compatible = "fsl-i2c";
reg = <0x3100 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
}; };
dma@21300 { mdio@24520 {
#address-cells = <1>; phy0: ethernet-phy@0 {
#size-cells = <1>; interrupts = <10 1 0 0>;
compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma"; reg = <0>;
reg = <0x21300 0x4>;
ranges = <0x0 0x21100 0x200>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,mpc8641-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
interrupt-parent = <&mpic>;
interrupts = <20 2>;
}; };
dma-channel@80 { phy1: ethernet-phy@1 {
compatible = "fsl,mpc8641-dma-channel", interrupts = <10 1 0 0>;
"fsl,eloplus-dma-channel"; reg = <1>;
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&mpic>;
interrupts = <21 2>;
}; };
dma-channel@100 { phy2: ethernet-phy@2 {
compatible = "fsl,mpc8641-dma-channel", interrupts = <10 1 0 0>;
"fsl,eloplus-dma-channel"; reg = <2>;
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&mpic>;
interrupts = <22 2>;
}; };
dma-channel@180 { phy3: ethernet-phy@3 {
compatible = "fsl,mpc8641-dma-channel", interrupts = <10 1 0 0>;
"fsl,eloplus-dma-channel"; reg = <3>;
reg = <0x180 0x80>;
cell-index = <3>;
interrupt-parent = <&mpic>;
interrupts = <23 2>;
}; };
}; tbi0: tbi-phy@11 {
reg = <0x11>;
enet0: ethernet@24000 { device_type = "tbi-phy";
#address-cells = <1>;
#size-cells = <1>;
cell-index = <0>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <0x24000 0x1000>;
ranges = <0x0 0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi0>;
phy-handle = <&phy0>;
phy-connection-type = "rgmii-id";
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <0x520 0x20>;
phy0: ethernet-phy@0 {
interrupt-parent = <&mpic>;
interrupts = <10 1>;
reg = <0>;
};
phy1: ethernet-phy@1 {
interrupt-parent = <&mpic>;
interrupts = <10 1>;
reg = <1>;
};
phy2: ethernet-phy@2 {
interrupt-parent = <&mpic>;
interrupts = <10 1>;
reg = <2>;
};
phy3: ethernet-phy@3 {
interrupt-parent = <&mpic>;
interrupts = <10 1>;
reg = <3>;
};
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
}; };
}; };
enet1: ethernet@25000 { enet1: ethernet@25000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <1>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <0x25000 0x1000>;
ranges = <0x0 0x25000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <35 2 36 2 40 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi1>; tbi-handle = <&tbi1>;
phy-handle = <&phy1>; phy-handle = <&phy1>;
phy-connection-type = "rgmii-id"; phy-connection-type = "rgmii-id";
};
mdio@520 { mdio@25520 {
#address-cells = <1>; tbi1: tbi-phy@11 {
#size-cells = <0>; reg = <0x11>;
compatible = "fsl,gianfar-tbi"; device_type = "tbi-phy";
reg = <0x520 0x20>;
tbi1: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
}; };
}; };
enet2: ethernet@26000 { enet2: ethernet@26000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <2>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <0x26000 0x1000>;
ranges = <0x0 0x26000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <31 2 32 2 33 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi2>; tbi-handle = <&tbi2>;
phy-handle = <&phy2>; phy-handle = <&phy2>;
phy-connection-type = "rgmii-id"; phy-connection-type = "rgmii-id";
};
mdio@520 { mdio@26520 {
#address-cells = <1>; tbi2: tbi-phy@11 {
#size-cells = <0>; reg = <0x11>;
compatible = "fsl,gianfar-tbi"; device_type = "tbi-phy";
reg = <0x520 0x20>;
tbi2: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
}; };
}; };
enet3: ethernet@27000 { enet3: ethernet@27000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <3>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <0x27000 0x1000>;
ranges = <0x0 0x27000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <37 2 38 2 39 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi3>; tbi-handle = <&tbi3>;
phy-handle = <&phy3>; phy-handle = <&phy3>;
phy-connection-type = "rgmii-id"; phy-connection-type = "rgmii-id";
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x520 0x20>;
tbi3: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
}; };
serial0: serial@4500 { mdio@27520 {
cell-index = <0>; tbi3: tbi-phy@11 {
device_type = "serial"; reg = <0x11>;
compatible = "fsl,ns16550", "ns16550"; device_type = "tbi-phy";
reg = <0x4500 0x100>; };
clock-frequency = <0>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
serial1: serial@4600 {
cell-index = <1>;
device_type = "serial";
compatible = "fsl,ns16550", "ns16550";
reg = <0x4600 0x100>;
clock-frequency = <0>;
interrupts = <28 2>;
interrupt-parent = <&mpic>;
};
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
};
global-utilities@e0000 {
compatible = "fsl,mpc8641-guts";
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
}; };
}; };
pci0: pcie@fffe08000 { pci0: pcie@fffe08000 {
cell-index = <0>;
compatible = "fsl,mpc8641-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0x0f 0xffe08000 0x0 0x1000>; reg = <0x0f 0xffe08000 0x0 0x1000>;
bus-range = <0x0 0xff>;
ranges = <0x02000000 0x0 0xe0000000 0x0c 0x00000000 0x0 0x20000000 ranges = <0x02000000 0x0 0xe0000000 0x0c 0x00000000 0x0 0x20000000
0x01000000 0x0 0x00000000 0x0f 0xffc00000 0x0 0x00010000>; 0x01000000 0x0 0x00000000 0x0f 0xffc00000 0x0 0x00010000>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <24 2>;
interrupt-map-mask = <0xff00 0 0 7>; interrupt-map-mask = <0xff00 0 0 7>;
interrupt-map = < interrupt-map = <
/* IDSEL 0x11 func 0 - PCI slot 1 */ /* IDSEL 0x11 func 0 - PCI slot 1 */
...@@ -488,10 +254,6 @@ ...@@ -488,10 +254,6 @@
>; >;
pcie@0 { pcie@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <0x02000000 0x0 0xe0000000 ranges = <0x02000000 0x0 0xe0000000
0x02000000 0x0 0xe0000000 0x02000000 0x0 0xe0000000
0x0 0x20000000 0x0 0x20000000
...@@ -511,7 +273,6 @@ ...@@ -511,7 +273,6 @@
0x0 0x00010000>; 0x0 0x00010000>;
isa@1e { isa@1e {
device_type = "isa"; device_type = "isa";
#interrupt-cells = <2>;
#size-cells = <1>; #size-cells = <1>;
#address-cells = <2>; #address-cells = <2>;
reg = <0xf000 0 0 0 0>; reg = <0xf000 0 0 0 0>;
...@@ -528,8 +289,7 @@ ...@@ -528,8 +289,7 @@
#address-cells = <0>; #address-cells = <0>;
#interrupt-cells = <2>; #interrupt-cells = <2>;
compatible = "chrp,iic"; compatible = "chrp,iic";
interrupts = <9 2>; interrupts = <9 2 0 0>;
interrupt-parent = <&mpic>;
}; };
i8042@60 { i8042@60 {
...@@ -537,8 +297,7 @@ ...@@ -537,8 +297,7 @@
#address-cells = <1>; #address-cells = <1>;
reg = <1 0x60 1 1 0x64 1>; reg = <1 0x60 1 1 0x64 1>;
interrupts = <1 3 12 3>; interrupts = <1 3 12 3>;
interrupt-parent = interrupt-parent = <&i8259>;
<&i8259>;
keyboard@0 { keyboard@0 {
reg = <0>; reg = <0>;
...@@ -567,19 +326,16 @@ ...@@ -567,19 +326,16 @@
}; };
pci1: pcie@fffe09000 { pci1: pcie@fffe09000 {
cell-index = <1>;
compatible = "fsl,mpc8641-pcie"; compatible = "fsl,mpc8641-pcie";
device_type = "pci"; device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
reg = <0x0f 0xffe09000 0x0 0x1000>; reg = <0x0f 0xffe09000 0x0 0x1000>;
bus-range = <0x0 0xff>; bus-range = <0x0 0xff>;
ranges = <0x02000000 0x0 0xe0000000 0x0c 0x20000000 0x0 0x20000000 ranges = <0x02000000 0x0 0xe0000000 0x0c 0x20000000 0x0 0x20000000
0x01000000 0x0 0x00000000 0x0f 0xffc10000 0x0 0x00010000>; 0x01000000 0x0 0x00000000 0x0f 0xffc10000 0x0 0x00010000>;
clock-frequency = <33333333>; clock-frequency = <100000000>;
interrupt-parent = <&mpic>; interrupts = <25 2 0 0>;
interrupts = <25 2>;
interrupt-map-mask = <0xf800 0 0 7>; interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = < interrupt-map = <
/* IDSEL 0x0 */ /* IDSEL 0x0 */
...@@ -603,3 +359,5 @@ ...@@ -603,3 +359,5 @@
}; };
}; };
}; };
/include/ "mpc8641si-post.dtsi"
arch/powerpc/boot/dts/fsl/mpc8641si-post.dtsi 0 → 100644
浏览文件 @ a1b53446
/*
* MPC8641 Silicon/SoC Device Tree Source (post include)
*
* Copyright 2016 Elettra-Sincrotrone Trieste S.C.p.A.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
&lbc {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,mpc8641-localbus", "simple-bus";
interrupts = <19 2 0 0>;
};
&soc {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "fsl,mpc8641-soc", "simple-bus";
bus-frequency = <0>;
mcm-law@0 {
compatible = "fsl,mcm-law";
reg = <0x0 0x1000>;
fsl,num-laws = <10>;
};
mcm@1000 {
compatible = "fsl,mpc8641-mcm", "fsl,mcm";
reg = <0x1000 0x1000>;
interrupts = <17 2 0 0>;
};
/include/ "pq3-i2c-0.dtsi"
/include/ "pq3-i2c-1.dtsi"
/include/ "pq3-duart-0.dtsi"
serial@4600 {
interrupts = <28 2 0 0>;
};
/include/ "pq3-dma-0.dtsi"
dma@21300 {
compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
};
dma-channel@0 {
compatible = "fsl,mpc8641-dma-channel", "fsl,eloplus-dma-channel";
};
dma-channel@80 {
compatible = "fsl,mpc8641-dma-channel", "fsl,eloplus-dma-channel";
};
dma-channel@100 {
compatible = "fsl,mpc8641-dma-channel", "fsl,eloplus-dma-channel";
};
dma-channel@180 {
compatible = "fsl,mpc8641-dma-channel", "fsl,eloplus-dma-channel";
};
/include/ "pq3-etsec1-0.dtsi"
ethernet@24000 {
model = "TSEC";
};
/include/ "pq3-etsec1-1.dtsi"
ethernet@25000 {
model = "TSEC";
};
/include/ "pq3-etsec1-2.dtsi"
ethernet@26000 {
model = "TSEC";
};
/include/ "pq3-etsec1-3.dtsi"
ethernet@27000 {
model = "TSEC";
};
/include/ "qoriq-mpic.dtsi"
msi@41600 {
compatible = "fsl,mpc8641-msi", "fsl,mpic-msi";
};
msi@41800 {
compatible = "fsl,mpc8641-msi", "fsl,mpic-msi";
};
msi@41a00 {
compatible = "fsl,mpc8641-msi", "fsl,mpic-msi";
};
global-utilities@e0000 {
compatible = "fsl,mpc8641-guts";
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
};
&pci0 {
compatible = "fsl,mpc8641-pcie";
device_type = "pci";
#size-cells = <2>;
#address-cells = <3>;
bus-range = <0x0 0xff>;
clock-frequency = <100000000>;
interrupts = <24 2 0 0>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
0x0000 0x0 0x0 0x1 &mpic 0x0 0x1
0x0000 0x0 0x0 0x2 &mpic 0x1 0x1
0x0000 0x0 0x0 0x3 &mpic 0x2 0x1
0x0000 0x0 0x0 0x4 &mpic 0x3 0x1
>;
pcie@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
};
};
arch/powerpc/boot/dts/fsl/mpc8641si-pre.dtsi 0 → 100644
浏览文件 @ a1b53446
/*
* MPC8641 Silicon/SoC Device Tree Source (pre include)
*
* Copyright 2016 Elettra-Sincrotrone Trieste S.C.p.A.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
/dts-v1/;
/ {
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&mpic>;
aliases {
ethernet0 = &enet0;
ethernet1 = &enet1;
ethernet2 = &enet2;
ethernet3 = &enet3;
serial0 = &serial0;
serial1 = &serial1;
pci0 = &pci0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8641@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <32>;
i-cache-line-size = <32>;
d-cache-size = <32768>;
i-cache-size = <32768>;
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
};
PowerPC,8641@1 {
device_type = "cpu";
reg = <1>;
d-cache-line-size = <32>;
i-cache-line-size = <32>;
d-cache-size = <32768>;
i-cache-size = <32768>;
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
};
};
};
arch/powerpc/boot/dts/fsl/mvme2500.dts
浏览文件 @ a1b53446
...@@ -70,12 +70,12 @@ ...@@ -70,12 +70,12 @@
fsl,espi-num-chipselects = <2>; fsl,espi-num-chipselects = <2>;
flash@0 { flash@0 {
compatible = "atmel,at25df641"; compatible = "atmel,at25df641", "jedec,spi-nor";
reg = <0>; reg = <0>;
spi-max-frequency = <10000000>; spi-max-frequency = <10000000>;
}; };
flash@1 { flash@1 {
compatible = "atmel,at25df641"; compatible = "atmel,at25df641", "jedec,spi-nor";
reg = <1>; reg = <1>;
spi-max-frequency = <10000000>; spi-max-frequency = <10000000>;
}; };
......
arch/powerpc/boot/dts/fsl/p1010rdb.dtsi
浏览文件 @ a1b53446
...@@ -110,7 +110,7 @@ ...@@ -110,7 +110,7 @@
flash@0 { flash@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "spansion,s25sl12801"; compatible = "spansion,s25sl12801", "jedec,spi-nor";
reg = <0>; reg = <0>;
spi-max-frequency = <40000000>; spi-max-frequency = <40000000>;
......
arch/powerpc/boot/dts/fsl/p1020rdb-pc.dtsi
浏览文件 @ a1b53446
...@@ -151,7 +151,7 @@ ...@@ -151,7 +151,7 @@
flash@0 { flash@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "spansion,s25sl12801"; compatible = "spansion,s25sl12801", "jedec,spi-nor";
reg = <0>; reg = <0>;
spi-max-frequency = <40000000>; /* input clock */ spi-max-frequency = <40000000>; /* input clock */
......
arch/powerpc/boot/dts/fsl/p1020rdb-pd.dts
浏览文件 @ a1b53446
...@@ -155,7 +155,7 @@ ...@@ -155,7 +155,7 @@
flash@0 { flash@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "spansion,s25sl12801"; compatible = "spansion,s25sl12801", "jedec,spi-nor";
reg = <0>; reg = <0>;
/* input clock */ /* input clock */
spi-max-frequency = <40000000>; spi-max-frequency = <40000000>;
......
arch/powerpc/boot/dts/fsl/p1020rdb.dtsi
浏览文件 @ a1b53446
...@@ -148,7 +148,7 @@ ...@@ -148,7 +148,7 @@
flash@0 { flash@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "spansion,s25sl12801"; compatible = "spansion,s25sl12801", "jedec,spi-nor";
reg = <0>; reg = <0>;
spi-max-frequency = <40000000>; /* input clock */ spi-max-frequency = <40000000>; /* input clock */
......
arch/powerpc/boot/dts/fsl/p1021mds.dts
浏览文件 @ a1b53446
...@@ -123,7 +123,7 @@ ...@@ -123,7 +123,7 @@
flash@0 { flash@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "spansion,s25sl12801"; compatible = "spansion,s25sl12801", "jedec,spi-nor";
reg = <0>; reg = <0>;
spi-max-frequency = <40000000>; /* input clock */ spi-max-frequency = <40000000>; /* input clock */
......
arch/powerpc/boot/dts/fsl/p1021rdb-pc.dtsi
浏览文件 @ a1b53446
...@@ -150,7 +150,7 @@ ...@@ -150,7 +150,7 @@
flash@0 { flash@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "spansion,s25sl12801"; compatible = "spansion,s25sl12801", "jedec,spi-nor";
reg = <0>; reg = <0>;
spi-max-frequency = <40000000>; /* input clock */ spi-max-frequency = <40000000>; /* input clock */
......
arch/powerpc/boot/dts/fsl/p1022ds.dtsi
浏览文件 @ a1b53446
...@@ -160,7 +160,7 @@ ...@@ -160,7 +160,7 @@
flash@0 { flash@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "spansion,s25sl12801"; compatible = "spansion,s25sl12801", "jedec,spi-nor";
reg = <0>; reg = <0>;
spi-max-frequency = <40000000>; /* input clock */ spi-max-frequency = <40000000>; /* input clock */
......
arch/powerpc/boot/dts/fsl/p1022rdk.dts
浏览文件 @ a1b53446
...@@ -86,7 +86,7 @@ ...@@ -86,7 +86,7 @@
flash@0 { flash@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "spansion,m25p80"; compatible = "spansion,m25p80", "jedec,spi-nor";
reg = <0>; reg = <0>;
spi-max-frequency = <1000000>; spi-max-frequency = <1000000>;
partition@0 { partition@0 {
......
arch/powerpc/boot/dts/fsl/p1024rdb.dtsi
浏览文件 @ a1b53446
...@@ -129,7 +129,7 @@ ...@@ -129,7 +129,7 @@
flash@0 { flash@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "spansion,m25p80"; compatible = "spansion,m25p80", "jedec,spi-nor";
reg = <0>; reg = <0>;
spi-max-frequency = <40000000>; spi-max-frequency = <40000000>;
......
arch/powerpc/boot/dts/fsl/p1025rdb.dtsi
浏览文件 @ a1b53446
...@@ -137,7 +137,7 @@ ...@@ -137,7 +137,7 @@
flash@0 { flash@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "spansion,s25sl12801"; compatible = "spansion,s25sl12801", "jedec,spi-nor";
reg = <0>; reg = <0>;
spi-max-frequency = <40000000>; /* input clock */ spi-max-frequency = <40000000>; /* input clock */
......
arch/powerpc/boot/dts/fsl/p2020rdb-pc.dtsi
浏览文件 @ a1b53446
...@@ -151,7 +151,7 @@ ...@@ -151,7 +151,7 @@
flash@0 { flash@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "spansion,m25p80"; compatible = "spansion,m25p80", "jedec,spi-nor";
reg = <0>; reg = <0>;
spi-max-frequency = <40000000>; spi-max-frequency = <40000000>;
......
arch/powerpc/boot/dts/fsl/p2020rdb.dts
浏览文件 @ a1b53446
...@@ -155,7 +155,7 @@ ...@@ -155,7 +155,7 @@
flash@0 { flash@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "spansion,s25sl12801"; compatible = "spansion,s25sl12801", "jedec,spi-nor";
reg = <0>; reg = <0>;
spi-max-frequency = <40000000>; spi-max-frequency = <40000000>;
......
arch/powerpc/boot/dts/fsl/p2041rdb.dts
浏览文件 @ a1b53446
/* /*
* P2041RDB Device Tree Source * P2041RDB Device Tree Source
* *
* Copyright 2011 - 2014 Freescale Semiconductor Inc. * Copyright 2011 - 2015 Freescale Semiconductor Inc.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -41,6 +41,19 @@ ...@@ -41,6 +41,19 @@
#size-cells = <2>; #size-cells = <2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
aliases {
phy_rgmii_0 = &phy_rgmii_0;
phy_rgmii_1 = &phy_rgmii_1;
phy_sgmii_2 = &phy_sgmii_2;
phy_sgmii_3 = &phy_sgmii_3;
phy_sgmii_4 = &phy_sgmii_4;
phy_sgmii_1c = &phy_sgmii_1c;
phy_sgmii_1d = &phy_sgmii_1d;
phy_sgmii_1e = &phy_sgmii_1e;
phy_sgmii_1f = &phy_sgmii_1f;
phy_xgmii_2 = &phy_xgmii_2;
};
memory { memory {
device_type = "memory"; device_type = "memory";
}; };
...@@ -83,7 +96,7 @@ ...@@ -83,7 +96,7 @@
flash@0 { flash@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "spansion,s25sl12801"; compatible = "spansion,s25sl12801", "jedec,spi-nor";
reg = <0>; reg = <0>;
spi-max-frequency = <40000000>; /* input clock */ spi-max-frequency = <40000000>; /* input clock */
partition@u-boot { partition@u-boot {
...@@ -137,6 +150,83 @@ ...@@ -137,6 +150,83 @@
usb1: usb@211000 { usb1: usb@211000 {
dr_mode = "host"; dr_mode = "host";
}; };
fman@400000 {
ethernet@e0000 {
phy-handle = <&phy_sgmii_2>;
phy-connection-type = "sgmii";
};
mdio@e1120 {
phy_rgmii_0: ethernet-phy@0 {
reg = <0x0>;
};
phy_rgmii_1: ethernet-phy@1 {
reg = <0x1>;
};
phy_sgmii_2: ethernet-phy@2 {
reg = <0x2>;
};
phy_sgmii_3: ethernet-phy@3 {
reg = <0x3>;
};
phy_sgmii_4: ethernet-phy@4 {
reg = <0x4>;
};
phy_sgmii_1c: ethernet-phy@1c {
reg = <0x1c>;
};
phy_sgmii_1d: ethernet-phy@1d {
reg = <0x1d>;
};
phy_sgmii_1e: ethernet-phy@1e {
reg = <0x1e>;
};
phy_sgmii_1f: ethernet-phy@1f {
reg = <0x1f>;
};
};
ethernet@e2000 {
phy-handle = <&phy_sgmii_3>;
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-handle = <&phy_sgmii_4>;
phy-connection-type = "sgmii";
};
ethernet@e6000 {
phy-handle = <&phy_rgmii_1>;
phy-connection-type = "rgmii";
};
ethernet@e8000 {
phy-handle = <&phy_rgmii_0>;
phy-connection-type = "rgmii";
};
ethernet@f0000 {
phy-handle = <&phy_xgmii_2>;
phy-connection-type = "xgmii";
};
mdio@f1000 {
phy_xgmii_2: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x0>;
};
};
};
}; };
rio: rapidio@ffe0c0000 { rio: rapidio@ffe0c0000 {
......
arch/powerpc/boot/dts/fsl/p3041ds.dts
浏览文件 @ a1b53446
/* /*
* P3041DS Device Tree Source * P3041DS Device Tree Source
* *
* Copyright 2010 - 2014 Freescale Semiconductor Inc. * Copyright 2010 - 2015 Freescale Semiconductor Inc.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -41,6 +41,20 @@ ...@@ -41,6 +41,20 @@
#size-cells = <2>; #size-cells = <2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
aliases{
phy_rgmii_0 = &phy_rgmii_0;
phy_rgmii_1 = &phy_rgmii_1;
phy_sgmii_1c = &phy_sgmii_1c;
phy_sgmii_1d = &phy_sgmii_1d;
phy_sgmii_1e = &phy_sgmii_1e;
phy_sgmii_1f = &phy_sgmii_1f;
phy_xgmii_1 = &phy_xgmii_1;
phy_xgmii_2 = &phy_xgmii_2;
emi1_rgmii = &hydra_mdio_rgmii;
emi1_sgmii = &hydra_mdio_sgmii;
emi2_xgmii = &hydra_mdio_xgmii;
};
memory { memory {
device_type = "memory"; device_type = "memory";
}; };
...@@ -83,7 +97,7 @@ ...@@ -83,7 +97,7 @@
flash@0 { flash@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "spansion,s25sl12801"; compatible = "spansion,s25sl12801", "jedec,spi-nor";
reg = <0>; reg = <0>;
spi-max-frequency = <35000000>; /* input clock */ spi-max-frequency = <35000000>; /* input clock */
partition@u-boot { partition@u-boot {
...@@ -150,6 +164,52 @@ ...@@ -150,6 +164,52 @@
reg = <0x4c>; reg = <0x4c>;
}; };
}; };
fman@400000{
ethernet@e0000 {
phy-handle = <&phy_sgmii_1c>;
phy-connection-type = "sgmii";
};
ethernet@e2000 {
phy-handle = <&phy_sgmii_1d>;
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-handle = <&phy_sgmii_1e>;
phy-connection-type = "sgmii";
};
ethernet@e6000 {
phy-handle = <&phy_sgmii_1f>;
phy-connection-type = "sgmii";
};
ethernet@e8000 {
phy-handle = <&phy_rgmii_1>;
phy-connection-type = "rgmii";
};
ethernet@f0000 {
phy-handle = <&phy_xgmii_1>;
phy-connection-type = "xgmii";
};
hydra_mdio_xgmii: mdio@f1000 {
status = "disabled";
phy_xgmii_1: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x4>;
};
phy_xgmii_2: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x0>;
};
};
};
}; };
rio: rapidio@ffe0c0000 { rio: rapidio@ffe0c0000 {
...@@ -215,8 +275,58 @@ ...@@ -215,8 +275,58 @@
}; };
board-control@3,0 { board-control@3,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,p3041ds-fpga", "fsl,fpga-ngpixis"; compatible = "fsl,p3041ds-fpga", "fsl,fpga-ngpixis";
reg = <3 0 0x30>; reg = <3 0 0x30>;
ranges = <0 3 0 0x30>;
mdio-mux-emi1 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mdio-mux-mmioreg", "mdio-mux";
mdio-parent-bus = <&mdio0>;
reg = <9 1>;
mux-mask = <0x78>;
hydra_mdio_rgmii: rgmii-mdio@8 {
#address-cells = <1>;
#size-cells = <0>;
reg = <8>;
status = "disabled";
phy_rgmii_0: ethernet-phy@0 {
reg = <0x0>;
};
phy_rgmii_1: ethernet-phy@1 {
reg = <0x1>;
};
};
hydra_mdio_sgmii: sgmii-mdio@28 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x28>;
status = "disabled";
phy_sgmii_1c: ethernet-phy@1c {
reg = <0x1c>;
};
phy_sgmii_1d: ethernet-phy@1d {
reg = <0x1d>;
};
phy_sgmii_1e: ethernet-phy@1e {
reg = <0x1e>;
};
phy_sgmii_1f: ethernet-phy@1f {
reg = <0x1f>;
};
};
};
}; };
}; };
......
arch/powerpc/boot/dts/fsl/p4080ds.dts
浏览文件 @ a1b53446
/* /*
* P4080DS Device Tree Source * P4080DS Device Tree Source
* *
* Copyright 2009 - 2014 Freescale Semiconductor Inc. * Copyright 2009 - 2015 Freescale Semiconductor Inc.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -41,6 +41,20 @@ ...@@ -41,6 +41,20 @@
#size-cells = <2>; #size-cells = <2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
aliases {
phy_rgmii = &phyrgmii;
phy5_slot3 = &phy5slot3;
phy6_slot3 = &phy6slot3;
phy7_slot3 = &phy7slot3;
phy8_slot3 = &phy8slot3;
emi1_slot3 = &p4080mdio2;
emi1_slot4 = &p4080mdio1;
emi1_slot5 = &p4080mdio3;
emi1_rgmii = &p4080mdio0;
emi2_slot4 = &p4080xmdio1;
emi2_slot5 = &p4080xmdio3;
};
memory { memory {
device_type = "memory"; device_type = "memory";
}; };
...@@ -84,7 +98,7 @@ ...@@ -84,7 +98,7 @@
flash@0 { flash@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "spansion,s25sl12801"; compatible = "spansion,s25sl12801", "jedec,spi-nor";
reg = <0>; reg = <0>;
spi-max-frequency = <40000000>; /* input clock */ spi-max-frequency = <40000000>; /* input clock */
partition@u-boot { partition@u-boot {
...@@ -137,6 +151,60 @@ ...@@ -137,6 +151,60 @@
dr_mode = "host"; dr_mode = "host";
phy_type = "ulpi"; phy_type = "ulpi";
}; };
fman@400000 {
ethernet@e0000 {
phy-handle = <&phy0>;
phy-connection-type = "sgmii";
};
ethernet@e2000 {
phy-handle = <&phy1>;
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-handle = <&phy2>;
phy-connection-type = "sgmii";
};
ethernet@e6000 {
phy-handle = <&phy3>;
phy-connection-type = "sgmii";
};
ethernet@f0000 {
phy-handle = <&phy10>;
phy-connection-type = "xgmii";
};
};
fman@500000 {
ethernet@e0000 {
phy-handle = <&phy5>;
phy-connection-type = "sgmii";
};
ethernet@e2000 {
phy-handle = <&phy6>;
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-handle = <&phy7>;
phy-connection-type = "sgmii";
};
ethernet@e6000 {
phy-handle = <&phy8>;
phy-connection-type = "sgmii";
};
ethernet@f0000 {
phy-handle = <&phy11>;
phy-connection-type = "xgmii";
};
};
}; };
rio: rapidio@ffe0c0000 { rio: rapidio@ffe0c0000 {
...@@ -213,6 +281,120 @@ ...@@ -213,6 +281,120 @@
}; };
}; };
mdio-mux-emi1 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mdio-mux-gpio", "mdio-mux";
mdio-parent-bus = <&mdio0>;
gpios = <&gpio0 1 0>, <&gpio0 0 0>;
p4080mdio0: mdio@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
phyrgmii: ethernet-phy@0 {
reg = <0x0>;
};
};
p4080mdio1: mdio@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
phy5: ethernet-phy@1c {
reg = <0x1c>;
};
phy6: ethernet-phy@1d {
reg = <0x1d>;
};
phy7: ethernet-phy@1e {
reg = <0x1e>;
};
phy8: ethernet-phy@1f {
reg = <0x1f>;
};
};
p4080mdio2: mdio@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
status = "disabled";
phy5slot3: ethernet-phy@1c {
reg = <0x1c>;
};
phy6slot3: ethernet-phy@1d {
reg = <0x1d>;
};
phy7slot3: ethernet-phy@1e {
reg = <0x1e>;
};
phy8slot3: ethernet-phy@1f {
reg = <0x1f>;
};
};
p4080mdio3: mdio@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
phy0: ethernet-phy@1c {
reg = <0x1c>;
};
phy1: ethernet-phy@1d {
reg = <0x1d>;
};
phy2: ethernet-phy@1e {
reg = <0x1e>;
};
phy3: ethernet-phy@1f {
reg = <0x1f>;
};
};
};
mdio-mux-emi2 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mdio-mux-gpio", "mdio-mux";
mdio-parent-bus = <&xmdio0>;
gpios = <&gpio0 3 0>, <&gpio0 2 0>;
p4080xmdio1: mdio@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
phy11: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x0>;
};
};
p4080xmdio3: mdio@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
phy10: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x4>;
};
};
};
}; };
/include/ "p4080si-post.dtsi" /include/ "p4080si-post.dtsi"
arch/powerpc/boot/dts/fsl/p5020ds.dts
浏览文件 @ a1b53446
/* /*
* P5020DS Device Tree Source * P5020DS Device Tree Source
* *
* Copyright 2010 - 2014 Freescale Semiconductor Inc. * Copyright 2010 - 2015 Freescale Semiconductor Inc.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -41,6 +41,20 @@ ...@@ -41,6 +41,20 @@
#size-cells = <2>; #size-cells = <2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
aliases {
phy_rgmii_0 = &phy_rgmii_0;
phy_rgmii_1 = &phy_rgmii_1;
phy_sgmii_1c = &phy_sgmii_1c;
phy_sgmii_1d = &phy_sgmii_1d;
phy_sgmii_1e = &phy_sgmii_1e;
phy_sgmii_1f = &phy_sgmii_1f;
phy_xgmii_1 = &phy_xgmii_1;
phy_xgmii_2 = &phy_xgmii_2;
emi1_rgmii = &hydra_mdio_rgmii;
emi1_sgmii = &hydra_mdio_sgmii;
emi2_xgmii = &hydra_mdio_xgmii;
};
memory { memory {
device_type = "memory"; device_type = "memory";
}; };
...@@ -83,7 +97,7 @@ ...@@ -83,7 +97,7 @@
flash@0 { flash@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "spansion,s25sl12801"; compatible = "spansion,s25sl12801", "jedec,spi-nor";
reg = <0>; reg = <0>;
spi-max-frequency = <40000000>; /* input clock */ spi-max-frequency = <40000000>; /* input clock */
partition@u-boot { partition@u-boot {
...@@ -150,6 +164,52 @@ ...@@ -150,6 +164,52 @@
reg = <0x4c>; reg = <0x4c>;
}; };
}; };
fman@400000 {
ethernet@e0000 {
phy-handle = <&phy_sgmii_1c>;
phy-connection-type = "sgmii";
};
ethernet@e2000 {
phy-handle = <&phy_sgmii_1d>;
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-handle = <&phy_sgmii_1e>;
phy-connection-type = "sgmii";
};
ethernet@e6000 {
phy-handle = <&phy_sgmii_1f>;
phy-connection-type = "sgmii";
};
ethernet@e8000 {
phy-handle = <&phy_rgmii_1>;
phy-connection-type = "rgmii";
};
ethernet@f0000 {
phy-handle = <&phy_xgmii_1>;
phy-connection-type = "xgmii";
};
hydra_mdio_xgmii: mdio@f1000 {
status = "disabled";
phy_xgmii_1: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x4>;
};
phy_xgmii_2: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x0>;
};
};
};
}; };
rio: rapidio@ffe0c0000 { rio: rapidio@ffe0c0000 {
...@@ -215,8 +275,58 @@ ...@@ -215,8 +275,58 @@
}; };
board-control@3,0 { board-control@3,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,p5020ds-fpga", "fsl,fpga-ngpixis"; compatible = "fsl,p5020ds-fpga", "fsl,fpga-ngpixis";
reg = <3 0 0x30>; reg = <3 0 0x30>;
ranges = <0 3 0 0x30>;
mdio-mux-emi1 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mdio-mux-mmioreg", "mdio-mux";
mdio-parent-bus = <&mdio0>;
reg = <9 1>;
mux-mask = <0x78>;
hydra_mdio_rgmii: rgmii-mdio@8 {
#address-cells = <1>;
#size-cells = <0>;
reg = <8>;
status = "disabled";
phy_rgmii_0: ethernet-phy@0 {
reg = <0x0>;
};
phy_rgmii_1: ethernet-phy@1 {
reg = <0x1>;
};
};
hydra_mdio_sgmii: sgmii-mdio@28 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x28>;
status = "disabled";
phy_sgmii_1c: ethernet-phy@1c {
reg = <0x1c>;
};
phy_sgmii_1d: ethernet-phy@1d {
reg = <0x1d>;
};
phy_sgmii_1e: ethernet-phy@1e {
reg = <0x1e>;
};
phy_sgmii_1f: ethernet-phy@1f {
reg = <0x1f>;
};
};
};
}; };
}; };
......
arch/powerpc/boot/dts/fsl/p5040ds.dts
浏览文件 @ a1b53446
/* /*
* P5040DS Device Tree Source * P5040DS Device Tree Source
* *
* Copyright 2012 - 2014 Freescale Semiconductor Inc. * Copyright 2012 - 2015 Freescale Semiconductor Inc.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -41,6 +41,32 @@ ...@@ -41,6 +41,32 @@
#size-cells = <2>; #size-cells = <2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
aliases{
phy_sgmii_slot2_1c = &phy_sgmii_slot2_1c;
phy_sgmii_slot2_1d = &phy_sgmii_slot2_1d;
phy_sgmii_slot2_1e = &phy_sgmii_slot2_1e;
phy_sgmii_slot2_1f = &phy_sgmii_slot2_1f;
phy_sgmii_slot3_1c = &phy_sgmii_slot3_1c;
phy_sgmii_slot3_1d = &phy_sgmii_slot3_1d;
phy_sgmii_slot3_1e = &phy_sgmii_slot3_1e;
phy_sgmii_slot3_1f = &phy_sgmii_slot3_1f;
phy_sgmii_slot5_1c = &phy_sgmii_slot5_1c;
phy_sgmii_slot5_1d = &phy_sgmii_slot5_1d;
phy_sgmii_slot5_1e = &phy_sgmii_slot5_1e;
phy_sgmii_slot5_1f = &phy_sgmii_slot5_1f;
phy_sgmii_slot6_1c = &phy_sgmii_slot6_1c;
phy_sgmii_slot6_1d = &phy_sgmii_slot6_1d;
phy_sgmii_slot6_1e = &phy_sgmii_slot6_1e;
phy_sgmii_slot6_1f = &phy_sgmii_slot6_1f;
hydra_rg = &hydra_rg;
hydra_sg_slot2 = &hydra_sg_slot2;
hydra_sg_slot3 = &hydra_sg_slot3;
hydra_sg_slot5 = &hydra_sg_slot5;
hydra_sg_slot6 = &hydra_sg_slot6;
hydra_xg_slot1 = &hydra_xg_slot1;
hydra_xg_slot2 = &hydra_xg_slot2;
};
memory { memory {
device_type = "memory"; device_type = "memory";
}; };
...@@ -83,7 +109,7 @@ ...@@ -83,7 +109,7 @@
flash@0 { flash@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "spansion,s25sl12801"; compatible = "spansion,s25sl12801", "jedec,spi-nor";
reg = <0>; reg = <0>;
spi-max-frequency = <40000000>; /* input clock */ spi-max-frequency = <40000000>; /* input clock */
partition@u-boot { partition@u-boot {
...@@ -147,6 +173,62 @@ ...@@ -147,6 +173,62 @@
reg = <0x4c>; reg = <0x4c>;
}; };
}; };
fman@400000 {
ethernet@e0000 {
phy-connection-type = "sgmii";
};
ethernet@e2000 {
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-connection-type = "sgmii";
};
ethernet@e6000 {
phy-connection-type = "sgmii";
};
ethernet@e8000 {
phy-handle = <&phy_rgmii_0>;
phy-connection-type = "rgmii";
};
ethernet@f0000 {
phy-handle = <&phy_xgmii_slot_2>;
phy-connection-type = "xgmii";
};
};
fman@500000 {
ethernet@e0000 {
phy-connection-type = "sgmii";
};
ethernet@e2000 {
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-connection-type = "sgmii";
};
ethernet@e6000 {
phy-connection-type = "sgmii";
};
ethernet@e8000 {
phy-handle = <&phy_rgmii_1>;
phy-connection-type = "rgmii";
};
ethernet@f0000 {
phy-handle = <&phy_xgmii_slot_1>;
phy-connection-type = "xgmii";
};
};
}; };
lbc: localbus@ffe124000 { lbc: localbus@ffe124000 {
...@@ -200,8 +282,158 @@ ...@@ -200,8 +282,158 @@
}; };
board-control@3,0 { board-control@3,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,p5040ds-fpga", "fsl,fpga-ngpixis"; compatible = "fsl,p5040ds-fpga", "fsl,fpga-ngpixis";
reg = <3 0 0x40>; reg = <3 0 0x40>;
ranges = <0 3 0 0x40>;
mdio-mux-emi1 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mdio-mux-mmioreg", "mdio-mux";
mdio-parent-bus = <&mdio0>;
reg = <9 1>;
mux-mask = <0x78>;
hydra_rg:rgmii-mdio@8 {
#address-cells = <1>;
#size-cells = <0>;
reg = <8>;
status = "disabled";
phy_rgmii_0: ethernet-phy@0 {
reg = <0x0>;
};
phy_rgmii_1: ethernet-phy@1 {
reg = <0x1>;
};
};
hydra_sg_slot2: sgmii-mdio@28 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x28>;
status = "disabled";
phy_sgmii_slot2_1c: ethernet-phy@1c {
reg = <0x1c>;
};
phy_sgmii_slot2_1d: ethernet-phy@1d {
reg = <0x1d>;
};
phy_sgmii_slot2_1e: ethernet-phy@1e {
reg = <0x1e>;
};
phy_sgmii_slot2_1f: ethernet-phy@1f {
reg = <0x1f>;
};
};
hydra_sg_slot3: sgmii-mdio@68 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x68>;
status = "disabled";
phy_sgmii_slot3_1c: ethernet-phy@1c {
reg = <0x1c>;
};
phy_sgmii_slot3_1d: ethernet-phy@1d {
reg = <0x1d>;
};
phy_sgmii_slot3_1e: ethernet-phy@1e {
reg = <0x1e>;
};
phy_sgmii_slot3_1f: ethernet-phy@1f {
reg = <0x1f>;
};
};
hydra_sg_slot5: sgmii-mdio@38 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x38>;
status = "disabled";
phy_sgmii_slot5_1c: ethernet-phy@1c {
reg = <0x1c>;
};
phy_sgmii_slot5_1d: ethernet-phy@1d {
reg = <0x1d>;
};
phy_sgmii_slot5_1e: ethernet-phy@1e {
reg = <0x1e>;
};
phy_sgmii_slot5_1f: ethernet-phy@1f {
reg = <0x1f>;
};
};
hydra_sg_slot6: sgmii-mdio@48 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x48>;
status = "disabled";
phy_sgmii_slot6_1c: ethernet-phy@1c {
reg = <0x1c>;
};
phy_sgmii_slot6_1d: ethernet-phy@1d {
reg = <0x1d>;
};
phy_sgmii_slot6_1e: ethernet-phy@1e {
reg = <0x1e>;
};
phy_sgmii_slot6_1f: ethernet-phy@1f {
reg = <0x1f>;
};
};
};
mdio-mux-emi2 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mdio-mux-mmioreg", "mdio-mux";
mdio-parent-bus = <&xmdio0>;
reg = <9 1>;
mux-mask = <0x06>;
hydra_xg_slot1: hydra-xg-slot1@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
status = "disabled";
phy_xgmii_slot_1: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <4>;
};
};
hydra_xg_slot2: hydra-xg-slot2@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
phy_xgmii_slot_2: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0>;
};
};
};
}; };
}; };
......
arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
浏览文件 @ a1b53446
...@@ -420,6 +420,7 @@ ...@@ -420,6 +420,7 @@
fsl,iommu-parent = <&pamu4>; fsl,iommu-parent = <&pamu4>;
}; };
/include/ "qoriq-raid1.0-0.dtsi"
/include/ "qoriq-qman1.dtsi" /include/ "qoriq-qman1.dtsi"
/include/ "qoriq-bman1.dtsi" /include/ "qoriq-bman1.dtsi"
......
arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
浏览文件 @ a1b53446
...@@ -73,6 +73,12 @@ ...@@ -73,6 +73,12 @@
rtic_d = &rtic_d; rtic_d = &rtic_d;
sec_mon = &sec_mon; sec_mon = &sec_mon;
raideng = &raideng;
raideng_jr0 = &raideng_jr0;
raideng_jr1 = &raideng_jr1;
raideng_jr2 = &raideng_jr2;
raideng_jr3 = &raideng_jr3;
fman0 = &fman0; fman0 = &fman0;
fman1 = &fman1; fman1 = &fman1;
ethernet0 = &enet0; ethernet0 = &enet0;
......
arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0-best-effort.dtsi
浏览文件 @ a1b53446
...@@ -55,6 +55,7 @@ fman@400000 { ...@@ -55,6 +55,7 @@ fman@400000 {
reg = <0xe0000 0x1000>; reg = <0xe0000 0x1000>;
fsl,fman-ports = <&fman0_rx_0x08 &fman0_tx_0x28>; fsl,fman-ports = <&fman0_rx_0x08 &fman0_tx_0x28>;
ptp-timer = <&ptp_timer0>; ptp-timer = <&ptp_timer0>;
pcsphy-handle = <&pcsphy0>;
}; };
mdio@e1000 { mdio@e1000 {
...@@ -62,5 +63,9 @@ fman@400000 { ...@@ -62,5 +63,9 @@ fman@400000 {
#size-cells = <0>; #size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xe1000 0x1000>; reg = <0xe1000 0x1000>;
pcsphy0: ethernet-phy@0 {
reg = <0x0>;
};
}; };
}; };
arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi
浏览文件 @ a1b53446
...@@ -52,6 +52,7 @@ fman@400000 { ...@@ -52,6 +52,7 @@ fman@400000 {
compatible = "fsl,fman-memac"; compatible = "fsl,fman-memac";
reg = <0xf0000 0x1000>; reg = <0xf0000 0x1000>;
fsl,fman-ports = <&fman0_rx_0x10 &fman0_tx_0x30>; fsl,fman-ports = <&fman0_rx_0x10 &fman0_tx_0x30>;
pcsphy-handle = <&pcsphy6>;
}; };
mdio@f1000 { mdio@f1000 {
...@@ -59,5 +60,9 @@ fman@400000 { ...@@ -59,5 +60,9 @@ fman@400000 {
#size-cells = <0>; #size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xf1000 0x1000>; reg = <0xf1000 0x1000>;
pcsphy6: ethernet-phy@0 {
reg = <0x0>;
};
}; };
}; };
arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1-best-effort.dtsi
浏览文件 @ a1b53446
...@@ -55,6 +55,7 @@ fman@400000 { ...@@ -55,6 +55,7 @@ fman@400000 {
reg = <0xe2000 0x1000>; reg = <0xe2000 0x1000>;
fsl,fman-ports = <&fman0_rx_0x09 &fman0_tx_0x29>; fsl,fman-ports = <&fman0_rx_0x09 &fman0_tx_0x29>;
ptp-timer = <&ptp_timer0>; ptp-timer = <&ptp_timer0>;
pcsphy-handle = <&pcsphy1>;
}; };
mdio@e3000 { mdio@e3000 {
...@@ -62,5 +63,9 @@ fman@400000 { ...@@ -62,5 +63,9 @@ fman@400000 {
#size-cells = <0>; #size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xe3000 0x1000>; reg = <0xe3000 0x1000>;
pcsphy1: ethernet-phy@0 {
reg = <0x0>;
};
}; };
}; };
arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi
浏览文件 @ a1b53446
...@@ -52,6 +52,7 @@ fman@400000 { ...@@ -52,6 +52,7 @@ fman@400000 {
compatible = "fsl,fman-memac"; compatible = "fsl,fman-memac";
reg = <0xf2000 0x1000>; reg = <0xf2000 0x1000>;
fsl,fman-ports = <&fman0_rx_0x11 &fman0_tx_0x31>; fsl,fman-ports = <&fman0_rx_0x11 &fman0_tx_0x31>;
pcsphy-handle = <&pcsphy7>;
}; };
mdio@f3000 { mdio@f3000 {
...@@ -59,5 +60,9 @@ fman@400000 { ...@@ -59,5 +60,9 @@ fman@400000 {
#size-cells = <0>; #size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xf3000 0x1000>; reg = <0xf3000 0x1000>;
pcsphy7: ethernet-phy@0 {
reg = <0x0>;
};
}; };
}; };
arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-0.dtsi
浏览文件 @ a1b53446
...@@ -51,6 +51,7 @@ fman@400000 { ...@@ -51,6 +51,7 @@ fman@400000 {
reg = <0xe0000 0x1000>; reg = <0xe0000 0x1000>;
fsl,fman-ports = <&fman0_rx_0x08 &fman0_tx_0x28>; fsl,fman-ports = <&fman0_rx_0x08 &fman0_tx_0x28>;
ptp-timer = <&ptp_timer0>; ptp-timer = <&ptp_timer0>;
pcsphy-handle = <&pcsphy0>;
}; };
mdio@e1000 { mdio@e1000 {
...@@ -58,5 +59,9 @@ fman@400000 { ...@@ -58,5 +59,9 @@ fman@400000 {
#size-cells = <0>; #size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xe1000 0x1000>; reg = <0xe1000 0x1000>;
pcsphy0: ethernet-phy@0 {
reg = <0x0>;
};
}; };
}; };
arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-1.dtsi
浏览文件 @ a1b53446
...@@ -51,6 +51,7 @@ fman@400000 { ...@@ -51,6 +51,7 @@ fman@400000 {
reg = <0xe2000 0x1000>; reg = <0xe2000 0x1000>;
fsl,fman-ports = <&fman0_rx_0x09 &fman0_tx_0x29>; fsl,fman-ports = <&fman0_rx_0x09 &fman0_tx_0x29>;
ptp-timer = <&ptp_timer0>; ptp-timer = <&ptp_timer0>;
pcsphy-handle = <&pcsphy1>;
}; };
mdio@e3000 { mdio@e3000 {
...@@ -58,5 +59,9 @@ fman@400000 { ...@@ -58,5 +59,9 @@ fman@400000 {
#size-cells = <0>; #size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xe3000 0x1000>; reg = <0xe3000 0x1000>;
pcsphy1: ethernet-phy@0 {
reg = <0x0>;
};
}; };
}; };
arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-2.dtsi
浏览文件 @ a1b53446
...@@ -51,6 +51,7 @@ fman@400000 { ...@@ -51,6 +51,7 @@ fman@400000 {
reg = <0xe4000 0x1000>; reg = <0xe4000 0x1000>;
fsl,fman-ports = <&fman0_rx_0x0a &fman0_tx_0x2a>; fsl,fman-ports = <&fman0_rx_0x0a &fman0_tx_0x2a>;
ptp-timer = <&ptp_timer0>; ptp-timer = <&ptp_timer0>;
pcsphy-handle = <&pcsphy2>;
}; };
mdio@e5000 { mdio@e5000 {
...@@ -58,5 +59,9 @@ fman@400000 { ...@@ -58,5 +59,9 @@ fman@400000 {
#size-cells = <0>; #size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xe5000 0x1000>; reg = <0xe5000 0x1000>;
pcsphy2: ethernet-phy@0 {
reg = <0x0>;
};
}; };
}; };
arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-3.dtsi
浏览文件 @ a1b53446
...@@ -51,6 +51,7 @@ fman@400000 { ...@@ -51,6 +51,7 @@ fman@400000 {
reg = <0xe6000 0x1000>; reg = <0xe6000 0x1000>;
fsl,fman-ports = <&fman0_rx_0x0b &fman0_tx_0x2b>; fsl,fman-ports = <&fman0_rx_0x0b &fman0_tx_0x2b>;
ptp-timer = <&ptp_timer0>; ptp-timer = <&ptp_timer0>;
pcsphy-handle = <&pcsphy3>;
}; };
mdio@e7000 { mdio@e7000 {
...@@ -58,5 +59,9 @@ fman@400000 { ...@@ -58,5 +59,9 @@ fman@400000 {
#size-cells = <0>; #size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xe7000 0x1000>; reg = <0xe7000 0x1000>;
pcsphy3: ethernet-phy@0 {
reg = <0x0>;
};
}; };
}; };
arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-4.dtsi
浏览文件 @ a1b53446
...@@ -51,6 +51,7 @@ fman@400000 { ...@@ -51,6 +51,7 @@ fman@400000 {
reg = <0xe8000 0x1000>; reg = <0xe8000 0x1000>;
fsl,fman-ports = <&fman0_rx_0x0c &fman0_tx_0x2c>; fsl,fman-ports = <&fman0_rx_0x0c &fman0_tx_0x2c>;
ptp-timer = <&ptp_timer0>; ptp-timer = <&ptp_timer0>;
pcsphy-handle = <&pcsphy4>;
}; };
mdio@e9000 { mdio@e9000 {
...@@ -58,5 +59,9 @@ fman@400000 { ...@@ -58,5 +59,9 @@ fman@400000 {
#size-cells = <0>; #size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xe9000 0x1000>; reg = <0xe9000 0x1000>;
pcsphy4: ethernet-phy@0 {
reg = <0x0>;
};
}; };
}; };
arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-5.dtsi
浏览文件 @ a1b53446
...@@ -51,6 +51,7 @@ fman@400000 { ...@@ -51,6 +51,7 @@ fman@400000 {
reg = <0xea000 0x1000>; reg = <0xea000 0x1000>;
fsl,fman-ports = <&fman0_rx_0x0d &fman0_tx_0x2d>; fsl,fman-ports = <&fman0_rx_0x0d &fman0_tx_0x2d>;
ptp-timer = <&ptp_timer0>; ptp-timer = <&ptp_timer0>;
pcsphy-handle = <&pcsphy5>;
}; };
mdio@eb000 { mdio@eb000 {
...@@ -58,5 +59,9 @@ fman@400000 { ...@@ -58,5 +59,9 @@ fman@400000 {
#size-cells = <0>; #size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xeb000 0x1000>; reg = <0xeb000 0x1000>;
pcsphy5: ethernet-phy@0 {
reg = <0x0>;
};
}; };
}; };
arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-0.dtsi
浏览文件 @ a1b53446
...@@ -52,6 +52,7 @@ fman@500000 { ...@@ -52,6 +52,7 @@ fman@500000 {
compatible = "fsl,fman-memac"; compatible = "fsl,fman-memac";
reg = <0xf0000 0x1000>; reg = <0xf0000 0x1000>;
fsl,fman-ports = <&fman1_rx_0x10 &fman1_tx_0x30>; fsl,fman-ports = <&fman1_rx_0x10 &fman1_tx_0x30>;
pcsphy-handle = <&pcsphy14>;
}; };
mdio@f1000 { mdio@f1000 {
...@@ -59,5 +60,9 @@ fman@500000 { ...@@ -59,5 +60,9 @@ fman@500000 {
#size-cells = <0>; #size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xf1000 0x1000>; reg = <0xf1000 0x1000>;
pcsphy14: ethernet-phy@0 {
reg = <0x0>;
};
}; };
}; };
arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-1.dtsi
浏览文件 @ a1b53446
...@@ -52,6 +52,7 @@ fman@500000 { ...@@ -52,6 +52,7 @@ fman@500000 {
compatible = "fsl,fman-memac"; compatible = "fsl,fman-memac";
reg = <0xf2000 0x1000>; reg = <0xf2000 0x1000>;
fsl,fman-ports = <&fman1_rx_0x11 &fman1_tx_0x31>; fsl,fman-ports = <&fman1_rx_0x11 &fman1_tx_0x31>;
pcsphy-handle = <&pcsphy15>;
}; };
mdio@f3000 { mdio@f3000 {
...@@ -59,5 +60,9 @@ fman@500000 { ...@@ -59,5 +60,9 @@ fman@500000 {
#size-cells = <0>; #size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xf3000 0x1000>; reg = <0xf3000 0x1000>;
pcsphy15: ethernet-phy@0 {
reg = <0x0>;
};
}; };
}; };
arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-0.dtsi
浏览文件 @ a1b53446
...@@ -51,6 +51,7 @@ fman@500000 { ...@@ -51,6 +51,7 @@ fman@500000 {
reg = <0xe0000 0x1000>; reg = <0xe0000 0x1000>;
fsl,fman-ports = <&fman1_rx_0x08 &fman1_tx_0x28>; fsl,fman-ports = <&fman1_rx_0x08 &fman1_tx_0x28>;
ptp-timer = <&ptp_timer1>; ptp-timer = <&ptp_timer1>;
pcsphy-handle = <&pcsphy8>;
}; };
mdio@e1000 { mdio@e1000 {
...@@ -58,5 +59,9 @@ fman@500000 { ...@@ -58,5 +59,9 @@ fman@500000 {
#size-cells = <0>; #size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xe1000 0x1000>; reg = <0xe1000 0x1000>;
pcsphy8: ethernet-phy@0 {
reg = <0x0>;
};
}; };
}; };
arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-1.dtsi
浏览文件 @ a1b53446
...@@ -51,6 +51,7 @@ fman@500000 { ...@@ -51,6 +51,7 @@ fman@500000 {
reg = <0xe2000 0x1000>; reg = <0xe2000 0x1000>;
fsl,fman-ports = <&fman1_rx_0x09 &fman1_tx_0x29>; fsl,fman-ports = <&fman1_rx_0x09 &fman1_tx_0x29>;
ptp-timer = <&ptp_timer1>; ptp-timer = <&ptp_timer1>;
pcsphy-handle = <&pcsphy9>;
}; };
mdio@e3000 { mdio@e3000 {
...@@ -58,5 +59,9 @@ fman@500000 { ...@@ -58,5 +59,9 @@ fman@500000 {
#size-cells = <0>; #size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xe3000 0x1000>; reg = <0xe3000 0x1000>;
pcsphy9: ethernet-phy@0 {
reg = <0x0>;
};
}; };
}; };
arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-2.dtsi
浏览文件 @ a1b53446
...@@ -51,6 +51,7 @@ fman@500000 { ...@@ -51,6 +51,7 @@ fman@500000 {
reg = <0xe4000 0x1000>; reg = <0xe4000 0x1000>;
fsl,fman-ports = <&fman1_rx_0x0a &fman1_tx_0x2a>; fsl,fman-ports = <&fman1_rx_0x0a &fman1_tx_0x2a>;
ptp-timer = <&ptp_timer1>; ptp-timer = <&ptp_timer1>;
pcsphy-handle = <&pcsphy10>;
}; };
mdio@e5000 { mdio@e5000 {
...@@ -58,5 +59,9 @@ fman@500000 { ...@@ -58,5 +59,9 @@ fman@500000 {
#size-cells = <0>; #size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xe5000 0x1000>; reg = <0xe5000 0x1000>;
pcsphy10: ethernet-phy@0 {
reg = <0x0>;
};
}; };
}; };
arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-3.dtsi
浏览文件 @ a1b53446
...@@ -51,6 +51,7 @@ fman@500000 { ...@@ -51,6 +51,7 @@ fman@500000 {
reg = <0xe6000 0x1000>; reg = <0xe6000 0x1000>;
fsl,fman-ports = <&fman1_rx_0x0b &fman1_tx_0x2b>; fsl,fman-ports = <&fman1_rx_0x0b &fman1_tx_0x2b>;
ptp-timer = <&ptp_timer1>; ptp-timer = <&ptp_timer1>;
pcsphy-handle = <&pcsphy11>;
}; };
mdio@e7000 { mdio@e7000 {
...@@ -58,5 +59,9 @@ fman@500000 { ...@@ -58,5 +59,9 @@ fman@500000 {
#size-cells = <0>; #size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xe7000 0x1000>; reg = <0xe7000 0x1000>;
pcsphy11: ethernet-phy@0 {
reg = <0x0>;
};
}; };
}; };
arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-4.dtsi
浏览文件 @ a1b53446
...@@ -51,6 +51,7 @@ fman@500000 { ...@@ -51,6 +51,7 @@ fman@500000 {
reg = <0xe8000 0x1000>; reg = <0xe8000 0x1000>;
fsl,fman-ports = <&fman1_rx_0x0c &fman1_tx_0x2c>; fsl,fman-ports = <&fman1_rx_0x0c &fman1_tx_0x2c>;
ptp-timer = <&ptp_timer1>; ptp-timer = <&ptp_timer1>;
pcsphy-handle = <&pcsphy12>;
}; };
mdio@e9000 { mdio@e9000 {
...@@ -58,5 +59,9 @@ fman@500000 { ...@@ -58,5 +59,9 @@ fman@500000 {
#size-cells = <0>; #size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xe9000 0x1000>; reg = <0xe9000 0x1000>;
pcsphy12: ethernet-phy@0 {
reg = <0x0>;
};
}; };
}; };
arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-5.dtsi
浏览文件 @ a1b53446
...@@ -51,6 +51,7 @@ fman@500000 { ...@@ -51,6 +51,7 @@ fman@500000 {
reg = <0xea000 0x1000>; reg = <0xea000 0x1000>;
fsl,fman-ports = <&fman1_rx_0x0d &fman1_tx_0x2d>; fsl,fman-ports = <&fman1_rx_0x0d &fman1_tx_0x2d>;
ptp-timer = <&ptp_timer1>; ptp-timer = <&ptp_timer1>;
pcsphy-handle = <&pcsphy13>;
}; };
mdio@eb000 { mdio@eb000 {
...@@ -58,5 +59,9 @@ fman@500000 { ...@@ -58,5 +59,9 @@ fman@500000 {
#size-cells = <0>; #size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xeb000 0x1000>; reg = <0xeb000 0x1000>;
pcsphy13: ethernet-phy@0 {
reg = <0x0>;
};
}; };
}; };
arch/powerpc/boot/dts/sbc8641d.dts → arch/powerpc/boot/dts/fsl/sbc8641d.dts
浏览文件 @ a1b53446
...@@ -13,65 +13,23 @@ ...@@ -13,65 +13,23 @@
* option) any later version. * option) any later version.
*/ */
/dts-v1/; /include/ "mpc8641si-pre.dtsi"
/ { / {
model = "SBC8641D"; model = "SBC8641D";
compatible = "wind,sbc8641"; compatible = "wind,sbc8641";
#address-cells = <1>;
#size-cells = <1>;
aliases { aliases {
ethernet0 = &enet0;
ethernet1 = &enet1;
ethernet2 = &enet2;
ethernet3 = &enet3;
serial0 = &serial0;
serial1 = &serial1;
pci0 = &pci0;
pci1 = &pci1; pci1 = &pci1;
}; };
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8641@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <32>;
i-cache-line-size = <32>;
d-cache-size = <32768>; // L1
i-cache-size = <32768>; // L1
timebase-frequency = <0>; // From uboot
bus-frequency = <0>; // From uboot
clock-frequency = <0>; // From uboot
};
PowerPC,8641@1 {
device_type = "cpu";
reg = <1>;
d-cache-line-size = <32>;
i-cache-line-size = <32>;
d-cache-size = <32768>;
i-cache-size = <32768>;
timebase-frequency = <0>; // From uboot
bus-frequency = <0>; // From uboot
clock-frequency = <0>; // From uboot
};
};
memory { memory {
device_type = "memory"; device_type = "memory";
reg = <0x00000000 0x20000000>; // 512M at 0x0 reg = <0x00000000 0x20000000>; // 512M at 0x0
}; };
localbus@f8005000 { lbc: localbus@f8005000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,mpc8641-localbus", "simple-bus";
reg = <0xf8005000 0x1000>; reg = <0xf8005000 0x1000>;
interrupts = <19 2>;
interrupt-parent = <&mpic>;
ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
1 0 0xf0000000 0x00010000 // 64KB EEPROM 1 0 0xf0000000 0x00010000 // 64KB EEPROM
...@@ -120,283 +78,81 @@ ...@@ -120,283 +78,81 @@
}; };
}; };
soc@f8000000 { soc: soc@f8000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "simple-bus";
ranges = <0x00000000 0xf8000000 0x00100000>; ranges = <0x00000000 0xf8000000 0x00100000>;
bus-frequency = <0>;
mcm-law@0 {
compatible = "fsl,mcm-law";
reg = <0x0 0x1000>;
fsl,num-laws = <10>;
};
mcm@1000 {
compatible = "fsl,mpc8641-mcm", "fsl,mcm";
reg = <0x1000 0x1000>;
interrupts = <17 2>;
interrupt-parent = <&mpic>;
};
i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
i2c@3100 { enet0: ethernet@24000 {
#address-cells = <1>; tbi-handle = <&tbi0>;
#size-cells = <0>; phy-handle = <&phy0>;
cell-index = <1>; phy-connection-type = "rgmii-id";
compatible = "fsl-i2c";
reg = <0x3100 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
}; };
dma@21300 { mdio@24520 {
#address-cells = <1>; phy0: ethernet-phy@1f {
#size-cells = <1>; reg = <0x1f>;
compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
reg = <0x21300 0x4>;
ranges = <0x0 0x21100 0x200>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,mpc8641-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
interrupt-parent = <&mpic>;
interrupts = <20 2>;
}; };
dma-channel@80 { phy1: ethernet-phy@0 {
compatible = "fsl,mpc8641-dma-channel", reg = <0>;
"fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&mpic>;
interrupts = <21 2>;
}; };
dma-channel@100 { phy2: ethernet-phy@1 {
compatible = "fsl,mpc8641-dma-channel", reg = <1>;
"fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&mpic>;
interrupts = <22 2>;
}; };
dma-channel@180 { phy3: ethernet-phy@2 {
compatible = "fsl,mpc8641-dma-channel", reg = <2>;
"fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
interrupt-parent = <&mpic>;
interrupts = <23 2>;
}; };
}; tbi0: tbi-phy@11 {
reg = <0x11>;
enet0: ethernet@24000 { device_type = "tbi-phy";
#address-cells = <1>;
#size-cells = <1>;
cell-index = <0>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <0x24000 0x1000>;
ranges = <0x0 0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi0>;
phy-handle = <&phy0>;
phy-connection-type = "rgmii-id";
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <0x520 0x20>;
phy0: ethernet-phy@1f {
reg = <0x1f>;
};
phy1: ethernet-phy@0 {
reg = <0>;
};
phy2: ethernet-phy@1 {
reg = <1>;
};
phy3: ethernet-phy@2 {
reg = <2>;
};
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
}; };
}; };
enet1: ethernet@25000 { enet1: ethernet@25000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <1>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <0x25000 0x1000>;
ranges = <0x0 0x25000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <35 2 36 2 40 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi1>; tbi-handle = <&tbi1>;
phy-handle = <&phy1>; phy-handle = <&phy1>;
phy-connection-type = "rgmii-id"; phy-connection-type = "rgmii-id";
};
mdio@520 { mdio@25520 {
#address-cells = <1>; tbi1: tbi-phy@11 {
#size-cells = <0>; reg = <0x11>;
compatible = "fsl,gianfar-tbi"; device_type = "tbi-phy";
reg = <0x520 0x20>;
tbi1: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
}; };
}; };
enet2: ethernet@26000 { enet2: ethernet@26000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <2>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <0x26000 0x1000>;
ranges = <0x0 0x26000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <31 2 32 2 33 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi2>; tbi-handle = <&tbi2>;
phy-handle = <&phy2>; phy-handle = <&phy2>;
phy-connection-type = "rgmii-id"; phy-connection-type = "rgmii-id";
};
mdio@520 { mdio@26520 {
#address-cells = <1>; tbi2: tbi-phy@11 {
#size-cells = <0>; reg = <0x11>;
compatible = "fsl,gianfar-tbi"; device_type = "tbi-phy";
reg = <0x520 0x20>;
tbi2: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
}; };
}; };
enet3: ethernet@27000 { enet3: ethernet@27000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <3>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <0x27000 0x1000>;
ranges = <0x0 0x27000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <37 2 38 2 39 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi3>; tbi-handle = <&tbi3>;
phy-handle = <&phy3>; phy-handle = <&phy3>;
phy-connection-type = "rgmii-id"; phy-connection-type = "rgmii-id";
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x520 0x20>;
tbi3: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "fsl,ns16550", "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <0>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
serial1: serial@4600 {
cell-index = <1>;
device_type = "serial";
compatible = "fsl,ns16550", "ns16550";
reg = <0x4600 0x100>;
clock-frequency = <0>;
interrupts = <28 2>;
interrupt-parent = <&mpic>;
}; };
mpic: pic@40000 { mdio@27520 {
clock-frequency = <0>; tbi3: tbi-phy@11 {
interrupt-controller; reg = <0x11>;
#address-cells = <0>; device_type = "tbi-phy";
#interrupt-cells = <2>; };
reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
};
global-utilities@e0000 {
compatible = "fsl,mpc8641-guts";
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
}; };
}; };
pci0: pcie@f8008000 { pci0: pcie@f8008000 {
compatible = "fsl,mpc8641-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0xf8008000 0x1000>; reg = <0xf8008000 0x1000>;
bus-range = <0x0 0xff>;
ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>; 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <24 2>;
interrupt-map-mask = <0xff00 0 0 7>; interrupt-map-mask = <0xff00 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 */
0x0000 0 0 1 &mpic 0 1
0x0000 0 0 2 &mpic 1 1
0x0000 0 0 3 &mpic 2 1
0x0000 0 0 4 &mpic 3 1
>;
pcie@0 { pcie@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <0x02000000 0x0 0x80000000 ranges = <0x02000000 0x0 0x80000000
0x02000000 0x0 0x80000000 0x02000000 0x0 0x80000000
0x0 0x20000000 0x0 0x20000000
...@@ -411,16 +167,14 @@ ...@@ -411,16 +167,14 @@
pci1: pcie@f8009000 { pci1: pcie@f8009000 {
compatible = "fsl,mpc8641-pcie"; compatible = "fsl,mpc8641-pcie";
device_type = "pci"; device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
reg = <0xf8009000 0x1000>; reg = <0xf8009000 0x1000>;
bus-range = <0 0xff>; bus-range = <0 0xff>;
ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>; 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
clock-frequency = <33333333>; clock-frequency = <100000000>;
interrupt-parent = <&mpic>; interrupts = <25 2 0 0>;
interrupts = <25 2>;
interrupt-map-mask = <0xf800 0 0 7>; interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = < interrupt-map = <
/* IDSEL 0x0 */ /* IDSEL 0x0 */
...@@ -445,3 +199,5 @@ ...@@ -445,3 +199,5 @@
}; };
}; };
}; };
/include/ "mpc8641si-post.dtsi"
arch/powerpc/boot/dts/fsl/t1023rdb.dts
浏览文件 @ a1b53446
...@@ -79,7 +79,7 @@ ...@@ -79,7 +79,7 @@
flash@0 { flash@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "spansion,s25fl512s"; compatible = "spansion,s25fl512s", "jedec,spi-nor";
reg = <0>; reg = <0>;
spi-max-frequency = <10000000>; /* input clk */ spi-max-frequency = <10000000>; /* input clk */
}; };
...@@ -111,6 +111,47 @@ ...@@ -111,6 +111,47 @@
shunt-resistor = <1000>; shunt-resistor = <1000>;
}; };
}; };
fman@400000 {
fm1mac1: ethernet@e0000 {
phy-handle = <&sgmii_rtk_phy2>;
phy-connection-type = "sgmii";
sleep = <&rcpm 0x80000000>;
};
fm1mac2: ethernet@e2000 {
sleep = <&rcpm 0x40000000>;
};
fm1mac3: ethernet@e4000 {
phy-handle = <&sgmii_aqr_phy3>;
phy-connection-type = "sgmii-2500";
sleep = <&rcpm 0x20000000>;
};
fm1mac4: ethernet@e6000 {
phy-handle = <&rgmii_rtk_phy1>;
phy-connection-type = "rgmii";
sleep = <&rcpm 0x10000000>;
};
mdio0: mdio@fc000 {
rgmii_rtk_phy1: ethernet-phy@1 {
reg = <0x1>;
};
sgmii_rtk_phy2: ethernet-phy@3 {
reg = <0x3>;
};
};
xmdio0: mdio@fd000 {
sgmii_aqr_phy3: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x2>;
};
};
};
}; };
pci0: pcie@ffe240000 { pci0: pcie@ffe240000 {
......
arch/powerpc/boot/dts/fsl/t1024qds.dts
浏览文件 @ a1b53446
...@@ -87,7 +87,7 @@ ...@@ -87,7 +87,7 @@
flash@0 { flash@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "micron,n25q128a11"; /* 16MB */ compatible = "micron,n25q128a11", "jedec,spi-nor"; /* 16MB */
reg = <0>; reg = <0>;
spi-max-frequency = <10000000>; spi-max-frequency = <10000000>;
}; };
...@@ -95,7 +95,7 @@ ...@@ -95,7 +95,7 @@
flash@1 { flash@1 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "sst,sst25wf040"; /* 512KB */ compatible = "sst,sst25wf040", "jedec,spi-nor"; /* 512KB */
reg = <1>; reg = <1>;
spi-max-frequency = <10000000>; spi-max-frequency = <10000000>;
}; };
...@@ -103,7 +103,7 @@ ...@@ -103,7 +103,7 @@
flash@2 { flash@2 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "eon,en25s64"; /* 8MB */ compatible = "eon,en25s64", "jedec,spi-nor"; /* 8MB */
reg = <2>; reg = <2>;
spi-max-frequency = <10000000>; spi-max-frequency = <10000000>;
}; };
......
arch/powerpc/boot/dts/fsl/t1024rdb.dts
浏览文件 @ a1b53446
...@@ -89,7 +89,7 @@ ...@@ -89,7 +89,7 @@
flash@0 { flash@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "micron,n25q512ax3"; compatible = "micron,n25q512ax3", "jedec,spi-nor";
reg = <0>; reg = <0>;
spi-max-frequency = <10000000>; /* input clk */ spi-max-frequency = <10000000>; /* input clk */
}; };
...@@ -140,6 +140,51 @@ ...@@ -140,6 +140,51 @@
#size-cells = <0>; #size-cells = <0>;
}; };
}; };
fman@400000 {
fm1mac1: ethernet@e0000 {
phy-handle = <&xg_aqr105_phy3>;
phy-connection-type = "xgmii";
sleep = <&rcpm 0x80000000>;
};
fm1mac2: ethernet@e2000 {
sleep = <&rcpm 0x40000000>;
};
fm1mac3: ethernet@e4000 {
phy-handle = <&rgmii_phy2>;
phy-connection-type = "rgmii";
sleep = <&rcpm 0x20000000>;
};
fm1mac4: ethernet@e6000 {
phy-handle = <&rgmii_phy1>;
phy-connection-type = "rgmii";
sleep = <&rcpm 0x10000000>;
};
mdio0: mdio@fc000 {
rgmii_phy1: ethernet-phy@2 {
reg = <0x2>;
};
rgmii_phy2: ethernet-phy@6 {
reg = <0x6>;
};
};
xmdio0: mdio@fd000 {
xg_aqr105_phy3: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x1>;
};
sg_2500_aqr105_phy4: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x2>;
};
};
};
}; };
pci0: pcie@ffe240000 { pci0: pcie@ffe240000 {
......
arch/powerpc/boot/dts/fsl/t1040rdb.dts
浏览文件 @ a1b53446
/* /*
* T1040RDB Device Tree Source * T1040RDB Device Tree Source
* *
* Copyright 2014 Freescale Semiconductor Inc. * Copyright 2014 - 2015 Freescale Semiconductor Inc.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -38,6 +38,36 @@ ...@@ -38,6 +38,36 @@
/ { / {
model = "fsl,T1040RDB"; model = "fsl,T1040RDB";
compatible = "fsl,T1040RDB"; compatible = "fsl,T1040RDB";
aliases {
phy_sgmii_2 = &phy_sgmii_2;
};
soc@ffe000000 {
fman@400000 {
ethernet@e0000 {
fixed-link = <0 1 1000 0 0>;
phy-connection-type = "sgmii";
};
ethernet@e2000 {
fixed-link = <1 1 1000 0 0>;
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-handle = <&phy_sgmii_2>;
phy-connection-type = "sgmii";
};
mdio@fc000 {
phy_sgmii_2: ethernet-phy@03 {
reg = <0x03>;
};
};
};
};
ifc: localbus@ffe124000 { ifc: localbus@ffe124000 {
cpld@3,0 { cpld@3,0 {
compatible = "fsl,t1040rdb-cpld"; compatible = "fsl,t1040rdb-cpld";
......
arch/powerpc/boot/dts/fsl/t1042rdb.dts
浏览文件 @ a1b53446
/* /*
* T1042RDB Device Tree Source * T1042RDB Device Tree Source
* *
* Copyright 2014 Freescale Semiconductor Inc. * Copyright 2014 - 2015 Freescale Semiconductor Inc.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -38,6 +38,34 @@ ...@@ -38,6 +38,34 @@
/ { / {
model = "fsl,T1042RDB"; model = "fsl,T1042RDB";
compatible = "fsl,T1042RDB"; compatible = "fsl,T1042RDB";
aliases {
phy_sgmii_2 = &phy_sgmii_2;
};
soc@ffe000000 {
fman@400000 {
ethernet@e0000 {
status = "disabled";
};
ethernet@e2000 {
status = "disabled";
};
ethernet@e4000 {
phy-handle = <&phy_sgmii_2>;
phy-connection-type = "sgmii";
};
mdio@fc000 {
phy_sgmii_2: ethernet-phy@03 {
reg = <0x03>;
};
};
};
};
ifc: localbus@ffe124000 { ifc: localbus@ffe124000 {
cpld@3,0 { cpld@3,0 {
compatible = "fsl,t1042rdb-cpld"; compatible = "fsl,t1042rdb-cpld";
......
arch/powerpc/boot/dts/fsl/t1042rdb_pi.dts
浏览文件 @ a1b53446
/* /*
* T1042RDB_PI Device Tree Source * T1042RDB_PI Device Tree Source
* *
* Copyright 2014 Freescale Semiconductor Inc. * Copyright 2014 - 2015 Freescale Semiconductor Inc.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -38,11 +38,13 @@ ...@@ -38,11 +38,13 @@
/ { / {
model = "fsl,T1042RDB_PI"; model = "fsl,T1042RDB_PI";
compatible = "fsl,T1042RDB_PI"; compatible = "fsl,T1042RDB_PI";
ifc: localbus@ffe124000 { ifc: localbus@ffe124000 {
cpld@3,0 { cpld@3,0 {
compatible = "fsl,t1042rdb_pi-cpld"; compatible = "fsl,t1042rdb_pi-cpld";
}; };
}; };
soc: soc@ffe000000 { soc: soc@ffe000000 {
i2c@118000 { i2c@118000 {
rtc@68 { rtc@68 {
...@@ -51,6 +53,20 @@ ...@@ -51,6 +53,20 @@
interrupts = <0x2 0x1 0 0>; interrupts = <0x2 0x1 0 0>;
}; };
}; };
fman@400000 {
ethernet@e0000 {
status = "disabled";
};
ethernet@e2000 {
status = "disabled";
};
ethernet@e4000 {
status = "disabled";
};
};
}; };
}; };
......
arch/powerpc/boot/dts/fsl/t104xd4rdb.dtsi
浏览文件 @ a1b53446
...@@ -104,7 +104,7 @@ ...@@ -104,7 +104,7 @@
flash@0 { flash@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "micron,n25q512ax3"; compatible = "micron,n25q512ax3", "jedec,spi-nor";
reg = <0>; reg = <0>;
/* input clock */ /* input clock */
spi-max-frequency = <10000000>; spi-max-frequency = <10000000>;
......
arch/powerpc/boot/dts/fsl/t104xqds.dtsi
浏览文件 @ a1b53446
/* /*
* T104xQDS Device Tree Source * T104xQDS Device Tree Source
* *
* Copyright 2013 - 2014 Freescale Semiconductor Inc. * Copyright 2013 - 2015 Freescale Semiconductor Inc.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -38,6 +38,33 @@ ...@@ -38,6 +38,33 @@
#size-cells = <2>; #size-cells = <2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
aliases {
emi1_rgmii0 = &t1040mdio0;
emi1_rgmii1 = &t1040mdio1;
emi1_slot3 = &t1040mdio3;
emi1_slot5 = &t1040mdio5;
emi1_slot6 = &t1040mdio6;
emi1_slot7 = &t1040mdio7;
rgmii_phy1 = &rgmii_phy1;
rgmii_phy2 = &rgmii_phy2;
phy_s3_01 = &phy_s3_01;
phy_s3_02 = &phy_s3_02;
phy_s3_03 = &phy_s3_03;
phy_s3_04 = &phy_s3_04;
phy_s5_01 = &phy_s5_01;
phy_s5_02 = &phy_s5_02;
phy_s5_03 = &phy_s5_03;
phy_s5_04 = &phy_s5_04;
phy_s6_01 = &phy_s6_01;
phy_s6_02 = &phy_s6_02;
phy_s6_03 = &phy_s6_03;
phy_s6_04 = &phy_s6_04;
phy_s7_01 = &phy_s7_01;
phy_s7_02 = &phy_s7_02;
phy_s7_03 = &phy_s7_03;
phy_s7_04 = &phy_s7_04;
};
reserved-memory { reserved-memory {
#address-cells = <2>; #address-cells = <2>;
#size-cells = <2>; #size-cells = <2>;
...@@ -85,6 +112,128 @@ ...@@ -85,6 +112,128 @@
#size-cells = <1>; #size-cells = <1>;
compatible = "fsl,fpga-qixis"; compatible = "fsl,fpga-qixis";
reg = <3 0 0x300>; reg = <3 0 0x300>;
ranges = <0 3 0 0x300>;
mdio-mux-emi1 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mdio-mux-mmioreg", "mdio-mux";
mdio-parent-bus = <&mdio0>;
reg = <0x54 1>;
mux-mask = <0xe0>;
t1040mdio0: mdio@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x00>;
status = "disabled";
rgmii_phy1: ethernet-phy@1 {
reg = <0x1>;
};
};
t1040mdio1: mdio@20 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x20>;
status = "disabled";
rgmii_phy2: ethernet-phy@2 {
reg = <0x2>;
};
};
t1040mdio3: mdio@60 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x60>;
status = "disabled";
phy_s3_01: ethernet-phy@1c {
reg = <0x1c>;
};
phy_s3_02: ethernet-phy@1d {
reg = <0x1d>;
};
phy_s3_03: ethernet-phy@1e {
reg = <0x1e>;
};
phy_s3_04: ethernet-phy@1f {
reg = <0x1f>;
};
};
t1040mdio5: mdio@a0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0xa0>;
phy_s5_01: ethernet-phy@1c {
reg = <0x14>;
};
phy_s5_02: ethernet-phy@1d {
reg = <0x15>;
};
phy_s5_03: ethernet-phy@1e {
reg = <0x16>;
};
phy_s5_04: ethernet-phy@1f {
reg = <0x17>;
};
};
t1040mdio6: mdio@c0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0xc0>;
phy_s6_01: ethernet-phy@1c {
reg = <0x18>;
};
phy_s6_02: ethernet-phy@1d {
reg = <0x19>;
};
phy_s6_03: ethernet-phy@1e {
reg = <0x1a>;
};
phy_s6_04: ethernet-phy@1f {
reg = <0x1b>;
};
};
t1040mdio7: mdio@e0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0xe0>;
status = "disabled";
phy_s7_01: ethernet-phy@1c {
reg = <0x1c>;
};
phy_s7_02: ethernet-phy@1d {
reg = <0x1d>;
};
phy_s7_03: ethernet-phy@1e {
reg = <0x1e>;
};
phy_s7_04: ethernet-phy@1f {
reg = <0x1f>;
};
};
};
}; };
}; };
...@@ -112,7 +261,7 @@ ...@@ -112,7 +261,7 @@
flash@0 { flash@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "micron,n25q128a11"; compatible = "micron,n25q128a11", "jedec,spi-nor";
reg = <0>; reg = <0>;
spi-max-frequency = <10000000>; /* input clock */ spi-max-frequency = <10000000>; /* input clock */
}; };
...@@ -129,6 +278,33 @@ ...@@ -129,6 +278,33 @@
interrupts = <0x1 0x1 0 0>; interrupts = <0x1 0x1 0 0>;
}; };
}; };
fman@400000 {
ethernet@e0000 {
fixed-link = <0 1 1000 0 0>;
phy-connection-type = "sgmii";
};
ethernet@e2000 {
fixed-link = <1 1 1000 0 0>;
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-handle = <&phy_s7_03>;
phy-connection-type = "sgmii";
};
ethernet@e6000 {
phy-handle = <&rgmii_phy1>;
phy-connection-type = "rgmii";
};
ethernet@e8000 {
phy-handle = <&rgmii_phy2>;
phy-connection-type = "rgmii";
};
};
}; };
pci0: pcie@ffe240000 { pci0: pcie@ffe240000 {
......
arch/powerpc/boot/dts/fsl/t104xrdb.dtsi
浏览文件 @ a1b53446
/* /*
* T1040RDB/T1042RDB Device Tree Source * T1040RDB/T1042RDB Device Tree Source
* *
* Copyright 2014 Freescale Semiconductor Inc. * Copyright 2014 - 2015 Freescale Semiconductor Inc.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -33,6 +33,12 @@ ...@@ -33,6 +33,12 @@
*/ */
/ { / {
aliases {
phy_rgmii_0 = &phy_rgmii_0;
phy_rgmii_1 = &phy_rgmii_1;
phy_sgmii_2 = &phy_sgmii_2;
};
reserved-memory { reserved-memory {
#address-cells = <2>; #address-cells = <2>;
#size-cells = <2>; #size-cells = <2>;
...@@ -103,10 +109,15 @@ ...@@ -103,10 +109,15 @@
flash@0 { flash@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "micron,n25q512a"; compatible = "micron,n25q512a", "jedec,spi-nor";
reg = <0>; reg = <0>;
spi-max-frequency = <10000000>; /* input clock */ spi-max-frequency = <10000000>; /* input clock */
}; };
slic@3 {
compatible = "maxim,ds26522";
reg = <3>;
spi-max-frequency = <2000000>; /* input clock */
};
}; };
i2c@118000 { i2c@118000 {
...@@ -125,6 +136,31 @@ ...@@ -125,6 +136,31 @@
}; };
}; };
fman@400000 {
ethernet@e6000 {
phy-handle = <&phy_rgmii_0>;
phy-connection-type = "rgmii";
};
ethernet@e8000 {
phy-handle = <&phy_rgmii_1>;
phy-connection-type = "rgmii";
};
mdio0: mdio@fc000 {
phy_sgmii_2: ethernet-phy@03 {
reg = <0x03>;
};
phy_rgmii_0: ethernet-phy@01 {
reg = <0x01>;
};
phy_rgmii_1: ethernet-phy@02 {
reg = <0x02>;
};
};
};
}; };
pci0: pcie@ffe240000 { pci0: pcie@ffe240000 {
......
arch/powerpc/boot/dts/fsl/t2080qds.dts
浏览文件 @ a1b53446
/* /*
* T2080QDS Device Tree Source * T2080QDS Device Tree Source
* *
* Copyright 2013 Freescale Semiconductor Inc. * Copyright 2013 - 2015 Freescale Semiconductor Inc.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -42,6 +42,12 @@ ...@@ -42,6 +42,12 @@
#size-cells = <2>; #size-cells = <2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
aliases {
emi1_slot1 = &t2080mdio2;
emi1_slot2 = &t2080mdio3;
emi1_slot3 = &t2080mdio4;
};
rio: rapidio@ffe0c0000 { rio: rapidio@ffe0c0000 {
reg = <0xf 0xfe0c0000 0 0x11000>; reg = <0xf 0xfe0c0000 0 0x11000>;
...@@ -54,4 +60,154 @@ ...@@ -54,4 +60,154 @@
}; };
}; };
&soc {
fman@400000 {
ethernet@e0000 {
phy-handle = <&phy_sgmii_s3_1e>;
phy-connection-type = "xgmii";
};
ethernet@e2000 {
phy-handle = <&phy_sgmii_s3_1f>;
phy-connection-type = "xgmii";
};
ethernet@e4000 {
phy-handle = <&rgmii_phy1>;
phy-connection-type = "rgmii";
};
ethernet@e6000 {
phy-handle = <&rgmii_phy2>;
phy-connection-type = "rgmii";
};
ethernet@e8000 {
phy-handle = <&phy_sgmii_s2_1e>;
phy-connection-type = "sgmii";
};
ethernet@ea000 {
phy-handle = <&phy_sgmii_s2_1d>;
phy-connection-type = "sgmii";
};
ethernet@f0000 {
phy-handle = <&phy_xaui_slot3>;
phy-connection-type = "xgmii";
};
ethernet@f2000 {
phy-handle = <&phy_sgmii_s3_1f>;
phy-connection-type = "xgmii";
};
mdio@fd000 {
phy_xaui_slot3: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x3>;
};
};
};
};
&boardctrl {
mdio-mux-emi1 {
compatible = "mdio-mux-mmioreg", "mdio-mux";
mdio-parent-bus = <&mdio0>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x54 1>;
mux-mask = <0xe0>;
t2080mdio0: mdio@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
rgmii_phy1: ethernet-phy@1 {
reg = <0x1>;
};
};
t2080mdio1: mdio@20 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x20>;
rgmii_phy2: ethernet-phy@2 {
reg = <0x2>;
};
};
t2080mdio2: mdio@40 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40>;
status = "disabled";
phy_sgmii_s1_1c: ethernet-phy@1c {
reg = <0x1c>;
};
phy_sgmii_s1_1d: ethernet-phy@1d {
reg = <0x1d>;
};
phy_sgmii_s1_1e: ethernet-phy@1e {
reg = <0x1e>;
};
phy_sgmii_s1_1f: ethernet-phy@1f {
reg = <0x1f>;
};
};
t2080mdio3: mdio@c0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0xc0>;
phy_sgmii_s2_1c: ethernet-phy@1c {
reg = <0x1c>;
};
phy_sgmii_s2_1d: ethernet-phy@1d {
reg = <0x1d>;
};
phy_sgmii_s2_1e: ethernet-phy@1e {
reg = <0x1e>;
};
phy_sgmii_s2_1f: ethernet-phy@1f {
reg = <0x1f>;
};
};
t2080mdio4: mdio@60 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x60>;
status = "disabled";
phy_sgmii_s3_1c: ethernet-phy@1c {
reg = <0x1c>;
};
phy_sgmii_s3_1d: ethernet-phy@1d {
reg = <0x1d>;
};
phy_sgmii_s3_1e: ethernet-phy@1e {
reg = <0x1e>;
};
phy_sgmii_s3_1f: ethernet-phy@1f {
reg = <0x1f>;
};
};
};
};
/include/ "t2080si-post.dtsi" /include/ "t2080si-post.dtsi"
arch/powerpc/boot/dts/fsl/t2080rdb.dts
浏览文件 @ a1b53446
/* /*
* T2080PCIe-RDB Board Device Tree Source * T2080PCIe-RDB Board Device Tree Source
* *
* Copyright 2014 Freescale Semiconductor Inc. * Copyright 2014 - 2015 Freescale Semiconductor Inc.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -54,4 +54,69 @@ ...@@ -54,4 +54,69 @@
}; };
}; };
&soc {
fman@400000 {
ethernet@e0000 {
phy-handle = <&xg_aq1202_phy3>;
phy-connection-type = "xgmii";
};
ethernet@e2000 {
phy-handle = <&xg_aq1202_phy4>;
phy-connection-type = "xgmii";
};
ethernet@e4000 {
phy-handle = <&rgmii_phy1>;
phy-connection-type = "rgmii";
};
ethernet@e6000 {
phy-handle = <&rgmii_phy2>;
phy-connection-type = "rgmii";
};
ethernet@f0000 {
phy-handle = <&xg_cs4315_phy1>;
phy-connection-type = "xgmii";
};
ethernet@f2000 {
phy-handle = <&xg_cs4315_phy2>;
phy-connection-type = "xgmii";
};
mdio@fc000 {
rgmii_phy1: ethernet-phy@1 {
reg = <0x1>;
};
rgmii_phy2: ethernet-phy@2 {
reg = <0x2>;
};
};
mdio@fd000 {
xg_cs4315_phy1: ethernet-phy@c {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0xc>;
};
xg_cs4315_phy2: ethernet-phy@d {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0xd>;
};
xg_aq1202_phy3: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x0>;
};
xg_aq1202_phy4: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x1>;
};
};
};
};
/include/ "t2080si-post.dtsi" /include/ "t2080si-post.dtsi"
arch/powerpc/boot/dts/fsl/t2081qds.dts
浏览文件 @ a1b53446
/* /*
* T2081QDS Device Tree Source * T2081QDS Device Tree Source
* *
* Copyright 2013 Freescale Semiconductor Inc. * Copyright 2013 - 2015 Freescale Semiconductor Inc.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -41,6 +41,225 @@ ...@@ -41,6 +41,225 @@
#address-cells = <2>; #address-cells = <2>;
#size-cells = <2>; #size-cells = <2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
aliases {
emi1_slot1 = &t2081mdio2;
emi1_slot2 = &t2081mdio3;
emi1_slot3 = &t2081mdio4;
emi1_slot5 = &t2081mdio5;
emi1_slot6 = &t2081mdio6;
emi1_slot7 = &t2081mdio7;
};
};
&soc {
fman@400000 {
ethernet@e0000 {
phy-handle = <&phy_sgmii_s7_1c>;
phy-connection-type = "sgmii";
};
ethernet@e2000 {
phy-handle = <&phy_sgmii_s7_1d>;
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-handle = <&rgmii_phy1>;
phy-connection-type = "rgmii";
};
ethernet@e6000 {
phy-handle = <&rgmii_phy2>;
phy-connection-type = "rgmii";
};
ethernet@e8000 {
phy-handle = <&phy_sgmii_s3_1c>;
phy-connection-type = "sgmii";
};
ethernet@ea000 {
phy-handle = <&phy_sgmii_s7_1f>;
phy-connection-type = "sgmii";
};
ethernet@f0000 {
phy-handle = <&phy_sgmii_s2_1c>;
phy-connection-type = "xgmii";
};
ethernet@f2000 {
phy-handle = <&phy_sgmii_s7_1e>;
phy-connection-type = "xgmii";
};
};
};
&boardctrl {
mdio-mux-emi1 {
compatible = "mdio-mux-mmioreg", "mdio-mux";
mdio-parent-bus = <&mdio0>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x54 1>;
mux-mask = <0xe0>;
t2081mdio0: mdio@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
rgmii_phy1: ethernet-phy@1 {
reg = <0x1>;
};
};
t2081mdio1: mdio@20 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x20>;
rgmii_phy2: ethernet-phy@2 {
reg = <0x2>;
};
};
t2081mdio2: mdio@40 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40>;
phy_sgmii_s1_1c: ethernet-phy@1c {
reg = <0x1c>;
};
phy_sgmii_s1_1d: ethernet-phy@1d {
reg = <0x1d>;
};
phy_sgmii_s1_1e: ethernet-phy@1e {
reg = <0x1e>;
};
phy_sgmii_s1_1f: ethernet-phy@1f {
reg = <0x1f>;
};
};
t2081mdio3: mdio@60 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x60>;
phy_sgmii_s2_1c: ethernet-phy@1c {
reg = <0x1c>;
};
phy_sgmii_s2_1d: ethernet-phy@1d {
reg = <0x1d>;
};
phy_sgmii_s2_1e: ethernet-phy@1e {
reg = <0x1e>;
};
phy_sgmii_s2_1f: ethernet-phy@1f {
reg = <0x1f>;
};
};
t2081mdio4: mdio@80 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x80>;
status = "disabled";
phy_sgmii_s3_1c: ethernet-phy@1c {
reg = <0x1c>;
};
phy_sgmii_s3_1d: ethernet-phy@1d {
reg = <0x1d>;
};
phy_sgmii_s3_1e: ethernet-phy@1e {
reg = <0x1e>;
};
phy_sgmii_s3_1f: ethernet-phy@1f {
reg = <0x1f>;
};
};
t2081mdio5: mdio@a0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0xa0>;
status = "disabled";
phy_sgmii_s5_1c: ethernet-phy@1c {
reg = <0x1c>;
};
phy_sgmii_s5_1d: ethernet-phy@1d {
reg = <0x1d>;
};
phy_sgmii_s5_1e: ethernet-phy@1e {
reg = <0x1e>;
};
phy_sgmii_s5_1f: ethernet-phy@1f {
reg = <0x1f>;
};
};
t2081mdio6: mdio@c0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0xc0>;
status = "disabled";
phy_sgmii_s6_1c: ethernet-phy@1c {
reg = <0x1c>;
};
phy_sgmii_s6_1d: ethernet-phy@1d {
reg = <0x1d>;
};
phy_sgmii_s6_1e: ethernet-phy@1e {
reg = <0x1e>;
};
phy_sgmii_s6_1f: ethernet-phy@1f {
reg = <0x1f>;
};
};
t2081mdio7: mdio@e0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0xe0>;
phy_sgmii_s7_1c: ethernet-phy@1c {
reg = <0x1c>;
};
phy_sgmii_s7_1d: ethernet-phy@1d {
reg = <0x1d>;
};
phy_sgmii_s7_1e: ethernet-phy@1e {
reg = <0x1e>;
};
phy_sgmii_s7_1f: ethernet-phy@1f {
reg = <0x1f>;
};
};
};
}; };
/include/ "t2081si-post.dtsi" /include/ "t2081si-post.dtsi"
arch/powerpc/boot/dts/fsl/t208xqds.dtsi
浏览文件 @ a1b53446
...@@ -112,7 +112,7 @@ ...@@ -112,7 +112,7 @@
flash@0 { flash@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "micron,n25q128a11"; /* 16MB */ compatible = "micron,n25q128a11", "jedec,spi-nor"; /* 16MB */
reg = <0>; reg = <0>;
spi-max-frequency = <40000000>; /* input clock */ spi-max-frequency = <40000000>; /* input clock */
}; };
...@@ -120,7 +120,7 @@ ...@@ -120,7 +120,7 @@
flash@1 { flash@1 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "sst,sst25wf040"; compatible = "sst,sst25wf040", "jedec,spi-nor";
reg = <1>; reg = <1>;
spi-max-frequency = <35000000>; spi-max-frequency = <35000000>;
}; };
...@@ -128,7 +128,7 @@ ...@@ -128,7 +128,7 @@
flash@2 { flash@2 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "eon,en25s64"; compatible = "eon,en25s64", "jedec,spi-nor";
reg = <2>; reg = <2>;
spi-max-frequency = <35000000>; spi-max-frequency = <35000000>;
}; };
......
arch/powerpc/boot/dts/fsl/t208xrdb.dtsi
浏览文件 @ a1b53446
...@@ -113,7 +113,7 @@ ...@@ -113,7 +113,7 @@
flash@0 { flash@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "micron,n25q512a"; compatible = "micron,n25q512a", "jedec,spi-nor";
reg = <0>; reg = <0>;
spi-max-frequency = <10000000>; /* input clock */ spi-max-frequency = <10000000>; /* input clock */
}; };
......
arch/powerpc/boot/dts/fsl/t4240qds.dts
浏览文件 @ a1b53446
/* /*
* T4240QDS Device Tree Source * T4240QDS Device Tree Source
* *
* Copyright 2012 - 2014 Freescale Semiconductor Inc. * Copyright 2012 - 2015 Freescale Semiconductor Inc.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -41,6 +41,44 @@ ...@@ -41,6 +41,44 @@
#size-cells = <2>; #size-cells = <2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
aliases{
phy_rgmii1 = &phyrgmii1;
phy_rgmii2 = &phyrgmii2;
phy_sgmii3 = &phy3;
phy_sgmii4 = &phy4;
phy_sgmii11 = &phy11;
phy_sgmii12 = &phy12;
sgmii_phy11 = &sgmiiphy11;
sgmii_phy12 = &sgmiiphy12;
sgmii_phy13 = &sgmiiphy13;
sgmii_phy14 = &sgmiiphy14;
sgmii_phy21 = &sgmiiphy21;
sgmii_phy22 = &sgmiiphy22;
sgmii_phy23 = &sgmiiphy23;
sgmii_phy24 = &sgmiiphy24;
sgmii_phy31 = &sgmiiphy31;
sgmii_phy32 = &sgmiiphy32;
sgmii_phy33 = &sgmiiphy33;
sgmii_phy34 = &sgmiiphy34;
sgmii_phy41 = &sgmiiphy41;
sgmii_phy42 = &sgmiiphy42;
sgmii_phy43 = &sgmiiphy43;
sgmii_phy44 = &sgmiiphy44;
phy_xfi1 = &xfiphy1;
phy_xfi2 = &xfiphy2;
phy_xfi3 = &xfiphy3;
phy_xfi4 = &xfiphy4;
xfi_pcs_mdio1 = &xfimdio0;
xfi_pcs_mdio2 = &xfimdio1;
xfi_pcs_mdio3 = &xfimdio2;
xfi_pcs_mdio4 = &xfimdio3;
emi1_rgmii = &t4240mdio0;
emi1_slot1 = &t4240mdio1;
emi1_slot2 = &t4240mdio2;
emi1_slot3 = &t4240mdio3;
emi1_slot4 = &t4240mdio4;
};
ifc: localbus@ffe124000 { ifc: localbus@ffe124000 {
reg = <0xf 0xfe124000 0 0x2000>; reg = <0xf 0xfe124000 0 0x2000>;
ranges = <0 0 0xf 0xe8000000 0x08000000 ranges = <0 0 0xf 0xe8000000 0x08000000
...@@ -91,8 +129,190 @@ ...@@ -91,8 +129,190 @@
}; };
board-control@3,0 { board-control@3,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,t4240qds-fpga", "fsl,fpga-qixis"; compatible = "fsl,t4240qds-fpga", "fsl,fpga-qixis";
reg = <3 0 0x300>; reg = <3 0 0x300>;
ranges = <0 3 0 0x300>;
mdio-mux-emi1 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mdio-mux-mmioreg", "mdio-mux";
mdio-parent-bus = <&mdio1>;
reg = <0x54 1>;
mux-mask = <0xe0>;
t4240mdio0: mdio@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
phyrgmii1: ethernet-phy@1 {
reg = <0x1>;
};
phyrgmii2: ethernet-phy@2 {
reg = <0x2>;
};
};
t4240mdio1: mdio@20 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x20>;
status = "disabled";
phy1: ethernet-phy@0 {
reg = <0x0>;
};
phy2: ethernet-phy@1 {
reg = <0x1>;
};
phy3: ethernet-phy@2 {
reg = <0x2>;
};
phy4: ethernet-phy@3 {
reg = <0x3>;
};
sgmiiphy11: ethernet-phy@1c {
reg = <0x1c>;
};
sgmiiphy12: ethernet-phy@1d {
reg = <0x1d>;
};
sgmiiphy13: ethernet-phy@1e {
reg = <0x1e>;
};
sgmiiphy14: ethernet-phy@1f {
reg = <0x1f>;
};
};
t4240mdio2: mdio@40 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40>;
status = "disabled";
phy5: ethernet-phy@4 {
reg = <0x4>;
};
phy6: ethernet-phy@5 {
reg = <0x5>;
};
phy7: ethernet-phy@6 {
reg = <0x6>;
};
phy8: ethernet-phy@7 {
reg = <0x7>;
};
sgmiiphy21: ethernet-phy@1c {
reg = <0x1c>;
};
sgmiiphy22: ethernet-phy@1d {
reg = <0x1d>;
};
sgmiiphy23: ethernet-phy@1e {
reg = <0x1e>;
};
sgmiiphy24: ethernet-phy@1f {
reg = <0x1f>;
};
};
t4240mdio3: mdio@60 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x60>;
status = "disabled";
phy9: ethernet-phy@8 {
reg = <0x8>;
};
phy10: ethernet-phy@9 {
reg = <0x9>;
};
phy11: ethernet-phy@a {
reg = <0xa>;
};
phy12: ethernet-phy@b {
reg = <0xb>;
};
sgmiiphy31: ethernet-phy@1c {
reg = <0x1c>;
};
sgmiiphy32: ethernet-phy@1d {
reg = <0x1d>;
};
sgmiiphy33: ethernet-phy@1e {
reg = <0x1e>;
};
sgmiiphy34: ethernet-phy@1f {
reg = <0x1f>;
};
};
t4240mdio4: mdio@80 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x80>;
status = "disabled";
phy13: ethernet-phy@c {
reg = <0xc>;
};
phy14: ethernet-phy@d {
reg = <0xd>;
};
phy15: ethernet-phy@e {
reg = <0xe>;
};
phy16: ethernet-phy@f {
reg = <0xf>;
};
sgmiiphy41: ethernet-phy@1c {
reg = <0x1c>;
};
sgmiiphy42: ethernet-phy@1d {
reg = <0x1d>;
};
sgmiiphy43: ethernet-phy@1e {
reg = <0x1e>;
};
sgmiiphy44: ethernet-phy@1f {
reg = <0x1f>;
};
};
};
}; };
}; };
...@@ -138,7 +358,7 @@ ...@@ -138,7 +358,7 @@
flash@0 { flash@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "sst,sst25wf040"; compatible = "sst,sst25wf040", "jedec,spi-nor";
reg = <0>; reg = <0>;
spi-max-frequency = <40000000>; /* input clock */ spi-max-frequency = <40000000>; /* input clock */
}; };
...@@ -234,6 +454,184 @@ ...@@ -234,6 +454,184 @@
sdhc@114000 { sdhc@114000 {
voltage-ranges = <1800 1800 3300 3300>; voltage-ranges = <1800 1800 3300 3300>;
}; };
fman@400000 {
port@83000 {
status = "disabled";
};
port@84000 {
status = "disabled";
};
port@85000 {
status = "disabled";
};
port@86000 {
status = "disabled";
};
port@87000 {
status = "disabled";
};
ethernet@e0000 {
phy-handle = <&phy5>;
phy-connection-type = "sgmii";
};
ethernet@e2000 {
phy-handle = <&phy6>;
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-handle = <&phy7>;
phy-connection-type = "sgmii";
};
ethernet@e6000 {
phy-handle = <&phy8>;
phy-connection-type = "sgmii";
};
ethernet@e8000 {
phy-handle = <&phyrgmii2>;
phy-connection-type = "rgmii";
};
ethernet@ea000 {
phy-handle = <&phy2>;
phy-connection-type = "sgmii";
};
ethernet@f0000 {
phy-handle = <&xauiphy1>;
phy-connection-type = "xgmii";
};
ethernet@f2000 {
phy-handle = <&xauiphy2>;
phy-connection-type = "xgmii";
};
xfimdio0: mdio@f1000 {
status = "disabled";
xfiphy1: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x0>;
};
};
xfimdio1: mdio@f3000 {
status = "disabled";
xfiphy2: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x0>;
};
};
};
fman@500000 {
port@84000 {
status = "disabled";
};
port@85000 {
status = "disabled";
};
port@86000 {
status = "disabled";
};
port@87000 {
status = "disabled";
};
ethernet@e0000 {
phy-handle = <&phy13>;
phy-connection-type = "sgmii";
};
ethernet@e2000 {
phy-handle = <&phy14>;
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-handle = <&phy15>;
phy-connection-type = "sgmii";
};
ethernet@e6000 {
phy-handle = <&phy16>;
phy-connection-type = "sgmii";
};
ethernet@e8000 {
phy-handle = <&phyrgmii1>;
phy-connection-type = "rgmii";
};
ethernet@ea000 {
phy-handle = <&phy10>;
phy-connection-type = "sgmii";
};
ethernet@f0000 {
phy-handle = <&xauiphy3>;
phy-connection-type = "xgmii";
};
ethernet@f2000 {
phy-handle = <&xauiphy4>;
phy-connection-type = "xgmii";
};
xfimdio2: mdio@f1000 {
status = "disabled";
xfiphy3: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x0>;
};
};
xfimdio3: mdio@f3000 {
status = "disabled";
xfiphy4: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x0>;
};
};
mdio@fd000 {
xauiphy1: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x0>;
};
xauiphy2: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x1>;
};
xauiphy3: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x2>;
};
xauiphy4: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x3>;
};
};
};
}; };
pci0: pcie@ffe240000 { pci0: pcie@ffe240000 {
......
arch/powerpc/boot/dts/fsl/t4240rdb.dts
浏览文件 @ a1b53446
/* /*
* T4240RDB Device Tree Source * T4240RDB Device Tree Source
* *
* Copyright 2014 Freescale Semiconductor Inc. * Copyright 2014 - 2015 Freescale Semiconductor Inc.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -41,6 +41,17 @@ ...@@ -41,6 +41,17 @@
#size-cells = <2>; #size-cells = <2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
aliases {
sgmii_phy21 = &sgmiiphy21;
sgmii_phy22 = &sgmiiphy22;
sgmii_phy23 = &sgmiiphy23;
sgmii_phy24 = &sgmiiphy24;
sgmii_phy41 = &sgmiiphy41;
sgmii_phy42 = &sgmiiphy42;
sgmii_phy43 = &sgmiiphy43;
sgmii_phy44 = &sgmiiphy44;
};
ifc: localbus@ffe124000 { ifc: localbus@ffe124000 {
reg = <0xf 0xfe124000 0 0x2000>; reg = <0xf 0xfe124000 0 0x2000>;
ranges = <0 0 0xf 0xe8000000 0x08000000 ranges = <0 0 0xf 0xe8000000 0x08000000
...@@ -107,7 +118,7 @@ ...@@ -107,7 +118,7 @@
flash@0 { flash@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "sst,sst25wf040"; compatible = "sst,sst25wf040", "jedec,spi-nor";
reg = <0>; reg = <0>;
spi-max-frequency = <40000000>; /* input clock */ spi-max-frequency = <40000000>; /* input clock */
}; };
...@@ -136,6 +147,142 @@ ...@@ -136,6 +147,142 @@
sdhc@114000 { sdhc@114000 {
voltage-ranges = <1800 1800 3300 3300>; voltage-ranges = <1800 1800 3300 3300>;
}; };
fman@400000 {
ethernet@e0000 {
phy-handle = <&sgmiiphy21>;
phy-connection-type = "sgmii";
};
ethernet@e2000 {
phy-handle = <&sgmiiphy22>;
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-handle = <&sgmiiphy23>;
phy-connection-type = "sgmii";
};
ethernet@e6000 {
phy-handle = <&sgmiiphy24>;
phy-connection-type = "sgmii";
};
ethernet@e8000 {
status = "disabled";
};
ethernet@ea000 {
status = "disabled";
};
ethernet@f0000 {
phy-handle = <&xfiphy1>;
phy-connection-type = "xgmii";
};
ethernet@f2000 {
phy-handle = <&xfiphy2>;
phy-connection-type = "xgmii";
};
};
fman@500000 {
ethernet@e0000 {
phy-handle = <&sgmiiphy41>;
phy-connection-type = "sgmii";
};
ethernet@e2000 {
phy-handle = <&sgmiiphy42>;
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-handle = <&sgmiiphy43>;
phy-connection-type = "sgmii";
};
ethernet@e6000 {
phy-handle = <&sgmiiphy44>;
phy-connection-type = "sgmii";
};
ethernet@e8000 {
status = "disabled";
};
ethernet@ea000 {
status = "disabled";
};
ethernet@f0000 {
phy-handle = <&xfiphy3>;
phy-connection-type = "xgmii";
};
ethernet@f2000 {
phy-handle = <&xfiphy4>;
phy-connection-type = "xgmii";
};
mdio@fc000 {
sgmiiphy21: ethernet-phy@0 {
reg = <0x0>;
};
sgmiiphy22: ethernet-phy@1 {
reg = <0x1>;
};
sgmiiphy23: ethernet-phy@2 {
reg = <0x2>;
};
sgmiiphy24: ethernet-phy@3 {
reg = <0x3>;
};
sgmiiphy41: ethernet-phy@4 {
reg = <0x4>;
};
sgmiiphy42: ethernet-phy@5 {
reg = <0x5>;
};
sgmiiphy43: ethernet-phy@6 {
reg = <0x6>;
};
sgmiiphy44: ethernet-phy@7 {
reg = <0x7>;
};
};
mdio@fd000 {
xfiphy1: ethernet-phy@10 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x10>;
};
xfiphy2: ethernet-phy@11 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x11>;
};
xfiphy3: ethernet-phy@13 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x13>;
};
xfiphy4: ethernet-phy@12 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x12>;
};
};
};
}; };
pci0: pcie@ffe240000 { pci0: pcie@ffe240000 {
......
arch/powerpc/configs/83xx/mpc834x_itx_defconfig
浏览文件 @ a1b53446
...@@ -35,7 +35,6 @@ CONFIG_MTD_PHYSMAP=y ...@@ -35,7 +35,6 @@ CONFIG_MTD_PHYSMAP=y
CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=32768 CONFIG_BLK_DEV_RAM_SIZE=32768
CONFIG_IDE=y
CONFIG_BLK_DEV_SD=y CONFIG_BLK_DEV_SD=y
CONFIG_CHR_DEV_SG=y CONFIG_CHR_DEV_SG=y
CONFIG_SCSI_SPI_ATTRS=y CONFIG_SCSI_SPI_ATTRS=y
......
arch/powerpc/configs/85xx/ksi8560_defconfig
浏览文件 @ a1b53446
...@@ -34,7 +34,6 @@ CONFIG_MTD_PHYSMAP_OF=y ...@@ -34,7 +34,6 @@ CONFIG_MTD_PHYSMAP_OF=y
CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=32768 CONFIG_BLK_DEV_RAM_SIZE=32768
CONFIG_IDE=y
CONFIG_NETDEVICES=y CONFIG_NETDEVICES=y
CONFIG_FS_ENET=y CONFIG_FS_ENET=y
# CONFIG_FS_ENET_HAS_SCC is not set # CONFIG_FS_ENET_HAS_SCC is not set
......
arch/powerpc/configs/85xx/stx_gp3_defconfig
浏览文件 @ a1b53446
...@@ -31,8 +31,6 @@ CONFIG_BLK_DEV_LOOP=m ...@@ -31,8 +31,6 @@ CONFIG_BLK_DEV_LOOP=m
CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_NBD=m
CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=32768 CONFIG_BLK_DEV_RAM_SIZE=32768
CONFIG_IDE=y
CONFIG_BLK_DEV_IDECD=m
CONFIG_SCSI=m CONFIG_SCSI=m
CONFIG_BLK_DEV_SD=m CONFIG_BLK_DEV_SD=m
CONFIG_CHR_DEV_ST=m CONFIG_CHR_DEV_ST=m
......
arch/powerpc/configs/86xx/mpc8641_hpcn_defconfig → arch/powerpc/configs/86xx-hw.config
浏览文件 @ a1b53446
CONFIG_SMP=y CONFIG_ATA=y
CONFIG_NR_CPUS=2
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_AUDIT=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
CONFIG_KALLSYMS_ALL=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_MODVERSIONS=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_PARTITION_ADVANCED=y
CONFIG_MAC_PARTITION=y
# CONFIG_PPC_CHRP is not set
# CONFIG_PPC_PMAC is not set
CONFIG_PPC_86xx=y
CONFIG_MPC8641_HPCN=y
CONFIG_HIGHMEM=y
CONFIG_HZ_1000=y
CONFIG_BINFMT_MISC=m
CONFIG_PCI=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_XFRM_USER=y
CONFIG_NET_KEY=m
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
CONFIG_IP_MULTIPLE_TABLES=y
CONFIG_IP_ROUTE_MULTIPATH=y
CONFIG_IP_ROUTE_VERBOSE=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y
CONFIG_NET_IPIP=y
CONFIG_IP_MROUTE=y
CONFIG_IP_PIMSM_V1=y
CONFIG_IP_PIMSM_V2=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
CONFIG_IPV6=y
CONFIG_IP_SCTP=m
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_NBD=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=131072
CONFIG_EEPROM_LEGACY=y
CONFIG_BLK_DEV_SD=y CONFIG_BLK_DEV_SD=y
CONFIG_CHR_DEV_ST=y
CONFIG_BLK_DEV_SR=y CONFIG_BLK_DEV_SR=y
CONFIG_BROADCOM_PHY=y
# CONFIG_CARDBUS is not set
CONFIG_CHR_DEV_SG=y CONFIG_CHR_DEV_SG=y
CONFIG_SCSI_LOGGING=y CONFIG_CHR_DEV_ST=y
CONFIG_ATA=y CONFIG_CRC_T10DIF=y
CONFIG_SATA_AHCI=y CONFIG_CRYPTO_HMAC=y
CONFIG_PATA_ALI=y CONFIG_DS1682=y
CONFIG_NETDEVICES=y CONFIG_EEPROM_LEGACY=y
CONFIG_DUMMY=y CONFIG_GEF_WDT=y
CONFIG_GIANFAR=y CONFIG_GIANFAR=y
CONFIG_VITESSE_PHY=y CONFIG_GPIO_GE_FPGA=y
CONFIG_INPUT_FF_MEMLESS=m CONFIG_GPIO_SYSFS=y
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
CONFIG_SERIO_LIBPS2=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=2
CONFIG_SERIAL_8250_RUNTIME_UARTS=2
CONFIG_SERIAL_8250_EXTENDED=y
CONFIG_SERIAL_8250_MANY_PORTS=y
CONFIG_SERIAL_8250_SHARE_IRQ=y
CONFIG_SERIAL_8250_DETECT_IRQ=y
CONFIG_SERIAL_8250_RSA=y
# CONFIG_HW_RANDOM is not set
CONFIG_NVRAM=y
CONFIG_I2C=y
CONFIG_I2C_MPC=y
# CONFIG_HWMON is not set
CONFIG_SOUND=y
CONFIG_SND=y
CONFIG_SND_MIXER_OSS=y
CONFIG_SND_PCM_OSS=y
# CONFIG_SND_SUPPORT_OLD_API is not set
CONFIG_SND_INTEL8X0=y
CONFIG_HID_A4TECH=y CONFIG_HID_A4TECH=y
CONFIG_HID_APPLE=y CONFIG_HID_APPLE=y
CONFIG_HID_BELKIN=y CONFIG_HID_BELKIN=y
...@@ -110,47 +28,77 @@ CONFIG_HID_PANTHERLORD=y ...@@ -110,47 +28,77 @@ CONFIG_HID_PANTHERLORD=y
CONFIG_HID_PETALYNX=y CONFIG_HID_PETALYNX=y
CONFIG_HID_SAMSUNG=y CONFIG_HID_SAMSUNG=y
CONFIG_HID_SUNPLUS=y CONFIG_HID_SUNPLUS=y
CONFIG_USB=y CONFIG_HW_RANDOM=y
CONFIG_USB_MON=y CONFIG_HZ_1000=y
CONFIG_I2C_MPC=y
CONFIG_I2C=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
CONFIG_INPUT_FF_MEMLESS=m
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_MOUSE is not set
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_LE_BYTE_SWAP=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_NAND_FSL_ELBC=y
CONFIG_MTD_NAND=y
CONFIG_MTD_PHYSMAP_OF=y
CONFIG_NETDEVICES=y
CONFIG_NET_TULIP=y
CONFIG_NVRAM=y
CONFIG_PATA_ALI=y
CONFIG_PCCARD=y
CONFIG_PCI_DEBUG=y
# CONFIG_PCIEASPM is not set
CONFIG_PCIEPORTBUS=y
CONFIG_PCI=y
# CONFIG_PCMCIA_LOAD_CIS is not set
# CONFIG_PPC_CHRP is not set
# CONFIG_PPC_PMAC is not set
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_CMOS=y
CONFIG_RTC_DRV_RX8581=y
CONFIG_SATA_AHCI=y
CONFIG_SATA_SIL24=y
CONFIG_SATA_SIL=y
CONFIG_SCSI_LOGGING=y
CONFIG_SENSORS_LM90=y
CONFIG_SENSORS_LM92=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_DETECT_IRQ=y
CONFIG_SERIAL_8250_EXTENDED=y
CONFIG_SERIAL_8250_MANY_PORTS=y
CONFIG_SERIAL_8250_NR_UARTS=2
CONFIG_SERIAL_8250_RSA=y
CONFIG_SERIAL_8250_RUNTIME_UARTS=2
CONFIG_SERIAL_8250_SHARE_IRQ=y
CONFIG_SERIAL_8250=y
CONFIG_SERIO_LIBPS2=y
CONFIG_SND_INTEL8X0=y
CONFIG_SND_MIXER_OSS=y
CONFIG_SND_PCM_OSS=y
# CONFIG_SND_SUPPORT_OLD_API is not set
CONFIG_SND=y
CONFIG_SOUND=y
CONFIG_ULI526X=y
CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y CONFIG_USB_MON=y
CONFIG_USB_OHCI_HCD_PPC_OF_BE=y CONFIG_USB_OHCI_HCD_PPC_OF_BE=y
CONFIG_USB_OHCI_HCD_PPC_OF_LE=y CONFIG_USB_OHCI_HCD_PPC_OF_LE=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_STORAGE=y CONFIG_USB_STORAGE=y
CONFIG_RTC_CLASS=y CONFIG_USB=y
CONFIG_RTC_DRV_CMOS=y CONFIG_VITESSE_PHY=y
CONFIG_EXT2_FS=y CONFIG_VME_BUS=y
CONFIG_EXT3_FS=y CONFIG_VME_TSI148=y
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set CONFIG_WATCHDOG=y
CONFIG_ISO9660_FS=m # CONFIG_YENTA_O2 is not set
CONFIG_JOLIET=y # CONFIG_YENTA_RICOH is not set
CONFIG_ZISOFS=y # CONFIG_YENTA_TOSHIBA is not set
CONFIG_UDF_FS=m CONFIG_YENTA=y
CONFIG_MSDOS_FS=m
CONFIG_VFAT_FS=y
CONFIG_NTFS_FS=y
CONFIG_PROC_KCORE=y
CONFIG_TMPFS=y
CONFIG_ADFS_FS=m
CONFIG_AFFS_FS=m
CONFIG_HFS_FS=m
CONFIG_HFSPLUS_FS=m
CONFIG_BEFS_FS=m
CONFIG_BFS_FS=m
CONFIG_EFS_FS=m
CONFIG_CRAMFS=y
CONFIG_VXFS_FS=m
CONFIG_HPFS_FS=m
CONFIG_QNX4FS_FS=m
CONFIG_SYSV_FS=m
CONFIG_UFS_FS=m
CONFIG_NFS_FS=y
CONFIG_NFS_V4=y
CONFIG_ROOT_NFS=y
CONFIG_NFSD=y
CONFIG_CRC_T10DIF=y
CONFIG_DEBUG_INFO=y
CONFIG_DETECT_HUNG_TASK=y
CONFIG_CRYPTO_PCBC=m
CONFIG_CRYPTO_HMAC=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set
arch/powerpc/configs/86xx-smp.config 0 → 100644
浏览文件 @ a1b53446
CONFIG_NR_CPUS=2
CONFIG_SMP=y
arch/powerpc/configs/86xx/gef_ppc9a_defconfig 已删除 100644 → 0
浏览文件 @ d8c0282f
CONFIG_SMP=y
CONFIG_NR_CPUS=2
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BSD_PROCESS_ACCT_V3=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_PPC_CHRP is not set
# CONFIG_PPC_PMAC is not set
CONFIG_PPC_86xx=y
CONFIG_GEF_PPC9A=y
CONFIG_HIGHMEM=y
CONFIG_HZ_1000=y
CONFIG_PREEMPT=y
CONFIG_BINFMT_MISC=m
CONFIG_PCI=y
CONFIG_PCIEPORTBUS=y
# CONFIG_PCIEASPM is not set
CONFIG_PCCARD=y
# CONFIG_PCMCIA_LOAD_CIS is not set
# CONFIG_CARDBUS is not set
CONFIG_YENTA=y
# CONFIG_YENTA_O2 is not set
# CONFIG_YENTA_RICOH is not set
# CONFIG_YENTA_TOSHIBA is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_XFRM_USER=m
CONFIG_NET_KEY=m
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
CONFIG_IP_MULTIPLE_TABLES=y
CONFIG_IP_ROUTE_MULTIPATH=y
CONFIG_IP_ROUTE_VERBOSE=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y
CONFIG_NET_IPIP=m
CONFIG_IP_MROUTE=y
CONFIG_IP_PIMSM_V1=y
CONFIG_IP_PIMSM_V2=y
CONFIG_SYN_COOKIES=y
CONFIG_INET_AH=m
CONFIG_INET_ESP=m
CONFIG_INET_IPCOMP=m
# CONFIG_INET_XFRM_MODE_BEET is not set
CONFIG_INET6_AH=m
CONFIG_INET6_ESP=m
CONFIG_INET6_IPCOMP=m
CONFIG_IPV6_TUNNEL=m
CONFIG_NET_PKTGEN=m
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_MTD=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP_OF=y
CONFIG_BLK_DEV_LOOP=m
CONFIG_BLK_DEV_CRYPTOLOOP=m
CONFIG_BLK_DEV_NBD=m
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=131072
CONFIG_DS1682=y
CONFIG_IDE=y
CONFIG_BLK_DEV_IDECS=y
CONFIG_BLK_DEV_SD=y
CONFIG_CHR_DEV_ST=y
CONFIG_BLK_DEV_SR=y
CONFIG_ATA=y
CONFIG_SATA_SIL=y
CONFIG_NETDEVICES=y
CONFIG_BONDING=m
CONFIG_DUMMY=m
CONFIG_NETCONSOLE=y
CONFIG_TUN=m
CONFIG_GIANFAR=y
CONFIG_PPP=m
CONFIG_PPP_BSDCOMP=m
CONFIG_PPP_DEFLATE=m
CONFIG_PPP_FILTER=y
CONFIG_PPP_MULTILINK=y
CONFIG_PPPOE=m
CONFIG_PPP_ASYNC=m
CONFIG_PPP_SYNC_TTY=m
CONFIG_SLIP=m
CONFIG_SLIP_COMPRESSED=y
CONFIG_SLIP_SMART=y
CONFIG_SLIP_MODE_SLIP6=y
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
# CONFIG_SERIAL_8250_PCI is not set
CONFIG_SERIAL_8250_NR_UARTS=2
CONFIG_SERIAL_8250_RUNTIME_UARTS=2
CONFIG_HW_RANDOM=y
CONFIG_NVRAM=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MPC=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_GE_FPGA=y
CONFIG_SENSORS_LM90=y
CONFIG_SENSORS_LM92=y
CONFIG_WATCHDOG=y
CONFIG_GEF_WDT=y
CONFIG_HID_A4TECH=y
CONFIG_HID_APPLE=y
CONFIG_HID_BELKIN=y
CONFIG_HID_CHERRY=y
CONFIG_HID_CHICONY=y
CONFIG_HID_CYPRESS=y
CONFIG_HID_EZKEY=y
CONFIG_HID_GYRATION=y
CONFIG_HID_LOGITECH=y
CONFIG_HID_MICROSOFT=y
CONFIG_HID_MONTEREY=y
CONFIG_HID_PANTHERLORD=y
CONFIG_HID_PETALYNX=y
CONFIG_HID_SAMSUNG=y
CONFIG_HID_SUNPLUS=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_USB_EHCI_HCD_PPC_OF is not set
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_RTC_CLASS=y
# CONFIG_RTC_INTF_PROC is not set
CONFIG_RTC_DRV_RX8581=y
CONFIG_STAGING=y
CONFIG_VME_BUS=y
CONFIG_VME_TSI148=y
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_POSIX_ACL=y
CONFIG_EXT3_FS=y
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
CONFIG_EXT3_FS_POSIX_ACL=y
CONFIG_ISO9660_FS=y
CONFIG_JOLIET=y
CONFIG_ZISOFS=y
CONFIG_UDF_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_FAT_DEFAULT_CODEPAGE=850
CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
CONFIG_PROC_KCORE=y
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V4=y
CONFIG_ROOT_NFS=y
CONFIG_CIFS=m
CONFIG_CIFS_XATTR=y
CONFIG_CIFS_POSIX=y
CONFIG_NLS_CODEPAGE_437=m
CONFIG_NLS_CODEPAGE_737=m
CONFIG_NLS_CODEPAGE_775=m
CONFIG_NLS_CODEPAGE_850=m
CONFIG_NLS_CODEPAGE_852=m
CONFIG_NLS_CODEPAGE_855=m
CONFIG_NLS_CODEPAGE_857=m
CONFIG_NLS_CODEPAGE_860=m
CONFIG_NLS_CODEPAGE_861=m
CONFIG_NLS_CODEPAGE_862=m
CONFIG_NLS_CODEPAGE_863=m
CONFIG_NLS_CODEPAGE_864=m
CONFIG_NLS_CODEPAGE_865=m
CONFIG_NLS_CODEPAGE_866=m
CONFIG_NLS_CODEPAGE_869=m
CONFIG_NLS_CODEPAGE_936=m
CONFIG_NLS_CODEPAGE_950=m
CONFIG_NLS_CODEPAGE_932=m
CONFIG_NLS_CODEPAGE_949=m
CONFIG_NLS_CODEPAGE_874=m
CONFIG_NLS_ISO8859_8=m
CONFIG_NLS_CODEPAGE_1250=m
CONFIG_NLS_CODEPAGE_1251=m
CONFIG_NLS_ASCII=m
CONFIG_NLS_ISO8859_1=m
CONFIG_NLS_ISO8859_2=m
CONFIG_NLS_ISO8859_3=m
CONFIG_NLS_ISO8859_4=m
CONFIG_NLS_ISO8859_5=m
CONFIG_NLS_ISO8859_6=m
CONFIG_NLS_ISO8859_7=m
CONFIG_NLS_ISO8859_9=m
CONFIG_NLS_ISO8859_13=m
CONFIG_NLS_ISO8859_14=m
CONFIG_NLS_ISO8859_15=m
CONFIG_NLS_KOI8_R=m
CONFIG_NLS_KOI8_U=m
CONFIG_NLS_UTF8=m
CONFIG_CRC_CCITT=y
CONFIG_CRC_T10DIF=y
CONFIG_LIBCRC32C=y
CONFIG_MAGIC_SYSRQ=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set
# CONFIG_CRYPTO_HW is not set
arch/powerpc/configs/86xx/gef_sbc310_defconfig 已删除 100644 → 0
浏览文件 @ d8c0282f
CONFIG_SMP=y
CONFIG_NR_CPUS=2
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BSD_PROCESS_ACCT_V3=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_PPC_CHRP is not set
# CONFIG_PPC_PMAC is not set
CONFIG_PPC_86xx=y
CONFIG_GEF_SBC310=y
CONFIG_HIGHMEM=y
CONFIG_HZ_1000=y
CONFIG_PREEMPT=y
CONFIG_BINFMT_MISC=y
CONFIG_PCI=y
CONFIG_PCIEPORTBUS=y
# CONFIG_PCIEASPM is not set
CONFIG_PCCARD=y
# CONFIG_PCMCIA_LOAD_CIS is not set
# CONFIG_CARDBUS is not set
CONFIG_YENTA=y
# CONFIG_YENTA_O2 is not set
# CONFIG_YENTA_RICOH is not set
# CONFIG_YENTA_TOSHIBA is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_XFRM_USER=m
CONFIG_NET_KEY=m
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
CONFIG_IP_MULTIPLE_TABLES=y
CONFIG_IP_ROUTE_MULTIPATH=y
CONFIG_IP_ROUTE_VERBOSE=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y
CONFIG_NET_IPIP=m
CONFIG_IP_MROUTE=y
CONFIG_IP_PIMSM_V1=y
CONFIG_IP_PIMSM_V2=y
CONFIG_SYN_COOKIES=y
CONFIG_INET_AH=m
CONFIG_INET_ESP=m
CONFIG_INET_IPCOMP=m
# CONFIG_INET_XFRM_MODE_BEET is not set
CONFIG_INET6_AH=m
CONFIG_INET6_ESP=m
CONFIG_INET6_IPCOMP=m
CONFIG_IPV6_TUNNEL=m
CONFIG_NET_PKTGEN=m
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_MTD=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP_OF=y
CONFIG_BLK_DEV_LOOP=m
CONFIG_BLK_DEV_CRYPTOLOOP=m
CONFIG_BLK_DEV_NBD=m
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=131072
CONFIG_DS1682=y
CONFIG_IDE=y
CONFIG_BLK_DEV_IDECS=y
CONFIG_BLK_DEV_SD=y
CONFIG_CHR_DEV_ST=y
CONFIG_BLK_DEV_SR=y
CONFIG_ATA=y
CONFIG_SATA_SIL24=y
# CONFIG_ATA_SFF is not set
CONFIG_NETDEVICES=y
CONFIG_BONDING=m
CONFIG_DUMMY=m
CONFIG_NETCONSOLE=y
CONFIG_TUN=m
CONFIG_GIANFAR=y
CONFIG_PPP=m
CONFIG_PPP_BSDCOMP=m
CONFIG_PPP_DEFLATE=m
CONFIG_PPP_FILTER=y
CONFIG_PPP_MULTILINK=y
CONFIG_PPPOE=m
CONFIG_PPP_ASYNC=m
CONFIG_PPP_SYNC_TTY=m
CONFIG_SLIP=m
CONFIG_SLIP_COMPRESSED=y
CONFIG_SLIP_SMART=y
CONFIG_SLIP_MODE_SLIP6=y
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
# CONFIG_SERIAL_8250_PCI is not set
CONFIG_SERIAL_8250_NR_UARTS=2
CONFIG_SERIAL_8250_RUNTIME_UARTS=2
CONFIG_HW_RANDOM=y
CONFIG_NVRAM=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MPC=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_GE_FPGA=y
CONFIG_SENSORS_LM90=y
CONFIG_SENSORS_LM92=y
CONFIG_WATCHDOG=y
CONFIG_GEF_WDT=y
CONFIG_HID_A4TECH=y
CONFIG_HID_APPLE=y
CONFIG_HID_BELKIN=y
CONFIG_HID_CHERRY=y
CONFIG_HID_CHICONY=y
CONFIG_HID_CYPRESS=y
CONFIG_HID_EZKEY=y
CONFIG_HID_GYRATION=y
CONFIG_HID_LOGITECH=y
CONFIG_HID_MICROSOFT=y
CONFIG_HID_MONTEREY=y
CONFIG_HID_PANTHERLORD=y
CONFIG_HID_PETALYNX=y
CONFIG_HID_SAMSUNG=y
CONFIG_HID_SUNPLUS=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_USB_EHCI_HCD_PPC_OF is not set
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_RTC_CLASS=y
# CONFIG_RTC_INTF_PROC is not set
CONFIG_RTC_DRV_RX8581=y
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_POSIX_ACL=y
CONFIG_EXT3_FS=y
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
CONFIG_EXT3_FS_POSIX_ACL=y
CONFIG_ISO9660_FS=y
CONFIG_JOLIET=y
CONFIG_ZISOFS=y
CONFIG_UDF_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_FAT_DEFAULT_CODEPAGE=850
CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
CONFIG_PROC_KCORE=y
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V4=y
CONFIG_ROOT_NFS=y
CONFIG_CIFS=m
CONFIG_CIFS_XATTR=y
CONFIG_CIFS_POSIX=y
CONFIG_NLS_CODEPAGE_437=m
CONFIG_NLS_CODEPAGE_737=m
CONFIG_NLS_CODEPAGE_775=m
CONFIG_NLS_CODEPAGE_850=m
CONFIG_NLS_CODEPAGE_852=m
CONFIG_NLS_CODEPAGE_855=m
CONFIG_NLS_CODEPAGE_857=m
CONFIG_NLS_CODEPAGE_860=m
CONFIG_NLS_CODEPAGE_861=m
CONFIG_NLS_CODEPAGE_862=m
CONFIG_NLS_CODEPAGE_863=m
CONFIG_NLS_CODEPAGE_864=m
CONFIG_NLS_CODEPAGE_865=m
CONFIG_NLS_CODEPAGE_866=m
CONFIG_NLS_CODEPAGE_869=m
CONFIG_NLS_CODEPAGE_936=m
CONFIG_NLS_CODEPAGE_950=m
CONFIG_NLS_CODEPAGE_932=m
CONFIG_NLS_CODEPAGE_949=m
CONFIG_NLS_CODEPAGE_874=m
CONFIG_NLS_ISO8859_8=m
CONFIG_NLS_CODEPAGE_1250=m
CONFIG_NLS_CODEPAGE_1251=m
CONFIG_NLS_ASCII=m
CONFIG_NLS_ISO8859_1=m
CONFIG_NLS_ISO8859_2=m
CONFIG_NLS_ISO8859_3=m
CONFIG_NLS_ISO8859_4=m
CONFIG_NLS_ISO8859_5=m
CONFIG_NLS_ISO8859_6=m
CONFIG_NLS_ISO8859_7=m
CONFIG_NLS_ISO8859_9=m
CONFIG_NLS_ISO8859_13=m
CONFIG_NLS_ISO8859_14=m
CONFIG_NLS_ISO8859_15=m
CONFIG_NLS_KOI8_R=m
CONFIG_NLS_KOI8_U=m
CONFIG_NLS_UTF8=m
CONFIG_CRC_CCITT=y
CONFIG_CRC_T10DIF=y
CONFIG_LIBCRC32C=y
CONFIG_MAGIC_SYSRQ=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set
# CONFIG_CRYPTO_HW is not set
arch/powerpc/configs/86xx/gef_sbc610_defconfig 已删除 100644 → 0
浏览文件 @ d8c0282f
CONFIG_SMP=y
CONFIG_NR_CPUS=2
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BSD_PROCESS_ACCT_V3=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_PPC_CHRP is not set
# CONFIG_PPC_PMAC is not set
CONFIG_PPC_86xx=y
CONFIG_GEF_SBC610=y
CONFIG_HIGHMEM=y
CONFIG_HZ_1000=y
CONFIG_PREEMPT=y
CONFIG_BINFMT_MISC=m
CONFIG_PCI=y
CONFIG_PCIEPORTBUS=y
# CONFIG_PCIEASPM is not set
CONFIG_PCI_DEBUG=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_XFRM_USER=m
CONFIG_NET_KEY=m
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
CONFIG_IP_MULTIPLE_TABLES=y
CONFIG_IP_ROUTE_MULTIPATH=y
CONFIG_IP_ROUTE_VERBOSE=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y
CONFIG_NET_IPIP=m
CONFIG_IP_MROUTE=y
CONFIG_IP_PIMSM_V1=y
CONFIG_IP_PIMSM_V2=y
CONFIG_SYN_COOKIES=y
CONFIG_INET_AH=m
CONFIG_INET_ESP=m
CONFIG_INET_IPCOMP=m
# CONFIG_INET_LRO is not set
CONFIG_INET6_AH=m
CONFIG_INET6_ESP=m
CONFIG_INET6_IPCOMP=m
CONFIG_IPV6_TUNNEL=m
CONFIG_NETFILTER=y
# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
CONFIG_IP_NF_IPTABLES=m
CONFIG_IP_NF_MATCH_ECN=m
CONFIG_IP_NF_MATCH_TTL=m
CONFIG_IP_NF_FILTER=m
CONFIG_IP_NF_TARGET_REJECT=m
CONFIG_IP_NF_MANGLE=m
CONFIG_IP_NF_TARGET_ECN=m
CONFIG_IP_NF_RAW=m
CONFIG_IP_NF_ARPTABLES=m
CONFIG_IP_NF_ARPFILTER=m
CONFIG_IP_NF_ARP_MANGLE=m
CONFIG_IP6_NF_IPTABLES=m
CONFIG_IP6_NF_MATCH_EUI64=m
CONFIG_IP6_NF_MATCH_FRAG=m
CONFIG_IP6_NF_MATCH_OPTS=m
CONFIG_IP6_NF_MATCH_HL=m
CONFIG_IP6_NF_MATCH_IPV6HEADER=m
CONFIG_IP6_NF_MATCH_RT=m
CONFIG_IP6_NF_FILTER=m
CONFIG_IP6_NF_MANGLE=m
CONFIG_IP6_NF_RAW=m
CONFIG_IP_SCTP=m
CONFIG_TIPC=m
CONFIG_ATM=m
CONFIG_ATM_CLIP=m
CONFIG_ATM_LANE=m
CONFIG_ATM_MPOA=m
CONFIG_ATM_BR2684=m
CONFIG_BRIDGE=m
CONFIG_VLAN_8021Q=m
CONFIG_NET_SCHED=y
CONFIG_NET_SCH_CBQ=m
CONFIG_NET_SCH_HTB=m
CONFIG_NET_SCH_HFSC=m
CONFIG_NET_SCH_ATM=m
CONFIG_NET_SCH_PRIO=m
CONFIG_NET_SCH_RED=m
CONFIG_NET_SCH_SFQ=m
CONFIG_NET_SCH_TEQL=m
CONFIG_NET_SCH_TBF=m
CONFIG_NET_SCH_GRED=m
CONFIG_NET_SCH_DSMARK=m
CONFIG_NET_SCH_NETEM=m
CONFIG_NET_CLS_TCINDEX=m
CONFIG_NET_CLS_ROUTE4=m
CONFIG_NET_CLS_FW=m
CONFIG_NET_CLS_U32=m
CONFIG_NET_CLS_RSVP=m
CONFIG_NET_CLS_RSVP6=m
CONFIG_NET_PKTGEN=m
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
# CONFIG_FW_LOADER is not set
CONFIG_MTD=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP_OF=y
CONFIG_BLK_DEV_LOOP=m
CONFIG_BLK_DEV_CRYPTOLOOP=m
CONFIG_BLK_DEV_NBD=m
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=131072
CONFIG_DS1682=y
CONFIG_BLK_DEV_SD=y
CONFIG_CHR_DEV_ST=y
CONFIG_BLK_DEV_SR=y
CONFIG_ATA=y
CONFIG_SATA_SIL=y
CONFIG_NETDEVICES=y
CONFIG_BONDING=m
CONFIG_DUMMY=m
CONFIG_NETCONSOLE=y
CONFIG_TUN=m
CONFIG_GIANFAR=y
CONFIG_PPP=m
CONFIG_PPP_BSDCOMP=m
CONFIG_PPP_DEFLATE=m
CONFIG_PPP_FILTER=y
CONFIG_PPP_MULTILINK=y
CONFIG_PPPOATM=m
CONFIG_PPPOE=m
CONFIG_PPP_ASYNC=m
CONFIG_PPP_SYNC_TTY=m
CONFIG_SLIP=m
CONFIG_SLIP_COMPRESSED=y
CONFIG_SLIP_SMART=y
CONFIG_SLIP_MODE_SLIP6=y
CONFIG_INPUT_FF_MEMLESS=m
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
# CONFIG_SERIAL_8250_PCI is not set
CONFIG_SERIAL_8250_NR_UARTS=2
CONFIG_SERIAL_8250_RUNTIME_UARTS=2
CONFIG_HW_RANDOM=y
CONFIG_NVRAM=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MPC=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_GE_FPGA=y
CONFIG_SENSORS_LM90=y
CONFIG_SENSORS_LM92=y
CONFIG_WATCHDOG=y
CONFIG_GEF_WDT=y
CONFIG_HID_A4TECH=y
CONFIG_HID_APPLE=y
CONFIG_HID_BELKIN=y
CONFIG_HID_CHERRY=y
CONFIG_HID_CHICONY=y
CONFIG_HID_CYPRESS=y
CONFIG_HID_EZKEY=y
CONFIG_HID_GYRATION=y
CONFIG_HID_LOGITECH=y
CONFIG_HID_MICROSOFT=y
CONFIG_HID_MONTEREY=y
CONFIG_HID_PANTHERLORD=y
CONFIG_HID_PETALYNX=y
CONFIG_HID_SAMSUNG=y
CONFIG_HID_SUNPLUS=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_USB_EHCI_HCD_PPC_OF is not set
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_RTC_CLASS=y
# CONFIG_RTC_INTF_PROC is not set
CONFIG_RTC_DRV_RX8581=y
CONFIG_STAGING=y
CONFIG_VME_BUS=y
CONFIG_VME_TSI148=y
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_POSIX_ACL=y
CONFIG_EXT3_FS=y
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
CONFIG_EXT3_FS_POSIX_ACL=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_PROC_KCORE=y
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V4=y
CONFIG_ROOT_NFS=y
CONFIG_CIFS=m
CONFIG_CIFS_XATTR=y
CONFIG_CIFS_POSIX=y
CONFIG_NLS_CODEPAGE_437=m
CONFIG_NLS_CODEPAGE_737=m
CONFIG_NLS_CODEPAGE_775=m
CONFIG_NLS_CODEPAGE_850=m
CONFIG_NLS_CODEPAGE_852=m
CONFIG_NLS_CODEPAGE_855=m
CONFIG_NLS_CODEPAGE_857=m
CONFIG_NLS_CODEPAGE_860=m
CONFIG_NLS_CODEPAGE_861=m
CONFIG_NLS_CODEPAGE_862=m
CONFIG_NLS_CODEPAGE_863=m
CONFIG_NLS_CODEPAGE_864=m
CONFIG_NLS_CODEPAGE_865=m
CONFIG_NLS_CODEPAGE_866=m
CONFIG_NLS_CODEPAGE_869=m
CONFIG_NLS_CODEPAGE_936=m
CONFIG_NLS_CODEPAGE_950=m
CONFIG_NLS_CODEPAGE_932=m
CONFIG_NLS_CODEPAGE_949=m
CONFIG_NLS_CODEPAGE_874=m
CONFIG_NLS_ISO8859_8=m
CONFIG_NLS_CODEPAGE_1250=m
CONFIG_NLS_CODEPAGE_1251=m
CONFIG_NLS_ASCII=m
CONFIG_NLS_ISO8859_1=m
CONFIG_NLS_ISO8859_2=m
CONFIG_NLS_ISO8859_3=m
CONFIG_NLS_ISO8859_4=m
CONFIG_NLS_ISO8859_5=m
CONFIG_NLS_ISO8859_6=m
CONFIG_NLS_ISO8859_7=m
CONFIG_NLS_ISO8859_9=m
CONFIG_NLS_ISO8859_13=m
CONFIG_NLS_ISO8859_14=m
CONFIG_NLS_ISO8859_15=m
CONFIG_NLS_KOI8_R=m
CONFIG_NLS_KOI8_U=m
CONFIG_NLS_UTF8=m
CONFIG_DEBUG_INFO=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DETECT_HUNG_TASK=y
# CONFIG_DEBUG_BUGVERBOSE is not set
CONFIG_SECURITY=y
CONFIG_SECURITY_NETWORK=y
CONFIG_CRYPTO_NULL=m
CONFIG_CRYPTO_TEST=m
CONFIG_CRYPTO_PCBC=m
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_MICHAEL_MIC=m
CONFIG_CRYPTO_SHA512=m
CONFIG_CRYPTO_WP512=m
CONFIG_CRYPTO_ANUBIS=m
CONFIG_CRYPTO_BLOWFISH=m
CONFIG_CRYPTO_CAST5=m
CONFIG_CRYPTO_CAST6=m
CONFIG_CRYPTO_KHAZAD=m
CONFIG_CRYPTO_SERPENT=m
CONFIG_CRYPTO_TEA=m
CONFIG_CRYPTO_TWOFISH=m
# CONFIG_CRYPTO_ANSI_CPRNG is not set
# CONFIG_CRYPTO_HW is not set
arch/powerpc/configs/86xx/mpc8610_hpcd_defconfig 已删除 100644 → 0
浏览文件 @ d8c0282f
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
# CONFIG_ELF_CORE is not set
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_PARTITION_ADVANCED=y
CONFIG_LDM_PARTITION=y
# CONFIG_IOSCHED_CFQ is not set
# CONFIG_PPC_CHRP is not set
# CONFIG_PPC_PMAC is not set
CONFIG_PPC_86xx=y
CONFIG_MPC8610_HPCD=y
CONFIG_HIGHMEM=y
CONFIG_HZ_1000=y
CONFIG_FORCE_MAX_ZONEORDER=12
# CONFIG_SECCOMP is not set
CONFIG_PCI=y
CONFIG_PCIEPORTBUS=y
# CONFIG_PCIEASPM is not set
CONFIG_PCI_DEBUG=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_XFRM_USER=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y
# CONFIG_INET_LRO is not set
CONFIG_IPV6=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_FSL_ELBC=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=131072
CONFIG_IDE=y
CONFIG_BLK_DEV_SD=y
CONFIG_CHR_DEV_SG=y
CONFIG_ATA=y
CONFIG_SATA_AHCI=y
CONFIG_PATA_ALI=y
CONFIG_NETDEVICES=y
CONFIG_DUMMY=y
CONFIG_NET_TULIP=y
CONFIG_ULI526X=y
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
CONFIG_SERIO_LIBPS2=y
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=2
CONFIG_SERIAL_8250_RUNTIME_UARTS=2
CONFIG_SERIAL_8250_EXTENDED=y
CONFIG_SERIAL_8250_MANY_PORTS=y
CONFIG_SERIAL_8250_SHARE_IRQ=y
CONFIG_SERIAL_8250_DETECT_IRQ=y
CONFIG_SERIAL_8250_RSA=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_MPC=y
# CONFIG_HWMON is not set
CONFIG_FB=y
CONFIG_FB_FSL_DIU=y
CONFIG_VGACON_SOFT_SCROLLBACK=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_SOUND=y
CONFIG_SND=y
CONFIG_SND_MIXER_OSS=y
CONFIG_SND_PCM_OSS=y
# CONFIG_SND_SUPPORT_OLD_API is not set
CONFIG_SND_SOC=y
CONFIG_SND_POWERPC_SOC=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_CMOS=y
CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
# CONFIG_DNOTIFY is not set
CONFIG_PROC_KCORE=y
CONFIG_TMPFS=y
CONFIG_NFS_FS=y
CONFIG_ROOT_NFS=y
CONFIG_NFSD=y
CONFIG_NLS=y
CONFIG_CRC_T10DIF=y
CONFIG_FONTS=y
CONFIG_FONT_8x8=y
CONFIG_FONT_8x16=y
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_SHIRQ=y
CONFIG_DETECT_HUNG_TASK=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set
arch/powerpc/configs/86xx/sbc8641d_defconfig 已删除 100644 → 0
浏览文件 @ d8c0282f
CONFIG_SMP=y
CONFIG_NR_CPUS=2
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BSD_PROCESS_ACCT_V3=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_PPC_CHRP is not set
# CONFIG_PPC_PMAC is not set
CONFIG_PPC_86xx=y
CONFIG_SBC8641D=y
CONFIG_PREEMPT=y
CONFIG_BINFMT_MISC=m
CONFIG_PCI=y
CONFIG_PCIEPORTBUS=y
# CONFIG_PCIEASPM is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_XFRM_USER=m
CONFIG_NET_KEY=m
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
CONFIG_IP_MULTIPLE_TABLES=y
CONFIG_IP_ROUTE_MULTIPATH=y
CONFIG_IP_ROUTE_VERBOSE=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y
CONFIG_NET_IPIP=m
CONFIG_IP_MROUTE=y
CONFIG_IP_PIMSM_V1=y
CONFIG_IP_PIMSM_V2=y
CONFIG_SYN_COOKIES=y
CONFIG_INET_AH=m
CONFIG_INET_ESP=m
CONFIG_INET_IPCOMP=m
# CONFIG_INET_LRO is not set
CONFIG_INET6_AH=m
CONFIG_INET6_ESP=m
CONFIG_INET6_IPCOMP=m
CONFIG_IPV6_TUNNEL=m
CONFIG_NETFILTER=y
# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
CONFIG_IP_NF_IPTABLES=m
CONFIG_IP_NF_MATCH_ECN=m
CONFIG_IP_NF_MATCH_TTL=m
CONFIG_IP_NF_FILTER=m
CONFIG_IP_NF_TARGET_REJECT=m
CONFIG_IP_NF_MANGLE=m
CONFIG_IP_NF_TARGET_ECN=m
CONFIG_IP_NF_RAW=m
CONFIG_IP_NF_ARPTABLES=m
CONFIG_IP_NF_ARPFILTER=m
CONFIG_IP_NF_ARP_MANGLE=m
CONFIG_IP6_NF_IPTABLES=m
CONFIG_IP6_NF_MATCH_EUI64=m
CONFIG_IP6_NF_MATCH_FRAG=m
CONFIG_IP6_NF_MATCH_OPTS=m
CONFIG_IP6_NF_MATCH_HL=m
CONFIG_IP6_NF_MATCH_IPV6HEADER=m
CONFIG_IP6_NF_MATCH_RT=m
CONFIG_IP6_NF_FILTER=m
CONFIG_IP6_NF_MANGLE=m
CONFIG_IP6_NF_RAW=m
CONFIG_IP_SCTP=m
CONFIG_TIPC=m
CONFIG_ATM=m
CONFIG_ATM_CLIP=m
CONFIG_ATM_LANE=m
CONFIG_ATM_MPOA=m
CONFIG_ATM_BR2684=m
CONFIG_BRIDGE=m
CONFIG_VLAN_8021Q=m
CONFIG_NET_SCHED=y
CONFIG_NET_SCH_CBQ=m
CONFIG_NET_SCH_HTB=m
CONFIG_NET_SCH_HFSC=m
CONFIG_NET_SCH_ATM=m
CONFIG_NET_SCH_PRIO=m
CONFIG_NET_SCH_RED=m
CONFIG_NET_SCH_SFQ=m
CONFIG_NET_SCH_TEQL=m
CONFIG_NET_SCH_TBF=m
CONFIG_NET_SCH_GRED=m
CONFIG_NET_SCH_DSMARK=m
CONFIG_NET_SCH_NETEM=m
CONFIG_NET_CLS_TCINDEX=m
CONFIG_NET_CLS_ROUTE4=m
CONFIG_NET_CLS_FW=m
CONFIG_NET_CLS_U32=m
CONFIG_NET_CLS_RSVP=m
CONFIG_NET_CLS_RSVP6=m
CONFIG_NET_PKTGEN=m
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
# CONFIG_FW_LOADER is not set
CONFIG_MTD=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_LE_BYTE_SWAP=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_PHYSMAP_OF=y
CONFIG_BLK_DEV_LOOP=m
CONFIG_BLK_DEV_CRYPTOLOOP=m
CONFIG_BLK_DEV_NBD=m
CONFIG_BLK_DEV_RAM=y
CONFIG_MD=y
CONFIG_BLK_DEV_MD=y
CONFIG_MD_LINEAR=y
CONFIG_MD_RAID0=y
CONFIG_MD_RAID1=y
CONFIG_MD_RAID10=y
CONFIG_MD_MULTIPATH=y
CONFIG_MD_FAULTY=y
CONFIG_BLK_DEV_DM=y
CONFIG_DM_CRYPT=y
CONFIG_DM_SNAPSHOT=y
CONFIG_DM_MIRROR=y
CONFIG_DM_ZERO=y
CONFIG_NETDEVICES=y
CONFIG_BONDING=m
CONFIG_DUMMY=m
CONFIG_NETCONSOLE=y
CONFIG_TUN=m
CONFIG_GIANFAR=y
CONFIG_BROADCOM_PHY=y
CONFIG_PPP=m
CONFIG_PPP_BSDCOMP=m
CONFIG_PPP_DEFLATE=m
CONFIG_PPP_FILTER=y
CONFIG_PPP_MULTILINK=y
CONFIG_PPPOATM=m
CONFIG_PPPOE=m
CONFIG_PPP_ASYNC=m
CONFIG_PPP_SYNC_TTY=m
CONFIG_SLIP=m
CONFIG_SLIP_COMPRESSED=y
CONFIG_SLIP_SMART=y
CONFIG_SLIP_MODE_SLIP6=y
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
# CONFIG_SERIAL_8250_PCI is not set
CONFIG_SERIAL_8250_NR_UARTS=2
CONFIG_SERIAL_8250_RUNTIME_UARTS=2
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MPC=y
CONFIG_WATCHDOG=y
CONFIG_SOFT_WATCHDOG=m
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_POSIX_ACL=y
CONFIG_EXT3_FS=y
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
CONFIG_EXT3_FS_POSIX_ACL=y
CONFIG_REISERFS_FS=m
CONFIG_REISERFS_FS_XATTR=y
CONFIG_REISERFS_FS_POSIX_ACL=y
CONFIG_AUTOFS4_FS=m
CONFIG_PROC_KCORE=y
CONFIG_TMPFS=y
CONFIG_MINIX_FS=m
CONFIG_ROMFS_FS=m
CONFIG_NFS_FS=y
CONFIG_NFS_V4=y
CONFIG_ROOT_NFS=y
CONFIG_CIFS=m
CONFIG_CIFS_XATTR=y
CONFIG_CIFS_POSIX=y
CONFIG_NLS_CODEPAGE_437=m
CONFIG_NLS_CODEPAGE_737=m
CONFIG_NLS_CODEPAGE_775=m
CONFIG_NLS_CODEPAGE_850=m
CONFIG_NLS_CODEPAGE_852=m
CONFIG_NLS_CODEPAGE_855=m
CONFIG_NLS_CODEPAGE_857=m
CONFIG_NLS_CODEPAGE_860=m
CONFIG_NLS_CODEPAGE_861=m
CONFIG_NLS_CODEPAGE_862=m
CONFIG_NLS_CODEPAGE_863=m
CONFIG_NLS_CODEPAGE_864=m
CONFIG_NLS_CODEPAGE_865=m
CONFIG_NLS_CODEPAGE_866=m
CONFIG_NLS_CODEPAGE_869=m
CONFIG_NLS_CODEPAGE_936=m
CONFIG_NLS_CODEPAGE_950=m
CONFIG_NLS_CODEPAGE_932=m
CONFIG_NLS_CODEPAGE_949=m
CONFIG_NLS_CODEPAGE_874=m
CONFIG_NLS_ISO8859_8=m
CONFIG_NLS_CODEPAGE_1250=m
CONFIG_NLS_CODEPAGE_1251=m
CONFIG_NLS_ASCII=m
CONFIG_NLS_ISO8859_1=m
CONFIG_NLS_ISO8859_2=m
CONFIG_NLS_ISO8859_3=m
CONFIG_NLS_ISO8859_4=m
CONFIG_NLS_ISO8859_5=m
CONFIG_NLS_ISO8859_6=m
CONFIG_NLS_ISO8859_7=m
CONFIG_NLS_ISO8859_9=m
CONFIG_NLS_ISO8859_13=m
CONFIG_NLS_ISO8859_14=m
CONFIG_NLS_ISO8859_15=m
CONFIG_NLS_KOI8_R=m
CONFIG_NLS_KOI8_U=m
CONFIG_NLS_UTF8=m
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_FS=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DETECT_HUNG_TASK=y
# CONFIG_DEBUG_BUGVERBOSE is not set
CONFIG_SECURITY=y
CONFIG_SECURITY_NETWORK=y
CONFIG_CRYPTO_NULL=m
CONFIG_CRYPTO_TEST=m
CONFIG_CRYPTO_PCBC=m
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_MICHAEL_MIC=m
CONFIG_CRYPTO_SHA512=m
CONFIG_CRYPTO_WP512=m
CONFIG_CRYPTO_ANUBIS=m
CONFIG_CRYPTO_BLOWFISH=m
CONFIG_CRYPTO_CAST5=m
CONFIG_CRYPTO_CAST6=m
CONFIG_CRYPTO_KHAZAD=m
CONFIG_CRYPTO_SERPENT=m
CONFIG_CRYPTO_TEA=m
CONFIG_CRYPTO_TWOFISH=m
# CONFIG_CRYPTO_ANSI_CPRNG is not set
arch/powerpc/configs/mpc86xx_basic_defconfig 0 → 100644
浏览文件 @ a1b53446
CONFIG_HIGHMEM=y
CONFIG_KEXEC=y
CONFIG_PPC_86xx=y
CONFIG_PROC_KCORE=y
CONFIG_GEF_PPC9A=y
CONFIG_GEF_SBC310=y
CONFIG_GEF_SBC610=y
CONFIG_MPC8610_HPCD=y
CONFIG_MPC8641_HPCN=y
CONFIG_SBC8641D=y
arch/powerpc/configs/mpc86xx_defconfig 已删除 100644 → 0
浏览文件 @ d8c0282f
CONFIG_SMP=y
CONFIG_NR_CPUS=2
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_AUDIT=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
CONFIG_KALLSYMS_ALL=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_MODVERSIONS=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_PARTITION_ADVANCED=y
CONFIG_MAC_PARTITION=y
# CONFIG_PPC_CHRP is not set
# CONFIG_PPC_PMAC is not set
CONFIG_PPC_86xx=y
CONFIG_MPC8641_HPCN=y
CONFIG_SBC8641D=y
CONFIG_MPC8610_HPCD=y
CONFIG_GEF_SBC610=y
CONFIG_HIGHMEM=y
CONFIG_HZ_1000=y
CONFIG_BINFMT_MISC=m
CONFIG_PCI=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_XFRM_USER=y
CONFIG_NET_KEY=m
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
CONFIG_IP_MULTIPLE_TABLES=y
CONFIG_IP_ROUTE_MULTIPATH=y
CONFIG_IP_ROUTE_VERBOSE=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y
CONFIG_NET_IPIP=y
CONFIG_IP_MROUTE=y
CONFIG_IP_PIMSM_V1=y
CONFIG_IP_PIMSM_V2=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
CONFIG_IPV6=y
CONFIG_IP_SCTP=m
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_NBD=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=131072
CONFIG_EEPROM_LEGACY=y
CONFIG_BLK_DEV_SD=y
CONFIG_CHR_DEV_ST=y
CONFIG_BLK_DEV_SR=y
CONFIG_CHR_DEV_SG=y
CONFIG_SCSI_LOGGING=y
CONFIG_ATA=y
CONFIG_SATA_AHCI=y
CONFIG_PATA_ALI=y
CONFIG_NETDEVICES=y
CONFIG_DUMMY=y
CONFIG_GIANFAR=y
CONFIG_VITESSE_PHY=y
CONFIG_INPUT_FF_MEMLESS=m
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
CONFIG_SERIO_LIBPS2=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=2
CONFIG_SERIAL_8250_RUNTIME_UARTS=2
CONFIG_SERIAL_8250_EXTENDED=y
CONFIG_SERIAL_8250_MANY_PORTS=y
CONFIG_SERIAL_8250_SHARE_IRQ=y
CONFIG_SERIAL_8250_DETECT_IRQ=y
CONFIG_SERIAL_8250_RSA=y
# CONFIG_HW_RANDOM is not set
CONFIG_NVRAM=y
CONFIG_I2C=y
CONFIG_I2C_MPC=y
# CONFIG_HWMON is not set
CONFIG_SOUND=y
CONFIG_SND=y
CONFIG_SND_MIXER_OSS=y
CONFIG_SND_PCM_OSS=y
# CONFIG_SND_SUPPORT_OLD_API is not set
CONFIG_SND_INTEL8X0=y
CONFIG_HID_A4TECH=y
CONFIG_HID_APPLE=y
CONFIG_HID_BELKIN=y
CONFIG_HID_CHERRY=y
CONFIG_HID_CHICONY=y
CONFIG_HID_CYPRESS=y
CONFIG_HID_EZKEY=y
CONFIG_HID_GYRATION=y
CONFIG_HID_LOGITECH=y
CONFIG_HID_MICROSOFT=y
CONFIG_HID_MONTEREY=y
CONFIG_HID_PANTHERLORD=y
CONFIG_HID_PETALYNX=y
CONFIG_HID_SAMSUNG=y
CONFIG_HID_SUNPLUS=y
CONFIG_USB=y
CONFIG_USB_MON=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_HCD_PPC_OF_BE=y
CONFIG_USB_OHCI_HCD_PPC_OF_LE=y
CONFIG_USB_STORAGE=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_CMOS=y
CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
CONFIG_ISO9660_FS=m
CONFIG_JOLIET=y
CONFIG_ZISOFS=y
CONFIG_UDF_FS=m
CONFIG_MSDOS_FS=m
CONFIG_VFAT_FS=y
CONFIG_NTFS_FS=y
CONFIG_PROC_KCORE=y
CONFIG_TMPFS=y
CONFIG_ADFS_FS=m
CONFIG_AFFS_FS=m
CONFIG_HFS_FS=m
CONFIG_HFSPLUS_FS=m
CONFIG_BEFS_FS=m
CONFIG_BFS_FS=m
CONFIG_EFS_FS=m
CONFIG_CRAMFS=y
CONFIG_VXFS_FS=m
CONFIG_HPFS_FS=m
CONFIG_QNX4FS_FS=m
CONFIG_SYSV_FS=m
CONFIG_UFS_FS=m
CONFIG_NFS_FS=y
CONFIG_NFS_V4=y
CONFIG_ROOT_NFS=y
CONFIG_NFSD=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_850=y
CONFIG_NLS_ISO8859_1=y
CONFIG_CRC_T10DIF=y
CONFIG_DEBUG_INFO=y
CONFIG_DETECT_HUNG_TASK=y
CONFIG_CRYPTO_PCBC=m
CONFIG_CRYPTO_HMAC=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set
arch/powerpc/include/asm/cache.h
浏览文件 @ a1b53446
...@@ -69,6 +69,25 @@ extern void _set_L3CR(unsigned long); ...@@ -69,6 +69,25 @@ extern void _set_L3CR(unsigned long);
#define _set_L3CR(val) do { } while(0) #define _set_L3CR(val) do { } while(0)
#endif #endif
static inline void dcbz(void *addr)
{
__asm__ __volatile__ ("dcbz 0, %0" : : "r"(addr) : "memory");
}
static inline void dcbi(void *addr)
{
__asm__ __volatile__ ("dcbi 0, %0" : : "r"(addr) : "memory");
}
static inline void dcbf(void *addr)
{
__asm__ __volatile__ ("dcbf 0, %0" : : "r"(addr) : "memory");
}
static inline void dcbst(void *addr)
{
__asm__ __volatile__ ("dcbst 0, %0" : : "r"(addr) : "memory");
}
#endif /* !__ASSEMBLY__ */ #endif /* !__ASSEMBLY__ */
#endif /* __KERNEL__ */ #endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_CACHE_H */ #endif /* _ASM_POWERPC_CACHE_H */
arch/powerpc/include/asm/cacheflush.h
浏览文件 @ a1b53446
...@@ -30,8 +30,6 @@ extern void flush_dcache_page(struct page *page); ...@@ -30,8 +30,6 @@ extern void flush_dcache_page(struct page *page);
#define flush_dcache_mmap_lock(mapping) do { } while (0) #define flush_dcache_mmap_lock(mapping) do { } while (0)
#define flush_dcache_mmap_unlock(mapping) do { } while (0) #define flush_dcache_mmap_unlock(mapping) do { } while (0)
extern void __flush_disable_L1(void);
extern void flush_icache_range(unsigned long, unsigned long); extern void flush_icache_range(unsigned long, unsigned long);
extern void flush_icache_user_range(struct vm_area_struct *vma, extern void flush_icache_user_range(struct vm_area_struct *vma,
struct page *page, unsigned long addr, struct page *page, unsigned long addr,
...@@ -47,12 +45,58 @@ static inline void __flush_dcache_icache_phys(unsigned long physaddr) ...@@ -47,12 +45,58 @@ static inline void __flush_dcache_icache_phys(unsigned long physaddr)
} }
#endif #endif
extern void flush_dcache_range(unsigned long start, unsigned long stop);
#ifdef CONFIG_PPC32 #ifdef CONFIG_PPC32
extern void clean_dcache_range(unsigned long start, unsigned long stop); /*
extern void invalidate_dcache_range(unsigned long start, unsigned long stop); * Write any modified data cache blocks out to memory and invalidate them.
* Does not invalidate the corresponding instruction cache blocks.
*/
static inline void flush_dcache_range(unsigned long start, unsigned long stop)
{
void *addr = (void *)(start & ~(L1_CACHE_BYTES - 1));
unsigned long size = stop - (unsigned long)addr + (L1_CACHE_BYTES - 1);
unsigned long i;
for (i = 0; i < size >> L1_CACHE_SHIFT; i++, addr += L1_CACHE_BYTES)
dcbf(addr);
mb(); /* sync */
}
/*
* Write any modified data cache blocks out to memory.
* Does not invalidate the corresponding cache lines (especially for
* any corresponding instruction cache).
*/
static inline void clean_dcache_range(unsigned long start, unsigned long stop)
{
void *addr = (void *)(start & ~(L1_CACHE_BYTES - 1));
unsigned long size = stop - (unsigned long)addr + (L1_CACHE_BYTES - 1);
unsigned long i;
for (i = 0; i < size >> L1_CACHE_SHIFT; i++, addr += L1_CACHE_BYTES)
dcbst(addr);
mb(); /* sync */
}
/*
* Like above, but invalidate the D-cache. This is used by the 8xx
* to invalidate the cache so the PPC core doesn't get stale data
* from the CPM (no cache snooping here :-).
*/
static inline void invalidate_dcache_range(unsigned long start,
unsigned long stop)
{
void *addr = (void *)(start & ~(L1_CACHE_BYTES - 1));
unsigned long size = stop - (unsigned long)addr + (L1_CACHE_BYTES - 1);
unsigned long i;
for (i = 0; i < size >> L1_CACHE_SHIFT; i++, addr += L1_CACHE_BYTES)
dcbi(addr);
mb(); /* sync */
}
#endif /* CONFIG_PPC32 */ #endif /* CONFIG_PPC32 */
#ifdef CONFIG_PPC64 #ifdef CONFIG_PPC64
extern void flush_dcache_range(unsigned long start, unsigned long stop);
extern void flush_inval_dcache_range(unsigned long start, unsigned long stop); extern void flush_inval_dcache_range(unsigned long start, unsigned long stop);
extern void flush_dcache_phys_range(unsigned long start, unsigned long stop); extern void flush_dcache_phys_range(unsigned long start, unsigned long stop);
#endif #endif
......
arch/powerpc/include/asm/checksum.h
浏览文件 @ a1b53446
...@@ -9,30 +9,9 @@ ...@@ -9,30 +9,9 @@
* 2 of the License, or (at your option) any later version. * 2 of the License, or (at your option) any later version.
*/ */
/*
* This is a version of ip_compute_csum() optimized for IP headers,
* which always checksum on 4 octet boundaries. ihl is the number
* of 32-bit words and is always >= 5.
*/
#ifdef CONFIG_GENERIC_CSUM #ifdef CONFIG_GENERIC_CSUM
#include <asm-generic/checksum.h> #include <asm-generic/checksum.h>
#else #else
extern __sum16 ip_fast_csum(const void *iph, unsigned int ihl);
/*
* computes the checksum of a memory block at buff, length len,
* and adds in "sum" (32-bit)
*
* returns a 32-bit number suitable for feeding into itself
* or csum_tcpudp_magic
*
* this function must be called with even lengths, except
* for the last fragment, which may be odd
*
* it's best to have buff aligned on a 32-bit boundary
*/
extern __wsum csum_partial(const void *buff, int len, __wsum sum);
/* /*
* Computes the checksum of a memory block at src, length len, * Computes the checksum of a memory block at src, length len,
* and adds in "sum" (32-bit), while copying the block to dst. * and adds in "sum" (32-bit), while copying the block to dst.
...@@ -47,21 +26,12 @@ extern __wsum csum_partial_copy_generic(const void *src, void *dst, ...@@ -47,21 +26,12 @@ extern __wsum csum_partial_copy_generic(const void *src, void *dst,
int len, __wsum sum, int len, __wsum sum,
int *src_err, int *dst_err); int *src_err, int *dst_err);
#ifdef __powerpc64__
#define _HAVE_ARCH_COPY_AND_CSUM_FROM_USER #define _HAVE_ARCH_COPY_AND_CSUM_FROM_USER
extern __wsum csum_and_copy_from_user(const void __user *src, void *dst, extern __wsum csum_and_copy_from_user(const void __user *src, void *dst,
int len, __wsum sum, int *err_ptr); int len, __wsum sum, int *err_ptr);
#define HAVE_CSUM_COPY_USER #define HAVE_CSUM_COPY_USER
extern __wsum csum_and_copy_to_user(const void *src, void __user *dst, extern __wsum csum_and_copy_to_user(const void *src, void __user *dst,
int len, __wsum sum, int *err_ptr); int len, __wsum sum, int *err_ptr);
#else
/*
* the same as csum_partial, but copies from src to dst while it
* checksums.
*/
#define csum_partial_copy_from_user(src, dst, len, sum, errp) \
csum_partial_copy_generic((__force const void *)(src), (dst), (len), (sum), (errp), NULL)
#endif
#define csum_partial_copy_nocheck(src, dst, len, sum) \ #define csum_partial_copy_nocheck(src, dst, len, sum) \
csum_partial_copy_generic((src), (dst), (len), (sum), NULL, NULL) csum_partial_copy_generic((src), (dst), (len), (sum), NULL, NULL)
...@@ -83,15 +53,6 @@ static inline __sum16 csum_fold(__wsum sum) ...@@ -83,15 +53,6 @@ static inline __sum16 csum_fold(__wsum sum)
return (__force __sum16)(~((__force u32)sum + tmp) >> 16); return (__force __sum16)(~((__force u32)sum + tmp) >> 16);
} }
/*
* this routine is used for miscellaneous IP-like checksums, mainly
* in icmp.c
*/
static inline __sum16 ip_compute_csum(const void *buff, int len)
{
return csum_fold(csum_partial(buff, len, 0));
}
static inline __wsum csum_tcpudp_nofold(__be32 saddr, __be32 daddr, static inline __wsum csum_tcpudp_nofold(__be32 saddr, __be32 daddr,
unsigned short len, unsigned short len,
unsigned short proto, unsigned short proto,
...@@ -135,17 +96,117 @@ static inline __wsum csum_add(__wsum csum, __wsum addend) ...@@ -135,17 +96,117 @@ static inline __wsum csum_add(__wsum csum, __wsum addend)
{ {
#ifdef __powerpc64__ #ifdef __powerpc64__
u64 res = (__force u64)csum; u64 res = (__force u64)csum;
#endif
if (__builtin_constant_p(csum) && csum == 0)
return addend;
if (__builtin_constant_p(addend) && addend == 0)
return csum;
#ifdef __powerpc64__
res += (__force u64)addend; res += (__force u64)addend;
return (__force __wsum)((u32)res + (res >> 32)); return (__force __wsum)((u32)res + (res >> 32));
#else #else
asm("addc %0,%0,%1;" asm("addc %0,%0,%1;"
"addze %0,%0;" "addze %0,%0;"
: "+r" (csum) : "r" (addend)); : "+r" (csum) : "r" (addend) : "xer");
return csum; return csum;
#endif #endif
} }
/*
* This is a version of ip_compute_csum() optimized for IP headers,
* which always checksum on 4 octet boundaries. ihl is the number
* of 32-bit words and is always >= 5.
*/
static inline __wsum ip_fast_csum_nofold(const void *iph, unsigned int ihl)
{
const u32 *ptr = (const u32 *)iph + 1;
#ifdef __powerpc64__
unsigned int i;
u64 s = *(const u32 *)iph;
for (i = 0; i < ihl - 1; i++, ptr++)
s += *ptr;
s += (s >> 32);
return (__force __wsum)s;
#else
__wsum sum, tmp;
asm("mtctr %3;"
"addc %0,%4,%5;"
"1: lwzu %1, 4(%2);"
"adde %0,%0,%1;"
"bdnz 1b;"
"addze %0,%0;"
: "=r" (sum), "=r" (tmp), "+b" (ptr)
: "r" (ihl - 2), "r" (*(const u32 *)iph), "r" (*ptr)
: "ctr", "xer", "memory");
return sum;
#endif
}
static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
{
return csum_fold(ip_fast_csum_nofold(iph, ihl));
}
/*
* computes the checksum of a memory block at buff, length len,
* and adds in "sum" (32-bit)
*
* returns a 32-bit number suitable for feeding into itself
* or csum_tcpudp_magic
*
* this function must be called with even lengths, except
* for the last fragment, which may be odd
*
* it's best to have buff aligned on a 32-bit boundary
*/
__wsum __csum_partial(const void *buff, int len, __wsum sum);
static inline __wsum csum_partial(const void *buff, int len, __wsum sum)
{
if (__builtin_constant_p(len) && len <= 16 && (len & 1) == 0) {
if (len == 2)
sum = csum_add(sum, (__force __wsum)*(const u16 *)buff);
if (len >= 4)
sum = csum_add(sum, (__force __wsum)*(const u32 *)buff);
if (len == 6)
sum = csum_add(sum, (__force __wsum)
*(const u16 *)(buff + 4));
if (len >= 8)
sum = csum_add(sum, (__force __wsum)
*(const u32 *)(buff + 4));
if (len == 10)
sum = csum_add(sum, (__force __wsum)
*(const u16 *)(buff + 8));
if (len >= 12)
sum = csum_add(sum, (__force __wsum)
*(const u32 *)(buff + 8));
if (len == 14)
sum = csum_add(sum, (__force __wsum)
*(const u16 *)(buff + 12));
if (len >= 16)
sum = csum_add(sum, (__force __wsum)
*(const u32 *)(buff + 12));
} else if (__builtin_constant_p(len) && (len & 3) == 0) {
sum = csum_add(sum, ip_fast_csum_nofold(buff, len >> 2));
} else {
sum = __csum_partial(buff, len, sum);
}
return sum;
}
/*
* this routine is used for miscellaneous IP-like checksums, mainly
* in icmp.c
*/
static inline __sum16 ip_compute_csum(const void *buff, int len)
{
return csum_fold(csum_partial(buff, len, 0));
}
#endif #endif
#endif /* __KERNEL__ */ #endif /* __KERNEL__ */
#endif #endif
arch/powerpc/include/asm/cputable.h
浏览文件 @ a1b53446
...@@ -43,6 +43,11 @@ extern int machine_check_e500(struct pt_regs *regs); ...@@ -43,6 +43,11 @@ extern int machine_check_e500(struct pt_regs *regs);
extern int machine_check_e200(struct pt_regs *regs); extern int machine_check_e200(struct pt_regs *regs);
extern int machine_check_47x(struct pt_regs *regs); extern int machine_check_47x(struct pt_regs *regs);
extern void cpu_down_flush_e500v2(void);
extern void cpu_down_flush_e500mc(void);
extern void cpu_down_flush_e5500(void);
extern void cpu_down_flush_e6500(void);
/* NOTE WELL: Update identify_cpu() if fields are added or removed! */ /* NOTE WELL: Update identify_cpu() if fields are added or removed! */
struct cpu_spec { struct cpu_spec {
/* CPU is matched via (PVR & pvr_mask) == pvr_value */ /* CPU is matched via (PVR & pvr_mask) == pvr_value */
...@@ -59,6 +64,9 @@ struct cpu_spec { ...@@ -59,6 +64,9 @@ struct cpu_spec {
unsigned int icache_bsize; unsigned int icache_bsize;
unsigned int dcache_bsize; unsigned int dcache_bsize;
/* flush caches inside the current cpu */
void (*cpu_down_flush)(void);
/* number of performance monitor counters */ /* number of performance monitor counters */
unsigned int num_pmcs; unsigned int num_pmcs;
enum powerpc_pmc_type pmc_type; enum powerpc_pmc_type pmc_type;
......
arch/powerpc/include/asm/cputhreads.h
浏览文件 @ a1b53446
#ifndef _ASM_POWERPC_CPUTHREADS_H #ifndef _ASM_POWERPC_CPUTHREADS_H
#define _ASM_POWERPC_CPUTHREADS_H #define _ASM_POWERPC_CPUTHREADS_H
#ifndef __ASSEMBLY__
#include <linux/cpumask.h> #include <linux/cpumask.h>
/* /*
...@@ -94,7 +95,21 @@ static inline int cpu_last_thread_sibling(int cpu) ...@@ -94,7 +95,21 @@ static inline int cpu_last_thread_sibling(int cpu)
return cpu | (threads_per_core - 1); return cpu | (threads_per_core - 1);
} }
static inline u32 get_tensr(void)
{
#ifdef CONFIG_BOOKE
if (cpu_has_feature(CPU_FTR_SMT))
return mfspr(SPRN_TENSR);
#endif
return 1;
}
void book3e_start_thread(int thread, unsigned long addr);
void book3e_stop_thread(int thread);
#endif /* __ASSEMBLY__ */
#define INVALID_THREAD_HWID 0x0fff
#endif /* _ASM_POWERPC_CPUTHREADS_H */ #endif /* _ASM_POWERPC_CPUTHREADS_H */
arch/powerpc/include/asm/fsl_pm.h 0 → 100644
浏览文件 @ a1b53446
/*
* Support Power Management
*
* Copyright 2014-2015 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __PPC_FSL_PM_H
#define __PPC_FSL_PM_H
#define E500_PM_PH10 1
#define E500_PM_PH15 2
#define E500_PM_PH20 3
#define E500_PM_PH30 4
#define E500_PM_DOZE E500_PM_PH10
#define E500_PM_NAP E500_PM_PH15
#define PLAT_PM_SLEEP 20
#define PLAT_PM_LPM20 30
#define FSL_PM_SLEEP (1 << 0)
#define FSL_PM_DEEP_SLEEP (1 << 1)
struct fsl_pm_ops {
/* mask pending interrupts to the RCPM from MPIC */
void (*irq_mask)(int cpu);
/* unmask pending interrupts to the RCPM from MPIC */
void (*irq_unmask)(int cpu);
void (*cpu_enter_state)(int cpu, int state);
void (*cpu_exit_state)(int cpu, int state);
void (*cpu_up_prepare)(int cpu);
void (*cpu_die)(int cpu);
int (*plat_enter_sleep)(void);
void (*freeze_time_base)(bool freeze);
/* keep the power of IP blocks during sleep/deep sleep */
void (*set_ip_power)(bool enable, u32 mask);
/* get platform supported power management modes */
unsigned int (*get_pm_modes)(void);
};
extern const struct fsl_pm_ops *qoriq_pm_ops;
int __init fsl_rcpm_init(void);
#endif /* __PPC_FSL_PM_H */
arch/powerpc/include/asm/mmu-8xx.h
浏览文件 @ a1b53446
...@@ -171,9 +171,9 @@ typedef struct { ...@@ -171,9 +171,9 @@ typedef struct {
} mm_context_t; } mm_context_t;
#endif /* !__ASSEMBLY__ */ #endif /* !__ASSEMBLY__ */
#if (PAGE_SHIFT == 12) #if defined(CONFIG_PPC_4K_PAGES)
#define mmu_virtual_psize MMU_PAGE_4K #define mmu_virtual_psize MMU_PAGE_4K
#elif (PAGE_SHIFT == 14) #elif defined(CONFIG_PPC_16K_PAGES)
#define mmu_virtual_psize MMU_PAGE_16K #define mmu_virtual_psize MMU_PAGE_16K
#else #else
#error "Unsupported PAGE_SIZE" #error "Unsupported PAGE_SIZE"
......
arch/powerpc/include/asm/nohash/32/pgtable.h
浏览文件 @ a1b53446
...@@ -86,7 +86,7 @@ extern int icache_44x_need_flush; ...@@ -86,7 +86,7 @@ extern int icache_44x_need_flush;
* We no longer map larger than phys RAM with the BATs so we don't have * We no longer map larger than phys RAM with the BATs so we don't have
* to worry about the VMALLOC_OFFSET causing problems. We do have to worry * to worry about the VMALLOC_OFFSET causing problems. We do have to worry
* about clashes between our early calls to ioremap() that start growing down * about clashes between our early calls to ioremap() that start growing down
* from ioremap_base being run into the VM area allocations (growing upwards * from IOREMAP_TOP being run into the VM area allocations (growing upwards
* from VMALLOC_START). For this reason we have ioremap_bot to check when * from VMALLOC_START). For this reason we have ioremap_bot to check when
* we actually run into our mappings setup in the early boot with the VM * we actually run into our mappings setup in the early boot with the VM
* system. This really does become a problem for machines with good amounts * system. This really does become a problem for machines with good amounts
...@@ -309,7 +309,8 @@ static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry) ...@@ -309,7 +309,8 @@ static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry)
#define pte_index(address) \ #define pte_index(address) \
(((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
#define pte_offset_kernel(dir, addr) \ #define pte_offset_kernel(dir, addr) \
((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(addr)) (pmd_bad(*(dir)) ? NULL : (pte_t *)pmd_page_vaddr(*(dir)) + \
pte_index(addr))
#define pte_offset_map(dir, addr) \ #define pte_offset_map(dir, addr) \
((pte_t *) kmap_atomic(pmd_page(*(dir))) + pte_index(addr)) ((pte_t *) kmap_atomic(pmd_page(*(dir))) + pte_index(addr))
#define pte_unmap(pte) kunmap_atomic(pte) #define pte_unmap(pte) kunmap_atomic(pte)
......
arch/powerpc/include/asm/page_32.h
浏览文件 @ a1b53446
#ifndef _ASM_POWERPC_PAGE_32_H #ifndef _ASM_POWERPC_PAGE_32_H
#define _ASM_POWERPC_PAGE_32_H #define _ASM_POWERPC_PAGE_32_H
#include <asm/cache.h>
#if defined(CONFIG_PHYSICAL_ALIGN) && (CONFIG_PHYSICAL_START != 0) #if defined(CONFIG_PHYSICAL_ALIGN) && (CONFIG_PHYSICAL_START != 0)
#if (CONFIG_PHYSICAL_START % CONFIG_PHYSICAL_ALIGN) != 0 #if (CONFIG_PHYSICAL_START % CONFIG_PHYSICAL_ALIGN) != 0
#error "CONFIG_PHYSICAL_START must be a multiple of CONFIG_PHYSICAL_ALIGN" #error "CONFIG_PHYSICAL_START must be a multiple of CONFIG_PHYSICAL_ALIGN"
...@@ -36,9 +38,18 @@ typedef unsigned long long pte_basic_t; ...@@ -36,9 +38,18 @@ typedef unsigned long long pte_basic_t;
typedef unsigned long pte_basic_t; typedef unsigned long pte_basic_t;
#endif #endif
struct page; /*
extern void clear_pages(void *page, int order); * Clear page using the dcbz instruction, which doesn't cause any
static inline void clear_page(void *page) { clear_pages(page, 0); } * memory traffic (except to write out any cache lines which get
* displaced). This only works on cacheable memory.
*/
static inline void clear_page(void *addr)
{
unsigned int i;
for (i = 0; i < PAGE_SIZE / L1_CACHE_BYTES; i++, addr += L1_CACHE_BYTES)
dcbz(addr);
}
extern void copy_page(void *to, void *from); extern void copy_page(void *to, void *from);
#include <asm-generic/getorder.h> #include <asm-generic/getorder.h>
......
arch/powerpc/include/asm/reg.h
浏览文件 @ a1b53446
...@@ -1219,9 +1219,11 @@ static inline void mtmsr_isync(unsigned long val) ...@@ -1219,9 +1219,11 @@ static inline void mtmsr_isync(unsigned long val)
#define mfspr(rn) ({unsigned long rval; \ #define mfspr(rn) ({unsigned long rval; \
asm volatile("mfspr %0," __stringify(rn) \ asm volatile("mfspr %0," __stringify(rn) \
: "=r" (rval)); rval;}) : "=r" (rval)); rval;})
#ifndef mtspr
#define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : \ #define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : \
: "r" ((unsigned long)(v)) \ : "r" ((unsigned long)(v)) \
: "memory") : "memory")
#endif
extern void msr_check_and_set(unsigned long bits); extern void msr_check_and_set(unsigned long bits);
extern bool strict_msr_control; extern bool strict_msr_control;
......
arch/powerpc/include/asm/reg_8xx.h
浏览文件 @ a1b53446
...@@ -4,6 +4,8 @@ ...@@ -4,6 +4,8 @@
#ifndef _ASM_POWERPC_REG_8xx_H #ifndef _ASM_POWERPC_REG_8xx_H
#define _ASM_POWERPC_REG_8xx_H #define _ASM_POWERPC_REG_8xx_H
#include <asm/mmu-8xx.h>
/* Cache control on the MPC8xx is provided through some additional /* Cache control on the MPC8xx is provided through some additional
* special purpose registers. * special purpose registers.
*/ */
...@@ -14,6 +16,15 @@ ...@@ -14,6 +16,15 @@
#define SPRN_DC_ADR 569 /* Address needed for some commands */ #define SPRN_DC_ADR 569 /* Address needed for some commands */
#define SPRN_DC_DAT 570 /* Read-only data register */ #define SPRN_DC_DAT 570 /* Read-only data register */
/* Misc Debug */
#define SPRN_DPDR 630
#define SPRN_MI_CAM 816
#define SPRN_MI_RAM0 817
#define SPRN_MI_RAM1 818
#define SPRN_MD_CAM 824
#define SPRN_MD_RAM0 825
#define SPRN_MD_RAM1 826
/* Commands. Only the first few are available to the instruction cache. /* Commands. Only the first few are available to the instruction cache.
*/ */
#define IDC_ENABLE 0x02000000 /* Cache enable */ #define IDC_ENABLE 0x02000000 /* Cache enable */
...@@ -39,4 +50,86 @@ ...@@ -39,4 +50,86 @@
#define DC_DFWT 0x40000000 /* Data cache is forced write through */ #define DC_DFWT 0x40000000 /* Data cache is forced write through */
#define DC_LES 0x20000000 /* Caches are little endian mode */ #define DC_LES 0x20000000 /* Caches are little endian mode */
#ifdef CONFIG_8xx_CPU6
#define do_mtspr_cpu6(rn, rn_addr, v) \
do { \
int _reg_cpu6 = rn_addr, _tmp_cpu6[1]; \
asm volatile("stw %0, %1;" \
"lwz %0, %1;" \
"mtspr " __stringify(rn) ",%2" : \
: "r" (_reg_cpu6), "m"(_tmp_cpu6), \
"r" ((unsigned long)(v)) \
: "memory"); \
} while (0)
#define do_mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : \
: "r" ((unsigned long)(v)) \
: "memory")
#define mtspr(rn, v) \
do { \
if (rn == SPRN_IMMR) \
do_mtspr_cpu6(rn, 0x3d30, v); \
else if (rn == SPRN_IC_CST) \
do_mtspr_cpu6(rn, 0x2110, v); \
else if (rn == SPRN_IC_ADR) \
do_mtspr_cpu6(rn, 0x2310, v); \
else if (rn == SPRN_IC_DAT) \
do_mtspr_cpu6(rn, 0x2510, v); \
else if (rn == SPRN_DC_CST) \
do_mtspr_cpu6(rn, 0x3110, v); \
else if (rn == SPRN_DC_ADR) \
do_mtspr_cpu6(rn, 0x3310, v); \
else if (rn == SPRN_DC_DAT) \
do_mtspr_cpu6(rn, 0x3510, v); \
else if (rn == SPRN_MI_CTR) \
do_mtspr_cpu6(rn, 0x2180, v); \
else if (rn == SPRN_MI_AP) \
do_mtspr_cpu6(rn, 0x2580, v); \
else if (rn == SPRN_MI_EPN) \
do_mtspr_cpu6(rn, 0x2780, v); \
else if (rn == SPRN_MI_TWC) \
do_mtspr_cpu6(rn, 0x2b80, v); \
else if (rn == SPRN_MI_RPN) \
do_mtspr_cpu6(rn, 0x2d80, v); \
else if (rn == SPRN_MI_CAM) \
do_mtspr_cpu6(rn, 0x2190, v); \
else if (rn == SPRN_MI_RAM0) \
do_mtspr_cpu6(rn, 0x2390, v); \
else if (rn == SPRN_MI_RAM1) \
do_mtspr_cpu6(rn, 0x2590, v); \
else if (rn == SPRN_MD_CTR) \
do_mtspr_cpu6(rn, 0x3180, v); \
else if (rn == SPRN_M_CASID) \
do_mtspr_cpu6(rn, 0x3380, v); \
else if (rn == SPRN_MD_AP) \
do_mtspr_cpu6(rn, 0x3580, v); \
else if (rn == SPRN_MD_EPN) \
do_mtspr_cpu6(rn, 0x3780, v); \
else if (rn == SPRN_M_TWB) \
do_mtspr_cpu6(rn, 0x3980, v); \
else if (rn == SPRN_MD_TWC) \
do_mtspr_cpu6(rn, 0x3b80, v); \
else if (rn == SPRN_MD_RPN) \
do_mtspr_cpu6(rn, 0x3d80, v); \
else if (rn == SPRN_M_TW) \
do_mtspr_cpu6(rn, 0x3f80, v); \
else if (rn == SPRN_MD_CAM) \
do_mtspr_cpu6(rn, 0x3190, v); \
else if (rn == SPRN_MD_RAM0) \
do_mtspr_cpu6(rn, 0x3390, v); \
else if (rn == SPRN_MD_RAM1) \
do_mtspr_cpu6(rn, 0x3590, v); \
else if (rn == SPRN_DEC) \
do_mtspr_cpu6(rn, 0x2c00, v); \
else if (rn == SPRN_TBWL) \
do_mtspr_cpu6(rn, 0x3880, v); \
else if (rn == SPRN_TBWU) \
do_mtspr_cpu6(rn, 0x3a80, v); \
else if (rn == SPRN_DPDR) \
do_mtspr_cpu6(rn, 0x2d30, v); \
else \
do_mtspr(rn, v); \
} while (0)
#endif
#endif /* _ASM_POWERPC_REG_8xx_H */ #endif /* _ASM_POWERPC_REG_8xx_H */
arch/powerpc/include/asm/smp.h
浏览文件 @ a1b53446
...@@ -67,6 +67,9 @@ void generic_cpu_die(unsigned int cpu); ...@@ -67,6 +67,9 @@ void generic_cpu_die(unsigned int cpu);
void generic_set_cpu_dead(unsigned int cpu); void generic_set_cpu_dead(unsigned int cpu);
void generic_set_cpu_up(unsigned int cpu); void generic_set_cpu_up(unsigned int cpu);
int generic_check_cpu_restart(unsigned int cpu); int generic_check_cpu_restart(unsigned int cpu);
int is_cpu_dead(unsigned int cpu);
#else
#define generic_set_cpu_up(i) do { } while (0)
#endif #endif
#ifdef CONFIG_PPC64 #ifdef CONFIG_PPC64
...@@ -197,6 +200,7 @@ extern void generic_secondary_thread_init(void); ...@@ -197,6 +200,7 @@ extern void generic_secondary_thread_init(void);
extern unsigned long __secondary_hold_spinloop; extern unsigned long __secondary_hold_spinloop;
extern unsigned long __secondary_hold_acknowledge; extern unsigned long __secondary_hold_acknowledge;
extern char __secondary_hold; extern char __secondary_hold;
extern unsigned int booting_thread_hwid;
extern void __early_start(void); extern void __early_start(void);
#endif /* __ASSEMBLY__ */ #endif /* __ASSEMBLY__ */
......
arch/powerpc/include/asm/time.h
浏览文件 @ a1b53446
...@@ -31,8 +31,6 @@ extern void tick_broadcast_ipi_handler(void); ...@@ -31,8 +31,6 @@ extern void tick_broadcast_ipi_handler(void);
extern void generic_calibrate_decr(void); extern void generic_calibrate_decr(void);
extern void set_dec_cpu6(unsigned int val);
/* Some sane defaults: 125 MHz timebase, 1GHz processor */ /* Some sane defaults: 125 MHz timebase, 1GHz processor */
extern unsigned long ppc_proc_freq; extern unsigned long ppc_proc_freq;
#define DEFAULT_PROC_FREQ (DEFAULT_TB_FREQ * 8) #define DEFAULT_PROC_FREQ (DEFAULT_TB_FREQ * 8)
...@@ -166,14 +164,12 @@ static inline void set_dec(int val) ...@@ -166,14 +164,12 @@ static inline void set_dec(int val)
{ {
#if defined(CONFIG_40x) #if defined(CONFIG_40x)
mtspr(SPRN_PIT, val); mtspr(SPRN_PIT, val);
#elif defined(CONFIG_8xx_CPU6)
set_dec_cpu6(val - 1);
#else #else
#ifndef CONFIG_BOOKE #ifndef CONFIG_BOOKE
--val; --val;
#endif #endif
mtspr(SPRN_DEC, val); mtspr(SPRN_DEC, val);
#endif /* not 40x or 8xx_CPU6 */ #endif /* not 40x */
} }
static inline unsigned long tb_ticks_since(unsigned long tstamp) static inline unsigned long tb_ticks_since(unsigned long tstamp)
......
arch/powerpc/kernel/asm-offsets.c
浏览文件 @ a1b53446
...@@ -376,6 +376,7 @@ int main(void) ...@@ -376,6 +376,7 @@ int main(void)
DEFINE(CPU_SPEC_FEATURES, offsetof(struct cpu_spec, cpu_features)); DEFINE(CPU_SPEC_FEATURES, offsetof(struct cpu_spec, cpu_features));
DEFINE(CPU_SPEC_SETUP, offsetof(struct cpu_spec, cpu_setup)); DEFINE(CPU_SPEC_SETUP, offsetof(struct cpu_spec, cpu_setup));
DEFINE(CPU_SPEC_RESTORE, offsetof(struct cpu_spec, cpu_restore)); DEFINE(CPU_SPEC_RESTORE, offsetof(struct cpu_spec, cpu_restore));
DEFINE(CPU_DOWN_FLUSH, offsetof(struct cpu_spec, cpu_down_flush));
DEFINE(pbe_address, offsetof(struct pbe, address)); DEFINE(pbe_address, offsetof(struct pbe, address));
DEFINE(pbe_orig_address, offsetof(struct pbe, orig_address)); DEFINE(pbe_orig_address, offsetof(struct pbe, orig_address));
......
arch/powerpc/kernel/cpu_setup_fsl_booke.S
浏览文件 @ a1b53446
...@@ -13,11 +13,13 @@ ...@@ -13,11 +13,13 @@
* *
*/ */
#include <asm/page.h>
#include <asm/processor.h> #include <asm/processor.h>
#include <asm/cputable.h> #include <asm/cputable.h>
#include <asm/ppc_asm.h> #include <asm/ppc_asm.h>
#include <asm/mmu-book3e.h> #include <asm/mmu-book3e.h>
#include <asm/asm-offsets.h> #include <asm/asm-offsets.h>
#include <asm/mpc85xx.h>
_GLOBAL(__e500_icache_setup) _GLOBAL(__e500_icache_setup)
mfspr r0, SPRN_L1CSR1 mfspr r0, SPRN_L1CSR1
...@@ -233,3 +235,113 @@ _GLOBAL(__setup_cpu_e5500) ...@@ -233,3 +235,113 @@ _GLOBAL(__setup_cpu_e5500)
mtlr r5 mtlr r5
blr blr
#endif #endif
/* flush L1 date cache, it can apply to e500v2, e500mc and e5500 */
_GLOBAL(flush_dcache_L1)
mfmsr r10
wrteei 0
mfspr r3,SPRN_L1CFG0
rlwinm r5,r3,9,3 /* Extract cache block size */
twlgti r5,1 /* Only 32 and 64 byte cache blocks
* are currently defined.
*/
li r4,32
subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
* log2(number of ways)
*/
slw r5,r4,r5 /* r5 = cache block size */
rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
mulli r7,r7,13 /* An 8-way cache will require 13
* loads per set.
*/
slw r7,r7,r6
/* save off HID0 and set DCFA */
mfspr r8,SPRN_HID0
ori r9,r8,HID0_DCFA@l
mtspr SPRN_HID0,r9
isync
LOAD_REG_IMMEDIATE(r6, KERNELBASE)
mr r4, r6
mtctr r7
1: lwz r3,0(r4) /* Load... */
add r4,r4,r5
bdnz 1b
msync
mr r4, r6
mtctr r7
1: dcbf 0,r4 /* ...and flush. */
add r4,r4,r5
bdnz 1b
/* restore HID0 */
mtspr SPRN_HID0,r8
isync
wrtee r10
blr
has_L2_cache:
/* skip L2 cache on P2040/P2040E as they have no L2 cache */
mfspr r3, SPRN_SVR
/* shift right by 8 bits and clear E bit of SVR */
rlwinm r4, r3, 24, ~0x800
lis r3, SVR_P2040@h
ori r3, r3, SVR_P2040@l
cmpw r4, r3
beq 1f
li r3, 1
blr
1:
li r3, 0
blr
/* flush backside L2 cache */
flush_backside_L2_cache:
mflr r10
bl has_L2_cache
mtlr r10
cmpwi r3, 0
beq 2f
/* Flush the L2 cache */
mfspr r3, SPRN_L2CSR0
ori r3, r3, L2CSR0_L2FL@l
msync
isync
mtspr SPRN_L2CSR0,r3
isync
/* check if it is complete */
1: mfspr r3,SPRN_L2CSR0
andi. r3, r3, L2CSR0_L2FL@l
bne 1b
2:
blr
_GLOBAL(cpu_down_flush_e500v2)
mflr r0
bl flush_dcache_L1
mtlr r0
blr
_GLOBAL(cpu_down_flush_e500mc)
_GLOBAL(cpu_down_flush_e5500)
mflr r0
bl flush_dcache_L1
bl flush_backside_L2_cache
mtlr r0
blr
/* L1 Data Cache of e6500 contains no modified data, no flush is required */
_GLOBAL(cpu_down_flush_e6500)
blr
arch/powerpc/kernel/cputable.c
浏览文件 @ a1b53446
...@@ -2050,6 +2050,7 @@ static struct cpu_spec __initdata cpu_specs[] = { ...@@ -2050,6 +2050,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_setup = __setup_cpu_e500v2, .cpu_setup = __setup_cpu_e500v2,
.machine_check = machine_check_e500, .machine_check = machine_check_e500,
.platform = "ppc8548", .platform = "ppc8548",
.cpu_down_flush = cpu_down_flush_e500v2,
}, },
#else #else
{ /* e500mc */ { /* e500mc */
...@@ -2069,6 +2070,7 @@ static struct cpu_spec __initdata cpu_specs[] = { ...@@ -2069,6 +2070,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_setup = __setup_cpu_e500mc, .cpu_setup = __setup_cpu_e500mc,
.machine_check = machine_check_e500mc, .machine_check = machine_check_e500mc,
.platform = "ppce500mc", .platform = "ppce500mc",
.cpu_down_flush = cpu_down_flush_e500mc,
}, },
#endif /* CONFIG_PPC_E500MC */ #endif /* CONFIG_PPC_E500MC */
#endif /* CONFIG_PPC32 */ #endif /* CONFIG_PPC32 */
...@@ -2093,6 +2095,7 @@ static struct cpu_spec __initdata cpu_specs[] = { ...@@ -2093,6 +2095,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
#endif #endif
.machine_check = machine_check_e500mc, .machine_check = machine_check_e500mc,
.platform = "ppce5500", .platform = "ppce5500",
.cpu_down_flush = cpu_down_flush_e5500,
}, },
{ /* e6500 */ { /* e6500 */
.pvr_mask = 0xffff0000, .pvr_mask = 0xffff0000,
...@@ -2115,6 +2118,7 @@ static struct cpu_spec __initdata cpu_specs[] = { ...@@ -2115,6 +2118,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
#endif #endif
.machine_check = machine_check_e500mc, .machine_check = machine_check_e500mc,
.platform = "ppce6500", .platform = "ppce6500",
.cpu_down_flush = cpu_down_flush_e6500,
}, },
#endif /* CONFIG_PPC_E500MC */ #endif /* CONFIG_PPC_E500MC */
#ifdef CONFIG_PPC32 #ifdef CONFIG_PPC32
......
arch/powerpc/kernel/head_64.S
浏览文件 @ a1b53446
...@@ -40,6 +40,7 @@ ...@@ -40,6 +40,7 @@
#include <asm/kvm_book3s_asm.h> #include <asm/kvm_book3s_asm.h>
#include <asm/ptrace.h> #include <asm/ptrace.h>
#include <asm/hw_irq.h> #include <asm/hw_irq.h>
#include <asm/cputhreads.h>
/* The physical memory is laid out such that the secondary processor /* The physical memory is laid out such that the secondary processor
* spin code sits at 0x0000...0x00ff. On server, the vectors follow * spin code sits at 0x0000...0x00ff. On server, the vectors follow
...@@ -181,6 +182,64 @@ exception_marker: ...@@ -181,6 +182,64 @@ exception_marker:
#endif #endif
#ifdef CONFIG_PPC_BOOK3E #ifdef CONFIG_PPC_BOOK3E
/*
* The booting_thread_hwid holds the thread id we want to boot in cpu
* hotplug case. It is set by cpu hotplug code, and is invalid by default.
* The thread id is the same as the initial value of SPRN_PIR[THREAD_ID]
* bit field.
*/
.globl booting_thread_hwid
booting_thread_hwid:
.long INVALID_THREAD_HWID
.align 3
/*
* start a thread in the same core
* input parameters:
* r3 = the thread physical id
* r4 = the entry point where thread starts
*/
_GLOBAL(book3e_start_thread)
LOAD_REG_IMMEDIATE(r5, MSR_KERNEL)
cmpi 0, r3, 0
beq 10f
cmpi 0, r3, 1
beq 11f
/* If the thread id is invalid, just exit. */
b 13f
10:
mttmr TMRN_IMSR0, r5
mttmr TMRN_INIA0, r4
b 12f
11:
mttmr TMRN_IMSR1, r5
mttmr TMRN_INIA1, r4
12:
isync
li r6, 1
sld r6, r6, r3
mtspr SPRN_TENS, r6
13:
blr
/*
* stop a thread in the same core
* input parameter:
* r3 = the thread physical id
*/
_GLOBAL(book3e_stop_thread)
cmpi 0, r3, 0
beq 10f
cmpi 0, r3, 1
beq 10f
/* If the thread id is invalid, just exit. */
b 13f
10:
li r4, 1
sld r4, r4, r3
mtspr SPRN_TENC, r4
13:
blr
_GLOBAL(fsl_secondary_thread_init) _GLOBAL(fsl_secondary_thread_init)
mfspr r4,SPRN_BUCSR mfspr r4,SPRN_BUCSR
...@@ -261,6 +320,44 @@ _GLOBAL(generic_secondary_smp_init) ...@@ -261,6 +320,44 @@ _GLOBAL(generic_secondary_smp_init)
mr r3,r24 mr r3,r24
mr r4,r25 mr r4,r25
bl book3e_secondary_core_init bl book3e_secondary_core_init
/*
* After common core init has finished, check if the current thread is the
* one we wanted to boot. If not, start the specified thread and stop the
* current thread.
*/
LOAD_REG_ADDR(r4, booting_thread_hwid)
lwz r3, 0(r4)
li r5, INVALID_THREAD_HWID
cmpw r3, r5
beq 20f
/*
* The value of booting_thread_hwid has been stored in r3,
* so make it invalid.
*/
stw r5, 0(r4)
/*
* Get the current thread id and check if it is the one we wanted.
* If not, start the one specified in booting_thread_hwid and stop
* the current thread.
*/
mfspr r8, SPRN_TIR
cmpw r3, r8
beq 20f
/* start the specified thread */
LOAD_REG_ADDR(r5, fsl_secondary_thread_init)
ld r4, 0(r5)
bl book3e_start_thread
/* stop the current thread */
mr r3, r8
bl book3e_stop_thread
10:
b 10b
20:
#endif #endif
generic_secondary_common_init: generic_secondary_common_init:
......
arch/powerpc/kernel/head_8xx.S
浏览文件 @ a1b53446
...@@ -329,7 +329,7 @@ InstructionTLBMiss: ...@@ -329,7 +329,7 @@ InstructionTLBMiss:
/* If we are faulting a kernel address, we have to use the /* If we are faulting a kernel address, we have to use the
* kernel page tables. * kernel page tables.
*/ */
#ifdef CONFIG_MODULES #if defined(CONFIG_MODULES) || defined (CONFIG_DEBUG_PAGEALLOC)
/* Only modules will cause ITLB Misses as we always /* Only modules will cause ITLB Misses as we always
* pin the first 8MB of kernel memory */ * pin the first 8MB of kernel memory */
mfspr r11, SPRN_SRR0 /* Get effective address of fault */ mfspr r11, SPRN_SRR0 /* Get effective address of fault */
...@@ -385,27 +385,26 @@ InstructionTLBMiss: ...@@ -385,27 +385,26 @@ InstructionTLBMiss:
. = 0x1200 . = 0x1200
DataStoreTLBMiss: DataStoreTLBMiss:
#ifdef CONFIG_8xx_CPU6
mtspr SPRN_SPRG_SCRATCH2, r3 mtspr SPRN_SPRG_SCRATCH2, r3
#endif
EXCEPTION_PROLOG_0 EXCEPTION_PROLOG_0
mfcr r10 mfcr r3
/* If we are faulting a kernel address, we have to use the /* If we are faulting a kernel address, we have to use the
* kernel page tables. * kernel page tables.
*/ */
mfspr r11, SPRN_MD_EPN mfspr r10, SPRN_MD_EPN
IS_KERNEL(r11, r11) IS_KERNEL(r11, r10)
mfspr r11, SPRN_M_TW /* Get level 1 table */ mfspr r11, SPRN_M_TW /* Get level 1 table */
BRANCH_UNLESS_KERNEL(3f) BRANCH_UNLESS_KERNEL(3f)
lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha
3: 3:
mtcr r10
mfspr r10, SPRN_MD_EPN
/* Insert level 1 index */ /* Insert level 1 index */
rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29 rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29
lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */ lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */
mtcr r11
bt- 28,DTLBMiss8M /* bit 28 = Large page (8M) */
mtcr r3
/* We have a pte table, so load fetch the pte from the table. /* We have a pte table, so load fetch the pte from the table.
*/ */
...@@ -453,13 +452,34 @@ DataStoreTLBMiss: ...@@ -453,13 +452,34 @@ DataStoreTLBMiss:
MTSPR_CPU6(SPRN_MD_RPN, r10, r3) /* Update TLB entry */ MTSPR_CPU6(SPRN_MD_RPN, r10, r3) /* Update TLB entry */
/* Restore registers */ /* Restore registers */
#ifdef CONFIG_8xx_CPU6
mfspr r3, SPRN_SPRG_SCRATCH2 mfspr r3, SPRN_SPRG_SCRATCH2
mtspr SPRN_DAR, r11 /* Tag DAR */
EXCEPTION_EPILOG_0
rfi
DTLBMiss8M:
mtcr r3
ori r11, r11, MD_SVALID
MTSPR_CPU6(SPRN_MD_TWC, r11, r3)
#ifdef CONFIG_PPC_16K_PAGES
/*
* In 16k pages mode, each PGD entry defines a 64M block.
* Here we select the 8M page within the block.
*/
rlwimi r11, r10, 0, 0x03800000
#endif #endif
rlwinm r10, r11, 0, 0xff800000
ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_SHARED | _PAGE_DIRTY | \
_PAGE_PRESENT
MTSPR_CPU6(SPRN_MD_RPN, r10, r3) /* Update TLB entry */
li r11, RPN_PATTERN
mfspr r3, SPRN_SPRG_SCRATCH2
mtspr SPRN_DAR, r11 /* Tag DAR */ mtspr SPRN_DAR, r11 /* Tag DAR */
EXCEPTION_EPILOG_0 EXCEPTION_EPILOG_0
rfi rfi
/* This is an instruction TLB error on the MPC8xx. This could be due /* This is an instruction TLB error on the MPC8xx. This could be due
* to many reasons, such as executing guarded memory or illegal instruction * to many reasons, such as executing guarded memory or illegal instruction
* addresses. There is nothing to do but handle a big time error fault. * addresses. There is nothing to do but handle a big time error fault.
...@@ -537,13 +557,15 @@ FixupDAR:/* Entry point for dcbx workaround. */ ...@@ -537,13 +557,15 @@ FixupDAR:/* Entry point for dcbx workaround. */
/* Insert level 1 index */ /* Insert level 1 index */
3: rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29 3: rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29
lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */ lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */
mtcr r11
bt 28,200f /* bit 28 = Large page (8M) */
rlwinm r11, r11,0,0,19 /* Extract page descriptor page address */ rlwinm r11, r11,0,0,19 /* Extract page descriptor page address */
/* Insert level 2 index */ /* Insert level 2 index */
rlwimi r11, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29 rlwimi r11, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29
lwz r11, 0(r11) /* Get the pte */ lwz r11, 0(r11) /* Get the pte */
/* concat physical page address(r11) and page offset(r10) */ /* concat physical page address(r11) and page offset(r10) */
rlwimi r11, r10, 0, 32 - PAGE_SHIFT, 31 rlwimi r11, r10, 0, 32 - PAGE_SHIFT, 31
lwz r11,0(r11) 201: lwz r11,0(r11)
/* Check if it really is a dcbx instruction. */ /* Check if it really is a dcbx instruction. */
/* dcbt and dcbtst does not generate DTLB Misses/Errors, /* dcbt and dcbtst does not generate DTLB Misses/Errors,
* no need to include them here */ * no need to include them here */
...@@ -562,6 +584,10 @@ FixupDAR:/* Entry point for dcbx workaround. */ ...@@ -562,6 +584,10 @@ FixupDAR:/* Entry point for dcbx workaround. */
141: mfspr r10,SPRN_SPRG_SCRATCH2 141: mfspr r10,SPRN_SPRG_SCRATCH2
b DARFixed /* Nope, go back to normal TLB processing */ b DARFixed /* Nope, go back to normal TLB processing */
/* concat physical page address(r11) and page offset(r10) */
200: rlwimi r11, r10, 0, 32 - (PAGE_SHIFT << 1), 31
b 201b
144: mfspr r10, SPRN_DSISR 144: mfspr r10, SPRN_DSISR
rlwinm r10, r10,0,7,5 /* Clear store bit for buggy dcbst insn */ rlwinm r10, r10,0,7,5 /* Clear store bit for buggy dcbst insn */
mtspr SPRN_DSISR, r10 mtspr SPRN_DSISR, r10
...@@ -856,68 +882,6 @@ initial_mmu: ...@@ -856,68 +882,6 @@ initial_mmu:
blr blr
/*
* Set up to use a given MMU context.
* r3 is context number, r4 is PGD pointer.
*
* We place the physical address of the new task page directory loaded
* into the MMU base register, and set the ASID compare register with
* the new "context."
*/
_GLOBAL(set_context)
#ifdef CONFIG_BDI_SWITCH
/* Context switch the PTE pointer for the Abatron BDI2000.
* The PGDIR is passed as second argument.
*/
lis r5, KERNELBASE@h
lwz r5, 0xf0(r5)
stw r4, 0x4(r5)
#endif
/* Register M_TW will contain base address of level 1 table minus the
* lower part of the kernel PGDIR base address, so that all accesses to
* level 1 table are done relative to lower part of kernel PGDIR base
* address.
*/
li r5, (swapper_pg_dir-PAGE_OFFSET)@l
sub r4, r4, r5
tophys (r4, r4)
#ifdef CONFIG_8xx_CPU6
lis r6, cpu6_errata_word@h
ori r6, r6, cpu6_errata_word@l
li r7, 0x3f80
stw r7, 12(r6)
lwz r7, 12(r6)
#endif
mtspr SPRN_M_TW, r4 /* Update pointeur to level 1 table */
#ifdef CONFIG_8xx_CPU6
li r7, 0x3380
stw r7, 12(r6)
lwz r7, 12(r6)
#endif
mtspr SPRN_M_CASID, r3 /* Update context */
SYNC
blr
#ifdef CONFIG_8xx_CPU6
/* It's here because it is unique to the 8xx.
* It is important we get called with interrupts disabled. I used to
* do that, but it appears that all code that calls this already had
* interrupt disabled.
*/
.globl set_dec_cpu6
set_dec_cpu6:
lis r7, cpu6_errata_word@h
ori r7, r7, cpu6_errata_word@l
li r4, 0x2c00
stw r4, 8(r7)
lwz r4, 8(r7)
mtspr 22, r3 /* Update Decrementer */
SYNC
blr
#endif
/* /*
* We put a few things here that have to be page-aligned. * We put a few things here that have to be page-aligned.
* This stuff goes at the beginning of the data segment, * This stuff goes at the beginning of the data segment,
......
arch/powerpc/kernel/head_fsl_booke.S
浏览文件 @ a1b53446
...@@ -1037,80 +1037,6 @@ _GLOBAL(set_context) ...@@ -1037,80 +1037,6 @@ _GLOBAL(set_context)
isync /* Force context change */ isync /* Force context change */
blr blr
_GLOBAL(flush_dcache_L1)
mfspr r3,SPRN_L1CFG0
rlwinm r5,r3,9,3 /* Extract cache block size */
twlgti r5,1 /* Only 32 and 64 byte cache blocks
* are currently defined.
*/
li r4,32
subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
* log2(number of ways)
*/
slw r5,r4,r5 /* r5 = cache block size */
rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
mulli r7,r7,13 /* An 8-way cache will require 13
* loads per set.
*/
slw r7,r7,r6
/* save off HID0 and set DCFA */
mfspr r8,SPRN_HID0
ori r9,r8,HID0_DCFA@l
mtspr SPRN_HID0,r9
isync
lis r4,KERNELBASE@h
mtctr r7
1: lwz r3,0(r4) /* Load... */
add r4,r4,r5
bdnz 1b
msync
lis r4,KERNELBASE@h
mtctr r7
1: dcbf 0,r4 /* ...and flush. */
add r4,r4,r5
bdnz 1b
/* restore HID0 */
mtspr SPRN_HID0,r8
isync
blr
/* Flush L1 d-cache, invalidate and disable d-cache and i-cache */
_GLOBAL(__flush_disable_L1)
mflr r10
bl flush_dcache_L1 /* Flush L1 d-cache */
mtlr r10
mfspr r4, SPRN_L1CSR0 /* Invalidate and disable d-cache */
li r5, 2
rlwimi r4, r5, 0, 3
msync
isync
mtspr SPRN_L1CSR0, r4
isync
1: mfspr r4, SPRN_L1CSR0 /* Wait for the invalidate to finish */
andi. r4, r4, 2
bne 1b
mfspr r4, SPRN_L1CSR1 /* Invalidate and disable i-cache */
li r5, 2
rlwimi r4, r5, 0, 3
mtspr SPRN_L1CSR1, r4
isync
blr
#ifdef CONFIG_SMP #ifdef CONFIG_SMP
/* When we get here, r24 needs to hold the CPU # */ /* When we get here, r24 needs to hold the CPU # */
.globl __secondary_start .globl __secondary_start
......
arch/powerpc/kernel/misc_32.S
浏览文件 @ a1b53446
...@@ -91,17 +91,16 @@ _GLOBAL(mulhdu) ...@@ -91,17 +91,16 @@ _GLOBAL(mulhdu)
addc r7,r0,r7 addc r7,r0,r7
addze r4,r4 addze r4,r4
1: beqlr cr1 /* all done if high part of A is 0 */ 1: beqlr cr1 /* all done if high part of A is 0 */
mr r10,r3
mullw r9,r3,r5 mullw r9,r3,r5
mulhwu r3,r3,r5 mulhwu r10,r3,r5
beq 2f beq 2f
mullw r0,r10,r6 mullw r0,r3,r6
mulhwu r8,r10,r6 mulhwu r8,r3,r6
addc r7,r0,r7 addc r7,r0,r7
adde r4,r4,r8 adde r4,r4,r8
addze r3,r3 addze r10,r10
2: addc r4,r4,r9 2: addc r4,r4,r9
addze r3,r3 addze r3,r10
blr blr
/* /*
...@@ -296,12 +295,9 @@ _GLOBAL(real_writeb) ...@@ -296,12 +295,9 @@ _GLOBAL(real_writeb)
* Flush instruction cache. * Flush instruction cache.
* This is a no-op on the 601. * This is a no-op on the 601.
*/ */
#ifndef CONFIG_PPC_8xx
_GLOBAL(flush_instruction_cache) _GLOBAL(flush_instruction_cache)
#if defined(CONFIG_8xx) #if defined(CONFIG_4xx)
isync
lis r5, IDC_INVALL@h
mtspr SPRN_IC_CST, r5
#elif defined(CONFIG_4xx)
#ifdef CONFIG_403GCX #ifdef CONFIG_403GCX
li r3, 512 li r3, 512
mtctr r3 mtctr r3
...@@ -334,9 +330,10 @@ END_FTR_SECTION_IFSET(CPU_FTR_UNIFIED_ID_CACHE) ...@@ -334,9 +330,10 @@ END_FTR_SECTION_IFSET(CPU_FTR_UNIFIED_ID_CACHE)
mfspr r3,SPRN_HID0 mfspr r3,SPRN_HID0
ori r3,r3,HID0_ICFI ori r3,r3,HID0_ICFI
mtspr SPRN_HID0,r3 mtspr SPRN_HID0,r3
#endif /* CONFIG_8xx/4xx */ #endif /* CONFIG_4xx */
isync isync
blr blr
#endif /* CONFIG_PPC_8xx */
/* /*
* Write any modified data cache blocks out to memory * Write any modified data cache blocks out to memory
...@@ -350,10 +347,9 @@ BEGIN_FTR_SECTION ...@@ -350,10 +347,9 @@ BEGIN_FTR_SECTION
PURGE_PREFETCHED_INS PURGE_PREFETCHED_INS
blr /* for 601, do nothing */ blr /* for 601, do nothing */
END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
li r5,L1_CACHE_BYTES-1 rlwinm r3,r3,0,0,31 - L1_CACHE_SHIFT
andc r3,r3,r5
subf r4,r3,r4 subf r4,r3,r4
add r4,r4,r5 addi r4,r4,L1_CACHE_BYTES - 1
srwi. r4,r4,L1_CACHE_SHIFT srwi. r4,r4,L1_CACHE_SHIFT
beqlr beqlr
mtctr r4 mtctr r4
...@@ -376,71 +372,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) ...@@ -376,71 +372,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
sync /* additional sync needed on g4 */ sync /* additional sync needed on g4 */
isync isync
blr blr
/*
* Write any modified data cache blocks out to memory.
* Does not invalidate the corresponding cache lines (especially for
* any corresponding instruction cache).
*
* clean_dcache_range(unsigned long start, unsigned long stop)
*/
_GLOBAL(clean_dcache_range)
li r5,L1_CACHE_BYTES-1
andc r3,r3,r5
subf r4,r3,r4
add r4,r4,r5
srwi. r4,r4,L1_CACHE_SHIFT
beqlr
mtctr r4
1: dcbst 0,r3
addi r3,r3,L1_CACHE_BYTES
bdnz 1b
sync /* wait for dcbst's to get to ram */
blr
/*
* Write any modified data cache blocks out to memory and invalidate them.
* Does not invalidate the corresponding instruction cache blocks.
*
* flush_dcache_range(unsigned long start, unsigned long stop)
*/
_GLOBAL(flush_dcache_range)
li r5,L1_CACHE_BYTES-1
andc r3,r3,r5
subf r4,r3,r4
add r4,r4,r5
srwi. r4,r4,L1_CACHE_SHIFT
beqlr
mtctr r4
1: dcbf 0,r3
addi r3,r3,L1_CACHE_BYTES
bdnz 1b
sync /* wait for dcbst's to get to ram */
blr
/*
* Like above, but invalidate the D-cache. This is used by the 8xx
* to invalidate the cache so the PPC core doesn't get stale data
* from the CPM (no cache snooping here :-).
*
* invalidate_dcache_range(unsigned long start, unsigned long stop)
*/
_GLOBAL(invalidate_dcache_range)
li r5,L1_CACHE_BYTES-1
andc r3,r3,r5
subf r4,r3,r4
add r4,r4,r5
srwi. r4,r4,L1_CACHE_SHIFT
beqlr
mtctr r4
1: dcbi 0,r3
addi r3,r3,L1_CACHE_BYTES
bdnz 1b
sync /* wait for dcbi's to get to ram */
blr
/* /*
* Flush a particular page from the data cache to RAM. * Flush a particular page from the data cache to RAM.
* Note: this is necessary because the instruction cache does *not* * Note: this is necessary because the instruction cache does *not*
...@@ -518,22 +449,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) ...@@ -518,22 +449,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
blr blr
#endif /* CONFIG_BOOKE */ #endif /* CONFIG_BOOKE */
/*
* Clear pages using the dcbz instruction, which doesn't cause any
* memory traffic (except to write out any cache lines which get
* displaced). This only works on cacheable memory.
*
* void clear_pages(void *page, int order) ;
*/
_GLOBAL(clear_pages)
li r0,PAGE_SIZE/L1_CACHE_BYTES
slw r0,r0,r4
mtctr r0
1: dcbz 0,r3
addi r3,r3,L1_CACHE_BYTES
bdnz 1b
blr
/* /*
* Copy a whole page. We use the dcbz instruction on the destination * Copy a whole page. We use the dcbz instruction on the destination
* to reduce memory traffic (it eliminates the unnecessary reads of * to reduce memory traffic (it eliminates the unnecessary reads of
......
arch/powerpc/kernel/ppc_ksyms.c
浏览文件 @ a1b53446
...@@ -6,7 +6,9 @@ ...@@ -6,7 +6,9 @@
#include <asm/cacheflush.h> #include <asm/cacheflush.h>
#include <asm/epapr_hcalls.h> #include <asm/epapr_hcalls.h>
#ifdef CONFIG_PPC64
EXPORT_SYMBOL(flush_dcache_range); EXPORT_SYMBOL(flush_dcache_range);
#endif
EXPORT_SYMBOL(flush_icache_range); EXPORT_SYMBOL(flush_icache_range);
EXPORT_SYMBOL(empty_zero_page); EXPORT_SYMBOL(empty_zero_page);
......
arch/powerpc/kernel/ppc_ksyms_32.c
浏览文件 @ a1b53446
...@@ -10,7 +10,6 @@ ...@@ -10,7 +10,6 @@
#include <asm/pgtable.h> #include <asm/pgtable.h>
#include <asm/dcr.h> #include <asm/dcr.h>
EXPORT_SYMBOL(clear_pages);
EXPORT_SYMBOL(ISA_DMA_THRESHOLD); EXPORT_SYMBOL(ISA_DMA_THRESHOLD);
EXPORT_SYMBOL(DMA_MODE_READ); EXPORT_SYMBOL(DMA_MODE_READ);
EXPORT_SYMBOL(DMA_MODE_WRITE); EXPORT_SYMBOL(DMA_MODE_WRITE);
......
arch/powerpc/kernel/smp.c
浏览文件 @ a1b53446
...@@ -427,7 +427,7 @@ void generic_cpu_die(unsigned int cpu) ...@@ -427,7 +427,7 @@ void generic_cpu_die(unsigned int cpu)
for (i = 0; i < 100; i++) { for (i = 0; i < 100; i++) {
smp_rmb(); smp_rmb();
if (per_cpu(cpu_state, cpu) == CPU_DEAD) if (is_cpu_dead(cpu))
return; return;
msleep(100); msleep(100);
} }
...@@ -454,6 +454,11 @@ int generic_check_cpu_restart(unsigned int cpu) ...@@ -454,6 +454,11 @@ int generic_check_cpu_restart(unsigned int cpu)
return per_cpu(cpu_state, cpu) == CPU_UP_PREPARE; return per_cpu(cpu_state, cpu) == CPU_UP_PREPARE;
} }
int is_cpu_dead(unsigned int cpu)
{
return per_cpu(cpu_state, cpu) == CPU_DEAD;
}
static bool secondaries_inhibited(void) static bool secondaries_inhibited(void)
{ {
return kvm_hv_mode_active(); return kvm_hv_mode_active();
......
arch/powerpc/lib/Makefile
浏览文件 @ a1b53446
...@@ -22,8 +22,7 @@ obj64-$(CONFIG_SMP) += locks.o ...@@ -22,8 +22,7 @@ obj64-$(CONFIG_SMP) += locks.o
obj64-$(CONFIG_ALTIVEC) += vmx-helper.o obj64-$(CONFIG_ALTIVEC) += vmx-helper.o
ifeq ($(CONFIG_GENERIC_CSUM),) ifeq ($(CONFIG_GENERIC_CSUM),)
obj-y += checksum_$(CONFIG_WORD_SIZE).o obj-y += checksum_$(CONFIG_WORD_SIZE).o checksum_wrappers.o
obj-$(CONFIG_PPC64) += checksum_wrappers_64.o
endif endif
obj-$(CONFIG_PPC_EMULATE_SSTEP) += sstep.o ldstfp.o obj-$(CONFIG_PPC_EMULATE_SSTEP) += sstep.o ldstfp.o
......
arch/powerpc/lib/checksum_32.S
浏览文件 @ a1b53446
...@@ -14,68 +14,59 @@ ...@@ -14,68 +14,59 @@
#include <linux/sys.h> #include <linux/sys.h>
#include <asm/processor.h> #include <asm/processor.h>
#include <asm/cache.h>
#include <asm/errno.h> #include <asm/errno.h>
#include <asm/ppc_asm.h> #include <asm/ppc_asm.h>
.text .text
/*
* ip_fast_csum(buf, len) -- Optimized for IP header
* len is in words and is always >= 5.
*/
_GLOBAL(ip_fast_csum)
lwz r0,0(r3)
lwzu r5,4(r3)
addic. r4,r4,-2
addc r0,r0,r5
mtctr r4
blelr-
1: lwzu r4,4(r3)
adde r0,r0,r4
bdnz 1b
addze r0,r0 /* add in final carry */
rlwinm r3,r0,16,0,31 /* fold two halves together */
add r3,r0,r3
not r3,r3
srwi r3,r3,16
blr
/* /*
* computes the checksum of a memory block at buff, length len, * computes the checksum of a memory block at buff, length len,
* and adds in "sum" (32-bit) * and adds in "sum" (32-bit)
* *
* csum_partial(buff, len, sum) * __csum_partial(buff, len, sum)
*/ */
_GLOBAL(csum_partial) _GLOBAL(__csum_partial)
addic r0,r5,0
subi r3,r3,4 subi r3,r3,4
srwi. r6,r4,2 srawi. r6,r4,2 /* Divide len by 4 and also clear carry */
beq 3f /* if we're doing < 4 bytes */ beq 3f /* if we're doing < 4 bytes */
andi. r5,r3,2 /* Align buffer to longword boundary */ andi. r0,r3,2 /* Align buffer to longword boundary */
beq+ 1f beq+ 1f
lhz r5,4(r3) /* do 2 bytes to get aligned */ lhz r0,4(r3) /* do 2 bytes to get aligned */
addi r3,r3,2
subi r4,r4,2 subi r4,r4,2
addc r0,r0,r5 addi r3,r3,2
srwi. r6,r4,2 /* # words to do */ srwi. r6,r4,2 /* # words to do */
adde r5,r5,r0
beq 3f beq 3f
1: mtctr r6 1: andi. r6,r6,3 /* Prepare to handle words 4 by 4 */
2: lwzu r5,4(r3) /* the bdnz has zero overhead, so it should */ beq 21f
adde r0,r0,r5 /* be unnecessary to unroll this loop */ mtctr r6
2: lwzu r0,4(r3)
adde r5,r5,r0
bdnz 2b bdnz 2b
andi. r4,r4,3 21: srwi. r6,r4,4 /* # blocks of 4 words to do */
3: cmpwi 0,r4,2 beq 3f
blt+ 4f mtctr r6
lhz r5,4(r3) 22: lwz r0,4(r3)
lwz r6,8(r3)
lwz r7,12(r3)
lwzu r8,16(r3)
adde r5,r5,r0
adde r5,r5,r6
adde r5,r5,r7
adde r5,r5,r8
bdnz 22b
3: andi. r0,r4,2
beq+ 4f
lhz r0,4(r3)
addi r3,r3,2 addi r3,r3,2
subi r4,r4,2 adde r5,r5,r0
adde r0,r0,r5 4: andi. r0,r4,1
4: cmpwi 0,r4,1 beq+ 5f
bne+ 5f lbz r0,4(r3)
lbz r5,4(r3) slwi r0,r0,8 /* Upper byte of word */
slwi r5,r5,8 /* Upper byte of word */ adde r5,r5,r0
adde r0,r0,r5 5: addze r3,r5 /* add in final carry */
5: addze r3,r0 /* add in final carry */
blr blr
/* /*
...@@ -87,123 +78,220 @@ _GLOBAL(csum_partial) ...@@ -87,123 +78,220 @@ _GLOBAL(csum_partial)
* *
* csum_partial_copy_generic(src, dst, len, sum, src_err, dst_err) * csum_partial_copy_generic(src, dst, len, sum, src_err, dst_err)
*/ */
#define CSUM_COPY_16_BYTES_WITHEX(n) \
8 ## n ## 0: \
lwz r7,4(r4); \
8 ## n ## 1: \
lwz r8,8(r4); \
8 ## n ## 2: \
lwz r9,12(r4); \
8 ## n ## 3: \
lwzu r10,16(r4); \
8 ## n ## 4: \
stw r7,4(r6); \
adde r12,r12,r7; \
8 ## n ## 5: \
stw r8,8(r6); \
adde r12,r12,r8; \
8 ## n ## 6: \
stw r9,12(r6); \
adde r12,r12,r9; \
8 ## n ## 7: \
stwu r10,16(r6); \
adde r12,r12,r10
#define CSUM_COPY_16_BYTES_EXCODE(n) \
.section __ex_table,"a"; \
.align 2; \
.long 8 ## n ## 0b,src_error; \
.long 8 ## n ## 1b,src_error; \
.long 8 ## n ## 2b,src_error; \
.long 8 ## n ## 3b,src_error; \
.long 8 ## n ## 4b,dst_error; \
.long 8 ## n ## 5b,dst_error; \
.long 8 ## n ## 6b,dst_error; \
.long 8 ## n ## 7b,dst_error; \
.text
.text
.stabs "arch/powerpc/lib/",N_SO,0,0,0f
.stabs "checksum_32.S",N_SO,0,0,0f
0:
CACHELINE_BYTES = L1_CACHE_BYTES
LG_CACHELINE_BYTES = L1_CACHE_SHIFT
CACHELINE_MASK = (L1_CACHE_BYTES-1)
_GLOBAL(csum_partial_copy_generic) _GLOBAL(csum_partial_copy_generic)
addic r0,r6,0 stwu r1,-16(r1)
subi r3,r3,4 stw r7,12(r1)
subi r4,r4,4 stw r8,8(r1)
srwi. r6,r5,2
beq 3f /* if we're doing < 4 bytes */ andi. r0,r4,1 /* is destination address even ? */
andi. r9,r4,2 /* Align dst to longword boundary */ cmplwi cr7,r0,0
beq+ 1f addic r12,r6,0
81: lhz r6,4(r3) /* do 2 bytes to get aligned */ addi r6,r4,-4
addi r3,r3,2 neg r0,r4
subi r5,r5,2 addi r4,r3,-4
91: sth r6,4(r4) andi. r0,r0,CACHELINE_MASK /* # bytes to start of cache line */
addi r4,r4,2 beq 58f
addc r0,r0,r6
srwi. r6,r5,2 /* # words to do */ cmplw 0,r5,r0 /* is this more than total to do? */
beq 3f blt 63f /* if not much to do */
1: srwi. r6,r5,4 /* # groups of 4 words to do */ andi. r8,r0,3 /* get it word-aligned first */
beq 10f mtctr r8
mtctr r6 beq+ 61f
71: lwz r6,4(r3) li r3,0
72: lwz r9,8(r3) 70: lbz r9,4(r4) /* do some bytes */
73: lwz r10,12(r3) addi r4,r4,1
74: lwzu r11,16(r3) slwi r3,r3,8
adde r0,r0,r6 rlwimi r3,r9,0,24,31
75: stw r6,4(r4) 71: stb r9,4(r6)
adde r0,r0,r9 addi r6,r6,1
76: stw r9,8(r4) bdnz 70b
adde r0,r0,r10 adde r12,r12,r3
77: stw r10,12(r4) 61: subf r5,r0,r5
adde r0,r0,r11 srwi. r0,r0,2
78: stwu r11,16(r4) mtctr r0
bdnz 71b beq 58f
10: rlwinm. r6,r5,30,30,31 /* # words left to do */ 72: lwzu r9,4(r4) /* do some words */
beq 13f adde r12,r12,r9
mtctr r6 73: stwu r9,4(r6)
82: lwzu r9,4(r3) bdnz 72b
92: stwu r9,4(r4)
adde r0,r0,r9 58: srwi. r0,r5,LG_CACHELINE_BYTES /* # complete cachelines */
bdnz 82b clrlwi r5,r5,32-LG_CACHELINE_BYTES
13: andi. r5,r5,3 li r11,4
3: cmpwi 0,r5,2 beq 63f
blt+ 4f
83: lhz r6,4(r3) /* Here we decide how far ahead to prefetch the source */
addi r3,r3,2 li r3,4
subi r5,r5,2 cmpwi r0,1
93: sth r6,4(r4) li r7,0
ble 114f
li r7,1
#if MAX_COPY_PREFETCH > 1
/* Heuristically, for large transfers we prefetch
MAX_COPY_PREFETCH cachelines ahead. For small transfers
we prefetch 1 cacheline ahead. */
cmpwi r0,MAX_COPY_PREFETCH
ble 112f
li r7,MAX_COPY_PREFETCH
112: mtctr r7
111: dcbt r3,r4
addi r3,r3,CACHELINE_BYTES
bdnz 111b
#else
dcbt r3,r4
addi r3,r3,CACHELINE_BYTES
#endif /* MAX_COPY_PREFETCH > 1 */
114: subf r8,r7,r0
mr r0,r7
mtctr r8
53: dcbt r3,r4
54: dcbz r11,r6
/* the main body of the cacheline loop */
CSUM_COPY_16_BYTES_WITHEX(0)
#if L1_CACHE_BYTES >= 32
CSUM_COPY_16_BYTES_WITHEX(1)
#if L1_CACHE_BYTES >= 64
CSUM_COPY_16_BYTES_WITHEX(2)
CSUM_COPY_16_BYTES_WITHEX(3)
#if L1_CACHE_BYTES >= 128
CSUM_COPY_16_BYTES_WITHEX(4)
CSUM_COPY_16_BYTES_WITHEX(5)
CSUM_COPY_16_BYTES_WITHEX(6)
CSUM_COPY_16_BYTES_WITHEX(7)
#endif
#endif
#endif
bdnz 53b
cmpwi r0,0
li r3,4
li r7,0
bne 114b
63: srwi. r0,r5,2
mtctr r0
beq 64f
30: lwzu r0,4(r4)
adde r12,r12,r0
31: stwu r0,4(r6)
bdnz 30b
64: andi. r0,r5,2
beq+ 65f
40: lhz r0,4(r4)
addi r4,r4,2 addi r4,r4,2
adde r0,r0,r6 41: sth r0,4(r6)
4: cmpwi 0,r5,1 adde r12,r12,r0
bne+ 5f addi r6,r6,2
84: lbz r6,4(r3) 65: andi. r0,r5,1
94: stb r6,4(r4) beq+ 66f
slwi r6,r6,8 /* Upper byte of word */ 50: lbz r0,4(r4)
adde r0,r0,r6 51: stb r0,4(r6)
5: addze r3,r0 /* add in final carry */ slwi r0,r0,8
adde r12,r12,r0
66: addze r3,r12
addi r1,r1,16
beqlr+ cr7
rlwinm r3,r3,8,0,31 /* swap bytes for odd destination */
blr blr
/* These shouldn't go in the fixup section, since that would /* read fault */
cause the ex_table addresses to get out of order. */
src_error_4:
mfctr r6 /* update # bytes remaining from ctr */
rlwimi r5,r6,4,0,27
b 79f
src_error_1:
li r6,0
subi r5,r5,2
95: sth r6,4(r4)
addi r4,r4,2
79: srwi. r6,r5,2
beq 3f
mtctr r6
src_error_2:
li r6,0
96: stwu r6,4(r4)
bdnz 96b
3: andi. r5,r5,3
beq src_error
src_error_3:
li r6,0
mtctr r5
addi r4,r4,3
97: stbu r6,1(r4)
bdnz 97b
src_error: src_error:
cmpwi 0,r7,0 lwz r7,12(r1)
beq 1f addi r1,r1,16
li r6,-EFAULT cmpwi cr0,r7,0
stw r6,0(r7) beqlr
1: addze r3,r0 li r0,-EFAULT
stw r0,0(r7)
blr blr
/* write fault */
dst_error: dst_error:
cmpwi 0,r8,0 lwz r8,8(r1)
beq 1f addi r1,r1,16
li r6,-EFAULT cmpwi cr0,r8,0
stw r6,0(r8) beqlr
1: addze r3,r0 li r0,-EFAULT
stw r0,0(r8)
blr blr
.section __ex_table,"a" .section __ex_table,"a"
.long 81b,src_error_1 .align 2
.long 91b,dst_error .long 70b,src_error
.long 71b,src_error_4 .long 71b,dst_error
.long 72b,src_error_4 .long 72b,src_error
.long 73b,src_error_4 .long 73b,dst_error
.long 74b,src_error_4 .long 54b,dst_error
.long 75b,dst_error .text
.long 76b,dst_error
.long 77b,dst_error /*
.long 78b,dst_error * this stuff handles faults in the cacheline loop and branches to either
.long 82b,src_error_2 * src_error (if in read part) or dst_error (if in write part)
.long 92b,dst_error */
.long 83b,src_error_3 CSUM_COPY_16_BYTES_EXCODE(0)
.long 93b,dst_error #if L1_CACHE_BYTES >= 32
.long 84b,src_error_3 CSUM_COPY_16_BYTES_EXCODE(1)
.long 94b,dst_error #if L1_CACHE_BYTES >= 64
.long 95b,dst_error CSUM_COPY_16_BYTES_EXCODE(2)
.long 96b,dst_error CSUM_COPY_16_BYTES_EXCODE(3)
.long 97b,dst_error #if L1_CACHE_BYTES >= 128
CSUM_COPY_16_BYTES_EXCODE(4)
CSUM_COPY_16_BYTES_EXCODE(5)
CSUM_COPY_16_BYTES_EXCODE(6)
CSUM_COPY_16_BYTES_EXCODE(7)
#endif
#endif
#endif
.section __ex_table,"a"
.align 2
.long 30b,src_error
.long 31b,dst_error
.long 40b,src_error
.long 41b,dst_error
.long 50b,src_error
.long 51b,dst_error
arch/powerpc/lib/checksum_64.S
浏览文件 @ a1b53446
...@@ -17,40 +17,13 @@ ...@@ -17,40 +17,13 @@
#include <asm/errno.h> #include <asm/errno.h>
#include <asm/ppc_asm.h> #include <asm/ppc_asm.h>
/*
* ip_fast_csum(r3=buf, r4=len) -- Optimized for IP header
* len is in words and is always >= 5.
*
* In practice len == 5, but this is not guaranteed. So this code does not
* attempt to use doubleword instructions.
*/
_GLOBAL(ip_fast_csum)
lwz r0,0(r3)
lwzu r5,4(r3)
addic. r4,r4,-2
addc r0,r0,r5
mtctr r4
blelr-
1: lwzu r4,4(r3)
adde r0,r0,r4
bdnz 1b
addze r0,r0 /* add in final carry */
rldicl r4,r0,32,0 /* fold two 32-bit halves together */
add r0,r0,r4
srdi r0,r0,32
rlwinm r3,r0,16,0,31 /* fold two halves together */
add r3,r0,r3
not r3,r3
srwi r3,r3,16
blr
/* /*
* Computes the checksum of a memory block at buff, length len, * Computes the checksum of a memory block at buff, length len,
* and adds in "sum" (32-bit). * and adds in "sum" (32-bit).
* *
* csum_partial(r3=buff, r4=len, r5=sum) * __csum_partial(r3=buff, r4=len, r5=sum)
*/ */
_GLOBAL(csum_partial) _GLOBAL(__csum_partial)
addic r0,r5,0 /* clear carry */ addic r0,r5,0 /* clear carry */
srdi. r6,r4,3 /* less than 8 bytes? */ srdi. r6,r4,3 /* less than 8 bytes? */
......
arch/powerpc/lib/ppc_ksyms.c
浏览文件 @ a1b53446
...@@ -17,10 +17,8 @@ EXPORT_SYMBOL(strcmp); ...@@ -17,10 +17,8 @@ EXPORT_SYMBOL(strcmp);
EXPORT_SYMBOL(strncmp); EXPORT_SYMBOL(strncmp);
#ifndef CONFIG_GENERIC_CSUM #ifndef CONFIG_GENERIC_CSUM
EXPORT_SYMBOL(csum_partial); EXPORT_SYMBOL(__csum_partial);
EXPORT_SYMBOL(csum_partial_copy_generic); EXPORT_SYMBOL(csum_partial_copy_generic);
EXPORT_SYMBOL(ip_fast_csum);
EXPORT_SYMBOL(csum_tcpudp_magic);
#endif #endif
EXPORT_SYMBOL(__copy_tofrom_user); EXPORT_SYMBOL(__copy_tofrom_user);
......
arch/powerpc/mm/8xx_mmu.c 0 → 100644
浏览文件 @ a1b53446
/*
* This file contains the routines for initializing the MMU
* on the 8xx series of chips.
* -- christophe
*
* Derived from arch/powerpc/mm/40x_mmu.c:
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*
*/
#include <linux/memblock.h>
#include "mmu_decl.h"
extern int __map_without_ltlbs;
/*
* MMU_init_hw does the chip-specific initialization of the MMU hardware.
*/
void __init MMU_init_hw(void)
{
/* Nothing to do for the time being but keep it similar to other PPC */
}
#define LARGE_PAGE_SIZE_4M (1<<22)
#define LARGE_PAGE_SIZE_8M (1<<23)
#define LARGE_PAGE_SIZE_64M (1<<26)
unsigned long __init mmu_mapin_ram(unsigned long top)
{
unsigned long v, s, mapped;
phys_addr_t p;
v = KERNELBASE;
p = 0;
s = top;
if (__map_without_ltlbs)
return 0;
#ifdef CONFIG_PPC_4K_PAGES
while (s >= LARGE_PAGE_SIZE_8M) {
pmd_t *pmdp;
unsigned long val = p | MD_PS8MEG;
pmdp = pmd_offset(pud_offset(pgd_offset_k(v), v), v);
*pmdp++ = __pmd(val);
*pmdp++ = __pmd(val + LARGE_PAGE_SIZE_4M);
v += LARGE_PAGE_SIZE_8M;
p += LARGE_PAGE_SIZE_8M;
s -= LARGE_PAGE_SIZE_8M;
}
#else /* CONFIG_PPC_16K_PAGES */
while (s >= LARGE_PAGE_SIZE_64M) {
pmd_t *pmdp;
unsigned long val = p | MD_PS8MEG;
pmdp = pmd_offset(pud_offset(pgd_offset_k(v), v), v);
*pmdp++ = __pmd(val);
v += LARGE_PAGE_SIZE_64M;
p += LARGE_PAGE_SIZE_64M;
s -= LARGE_PAGE_SIZE_64M;
}
#endif
mapped = top - s;
/* If the size of RAM is not an exact power of two, we may not
* have covered RAM in its entirety with 8 MiB
* pages. Consequently, restrict the top end of RAM currently
* allocable so that calls to the MEMBLOCK to allocate PTEs for "tail"
* coverage with normal-sized pages (or other reasons) do not
* attempt to allocate outside the allowed range.
*/
memblock_set_current_limit(mapped);
return mapped;
}
void setup_initial_memory_limit(phys_addr_t first_memblock_base,
phys_addr_t first_memblock_size)
{
/* We don't currently support the first MEMBLOCK not mapping 0
* physical on those processors
*/
BUG_ON(first_memblock_base != 0);
#ifdef CONFIG_PIN_TLB
/* 8xx can only access 24MB at the moment */
memblock_set_current_limit(min_t(u64, first_memblock_size, 0x01800000));
#else
/* 8xx can only access 8MB at the moment */
memblock_set_current_limit(min_t(u64, first_memblock_size, 0x00800000));
#endif
}
/*
* Set up to use a given MMU context.
* id is context number, pgd is PGD pointer.
*
* We place the physical address of the new task page directory loaded
* into the MMU base register, and set the ASID compare register with
* the new "context."
*/
void set_context(unsigned long id, pgd_t *pgd)
{
s16 offset = (s16)(__pa(swapper_pg_dir));
#ifdef CONFIG_BDI_SWITCH
pgd_t **ptr = *(pgd_t ***)(KERNELBASE + 0xf0);
/* Context switch the PTE pointer for the Abatron BDI2000.
* The PGDIR is passed as second argument.
*/
*(ptr + 1) = pgd;
#endif
/* Register M_TW will contain base address of level 1 table minus the
* lower part of the kernel PGDIR base address, so that all accesses to
* level 1 table are done relative to lower part of kernel PGDIR base
* address.
*/
mtspr(SPRN_M_TW, __pa(pgd) - offset);
/* Update context */
mtspr(SPRN_M_CASID, id);
/* sync */
mb();
}
void flush_instruction_cache(void)
{
isync();
mtspr(SPRN_IC_CST, IDC_INVALL);
isync();
}
arch/powerpc/mm/Makefile
浏览文件 @ a1b53446
...@@ -25,6 +25,7 @@ obj-$(CONFIG_PPC_ICSWX) += icswx.o ...@@ -25,6 +25,7 @@ obj-$(CONFIG_PPC_ICSWX) += icswx.o
obj-$(CONFIG_PPC_ICSWX_PID) += icswx_pid.o obj-$(CONFIG_PPC_ICSWX_PID) += icswx_pid.o
obj-$(CONFIG_40x) += 40x_mmu.o obj-$(CONFIG_40x) += 40x_mmu.o
obj-$(CONFIG_44x) += 44x_mmu.o obj-$(CONFIG_44x) += 44x_mmu.o
obj-$(CONFIG_PPC_8xx) += 8xx_mmu.o
obj-$(CONFIG_PPC_FSL_BOOK3E) += fsl_booke_mmu.o obj-$(CONFIG_PPC_FSL_BOOK3E) += fsl_booke_mmu.o
obj-$(CONFIG_NEED_MULTIPLE_NODES) += numa.o obj-$(CONFIG_NEED_MULTIPLE_NODES) += numa.o
obj-$(CONFIG_PPC_SPLPAR) += vphn.o obj-$(CONFIG_PPC_SPLPAR) += vphn.o
......
arch/powerpc/mm/dma-noncoherent.c
浏览文件 @ a1b53446
...@@ -327,7 +327,7 @@ void __dma_sync(void *vaddr, size_t size, int direction) ...@@ -327,7 +327,7 @@ void __dma_sync(void *vaddr, size_t size, int direction)
* invalidate only when cache-line aligned otherwise there is * invalidate only when cache-line aligned otherwise there is
* the potential for discarding uncommitted data from the cache * the potential for discarding uncommitted data from the cache
*/ */
if ((start & (L1_CACHE_BYTES - 1)) || (size & (L1_CACHE_BYTES - 1))) if ((start | end) & (L1_CACHE_BYTES - 1))
flush_dcache_range(start, end); flush_dcache_range(start, end);
else else
invalidate_dcache_range(start, end); invalidate_dcache_range(start, end);
......
arch/powerpc/mm/fsl_booke_mmu.c
浏览文件 @ a1b53446
...@@ -72,10 +72,11 @@ unsigned long tlbcam_sz(int idx) ...@@ -72,10 +72,11 @@ unsigned long tlbcam_sz(int idx)
return tlbcam_addrs[idx].limit - tlbcam_addrs[idx].start + 1; return tlbcam_addrs[idx].limit - tlbcam_addrs[idx].start + 1;
} }
#ifdef CONFIG_FSL_BOOKE
/* /*
* Return PA for this VA if it is mapped by a CAM, or 0 * Return PA for this VA if it is mapped by a CAM, or 0
*/ */
phys_addr_t v_mapped_by_tlbcam(unsigned long va) phys_addr_t v_block_mapped(unsigned long va)
{ {
int b; int b;
for (b = 0; b < tlbcam_index; ++b) for (b = 0; b < tlbcam_index; ++b)
...@@ -87,7 +88,7 @@ phys_addr_t v_mapped_by_tlbcam(unsigned long va) ...@@ -87,7 +88,7 @@ phys_addr_t v_mapped_by_tlbcam(unsigned long va)
/* /*
* Return VA for a given PA or 0 if not mapped * Return VA for a given PA or 0 if not mapped
*/ */
unsigned long p_mapped_by_tlbcam(phys_addr_t pa) unsigned long p_block_mapped(phys_addr_t pa)
{ {
int b; int b;
for (b = 0; b < tlbcam_index; ++b) for (b = 0; b < tlbcam_index; ++b)
...@@ -97,6 +98,7 @@ unsigned long p_mapped_by_tlbcam(phys_addr_t pa) ...@@ -97,6 +98,7 @@ unsigned long p_mapped_by_tlbcam(phys_addr_t pa)
return tlbcam_addrs[b].start+(pa-tlbcam_addrs[b].phys); return tlbcam_addrs[b].start+(pa-tlbcam_addrs[b].phys);
return 0; return 0;
} }
#endif
/* /*
* Set up a variable-size TLB entry (tlbcam). The parameters are not checked; * Set up a variable-size TLB entry (tlbcam). The parameters are not checked;
......
arch/powerpc/mm/init_32.c
浏览文件 @ a1b53446
...@@ -178,10 +178,6 @@ void __init MMU_init(void) ...@@ -178,10 +178,6 @@ void __init MMU_init(void)
/* Initialize early top-down ioremap allocator */ /* Initialize early top-down ioremap allocator */
ioremap_bot = IOREMAP_TOP; ioremap_bot = IOREMAP_TOP;
/* Map in I/O resources */
if (ppc_md.progress)
ppc_md.progress("MMU:setio", 0x302);
if (ppc_md.progress) if (ppc_md.progress)
ppc_md.progress("MMU:exit", 0x211); ppc_md.progress("MMU:exit", 0x211);
...@@ -193,22 +189,3 @@ void __init MMU_init(void) ...@@ -193,22 +189,3 @@ void __init MMU_init(void)
/* Shortly after that, the entire linear mapping will be available */ /* Shortly after that, the entire linear mapping will be available */
memblock_set_current_limit(lowmem_end_addr); memblock_set_current_limit(lowmem_end_addr);
} }
#ifdef CONFIG_8xx /* No 8xx specific .c file to put that in ... */
void setup_initial_memory_limit(phys_addr_t first_memblock_base,
phys_addr_t first_memblock_size)
{
/* We don't currently support the first MEMBLOCK not mapping 0
* physical on those processors
*/
BUG_ON(first_memblock_base != 0);
#ifdef CONFIG_PIN_TLB
/* 8xx can only access 24MB at the moment */
memblock_set_current_limit(min_t(u64, first_memblock_size, 0x01800000));
#else
/* 8xx can only access 8MB at the moment */
memblock_set_current_limit(min_t(u64, first_memblock_size, 0x00800000));
#endif
}
#endif /* CONFIG_8xx */
arch/powerpc/mm/mmu_decl.h
浏览文件 @ a1b53446
...@@ -100,7 +100,6 @@ extern void setbat(int index, unsigned long virt, phys_addr_t phys, ...@@ -100,7 +100,6 @@ extern void setbat(int index, unsigned long virt, phys_addr_t phys,
extern int __map_without_bats; extern int __map_without_bats;
extern int __allow_ioremap_reserved; extern int __allow_ioremap_reserved;
extern unsigned long ioremap_base;
extern unsigned int rtas_data, rtas_size; extern unsigned int rtas_data, rtas_size;
struct hash_pte; struct hash_pte;
...@@ -133,22 +132,17 @@ extern void wii_memory_fixups(void); ...@@ -133,22 +132,17 @@ extern void wii_memory_fixups(void);
/* ...and now those things that may be slightly different between processor /* ...and now those things that may be slightly different between processor
* architectures. -- Dan * architectures. -- Dan
*/ */
#if defined(CONFIG_8xx) #ifdef CONFIG_PPC32
#define MMU_init_hw() do { } while(0)
#define mmu_mapin_ram(top) (0UL)
#elif defined(CONFIG_4xx)
extern void MMU_init_hw(void); extern void MMU_init_hw(void);
extern unsigned long mmu_mapin_ram(unsigned long top); extern unsigned long mmu_mapin_ram(unsigned long top);
#endif
#elif defined(CONFIG_PPC_FSL_BOOK3E) #ifdef CONFIG_PPC_FSL_BOOK3E
extern unsigned long map_mem_in_cams(unsigned long ram, int max_cam_idx, extern unsigned long map_mem_in_cams(unsigned long ram, int max_cam_idx,
bool dryrun); bool dryrun);
extern unsigned long calc_cam_sz(unsigned long ram, unsigned long virt, extern unsigned long calc_cam_sz(unsigned long ram, unsigned long virt,
phys_addr_t phys); phys_addr_t phys);
#ifdef CONFIG_PPC32 #ifdef CONFIG_PPC32
extern void MMU_init_hw(void);
extern unsigned long mmu_mapin_ram(unsigned long top);
extern void adjust_total_lowmem(void); extern void adjust_total_lowmem(void);
extern int switch_to_as1(void); extern int switch_to_as1(void);
extern void restore_to_as0(int esel, int offset, void *dt_ptr, int bootcpu); extern void restore_to_as0(int esel, int offset, void *dt_ptr, int bootcpu);
...@@ -163,8 +157,14 @@ struct tlbcam { ...@@ -163,8 +157,14 @@ struct tlbcam {
u32 MAS3; u32 MAS3;
u32 MAS7; u32 MAS7;
}; };
#elif defined(CONFIG_PPC32) #endif
/* anything 32-bit except 4xx or 8xx */
extern void MMU_init_hw(void); #if defined(CONFIG_6xx) || defined(CONFIG_FSL_BOOKE)
extern unsigned long mmu_mapin_ram(unsigned long top); /* 6xx have BATS */
/* FSL_BOOKE have TLBCAM */
phys_addr_t v_block_mapped(unsigned long va);
unsigned long p_block_mapped(phys_addr_t pa);
#else
static inline phys_addr_t v_block_mapped(unsigned long va) { return 0; }
static inline unsigned long p_block_mapped(phys_addr_t pa) { return 0; }
#endif #endif
arch/powerpc/mm/pgtable_32.c
浏览文件 @ a1b53446
...@@ -37,35 +37,10 @@ ...@@ -37,35 +37,10 @@
#include "mmu_decl.h" #include "mmu_decl.h"
unsigned long ioremap_base;
unsigned long ioremap_bot; unsigned long ioremap_bot;
EXPORT_SYMBOL(ioremap_bot); /* aka VMALLOC_END */ EXPORT_SYMBOL(ioremap_bot); /* aka VMALLOC_END */
#ifdef CONFIG_6xx extern char etext[], _stext[], _sinittext[], _einittext[];
#define HAVE_BATS 1
#endif
#if defined(CONFIG_FSL_BOOKE)
#define HAVE_TLBCAM 1
#endif
extern char etext[], _stext[];
#ifdef HAVE_BATS
extern phys_addr_t v_mapped_by_bats(unsigned long va);
extern unsigned long p_mapped_by_bats(phys_addr_t pa);
#else /* !HAVE_BATS */
#define v_mapped_by_bats(x) (0UL)
#define p_mapped_by_bats(x) (0UL)
#endif /* HAVE_BATS */
#ifdef HAVE_TLBCAM
extern phys_addr_t v_mapped_by_tlbcam(unsigned long va);
extern unsigned long p_mapped_by_tlbcam(phys_addr_t pa);
#else /* !HAVE_TLBCAM */
#define v_mapped_by_tlbcam(x) (0UL)
#define p_mapped_by_tlbcam(x) (0UL)
#endif /* HAVE_TLBCAM */
#define PGDIR_ORDER (32 + PGD_T_LOG2 - PGDIR_SHIFT) #define PGDIR_ORDER (32 + PGD_T_LOG2 - PGDIR_SHIFT)
...@@ -197,7 +172,7 @@ __ioremap_caller(phys_addr_t addr, unsigned long size, unsigned long flags, ...@@ -197,7 +172,7 @@ __ioremap_caller(phys_addr_t addr, unsigned long size, unsigned long flags,
/* /*
* Choose an address to map it to. * Choose an address to map it to.
* Once the vmalloc system is running, we use it. * Once the vmalloc system is running, we use it.
* Before then, we use space going down from ioremap_base * Before then, we use space going down from IOREMAP_TOP
* (ioremap_bot records where we're up to). * (ioremap_bot records where we're up to).
*/ */
p = addr & PAGE_MASK; p = addr & PAGE_MASK;
...@@ -228,19 +203,10 @@ __ioremap_caller(phys_addr_t addr, unsigned long size, unsigned long flags, ...@@ -228,19 +203,10 @@ __ioremap_caller(phys_addr_t addr, unsigned long size, unsigned long flags,
/* /*
* Is it already mapped? Perhaps overlapped by a previous * Is it already mapped? Perhaps overlapped by a previous
* BAT mapping. If the whole area is mapped then we're done, * mapping.
* otherwise remap it since we want to keep the virt addrs for
* each request contiguous.
*
* We make the assumption here that if the bottom and top
* of the range we want are mapped then it's mapped to the
* same virt address (and this is contiguous).
* -- Cort
*/ */
if ((v = p_mapped_by_bats(p)) /*&& p_mapped_by_bats(p+size-1)*/ ) v = p_block_mapped(p);
goto out; if (v)
if ((v = p_mapped_by_tlbcam(p)))
goto out; goto out;
if (slab_is_available()) { if (slab_is_available()) {
...@@ -278,7 +244,8 @@ void iounmap(volatile void __iomem *addr) ...@@ -278,7 +244,8 @@ void iounmap(volatile void __iomem *addr)
* If mapped by BATs then there is nothing to do. * If mapped by BATs then there is nothing to do.
* Calling vfree() generates a benign warning. * Calling vfree() generates a benign warning.
*/ */
if (v_mapped_by_bats((unsigned long)addr)) return; if (v_block_mapped((unsigned long)addr))
return;
if (addr > high_memory && (unsigned long) addr < ioremap_bot) if (addr > high_memory && (unsigned long) addr < ioremap_bot)
vunmap((void *) (PAGE_MASK & (unsigned long)addr)); vunmap((void *) (PAGE_MASK & (unsigned long)addr));
...@@ -322,7 +289,8 @@ void __init __mapin_ram_chunk(unsigned long offset, unsigned long top) ...@@ -322,7 +289,8 @@ void __init __mapin_ram_chunk(unsigned long offset, unsigned long top)
v = PAGE_OFFSET + s; v = PAGE_OFFSET + s;
p = memstart_addr + s; p = memstart_addr + s;
for (; s < top; s += PAGE_SIZE) { for (; s < top; s += PAGE_SIZE) {
ktext = ((char *) v >= _stext && (char *) v < etext); ktext = ((char *)v >= _stext && (char *)v < etext) ||
((char *)v >= _sinittext && (char *)v < _einittext);
f = ktext ? pgprot_val(PAGE_KERNEL_TEXT) : pgprot_val(PAGE_KERNEL); f = ktext ? pgprot_val(PAGE_KERNEL_TEXT) : pgprot_val(PAGE_KERNEL);
map_page(v, p, f); map_page(v, p, f);
#ifdef CONFIG_PPC_STD_MMU_32 #ifdef CONFIG_PPC_STD_MMU_32
...@@ -403,7 +371,7 @@ static int __change_page_attr(struct page *page, pgprot_t prot) ...@@ -403,7 +371,7 @@ static int __change_page_attr(struct page *page, pgprot_t prot)
BUG_ON(PageHighMem(page)); BUG_ON(PageHighMem(page));
address = (unsigned long)page_address(page); address = (unsigned long)page_address(page);
if (v_mapped_by_bats(address) || v_mapped_by_tlbcam(address)) if (v_block_mapped(address))
return 0; return 0;
if (!get_pteptr(&init_mm, address, &kpte, &kpmd)) if (!get_pteptr(&init_mm, address, &kpte, &kpmd))
return -EINVAL; return -EINVAL;
......
arch/powerpc/mm/ppc_mmu_32.c
浏览文件 @ a1b53446
...@@ -49,7 +49,7 @@ struct batrange { /* stores address ranges mapped by BATs */ ...@@ -49,7 +49,7 @@ struct batrange { /* stores address ranges mapped by BATs */
/* /*
* Return PA for this VA if it is mapped by a BAT, or 0 * Return PA for this VA if it is mapped by a BAT, or 0
*/ */
phys_addr_t v_mapped_by_bats(unsigned long va) phys_addr_t v_block_mapped(unsigned long va)
{ {
int b; int b;
for (b = 0; b < 4; ++b) for (b = 0; b < 4; ++b)
...@@ -61,7 +61,7 @@ phys_addr_t v_mapped_by_bats(unsigned long va) ...@@ -61,7 +61,7 @@ phys_addr_t v_mapped_by_bats(unsigned long va)
/* /*
* Return VA for a given PA or 0 if not mapped * Return VA for a given PA or 0 if not mapped
*/ */
unsigned long p_mapped_by_bats(phys_addr_t pa) unsigned long p_block_mapped(phys_addr_t pa)
{ {
int b; int b;
for (b = 0; b < 4; ++b) for (b = 0; b < 4; ++b)
......
arch/powerpc/mm/tlb_nohash.c
浏览文件 @ a1b53446
...@@ -640,9 +640,7 @@ static void early_init_this_mmu(void) ...@@ -640,9 +640,7 @@ static void early_init_this_mmu(void)
* transient mapping would cause problems. * transient mapping would cause problems.
*/ */
#ifdef CONFIG_SMP #ifdef CONFIG_SMP
if (cpu != boot_cpuid && if (hweight32(get_tensr()) > 1)
(cpu != cpu_first_thread_sibling(cpu) ||
cpu == cpu_first_thread_sibling(boot_cpuid)))
map = false; map = false;
#endif #endif
......
arch/powerpc/platforms/85xx/Kconfig
浏览文件 @ a1b53446
...@@ -8,6 +8,7 @@ menuconfig FSL_SOC_BOOKE ...@@ -8,6 +8,7 @@ menuconfig FSL_SOC_BOOKE
select FSL_PCI if PCI select FSL_PCI if PCI
select SERIAL_8250_EXTENDED if SERIAL_8250 select SERIAL_8250_EXTENDED if SERIAL_8250
select SERIAL_8250_SHARE_IRQ if SERIAL_8250 select SERIAL_8250_SHARE_IRQ if SERIAL_8250
select FSL_CORENET_RCPM if PPC_E500MC
default y default y
if FSL_SOC_BOOKE if FSL_SOC_BOOKE
......
arch/powerpc/platforms/85xx/Makefile
浏览文件 @ a1b53446
...@@ -2,6 +2,7 @@ ...@@ -2,6 +2,7 @@
# Makefile for the PowerPC 85xx linux kernel. # Makefile for the PowerPC 85xx linux kernel.
# #
obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_SMP) += smp.o
obj-$(CONFIG_FSL_PMC) += mpc85xx_pm_ops.o
obj-y += common.o obj-y += common.o
......
arch/powerpc/platforms/85xx/common.c
浏览文件 @ a1b53446
...@@ -9,11 +9,14 @@ ...@@ -9,11 +9,14 @@
#include <linux/of_irq.h> #include <linux/of_irq.h>
#include <linux/of_platform.h> #include <linux/of_platform.h>
#include <asm/fsl_pm.h>
#include <soc/fsl/qe/qe.h> #include <soc/fsl/qe/qe.h>
#include <sysdev/cpm2_pic.h> #include <sysdev/cpm2_pic.h>
#include "mpc85xx.h" #include "mpc85xx.h"
const struct fsl_pm_ops *qoriq_pm_ops;
static const struct of_device_id mpc85xx_common_ids[] __initconst = { static const struct of_device_id mpc85xx_common_ids[] __initconst = {
{ .type = "soc", }, { .type = "soc", },
{ .compatible = "soc", }, { .compatible = "soc", },
......
arch/powerpc/platforms/85xx/mpc85xx_pm_ops.c 0 → 100644
浏览文件 @ a1b53446
/*
* MPC85xx PM operators
*
* Copyright 2015 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#define pr_fmt(fmt) "%s: " fmt, __func__
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/fsl/guts.h>
#include <asm/io.h>
#include <asm/fsl_pm.h>
static struct ccsr_guts __iomem *guts;
static void mpc85xx_irq_mask(int cpu)
{
}
static void mpc85xx_irq_unmask(int cpu)
{
}
static void mpc85xx_cpu_die(int cpu)
{
u32 tmp;
tmp = (mfspr(SPRN_HID0) & ~(HID0_DOZE|HID0_SLEEP)) | HID0_NAP;
mtspr(SPRN_HID0, tmp);
/* Enter NAP mode. */
tmp = mfmsr();
tmp |= MSR_WE;
asm volatile(
"msync\n"
"mtmsr %0\n"
"isync\n"
:
: "r" (tmp));
}
static void mpc85xx_cpu_up_prepare(int cpu)
{
}
static void mpc85xx_freeze_time_base(bool freeze)
{
uint32_t mask;
mask = CCSR_GUTS_DEVDISR_TB0 | CCSR_GUTS_DEVDISR_TB1;
if (freeze)
setbits32(&guts->devdisr, mask);
else
clrbits32(&guts->devdisr, mask);
in_be32(&guts->devdisr);
}
static const struct of_device_id mpc85xx_smp_guts_ids[] = {
{ .compatible = "fsl,mpc8572-guts", },
{ .compatible = "fsl,p1020-guts", },
{ .compatible = "fsl,p1021-guts", },
{ .compatible = "fsl,p1022-guts", },
{ .compatible = "fsl,p1023-guts", },
{ .compatible = "fsl,p2020-guts", },
{ .compatible = "fsl,bsc9132-guts", },
{},
};
static const struct fsl_pm_ops mpc85xx_pm_ops = {
.freeze_time_base = mpc85xx_freeze_time_base,
.irq_mask = mpc85xx_irq_mask,
.irq_unmask = mpc85xx_irq_unmask,
.cpu_die = mpc85xx_cpu_die,
.cpu_up_prepare = mpc85xx_cpu_up_prepare,
};
int __init mpc85xx_setup_pmc(void)
{
struct device_node *np;
np = of_find_matching_node(NULL, mpc85xx_smp_guts_ids);
if (np) {
guts = of_iomap(np, 0);
of_node_put(np);
if (!guts) {
pr_err("Could not map guts node address\n");
return -ENOMEM;
}
}
qoriq_pm_ops = &mpc85xx_pm_ops;
return 0;
}
arch/powerpc/platforms/85xx/smp.c
浏览文件 @ a1b53446
...@@ -2,7 +2,7 @@ ...@@ -2,7 +2,7 @@
* Author: Andy Fleming <afleming@freescale.com> * Author: Andy Fleming <afleming@freescale.com>
* Kumar Gala <galak@kernel.crashing.org> * Kumar Gala <galak@kernel.crashing.org>
* *
* Copyright 2006-2008, 2011-2012 Freescale Semiconductor Inc. * Copyright 2006-2008, 2011-2012, 2015 Freescale Semiconductor Inc.
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the * under the terms of the GNU General Public License as published by the
...@@ -15,7 +15,6 @@ ...@@ -15,7 +15,6 @@
#include <linux/init.h> #include <linux/init.h>
#include <linux/delay.h> #include <linux/delay.h>
#include <linux/of.h> #include <linux/of.h>
#include <linux/of_address.h>
#include <linux/kexec.h> #include <linux/kexec.h>
#include <linux/highmem.h> #include <linux/highmem.h>
#include <linux/cpu.h> #include <linux/cpu.h>
...@@ -29,6 +28,7 @@ ...@@ -29,6 +28,7 @@
#include <asm/dbell.h> #include <asm/dbell.h>
#include <asm/code-patching.h> #include <asm/code-patching.h>
#include <asm/cputhreads.h> #include <asm/cputhreads.h>
#include <asm/fsl_pm.h>
#include <sysdev/fsl_soc.h> #include <sysdev/fsl_soc.h>
#include <sysdev/mpic.h> #include <sysdev/mpic.h>
...@@ -43,35 +43,23 @@ struct epapr_spin_table { ...@@ -43,35 +43,23 @@ struct epapr_spin_table {
u32 pir; u32 pir;
}; };
static struct ccsr_guts __iomem *guts; #ifdef CONFIG_HOTPLUG_CPU
static u64 timebase; static u64 timebase;
static int tb_req; static int tb_req;
static int tb_valid; static int tb_valid;
static void mpc85xx_timebase_freeze(int freeze)
{
uint32_t mask;
mask = CCSR_GUTS_DEVDISR_TB0 | CCSR_GUTS_DEVDISR_TB1;
if (freeze)
setbits32(&guts->devdisr, mask);
else
clrbits32(&guts->devdisr, mask);
in_be32(&guts->devdisr);
}
static void mpc85xx_give_timebase(void) static void mpc85xx_give_timebase(void)
{ {
unsigned long flags; unsigned long flags;
local_irq_save(flags); local_irq_save(flags);
hard_irq_disable();
while (!tb_req) while (!tb_req)
barrier(); barrier();
tb_req = 0; tb_req = 0;
mpc85xx_timebase_freeze(1); qoriq_pm_ops->freeze_time_base(true);
#ifdef CONFIG_PPC64 #ifdef CONFIG_PPC64
/* /*
* e5500/e6500 have a workaround for erratum A-006958 in place * e5500/e6500 have a workaround for erratum A-006958 in place
...@@ -104,7 +92,7 @@ static void mpc85xx_give_timebase(void) ...@@ -104,7 +92,7 @@ static void mpc85xx_give_timebase(void)
while (tb_valid) while (tb_valid)
barrier(); barrier();
mpc85xx_timebase_freeze(0); qoriq_pm_ops->freeze_time_base(false);
local_irq_restore(flags); local_irq_restore(flags);
} }
...@@ -114,6 +102,7 @@ static void mpc85xx_take_timebase(void) ...@@ -114,6 +102,7 @@ static void mpc85xx_take_timebase(void)
unsigned long flags; unsigned long flags;
local_irq_save(flags); local_irq_save(flags);
hard_irq_disable();
tb_req = 1; tb_req = 1;
while (!tb_valid) while (!tb_valid)
...@@ -126,36 +115,54 @@ static void mpc85xx_take_timebase(void) ...@@ -126,36 +115,54 @@ static void mpc85xx_take_timebase(void)
local_irq_restore(flags); local_irq_restore(flags);
} }
#ifdef CONFIG_HOTPLUG_CPU
static void smp_85xx_mach_cpu_die(void) static void smp_85xx_mach_cpu_die(void)
{ {
unsigned int cpu = smp_processor_id(); unsigned int cpu = smp_processor_id();
u32 tmp;
local_irq_disable(); local_irq_disable();
hard_irq_disable();
/* mask all irqs to prevent cpu wakeup */
qoriq_pm_ops->irq_mask(cpu);
idle_task_exit(); idle_task_exit();
generic_set_cpu_dead(cpu);
mb();
mtspr(SPRN_TCR, 0); mtspr(SPRN_TCR, 0);
mtspr(SPRN_TSR, mfspr(SPRN_TSR));
__flush_disable_L1(); generic_set_cpu_dead(cpu);
tmp = (mfspr(SPRN_HID0) & ~(HID0_DOZE|HID0_SLEEP)) | HID0_NAP;
mtspr(SPRN_HID0, tmp);
isync();
/* Enter NAP mode. */ cur_cpu_spec->cpu_down_flush();
tmp = mfmsr();
tmp |= MSR_WE; qoriq_pm_ops->cpu_die(cpu);
mb();
mtmsr(tmp);
isync();
while (1) while (1)
; ;
} }
static void qoriq_cpu_kill(unsigned int cpu)
{
int i;
for (i = 0; i < 500; i++) {
if (is_cpu_dead(cpu)) {
#ifdef CONFIG_PPC64
paca[cpu].cpu_start = 0;
#endif
return;
}
msleep(20);
}
pr_err("CPU%d didn't die...\n", cpu);
}
#endif #endif
/*
* To keep it compatible with old boot program which uses
* cache-inhibit spin table, we need to flush the cache
* before accessing spin table to invalidate any staled data.
* We also need to flush the cache after writing to spin
* table to push data out.
*/
static inline void flush_spin_table(void *spin_table) static inline void flush_spin_table(void *spin_table)
{ {
flush_dcache_range((ulong)spin_table, flush_dcache_range((ulong)spin_table,
...@@ -173,78 +180,28 @@ static inline u32 read_spin_table_addr_l(void *spin_table) ...@@ -173,78 +180,28 @@ static inline u32 read_spin_table_addr_l(void *spin_table)
static void wake_hw_thread(void *info) static void wake_hw_thread(void *info)
{ {
void fsl_secondary_thread_init(void); void fsl_secondary_thread_init(void);
unsigned long imsr, inia; unsigned long inia;
int nr = *(const int *)info; int cpu = *(const int *)info;
imsr = MSR_KERNEL;
inia = *(unsigned long *)fsl_secondary_thread_init; inia = *(unsigned long *)fsl_secondary_thread_init;
book3e_start_thread(cpu_thread_in_core(cpu), inia);
if (cpu_thread_in_core(nr) == 0) {
/* For when we boot on a secondary thread with kdump */
mttmr(TMRN_IMSR0, imsr);
mttmr(TMRN_INIA0, inia);
mtspr(SPRN_TENS, TEN_THREAD(0));
} else {
mttmr(TMRN_IMSR1, imsr);
mttmr(TMRN_INIA1, inia);
mtspr(SPRN_TENS, TEN_THREAD(1));
}
smp_generic_kick_cpu(nr);
} }
#endif #endif
static int smp_85xx_kick_cpu(int nr) static int smp_85xx_start_cpu(int cpu)
{ {
unsigned long flags; int ret = 0;
const u64 *cpu_rel_addr;
__iomem struct epapr_spin_table *spin_table;
struct device_node *np; struct device_node *np;
int hw_cpu = get_hard_smp_processor_id(nr); const u64 *cpu_rel_addr;
unsigned long flags;
int ioremappable; int ioremappable;
int ret = 0; int hw_cpu = get_hard_smp_processor_id(cpu);
struct epapr_spin_table __iomem *spin_table;
WARN_ON(nr < 0 || nr >= NR_CPUS);
WARN_ON(hw_cpu < 0 || hw_cpu >= NR_CPUS);
pr_debug("smp_85xx_kick_cpu: kick CPU #%d\n", nr);
#ifdef CONFIG_PPC64
/* Threads don't use the spin table */
if (cpu_thread_in_core(nr) != 0) {
int primary = cpu_first_thread_sibling(nr);
if (WARN_ON_ONCE(!cpu_has_feature(CPU_FTR_SMT)))
return -ENOENT;
if (cpu_thread_in_core(nr) != 1) {
pr_err("%s: cpu %d: invalid hw thread %d\n",
__func__, nr, cpu_thread_in_core(nr));
return -ENOENT;
}
if (!cpu_online(primary)) { np = of_get_cpu_node(cpu, NULL);
pr_err("%s: cpu %d: primary %d not online\n",
__func__, nr, primary);
return -ENOENT;
}
smp_call_function_single(primary, wake_hw_thread, &nr, 0);
return 0;
} else if (cpu_thread_in_core(boot_cpuid) != 0 &&
cpu_first_thread_sibling(boot_cpuid) == nr) {
if (WARN_ON_ONCE(!cpu_has_feature(CPU_FTR_SMT)))
return -ENOENT;
smp_call_function_single(boot_cpuid, wake_hw_thread, &nr, 0);
}
#endif
np = of_get_cpu_node(nr, NULL);
cpu_rel_addr = of_get_property(np, "cpu-release-addr", NULL); cpu_rel_addr = of_get_property(np, "cpu-release-addr", NULL);
if (!cpu_rel_addr) {
if (cpu_rel_addr == NULL) { pr_err("No cpu-release-addr for cpu %d\n", cpu);
printk(KERN_ERR "No cpu-release-addr for cpu %d\n", nr);
return -ENOENT; return -ENOENT;
} }
...@@ -264,28 +221,18 @@ static int smp_85xx_kick_cpu(int nr) ...@@ -264,28 +221,18 @@ static int smp_85xx_kick_cpu(int nr)
spin_table = phys_to_virt(*cpu_rel_addr); spin_table = phys_to_virt(*cpu_rel_addr);
local_irq_save(flags); local_irq_save(flags);
#ifdef CONFIG_PPC32 hard_irq_disable();
#ifdef CONFIG_HOTPLUG_CPU
/* Corresponding to generic_set_cpu_dead() */
generic_set_cpu_up(nr);
if (system_state == SYSTEM_RUNNING) { if (qoriq_pm_ops)
/* qoriq_pm_ops->cpu_up_prepare(cpu);
* To keep it compatible with old boot program which uses
* cache-inhibit spin table, we need to flush the cache
* before accessing spin table to invalidate any staled data.
* We also need to flush the cache after writing to spin
* table to push data out.
*/
flush_spin_table(spin_table);
out_be32(&spin_table->addr_l, 0);
flush_spin_table(spin_table);
/* if cpu is not spinning, reset it */
if (read_spin_table_addr_l(spin_table) != 1) {
/* /*
* We don't set the BPTR register here since it already points * We don't set the BPTR register here since it already points
* to the boot page properly. * to the boot page properly.
*/ */
mpic_reset_core(nr); mpic_reset_core(cpu);
/* /*
* wait until core is ready... * wait until core is ready...
...@@ -295,40 +242,23 @@ static int smp_85xx_kick_cpu(int nr) ...@@ -295,40 +242,23 @@ static int smp_85xx_kick_cpu(int nr)
if (!spin_event_timeout( if (!spin_event_timeout(
read_spin_table_addr_l(spin_table) == 1, read_spin_table_addr_l(spin_table) == 1,
10000, 100)) { 10000, 100)) {
pr_err("%s: timeout waiting for core %d to reset\n", pr_err("timeout waiting for cpu %d to reset\n",
__func__, hw_cpu); hw_cpu);
ret = -ENOENT; ret = -EAGAIN;
goto out; goto err;
} }
/* clear the acknowledge status */
__secondary_hold_acknowledge = -1;
} }
#endif
flush_spin_table(spin_table);
out_be32(&spin_table->pir, hw_cpu);
out_be32(&spin_table->addr_l, __pa(__early_start));
flush_spin_table(spin_table);
/* Wait a bit for the CPU to ack. */
if (!spin_event_timeout(__secondary_hold_acknowledge == hw_cpu,
10000, 100)) {
pr_err("%s: timeout waiting for core %d to ack\n",
__func__, hw_cpu);
ret = -ENOENT;
goto out;
}
out:
#else
smp_generic_kick_cpu(nr);
flush_spin_table(spin_table); flush_spin_table(spin_table);
out_be32(&spin_table->pir, hw_cpu); out_be32(&spin_table->pir, hw_cpu);
#ifdef CONFIG_PPC64
out_be64((u64 *)(&spin_table->addr_h), out_be64((u64 *)(&spin_table->addr_h),
__pa(ppc_function_entry(generic_secondary_smp_init))); __pa(ppc_function_entry(generic_secondary_smp_init)));
flush_spin_table(spin_table); #else
out_be32(&spin_table->addr_l, __pa(__early_start));
#endif #endif
flush_spin_table(spin_table);
err:
local_irq_restore(flags); local_irq_restore(flags);
if (ioremappable) if (ioremappable)
...@@ -337,6 +267,81 @@ static int smp_85xx_kick_cpu(int nr) ...@@ -337,6 +267,81 @@ static int smp_85xx_kick_cpu(int nr)
return ret; return ret;
} }
static int smp_85xx_kick_cpu(int nr)
{
int ret = 0;
#ifdef CONFIG_PPC64
int primary = nr;
#endif
WARN_ON(nr < 0 || nr >= num_possible_cpus());
pr_debug("kick CPU #%d\n", nr);
#ifdef CONFIG_PPC64
if (threads_per_core == 2) {
if (WARN_ON_ONCE(!cpu_has_feature(CPU_FTR_SMT)))
return -ENOENT;
booting_thread_hwid = cpu_thread_in_core(nr);
primary = cpu_first_thread_sibling(nr);
if (qoriq_pm_ops)
qoriq_pm_ops->cpu_up_prepare(nr);
/*
* If either thread in the core is online, use it to start
* the other.
*/
if (cpu_online(primary)) {
smp_call_function_single(primary,
wake_hw_thread, &nr, 1);
goto done;
} else if (cpu_online(primary + 1)) {
smp_call_function_single(primary + 1,
wake_hw_thread, &nr, 1);
goto done;
}
/*
* If getting here, it means both threads in the core are
* offline. So start the primary thread, then it will start
* the thread specified in booting_thread_hwid, the one
* corresponding to nr.
*/
} else if (threads_per_core == 1) {
/*
* If one core has only one thread, set booting_thread_hwid to
* an invalid value.
*/
booting_thread_hwid = INVALID_THREAD_HWID;
} else if (threads_per_core > 2) {
pr_err("Do not support more than 2 threads per CPU.");
return -EINVAL;
}
ret = smp_85xx_start_cpu(primary);
if (ret)
return ret;
done:
paca[nr].cpu_start = 1;
generic_set_cpu_up(nr);
return ret;
#else
ret = smp_85xx_start_cpu(nr);
if (ret)
return ret;
generic_set_cpu_up(nr);
return ret;
#endif
}
struct smp_ops_t smp_85xx_ops = { struct smp_ops_t smp_85xx_ops = {
.kick_cpu = smp_85xx_kick_cpu, .kick_cpu = smp_85xx_kick_cpu,
.cpu_bootable = smp_generic_cpu_bootable, .cpu_bootable = smp_generic_cpu_bootable,
...@@ -359,7 +364,7 @@ void mpc85xx_smp_kexec_cpu_down(int crash_shutdown, int secondary) ...@@ -359,7 +364,7 @@ void mpc85xx_smp_kexec_cpu_down(int crash_shutdown, int secondary)
local_irq_disable(); local_irq_disable();
if (secondary) { if (secondary) {
__flush_disable_L1(); cur_cpu_spec->cpu_down_flush();
atomic_inc(&kexec_down_cpus); atomic_inc(&kexec_down_cpus);
/* loop forever */ /* loop forever */
while (1); while (1);
...@@ -467,16 +472,6 @@ static void smp_85xx_setup_cpu(int cpu_nr) ...@@ -467,16 +472,6 @@ static void smp_85xx_setup_cpu(int cpu_nr)
smp_85xx_basic_setup(cpu_nr); smp_85xx_basic_setup(cpu_nr);
} }
static const struct of_device_id mpc85xx_smp_guts_ids[] = {
{ .compatible = "fsl,mpc8572-guts", },
{ .compatible = "fsl,p1020-guts", },
{ .compatible = "fsl,p1021-guts", },
{ .compatible = "fsl,p1022-guts", },
{ .compatible = "fsl,p1023-guts", },
{ .compatible = "fsl,p2020-guts", },
{},
};
void __init mpc85xx_smp_init(void) void __init mpc85xx_smp_init(void)
{ {
struct device_node *np; struct device_node *np;
...@@ -500,22 +495,21 @@ void __init mpc85xx_smp_init(void) ...@@ -500,22 +495,21 @@ void __init mpc85xx_smp_init(void)
smp_85xx_ops.probe = NULL; smp_85xx_ops.probe = NULL;
} }
np = of_find_matching_node(NULL, mpc85xx_smp_guts_ids); #ifdef CONFIG_HOTPLUG_CPU
if (np) { #ifdef CONFIG_FSL_CORENET_RCPM
guts = of_iomap(np, 0); fsl_rcpm_init();
of_node_put(np); #endif
if (!guts) {
pr_err("%s: Could not map guts node address\n", #ifdef CONFIG_FSL_PMC
__func__); mpc85xx_setup_pmc();
return; #endif
} if (qoriq_pm_ops) {
smp_85xx_ops.give_timebase = mpc85xx_give_timebase; smp_85xx_ops.give_timebase = mpc85xx_give_timebase;
smp_85xx_ops.take_timebase = mpc85xx_take_timebase; smp_85xx_ops.take_timebase = mpc85xx_take_timebase;
#ifdef CONFIG_HOTPLUG_CPU
ppc_md.cpu_die = smp_85xx_mach_cpu_die; ppc_md.cpu_die = smp_85xx_mach_cpu_die;
#endif smp_85xx_ops.cpu_die = qoriq_cpu_kill;
} }
#endif
smp_ops = &smp_85xx_ops; smp_ops = &smp_85xx_ops;
#ifdef CONFIG_KEXEC #ifdef CONFIG_KEXEC
......
arch/powerpc/platforms/85xx/smp.h
浏览文件 @ a1b53446
...@@ -5,6 +5,7 @@ ...@@ -5,6 +5,7 @@
#ifdef CONFIG_SMP #ifdef CONFIG_SMP
void __init mpc85xx_smp_init(void); void __init mpc85xx_smp_init(void);
int __init mpc85xx_setup_pmc(void);
#else #else
static inline void mpc85xx_smp_init(void) static inline void mpc85xx_smp_init(void)
{ {
......
arch/powerpc/platforms/86xx/Makefile
浏览文件 @ a1b53446
...@@ -2,7 +2,7 @@ ...@@ -2,7 +2,7 @@
# Makefile for the PowerPC 86xx linux kernel. # Makefile for the PowerPC 86xx linux kernel.
# #
obj-y := pic.o obj-y := pic.o common.o
obj-$(CONFIG_SMP) += mpc86xx_smp.o obj-$(CONFIG_SMP) += mpc86xx_smp.o
obj-$(CONFIG_MPC8641_HPCN) += mpc86xx_hpcn.o obj-$(CONFIG_MPC8641_HPCN) += mpc86xx_hpcn.o
obj-$(CONFIG_SBC8641D) += sbc8641d.o obj-$(CONFIG_SBC8641D) += sbc8641d.o
......
arch/powerpc/platforms/86xx/common.c 0 → 100644
浏览文件 @ a1b53446
/*
* Routines common to most mpc86xx-based boards.
*
* This is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/of_platform.h>
#include <asm/synch.h>
#include "mpc86xx.h"
static const struct of_device_id mpc86xx_common_ids[] __initconst = {
{ .type = "soc", },
{ .compatible = "soc", },
{ .compatible = "simple-bus", },
{ .name = "localbus", },
{ .compatible = "gianfar", },
{ .compatible = "fsl,mpc8641-pcie", },
{},
};
int __init mpc86xx_common_publish_devices(void)
{
return of_platform_bus_probe(NULL, mpc86xx_common_ids, NULL);
}
long __init mpc86xx_time_init(void)
{
unsigned int temp;
/* Set the time base to zero */
mtspr(SPRN_TBWL, 0);
mtspr(SPRN_TBWU, 0);
temp = mfspr(SPRN_HID0);
temp |= HID0_TBEN;
mtspr(SPRN_HID0, temp);
isync();
return 0;
}
arch/powerpc/platforms/86xx/gef_ppc9a.c
浏览文件 @ a1b53446
...@@ -197,37 +197,7 @@ static int __init gef_ppc9a_probe(void) ...@@ -197,37 +197,7 @@ static int __init gef_ppc9a_probe(void)
return 0; return 0;
} }
static long __init mpc86xx_time_init(void) machine_arch_initcall(gef_ppc9a, mpc86xx_common_publish_devices);
{
unsigned int temp;
/* Set the time base to zero */
mtspr(SPRN_TBWL, 0);
mtspr(SPRN_TBWU, 0);
temp = mfspr(SPRN_HID0);
temp |= HID0_TBEN;
mtspr(SPRN_HID0, temp);
asm volatile("isync");
return 0;
}
static const struct of_device_id of_bus_ids[] __initconst = {
{ .compatible = "simple-bus", },
{ .compatible = "gianfar", },
{ .compatible = "fsl,mpc8641-pcie", },
{},
};
static int __init declare_of_platform_devices(void)
{
printk(KERN_DEBUG "Probe platform devices\n");
of_platform_bus_probe(NULL, of_bus_ids, NULL);
return 0;
}
machine_arch_initcall(gef_ppc9a, declare_of_platform_devices);
define_machine(gef_ppc9a) { define_machine(gef_ppc9a) {
.name = "GE PPC9A", .name = "GE PPC9A",
......
arch/powerpc/platforms/86xx/gef_sbc310.c
浏览文件 @ a1b53446
...@@ -184,37 +184,7 @@ static int __init gef_sbc310_probe(void) ...@@ -184,37 +184,7 @@ static int __init gef_sbc310_probe(void)
return 0; return 0;
} }
static long __init mpc86xx_time_init(void) machine_arch_initcall(gef_sbc310, mpc86xx_common_publish_devices);
{
unsigned int temp;
/* Set the time base to zero */
mtspr(SPRN_TBWL, 0);
mtspr(SPRN_TBWU, 0);
temp = mfspr(SPRN_HID0);
temp |= HID0_TBEN;
mtspr(SPRN_HID0, temp);
asm volatile("isync");
return 0;
}
static const struct of_device_id of_bus_ids[] __initconst = {
{ .compatible = "simple-bus", },
{ .compatible = "gianfar", },
{ .compatible = "fsl,mpc8641-pcie", },
{},
};
static int __init declare_of_platform_devices(void)
{
printk(KERN_DEBUG "Probe platform devices\n");
of_platform_bus_probe(NULL, of_bus_ids, NULL);
return 0;
}
machine_arch_initcall(gef_sbc310, declare_of_platform_devices);
define_machine(gef_sbc310) { define_machine(gef_sbc310) {
.name = "GE SBC310", .name = "GE SBC310",
......
arch/powerpc/platforms/86xx/gef_sbc610.c
浏览文件 @ a1b53446
...@@ -174,37 +174,7 @@ static int __init gef_sbc610_probe(void) ...@@ -174,37 +174,7 @@ static int __init gef_sbc610_probe(void)
return 0; return 0;
} }
static long __init mpc86xx_time_init(void) machine_arch_initcall(gef_sbc610, mpc86xx_common_publish_devices);
{
unsigned int temp;
/* Set the time base to zero */
mtspr(SPRN_TBWL, 0);
mtspr(SPRN_TBWU, 0);
temp = mfspr(SPRN_HID0);
temp |= HID0_TBEN;
mtspr(SPRN_HID0, temp);
asm volatile("isync");
return 0;
}
static const struct of_device_id of_bus_ids[] __initconst = {
{ .compatible = "simple-bus", },
{ .compatible = "gianfar", },
{ .compatible = "fsl,mpc8641-pcie", },
{},
};
static int __init declare_of_platform_devices(void)
{
printk(KERN_DEBUG "Probe platform devices\n");
of_platform_bus_probe(NULL, of_bus_ids, NULL);
return 0;
}
machine_arch_initcall(gef_sbc610, declare_of_platform_devices);
define_machine(gef_sbc610) { define_machine(gef_sbc610) {
.name = "GE SBC610", .name = "GE SBC610",
......
arch/powerpc/platforms/86xx/mpc8610_hpcd.c
浏览文件 @ a1b53446
...@@ -88,12 +88,10 @@ static inline void mpc8610_suspend_init(void) { } ...@@ -88,12 +88,10 @@ static inline void mpc8610_suspend_init(void) { }
static const struct of_device_id mpc8610_ids[] __initconst = { static const struct of_device_id mpc8610_ids[] __initconst = {
{ .compatible = "fsl,mpc8610-immr", }, { .compatible = "fsl,mpc8610-immr", },
{ .compatible = "fsl,mpc8610-guts", }, { .compatible = "fsl,mpc8610-guts", },
{ .compatible = "simple-bus", },
/* So that the DMA channel nodes can be probed individually: */ /* So that the DMA channel nodes can be probed individually: */
{ .compatible = "fsl,eloplus-dma", }, { .compatible = "fsl,eloplus-dma", },
/* PCI controllers */ /* PCI controllers */
{ .compatible = "fsl,mpc8610-pci", }, { .compatible = "fsl,mpc8610-pci", },
{ .compatible = "fsl,mpc8641-pcie", },
{} {}
}; };
...@@ -105,6 +103,8 @@ static int __init mpc8610_declare_of_platform_devices(void) ...@@ -105,6 +103,8 @@ static int __init mpc8610_declare_of_platform_devices(void)
/* Enable wakeup on PIXIS' event IRQ. */ /* Enable wakeup on PIXIS' event IRQ. */
mpc8610_suspend_init(); mpc8610_suspend_init();
mpc86xx_common_publish_devices();
/* Without this call, the SSI device driver won't get probed. */ /* Without this call, the SSI device driver won't get probed. */
of_platform_bus_probe(NULL, mpc8610_ids, NULL); of_platform_bus_probe(NULL, mpc8610_ids, NULL);
...@@ -327,22 +327,6 @@ static int __init mpc86xx_hpcd_probe(void) ...@@ -327,22 +327,6 @@ static int __init mpc86xx_hpcd_probe(void)
return 0; return 0;
} }
static long __init mpc86xx_time_init(void)
{
unsigned int temp;
/* Set the time base to zero */
mtspr(SPRN_TBWL, 0);
mtspr(SPRN_TBWU, 0);
temp = mfspr(SPRN_HID0);
temp |= HID0_TBEN;
mtspr(SPRN_HID0, temp);
asm volatile("isync");
return 0;
}
define_machine(mpc86xx_hpcd) { define_machine(mpc86xx_hpcd) {
.name = "MPC86xx HPCD", .name = "MPC86xx HPCD",
.probe = mpc86xx_hpcd_probe, .probe = mpc86xx_hpcd_probe,
......
arch/powerpc/platforms/86xx/mpc86xx.h
浏览文件 @ a1b53446
...@@ -17,5 +17,7 @@ ...@@ -17,5 +17,7 @@
extern void mpc86xx_smp_init(void); extern void mpc86xx_smp_init(void);
extern void mpc86xx_init_irq(void); extern void mpc86xx_init_irq(void);
extern long mpc86xx_time_init(void);
extern int mpc86xx_common_publish_devices(void);
#endif /* __MPC86XX_H__ */ #endif /* __MPC86XX_H__ */
arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
浏览文件 @ a1b53446
...@@ -110,33 +110,14 @@ static int __init mpc86xx_hpcn_probe(void) ...@@ -110,33 +110,14 @@ static int __init mpc86xx_hpcn_probe(void)
return 0; return 0;
} }
static long __init
mpc86xx_time_init(void)
{
unsigned int temp;
/* Set the time base to zero */
mtspr(SPRN_TBWL, 0);
mtspr(SPRN_TBWU, 0);
temp = mfspr(SPRN_HID0);
temp |= HID0_TBEN;
mtspr(SPRN_HID0, temp);
asm volatile("isync");
return 0;
}
static const struct of_device_id of_bus_ids[] __initconst = { static const struct of_device_id of_bus_ids[] __initconst = {
{ .compatible = "simple-bus", },
{ .compatible = "fsl,srio", }, { .compatible = "fsl,srio", },
{ .compatible = "gianfar", },
{ .compatible = "fsl,mpc8641-pcie", },
{}, {},
}; };
static int __init declare_of_platform_devices(void) static int __init declare_of_platform_devices(void)
{ {
mpc86xx_common_publish_devices();
of_platform_bus_probe(NULL, of_bus_ids, NULL); of_platform_bus_probe(NULL, of_bus_ids, NULL);
return 0; return 0;
......
arch/powerpc/platforms/86xx/sbc8641d.c
浏览文件 @ a1b53446
...@@ -75,37 +75,7 @@ static int __init sbc8641_probe(void) ...@@ -75,37 +75,7 @@ static int __init sbc8641_probe(void)
return 0; return 0;
} }
static long __init machine_arch_initcall(sbc8641, mpc86xx_common_publish_devices);
mpc86xx_time_init(void)
{
unsigned int temp;
/* Set the time base to zero */
mtspr(SPRN_TBWL, 0);
mtspr(SPRN_TBWU, 0);
temp = mfspr(SPRN_HID0);
temp |= HID0_TBEN;
mtspr(SPRN_HID0, temp);
asm volatile("isync");
return 0;
}
static const struct of_device_id of_bus_ids[] __initconst = {
{ .compatible = "simple-bus", },
{ .compatible = "gianfar", },
{ .compatible = "fsl,mpc8641-pcie", },
{},
};
static int __init declare_of_platform_devices(void)
{
of_platform_bus_probe(NULL, of_bus_ids, NULL);
return 0;
}
machine_arch_initcall(sbc8641, declare_of_platform_devices);
define_machine(sbc8641) { define_machine(sbc8641) {
.name = "SBC8641D", .name = "SBC8641D",
......
arch/powerpc/platforms/embedded6xx/mpc10x.h
浏览文件 @ a1b53446
...@@ -24,13 +24,11 @@ ...@@ -24,13 +24,11 @@
* Processor: 0x80000000 - 0x807fffff -> PCI I/O: 0x00000000 - 0x007fffff * Processor: 0x80000000 - 0x807fffff -> PCI I/O: 0x00000000 - 0x007fffff
* Processor: 0xc0000000 - 0xdfffffff -> PCI MEM: 0x00000000 - 0x1fffffff * Processor: 0xc0000000 - 0xdfffffff -> PCI MEM: 0x00000000 - 0x1fffffff
* PCI MEM: 0x80000000 -> Processor System Memory: 0x00000000 * PCI MEM: 0x80000000 -> Processor System Memory: 0x00000000
* EUMB mapped to: ioremap_base - 0x00100000 (ioremap_base - 1 MB)
* *
* MAP B (CHRP Map) * MAP B (CHRP Map)
* Processor: 0xfe000000 - 0xfebfffff -> PCI I/O: 0x00000000 - 0x00bfffff * Processor: 0xfe000000 - 0xfebfffff -> PCI I/O: 0x00000000 - 0x00bfffff
* Processor: 0x80000000 - 0xbfffffff -> PCI MEM: 0x80000000 - 0xbfffffff * Processor: 0x80000000 - 0xbfffffff -> PCI MEM: 0x80000000 - 0xbfffffff
* PCI MEM: 0x00000000 -> Processor System Memory: 0x00000000 * PCI MEM: 0x00000000 -> Processor System Memory: 0x00000000
* EUMB mapped to: ioremap_base - 0x00100000 (ioremap_base - 1 MB)
*/ */
/* /*
...@@ -138,14 +136,6 @@ ...@@ -138,14 +136,6 @@
#define MPC10X_EUMB_WP_OFFSET 0x000ff000 /* Data path diagnostic, watchpoint reg offset */ #define MPC10X_EUMB_WP_OFFSET 0x000ff000 /* Data path diagnostic, watchpoint reg offset */
#define MPC10X_EUMB_WP_SIZE 0x00001000 /* Data path diagnostic, watchpoint reg size */ #define MPC10X_EUMB_WP_SIZE 0x00001000 /* Data path diagnostic, watchpoint reg size */
/*
* Define some recommended places to put the EUMB regs.
* For both maps, recommend putting the EUMB from 0xeff00000 to 0xefffffff.
*/
extern unsigned long ioremap_base;
#define MPC10X_MAPA_EUMB_BASE (ioremap_base - MPC10X_EUMB_SIZE)
#define MPC10X_MAPB_EUMB_BASE MPC10X_MAPA_EUMB_BASE
enum ppc_sys_devices { enum ppc_sys_devices {
MPC10X_IIC1, MPC10X_IIC1,
MPC10X_DMA0, MPC10X_DMA0,
......
arch/powerpc/sysdev/Kconfig
浏览文件 @ a1b53446
...@@ -40,3 +40,8 @@ config SCOM_DEBUGFS ...@@ -40,3 +40,8 @@ config SCOM_DEBUGFS
config GE_FPGA config GE_FPGA
bool bool
default n default n
config FSL_CORENET_RCPM
bool
help
This option enables support for RCPM (Run Control/Power Management).
arch/powerpc/sysdev/Makefile
浏览文件 @ a1b53446
...@@ -20,6 +20,7 @@ obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o ...@@ -20,6 +20,7 @@ obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o
obj-$(CONFIG_FSL_SOC) += fsl_soc.o fsl_mpic_err.o obj-$(CONFIG_FSL_SOC) += fsl_soc.o fsl_mpic_err.o
obj-$(CONFIG_FSL_PCI) += fsl_pci.o $(fsl-msi-obj-y) obj-$(CONFIG_FSL_PCI) += fsl_pci.o $(fsl-msi-obj-y)
obj-$(CONFIG_FSL_PMC) += fsl_pmc.o obj-$(CONFIG_FSL_PMC) += fsl_pmc.o
obj-$(CONFIG_FSL_CORENET_RCPM) += fsl_rcpm.o
obj-$(CONFIG_FSL_LBC) += fsl_lbc.o obj-$(CONFIG_FSL_LBC) += fsl_lbc.o
obj-$(CONFIG_FSL_GTM) += fsl_gtm.o obj-$(CONFIG_FSL_GTM) += fsl_gtm.o
obj-$(CONFIG_FSL_85XX_CACHE_SRAM) += fsl_85xx_l2ctlr.o fsl_85xx_cache_sram.o obj-$(CONFIG_FSL_85XX_CACHE_SRAM) += fsl_85xx_l2ctlr.o fsl_85xx_cache_sram.o
......
arch/powerpc/sysdev/cpm1.c
浏览文件 @ a1b53446
...@@ -228,7 +228,10 @@ void __init cpm_reset(void) ...@@ -228,7 +228,10 @@ void __init cpm_reset(void)
* Bit 25, FAM can also be set to use FEC aggressive mode (860T). * Bit 25, FAM can also be set to use FEC aggressive mode (860T).
*/ */
siu_conf = immr_map(im_siu_conf); siu_conf = immr_map(im_siu_conf);
out_be32(&siu_conf->sc_sdcr, 1); if ((mfspr(SPRN_IMMR) & 0xffff) == 0x0900) /* MPC885 */
out_be32(&siu_conf->sc_sdcr, 0x40);
else
out_be32(&siu_conf->sc_sdcr, 1);
immr_unmap(siu_conf); immr_unmap(siu_conf);
cpm_muram_init(); cpm_muram_init();
......
arch/powerpc/sysdev/fsl_lbc.c
浏览文件 @ a1b53446
...@@ -27,6 +27,7 @@ ...@@ -27,6 +27,7 @@
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/interrupt.h> #include <linux/interrupt.h>
#include <linux/mod_devicetable.h> #include <linux/mod_devicetable.h>
#include <linux/syscore_ops.h>
#include <asm/prom.h> #include <asm/prom.h>
#include <asm/fsl_lbc.h> #include <asm/fsl_lbc.h>
...@@ -352,24 +353,42 @@ static int fsl_lbc_ctrl_probe(struct platform_device *dev) ...@@ -352,24 +353,42 @@ static int fsl_lbc_ctrl_probe(struct platform_device *dev)
#ifdef CONFIG_SUSPEND #ifdef CONFIG_SUSPEND
/* save lbc registers */ /* save lbc registers */
static int fsl_lbc_suspend(struct platform_device *pdev, pm_message_t state) static int fsl_lbc_syscore_suspend(void)
{ {
struct fsl_lbc_ctrl *ctrl = dev_get_drvdata(&pdev->dev); struct fsl_lbc_ctrl *ctrl;
struct fsl_lbc_regs __iomem *lbc = ctrl->regs; struct fsl_lbc_regs __iomem *lbc;
ctrl = fsl_lbc_ctrl_dev;
if (!ctrl)
goto out;
lbc = ctrl->regs;
if (!lbc)
goto out;
ctrl->saved_regs = kmalloc(sizeof(struct fsl_lbc_regs), GFP_KERNEL); ctrl->saved_regs = kmalloc(sizeof(struct fsl_lbc_regs), GFP_KERNEL);
if (!ctrl->saved_regs) if (!ctrl->saved_regs)
return -ENOMEM; return -ENOMEM;
_memcpy_fromio(ctrl->saved_regs, lbc, sizeof(struct fsl_lbc_regs)); _memcpy_fromio(ctrl->saved_regs, lbc, sizeof(struct fsl_lbc_regs));
out:
return 0; return 0;
} }
/* restore lbc registers */ /* restore lbc registers */
static int fsl_lbc_resume(struct platform_device *pdev) static void fsl_lbc_syscore_resume(void)
{ {
struct fsl_lbc_ctrl *ctrl = dev_get_drvdata(&pdev->dev); struct fsl_lbc_ctrl *ctrl;
struct fsl_lbc_regs __iomem *lbc = ctrl->regs; struct fsl_lbc_regs __iomem *lbc;
ctrl = fsl_lbc_ctrl_dev;
if (!ctrl)
goto out;
lbc = ctrl->regs;
if (!lbc)
goto out;
if (ctrl->saved_regs) { if (ctrl->saved_regs) {
_memcpy_toio(lbc, ctrl->saved_regs, _memcpy_toio(lbc, ctrl->saved_regs,
...@@ -377,7 +396,9 @@ static int fsl_lbc_resume(struct platform_device *pdev) ...@@ -377,7 +396,9 @@ static int fsl_lbc_resume(struct platform_device *pdev)
kfree(ctrl->saved_regs); kfree(ctrl->saved_regs);
ctrl->saved_regs = NULL; ctrl->saved_regs = NULL;
} }
return 0;
out:
return;
} }
#endif /* CONFIG_SUSPEND */ #endif /* CONFIG_SUSPEND */
...@@ -389,20 +410,26 @@ static const struct of_device_id fsl_lbc_match[] = { ...@@ -389,20 +410,26 @@ static const struct of_device_id fsl_lbc_match[] = {
{}, {},
}; };
#ifdef CONFIG_SUSPEND
static struct syscore_ops lbc_syscore_pm_ops = {
.suspend = fsl_lbc_syscore_suspend,
.resume = fsl_lbc_syscore_resume,
};
#endif
static struct platform_driver fsl_lbc_ctrl_driver = { static struct platform_driver fsl_lbc_ctrl_driver = {
.driver = { .driver = {
.name = "fsl-lbc", .name = "fsl-lbc",
.of_match_table = fsl_lbc_match, .of_match_table = fsl_lbc_match,
}, },
.probe = fsl_lbc_ctrl_probe, .probe = fsl_lbc_ctrl_probe,
#ifdef CONFIG_SUSPEND
.suspend = fsl_lbc_suspend,
.resume = fsl_lbc_resume,
#endif
}; };
static int __init fsl_lbc_init(void) static int __init fsl_lbc_init(void)
{ {
#ifdef CONFIG_SUSPEND
register_syscore_ops(&lbc_syscore_pm_ops);
#endif
return platform_driver_register(&fsl_lbc_ctrl_driver); return platform_driver_register(&fsl_lbc_ctrl_driver);
} }
subsys_initcall(fsl_lbc_init); subsys_initcall(fsl_lbc_init);
arch/powerpc/sysdev/fsl_rcpm.c 0 → 100644
浏览文件 @ a1b53446
/*
* RCPM(Run Control/Power Management) support
*
* Copyright 2012-2015 Freescale Semiconductor Inc.
*
* Author: Chenhui Zhao <chenhui.zhao@freescale.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#define pr_fmt(fmt) "%s: " fmt, __func__
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/of_address.h>
#include <linux/export.h>
#include <asm/io.h>
#include <linux/fsl/guts.h>
#include <asm/cputhreads.h>
#include <asm/fsl_pm.h>
static struct ccsr_rcpm_v1 __iomem *rcpm_v1_regs;
static struct ccsr_rcpm_v2 __iomem *rcpm_v2_regs;
static unsigned int fsl_supported_pm_modes;
static void rcpm_v1_irq_mask(int cpu)
{
int hw_cpu = get_hard_smp_processor_id(cpu);
unsigned int mask = 1 << hw_cpu;
setbits32(&rcpm_v1_regs->cpmimr, mask);
setbits32(&rcpm_v1_regs->cpmcimr, mask);
setbits32(&rcpm_v1_regs->cpmmcmr, mask);
setbits32(&rcpm_v1_regs->cpmnmimr, mask);
}
static void rcpm_v2_irq_mask(int cpu)
{
int hw_cpu = get_hard_smp_processor_id(cpu);
unsigned int mask = 1 << hw_cpu;
setbits32(&rcpm_v2_regs->tpmimr0, mask);
setbits32(&rcpm_v2_regs->tpmcimr0, mask);
setbits32(&rcpm_v2_regs->tpmmcmr0, mask);
setbits32(&rcpm_v2_regs->tpmnmimr0, mask);
}
static void rcpm_v1_irq_unmask(int cpu)
{
int hw_cpu = get_hard_smp_processor_id(cpu);
unsigned int mask = 1 << hw_cpu;
clrbits32(&rcpm_v1_regs->cpmimr, mask);
clrbits32(&rcpm_v1_regs->cpmcimr, mask);
clrbits32(&rcpm_v1_regs->cpmmcmr, mask);
clrbits32(&rcpm_v1_regs->cpmnmimr, mask);
}
static void rcpm_v2_irq_unmask(int cpu)
{
int hw_cpu = get_hard_smp_processor_id(cpu);
unsigned int mask = 1 << hw_cpu;
clrbits32(&rcpm_v2_regs->tpmimr0, mask);
clrbits32(&rcpm_v2_regs->tpmcimr0, mask);
clrbits32(&rcpm_v2_regs->tpmmcmr0, mask);
clrbits32(&rcpm_v2_regs->tpmnmimr0, mask);
}
static void rcpm_v1_set_ip_power(bool enable, u32 mask)
{
if (enable)
setbits32(&rcpm_v1_regs->ippdexpcr, mask);
else
clrbits32(&rcpm_v1_regs->ippdexpcr, mask);
}
static void rcpm_v2_set_ip_power(bool enable, u32 mask)
{
if (enable)
setbits32(&rcpm_v2_regs->ippdexpcr[0], mask);
else
clrbits32(&rcpm_v2_regs->ippdexpcr[0], mask);
}
static void rcpm_v1_cpu_enter_state(int cpu, int state)
{
int hw_cpu = get_hard_smp_processor_id(cpu);
unsigned int mask = 1 << hw_cpu;
switch (state) {
case E500_PM_PH10:
setbits32(&rcpm_v1_regs->cdozcr, mask);
break;
case E500_PM_PH15:
setbits32(&rcpm_v1_regs->cnapcr, mask);
break;
default:
pr_warn("Unknown cpu PM state (%d)\n", state);
break;
}
}
static void rcpm_v2_cpu_enter_state(int cpu, int state)
{
int hw_cpu = get_hard_smp_processor_id(cpu);
u32 mask = 1 << cpu_core_index_of_thread(cpu);
switch (state) {
case E500_PM_PH10:
/* one bit corresponds to one thread for PH10 of 6500 */
setbits32(&rcpm_v2_regs->tph10setr0, 1 << hw_cpu);
break;
case E500_PM_PH15:
setbits32(&rcpm_v2_regs->pcph15setr, mask);
break;
case E500_PM_PH20:
setbits32(&rcpm_v2_regs->pcph20setr, mask);
break;
case E500_PM_PH30:
setbits32(&rcpm_v2_regs->pcph30setr, mask);
break;
default:
pr_warn("Unknown cpu PM state (%d)\n", state);
}
}
static void rcpm_v1_cpu_die(int cpu)
{
rcpm_v1_cpu_enter_state(cpu, E500_PM_PH15);
}
#ifdef CONFIG_PPC64
static void qoriq_disable_thread(int cpu)
{
int thread = cpu_thread_in_core(cpu);
book3e_stop_thread(thread);
}
#endif
static void rcpm_v2_cpu_die(int cpu)
{
#ifdef CONFIG_PPC64
int primary;
if (threads_per_core == 2) {
primary = cpu_first_thread_sibling(cpu);
if (cpu_is_offline(primary) && cpu_is_offline(primary + 1)) {
/* if both threads are offline, put the cpu in PH20 */
rcpm_v2_cpu_enter_state(cpu, E500_PM_PH20);
} else {
/* if only one thread is offline, disable the thread */
qoriq_disable_thread(cpu);
}
}
#endif
if (threads_per_core == 1)
rcpm_v2_cpu_enter_state(cpu, E500_PM_PH20);
}
static void rcpm_v1_cpu_exit_state(int cpu, int state)
{
int hw_cpu = get_hard_smp_processor_id(cpu);
unsigned int mask = 1 << hw_cpu;
switch (state) {
case E500_PM_PH10:
clrbits32(&rcpm_v1_regs->cdozcr, mask);
break;
case E500_PM_PH15:
clrbits32(&rcpm_v1_regs->cnapcr, mask);
break;
default:
pr_warn("Unknown cpu PM state (%d)\n", state);
break;
}
}
static void rcpm_v1_cpu_up_prepare(int cpu)
{
rcpm_v1_cpu_exit_state(cpu, E500_PM_PH15);
rcpm_v1_irq_unmask(cpu);
}
static void rcpm_v2_cpu_exit_state(int cpu, int state)
{
int hw_cpu = get_hard_smp_processor_id(cpu);
u32 mask = 1 << cpu_core_index_of_thread(cpu);
switch (state) {
case E500_PM_PH10:
setbits32(&rcpm_v2_regs->tph10clrr0, 1 << hw_cpu);
break;
case E500_PM_PH15:
setbits32(&rcpm_v2_regs->pcph15clrr, mask);
break;
case E500_PM_PH20:
setbits32(&rcpm_v2_regs->pcph20clrr, mask);
break;
case E500_PM_PH30:
setbits32(&rcpm_v2_regs->pcph30clrr, mask);
break;
default:
pr_warn("Unknown cpu PM state (%d)\n", state);
}
}
static void rcpm_v2_cpu_up_prepare(int cpu)
{
rcpm_v2_cpu_exit_state(cpu, E500_PM_PH20);
rcpm_v2_irq_unmask(cpu);
}
static int rcpm_v1_plat_enter_state(int state)
{
u32 *pmcsr_reg = &rcpm_v1_regs->powmgtcsr;
int ret = 0;
int result;
switch (state) {
case PLAT_PM_SLEEP:
setbits32(pmcsr_reg, RCPM_POWMGTCSR_SLP);
/* Upon resume, wait for RCPM_POWMGTCSR_SLP bit to be clear. */
result = spin_event_timeout(
!(in_be32(pmcsr_reg) & RCPM_POWMGTCSR_SLP), 10000, 10);
if (!result) {
pr_err("timeout waiting for SLP bit to be cleared\n");
ret = -ETIMEDOUT;
}
break;
default:
pr_warn("Unknown platform PM state (%d)", state);
ret = -EINVAL;
}
return ret;
}
static int rcpm_v2_plat_enter_state(int state)
{
u32 *pmcsr_reg = &rcpm_v2_regs->powmgtcsr;
int ret = 0;
int result;
switch (state) {
case PLAT_PM_LPM20:
/* clear previous LPM20 status */
setbits32(pmcsr_reg, RCPM_POWMGTCSR_P_LPM20_ST);
/* enter LPM20 status */
setbits32(pmcsr_reg, RCPM_POWMGTCSR_LPM20_RQ);
/* At this point, the device is in LPM20 status. */
/* resume ... */
result = spin_event_timeout(
!(in_be32(pmcsr_reg) & RCPM_POWMGTCSR_LPM20_ST), 10000, 10);
if (!result) {
pr_err("timeout waiting for LPM20 bit to be cleared\n");
ret = -ETIMEDOUT;
}
break;
default:
pr_warn("Unknown platform PM state (%d)\n", state);
ret = -EINVAL;
}
return ret;
}
static int rcpm_v1_plat_enter_sleep(void)
{
return rcpm_v1_plat_enter_state(PLAT_PM_SLEEP);
}
static int rcpm_v2_plat_enter_sleep(void)
{
return rcpm_v2_plat_enter_state(PLAT_PM_LPM20);
}
static void rcpm_common_freeze_time_base(u32 *tben_reg, int freeze)
{
static u32 mask;
if (freeze) {
mask = in_be32(tben_reg);
clrbits32(tben_reg, mask);
} else {
setbits32(tben_reg, mask);
}
/* read back to push the previous write */
in_be32(tben_reg);
}
static void rcpm_v1_freeze_time_base(bool freeze)
{
rcpm_common_freeze_time_base(&rcpm_v1_regs->ctbenr, freeze);
}
static void rcpm_v2_freeze_time_base(bool freeze)
{
rcpm_common_freeze_time_base(&rcpm_v2_regs->pctbenr, freeze);
}
static unsigned int rcpm_get_pm_modes(void)
{
return fsl_supported_pm_modes;
}
static const struct fsl_pm_ops qoriq_rcpm_v1_ops = {
.irq_mask = rcpm_v1_irq_mask,
.irq_unmask = rcpm_v1_irq_unmask,
.cpu_enter_state = rcpm_v1_cpu_enter_state,
.cpu_exit_state = rcpm_v1_cpu_exit_state,
.cpu_up_prepare = rcpm_v1_cpu_up_prepare,
.cpu_die = rcpm_v1_cpu_die,
.plat_enter_sleep = rcpm_v1_plat_enter_sleep,
.set_ip_power = rcpm_v1_set_ip_power,
.freeze_time_base = rcpm_v1_freeze_time_base,
.get_pm_modes = rcpm_get_pm_modes,
};
static const struct fsl_pm_ops qoriq_rcpm_v2_ops = {
.irq_mask = rcpm_v2_irq_mask,
.irq_unmask = rcpm_v2_irq_unmask,
.cpu_enter_state = rcpm_v2_cpu_enter_state,
.cpu_exit_state = rcpm_v2_cpu_exit_state,
.cpu_up_prepare = rcpm_v2_cpu_up_prepare,
.cpu_die = rcpm_v2_cpu_die,
.plat_enter_sleep = rcpm_v2_plat_enter_sleep,
.set_ip_power = rcpm_v2_set_ip_power,
.freeze_time_base = rcpm_v2_freeze_time_base,
.get_pm_modes = rcpm_get_pm_modes,
};
static const struct of_device_id rcpm_matches[] = {
{
.compatible = "fsl,qoriq-rcpm-1.0",
.data = &qoriq_rcpm_v1_ops,
},
{
.compatible = "fsl,qoriq-rcpm-2.0",
.data = &qoriq_rcpm_v2_ops,
},
{
.compatible = "fsl,qoriq-rcpm-2.1",
.data = &qoriq_rcpm_v2_ops,
},
{},
};
int __init fsl_rcpm_init(void)
{
struct device_node *np;
const struct of_device_id *match;
void __iomem *base;
np = of_find_matching_node_and_match(NULL, rcpm_matches, &match);
if (!np)
return 0;
base = of_iomap(np, 0);
of_node_put(np);
if (!base) {
pr_err("of_iomap() error.\n");
return -ENOMEM;
}
rcpm_v1_regs = base;
rcpm_v2_regs = base;
/* support sleep by default */
fsl_supported_pm_modes = FSL_PM_SLEEP;
qoriq_pm_ops = match->data;
return 0;
}
drivers/soc/fsl/qe/qe_common.c
浏览文件 @ a1b53446
...@@ -102,6 +102,39 @@ int cpm_muram_init(void) ...@@ -102,6 +102,39 @@ int cpm_muram_init(void)
return ret; return ret;
} }
/*
* cpm_muram_alloc_common - cpm_muram_alloc common code
* @size: number of bytes to allocate
* @algo: algorithm for alloc.
* @data: data for genalloc's algorithm.
*
* This function returns an offset into the muram area.
*/
static unsigned long cpm_muram_alloc_common(unsigned long size,
genpool_algo_t algo, void *data)
{
struct muram_block *entry;
unsigned long start;
start = gen_pool_alloc_algo(muram_pool, size, algo, data);
if (!start)
goto out2;
start = start - GENPOOL_OFFSET;
memset_io(cpm_muram_addr(start), 0, size);
entry = kmalloc(sizeof(*entry), GFP_ATOMIC);
if (!entry)
goto out1;
entry->start = start;
entry->size = size;
list_add(&entry->head, &muram_block_list);
return start;
out1:
gen_pool_free(muram_pool, start, size);
out2:
return (unsigned long)-ENOMEM;
}
/* /*
* cpm_muram_alloc - allocate the requested size worth of multi-user ram * cpm_muram_alloc - allocate the requested size worth of multi-user ram
* @size: number of bytes to allocate * @size: number of bytes to allocate
...@@ -175,39 +208,6 @@ unsigned long cpm_muram_alloc_fixed(unsigned long offset, unsigned long size) ...@@ -175,39 +208,6 @@ unsigned long cpm_muram_alloc_fixed(unsigned long offset, unsigned long size)
} }
EXPORT_SYMBOL(cpm_muram_alloc_fixed); EXPORT_SYMBOL(cpm_muram_alloc_fixed);
/*
* cpm_muram_alloc_common - cpm_muram_alloc common code
* @size: number of bytes to allocate
* @algo: algorithm for alloc.
* @data: data for genalloc's algorithm.
*
* This function returns an offset into the muram area.
*/
unsigned long cpm_muram_alloc_common(unsigned long size, genpool_algo_t algo,
void *data)
{
struct muram_block *entry;
unsigned long start;
start = gen_pool_alloc_algo(muram_pool, size, algo, data);
if (!start)
goto out2;
start = start - GENPOOL_OFFSET;
memset_io(cpm_muram_addr(start), 0, size);
entry = kmalloc(sizeof(*entry), GFP_KERNEL);
if (!entry)
goto out1;
entry->start = start;
entry->size = size;
list_add(&entry->head, &muram_block_list);
return start;
out1:
gen_pool_free(muram_pool, start, size);
out2:
return (unsigned long)-ENOMEM;
}
/** /**
* cpm_muram_addr - turn a muram offset into a virtual address * cpm_muram_addr - turn a muram offset into a virtual address
* @offset: muram offset to convert * @offset: muram offset to convert
......
drivers/soc/fsl/qe/qe_ic.c
浏览文件 @ a1b53446
...@@ -259,6 +259,11 @@ static int qe_ic_host_map(struct irq_domain *h, unsigned int virq, ...@@ -259,6 +259,11 @@ static int qe_ic_host_map(struct irq_domain *h, unsigned int virq,
struct qe_ic *qe_ic = h->host_data; struct qe_ic *qe_ic = h->host_data;
struct irq_chip *chip; struct irq_chip *chip;
if (hw >= ARRAY_SIZE(qe_ic_info)) {
pr_err("%s: Invalid hw irq number for QEIC\n", __func__);
return -EINVAL;
}
if (qe_ic_info[hw].mask == 0) { if (qe_ic_info[hw].mask == 0) {
printk(KERN_ERR "Can't map reserved IRQ\n"); printk(KERN_ERR "Can't map reserved IRQ\n");
return -EINVAL; return -EINVAL;
...@@ -407,7 +412,8 @@ int qe_ic_set_priority(unsigned int virq, unsigned int priority) ...@@ -407,7 +412,8 @@ int qe_ic_set_priority(unsigned int virq, unsigned int priority)
if (priority > 8 || priority == 0) if (priority > 8 || priority == 0)
return -EINVAL; return -EINVAL;
if (src > 127) if (WARN_ONCE(src >= ARRAY_SIZE(qe_ic_info),
"%s: Invalid hw irq number for QEIC\n", __func__))
return -EINVAL; return -EINVAL;
if (qe_ic_info[src].pri_reg == 0) if (qe_ic_info[src].pri_reg == 0)
return -EINVAL; return -EINVAL;
...@@ -436,6 +442,9 @@ int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high) ...@@ -436,6 +442,9 @@ int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high)
if (priority > 2 || priority == 0) if (priority > 2 || priority == 0)
return -EINVAL; return -EINVAL;
if (WARN_ONCE(src >= ARRAY_SIZE(qe_ic_info),
"%s: Invalid hw irq number for QEIC\n", __func__))
return -EINVAL;
switch (qe_ic_info[src].pri_reg) { switch (qe_ic_info[src].pri_reg) {
case QEIC_CIPZCC: case QEIC_CIPZCC:
......
include/linux/fsl/guts.h
浏览文件 @ a1b53446
...@@ -189,4 +189,109 @@ static inline void guts_set_pmuxcr_dma(struct ccsr_guts __iomem *guts, ...@@ -189,4 +189,109 @@ static inline void guts_set_pmuxcr_dma(struct ccsr_guts __iomem *guts,
#endif #endif
struct ccsr_rcpm_v1 {
u8 res0000[4];
__be32 cdozsr; /* 0x0004 Core Doze Status Register */
u8 res0008[4];
__be32 cdozcr; /* 0x000c Core Doze Control Register */
u8 res0010[4];
__be32 cnapsr; /* 0x0014 Core Nap Status Register */
u8 res0018[4];
__be32 cnapcr; /* 0x001c Core Nap Control Register */
u8 res0020[4];
__be32 cdozpsr; /* 0x0024 Core Doze Previous Status Register */
u8 res0028[4];
__be32 cnappsr; /* 0x002c Core Nap Previous Status Register */
u8 res0030[4];
__be32 cwaitsr; /* 0x0034 Core Wait Status Register */
u8 res0038[4];
__be32 cwdtdsr; /* 0x003c Core Watchdog Detect Status Register */
__be32 powmgtcsr; /* 0x0040 PM Control&Status Register */
#define RCPM_POWMGTCSR_SLP 0x00020000
u8 res0044[12];
__be32 ippdexpcr; /* 0x0050 IP Powerdown Exception Control Register */
u8 res0054[16];
__be32 cpmimr; /* 0x0064 Core PM IRQ Mask Register */
u8 res0068[4];
__be32 cpmcimr; /* 0x006c Core PM Critical IRQ Mask Register */
u8 res0070[4];
__be32 cpmmcmr; /* 0x0074 Core PM Machine Check Mask Register */
u8 res0078[4];
__be32 cpmnmimr; /* 0x007c Core PM NMI Mask Register */
u8 res0080[4];
__be32 ctbenr; /* 0x0084 Core Time Base Enable Register */
u8 res0088[4];
__be32 ctbckselr; /* 0x008c Core Time Base Clock Select Register */
u8 res0090[4];
__be32 ctbhltcr; /* 0x0094 Core Time Base Halt Control Register */
u8 res0098[4];
__be32 cmcpmaskcr; /* 0x00a4 Core Machine Check Mask Register */
};
struct ccsr_rcpm_v2 {
u8 res_00[12];
__be32 tph10sr0; /* Thread PH10 Status Register */
u8 res_10[12];
__be32 tph10setr0; /* Thread PH10 Set Control Register */
u8 res_20[12];
__be32 tph10clrr0; /* Thread PH10 Clear Control Register */
u8 res_30[12];
__be32 tph10psr0; /* Thread PH10 Previous Status Register */
u8 res_40[12];
__be32 twaitsr0; /* Thread Wait Status Register */
u8 res_50[96];
__be32 pcph15sr; /* Physical Core PH15 Status Register */
__be32 pcph15setr; /* Physical Core PH15 Set Control Register */
__be32 pcph15clrr; /* Physical Core PH15 Clear Control Register */
__be32 pcph15psr; /* Physical Core PH15 Prev Status Register */
u8 res_c0[16];
__be32 pcph20sr; /* Physical Core PH20 Status Register */
__be32 pcph20setr; /* Physical Core PH20 Set Control Register */
__be32 pcph20clrr; /* Physical Core PH20 Clear Control Register */
__be32 pcph20psr; /* Physical Core PH20 Prev Status Register */
__be32 pcpw20sr; /* Physical Core PW20 Status Register */
u8 res_e0[12];
__be32 pcph30sr; /* Physical Core PH30 Status Register */
__be32 pcph30setr; /* Physical Core PH30 Set Control Register */
__be32 pcph30clrr; /* Physical Core PH30 Clear Control Register */
__be32 pcph30psr; /* Physical Core PH30 Prev Status Register */
u8 res_100[32];
__be32 ippwrgatecr; /* IP Power Gating Control Register */
u8 res_124[12];
__be32 powmgtcsr; /* Power Management Control & Status Reg */
#define RCPM_POWMGTCSR_LPM20_RQ 0x00100000
#define RCPM_POWMGTCSR_LPM20_ST 0x00000200
#define RCPM_POWMGTCSR_P_LPM20_ST 0x00000100
u8 res_134[12];
__be32 ippdexpcr[4]; /* IP Powerdown Exception Control Reg */
u8 res_150[12];
__be32 tpmimr0; /* Thread PM Interrupt Mask Reg */
u8 res_160[12];
__be32 tpmcimr0; /* Thread PM Crit Interrupt Mask Reg */
u8 res_170[12];
__be32 tpmmcmr0; /* Thread PM Machine Check Interrupt Mask Reg */
u8 res_180[12];
__be32 tpmnmimr0; /* Thread PM NMI Mask Reg */
u8 res_190[12];
__be32 tmcpmaskcr0; /* Thread Machine Check Mask Control Reg */
__be32 pctbenr; /* Physical Core Time Base Enable Reg */
__be32 pctbclkselr; /* Physical Core Time Base Clock Select */
__be32 tbclkdivr; /* Time Base Clock Divider Register */
u8 res_1ac[4];
__be32 ttbhltcr[4]; /* Thread Time Base Halt Control Register */
__be32 clpcl10sr; /* Cluster PCL10 Status Register */
__be32 clpcl10setr; /* Cluster PCL30 Set Control Register */
__be32 clpcl10clrr; /* Cluster PCL30 Clear Control Register */
__be32 clpcl10psr; /* Cluster PCL30 Prev Status Register */
__be32 cddslpsetr; /* Core Domain Deep Sleep Set Register */
__be32 cddslpclrr; /* Core Domain Deep Sleep Clear Register */
__be32 cdpwroksetr; /* Core Domain Power OK Set Register */
__be32 cdpwrokclrr; /* Core Domain Power OK Clear Register */
__be32 cdpwrensr; /* Core Domain Power Enable Status Register */
__be32 cddslsr; /* Core Domain Deep Sleep Status Register */
u8 res_1e8[8];
__be32 dslpcntcr[8]; /* Deep Sleep Counter Cfg Register */
u8 res_300[3568];
};
#endif #endif
include/soc/fsl/qe/qe.h
浏览文件 @ a1b53446
...@@ -103,8 +103,6 @@ int cpm_muram_init(void); ...@@ -103,8 +103,6 @@ int cpm_muram_init(void);
unsigned long cpm_muram_alloc(unsigned long size, unsigned long align); unsigned long cpm_muram_alloc(unsigned long size, unsigned long align);
int cpm_muram_free(unsigned long offset); int cpm_muram_free(unsigned long offset);
unsigned long cpm_muram_alloc_fixed(unsigned long offset, unsigned long size); unsigned long cpm_muram_alloc_fixed(unsigned long offset, unsigned long size);
unsigned long cpm_muram_alloc_common(unsigned long size, genpool_algo_t algo,
void *data);
void __iomem *cpm_muram_addr(unsigned long offset); void __iomem *cpm_muram_addr(unsigned long offset);
unsigned long cpm_muram_offset(void __iomem *addr); unsigned long cpm_muram_offset(void __iomem *addr);
dma_addr_t cpm_muram_dma(void __iomem *addr); dma_addr_t cpm_muram_dma(void __iomem *addr);
......
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