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kernel_linux
提交 8efcf34a 编写于 作者: L Linus Torvalds
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Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull ARM SoC late updates from Olof Johansson:
 "This is a branch with a few merge requests that either came in late,
  or took a while longer for us to review and merge than usual and thus
  cut it a bit close to the merge window. We stage them in a separate
  branch and if things look good, we still send them up -- and that's
  the case here.

  This is mostly DT additions for Renesas platforms, adding IP block
  descriptions for existing and new SoCs.

  There are also some driver updates for Qualcomm platforms for SMEM/QMI
  and GENI, which is their generalized serial protocol interface"

* tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (186 commits)
  soc: qcom: smem: introduce qcom_smem_virt_to_phys()
  soc: qcom: qmi: fix a buffer sizing bug
  MAINTAINERS: Update pattern for qcom_scm
  soc: Unconditionally include qcom Makefile
  soc: qcom: smem: check sooner in qcom_smem_set_global_partition()
  soc: qcom: smem: fix qcom_smem_set_global_partition()
  soc: qcom: smem: fix off-by-one error in qcom_smem_alloc_private()
  soc: qcom: smem: byte swap values properly
  soc: qcom: smem: return proper type for cached entry functions
  soc: qcom: smem: fix first cache entry calculation
  soc: qcom: cmd-db: Make endian-agnostic
  drivers: qcom: add command DB driver
  arm64: dts: renesas: salvator-common: Add ADV7482 support
  ARM: dts: r8a7740: Add CEU1
  ARM: dts: r8a7740: Add CEU0
  arm64: dts: renesas: salvator-common: enable VIN
  arm64: dts: renesas: r8a77970: add VIN and CSI-2 nodes
  arm64: dts: renesas: r8a77965: add VIN and CSI-2 nodes
  arm64: dts: renesas: r8a7796: add VIN and CSI-2 nodes
  arm64: dts: renesas: r8a7795-es1: add CSI-2 node
  ...
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Documentation/devicetree/bindings/firmware/qcom,scm.txt
浏览文件 @ 8efcf34a
...@@ -11,9 +11,10 @@ Required properties: ...@@ -11,9 +11,10 @@ Required properties:
* "qcom,scm-msm8660" for MSM8660 platforms * "qcom,scm-msm8660" for MSM8660 platforms
* "qcom,scm-msm8690" for MSM8690 platforms * "qcom,scm-msm8690" for MSM8690 platforms
* "qcom,scm-msm8996" for MSM8996 platforms * "qcom,scm-msm8996" for MSM8996 platforms
* "qcom,scm-ipq4019" for IPQ4019 platforms
* "qcom,scm" for later processors (MSM8916, APQ8084, MSM8974, etc) * "qcom,scm" for later processors (MSM8916, APQ8084, MSM8974, etc)
- clocks: One to three clocks may be required based on compatible. - clocks: One to three clocks may be required based on compatible.
* No clock required for "qcom,scm-msm8996" * No clock required for "qcom,scm-msm8996", "qcom,scm-ipq4019"
* Only core clock required for "qcom,scm-apq8064", "qcom,scm-msm8660", and "qcom,scm-msm8960" * Only core clock required for "qcom,scm-apq8064", "qcom,scm-msm8660", and "qcom,scm-msm8960"
* Core, iface, and bus clocks required for "qcom,scm" * Core, iface, and bus clocks required for "qcom,scm"
- clock-names: Must contain "core" for the core clock, "iface" for the interface - clock-names: Must contain "core" for the core clock, "iface" for the interface
......
Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.txt
浏览文件 @ 8efcf34a
...@@ -22,6 +22,7 @@ resources. ...@@ -22,6 +22,7 @@ resources.
"qcom,rpm-apq8084" "qcom,rpm-apq8084"
"qcom,rpm-msm8916" "qcom,rpm-msm8916"
"qcom,rpm-msm8974" "qcom,rpm-msm8974"
"qcom,rpm-msm8998"
- qcom,smd-channels: - qcom,smd-channels:
Usage: required Usage: required
......
MAINTAINERS
浏览文件 @ 8efcf34a
...@@ -1830,7 +1830,7 @@ F: drivers/spi/spi-qup.c ...@@ -1830,7 +1830,7 @@ F: drivers/spi/spi-qup.c
F: drivers/tty/serial/msm_serial.c F: drivers/tty/serial/msm_serial.c
F: drivers/*/pm8???-* F: drivers/*/pm8???-*
F: drivers/mfd/ssbi.c F: drivers/mfd/ssbi.c
F: drivers/firmware/qcom_scm.c F: drivers/firmware/qcom_scm*
T: git git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git T: git git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git
ARM/RADISYS ENP2611 MACHINE SUPPORT ARM/RADISYS ENP2611 MACHINE SUPPORT
......
arch/arm/boot/dts/Makefile
浏览文件 @ 8efcf34a
...@@ -807,6 +807,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \ ...@@ -807,6 +807,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
r8a7745-iwg22d-sodimm.dtb \ r8a7745-iwg22d-sodimm.dtb \
r8a7745-iwg22d-sodimm-dbhd-ca.dtb \ r8a7745-iwg22d-sodimm-dbhd-ca.dtb \
r8a7745-sk-rzg1e.dtb \ r8a7745-sk-rzg1e.dtb \
r8a77470-iwg23s-sbc.dtb \
r8a7778-bockw.dtb \ r8a7778-bockw.dtb \
r8a7779-marzen.dtb \ r8a7779-marzen.dtb \
r8a7790-lager.dtb \ r8a7790-lager.dtb \
......
arch/arm/boot/dts/emev2-kzm9d.dts
浏览文件 @ 8efcf34a
...@@ -34,9 +34,6 @@ ...@@ -34,9 +34,6 @@
gpio_keys { gpio_keys {
compatible = "gpio-keys"; compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
one { one {
debounce-interval = <50>; debounce-interval = <50>;
wakeup-source; wakeup-source;
......
arch/arm/boot/dts/emev2.dtsi
浏览文件 @ 8efcf34a
...@@ -31,13 +31,13 @@ ...@@ -31,13 +31,13 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
cpu@0 { cpu0: cpu@0 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a9"; compatible = "arm,cortex-a9";
reg = <0>; reg = <0>;
clock-frequency = <533000000>; clock-frequency = <533000000>;
}; };
cpu@1 { cpu1: cpu@1 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a9"; compatible = "arm,cortex-a9";
reg = <1>; reg = <1>;
...@@ -57,6 +57,7 @@ ...@@ -57,6 +57,7 @@
compatible = "arm,cortex-a9-pmu"; compatible = "arm,cortex-a9-pmu";
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>;
}; };
clocks@e0110000 { clocks@e0110000 {
......
arch/arm/boot/dts/r7s72100.dtsi
浏览文件 @ 8efcf34a
...@@ -15,7 +15,6 @@ ...@@ -15,7 +15,6 @@
/ { / {
compatible = "renesas,r7s72100"; compatible = "renesas,r7s72100";
interrupt-parent = <&gic>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
...@@ -31,40 +30,6 @@ ...@@ -31,40 +30,6 @@
spi4 = &spi4; spi4 = &spi4;
}; };
clocks {
ranges;
#address-cells = <1>;
#size-cells = <1>;
/* External clocks */
extal_clk: extal {
#clock-cells = <0>;
compatible = "fixed-clock";
/* If clk present, value must be set by board */
clock-frequency = <0>;
};
usb_x1_clk: usb_x1 {
#clock-cells = <0>;
compatible = "fixed-clock";
/* If clk present, value must be set by board */
clock-frequency = <0>;
};
rtc_x1_clk: rtc_x1 {
#clock-cells = <0>;
compatible = "fixed-clock";
/* If clk present, value must be set by board to 32678 */
clock-frequency = <0>;
};
rtc_x3_clk: rtc_x3 {
#clock-cells = <0>;
compatible = "fixed-clock";
/* If clk present, value must be set by board to 4000000 */
clock-frequency = <0>;
};
/* Fixed factor clocks */ /* Fixed factor clocks */
b_clk: b { b_clk: b {
#clock-cells = <0>; #clock-cells = <0>;
...@@ -73,126 +38,6 @@ ...@@ -73,126 +38,6 @@
clock-mult = <1>; clock-mult = <1>;
clock-div = <3>; clock-div = <3>;
}; };
p1_clk: p1 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R7S72100_CLK_PLL>;
clock-mult = <1>;
clock-div = <6>;
};
p0_clk: p0 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R7S72100_CLK_PLL>;
clock-mult = <1>;
clock-div = <12>;
};
/* Special CPG clocks */
cpg_clocks: cpg_clocks@fcfe0000 {
#clock-cells = <1>;
compatible = "renesas,r7s72100-cpg-clocks",
"renesas,rz-cpg-clocks";
reg = <0xfcfe0000 0x18>;
clocks = <&extal_clk>, <&usb_x1_clk>;
clock-output-names = "pll", "i", "g";
#power-domain-cells = <0>;
};
/* MSTP clocks */
mstp3_clks: mstp3_clks@fcfe0420 {
#clock-cells = <1>;
compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0xfcfe0420 4>;
clocks = <&p0_clk>;
clock-indices = <R7S72100_CLK_MTU2>;
clock-output-names = "mtu2";
};
mstp4_clks: mstp4_clks@fcfe0424 {
#clock-cells = <1>;
compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0xfcfe0424 4>;
clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
<&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
clock-indices = <
R7S72100_CLK_SCIF0 R7S72100_CLK_SCIF1 R7S72100_CLK_SCIF2 R7S72100_CLK_SCIF3
R7S72100_CLK_SCIF4 R7S72100_CLK_SCIF5 R7S72100_CLK_SCIF6 R7S72100_CLK_SCIF7
>;
clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7";
};
mstp5_clks: mstp5_clks@fcfe0428 {
#clock-cells = <1>;
compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0xfcfe0428 4>;
clocks = <&p0_clk>, <&p0_clk>;
clock-indices = <R7S72100_CLK_OSTM0 R7S72100_CLK_OSTM1>;
clock-output-names = "ostm0", "ostm1";
};
mstp6_clks: mstp6_clks@fcfe042c {
#clock-cells = <1>;
compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0xfcfe042c 4>;
clocks = <&p0_clk>;
clock-indices = <R7S72100_CLK_RTC>;
clock-output-names = "rtc";
};
mstp7_clks: mstp7_clks@fcfe0430 {
#clock-cells = <1>;
compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0xfcfe0430 4>;
clocks = <&b_clk>, <&p1_clk>, <&p1_clk>;
clock-indices = <R7S72100_CLK_ETHER R7S72100_CLK_USB0 R7S72100_CLK_USB1>;
clock-output-names = "ether", "usb0", "usb1";
};
mstp8_clks: mstp8_clks@fcfe0434 {
#clock-cells = <1>;
compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0xfcfe0434 4>;
clocks = <&p1_clk>;
clock-indices = <R7S72100_CLK_MMCIF>;
clock-output-names = "mmcif";
};
mstp9_clks: mstp9_clks@fcfe0438 {
#clock-cells = <1>;
compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0xfcfe0438 4>;
clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>;
clock-indices = <
R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3
>;
clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3";
};
mstp10_clks: mstp10_clks@fcfe043c {
#clock-cells = <1>;
compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0xfcfe043c 4>;
clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
<&p1_clk>;
clock-indices = <
R7S72100_CLK_SPI0 R7S72100_CLK_SPI1 R7S72100_CLK_SPI2 R7S72100_CLK_SPI3
R7S72100_CLK_SPI4
>;
clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4";
};
mstp12_clks: mstp12_clks@fcfe0444 {
#clock-cells = <1>;
compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0xfcfe0444 4>;
clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
clock-indices = <
R7S72100_CLK_SDHI00 R7S72100_CLK_SDHI01
R7S72100_CLK_SDHI10 R7S72100_CLK_SDHI11
>;
clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11";
};
};
cpus { cpus {
#address-cells = <1>; #address-cells = <1>;
...@@ -208,82 +53,65 @@ ...@@ -208,82 +53,65 @@
}; };
}; };
pinctrl: pin-controller@fcfe3000 { /* External clocks */
compatible = "renesas,r7s72100-ports"; extal_clk: extal {
#clock-cells = <0>;
reg = <0xfcfe3000 0x4230>; compatible = "fixed-clock";
/* If clk present, value must be set by board */
port0: gpio-0 { clock-frequency = <0>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 0 6>;
};
port1: gpio-1 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 16 16>;
};
port2: gpio-2 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 32 16>;
};
port3: gpio-3 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 48 16>;
}; };
port4: gpio-4 { p0_clk: p0 {
gpio-controller; #clock-cells = <0>;
#gpio-cells = <2>; compatible = "fixed-factor-clock";
gpio-ranges = <&pinctrl 0 64 16>; clocks = <&cpg_clocks R7S72100_CLK_PLL>;
clock-mult = <1>;
clock-div = <12>;
}; };
port5: gpio-5 { p1_clk: p1 {
gpio-controller; #clock-cells = <0>;
#gpio-cells = <2>; compatible = "fixed-factor-clock";
gpio-ranges = <&pinctrl 0 80 11>; clocks = <&cpg_clocks R7S72100_CLK_PLL>;
clock-mult = <1>;
clock-div = <6>;
}; };
port6: gpio-6 { pmu {
gpio-controller; compatible = "arm,cortex-a9-pmu";
#gpio-cells = <2>; interrupts-extended = <&gic GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
gpio-ranges = <&pinctrl 0 96 16>;
}; };
port7: gpio-7 { rtc_x1_clk: rtc_x1 {
gpio-controller; #clock-cells = <0>;
#gpio-cells = <2>; compatible = "fixed-clock";
gpio-ranges = <&pinctrl 0 112 16>; /* If clk present, value must be set by board to 32678 */
clock-frequency = <0>;
}; };
port8: gpio-8 { rtc_x3_clk: rtc_x3 {
gpio-controller; #clock-cells = <0>;
#gpio-cells = <2>; compatible = "fixed-clock";
gpio-ranges = <&pinctrl 0 128 16>; /* If clk present, value must be set by board to 4000000 */
clock-frequency = <0>;
}; };
port9: gpio-9 { soc {
gpio-controller; compatible = "simple-bus";
#gpio-cells = <2>; interrupt-parent = <&gic>;
gpio-ranges = <&pinctrl 0 144 8>;
};
port10: gpio-10 { #address-cells = <1>;
gpio-controller; #size-cells = <1>;
#gpio-cells = <2>; ranges;
gpio-ranges = <&pinctrl 0 160 16>;
};
port11: gpio-11 { L2: cache-controller@3ffff000 {
gpio-controller; compatible = "arm,pl310-cache";
#gpio-cells = <2>; reg = <0x3ffff000 0x1000>;
gpio-ranges = <&pinctrl 0 176 16>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
}; arm,early-bresp-disable;
arm,full-line-zero-disable;
cache-unified;
cache-level = <2>;
}; };
scif0: serial@e8007000 { scif0: serial@e8007000 {
...@@ -465,8 +293,73 @@ ...@@ -465,8 +293,73 @@
status = "disabled"; status = "disabled";
}; };
gic: interrupt-controller@e8201000 { usbhs0: usb@e8010000 {
compatible = "arm,pl390"; compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs";
reg = <0xe8010000 0x1a0>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp7_clks R7S72100_CLK_USB0>;
renesas,buswait = <4>;
power-domains = <&cpg_clocks>;
status = "disabled";
};
usbhs1: usb@e8207000 {
compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs";
reg = <0xe8207000 0x1a0>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp7_clks R7S72100_CLK_USB1>;
renesas,buswait = <4>;
power-domains = <&cpg_clocks>;
status = "disabled";
};
mmcif: mmc@e804c800 {
compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif";
reg = <0xe804c800 0x80>;
interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R7S72100_CLK_MMCIF>;
power-domains = <&cpg_clocks>;
reg-io-width = <4>;
bus-width = <8>;
status = "disabled";
};
sdhi0: sd@e804e000 {
compatible = "renesas,sdhi-r7s72100";
reg = <0xe804e000 0x100>;
interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp12_clks R7S72100_CLK_SDHI00>,
<&mstp12_clks R7S72100_CLK_SDHI01>;
clock-names = "core", "cd";
power-domains = <&cpg_clocks>;
cap-sd-highspeed;
cap-sdio-irq;
status = "disabled";
};
sdhi1: sd@e804e800 {
compatible = "renesas,sdhi-r7s72100";
reg = <0xe804e800 0x100>;
interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp12_clks R7S72100_CLK_SDHI10>,
<&mstp12_clks R7S72100_CLK_SDHI11>;
clock-names = "core", "cd";
power-domains = <&cpg_clocks>;
cap-sd-highspeed;
cap-sdio-irq;
status = "disabled";
};
gic: interrupt-controller@e8201000 {
compatible = "arm,pl390";
#interrupt-cells = <3>; #interrupt-cells = <3>;
#address-cells = <0>; #address-cells = <0>;
interrupt-controller; interrupt-controller;
...@@ -474,21 +367,234 @@ ...@@ -474,21 +367,234 @@
<0xe8202000 0x1000>; <0xe8202000 0x1000>;
}; };
L2: cache-controller@3ffff000 { ether: ethernet@e8203000 {
compatible = "arm,pl310-cache"; compatible = "renesas,ether-r7s72100";
reg = <0x3ffff000 0x1000>; reg = <0xe8203000 0x800>,
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; <0xe8204800 0x200>;
arm,early-bresp-disable; interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
arm,full-line-zero-disable; clocks = <&mstp7_clks R7S72100_CLK_ETHER>;
cache-unified; power-domains = <&cpg_clocks>;
cache-level = <2>; phy-mode = "mii";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
ceu: camera@e8210000 {
reg = <0xe8210000 0x3000>;
compatible = "renesas,r7s72100-ceu";
interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp6_clks R7S72100_CLK_CEU>;
power-domains = <&cpg_clocks>;
status = "disabled";
}; };
wdt: watchdog@fcfe0000 { wdt: watchdog@fcfe0000 {
compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt"; compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt";
reg = <0xfcfe0000 0x6>; reg = <0xfcfe0000 0x6>;
interrupts = <GIC_SPI 106 IRQ_TYPE_EDGE_RISING>; interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&p0_clk>;
};
/* Special CPG clocks */
cpg_clocks: cpg_clocks@fcfe0000 {
#clock-cells = <1>;
compatible = "renesas,r7s72100-cpg-clocks",
"renesas,rz-cpg-clocks";
reg = <0xfcfe0000 0x18>;
clocks = <&extal_clk>, <&usb_x1_clk>;
clock-output-names = "pll", "i", "g";
#power-domain-cells = <0>;
};
/* MSTP clocks */
mstp3_clks: mstp3_clks@fcfe0420 {
#clock-cells = <1>;
compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0xfcfe0420 4>;
clocks = <&p0_clk>; clocks = <&p0_clk>;
clock-indices = <R7S72100_CLK_MTU2>;
clock-output-names = "mtu2";
};
mstp4_clks: mstp4_clks@fcfe0424 {
#clock-cells = <1>;
compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0xfcfe0424 4>;
clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
<&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
clock-indices = <
R7S72100_CLK_SCIF0 R7S72100_CLK_SCIF1 R7S72100_CLK_SCIF2 R7S72100_CLK_SCIF3
R7S72100_CLK_SCIF4 R7S72100_CLK_SCIF5 R7S72100_CLK_SCIF6 R7S72100_CLK_SCIF7
>;
clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7";
};
mstp5_clks: mstp5_clks@fcfe0428 {
#clock-cells = <1>;
compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0xfcfe0428 4>;
clocks = <&p0_clk>, <&p0_clk>;
clock-indices = <R7S72100_CLK_OSTM0 R7S72100_CLK_OSTM1>;
clock-output-names = "ostm0", "ostm1";
};
mstp6_clks: mstp6_clks@fcfe042c {
#clock-cells = <1>;
compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0xfcfe042c 4>;
clocks = <&b_clk>, <&p0_clk>;
clock-indices = <R7S72100_CLK_CEU R7S72100_CLK_RTC>;
clock-output-names = "ceu", "rtc";
};
mstp7_clks: mstp7_clks@fcfe0430 {
#clock-cells = <1>;
compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0xfcfe0430 4>;
clocks = <&b_clk>, <&p1_clk>, <&p1_clk>;
clock-indices = <R7S72100_CLK_ETHER R7S72100_CLK_USB0 R7S72100_CLK_USB1>;
clock-output-names = "ether", "usb0", "usb1";
};
mstp8_clks: mstp8_clks@fcfe0434 {
#clock-cells = <1>;
compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0xfcfe0434 4>;
clocks = <&p1_clk>;
clock-indices = <R7S72100_CLK_MMCIF>;
clock-output-names = "mmcif";
};
mstp9_clks: mstp9_clks@fcfe0438 {
#clock-cells = <1>;
compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0xfcfe0438 4>;
clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>;
clock-indices = <
R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3
>;
clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3";
};
mstp10_clks: mstp10_clks@fcfe043c {
#clock-cells = <1>;
compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0xfcfe043c 4>;
clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
<&p1_clk>;
clock-indices = <
R7S72100_CLK_SPI0 R7S72100_CLK_SPI1 R7S72100_CLK_SPI2 R7S72100_CLK_SPI3
R7S72100_CLK_SPI4
>;
clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4";
};
mstp12_clks: mstp12_clks@fcfe0444 {
#clock-cells = <1>;
compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0xfcfe0444 4>;
clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
clock-indices = <
R7S72100_CLK_SDHI00 R7S72100_CLK_SDHI01
R7S72100_CLK_SDHI10 R7S72100_CLK_SDHI11
>;
clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11";
};
pinctrl: pin-controller@fcfe3000 {
compatible = "renesas,r7s72100-ports";
reg = <0xfcfe3000 0x4230>;
port0: gpio-0 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 0 6>;
};
port1: gpio-1 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 16 16>;
};
port2: gpio-2 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 32 16>;
};
port3: gpio-3 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 48 16>;
};
port4: gpio-4 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 64 16>;
};
port5: gpio-5 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 80 11>;
};
port6: gpio-6 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 96 16>;
};
port7: gpio-7 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 112 16>;
};
port8: gpio-8 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 128 16>;
};
port9: gpio-9 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 144 8>;
};
port10: gpio-10 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 160 16>;
};
port11: gpio-11 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 176 16>;
};
};
ostm0: timer@fcfec000 {
compatible = "renesas,r7s72100-ostm", "renesas,ostm";
reg = <0xfcfec000 0x30>;
interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
power-domains = <&cpg_clocks>;
status = "disabled";
};
ostm1: timer@fcfec400 {
compatible = "renesas,r7s72100-ostm", "renesas,ostm";
reg = <0xfcfec400 0x30>;
interrupts = <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>;
clocks = <&mstp5_clks R7S72100_CLK_OSTM1>;
power-domains = <&cpg_clocks>;
status = "disabled";
}; };
i2c0: i2c@fcfee000 { i2c0: i2c@fcfee000 {
...@@ -578,88 +684,12 @@ ...@@ -578,88 +684,12 @@
status = "disabled"; status = "disabled";
}; };
ether: ethernet@e8203000 {
compatible = "renesas,ether-r7s72100";
reg = <0xe8203000 0x800>,
<0xe8204800 0x200>;
interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp7_clks R7S72100_CLK_ETHER>;
power-domains = <&cpg_clocks>;
phy-mode = "mii";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
mmcif: mmc@e804c800 {
compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif";
reg = <0xe804c800 0x80>;
interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R7S72100_CLK_MMCIF>;
power-domains = <&cpg_clocks>;
reg-io-width = <4>;
bus-width = <8>;
status = "disabled";
};
sdhi0: sd@e804e000 {
compatible = "renesas,sdhi-r7s72100";
reg = <0xe804e000 0x100>;
interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp12_clks R7S72100_CLK_SDHI00>,
<&mstp12_clks R7S72100_CLK_SDHI01>;
clock-names = "core", "cd";
power-domains = <&cpg_clocks>;
cap-sd-highspeed;
cap-sdio-irq;
status = "disabled";
};
sdhi1: sd@e804e800 {
compatible = "renesas,sdhi-r7s72100";
reg = <0xe804e800 0x100>;
interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp12_clks R7S72100_CLK_SDHI10>,
<&mstp12_clks R7S72100_CLK_SDHI11>;
clock-names = "core", "cd";
power-domains = <&cpg_clocks>;
cap-sd-highspeed;
cap-sdio-irq;
status = "disabled";
};
ostm0: timer@fcfec000 {
compatible = "renesas,r7s72100-ostm", "renesas,ostm";
reg = <0xfcfec000 0x30>;
interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
power-domains = <&cpg_clocks>;
status = "disabled";
};
ostm1: timer@fcfec400 {
compatible = "renesas,r7s72100-ostm", "renesas,ostm";
reg = <0xfcfec400 0x30>;
interrupts = <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>;
clocks = <&mstp5_clks R7S72100_CLK_OSTM1>;
power-domains = <&cpg_clocks>;
status = "disabled";
};
rtc: rtc@fcff1000 { rtc: rtc@fcff1000 {
compatible = "renesas,r7s72100-rtc", "renesas,sh-rtc"; compatible = "renesas,r7s72100-rtc", "renesas,sh-rtc";
reg = <0xfcff1000 0x2e>; reg = <0xfcff1000 0x2e>;
interrupts = <GIC_SPI 276 IRQ_TYPE_EDGE_RISING interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
GIC_SPI 277 IRQ_TYPE_EDGE_RISING <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
GIC_SPI 278 IRQ_TYPE_EDGE_RISING>; <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "alarm", "period", "carry"; interrupt-names = "alarm", "period", "carry";
clocks = <&mstp6_clks R7S72100_CLK_RTC>, <&rtc_x1_clk>, clocks = <&mstp6_clks R7S72100_CLK_RTC>, <&rtc_x1_clk>,
<&rtc_x3_clk>, <&extal_clk>; <&rtc_x3_clk>, <&extal_clk>;
...@@ -667,4 +697,12 @@ ...@@ -667,4 +697,12 @@
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
}; };
};
usb_x1_clk: usb_x1 {
#clock-cells = <0>;
compatible = "fixed-clock";
/* If clk present, value must be set by board */
clock-frequency = <0>;
};
}; };
arch/arm/boot/dts/r8a73a4-ape6evm.dts
浏览文件 @ 8efcf34a
...@@ -234,7 +234,7 @@ ...@@ -234,7 +234,7 @@
&sdhi0 { &sdhi0 {
vmmc-supply = <&vcc_sdhi0>; vmmc-supply = <&vcc_sdhi0>;
bus-width = <4>; bus-width = <4>;
toshiba,mmc-wrprotect-disable; disable-wp;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&sdhi0_pins>; pinctrl-0 = <&sdhi0_pins>;
status = "okay"; status = "okay";
...@@ -244,7 +244,7 @@ ...@@ -244,7 +244,7 @@
vmmc-supply = <&ape6evm_fixed_3v3>; vmmc-supply = <&ape6evm_fixed_3v3>;
bus-width = <4>; bus-width = <4>;
broken-cd; broken-cd;
toshiba,mmc-wrprotect-disable; disable-wp;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&sdhi1_pins>; pinctrl-0 = <&sdhi1_pins>;
status = "okay"; status = "okay";
......
arch/arm/boot/dts/r8a73a4.dtsi
浏览文件 @ 8efcf34a
...@@ -57,10 +57,10 @@ ...@@ -57,10 +57,10 @@
timer { timer {
compatible = "arm,armv7-timer"; compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
}; };
dbsc1: memory-controller@e6790000 { dbsc1: memory-controller@e6790000 {
...@@ -464,7 +464,7 @@ ...@@ -464,7 +464,7 @@
<0 0xf1002000 0 0x2000>, <0 0xf1002000 0 0x2000>,
<0 0xf1004000 0 0x2000>, <0 0xf1004000 0 0x2000>,
<0 0xf1006000 0 0x2000>; <0 0xf1006000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&mstp4_clks R8A73A4_CLK_INTC_SYS>; clocks = <&mstp4_clks R8A73A4_CLK_INTC_SYS>;
clock-names = "clk"; clock-names = "clk";
power-domains = <&pd_c4>; power-domains = <&pd_c4>;
......
arch/arm/boot/dts/r8a7740.dtsi
浏览文件 @ 8efcf34a
...@@ -67,6 +67,24 @@ ...@@ -67,6 +67,24 @@
power-domains = <&pd_d4>; power-domains = <&pd_d4>;
}; };
ceu0: ceu@fe910000 {
reg = <0xfe910000 0x3000>;
compatible = "renesas,r8a7740-ceu";
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7740_CLK_CEU20>;
power-domains = <&pd_a4r>;
status = "disabled";
};
ceu1: ceu@fe914000 {
reg = <0xfe914000 0x3000>;
compatible = "renesas,r8a7740-ceu";
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7740_CLK_CEU21>;
power-domains = <&pd_a4r>;
status = "disabled";
};
cmt1: timer@e6138000 { cmt1: timer@e6138000 {
compatible = "renesas,cmt-48-r8a7740", "renesas,cmt-48"; compatible = "renesas,cmt-48-r8a7740", "renesas,cmt-48";
reg = <0xe6138000 0x170>; reg = <0xe6138000 0x170>;
......
arch/arm/boot/dts/r8a7743-iwg20m.dtsi
浏览文件 @ 8efcf34a
...@@ -91,6 +91,11 @@ ...@@ -91,6 +91,11 @@
}; };
}; };
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&sdhi0 { &sdhi0 {
pinctrl-0 = <&sdhi0_pins>; pinctrl-0 = <&sdhi0_pins>;
pinctrl-names = "default"; pinctrl-names = "default";
......
arch/arm/boot/dts/r8a7743.dtsi
浏览文件 @ 8efcf34a
...@@ -125,6 +125,13 @@ ...@@ -125,6 +125,13 @@
clock-frequency = <0>; clock-frequency = <0>;
}; };
pmu {
compatible = "arm,cortex-a15-pmu";
interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>;
};
/* External SCIF clock */ /* External SCIF clock */
scif_clk: scif { scif_clk: scif {
compatible = "fixed-clock"; compatible = "fixed-clock";
...@@ -297,6 +304,16 @@ ...@@ -297,6 +304,16 @@
reg = <0 0xe6160000 0 0x100>; reg = <0 0xe6160000 0 0x100>;
}; };
rwdt: watchdog@e6020000 {
compatible = "renesas,r8a7743-wdt",
"renesas,rcar-gen2-wdt";
reg = <0 0xe6020000 0 0x0c>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 402>;
status = "disabled";
};
sysc: system-controller@e6180000 { sysc: system-controller@e6180000 {
compatible = "renesas,r8a7743-sysc"; compatible = "renesas,r8a7743-sysc";
reg = <0 0xe6180000 0 0x200>; reg = <0 0xe6180000 0 0x200>;
...@@ -407,7 +424,7 @@ ...@@ -407,7 +424,7 @@
smp-sram@0 { smp-sram@0 {
compatible = "renesas,smp-sram"; compatible = "renesas,smp-sram";
reg = <0 0x10>; reg = <0 0x100>;
}; };
}; };
......
arch/arm/boot/dts/r8a7745-iwg22m.dtsi
浏览文件 @ 8efcf34a
...@@ -91,6 +91,11 @@ ...@@ -91,6 +91,11 @@
}; };
}; };
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&sdhi1 { &sdhi1 {
pinctrl-0 = <&sdhi1_pins>; pinctrl-0 = <&sdhi1_pins>;
pinctrl-names = "default"; pinctrl-names = "default";
......
arch/arm/boot/dts/r8a7745.dtsi
浏览文件 @ 8efcf34a
...@@ -105,6 +105,13 @@ ...@@ -105,6 +105,13 @@
clock-frequency = <0>; clock-frequency = <0>;
}; };
pmu {
compatible = "arm,cortex-a7-pmu";
interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>;
};
/* External SCIF clock */ /* External SCIF clock */
scif_clk: scif { scif_clk: scif {
compatible = "fixed-clock"; compatible = "fixed-clock";
...@@ -262,6 +269,16 @@ ...@@ -262,6 +269,16 @@
reg = <0 0xe6160000 0 0x100>; reg = <0 0xe6160000 0 0x100>;
}; };
rwdt: watchdog@e6020000 {
compatible = "renesas,r8a7745-wdt",
"renesas,rcar-gen2-wdt";
reg = <0 0xe6020000 0 0x0c>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 402>;
status = "disabled";
};
sysc: system-controller@e6180000 { sysc: system-controller@e6180000 {
compatible = "renesas,r8a7745-sysc"; compatible = "renesas,r8a7745-sysc";
reg = <0 0xe6180000 0 0x200>; reg = <0 0xe6180000 0 0x200>;
...@@ -360,7 +377,7 @@ ...@@ -360,7 +377,7 @@
smp-sram@0 { smp-sram@0 {
compatible = "renesas,smp-sram"; compatible = "renesas,smp-sram";
reg = <0 0x10>; reg = <0 0x100>;
}; };
}; };
......
arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts 0 → 100644
浏览文件 @ 8efcf34a
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the iWave-RZ/G1C single board computer
*
* Copyright (C) 2018 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a77470.dtsi"
/ {
model = "iWave iW-RainboW-G23S single board computer based on RZ/G1C";
compatible = "iwave,g23s", "renesas,r8a77470";
aliases {
ethernet0 = &avb;
serial1 = &scif1;
};
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
stdout-path = "serial1:115200n8";
};
memory@40000000 {
device_type = "memory";
reg = <0 0x40000000 0 0x20000000>;
};
};
&avb {
phy-handle = <&phy3>;
phy-mode = "gmii";
renesas,no-ether-link;
status = "okay";
phy3: ethernet-phy@3 {
reg = <3>;
micrel,led-mode = <1>;
};
};
&extal_clk {
clock-frequency = <20000000>;
};
&scif1 {
status = "okay";
};
arch/arm/boot/dts/r8a77470.dtsi 0 → 100644
浏览文件 @ 8efcf34a
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the r8a77470 SoC
*
* Copyright (C) 2018 Renesas Electronics Corp.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/ {
compatible = "renesas,r8a77470";
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0>;
clock-frequency = <1000000000>;
clocks = <&cpg CPG_CORE 0>;
power-domains = <&sysc 5>;
next-level-cache = <&L2_CA7>;
};
L2_CA7: cache-controller-0 {
compatible = "cache";
cache-unified;
cache-level = <2>;
power-domains = <&sysc 21>;
};
};
/* External root clock */
extal_clk: extal {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board. */
clock-frequency = <0>;
};
/* External SCIF clock */
scif_clk: scif {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board. */
clock-frequency = <0>;
};
soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a77470-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
clocks = <&extal_clk>, <&usb_extal_clk>;
clock-names = "extal", "usb_extal";
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
};
rst: reset-controller@e6160000 {
compatible = "renesas,r8a77470-rst";
reg = <0 0xe6160000 0 0x100>;
};
sysc: system-controller@e6180000 {
compatible = "renesas,r8a77470-sysc";
reg = <0 0xe6180000 0 0x200>;
#power-domain-cells = <1>;
};
irqc: interrupt-controller@e61c0000 {
compatible = "renesas,irqc-r8a77470", "renesas,irqc";
#interrupt-cells = <2>;
interrupt-controller;
reg = <0 0xe61c0000 0 0x200>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 407>;
power-domains = <&sysc 32>;
resets = <&cpg 407>;
};
icram0: sram@e63a0000 {
compatible = "mmio-sram";
reg = <0 0xe63a0000 0 0x12000>;
};
icram1: sram@e63c0000 {
compatible = "mmio-sram";
reg = <0 0xe63c0000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0xe63c0000 0x1000>;
smp-sram@0 {
compatible = "renesas,smp-sram";
reg = <0 0x100>;
};
};
icram2: sram@e6300000 {
compatible = "mmio-sram";
reg = <0 0xe6300000 0 0x20000>;
};
dmac0: dma-controller@e6700000 {
compatible = "renesas,dmac-r8a77470",
"renesas,rcar-dmac";
reg = <0 0xe6700000 0 0x20000>;
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14";
clocks = <&cpg CPG_MOD 219>;
clock-names = "fck";
power-domains = <&sysc 32>;
resets = <&cpg 219>;
#dma-cells = <1>;
dma-channels = <15>;
};
dmac1: dma-controller@e6720000 {
compatible = "renesas,dmac-r8a77470",
"renesas,rcar-dmac";
reg = <0 0xe6720000 0 0x20000>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14";
clocks = <&cpg CPG_MOD 218>;
clock-names = "fck";
power-domains = <&sysc 32>;
resets = <&cpg 218>;
#dma-cells = <1>;
dma-channels = <15>;
};
avb: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a77470",
"renesas,etheravb-rcar-gen2";
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 812>;
power-domains = <&sysc 32>;
resets = <&cpg 812>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
scif0: serial@e6e60000 {
compatible = "renesas,scif-r8a77470",
"renesas,rcar-gen2-scif", "renesas,scif";
reg = <0 0xe6e60000 0 0x40>;
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 721>,
<&cpg CPG_CORE 5>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
<&dmac1 0x29>, <&dmac1 0x2a>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc 32>;
resets = <&cpg 721>;
status = "disabled";
};
scif1: serial@e6e68000 {
compatible = "renesas,scif-r8a77470",
"renesas,rcar-gen2-scif", "renesas,scif";
reg = <0 0xe6e68000 0 0x40>;
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 720>,
<&cpg CPG_CORE 5>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
<&dmac1 0x2d>, <&dmac1 0x2e>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc 32>;
resets = <&cpg 720>;
status = "disabled";
};
scif2: serial@e6e58000 {
compatible = "renesas,scif-r8a77470",
"renesas,rcar-gen2-scif", "renesas,scif";
reg = <0 0xe6e58000 0 0x40>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 719>,
<&cpg CPG_CORE 5>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
<&dmac1 0x2b>, <&dmac1 0x2c>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc 32>;
resets = <&cpg 719>;
status = "disabled";
};
scif3: serial@e6ea8000 {
compatible = "renesas,scif-r8a77470",
"renesas,rcar-gen2-scif", "renesas,scif";
reg = <0 0xe6ea8000 0 0x40>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 718>,
<&cpg CPG_CORE 5>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
<&dmac1 0x2f>, <&dmac1 0x30>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc 32>;
resets = <&cpg 718>;
status = "disabled";
};
scif4: serial@e6ee0000 {
compatible = "renesas,scif-r8a77470",
"renesas,rcar-gen2-scif", "renesas,scif";
reg = <0 0xe6ee0000 0 0x40>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 715>,
<&cpg CPG_CORE 5>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
<&dmac1 0xfb>, <&dmac1 0xfc>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc 32>;
resets = <&cpg 715>;
status = "disabled";
};
scif5: serial@e6ee8000 {
compatible = "renesas,scif-r8a77470",
"renesas,rcar-gen2-scif", "renesas,scif";
reg = <0 0xe6ee8000 0 0x40>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 714>,
<&cpg CPG_CORE 5>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
<&dmac1 0xfd>, <&dmac1 0xfe>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc 32>;
resets = <&cpg 714>;
status = "disabled";
};
gic: interrupt-controller@f1001000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
<0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD 408>;
clock-names = "clk";
power-domains = <&sysc 32>;
resets = <&cpg 408>;
};
prr: chipid@ff000044 {
compatible = "renesas,prr";
reg = <0 0xff000044 0 4>;
};
};
timer {
compatible = "arm,armv7-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
};
/* External USB clock - can be overridden by the board */
usb_extal_clk: usb_extal {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
};
};
arch/arm/boot/dts/r8a7790-lager.dts
浏览文件 @ 8efcf34a
...@@ -902,9 +902,6 @@ ...@@ -902,9 +902,6 @@
status = "okay"; status = "okay";
port { port {
#address-cells = <1>;
#size-cells = <0>;
vin1ep0: endpoint { vin1ep0: endpoint {
remote-endpoint = <&adv7180>; remote-endpoint = <&adv7180>;
bus-width = <8>; bus-width = <8>;
...@@ -929,6 +926,11 @@ ...@@ -929,6 +926,11 @@
}; };
}; };
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&ssi1 { &ssi1 {
shared-pin; shared-pin;
}; };
arch/arm/boot/dts/r8a7790.dtsi
浏览文件 @ 8efcf34a
...@@ -202,6 +202,24 @@ ...@@ -202,6 +202,24 @@
clock-frequency = <0>; clock-frequency = <0>;
}; };
pmu-0 {
compatible = "arm,cortex-a15-pmu";
interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
pmu-1 {
compatible = "arm,cortex-a7-pmu";
interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
};
/* External SCIF clock */ /* External SCIF clock */
scif_clk: scif { scif_clk: scif {
compatible = "fixed-clock"; compatible = "fixed-clock";
...@@ -218,6 +236,16 @@ ...@@ -218,6 +236,16 @@
#size-cells = <2>; #size-cells = <2>;
ranges; ranges;
rwdt: watchdog@e6020000 {
compatible = "renesas,r8a7790-wdt",
"renesas,rcar-gen2-wdt";
reg = <0 0xe6020000 0 0x0c>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 402>;
status = "disabled";
};
gpio0: gpio@e6050000 { gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a7790", compatible = "renesas,gpio-r8a7790",
"renesas,rcar-gen2-gpio"; "renesas,rcar-gen2-gpio";
...@@ -443,7 +471,7 @@ ...@@ -443,7 +471,7 @@
smp-sram@0 { smp-sram@0 {
compatible = "renesas,smp-sram"; compatible = "renesas,smp-sram";
reg = <0 0x10>; reg = <0 0x100>;
}; };
}; };
...@@ -1544,7 +1572,7 @@ ...@@ -1544,7 +1572,7 @@
interrupt-controller; interrupt-controller;
reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
<0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD 408>; clocks = <&cpg CPG_MOD 408>;
clock-names = "clk"; clock-names = "clk";
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
...@@ -1615,6 +1643,33 @@ ...@@ -1615,6 +1643,33 @@
resets = <&cpg 127>; resets = <&cpg 127>;
}; };
fdp1@fe940000 {
compatible = "renesas,fdp1";
reg = <0 0xfe940000 0 0x2400>;
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 119>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 119>;
};
fdp1@fe944000 {
compatible = "renesas,fdp1";
reg = <0 0xfe944000 0 0x2400>;
interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 118>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 118>;
};
fdp1@fe948000 {
compatible = "renesas,fdp1";
reg = <0 0xfe948000 0 0x2400>;
interrupts = <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 117>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 117>;
};
jpu: jpeg-codec@fe980000 { jpu: jpeg-codec@fe980000 {
compatible = "renesas,jpu-r8a7790", compatible = "renesas,jpu-r8a7790",
"renesas,rcar-gen2-jpu"; "renesas,rcar-gen2-jpu";
...@@ -1773,10 +1828,10 @@ ...@@ -1773,10 +1828,10 @@
timer { timer {
compatible = "arm,armv7-timer"; compatible = "arm,armv7-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
}; };
/* External USB clock - can be overridden by the board */ /* External USB clock - can be overridden by the board */
......
arch/arm/boot/dts/r8a7791-koelsch.dts
浏览文件 @ 8efcf34a
...@@ -643,6 +643,11 @@ ...@@ -643,6 +643,11 @@
status = "okay"; status = "okay";
}; };
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&sata0 { &sata0 {
status = "okay"; status = "okay";
}; };
...@@ -850,9 +855,6 @@ ...@@ -850,9 +855,6 @@
pinctrl-names = "default"; pinctrl-names = "default";
port { port {
#address-cells = <1>;
#size-cells = <0>;
vin0ep2: endpoint { vin0ep2: endpoint {
remote-endpoint = <&adv7612_out>; remote-endpoint = <&adv7612_out>;
bus-width = <24>; bus-width = <24>;
...@@ -871,9 +873,6 @@ ...@@ -871,9 +873,6 @@
pinctrl-names = "default"; pinctrl-names = "default";
port { port {
#address-cells = <1>;
#size-cells = <0>;
vin1ep: endpoint { vin1ep: endpoint {
remote-endpoint = <&adv7180>; remote-endpoint = <&adv7180>;
bus-width = <8>; bus-width = <8>;
......
arch/arm/boot/dts/r8a7791-porter.dts
浏览文件 @ 8efcf34a
...@@ -386,9 +386,6 @@ ...@@ -386,9 +386,6 @@
pinctrl-names = "default"; pinctrl-names = "default";
port { port {
#address-cells = <1>;
#size-cells = <0>;
vin0ep: endpoint { vin0ep: endpoint {
remote-endpoint = <&adv7180>; remote-endpoint = <&adv7180>;
bus-width = <8>; bus-width = <8>;
...@@ -481,6 +478,11 @@ ...@@ -481,6 +478,11 @@
}; };
}; };
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&ssi1 { &ssi1 {
shared-pin; shared-pin;
}; };
arch/arm/boot/dts/r8a7791.dtsi
浏览文件 @ 8efcf34a
...@@ -126,6 +126,13 @@ ...@@ -126,6 +126,13 @@
clock-frequency = <0>; clock-frequency = <0>;
}; };
pmu {
compatible = "arm,cortex-a15-pmu";
interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>;
};
/* External SCIF clock */ /* External SCIF clock */
scif_clk: scif { scif_clk: scif {
compatible = "fixed-clock"; compatible = "fixed-clock";
...@@ -142,6 +149,16 @@ ...@@ -142,6 +149,16 @@
#size-cells = <2>; #size-cells = <2>;
ranges; ranges;
rwdt: watchdog@e6020000 {
compatible = "renesas,r8a7791-wdt",
"renesas,rcar-gen2-wdt";
reg = <0 0xe6020000 0 0x0c>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
resets = <&cpg 402>;
status = "disabled";
};
gpio0: gpio@e6050000 { gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a7791", compatible = "renesas,gpio-r8a7791",
"renesas,rcar-gen2-gpio"; "renesas,rcar-gen2-gpio";
...@@ -407,7 +424,7 @@ ...@@ -407,7 +424,7 @@
smp-sram@0 { smp-sram@0 {
compatible = "renesas,smp-sram"; compatible = "renesas,smp-sram";
reg = <0 0x10>; reg = <0 0x100>;
}; };
}; };
...@@ -1621,6 +1638,24 @@ ...@@ -1621,6 +1638,24 @@
resets = <&cpg 127>; resets = <&cpg 127>;
}; };
fdp1@fe940000 {
compatible = "renesas,fdp1";
reg = <0 0xfe940000 0 0x2400>;
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 119>;
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
resets = <&cpg 119>;
};
fdp1@fe944000 {
compatible = "renesas,fdp1";
reg = <0 0xfe944000 0 0x2400>;
interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 118>;
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
resets = <&cpg 118>;
};
jpu: jpeg-codec@fe980000 { jpu: jpeg-codec@fe980000 {
compatible = "renesas,jpu-r8a7791", compatible = "renesas,jpu-r8a7791",
"renesas,rcar-gen2-jpu"; "renesas,rcar-gen2-jpu";
......
arch/arm/boot/dts/r8a7792-blanche.dts
浏览文件 @ 8efcf34a
...@@ -239,6 +239,11 @@ ...@@ -239,6 +239,11 @@
}; };
}; };
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&scif0 { &scif0 {
pinctrl-0 = <&scif0_pins>; pinctrl-0 = <&scif0_pins>;
pinctrl-names = "default"; pinctrl-names = "default";
......
arch/arm/boot/dts/r8a7792-wheat.dts
浏览文件 @ 8efcf34a
...@@ -168,6 +168,11 @@ ...@@ -168,6 +168,11 @@
}; };
}; };
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&scif0 { &scif0 {
pinctrl-0 = <&scif0_pins>; pinctrl-0 = <&scif0_pins>;
pinctrl-names = "default"; pinctrl-names = "default";
...@@ -240,9 +245,15 @@ ...@@ -240,9 +245,15 @@
status = "okay"; status = "okay";
clock-frequency = <400000>; clock-frequency = <400000>;
/*
* The adv75xx resets its addresses to defaults during low power mode.
* Because we have two ADV7513 devices on the same bus, we must change
* both of them away from the defaults so that they do not conflict.
*/
hdmi@3d { hdmi@3d {
compatible = "adi,adv7513"; compatible = "adi,adv7513";
reg = <0x3d>; reg = <0x3d>, <0x2d>, <0x4d>, <0x5d>;
reg-names = "main", "cec", "edid", "packet";
adi,input-depth = <8>; adi,input-depth = <8>;
adi,input-colorspace = "rgb"; adi,input-colorspace = "rgb";
...@@ -272,7 +283,8 @@ ...@@ -272,7 +283,8 @@
hdmi@39 { hdmi@39 {
compatible = "adi,adv7513"; compatible = "adi,adv7513";
reg = <0x39>; reg = <0x39>, <0x29>, <0x49>, <0x59>;
reg-names = "main", "cec", "edid", "packet";
adi,input-depth = <8>; adi,input-depth = <8>;
adi,input-colorspace = "rgb"; adi,input-colorspace = "rgb";
......
arch/arm/boot/dts/r8a7792.dtsi
浏览文件 @ 8efcf34a
...@@ -85,6 +85,13 @@ ...@@ -85,6 +85,13 @@
clock-frequency = <0>; clock-frequency = <0>;
}; };
pmu {
compatible = "arm,cortex-a15-pmu";
interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>;
};
/* External SCIF clock */ /* External SCIF clock */
scif_clk: scif { scif_clk: scif {
compatible = "fixed-clock"; compatible = "fixed-clock";
...@@ -101,6 +108,16 @@ ...@@ -101,6 +108,16 @@
#size-cells = <2>; #size-cells = <2>;
ranges; ranges;
rwdt: watchdog@e6020000 {
compatible = "renesas,r8a7792-wdt",
"renesas,rcar-gen2-wdt";
reg = <0 0xe6020000 0 0x0c>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 402>;
status = "disabled";
};
gpio0: gpio@e6050000 { gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a7792", compatible = "renesas,gpio-r8a7792",
"renesas,rcar-gen2-gpio"; "renesas,rcar-gen2-gpio";
...@@ -341,7 +358,7 @@ ...@@ -341,7 +358,7 @@
smp-sram@0 { smp-sram@0 {
compatible = "renesas,smp-sram"; compatible = "renesas,smp-sram";
reg = <0 0x10>; reg = <0 0x100>;
}; };
}; };
......
arch/arm/boot/dts/r8a7793-gose.dts
浏览文件 @ 8efcf34a
...@@ -599,6 +599,11 @@ ...@@ -599,6 +599,11 @@
status = "okay"; status = "okay";
}; };
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&scif0 { &scif0 {
pinctrl-0 = <&scif0_pins>; pinctrl-0 = <&scif0_pins>;
pinctrl-names = "default"; pinctrl-names = "default";
...@@ -758,9 +763,6 @@ ...@@ -758,9 +763,6 @@
pinctrl-names = "default"; pinctrl-names = "default";
port { port {
#address-cells = <1>;
#size-cells = <0>;
vin0ep2: endpoint { vin0ep2: endpoint {
remote-endpoint = <&adv7612_out>; remote-endpoint = <&adv7612_out>;
bus-width = <24>; bus-width = <24>;
...@@ -780,9 +782,6 @@ ...@@ -780,9 +782,6 @@
status = "okay"; status = "okay";
port { port {
#address-cells = <1>;
#size-cells = <0>;
vin1ep: endpoint { vin1ep: endpoint {
remote-endpoint = <&adv7180_out>; remote-endpoint = <&adv7180_out>;
bus-width = <8>; bus-width = <8>;
......
arch/arm/boot/dts/r8a7793.dtsi
浏览文件 @ 8efcf34a
...@@ -110,6 +110,13 @@ ...@@ -110,6 +110,13 @@
clock-frequency = <0>; clock-frequency = <0>;
}; };
pmu {
compatible = "arm,cortex-a15-pmu";
interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>;
};
/* External SCIF clock */ /* External SCIF clock */
scif_clk: scif { scif_clk: scif {
compatible = "fixed-clock"; compatible = "fixed-clock";
...@@ -126,6 +133,16 @@ ...@@ -126,6 +133,16 @@
#size-cells = <2>; #size-cells = <2>;
ranges; ranges;
rwdt: watchdog@e6020000 {
compatible = "renesas,r8a7793-wdt",
"renesas,rcar-gen2-wdt";
reg = <0 0xe6020000 0 0x0c>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
resets = <&cpg 402>;
status = "disabled";
};
gpio0: gpio@e6050000 { gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a7793", compatible = "renesas,gpio-r8a7793",
"renesas,rcar-gen2-gpio"; "renesas,rcar-gen2-gpio";
...@@ -392,7 +409,7 @@ ...@@ -392,7 +409,7 @@
smp-sram@0 { smp-sram@0 {
compatible = "renesas,smp-sram"; compatible = "renesas,smp-sram";
reg = <0 0x10>; reg = <0 0x100>;
}; };
}; };
...@@ -1290,6 +1307,24 @@ ...@@ -1290,6 +1307,24 @@
resets = <&cpg 408>; resets = <&cpg 408>;
}; };
fdp1@fe940000 {
compatible = "renesas,fdp1";
reg = <0 0xfe940000 0 0x2400>;
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 119>;
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
resets = <&cpg 119>;
};
fdp1@fe944000 {
compatible = "renesas,fdp1";
reg = <0 0xfe944000 0 0x2400>;
interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 118>;
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
resets = <&cpg 118>;
};
du: display@feb00000 { du: display@feb00000 {
compatible = "renesas,du-r8a7793"; compatible = "renesas,du-r8a7793";
reg = <0 0xfeb00000 0 0x40000>; reg = <0 0xfeb00000 0 0x40000>;
......
arch/arm/boot/dts/r8a7794-alt.dts
浏览文件 @ 8efcf34a
...@@ -181,6 +181,12 @@ ...@@ -181,6 +181,12 @@
}; };
}; };
}; };
eeprom@50 {
compatible = "renesas,r1ex24002", "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
}; };
/* /*
...@@ -330,6 +336,11 @@ ...@@ -330,6 +336,11 @@
status = "okay"; status = "okay";
}; };
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&sdhi0 { &sdhi0 {
pinctrl-0 = <&sdhi0_pins>; pinctrl-0 = <&sdhi0_pins>;
pinctrl-1 = <&sdhi0_pins_uhs>; pinctrl-1 = <&sdhi0_pins_uhs>;
...@@ -375,9 +386,6 @@ ...@@ -375,9 +386,6 @@
pinctrl-names = "default"; pinctrl-names = "default";
port { port {
#address-cells = <1>;
#size-cells = <0>;
vin0ep: endpoint { vin0ep: endpoint {
remote-endpoint = <&adv7180>; remote-endpoint = <&adv7180>;
bus-width = <8>; bus-width = <8>;
......
arch/arm/boot/dts/r8a7794-silk.dts
浏览文件 @ 8efcf34a
...@@ -475,9 +475,6 @@ ...@@ -475,9 +475,6 @@
pinctrl-names = "default"; pinctrl-names = "default";
port { port {
#address-cells = <1>;
#size-cells = <0>;
vin0ep: endpoint { vin0ep: endpoint {
remote-endpoint = <&adv7180>; remote-endpoint = <&adv7180>;
bus-width = <8>; bus-width = <8>;
...@@ -540,6 +537,11 @@ ...@@ -540,6 +537,11 @@
}; };
}; };
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&ssi1 { &ssi1 {
shared-pin; shared-pin;
}; };
arch/arm/boot/dts/r8a7794.dtsi
浏览文件 @ 8efcf34a
...@@ -103,6 +103,13 @@ ...@@ -103,6 +103,13 @@
clock-frequency = <0>; clock-frequency = <0>;
}; };
pmu {
compatible = "arm,cortex-a7-pmu";
interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>;
};
/* External SCIF clock */ /* External SCIF clock */
scif_clk: scif { scif_clk: scif {
compatible = "fixed-clock"; compatible = "fixed-clock";
...@@ -119,6 +126,16 @@ ...@@ -119,6 +126,16 @@
#size-cells = <2>; #size-cells = <2>;
ranges; ranges;
rwdt: watchdog@e6020000 {
compatible = "renesas,r8a7794-wdt",
"renesas,rcar-gen2-wdt";
reg = <0 0xe6020000 0 0x0c>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
resets = <&cpg 402>;
status = "disabled";
};
gpio0: gpio@e6050000 { gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a7794", compatible = "renesas,gpio-r8a7794",
"renesas,rcar-gen2-gpio"; "renesas,rcar-gen2-gpio";
...@@ -348,7 +365,7 @@ ...@@ -348,7 +365,7 @@
smp-sram@0 { smp-sram@0 {
compatible = "renesas,smp-sram"; compatible = "renesas,smp-sram";
reg = <0 0x10>; reg = <0 0x100>;
}; };
}; };
...@@ -1323,6 +1340,15 @@ ...@@ -1323,6 +1340,15 @@
resets = <&cpg 128>; resets = <&cpg 128>;
}; };
fdp1@fe940000 {
compatible = "renesas,fdp1";
reg = <0 0xfe940000 0 0x2400>;
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 119>;
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
resets = <&cpg 119>;
};
du: display@feb00000 { du: display@feb00000 {
compatible = "renesas,du-r8a7794"; compatible = "renesas,du-r8a7794";
reg = <0 0xfeb00000 0 0x40000>; reg = <0 0xfeb00000 0 0x40000>;
......
arch/arm/boot/dts/sh73a0.dtsi
浏览文件 @ 8efcf34a
...@@ -22,7 +22,7 @@ ...@@ -22,7 +22,7 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
cpu@0 { cpu0: cpu@0 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a9"; compatible = "arm,cortex-a9";
reg = <0>; reg = <0>;
...@@ -31,7 +31,7 @@ ...@@ -31,7 +31,7 @@
power-domains = <&pd_a2sl>; power-domains = <&pd_a2sl>;
next-level-cache = <&L2>; next-level-cache = <&L2>;
}; };
cpu@1 { cpu1: cpu@1 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a9"; compatible = "arm,cortex-a9";
reg = <1>; reg = <1>;
...@@ -91,6 +91,7 @@ ...@@ -91,6 +91,7 @@
compatible = "arm,cortex-a9-pmu"; compatible = "arm,cortex-a9-pmu";
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>;
}; };
cmt1: timer@e6138000 { cmt1: timer@e6138000 {
...@@ -336,7 +337,7 @@ ...@@ -336,7 +337,7 @@
GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks SH73A0_CLK_SDHI1>; clocks = <&mstp3_clks SH73A0_CLK_SDHI1>;
power-domains = <&pd_a3sp>; power-domains = <&pd_a3sp>;
toshiba,mmc-wrprotect-disable; disable-wp;
cap-sd-highspeed; cap-sd-highspeed;
status = "disabled"; status = "disabled";
}; };
...@@ -348,7 +349,7 @@ ...@@ -348,7 +349,7 @@
GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks SH73A0_CLK_SDHI2>; clocks = <&mstp3_clks SH73A0_CLK_SDHI2>;
power-domains = <&pd_a3sp>; power-domains = <&pd_a3sp>;
toshiba,mmc-wrprotect-disable; disable-wp;
cap-sd-highspeed; cap-sd-highspeed;
status = "disabled"; status = "disabled";
}; };
......
arch/arm64/Kconfig.platforms
浏览文件 @ 8efcf34a
...@@ -208,6 +208,12 @@ config ARCH_R8A77980 ...@@ -208,6 +208,12 @@ config ARCH_R8A77980
help help
This enables support for the Renesas R-Car V3H SoC. This enables support for the Renesas R-Car V3H SoC.
config ARCH_R8A77990
bool "Renesas R-Car E3 SoC Platform"
depends on ARCH_RENESAS
help
This enables support for the Renesas R-Car E3 SoC.
config ARCH_R8A77995 config ARCH_R8A77995
bool "Renesas R-Car D3 SoC Platform" bool "Renesas R-Car D3 SoC Platform"
depends on ARCH_RENESAS depends on ARCH_RENESAS
......
arch/arm64/boot/dts/renesas/Makefile
浏览文件 @ 8efcf34a
...@@ -9,5 +9,6 @@ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-m3ulcb-kf.dtb ...@@ -9,5 +9,6 @@ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-m3ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb
dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb r8a77965-salvator-xs.dtb dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb r8a77965-salvator-xs.dtb
dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb r8a77970-v3msk.dtb dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb r8a77970-v3msk.dtb
dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb r8a77980-v3hsk.dtb
dtb-$(CONFIG_ARCH_R8A77990) += r8a77990-ebisu.dtb
dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb
arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts
浏览文件 @ 8efcf34a
...@@ -56,6 +56,12 @@ ...@@ -56,6 +56,12 @@
status = "okay"; status = "okay";
}; };
&sound_card {
dais = <&rsnd_port0 /* ak4613 */
&rsnd_port1 /* HDMI0 */
&rsnd_port2>; /* HDMI1 */
};
&hdmi0 { &hdmi0 {
status = "okay"; status = "okay";
...@@ -66,6 +72,12 @@ ...@@ -66,6 +72,12 @@
remote-endpoint = <&hdmi0_con>; remote-endpoint = <&hdmi0_con>;
}; };
}; };
port@2 {
reg = <2>;
dw_hdmi0_snd_in: endpoint {
remote-endpoint = <&rsnd_endpoint1>;
};
};
}; };
}; };
...@@ -83,6 +95,12 @@ ...@@ -83,6 +95,12 @@
remote-endpoint = <&hdmi1_con>; remote-endpoint = <&hdmi1_con>;
}; };
}; };
port@2 {
reg = <2>;
dw_hdmi1_snd_in: endpoint {
remote-endpoint = <&rsnd_endpoint2>;
};
};
}; };
}; };
...@@ -94,6 +112,34 @@ ...@@ -94,6 +112,34 @@
status = "okay"; status = "okay";
}; };
&rcar_sound {
ports {
/* rsnd_port0 is on salvator-common */
rsnd_port1: port@1 {
rsnd_endpoint1: endpoint {
remote-endpoint = <&dw_hdmi0_snd_in>;
dai-format = "i2s";
bitclock-master = <&rsnd_endpoint1>;
frame-master = <&rsnd_endpoint1>;
playback = <&ssi2>;
};
};
rsnd_port2: port@2 {
rsnd_endpoint2: endpoint {
remote-endpoint = <&dw_hdmi1_snd_in>;
dai-format = "i2s";
bitclock-master = <&rsnd_endpoint2>;
frame-master = <&rsnd_endpoint2>;
playback = <&ssi3>;
};
};
};
};
&pfc { &pfc {
usb2_pins: usb2 { usb2_pins: usb2 {
groups = "usb2"; groups = "usb2";
......
arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
浏览文件 @ 8efcf34a
...@@ -39,7 +39,6 @@ ...@@ -39,7 +39,6 @@
reg = <0 0xe7730000 0 0x1000>; reg = <0 0xe7730000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 8>; renesas,ipmmu-main = <&ipmmu_mm 8>;
#iommu-cells = <1>; #iommu-cells = <1>;
status = "disabled";
}; };
/delete-node/ usb-phy@ee0e0200; /delete-node/ usb-phy@ee0e0200;
...@@ -108,6 +107,61 @@ ...@@ -108,6 +107,61 @@
resets = <&cpg 117>; resets = <&cpg 117>;
renesas,fcp = <&fcpf2>; renesas,fcp = <&fcpf2>;
}; };
csi21: csi2@fea90000 {
compatible = "renesas,r8a7795-csi2";
reg = <0 0xfea90000 0 0x10000>;
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 713>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 713>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
csi21vin0: endpoint@0 {
reg = <0>;
remote-endpoint = <&vin0csi21>;
};
csi21vin1: endpoint@1 {
reg = <1>;
remote-endpoint = <&vin1csi21>;
};
csi21vin2: endpoint@2 {
reg = <2>;
remote-endpoint = <&vin2csi21>;
};
csi21vin3: endpoint@3 {
reg = <3>;
remote-endpoint = <&vin3csi21>;
};
csi21vin4: endpoint@4 {
reg = <4>;
remote-endpoint = <&vin4csi21>;
};
csi21vin5: endpoint@5 {
reg = <5>;
remote-endpoint = <&vin5csi21>;
};
csi21vin6: endpoint@6 {
reg = <6>;
remote-endpoint = <&vin6csi21>;
};
csi21vin7: endpoint@7 {
reg = <7>;
remote-endpoint = <&vin7csi21>;
};
};
};
};
}; };
&gpio1 { &gpio1 {
...@@ -175,3 +229,91 @@ ...@@ -175,3 +229,91 @@
&du { &du {
vsps = <&vspd0 &vspd1 &vspd2 &vspd3>; vsps = <&vspd0 &vspd1 &vspd2 &vspd3>;
}; };
&vin0 {
ports {
port@1 {
vin0csi21: endpoint@1 {
reg = <1>;
remote-endpoint= <&csi21vin0>;
};
};
};
};
&vin1 {
ports {
port@1 {
vin1csi21: endpoint@1 {
reg = <1>;
remote-endpoint= <&csi21vin1>;
};
};
};
};
&vin2 {
ports {
port@1 {
vin2csi21: endpoint@1 {
reg = <1>;
remote-endpoint= <&csi21vin2>;
};
};
};
};
&vin3 {
ports {
port@1 {
vin3csi21: endpoint@1 {
reg = <1>;
remote-endpoint= <&csi21vin3>;
};
};
};
};
&vin4 {
ports {
port@1 {
vin4csi21: endpoint@1 {
reg = <1>;
remote-endpoint= <&csi21vin4>;
};
};
};
};
&vin5 {
ports {
port@1 {
vin5csi21: endpoint@1 {
reg = <1>;
remote-endpoint= <&csi21vin5>;
};
};
};
};
&vin6 {
ports {
port@1 {
vin6csi21: endpoint@1 {
reg = <1>;
remote-endpoint= <&csi21vin6>;
};
};
};
};
&vin7 {
ports {
port@1 {
vin7csi21: endpoint@1 {
reg = <1>;
remote-endpoint= <&csi21vin7>;
};
};
};
};
arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
浏览文件 @ 8efcf34a
...@@ -56,6 +56,12 @@ ...@@ -56,6 +56,12 @@
status = "okay"; status = "okay";
}; };
&sound_card {
dais = <&rsnd_port0 /* ak4613 */
&rsnd_port1 /* HDMI0 */
&rsnd_port2>; /* HDMI1 */
};
&hdmi0 { &hdmi0 {
status = "okay"; status = "okay";
...@@ -66,6 +72,12 @@ ...@@ -66,6 +72,12 @@
remote-endpoint = <&hdmi0_con>; remote-endpoint = <&hdmi0_con>;
}; };
}; };
port@2 {
reg = <2>;
dw_hdmi0_snd_in: endpoint {
remote-endpoint = <&rsnd_endpoint1>;
};
};
}; };
}; };
...@@ -83,6 +95,12 @@ ...@@ -83,6 +95,12 @@
remote-endpoint = <&hdmi1_con>; remote-endpoint = <&hdmi1_con>;
}; };
}; };
port@2 {
reg = <2>;
dw_hdmi1_snd_in: endpoint {
remote-endpoint = <&rsnd_endpoint2>;
};
};
}; };
}; };
...@@ -94,6 +112,34 @@ ...@@ -94,6 +112,34 @@
status = "okay"; status = "okay";
}; };
&rcar_sound {
ports {
/* rsnd_port0 is on salvator-common */
rsnd_port1: port@1 {
rsnd_endpoint1: endpoint {
remote-endpoint = <&dw_hdmi0_snd_in>;
dai-format = "i2s";
bitclock-master = <&rsnd_endpoint1>;
frame-master = <&rsnd_endpoint1>;
playback = <&ssi2>;
};
};
rsnd_port2: port@2 {
rsnd_endpoint2: endpoint {
remote-endpoint = <&dw_hdmi1_snd_in>;
dai-format = "i2s";
bitclock-master = <&rsnd_endpoint2>;
frame-master = <&rsnd_endpoint2>;
playback = <&ssi3>;
};
};
};
};
&pfc { &pfc {
usb2_pins: usb2 { usb2_pins: usb2 {
groups = "usb2"; groups = "usb2";
......
arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
浏览文件 @ 8efcf34a
...@@ -56,6 +56,22 @@ ...@@ -56,6 +56,22 @@
status = "okay"; status = "okay";
}; };
&ehci3 {
dr_mode = "otg";
status = "okay";
};
&hsusb3 {
dr_mode = "otg";
status = "okay";
};
&sound_card {
dais = <&rsnd_port0 /* ak4613 */
&rsnd_port1 /* HDMI0 */
&rsnd_port2>; /* HDMI1 */
};
&hdmi0 { &hdmi0 {
status = "okay"; status = "okay";
...@@ -66,6 +82,12 @@ ...@@ -66,6 +82,12 @@
remote-endpoint = <&hdmi0_con>; remote-endpoint = <&hdmi0_con>;
}; };
}; };
port@2 {
reg = <2>;
dw_hdmi0_snd_in: endpoint {
remote-endpoint = <&rsnd_endpoint1>;
};
};
}; };
}; };
...@@ -83,6 +105,12 @@ ...@@ -83,6 +105,12 @@
remote-endpoint = <&hdmi1_con>; remote-endpoint = <&hdmi1_con>;
}; };
}; };
port@2 {
reg = <2>;
dw_hdmi1_snd_in: endpoint {
remote-endpoint = <&rsnd_endpoint2>;
};
};
}; };
}; };
...@@ -94,11 +122,61 @@ ...@@ -94,11 +122,61 @@
status = "okay"; status = "okay";
}; };
&ohci3 {
dr_mode = "otg";
status = "okay";
};
&rcar_sound {
ports {
/* rsnd_port0 is on salvator-common */
rsnd_port1: port@1 {
rsnd_endpoint1: endpoint {
remote-endpoint = <&dw_hdmi0_snd_in>;
dai-format = "i2s";
bitclock-master = <&rsnd_endpoint1>;
frame-master = <&rsnd_endpoint1>;
playback = <&ssi2>;
};
};
rsnd_port2: port@2 {
rsnd_endpoint2: endpoint {
remote-endpoint = <&dw_hdmi1_snd_in>;
dai-format = "i2s";
bitclock-master = <&rsnd_endpoint2>;
frame-master = <&rsnd_endpoint2>;
playback = <&ssi3>;
};
};
};
};
&pfc { &pfc {
usb2_pins: usb2 { usb2_pins: usb2 {
groups = "usb2"; groups = "usb2";
function = "usb2"; function = "usb2";
}; };
/*
* - On Salvator-X[S], GP6_3[01] are connected to ADV7482 as irq pins
* (when SW31 is the default setting on Salvator-XS).
* - If SW31 is the default setting, you cannot use USB2.0 ch3 on
* r8a7795 with Salvator-XS.
* Hence the SW31 setting must be changed like 2) below.
* 1) Default setting of SW31: ON-ON-OFF-OFF-OFF-OFF:
* - Connect GP6_3[01] to ADV7842.
* 2) Changed setting of SW31: OFF-OFF-ON-ON-ON-ON:
* - Connect GP6_3[01] to BD082065 (USB2.0 ch3's host power).
* - Connect GP6_{04,21} to ADV7842.
*/
usb2_ch3_pins: usb2_ch3 {
groups = "usb2_ch3";
function = "usb2_ch3";
};
}; };
&usb2_phy2 { &usb2_phy2 {
...@@ -107,3 +185,10 @@ ...@@ -107,3 +185,10 @@
status = "okay"; status = "okay";
}; };
&usb2_phy3 {
pinctrl-0 = <&usb2_ch3_pins>;
pinctrl-names = "default";
status = "okay";
};
arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
浏览文件 @ 8efcf34a
...@@ -40,6 +40,11 @@ ...@@ -40,6 +40,11 @@
"dclkin.0", "dclkin.1", "dclkin.2"; "dclkin.0", "dclkin.1", "dclkin.2";
}; };
&sound_card {
dais = <&rsnd_port0 /* ak4613 */
&rsnd_port1>; /* HDMI0 */
};
&hdmi0 { &hdmi0 {
status = "okay"; status = "okay";
...@@ -50,9 +55,32 @@ ...@@ -50,9 +55,32 @@
remote-endpoint = <&hdmi0_con>; remote-endpoint = <&hdmi0_con>;
}; };
}; };
port@2 {
reg = <2>;
dw_hdmi0_snd_in: endpoint {
remote-endpoint = <&rsnd_endpoint1>;
};
};
}; };
}; };
&hdmi0_con { &hdmi0_con {
remote-endpoint = <&rcar_dw_hdmi0_out>; remote-endpoint = <&rcar_dw_hdmi0_out>;
}; };
&rcar_sound {
ports {
/* rsnd_port0 is on salvator-common */
rsnd_port1: port@1 {
rsnd_endpoint1: endpoint {
remote-endpoint = <&dw_hdmi0_snd_in>;
dai-format = "i2s";
bitclock-master = <&rsnd_endpoint1>;
frame-master = <&rsnd_endpoint1>;
playback = <&ssi2>;
};
};
};
};
arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts
浏览文件 @ 8efcf34a
...@@ -40,6 +40,11 @@ ...@@ -40,6 +40,11 @@
"dclkin.0", "dclkin.1", "dclkin.2"; "dclkin.0", "dclkin.1", "dclkin.2";
}; };
&sound_card {
dais = <&rsnd_port0 /* ak4613 */
&rsnd_port1>; /* HDMI0 */
};
&hdmi0 { &hdmi0 {
status = "okay"; status = "okay";
...@@ -50,9 +55,32 @@ ...@@ -50,9 +55,32 @@
remote-endpoint = <&hdmi0_con>; remote-endpoint = <&hdmi0_con>;
}; };
}; };
port@2 {
reg = <2>;
dw_hdmi0_snd_in: endpoint {
remote-endpoint = <&rsnd_endpoint1>;
};
};
}; };
}; };
&hdmi0_con { &hdmi0_con {
remote-endpoint = <&rcar_dw_hdmi0_out>; remote-endpoint = <&rcar_dw_hdmi0_out>;
}; };
&rcar_sound {
ports {
/* rsnd_port0 is on salvator-common */
rsnd_port1: port@1 {
rsnd_endpoint1: endpoint {
remote-endpoint = <&dw_hdmi0_snd_in>;
dai-format = "i2s";
bitclock-master = <&rsnd_endpoint1>;
frame-master = <&rsnd_endpoint1>;
playback = <&ssi2>;
};
};
};
};
arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts
浏览文件 @ 8efcf34a
...@@ -19,3 +19,31 @@ ...@@ -19,3 +19,31 @@
reg = <0x0 0x48000000 0x0 0x78000000>; reg = <0x0 0x48000000 0x0 0x78000000>;
}; };
}; };
&du {
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 721>,
<&versaclock5 1>,
<&x21_clk>,
<&versaclock5 2>;
clock-names = "du.0", "du.1", "du.3",
"dclkin.0", "dclkin.1", "dclkin.3";
};
&hdmi0 {
status = "okay";
ports {
port@1 {
reg = <1>;
rcar_dw_hdmi0_out: endpoint {
remote-endpoint = <&hdmi0_con>;
};
};
};
};
&hdmi0_con {
remote-endpoint = <&rcar_dw_hdmi0_out>;
};
arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts
浏览文件 @ 8efcf34a
...@@ -19,3 +19,31 @@ ...@@ -19,3 +19,31 @@
reg = <0x0 0x48000000 0x0 0x78000000>; reg = <0x0 0x48000000 0x0 0x78000000>;
}; };
}; };
&du {
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 721>,
<&versaclock6 1>,
<&x21_clk>,
<&versaclock6 2>;
clock-names = "du.0", "du.1", "du.3",
"dclkin.0", "dclkin.1", "dclkin.3";
};
&hdmi0 {
status = "okay";
ports {
port@1 {
reg = <1>;
rcar_dw_hdmi0_out: endpoint {
remote-endpoint = <&hdmi0_con>;
};
};
};
};
&hdmi0_con {
remote-endpoint = <&rcar_dw_hdmi0_out>;
};
arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
浏览文件 @ 8efcf34a
...@@ -31,9 +31,57 @@ ...@@ -31,9 +31,57 @@
/* first 128MB is reserved for secure area. */ /* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x38000000>; reg = <0x0 0x48000000 0x0 0x38000000>;
}; };
hdmi-out {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_out: endpoint {
remote-endpoint = <&adv7511_out>;
};
};
};
d3p3: regulator-fixed {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
lvds-decoder {
compatible = "thine,thc63lvd1024";
vcc-supply = <&d3p3>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
thc63lvd1024_in: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
port@2 {
reg = <2>;
thc63lvd1024_out: endpoint {
remote-endpoint = <&adv7511_in>;
};
};
};
};
}; };
&avb { &avb {
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
renesas,no-ether-link; renesas,no-ether-link;
phy-handle = <&phy0>; phy-handle = <&phy0>;
phy-mode = "rgmii-id"; phy-mode = "rgmii-id";
...@@ -47,6 +95,16 @@ ...@@ -47,6 +95,16 @@
}; };
}; };
&canfd {
pinctrl-0 = <&canfd0_pins>;
pinctrl-names = "default";
status = "okay";
channel0 {
status = "okay";
};
};
&extal_clk { &extal_clk {
clock-frequency = <16666666>; clock-frequency = <16666666>;
}; };
...@@ -68,9 +126,51 @@ ...@@ -68,9 +126,51 @@
gpio-controller; gpio-controller;
#gpio-cells = <2>; #gpio-cells = <2>;
}; };
hdmi@39 {
compatible = "adi,adv7511w";
reg = <0x39>;
interrupt-parent = <&gpio1>;
interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
adi,input-style = <1>;
adi,input-justification = "evenly";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7511_in: endpoint {
remote-endpoint = <&thc63lvd1024_out>;
};
};
port@1 {
reg = <1>;
adv7511_out: endpoint {
remote-endpoint = <&hdmi_con_out>;
};
};
};
};
}; };
&pfc { &pfc {
avb_pins: avb0 {
groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
function = "avb0";
};
canfd0_pins: canfd0 {
groups = "canfd0_data_a";
function = "canfd0";
};
i2c0_pins: i2c0 { i2c0_pins: i2c0 {
groups = "i2c0"; groups = "i2c0";
function = "i2c0"; function = "i2c0";
...@@ -93,3 +193,19 @@ ...@@ -93,3 +193,19 @@
status = "okay"; status = "okay";
}; };
&du {
status = "okay";
};
&lvds0 {
status = "okay";
ports {
port@1 {
lvds0_out: endpoint {
remote-endpoint = <&thc63lvd1024_in>;
};
};
};
};
arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
浏览文件 @ 8efcf34a
...@@ -29,9 +29,71 @@ ...@@ -29,9 +29,71 @@
/* first 128MB is reserved for secure area. */ /* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x38000000>; reg = <0x0 0x48000000 0x0 0x38000000>;
}; };
osc5_clk: osc5-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <148500000>;
};
vcc_d1_8v: regulator-0 {
compatible = "regulator-fixed";
regulator-name = "VCC_D1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
vcc_d3_3v: regulator-1 {
compatible = "regulator-fixed";
regulator-name = "VCC_D3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
lvds-decoder {
compatible = "thine,thc63lvd1024";
vcc-supply = <&vcc_d3_3v>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
thc63lvd1024_in: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
port@2 {
reg = <2>;
thc63lvd1024_out: endpoint {
remote-endpoint = <&adv7511_in>;
};
};
};
};
hdmi-out {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con: endpoint {
remote-endpoint = <&adv7511_out>;
};
};
};
}; };
&avb { &avb {
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
renesas,no-ether-link; renesas,no-ether-link;
phy-handle = <&phy0>; phy-handle = <&phy0>;
phy-mode = "rgmii-id"; phy-mode = "rgmii-id";
...@@ -43,6 +105,13 @@ ...@@ -43,6 +105,13 @@
}; };
}; };
&du {
clocks = <&cpg CPG_MOD 724>,
<&osc5_clk>;
clock-names = "du.0", "dclkin.0";
status = "okay";
};
&extal_clk { &extal_clk {
clock-frequency = <16666666>; clock-frequency = <16666666>;
}; };
...@@ -52,12 +121,80 @@ ...@@ -52,12 +121,80 @@
}; };
&pfc { &pfc {
avb_pins: avb0 {
groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
function = "avb0";
};
i2c0_pins: i2c0 {
groups = "i2c0";
function = "i2c0";
};
scif0_pins: scif0 { scif0_pins: scif0 {
groups = "scif0_data"; groups = "scif0_data";
function = "scif0"; function = "scif0";
}; };
}; };
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
hdmi@39{
compatible = "adi,adv7511w";
#sound-dai-cells = <0>;
reg = <0x39>;
interrupt-parent = <&gpio1>;
interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
avdd-supply = <&vcc_d1_8v>;
dvdd-supply = <&vcc_d1_8v>;
pvdd-supply = <&vcc_d1_8v>;
bgvdd-supply = <&vcc_d1_8v>;
dvdd-3v-supply = <&vcc_d3_3v>;
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
adi,input-style = <1>;
adi,input-justification = "evenly";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7511_in: endpoint {
remote-endpoint = <&thc63lvd1024_out>;
};
};
port@1 {
reg = <1>;
adv7511_out: endpoint {
remote-endpoint = <&hdmi_con>;
};
};
};
};
};
&lvds0 {
status = "okay";
ports {
port@1 {
lvds0_out: endpoint {
remote-endpoint = <&thc63lvd1024_in>;
};
};
};
};
&scif0 { &scif0 {
pinctrl-0 = <&scif0_pins>; pinctrl-0 = <&scif0_pins>;
pinctrl-names = "default"; pinctrl-names = "default";
......
arch/arm64/boot/dts/renesas/r8a77980-condor.dts
浏览文件 @ 8efcf34a
...@@ -27,9 +27,30 @@ ...@@ -27,9 +27,30 @@
/* first 128MB is reserved for secure area. */ /* first 128MB is reserved for secure area. */
reg = <0 0x48000000 0 0x78000000>; reg = <0 0x48000000 0 0x78000000>;
}; };
d3_3v: regulator-0 {
compatible = "regulator-fixed";
regulator-name = "D3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
vddq_vin01: regulator-1 {
compatible = "regulator-fixed";
regulator-name = "VDDQ_VIN01";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
}; };
&avb { &avb {
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
phy-mode = "rgmii-id"; phy-mode = "rgmii-id";
phy-handle = <&phy0>; phy-handle = <&phy0>;
renesas,no-ether-link; renesas,no-ether-link;
...@@ -41,6 +62,16 @@ ...@@ -41,6 +62,16 @@
}; };
}; };
&canfd {
pinctrl-0 = <&canfd0_pins>;
pinctrl-names = "default";
status = "okay";
channel0 {
status = "okay";
};
};
&extal_clk { &extal_clk {
clock-frequency = <16666666>; clock-frequency = <16666666>;
}; };
...@@ -49,7 +80,57 @@ ...@@ -49,7 +80,57 @@
clock-frequency = <32768>; clock-frequency = <32768>;
}; };
&mmc0 {
pinctrl-0 = <&mmc_pins>;
pinctrl-1 = <&mmc_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&d3_3v>;
vqmmc-supply = <&vddq_vin01>;
mmc-hs200-1_8v;
bus-width = <8>;
non-removable;
status = "okay";
};
&pfc {
avb_pins: avb {
groups = "avb_mdio", "avb_rgmii";
function = "avb";
};
canfd0_pins: canfd0 {
groups = "canfd0_data_a";
function = "canfd0";
};
mmc_pins: mmc {
groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
function = "mmc";
power-source = <3300>;
};
mmc_pins_uhs: mmc_uhs {
groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
function = "mmc";
power-source = <1800>;
};
scif0_pins: scif0 {
groups = "scif0_data";
function = "scif0";
};
scif_clk_pins: scif_clk {
groups = "scif_clk_b";
function = "scif_clk";
};
};
&scif0 { &scif0 {
pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
pinctrl-names = "default";
status = "okay"; status = "okay";
}; };
......
arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts 0 → 100644
浏览文件 @ 8efcf34a
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the V3H Starter Kit board
*
* Copyright (C) 2018 Renesas Electronics Corp.
* Copyright (C) 2018 Cogent Embedded, Inc.
*/
/dts-v1/;
#include "r8a77980.dtsi"
/ {
model = "Renesas V3H Starter Kit board";
compatible = "renesas,v3hsk", "renesas,r8a77980";
aliases {
serial0 = &scif0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0 0x48000000 0 0x78000000>;
};
};
&extal_clk {
clock-frequency = <16666666>;
};
&extalr_clk {
clock-frequency = <32768>;
};
&pfc {
scif0_pins: scif0 {
groups = "scif0_data";
function = "scif0";
};
scif_clk_pins: scif_clk {
groups = "scif_clk_b";
function = "scif_clk";
};
};
&scif0 {
pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
pinctrl-names = "default";
status = "okay";
};
&scif_clk {
clock-frequency = <14745600>;
};
arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts 0 → 100644
浏览文件 @ 8efcf34a
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Device Tree Source for the ebisu board
*
* Copyright (C) 2018 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a77990.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Renesas Ebisu board based on r8a77990";
compatible = "renesas,ebisu", "renesas,r8a77990";
aliases {
serial0 = &scif2;
ethernet0 = &avb;
};
chosen {
bootargs = "ignore_loglevel";
stdout-path = "serial0:115200n8";
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x38000000>;
};
};
&avb {
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
renesas,no-ether-link;
phy-handle = <&phy0>;
phy-mode = "rgmii-txid";
status = "okay";
phy0: ethernet-phy@0 {
rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio2>;
interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
};
};
&extal_clk {
clock-frequency = <48000000>;
};
&pfc {
avb_pins: avb {
mux {
groups = "avb_link", "avb_mii";
function = "avb";
};
};
};
&scif2 {
status = "okay";
};
arch/arm64/boot/dts/renesas/r8a77990.dtsi 0 → 100644
浏览文件 @ 8efcf34a
此差异已折叠。
arch/arm64/boot/dts/renesas/r8a77995-draak.dts
浏览文件 @ 8efcf34a
...@@ -91,7 +91,7 @@ ...@@ -91,7 +91,7 @@
&pfc { &pfc {
avb0_pins: avb { avb0_pins: avb {
mux { mux {
groups = "avb0_link", "avb0_mdc", "avb0_mii"; groups = "avb0_link", "avb0_mdio", "avb0_mii";
function = "avb0"; function = "avb0";
}; };
}; };
......
arch/arm64/boot/dts/renesas/ulcb.dtsi
浏览文件 @ 8efcf34a
...@@ -243,6 +243,32 @@ ...@@ -243,6 +243,32 @@
&i2c_dvfs { &i2c_dvfs {
status = "okay"; status = "okay";
pmic: pmic@30 {
pinctrl-0 = <&irq0_pins>;
pinctrl-names = "default";
compatible = "rohm,bd9571mwv";
reg = <0x30>;
interrupt-parent = <&intc_ex>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
rohm,ddr-backup-power = <0xf>;
rohm,rstbmode-pulse;
regulators {
dvfs: dvfs {
regulator-name = "dvfs";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1030000>;
regulator-boot-on;
regulator-always-on;
};
};
};
}; };
&ohci1 { &ohci1 {
...@@ -255,12 +281,12 @@ ...@@ -255,12 +281,12 @@
avb_pins: avb { avb_pins: avb {
mux { mux {
groups = "avb_link", "avb_mdc", "avb_mii"; groups = "avb_link", "avb_mdio", "avb_mii";
function = "avb"; function = "avb";
}; };
pins_mdc { pins_mdio {
groups = "avb_mdc"; groups = "avb_mdio";
drive-strength = <24>; drive-strength = <24>;
}; };
...@@ -276,6 +302,11 @@ ...@@ -276,6 +302,11 @@
function = "i2c2"; function = "i2c2";
}; };
irq0_pins: irq0 {
groups = "intc_ex_irq0";
function = "intc_ex";
};
scif2_pins: scif2 { scif2_pins: scif2 {
groups = "scif2_data_a"; groups = "scif2_data_a";
function = "scif2"; function = "scif2";
......
drivers/firmware/qcom_scm.c
浏览文件 @ 8efcf34a
...@@ -603,6 +603,9 @@ static const struct of_device_id qcom_scm_dt_match[] = { ...@@ -603,6 +603,9 @@ static const struct of_device_id qcom_scm_dt_match[] = {
{ .compatible = "qcom,scm-msm8996", { .compatible = "qcom,scm-msm8996",
.data = NULL, /* no clocks */ .data = NULL, /* no clocks */
}, },
{ .compatible = "qcom,scm-ipq4019",
.data = NULL, /* no clocks */
},
{ .compatible = "qcom,scm", { .compatible = "qcom,scm",
.data = (void *)(SCM_HAS_CORE_CLK .data = (void *)(SCM_HAS_CORE_CLK
| SCM_HAS_IFACE_CLK | SCM_HAS_IFACE_CLK
......
drivers/of/platform.c
浏览文件 @ 8efcf34a
...@@ -505,6 +505,7 @@ EXPORT_SYMBOL_GPL(of_platform_default_populate); ...@@ -505,6 +505,7 @@ EXPORT_SYMBOL_GPL(of_platform_default_populate);
#ifndef CONFIG_PPC #ifndef CONFIG_PPC
static const struct of_device_id reserved_mem_matches[] = { static const struct of_device_id reserved_mem_matches[] = {
{ .compatible = "qcom,rmtfs-mem" }, { .compatible = "qcom,rmtfs-mem" },
{ .compatible = "qcom,cmd-db" },
{ .compatible = "ramoops" }, { .compatible = "ramoops" },
{} {}
}; };
......
drivers/soc/Makefile
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...@@ -14,7 +14,7 @@ obj-$(CONFIG_ARCH_MXC) += imx/ ...@@ -14,7 +14,7 @@ obj-$(CONFIG_ARCH_MXC) += imx/
obj-$(CONFIG_SOC_XWAY) += lantiq/ obj-$(CONFIG_SOC_XWAY) += lantiq/
obj-y += mediatek/ obj-y += mediatek/
obj-$(CONFIG_ARCH_MESON) += amlogic/ obj-$(CONFIG_ARCH_MESON) += amlogic/
obj-$(CONFIG_ARCH_QCOM) += qcom/ obj-y += qcom/
obj-y += renesas/ obj-y += renesas/
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
obj-$(CONFIG_SOC_SAMSUNG) += samsung/ obj-$(CONFIG_SOC_SAMSUNG) += samsung/
......
drivers/soc/qcom/Kconfig
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...@@ -3,6 +3,24 @@ ...@@ -3,6 +3,24 @@
# #
menu "Qualcomm SoC drivers" menu "Qualcomm SoC drivers"
config QCOM_COMMAND_DB
bool "Qualcomm Command DB"
depends on (ARCH_QCOM && OF) || COMPILE_TEST
help
Command DB queries shared memory by key string for shared system
resources. Platform drivers that require to set state of a shared
resource on a RPM-hardened platform must use this database to get
SoC specific identifier and information for the shared resources.
config QCOM_GENI_SE
tristate "QCOM GENI Serial Engine Driver"
depends on ARCH_QCOM || COMPILE_TEST
help
This driver is used to manage Generic Interface (GENI) firmware based
Qualcomm Technologies, Inc. Universal Peripheral (QUP) Wrapper. This
driver is also used to manage the common aspects of multiple Serial
Engines present in the QUP.
config QCOM_GLINK_SSR config QCOM_GLINK_SSR
tristate "Qualcomm Glink SSR driver" tristate "Qualcomm Glink SSR driver"
depends on RPMSG depends on RPMSG
......
drivers/soc/qcom/Makefile
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drivers/soc/qcom/cmd-db.c 0 → 100644
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drivers/soc/qcom/qcom-geni-se.c 0 → 100644
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drivers/soc/qcom/qmi_interface.c
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drivers/soc/qcom/smd-rpm.c
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drivers/soc/qcom/smem.c
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include/linux/qcom-geni-se.h 0 → 100644
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include/linux/soc/qcom/smem.h
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此差异已折叠。
include/soc/qcom/cmd-db.h 0 → 100644
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此差异已折叠。
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