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kernel_linux
提交 7f6233ca 编写于 作者: A Alex Deucher
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drm/radeon/ci: force pcie level before sclk and mclk 

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Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
上级 e745c3c9
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Showing with 17 addition and 17 deletion
drivers/gpu/drm/radeon/ci_dpm.c
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...@@ -4143,57 +4143,57 @@ int ci_dpm_force_performance_level(struct radeon_device *rdev, ...@@ -4143,57 +4143,57 @@ int ci_dpm_force_performance_level(struct radeon_device *rdev,
int ret; int ret;
if (level == RADEON_DPM_FORCED_LEVEL_HIGH) { if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
if ((!pi->sclk_dpm_key_disabled) && if ((!pi->pcie_dpm_key_disabled) &&
pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
levels = 0; levels = 0;
tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask; tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask;
while (tmp >>= 1) while (tmp >>= 1)
levels++; levels++;
if (levels) { if (levels) {
ret = ci_dpm_force_state_sclk(rdev, levels); ret = ci_dpm_force_state_pcie(rdev, level);
if (ret) if (ret)
return ret; return ret;
for (i = 0; i < rdev->usec_timeout; i++) { for (i = 0; i < rdev->usec_timeout; i++) {
tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &
CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT; CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT;
if (tmp == levels) if (tmp == levels)
break; break;
udelay(1); udelay(1);
} }
} }
} }
if ((!pi->mclk_dpm_key_disabled) && if ((!pi->sclk_dpm_key_disabled) &&
pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
levels = 0; levels = 0;
tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask; tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask;
while (tmp >>= 1) while (tmp >>= 1)
levels++; levels++;
if (levels) { if (levels) {
ret = ci_dpm_force_state_mclk(rdev, levels); ret = ci_dpm_force_state_sclk(rdev, levels);
if (ret) if (ret)
return ret; return ret;
for (i = 0; i < rdev->usec_timeout; i++) { for (i = 0; i < rdev->usec_timeout; i++) {
tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT; CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT;
if (tmp == levels) if (tmp == levels)
break; break;
udelay(1); udelay(1);
} }
} }
} }
if ((!pi->pcie_dpm_key_disabled) && if ((!pi->mclk_dpm_key_disabled) &&
pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
levels = 0; levels = 0;
tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask; tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
while (tmp >>= 1) while (tmp >>= 1)
levels++; levels++;
if (levels) { if (levels) {
ret = ci_dpm_force_state_pcie(rdev, level); ret = ci_dpm_force_state_mclk(rdev, levels);
if (ret) if (ret)
return ret; return ret;
for (i = 0; i < rdev->usec_timeout; i++) { for (i = 0; i < rdev->usec_timeout; i++) {
tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) & tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT; CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT;
if (tmp == levels) if (tmp == levels)
break; break;
udelay(1); udelay(1);
......
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