diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 7ea274475598d60e7a5f54c9c80f7943cab9687c..4fa856e9a87273428b0da890e69d7821bf11ce97 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -203,10 +203,14 @@ static void dcn10_log_hw_state(struct dc *dc)
 
 	for (i = 0; i < pool->pipe_count; i++) {
 		struct timing_generator *tg = pool->timing_generators[i];
-		struct dcn_otg_state s;
+		struct dcn_otg_state s = {0};
 
 		tgn10_read_otg_state(DCN10TG_FROM_TG(tg), &s);
 
+		//only print if OTG master is enabled
+		if ((s.otg_enabled & 1) == 0)
+			continue;
+
 		DTN_INFO("[%d]:\t %d \t %d \t %d \t %d \t "
 				"%d \t %d \t %d \t %d \t %d \t %d \t "
 				"%d \t %d \t %d \t %d \t %d \t ",
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
index 15f1f44e102acbc369234cd9e868da20056f7d35..405f595f219a4a8ce12e347acaaaf7f4b81eb9b8 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
@@ -1100,6 +1100,9 @@ static bool tgn10_is_stereo_left_eye(struct timing_generator *tg)
 void tgn10_read_otg_state(struct dcn10_timing_generator *tgn10,
 		struct dcn_otg_state *s)
 {
+	REG_GET(OTG_CONTROL,
+			OTG_MASTER_EN, &s->otg_enabled);
+
 	REG_GET_2(OTG_V_BLANK_START_END,
 			OTG_V_BLANK_START, &s->v_blank_start,
 			OTG_V_BLANK_END, &s->v_blank_end);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h
index 38d3dcf89d60d4617a6e8ed6b0c9dd1eb8056d1c..69da293e9b4a95bbe79b750b4fd86e9a4569ac27 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h
@@ -370,6 +370,7 @@ struct dcn_otg_state {
 	uint32_t h_sync_a_pol;
 	uint32_t h_total;
 	uint32_t underflow_occurred_status;
+	uint32_t otg_enabled;
 };
 
 void tgn10_read_otg_state(struct dcn10_timing_generator *tgn10,