提交 65fe31da 编写于 作者: P Peter De Schrijver 提交者: Olof Johansson

ARM: tegra: support for Tegra30 CPU powerdomains

Secondary CPU powerdomains can be powergated on Tegra30. Add the necessary
functions to do this. This will be used to boot the secondary CPUs later on.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: NStephen Warren <swarren@nvidia.com>
Tested-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>
上级 6cafa97d
...@@ -28,6 +28,7 @@ ...@@ -28,6 +28,7 @@
#include <mach/iomap.h> #include <mach/iomap.h>
#include <mach/system.h> #include <mach/system.h>
#include <mach/powergate.h>
#include "board.h" #include "board.h"
#include "clock.h" #include "clock.h"
...@@ -119,6 +120,7 @@ void __init tegra20_init_early(void) ...@@ -119,6 +120,7 @@ void __init tegra20_init_early(void)
tegra_clk_init_from_table(tegra20_clk_init_table); tegra_clk_init_from_table(tegra20_clk_init_table);
tegra_init_cache(0x331, 0x441); tegra_init_cache(0x331, 0x441);
tegra_pmc_init(); tegra_pmc_init();
tegra_powergate_init();
} }
#endif #endif
#ifdef CONFIG_ARCH_TEGRA_3x_SOC #ifdef CONFIG_ARCH_TEGRA_3x_SOC
...@@ -128,5 +130,6 @@ void __init tegra30_init_early(void) ...@@ -128,5 +130,6 @@ void __init tegra30_init_early(void)
tegra30_init_clocks(); tegra30_init_clocks();
tegra_init_cache(0x441, 0x551); tegra_init_cache(0x441, 0x551);
tegra_pmc_init(); tegra_pmc_init();
tegra_powergate_init();
} }
#endif #endif
...@@ -38,6 +38,9 @@ ...@@ -38,6 +38,9 @@
#define TEGRA_POWERGATE_CPU0 TEGRA_POWERGATE_CPU #define TEGRA_POWERGATE_CPU0 TEGRA_POWERGATE_CPU
#define TEGRA_POWERGATE_3D0 TEGRA_POWERGATE_3D #define TEGRA_POWERGATE_3D0 TEGRA_POWERGATE_3D
int __init tegra_powergate_init(void);
int tegra_cpu_powergate_id(int cpuid);
int tegra_powergate_is_powered(int id); int tegra_powergate_is_powered(int id);
int tegra_powergate_power_on(int id); int tegra_powergate_power_on(int id);
int tegra_powergate_power_off(int id); int tegra_powergate_power_off(int id);
......
...@@ -41,6 +41,14 @@ ...@@ -41,6 +41,14 @@
#define PWRGATE_STATUS 0x38 #define PWRGATE_STATUS 0x38
static int tegra_num_powerdomains; static int tegra_num_powerdomains;
static int tegra_num_cpu_domains;
static u8 *tegra_cpu_domains;
static u8 tegra30_cpu_domains[] = {
TEGRA_POWERGATE_CPU0,
TEGRA_POWERGATE_CPU1,
TEGRA_POWERGATE_CPU2,
TEGRA_POWERGATE_CPU3,
};
static DEFINE_SPINLOCK(tegra_powergate_lock); static DEFINE_SPINLOCK(tegra_powergate_lock);
...@@ -161,6 +169,14 @@ int tegra_powergate_sequence_power_up(int id, struct clk *clk) ...@@ -161,6 +169,14 @@ int tegra_powergate_sequence_power_up(int id, struct clk *clk)
return ret; return ret;
} }
int tegra_cpu_powergate_id(int cpuid)
{
if (cpuid > 0 && cpuid < tegra_num_cpu_domains)
return tegra_cpu_domains[cpuid];
return -EINVAL;
}
int __init tegra_powergate_init(void) int __init tegra_powergate_init(void)
{ {
switch (tegra_chip_id) { switch (tegra_chip_id) {
...@@ -169,6 +185,8 @@ int __init tegra_powergate_init(void) ...@@ -169,6 +185,8 @@ int __init tegra_powergate_init(void)
break; break;
case TEGRA30: case TEGRA30:
tegra_num_powerdomains = 14; tegra_num_powerdomains = 14;
tegra_num_cpu_domains = 4;
tegra_cpu_domains = tegra30_cpu_domains;
break; break;
default: default:
/* Unknown Tegra variant. Disable powergating */ /* Unknown Tegra variant. Disable powergating */
...@@ -178,7 +196,6 @@ int __init tegra_powergate_init(void) ...@@ -178,7 +196,6 @@ int __init tegra_powergate_init(void)
return 0; return 0;
} }
arch_initcall(tegra_powergate_init);
#ifdef CONFIG_DEBUG_FS #ifdef CONFIG_DEBUG_FS
......
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