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提交 60883e28 编写于 作者: M Mike Frysinger
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Blackfin: unify BF547/8/9 headers 

No point in duplicating entire lists when we can simply tail into other
parts for most of the MMRs.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>
上级 4ed250a5
隐藏空白更改
内联 并排
Showing with 8 addition and 5098 deletion
arch/blackfin/mach-bf548/include/mach/cdefBF548.h
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......@@ -18,165 +18,8 @@
/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
#include "cdefBF54x_base.h"
/* The following are the #defines needed by ADSP-BF548 that are not in the common header */
/* Timer Registers */
#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)
#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val)
#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)
#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)
#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)
#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)
#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val)
#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)
#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)
#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)
#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)
#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)
#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)
#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)
#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)
#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)
#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)
/* Timer Groubfin_read_() of 3 */
#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1)
#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val)
#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1)
#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1)
#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)
/* SPORT0 Registers */
#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
/* EPPI0 Registers */
#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS)
#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val)
#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT)
#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val)
#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY)
#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val)
#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT)
#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val)
#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY)
#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val)
#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME)
#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val)
#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE)
#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val)
#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV)
#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val)
#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL)
#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val)
#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL)
#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL)
#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB)
#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF)
#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP)
#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val)
/* UART2 Registers */
#define bfin_read_UART2_DLL() bfin_read16(UART2_DLL)
#define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val)
#define bfin_read_UART2_DLH() bfin_read16(UART2_DLH)
#define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val)
#define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL)
#define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val)
#define bfin_read_UART2_LCR() bfin_read16(UART2_LCR)
#define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val)
#define bfin_read_UART2_MCR() bfin_read16(UART2_MCR)
#define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val)
#define bfin_read_UART2_LSR() bfin_read16(UART2_LSR)
#define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val)
#define bfin_read_UART2_MSR() bfin_read16(UART2_MSR)
#define bfin_write_UART2_MSR(val) bfin_write16(UART2_MSR, val)
#define bfin_read_UART2_SCR() bfin_read16(UART2_SCR)
#define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val)
#define bfin_read_UART2_IER_SET() bfin_read16(UART2_IER_SET)
#define bfin_write_UART2_IER_SET(val) bfin_write16(UART2_IER_SET, val)
#define bfin_read_UART2_IER_CLEAR() bfin_read16(UART2_IER_CLEAR)
#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val)
#define bfin_read_UART2_RBR() bfin_read16(UART2_RBR)
#define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val)
/* Two Wire Interface Registers (TWI1) */
/* SPI2 Registers */
#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL)
#define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val)
#define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG)
#define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val)
#define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT)
#define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val)
#define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR)
#define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val)
#define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR)
#define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val)
#define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD)
#define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val)
#define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW)
#define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val)
/* The BF548 is like the BF547, but has additional CANs */
#include "cdefBF547.h"
/* CAN Controller 1 Config 1 Registers */
......@@ -923,631 +766,4 @@
#define bfin_read_CAN1_MB31_ID1() bfin_read16(CAN1_MB31_ID1)
#define bfin_write_CAN1_MB31_ID1(val) bfin_write16(CAN1_MB31_ID1, val)
/* ATAPI Registers */
#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL)
#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val)
#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS)
#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val)
#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR)
#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF)
#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF)
#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK)
#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS)
#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN)
#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS)
#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE)
#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE)
#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT)
#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT)
#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0)
#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0)
#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1)
#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0)
#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1)
#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2)
#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0)
#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1)
#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2)
#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3)
#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
/* SDH Registers */
#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL)
#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val)
#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL)
#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val)
#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT)
#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val)
#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND)
#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val)
#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD)
#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val)
#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0)
#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val)
#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1)
#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val)
#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2)
#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val)
#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3)
#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val)
#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER)
#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH)
#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val)
#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL)
#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val)
#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT)
#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val)
#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS)
#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val)
#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR)
#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0)
#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val)
#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1)
#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val)
#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT)
#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val)
#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO)
#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val)
#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS)
#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val)
#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK)
#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val)
#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG)
#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val)
#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN)
#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0)
#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val)
#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1)
#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val)
#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2)
#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val)
#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3)
#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val)
#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4)
#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val)
#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5)
#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val)
#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6)
#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val)
#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7)
#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val)
/* HOST Port Registers */
#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
/* USB Control Registers */
#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
/* USB Packet Control Registers */
#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
/* USB Endbfin_read_()oint FIFO Registers */
#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
/* USB OTG Control Registers */
#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
/* USB Phy Control Registers */
#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
/* (APHY_CNTRL is for ADI usage only) */
#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
/* (APHY_CALIB is for ADI usage only) */
#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
/* (PHY_TEST is for ADI usage only) */
#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST)
#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val)
#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
/* USB Endbfin_read_()oint 0 Control Registers */
#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
/* USB Endbfin_read_()oint 1 Control Registers */
#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
/* USB Endbfin_read_()oint 2 Control Registers */
#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
/* USB Endbfin_read_()oint 3 Control Registers */
#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
/* USB Endbfin_read_()oint 4 Control Registers */
#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
/* USB Endbfin_read_()oint 5 Control Registers */
#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
/* USB Endbfin_read_()oint 6 Control Registers */
#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
/* USB Endbfin_read_()oint 7 Control Registers */
#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
/* USB Channel 0 Config Registers */
#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL)
#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val)
#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW)
#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val)
#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH)
#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val)
#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW)
#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val)
#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH)
#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val)
/* USB Channel 1 Config Registers */
#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL)
#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val)
#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW)
#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val)
#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH)
#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val)
#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW)
#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val)
#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH)
#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val)
/* USB Channel 2 Config Registers */
#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL)
#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val)
#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW)
#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val)
#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH)
#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val)
#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW)
#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val)
#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH)
#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val)
/* USB Channel 3 Config Registers */
#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL)
#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val)
#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW)
#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val)
#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH)
#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val)
#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW)
#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val)
#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH)
#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val)
/* USB Channel 4 Config Registers */
#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL)
#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val)
#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW)
#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val)
#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH)
#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val)
#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW)
#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val)
#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH)
#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val)
/* USB Channel 5 Config Registers */
#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL)
#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val)
#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW)
#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val)
#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH)
#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW)
#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val)
#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH)
#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
/* USB Channel 6 Config Registers */
#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL)
#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val)
#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW)
#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val)
#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH)
#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val)
#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW)
#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val)
#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH)
#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val)
/* USB Channel 7 Config Registers */
#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL)
#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val)
#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW)
#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val)
#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH)
#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val)
#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW)
#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val)
#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH)
#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val)
/* Keybfin_read_()ad Registers */
#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL)
#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val)
#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE)
#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val)
#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL)
#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val)
#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL)
#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val)
#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT)
#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val)
#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL)
#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val)
/* Pixel Combfin_read_()ositor (PIXC) Registers */
#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL)
#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val)
#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL)
#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val)
#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF)
#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val)
#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART)
#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val)
#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND)
#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val)
#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART)
#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val)
#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND)
#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val)
#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP)
#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val)
#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART)
#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val)
#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND)
#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val)
#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART)
#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val)
#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND)
#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val)
#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP)
#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val)
#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT)
#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val)
#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON)
#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val)
#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON)
#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val)
#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON)
#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val)
#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS)
#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val)
#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC)
#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val)
/* Handshake MDMA 0 Registers */
#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
/* Handshake MDMA 1 Registers */
#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
#endif /* _CDEF_BF548_H */
arch/blackfin/mach-bf548/include/mach/cdefBF549.h
浏览文件 @ 60883e28
......@@ -18,165 +18,8 @@
/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
#include "cdefBF54x_base.h"
/* The following are the #defines needed by ADSP-BF549 that are not in the common header */
/* Timer Registers */
#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)
#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val)
#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)
#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)
#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)
#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)
#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val)
#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)
#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)
#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)
#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)
#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)
#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)
#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)
#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)
#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)
#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)
/* Timer Groubfin_read_() of 3 */
#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1)
#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val)
#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1)
#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1)
#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)
/* SPORT0 Registers */
#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
/* EPPI0 Registers */
#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS)
#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val)
#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT)
#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val)
#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY)
#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val)
#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT)
#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val)
#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY)
#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val)
#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME)
#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val)
#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE)
#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val)
#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV)
#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val)
#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL)
#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val)
#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL)
#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL)
#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB)
#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF)
#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP)
#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val)
/* UART2 Registers */
#define bfin_read_UART2_DLL() bfin_read16(UART2_DLL)
#define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val)
#define bfin_read_UART2_DLH() bfin_read16(UART2_DLH)
#define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val)
#define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL)
#define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val)
#define bfin_read_UART2_LCR() bfin_read16(UART2_LCR)
#define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val)
#define bfin_read_UART2_MCR() bfin_read16(UART2_MCR)
#define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val)
#define bfin_read_UART2_LSR() bfin_read16(UART2_LSR)
#define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val)
#define bfin_read_UART2_MSR() bfin_read16(UART2_MSR)
#define bfin_write_UART2_MSR(val) bfin_write16(UART2_MSR, val)
#define bfin_read_UART2_SCR() bfin_read16(UART2_SCR)
#define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val)
#define bfin_read_UART2_IER_SET() bfin_read16(UART2_IER_SET)
#define bfin_write_UART2_IER_SET(val) bfin_write16(UART2_IER_SET, val)
#define bfin_read_UART2_IER_CLEAR() bfin_read16(UART2_IER_CLEAR)
#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val)
#define bfin_read_UART2_RBR() bfin_read16(UART2_RBR)
#define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val)
/* Two Wire Interface Registers (TWI1) */
/* SPI2 Registers */
#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL)
#define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val)
#define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG)
#define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val)
#define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT)
#define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val)
#define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR)
#define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val)
#define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR)
#define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val)
#define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD)
#define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val)
#define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW)
#define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val)
/* The BF549 is like the BF544, but has MXVR */
#include "cdefBF547.h"
/* MXVR Registers */
......@@ -464,1376 +307,4 @@
#define bfin_read_MXVR_SCLK_CNT() bfin_read16(MXVR_SCLK_CNT)
#define bfin_write_MXVR_SCLK_CNT(val) bfin_write16(MXVR_SCLK_CNT, val)
/* CAN Controller 1 Config 1 Registers */
#define bfin_read_CAN1_MC1() bfin_read16(CAN1_MC1)
#define bfin_write_CAN1_MC1(val) bfin_write16(CAN1_MC1, val)
#define bfin_read_CAN1_MD1() bfin_read16(CAN1_MD1)
#define bfin_write_CAN1_MD1(val) bfin_write16(CAN1_MD1, val)
#define bfin_read_CAN1_TRS1() bfin_read16(CAN1_TRS1)
#define bfin_write_CAN1_TRS1(val) bfin_write16(CAN1_TRS1, val)
#define bfin_read_CAN1_TRR1() bfin_read16(CAN1_TRR1)
#define bfin_write_CAN1_TRR1(val) bfin_write16(CAN1_TRR1, val)
#define bfin_read_CAN1_TA1() bfin_read16(CAN1_TA1)
#define bfin_write_CAN1_TA1(val) bfin_write16(CAN1_TA1, val)
#define bfin_read_CAN1_AA1() bfin_read16(CAN1_AA1)
#define bfin_write_CAN1_AA1(val) bfin_write16(CAN1_AA1, val)
#define bfin_read_CAN1_RMP1() bfin_read16(CAN1_RMP1)
#define bfin_write_CAN1_RMP1(val) bfin_write16(CAN1_RMP1, val)
#define bfin_read_CAN1_RML1() bfin_read16(CAN1_RML1)
#define bfin_write_CAN1_RML1(val) bfin_write16(CAN1_RML1, val)
#define bfin_read_CAN1_MBTIF1() bfin_read16(CAN1_MBTIF1)
#define bfin_write_CAN1_MBTIF1(val) bfin_write16(CAN1_MBTIF1, val)
#define bfin_read_CAN1_MBRIF1() bfin_read16(CAN1_MBRIF1)
#define bfin_write_CAN1_MBRIF1(val) bfin_write16(CAN1_MBRIF1, val)
#define bfin_read_CAN1_MBIM1() bfin_read16(CAN1_MBIM1)
#define bfin_write_CAN1_MBIM1(val) bfin_write16(CAN1_MBIM1, val)
#define bfin_read_CAN1_RFH1() bfin_read16(CAN1_RFH1)
#define bfin_write_CAN1_RFH1(val) bfin_write16(CAN1_RFH1, val)
#define bfin_read_CAN1_OPSS1() bfin_read16(CAN1_OPSS1)
#define bfin_write_CAN1_OPSS1(val) bfin_write16(CAN1_OPSS1, val)
/* CAN Controller 1 Config 2 Registers */
#define bfin_read_CAN1_MC2() bfin_read16(CAN1_MC2)
#define bfin_write_CAN1_MC2(val) bfin_write16(CAN1_MC2, val)
#define bfin_read_CAN1_MD2() bfin_read16(CAN1_MD2)
#define bfin_write_CAN1_MD2(val) bfin_write16(CAN1_MD2, val)
#define bfin_read_CAN1_TRS2() bfin_read16(CAN1_TRS2)
#define bfin_write_CAN1_TRS2(val) bfin_write16(CAN1_TRS2, val)
#define bfin_read_CAN1_TRR2() bfin_read16(CAN1_TRR2)
#define bfin_write_CAN1_TRR2(val) bfin_write16(CAN1_TRR2, val)
#define bfin_read_CAN1_TA2() bfin_read16(CAN1_TA2)
#define bfin_write_CAN1_TA2(val) bfin_write16(CAN1_TA2, val)
#define bfin_read_CAN1_AA2() bfin_read16(CAN1_AA2)
#define bfin_write_CAN1_AA2(val) bfin_write16(CAN1_AA2, val)
#define bfin_read_CAN1_RMP2() bfin_read16(CAN1_RMP2)
#define bfin_write_CAN1_RMP2(val) bfin_write16(CAN1_RMP2, val)
#define bfin_read_CAN1_RML2() bfin_read16(CAN1_RML2)
#define bfin_write_CAN1_RML2(val) bfin_write16(CAN1_RML2, val)
#define bfin_read_CAN1_MBTIF2() bfin_read16(CAN1_MBTIF2)
#define bfin_write_CAN1_MBTIF2(val) bfin_write16(CAN1_MBTIF2, val)
#define bfin_read_CAN1_MBRIF2() bfin_read16(CAN1_MBRIF2)
#define bfin_write_CAN1_MBRIF2(val) bfin_write16(CAN1_MBRIF2, val)
#define bfin_read_CAN1_MBIM2() bfin_read16(CAN1_MBIM2)
#define bfin_write_CAN1_MBIM2(val) bfin_write16(CAN1_MBIM2, val)
#define bfin_read_CAN1_RFH2() bfin_read16(CAN1_RFH2)
#define bfin_write_CAN1_RFH2(val) bfin_write16(CAN1_RFH2, val)
#define bfin_read_CAN1_OPSS2() bfin_read16(CAN1_OPSS2)
#define bfin_write_CAN1_OPSS2(val) bfin_write16(CAN1_OPSS2, val)
/* CAN Controller 1 Clock/Interrubfin_read_()t/Counter Registers */
#define bfin_read_CAN1_CLOCK() bfin_read16(CAN1_CLOCK)
#define bfin_write_CAN1_CLOCK(val) bfin_write16(CAN1_CLOCK, val)
#define bfin_read_CAN1_TIMING() bfin_read16(CAN1_TIMING)
#define bfin_write_CAN1_TIMING(val) bfin_write16(CAN1_TIMING, val)
#define bfin_read_CAN1_DEBUG() bfin_read16(CAN1_DEBUG)
#define bfin_write_CAN1_DEBUG(val) bfin_write16(CAN1_DEBUG, val)
#define bfin_read_CAN1_STATUS() bfin_read16(CAN1_STATUS)
#define bfin_write_CAN1_STATUS(val) bfin_write16(CAN1_STATUS, val)
#define bfin_read_CAN1_CEC() bfin_read16(CAN1_CEC)
#define bfin_write_CAN1_CEC(val) bfin_write16(CAN1_CEC, val)
#define bfin_read_CAN1_GIS() bfin_read16(CAN1_GIS)
#define bfin_write_CAN1_GIS(val) bfin_write16(CAN1_GIS, val)
#define bfin_read_CAN1_GIM() bfin_read16(CAN1_GIM)
#define bfin_write_CAN1_GIM(val) bfin_write16(CAN1_GIM, val)
#define bfin_read_CAN1_GIF() bfin_read16(CAN1_GIF)
#define bfin_write_CAN1_GIF(val) bfin_write16(CAN1_GIF, val)
#define bfin_read_CAN1_CONTROL() bfin_read16(CAN1_CONTROL)
#define bfin_write_CAN1_CONTROL(val) bfin_write16(CAN1_CONTROL, val)
#define bfin_read_CAN1_INTR() bfin_read16(CAN1_INTR)
#define bfin_write_CAN1_INTR(val) bfin_write16(CAN1_INTR, val)
#define bfin_read_CAN1_MBTD() bfin_read16(CAN1_MBTD)
#define bfin_write_CAN1_MBTD(val) bfin_write16(CAN1_MBTD, val)
#define bfin_read_CAN1_EWR() bfin_read16(CAN1_EWR)
#define bfin_write_CAN1_EWR(val) bfin_write16(CAN1_EWR, val)
#define bfin_read_CAN1_ESR() bfin_read16(CAN1_ESR)
#define bfin_write_CAN1_ESR(val) bfin_write16(CAN1_ESR, val)
#define bfin_read_CAN1_UCCNT() bfin_read16(CAN1_UCCNT)
#define bfin_write_CAN1_UCCNT(val) bfin_write16(CAN1_UCCNT, val)
#define bfin_read_CAN1_UCRC() bfin_read16(CAN1_UCRC)
#define bfin_write_CAN1_UCRC(val) bfin_write16(CAN1_UCRC, val)
#define bfin_read_CAN1_UCCNF() bfin_read16(CAN1_UCCNF)
#define bfin_write_CAN1_UCCNF(val) bfin_write16(CAN1_UCCNF, val)
/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
#define bfin_read_CAN1_AM00L() bfin_read16(CAN1_AM00L)
#define bfin_write_CAN1_AM00L(val) bfin_write16(CAN1_AM00L, val)
#define bfin_read_CAN1_AM00H() bfin_read16(CAN1_AM00H)
#define bfin_write_CAN1_AM00H(val) bfin_write16(CAN1_AM00H, val)
#define bfin_read_CAN1_AM01L() bfin_read16(CAN1_AM01L)
#define bfin_write_CAN1_AM01L(val) bfin_write16(CAN1_AM01L, val)
#define bfin_read_CAN1_AM01H() bfin_read16(CAN1_AM01H)
#define bfin_write_CAN1_AM01H(val) bfin_write16(CAN1_AM01H, val)
#define bfin_read_CAN1_AM02L() bfin_read16(CAN1_AM02L)
#define bfin_write_CAN1_AM02L(val) bfin_write16(CAN1_AM02L, val)
#define bfin_read_CAN1_AM02H() bfin_read16(CAN1_AM02H)
#define bfin_write_CAN1_AM02H(val) bfin_write16(CAN1_AM02H, val)
#define bfin_read_CAN1_AM03L() bfin_read16(CAN1_AM03L)
#define bfin_write_CAN1_AM03L(val) bfin_write16(CAN1_AM03L, val)
#define bfin_read_CAN1_AM03H() bfin_read16(CAN1_AM03H)
#define bfin_write_CAN1_AM03H(val) bfin_write16(CAN1_AM03H, val)
#define bfin_read_CAN1_AM04L() bfin_read16(CAN1_AM04L)
#define bfin_write_CAN1_AM04L(val) bfin_write16(CAN1_AM04L, val)
#define bfin_read_CAN1_AM04H() bfin_read16(CAN1_AM04H)
#define bfin_write_CAN1_AM04H(val) bfin_write16(CAN1_AM04H, val)
#define bfin_read_CAN1_AM05L() bfin_read16(CAN1_AM05L)
#define bfin_write_CAN1_AM05L(val) bfin_write16(CAN1_AM05L, val)
#define bfin_read_CAN1_AM05H() bfin_read16(CAN1_AM05H)
#define bfin_write_CAN1_AM05H(val) bfin_write16(CAN1_AM05H, val)
#define bfin_read_CAN1_AM06L() bfin_read16(CAN1_AM06L)
#define bfin_write_CAN1_AM06L(val) bfin_write16(CAN1_AM06L, val)
#define bfin_read_CAN1_AM06H() bfin_read16(CAN1_AM06H)
#define bfin_write_CAN1_AM06H(val) bfin_write16(CAN1_AM06H, val)
#define bfin_read_CAN1_AM07L() bfin_read16(CAN1_AM07L)
#define bfin_write_CAN1_AM07L(val) bfin_write16(CAN1_AM07L, val)
#define bfin_read_CAN1_AM07H() bfin_read16(CAN1_AM07H)
#define bfin_write_CAN1_AM07H(val) bfin_write16(CAN1_AM07H, val)
#define bfin_read_CAN1_AM08L() bfin_read16(CAN1_AM08L)
#define bfin_write_CAN1_AM08L(val) bfin_write16(CAN1_AM08L, val)
#define bfin_read_CAN1_AM08H() bfin_read16(CAN1_AM08H)
#define bfin_write_CAN1_AM08H(val) bfin_write16(CAN1_AM08H, val)
#define bfin_read_CAN1_AM09L() bfin_read16(CAN1_AM09L)
#define bfin_write_CAN1_AM09L(val) bfin_write16(CAN1_AM09L, val)
#define bfin_read_CAN1_AM09H() bfin_read16(CAN1_AM09H)
#define bfin_write_CAN1_AM09H(val) bfin_write16(CAN1_AM09H, val)
#define bfin_read_CAN1_AM10L() bfin_read16(CAN1_AM10L)
#define bfin_write_CAN1_AM10L(val) bfin_write16(CAN1_AM10L, val)
#define bfin_read_CAN1_AM10H() bfin_read16(CAN1_AM10H)
#define bfin_write_CAN1_AM10H(val) bfin_write16(CAN1_AM10H, val)
#define bfin_read_CAN1_AM11L() bfin_read16(CAN1_AM11L)
#define bfin_write_CAN1_AM11L(val) bfin_write16(CAN1_AM11L, val)
#define bfin_read_CAN1_AM11H() bfin_read16(CAN1_AM11H)
#define bfin_write_CAN1_AM11H(val) bfin_write16(CAN1_AM11H, val)
#define bfin_read_CAN1_AM12L() bfin_read16(CAN1_AM12L)
#define bfin_write_CAN1_AM12L(val) bfin_write16(CAN1_AM12L, val)
#define bfin_read_CAN1_AM12H() bfin_read16(CAN1_AM12H)
#define bfin_write_CAN1_AM12H(val) bfin_write16(CAN1_AM12H, val)
#define bfin_read_CAN1_AM13L() bfin_read16(CAN1_AM13L)
#define bfin_write_CAN1_AM13L(val) bfin_write16(CAN1_AM13L, val)
#define bfin_read_CAN1_AM13H() bfin_read16(CAN1_AM13H)
#define bfin_write_CAN1_AM13H(val) bfin_write16(CAN1_AM13H, val)
#define bfin_read_CAN1_AM14L() bfin_read16(CAN1_AM14L)
#define bfin_write_CAN1_AM14L(val) bfin_write16(CAN1_AM14L, val)
#define bfin_read_CAN1_AM14H() bfin_read16(CAN1_AM14H)
#define bfin_write_CAN1_AM14H(val) bfin_write16(CAN1_AM14H, val)
#define bfin_read_CAN1_AM15L() bfin_read16(CAN1_AM15L)
#define bfin_write_CAN1_AM15L(val) bfin_write16(CAN1_AM15L, val)
#define bfin_read_CAN1_AM15H() bfin_read16(CAN1_AM15H)
#define bfin_write_CAN1_AM15H(val) bfin_write16(CAN1_AM15H, val)
/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
#define bfin_read_CAN1_AM16L() bfin_read16(CAN1_AM16L)
#define bfin_write_CAN1_AM16L(val) bfin_write16(CAN1_AM16L, val)
#define bfin_read_CAN1_AM16H() bfin_read16(CAN1_AM16H)
#define bfin_write_CAN1_AM16H(val) bfin_write16(CAN1_AM16H, val)
#define bfin_read_CAN1_AM17L() bfin_read16(CAN1_AM17L)
#define bfin_write_CAN1_AM17L(val) bfin_write16(CAN1_AM17L, val)
#define bfin_read_CAN1_AM17H() bfin_read16(CAN1_AM17H)
#define bfin_write_CAN1_AM17H(val) bfin_write16(CAN1_AM17H, val)
#define bfin_read_CAN1_AM18L() bfin_read16(CAN1_AM18L)
#define bfin_write_CAN1_AM18L(val) bfin_write16(CAN1_AM18L, val)
#define bfin_read_CAN1_AM18H() bfin_read16(CAN1_AM18H)
#define bfin_write_CAN1_AM18H(val) bfin_write16(CAN1_AM18H, val)
#define bfin_read_CAN1_AM19L() bfin_read16(CAN1_AM19L)
#define bfin_write_CAN1_AM19L(val) bfin_write16(CAN1_AM19L, val)
#define bfin_read_CAN1_AM19H() bfin_read16(CAN1_AM19H)
#define bfin_write_CAN1_AM19H(val) bfin_write16(CAN1_AM19H, val)
#define bfin_read_CAN1_AM20L() bfin_read16(CAN1_AM20L)
#define bfin_write_CAN1_AM20L(val) bfin_write16(CAN1_AM20L, val)
#define bfin_read_CAN1_AM20H() bfin_read16(CAN1_AM20H)
#define bfin_write_CAN1_AM20H(val) bfin_write16(CAN1_AM20H, val)
#define bfin_read_CAN1_AM21L() bfin_read16(CAN1_AM21L)
#define bfin_write_CAN1_AM21L(val) bfin_write16(CAN1_AM21L, val)
#define bfin_read_CAN1_AM21H() bfin_read16(CAN1_AM21H)
#define bfin_write_CAN1_AM21H(val) bfin_write16(CAN1_AM21H, val)
#define bfin_read_CAN1_AM22L() bfin_read16(CAN1_AM22L)
#define bfin_write_CAN1_AM22L(val) bfin_write16(CAN1_AM22L, val)
#define bfin_read_CAN1_AM22H() bfin_read16(CAN1_AM22H)
#define bfin_write_CAN1_AM22H(val) bfin_write16(CAN1_AM22H, val)
#define bfin_read_CAN1_AM23L() bfin_read16(CAN1_AM23L)
#define bfin_write_CAN1_AM23L(val) bfin_write16(CAN1_AM23L, val)
#define bfin_read_CAN1_AM23H() bfin_read16(CAN1_AM23H)
#define bfin_write_CAN1_AM23H(val) bfin_write16(CAN1_AM23H, val)
#define bfin_read_CAN1_AM24L() bfin_read16(CAN1_AM24L)
#define bfin_write_CAN1_AM24L(val) bfin_write16(CAN1_AM24L, val)
#define bfin_read_CAN1_AM24H() bfin_read16(CAN1_AM24H)
#define bfin_write_CAN1_AM24H(val) bfin_write16(CAN1_AM24H, val)
#define bfin_read_CAN1_AM25L() bfin_read16(CAN1_AM25L)
#define bfin_write_CAN1_AM25L(val) bfin_write16(CAN1_AM25L, val)
#define bfin_read_CAN1_AM25H() bfin_read16(CAN1_AM25H)
#define bfin_write_CAN1_AM25H(val) bfin_write16(CAN1_AM25H, val)
#define bfin_read_CAN1_AM26L() bfin_read16(CAN1_AM26L)
#define bfin_write_CAN1_AM26L(val) bfin_write16(CAN1_AM26L, val)
#define bfin_read_CAN1_AM26H() bfin_read16(CAN1_AM26H)
#define bfin_write_CAN1_AM26H(val) bfin_write16(CAN1_AM26H, val)
#define bfin_read_CAN1_AM27L() bfin_read16(CAN1_AM27L)
#define bfin_write_CAN1_AM27L(val) bfin_write16(CAN1_AM27L, val)
#define bfin_read_CAN1_AM27H() bfin_read16(CAN1_AM27H)
#define bfin_write_CAN1_AM27H(val) bfin_write16(CAN1_AM27H, val)
#define bfin_read_CAN1_AM28L() bfin_read16(CAN1_AM28L)
#define bfin_write_CAN1_AM28L(val) bfin_write16(CAN1_AM28L, val)
#define bfin_read_CAN1_AM28H() bfin_read16(CAN1_AM28H)
#define bfin_write_CAN1_AM28H(val) bfin_write16(CAN1_AM28H, val)
#define bfin_read_CAN1_AM29L() bfin_read16(CAN1_AM29L)
#define bfin_write_CAN1_AM29L(val) bfin_write16(CAN1_AM29L, val)
#define bfin_read_CAN1_AM29H() bfin_read16(CAN1_AM29H)
#define bfin_write_CAN1_AM29H(val) bfin_write16(CAN1_AM29H, val)
#define bfin_read_CAN1_AM30L() bfin_read16(CAN1_AM30L)
#define bfin_write_CAN1_AM30L(val) bfin_write16(CAN1_AM30L, val)
#define bfin_read_CAN1_AM30H() bfin_read16(CAN1_AM30H)
#define bfin_write_CAN1_AM30H(val) bfin_write16(CAN1_AM30H, val)
#define bfin_read_CAN1_AM31L() bfin_read16(CAN1_AM31L)
#define bfin_write_CAN1_AM31L(val) bfin_write16(CAN1_AM31L, val)
#define bfin_read_CAN1_AM31H() bfin_read16(CAN1_AM31H)
#define bfin_write_CAN1_AM31H(val) bfin_write16(CAN1_AM31H, val)
/* CAN Controller 1 Mailbox Data Registers */
#define bfin_read_CAN1_MB00_DATA0() bfin_read16(CAN1_MB00_DATA0)
#define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val)
#define bfin_read_CAN1_MB00_DATA1() bfin_read16(CAN1_MB00_DATA1)
#define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val)
#define bfin_read_CAN1_MB00_DATA2() bfin_read16(CAN1_MB00_DATA2)
#define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val)
#define bfin_read_CAN1_MB00_DATA3() bfin_read16(CAN1_MB00_DATA3)
#define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val)
#define bfin_read_CAN1_MB00_LENGTH() bfin_read16(CAN1_MB00_LENGTH)
#define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val)
#define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP)
#define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val)
#define bfin_read_CAN1_MB00_ID0() bfin_read16(CAN1_MB00_ID0)
#define bfin_write_CAN1_MB00_ID0(val) bfin_write16(CAN1_MB00_ID0, val)
#define bfin_read_CAN1_MB00_ID1() bfin_read16(CAN1_MB00_ID1)
#define bfin_write_CAN1_MB00_ID1(val) bfin_write16(CAN1_MB00_ID1, val)
#define bfin_read_CAN1_MB01_DATA0() bfin_read16(CAN1_MB01_DATA0)
#define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val)
#define bfin_read_CAN1_MB01_DATA1() bfin_read16(CAN1_MB01_DATA1)
#define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val)
#define bfin_read_CAN1_MB01_DATA2() bfin_read16(CAN1_MB01_DATA2)
#define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val)
#define bfin_read_CAN1_MB01_DATA3() bfin_read16(CAN1_MB01_DATA3)
#define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val)
#define bfin_read_CAN1_MB01_LENGTH() bfin_read16(CAN1_MB01_LENGTH)
#define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val)
#define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP)
#define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val)
#define bfin_read_CAN1_MB01_ID0() bfin_read16(CAN1_MB01_ID0)
#define bfin_write_CAN1_MB01_ID0(val) bfin_write16(CAN1_MB01_ID0, val)
#define bfin_read_CAN1_MB01_ID1() bfin_read16(CAN1_MB01_ID1)
#define bfin_write_CAN1_MB01_ID1(val) bfin_write16(CAN1_MB01_ID1, val)
#define bfin_read_CAN1_MB02_DATA0() bfin_read16(CAN1_MB02_DATA0)
#define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val)
#define bfin_read_CAN1_MB02_DATA1() bfin_read16(CAN1_MB02_DATA1)
#define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val)
#define bfin_read_CAN1_MB02_DATA2() bfin_read16(CAN1_MB02_DATA2)
#define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val)
#define bfin_read_CAN1_MB02_DATA3() bfin_read16(CAN1_MB02_DATA3)
#define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val)
#define bfin_read_CAN1_MB02_LENGTH() bfin_read16(CAN1_MB02_LENGTH)
#define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val)
#define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP)
#define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val)
#define bfin_read_CAN1_MB02_ID0() bfin_read16(CAN1_MB02_ID0)
#define bfin_write_CAN1_MB02_ID0(val) bfin_write16(CAN1_MB02_ID0, val)
#define bfin_read_CAN1_MB02_ID1() bfin_read16(CAN1_MB02_ID1)
#define bfin_write_CAN1_MB02_ID1(val) bfin_write16(CAN1_MB02_ID1, val)
#define bfin_read_CAN1_MB03_DATA0() bfin_read16(CAN1_MB03_DATA0)
#define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val)
#define bfin_read_CAN1_MB03_DATA1() bfin_read16(CAN1_MB03_DATA1)
#define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val)
#define bfin_read_CAN1_MB03_DATA2() bfin_read16(CAN1_MB03_DATA2)
#define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val)
#define bfin_read_CAN1_MB03_DATA3() bfin_read16(CAN1_MB03_DATA3)
#define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val)
#define bfin_read_CAN1_MB03_LENGTH() bfin_read16(CAN1_MB03_LENGTH)
#define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val)
#define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP)
#define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val)
#define bfin_read_CAN1_MB03_ID0() bfin_read16(CAN1_MB03_ID0)
#define bfin_write_CAN1_MB03_ID0(val) bfin_write16(CAN1_MB03_ID0, val)
#define bfin_read_CAN1_MB03_ID1() bfin_read16(CAN1_MB03_ID1)
#define bfin_write_CAN1_MB03_ID1(val) bfin_write16(CAN1_MB03_ID1, val)
#define bfin_read_CAN1_MB04_DATA0() bfin_read16(CAN1_MB04_DATA0)
#define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val)
#define bfin_read_CAN1_MB04_DATA1() bfin_read16(CAN1_MB04_DATA1)
#define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val)
#define bfin_read_CAN1_MB04_DATA2() bfin_read16(CAN1_MB04_DATA2)
#define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val)
#define bfin_read_CAN1_MB04_DATA3() bfin_read16(CAN1_MB04_DATA3)
#define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val)
#define bfin_read_CAN1_MB04_LENGTH() bfin_read16(CAN1_MB04_LENGTH)
#define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val)
#define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP)
#define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val)
#define bfin_read_CAN1_MB04_ID0() bfin_read16(CAN1_MB04_ID0)
#define bfin_write_CAN1_MB04_ID0(val) bfin_write16(CAN1_MB04_ID0, val)
#define bfin_read_CAN1_MB04_ID1() bfin_read16(CAN1_MB04_ID1)
#define bfin_write_CAN1_MB04_ID1(val) bfin_write16(CAN1_MB04_ID1, val)
#define bfin_read_CAN1_MB05_DATA0() bfin_read16(CAN1_MB05_DATA0)
#define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val)
#define bfin_read_CAN1_MB05_DATA1() bfin_read16(CAN1_MB05_DATA1)
#define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val)
#define bfin_read_CAN1_MB05_DATA2() bfin_read16(CAN1_MB05_DATA2)
#define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val)
#define bfin_read_CAN1_MB05_DATA3() bfin_read16(CAN1_MB05_DATA3)
#define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val)
#define bfin_read_CAN1_MB05_LENGTH() bfin_read16(CAN1_MB05_LENGTH)
#define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val)
#define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP)
#define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val)
#define bfin_read_CAN1_MB05_ID0() bfin_read16(CAN1_MB05_ID0)
#define bfin_write_CAN1_MB05_ID0(val) bfin_write16(CAN1_MB05_ID0, val)
#define bfin_read_CAN1_MB05_ID1() bfin_read16(CAN1_MB05_ID1)
#define bfin_write_CAN1_MB05_ID1(val) bfin_write16(CAN1_MB05_ID1, val)
#define bfin_read_CAN1_MB06_DATA0() bfin_read16(CAN1_MB06_DATA0)
#define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val)
#define bfin_read_CAN1_MB06_DATA1() bfin_read16(CAN1_MB06_DATA1)
#define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val)
#define bfin_read_CAN1_MB06_DATA2() bfin_read16(CAN1_MB06_DATA2)
#define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val)
#define bfin_read_CAN1_MB06_DATA3() bfin_read16(CAN1_MB06_DATA3)
#define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val)
#define bfin_read_CAN1_MB06_LENGTH() bfin_read16(CAN1_MB06_LENGTH)
#define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val)
#define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP)
#define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val)
#define bfin_read_CAN1_MB06_ID0() bfin_read16(CAN1_MB06_ID0)
#define bfin_write_CAN1_MB06_ID0(val) bfin_write16(CAN1_MB06_ID0, val)
#define bfin_read_CAN1_MB06_ID1() bfin_read16(CAN1_MB06_ID1)
#define bfin_write_CAN1_MB06_ID1(val) bfin_write16(CAN1_MB06_ID1, val)
#define bfin_read_CAN1_MB07_DATA0() bfin_read16(CAN1_MB07_DATA0)
#define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val)
#define bfin_read_CAN1_MB07_DATA1() bfin_read16(CAN1_MB07_DATA1)
#define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val)
#define bfin_read_CAN1_MB07_DATA2() bfin_read16(CAN1_MB07_DATA2)
#define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val)
#define bfin_read_CAN1_MB07_DATA3() bfin_read16(CAN1_MB07_DATA3)
#define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val)
#define bfin_read_CAN1_MB07_LENGTH() bfin_read16(CAN1_MB07_LENGTH)
#define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val)
#define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP)
#define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val)
#define bfin_read_CAN1_MB07_ID0() bfin_read16(CAN1_MB07_ID0)
#define bfin_write_CAN1_MB07_ID0(val) bfin_write16(CAN1_MB07_ID0, val)
#define bfin_read_CAN1_MB07_ID1() bfin_read16(CAN1_MB07_ID1)
#define bfin_write_CAN1_MB07_ID1(val) bfin_write16(CAN1_MB07_ID1, val)
#define bfin_read_CAN1_MB08_DATA0() bfin_read16(CAN1_MB08_DATA0)
#define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val)
#define bfin_read_CAN1_MB08_DATA1() bfin_read16(CAN1_MB08_DATA1)
#define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val)
#define bfin_read_CAN1_MB08_DATA2() bfin_read16(CAN1_MB08_DATA2)
#define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val)
#define bfin_read_CAN1_MB08_DATA3() bfin_read16(CAN1_MB08_DATA3)
#define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val)
#define bfin_read_CAN1_MB08_LENGTH() bfin_read16(CAN1_MB08_LENGTH)
#define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val)
#define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP)
#define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val)
#define bfin_read_CAN1_MB08_ID0() bfin_read16(CAN1_MB08_ID0)
#define bfin_write_CAN1_MB08_ID0(val) bfin_write16(CAN1_MB08_ID0, val)
#define bfin_read_CAN1_MB08_ID1() bfin_read16(CAN1_MB08_ID1)
#define bfin_write_CAN1_MB08_ID1(val) bfin_write16(CAN1_MB08_ID1, val)
#define bfin_read_CAN1_MB09_DATA0() bfin_read16(CAN1_MB09_DATA0)
#define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val)
#define bfin_read_CAN1_MB09_DATA1() bfin_read16(CAN1_MB09_DATA1)
#define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val)
#define bfin_read_CAN1_MB09_DATA2() bfin_read16(CAN1_MB09_DATA2)
#define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val)
#define bfin_read_CAN1_MB09_DATA3() bfin_read16(CAN1_MB09_DATA3)
#define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val)
#define bfin_read_CAN1_MB09_LENGTH() bfin_read16(CAN1_MB09_LENGTH)
#define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val)
#define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP)
#define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val)
#define bfin_read_CAN1_MB09_ID0() bfin_read16(CAN1_MB09_ID0)
#define bfin_write_CAN1_MB09_ID0(val) bfin_write16(CAN1_MB09_ID0, val)
#define bfin_read_CAN1_MB09_ID1() bfin_read16(CAN1_MB09_ID1)
#define bfin_write_CAN1_MB09_ID1(val) bfin_write16(CAN1_MB09_ID1, val)
#define bfin_read_CAN1_MB10_DATA0() bfin_read16(CAN1_MB10_DATA0)
#define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val)
#define bfin_read_CAN1_MB10_DATA1() bfin_read16(CAN1_MB10_DATA1)
#define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val)
#define bfin_read_CAN1_MB10_DATA2() bfin_read16(CAN1_MB10_DATA2)
#define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val)
#define bfin_read_CAN1_MB10_DATA3() bfin_read16(CAN1_MB10_DATA3)
#define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val)
#define bfin_read_CAN1_MB10_LENGTH() bfin_read16(CAN1_MB10_LENGTH)
#define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val)
#define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP)
#define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val)
#define bfin_read_CAN1_MB10_ID0() bfin_read16(CAN1_MB10_ID0)
#define bfin_write_CAN1_MB10_ID0(val) bfin_write16(CAN1_MB10_ID0, val)
#define bfin_read_CAN1_MB10_ID1() bfin_read16(CAN1_MB10_ID1)
#define bfin_write_CAN1_MB10_ID1(val) bfin_write16(CAN1_MB10_ID1, val)
#define bfin_read_CAN1_MB11_DATA0() bfin_read16(CAN1_MB11_DATA0)
#define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val)
#define bfin_read_CAN1_MB11_DATA1() bfin_read16(CAN1_MB11_DATA1)
#define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val)
#define bfin_read_CAN1_MB11_DATA2() bfin_read16(CAN1_MB11_DATA2)
#define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val)
#define bfin_read_CAN1_MB11_DATA3() bfin_read16(CAN1_MB11_DATA3)
#define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val)
#define bfin_read_CAN1_MB11_LENGTH() bfin_read16(CAN1_MB11_LENGTH)
#define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val)
#define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP)
#define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val)
#define bfin_read_CAN1_MB11_ID0() bfin_read16(CAN1_MB11_ID0)
#define bfin_write_CAN1_MB11_ID0(val) bfin_write16(CAN1_MB11_ID0, val)
#define bfin_read_CAN1_MB11_ID1() bfin_read16(CAN1_MB11_ID1)
#define bfin_write_CAN1_MB11_ID1(val) bfin_write16(CAN1_MB11_ID1, val)
#define bfin_read_CAN1_MB12_DATA0() bfin_read16(CAN1_MB12_DATA0)
#define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val)
#define bfin_read_CAN1_MB12_DATA1() bfin_read16(CAN1_MB12_DATA1)
#define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val)
#define bfin_read_CAN1_MB12_DATA2() bfin_read16(CAN1_MB12_DATA2)
#define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val)
#define bfin_read_CAN1_MB12_DATA3() bfin_read16(CAN1_MB12_DATA3)
#define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val)
#define bfin_read_CAN1_MB12_LENGTH() bfin_read16(CAN1_MB12_LENGTH)
#define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val)
#define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP)
#define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val)
#define bfin_read_CAN1_MB12_ID0() bfin_read16(CAN1_MB12_ID0)
#define bfin_write_CAN1_MB12_ID0(val) bfin_write16(CAN1_MB12_ID0, val)
#define bfin_read_CAN1_MB12_ID1() bfin_read16(CAN1_MB12_ID1)
#define bfin_write_CAN1_MB12_ID1(val) bfin_write16(CAN1_MB12_ID1, val)
#define bfin_read_CAN1_MB13_DATA0() bfin_read16(CAN1_MB13_DATA0)
#define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val)
#define bfin_read_CAN1_MB13_DATA1() bfin_read16(CAN1_MB13_DATA1)
#define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val)
#define bfin_read_CAN1_MB13_DATA2() bfin_read16(CAN1_MB13_DATA2)
#define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val)
#define bfin_read_CAN1_MB13_DATA3() bfin_read16(CAN1_MB13_DATA3)
#define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val)
#define bfin_read_CAN1_MB13_LENGTH() bfin_read16(CAN1_MB13_LENGTH)
#define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val)
#define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP)
#define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val)
#define bfin_read_CAN1_MB13_ID0() bfin_read16(CAN1_MB13_ID0)
#define bfin_write_CAN1_MB13_ID0(val) bfin_write16(CAN1_MB13_ID0, val)
#define bfin_read_CAN1_MB13_ID1() bfin_read16(CAN1_MB13_ID1)
#define bfin_write_CAN1_MB13_ID1(val) bfin_write16(CAN1_MB13_ID1, val)
#define bfin_read_CAN1_MB14_DATA0() bfin_read16(CAN1_MB14_DATA0)
#define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val)
#define bfin_read_CAN1_MB14_DATA1() bfin_read16(CAN1_MB14_DATA1)
#define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val)
#define bfin_read_CAN1_MB14_DATA2() bfin_read16(CAN1_MB14_DATA2)
#define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val)
#define bfin_read_CAN1_MB14_DATA3() bfin_read16(CAN1_MB14_DATA3)
#define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val)
#define bfin_read_CAN1_MB14_LENGTH() bfin_read16(CAN1_MB14_LENGTH)
#define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val)
#define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP)
#define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val)
#define bfin_read_CAN1_MB14_ID0() bfin_read16(CAN1_MB14_ID0)
#define bfin_write_CAN1_MB14_ID0(val) bfin_write16(CAN1_MB14_ID0, val)
#define bfin_read_CAN1_MB14_ID1() bfin_read16(CAN1_MB14_ID1)
#define bfin_write_CAN1_MB14_ID1(val) bfin_write16(CAN1_MB14_ID1, val)
#define bfin_read_CAN1_MB15_DATA0() bfin_read16(CAN1_MB15_DATA0)
#define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val)
#define bfin_read_CAN1_MB15_DATA1() bfin_read16(CAN1_MB15_DATA1)
#define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val)
#define bfin_read_CAN1_MB15_DATA2() bfin_read16(CAN1_MB15_DATA2)
#define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val)
#define bfin_read_CAN1_MB15_DATA3() bfin_read16(CAN1_MB15_DATA3)
#define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val)
#define bfin_read_CAN1_MB15_LENGTH() bfin_read16(CAN1_MB15_LENGTH)
#define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val)
#define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP)
#define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val)
#define bfin_read_CAN1_MB15_ID0() bfin_read16(CAN1_MB15_ID0)
#define bfin_write_CAN1_MB15_ID0(val) bfin_write16(CAN1_MB15_ID0, val)
#define bfin_read_CAN1_MB15_ID1() bfin_read16(CAN1_MB15_ID1)
#define bfin_write_CAN1_MB15_ID1(val) bfin_write16(CAN1_MB15_ID1, val)
/* CAN Controller 1 Mailbox Data Registers */
#define bfin_read_CAN1_MB16_DATA0() bfin_read16(CAN1_MB16_DATA0)
#define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val)
#define bfin_read_CAN1_MB16_DATA1() bfin_read16(CAN1_MB16_DATA1)
#define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val)
#define bfin_read_CAN1_MB16_DATA2() bfin_read16(CAN1_MB16_DATA2)
#define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val)
#define bfin_read_CAN1_MB16_DATA3() bfin_read16(CAN1_MB16_DATA3)
#define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val)
#define bfin_read_CAN1_MB16_LENGTH() bfin_read16(CAN1_MB16_LENGTH)
#define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val)
#define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP)
#define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val)
#define bfin_read_CAN1_MB16_ID0() bfin_read16(CAN1_MB16_ID0)
#define bfin_write_CAN1_MB16_ID0(val) bfin_write16(CAN1_MB16_ID0, val)
#define bfin_read_CAN1_MB16_ID1() bfin_read16(CAN1_MB16_ID1)
#define bfin_write_CAN1_MB16_ID1(val) bfin_write16(CAN1_MB16_ID1, val)
#define bfin_read_CAN1_MB17_DATA0() bfin_read16(CAN1_MB17_DATA0)
#define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val)
#define bfin_read_CAN1_MB17_DATA1() bfin_read16(CAN1_MB17_DATA1)
#define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val)
#define bfin_read_CAN1_MB17_DATA2() bfin_read16(CAN1_MB17_DATA2)
#define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val)
#define bfin_read_CAN1_MB17_DATA3() bfin_read16(CAN1_MB17_DATA3)
#define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val)
#define bfin_read_CAN1_MB17_LENGTH() bfin_read16(CAN1_MB17_LENGTH)
#define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val)
#define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP)
#define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val)
#define bfin_read_CAN1_MB17_ID0() bfin_read16(CAN1_MB17_ID0)
#define bfin_write_CAN1_MB17_ID0(val) bfin_write16(CAN1_MB17_ID0, val)
#define bfin_read_CAN1_MB17_ID1() bfin_read16(CAN1_MB17_ID1)
#define bfin_write_CAN1_MB17_ID1(val) bfin_write16(CAN1_MB17_ID1, val)
#define bfin_read_CAN1_MB18_DATA0() bfin_read16(CAN1_MB18_DATA0)
#define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val)
#define bfin_read_CAN1_MB18_DATA1() bfin_read16(CAN1_MB18_DATA1)
#define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val)
#define bfin_read_CAN1_MB18_DATA2() bfin_read16(CAN1_MB18_DATA2)
#define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val)
#define bfin_read_CAN1_MB18_DATA3() bfin_read16(CAN1_MB18_DATA3)
#define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val)
#define bfin_read_CAN1_MB18_LENGTH() bfin_read16(CAN1_MB18_LENGTH)
#define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val)
#define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP)
#define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val)
#define bfin_read_CAN1_MB18_ID0() bfin_read16(CAN1_MB18_ID0)
#define bfin_write_CAN1_MB18_ID0(val) bfin_write16(CAN1_MB18_ID0, val)
#define bfin_read_CAN1_MB18_ID1() bfin_read16(CAN1_MB18_ID1)
#define bfin_write_CAN1_MB18_ID1(val) bfin_write16(CAN1_MB18_ID1, val)
#define bfin_read_CAN1_MB19_DATA0() bfin_read16(CAN1_MB19_DATA0)
#define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val)
#define bfin_read_CAN1_MB19_DATA1() bfin_read16(CAN1_MB19_DATA1)
#define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val)
#define bfin_read_CAN1_MB19_DATA2() bfin_read16(CAN1_MB19_DATA2)
#define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val)
#define bfin_read_CAN1_MB19_DATA3() bfin_read16(CAN1_MB19_DATA3)
#define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val)
#define bfin_read_CAN1_MB19_LENGTH() bfin_read16(CAN1_MB19_LENGTH)
#define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val)
#define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP)
#define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val)
#define bfin_read_CAN1_MB19_ID0() bfin_read16(CAN1_MB19_ID0)
#define bfin_write_CAN1_MB19_ID0(val) bfin_write16(CAN1_MB19_ID0, val)
#define bfin_read_CAN1_MB19_ID1() bfin_read16(CAN1_MB19_ID1)
#define bfin_write_CAN1_MB19_ID1(val) bfin_write16(CAN1_MB19_ID1, val)
#define bfin_read_CAN1_MB20_DATA0() bfin_read16(CAN1_MB20_DATA0)
#define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val)
#define bfin_read_CAN1_MB20_DATA1() bfin_read16(CAN1_MB20_DATA1)
#define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val)
#define bfin_read_CAN1_MB20_DATA2() bfin_read16(CAN1_MB20_DATA2)
#define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val)
#define bfin_read_CAN1_MB20_DATA3() bfin_read16(CAN1_MB20_DATA3)
#define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val)
#define bfin_read_CAN1_MB20_LENGTH() bfin_read16(CAN1_MB20_LENGTH)
#define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val)
#define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP)
#define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val)
#define bfin_read_CAN1_MB20_ID0() bfin_read16(CAN1_MB20_ID0)
#define bfin_write_CAN1_MB20_ID0(val) bfin_write16(CAN1_MB20_ID0, val)
#define bfin_read_CAN1_MB20_ID1() bfin_read16(CAN1_MB20_ID1)
#define bfin_write_CAN1_MB20_ID1(val) bfin_write16(CAN1_MB20_ID1, val)
#define bfin_read_CAN1_MB21_DATA0() bfin_read16(CAN1_MB21_DATA0)
#define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val)
#define bfin_read_CAN1_MB21_DATA1() bfin_read16(CAN1_MB21_DATA1)
#define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val)
#define bfin_read_CAN1_MB21_DATA2() bfin_read16(CAN1_MB21_DATA2)
#define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val)
#define bfin_read_CAN1_MB21_DATA3() bfin_read16(CAN1_MB21_DATA3)
#define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val)
#define bfin_read_CAN1_MB21_LENGTH() bfin_read16(CAN1_MB21_LENGTH)
#define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val)
#define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP)
#define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val)
#define bfin_read_CAN1_MB21_ID0() bfin_read16(CAN1_MB21_ID0)
#define bfin_write_CAN1_MB21_ID0(val) bfin_write16(CAN1_MB21_ID0, val)
#define bfin_read_CAN1_MB21_ID1() bfin_read16(CAN1_MB21_ID1)
#define bfin_write_CAN1_MB21_ID1(val) bfin_write16(CAN1_MB21_ID1, val)
#define bfin_read_CAN1_MB22_DATA0() bfin_read16(CAN1_MB22_DATA0)
#define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val)
#define bfin_read_CAN1_MB22_DATA1() bfin_read16(CAN1_MB22_DATA1)
#define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val)
#define bfin_read_CAN1_MB22_DATA2() bfin_read16(CAN1_MB22_DATA2)
#define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val)
#define bfin_read_CAN1_MB22_DATA3() bfin_read16(CAN1_MB22_DATA3)
#define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val)
#define bfin_read_CAN1_MB22_LENGTH() bfin_read16(CAN1_MB22_LENGTH)
#define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val)
#define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP)
#define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val)
#define bfin_read_CAN1_MB22_ID0() bfin_read16(CAN1_MB22_ID0)
#define bfin_write_CAN1_MB22_ID0(val) bfin_write16(CAN1_MB22_ID0, val)
#define bfin_read_CAN1_MB22_ID1() bfin_read16(CAN1_MB22_ID1)
#define bfin_write_CAN1_MB22_ID1(val) bfin_write16(CAN1_MB22_ID1, val)
#define bfin_read_CAN1_MB23_DATA0() bfin_read16(CAN1_MB23_DATA0)
#define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val)
#define bfin_read_CAN1_MB23_DATA1() bfin_read16(CAN1_MB23_DATA1)
#define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val)
#define bfin_read_CAN1_MB23_DATA2() bfin_read16(CAN1_MB23_DATA2)
#define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val)
#define bfin_read_CAN1_MB23_DATA3() bfin_read16(CAN1_MB23_DATA3)
#define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val)
#define bfin_read_CAN1_MB23_LENGTH() bfin_read16(CAN1_MB23_LENGTH)
#define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val)
#define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP)
#define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val)
#define bfin_read_CAN1_MB23_ID0() bfin_read16(CAN1_MB23_ID0)
#define bfin_write_CAN1_MB23_ID0(val) bfin_write16(CAN1_MB23_ID0, val)
#define bfin_read_CAN1_MB23_ID1() bfin_read16(CAN1_MB23_ID1)
#define bfin_write_CAN1_MB23_ID1(val) bfin_write16(CAN1_MB23_ID1, val)
#define bfin_read_CAN1_MB24_DATA0() bfin_read16(CAN1_MB24_DATA0)
#define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val)
#define bfin_read_CAN1_MB24_DATA1() bfin_read16(CAN1_MB24_DATA1)
#define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val)
#define bfin_read_CAN1_MB24_DATA2() bfin_read16(CAN1_MB24_DATA2)
#define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val)
#define bfin_read_CAN1_MB24_DATA3() bfin_read16(CAN1_MB24_DATA3)
#define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val)
#define bfin_read_CAN1_MB24_LENGTH() bfin_read16(CAN1_MB24_LENGTH)
#define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val)
#define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP)
#define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val)
#define bfin_read_CAN1_MB24_ID0() bfin_read16(CAN1_MB24_ID0)
#define bfin_write_CAN1_MB24_ID0(val) bfin_write16(CAN1_MB24_ID0, val)
#define bfin_read_CAN1_MB24_ID1() bfin_read16(CAN1_MB24_ID1)
#define bfin_write_CAN1_MB24_ID1(val) bfin_write16(CAN1_MB24_ID1, val)
#define bfin_read_CAN1_MB25_DATA0() bfin_read16(CAN1_MB25_DATA0)
#define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val)
#define bfin_read_CAN1_MB25_DATA1() bfin_read16(CAN1_MB25_DATA1)
#define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val)
#define bfin_read_CAN1_MB25_DATA2() bfin_read16(CAN1_MB25_DATA2)
#define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val)
#define bfin_read_CAN1_MB25_DATA3() bfin_read16(CAN1_MB25_DATA3)
#define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val)
#define bfin_read_CAN1_MB25_LENGTH() bfin_read16(CAN1_MB25_LENGTH)
#define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val)
#define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP)
#define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val)
#define bfin_read_CAN1_MB25_ID0() bfin_read16(CAN1_MB25_ID0)
#define bfin_write_CAN1_MB25_ID0(val) bfin_write16(CAN1_MB25_ID0, val)
#define bfin_read_CAN1_MB25_ID1() bfin_read16(CAN1_MB25_ID1)
#define bfin_write_CAN1_MB25_ID1(val) bfin_write16(CAN1_MB25_ID1, val)
#define bfin_read_CAN1_MB26_DATA0() bfin_read16(CAN1_MB26_DATA0)
#define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val)
#define bfin_read_CAN1_MB26_DATA1() bfin_read16(CAN1_MB26_DATA1)
#define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val)
#define bfin_read_CAN1_MB26_DATA2() bfin_read16(CAN1_MB26_DATA2)
#define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val)
#define bfin_read_CAN1_MB26_DATA3() bfin_read16(CAN1_MB26_DATA3)
#define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val)
#define bfin_read_CAN1_MB26_LENGTH() bfin_read16(CAN1_MB26_LENGTH)
#define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val)
#define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP)
#define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val)
#define bfin_read_CAN1_MB26_ID0() bfin_read16(CAN1_MB26_ID0)
#define bfin_write_CAN1_MB26_ID0(val) bfin_write16(CAN1_MB26_ID0, val)
#define bfin_read_CAN1_MB26_ID1() bfin_read16(CAN1_MB26_ID1)
#define bfin_write_CAN1_MB26_ID1(val) bfin_write16(CAN1_MB26_ID1, val)
#define bfin_read_CAN1_MB27_DATA0() bfin_read16(CAN1_MB27_DATA0)
#define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val)
#define bfin_read_CAN1_MB27_DATA1() bfin_read16(CAN1_MB27_DATA1)
#define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val)
#define bfin_read_CAN1_MB27_DATA2() bfin_read16(CAN1_MB27_DATA2)
#define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val)
#define bfin_read_CAN1_MB27_DATA3() bfin_read16(CAN1_MB27_DATA3)
#define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val)
#define bfin_read_CAN1_MB27_LENGTH() bfin_read16(CAN1_MB27_LENGTH)
#define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val)
#define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP)
#define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val)
#define bfin_read_CAN1_MB27_ID0() bfin_read16(CAN1_MB27_ID0)
#define bfin_write_CAN1_MB27_ID0(val) bfin_write16(CAN1_MB27_ID0, val)
#define bfin_read_CAN1_MB27_ID1() bfin_read16(CAN1_MB27_ID1)
#define bfin_write_CAN1_MB27_ID1(val) bfin_write16(CAN1_MB27_ID1, val)
#define bfin_read_CAN1_MB28_DATA0() bfin_read16(CAN1_MB28_DATA0)
#define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val)
#define bfin_read_CAN1_MB28_DATA1() bfin_read16(CAN1_MB28_DATA1)
#define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val)
#define bfin_read_CAN1_MB28_DATA2() bfin_read16(CAN1_MB28_DATA2)
#define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val)
#define bfin_read_CAN1_MB28_DATA3() bfin_read16(CAN1_MB28_DATA3)
#define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val)
#define bfin_read_CAN1_MB28_LENGTH() bfin_read16(CAN1_MB28_LENGTH)
#define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val)
#define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP)
#define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val)
#define bfin_read_CAN1_MB28_ID0() bfin_read16(CAN1_MB28_ID0)
#define bfin_write_CAN1_MB28_ID0(val) bfin_write16(CAN1_MB28_ID0, val)
#define bfin_read_CAN1_MB28_ID1() bfin_read16(CAN1_MB28_ID1)
#define bfin_write_CAN1_MB28_ID1(val) bfin_write16(CAN1_MB28_ID1, val)
#define bfin_read_CAN1_MB29_DATA0() bfin_read16(CAN1_MB29_DATA0)
#define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val)
#define bfin_read_CAN1_MB29_DATA1() bfin_read16(CAN1_MB29_DATA1)
#define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val)
#define bfin_read_CAN1_MB29_DATA2() bfin_read16(CAN1_MB29_DATA2)
#define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val)
#define bfin_read_CAN1_MB29_DATA3() bfin_read16(CAN1_MB29_DATA3)
#define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val)
#define bfin_read_CAN1_MB29_LENGTH() bfin_read16(CAN1_MB29_LENGTH)
#define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val)
#define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP)
#define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val)
#define bfin_read_CAN1_MB29_ID0() bfin_read16(CAN1_MB29_ID0)
#define bfin_write_CAN1_MB29_ID0(val) bfin_write16(CAN1_MB29_ID0, val)
#define bfin_read_CAN1_MB29_ID1() bfin_read16(CAN1_MB29_ID1)
#define bfin_write_CAN1_MB29_ID1(val) bfin_write16(CAN1_MB29_ID1, val)
#define bfin_read_CAN1_MB30_DATA0() bfin_read16(CAN1_MB30_DATA0)
#define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val)
#define bfin_read_CAN1_MB30_DATA1() bfin_read16(CAN1_MB30_DATA1)
#define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val)
#define bfin_read_CAN1_MB30_DATA2() bfin_read16(CAN1_MB30_DATA2)
#define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val)
#define bfin_read_CAN1_MB30_DATA3() bfin_read16(CAN1_MB30_DATA3)
#define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val)
#define bfin_read_CAN1_MB30_LENGTH() bfin_read16(CAN1_MB30_LENGTH)
#define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val)
#define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP)
#define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val)
#define bfin_read_CAN1_MB30_ID0() bfin_read16(CAN1_MB30_ID0)
#define bfin_write_CAN1_MB30_ID0(val) bfin_write16(CAN1_MB30_ID0, val)
#define bfin_read_CAN1_MB30_ID1() bfin_read16(CAN1_MB30_ID1)
#define bfin_write_CAN1_MB30_ID1(val) bfin_write16(CAN1_MB30_ID1, val)
#define bfin_read_CAN1_MB31_DATA0() bfin_read16(CAN1_MB31_DATA0)
#define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val)
#define bfin_read_CAN1_MB31_DATA1() bfin_read16(CAN1_MB31_DATA1)
#define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val)
#define bfin_read_CAN1_MB31_DATA2() bfin_read16(CAN1_MB31_DATA2)
#define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val)
#define bfin_read_CAN1_MB31_DATA3() bfin_read16(CAN1_MB31_DATA3)
#define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val)
#define bfin_read_CAN1_MB31_LENGTH() bfin_read16(CAN1_MB31_LENGTH)
#define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val)
#define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP)
#define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val)
#define bfin_read_CAN1_MB31_ID0() bfin_read16(CAN1_MB31_ID0)
#define bfin_write_CAN1_MB31_ID0(val) bfin_write16(CAN1_MB31_ID0, val)
#define bfin_read_CAN1_MB31_ID1() bfin_read16(CAN1_MB31_ID1)
#define bfin_write_CAN1_MB31_ID1(val) bfin_write16(CAN1_MB31_ID1, val)
/* ATAPI Registers */
#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL)
#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val)
#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS)
#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val)
#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR)
#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF)
#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF)
#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK)
#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS)
#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN)
#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS)
#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE)
#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE)
#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT)
#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT)
#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0)
#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0)
#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1)
#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0)
#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1)
#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2)
#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0)
#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1)
#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2)
#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3)
#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
/* SDH Registers */
#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL)
#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val)
#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL)
#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val)
#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT)
#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val)
#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND)
#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val)
#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD)
#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val)
#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0)
#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val)
#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1)
#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val)
#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2)
#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val)
#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3)
#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val)
#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER)
#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH)
#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val)
#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL)
#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val)
#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT)
#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val)
#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS)
#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val)
#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR)
#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0)
#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val)
#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1)
#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val)
#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT)
#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val)
#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO)
#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val)
#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS)
#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val)
#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK)
#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val)
#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG)
#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val)
#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN)
#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0)
#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val)
#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1)
#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val)
#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2)
#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val)
#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3)
#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val)
#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4)
#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val)
#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5)
#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val)
#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6)
#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val)
#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7)
#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val)
/* HOST Port Registers */
#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
/* USB Control Registers */
#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
/* USB Packet Control Registers */
#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
/* USB Endbfin_read_()oint FIFO Registers */
#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
/* USB OTG Control Registers */
#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
/* USB Phy Control Registers */
#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
/* (APHY_CNTRL is for ADI usage only) */
#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
/* (APHY_CALIB is for ADI usage only) */
#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
/* (PHY_TEST is for ADI usage only) */
#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST)
#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val)
#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
/* USB Endbfin_read_()oint 0 Control Registers */
#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
/* USB Endbfin_read_()oint 1 Control Registers */
#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
/* USB Endbfin_read_()oint 2 Control Registers */
#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
/* USB Endbfin_read_()oint 3 Control Registers */
#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
/* USB Endbfin_read_()oint 4 Control Registers */
#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
/* USB Endbfin_read_()oint 5 Control Registers */
#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
/* USB Endbfin_read_()oint 6 Control Registers */
#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
/* USB Endbfin_read_()oint 7 Control Registers */
#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
/* USB Channel 0 Config Registers */
#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL)
#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val)
#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW)
#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val)
#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH)
#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val)
#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW)
#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val)
#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH)
#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val)
/* USB Channel 1 Config Registers */
#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL)
#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val)
#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW)
#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val)
#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH)
#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val)
#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW)
#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val)
#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH)
#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val)
/* USB Channel 2 Config Registers */
#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL)
#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val)
#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW)
#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val)
#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH)
#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val)
#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW)
#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val)
#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH)
#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val)
/* USB Channel 3 Config Registers */
#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL)
#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val)
#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW)
#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val)
#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH)
#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val)
#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW)
#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val)
#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH)
#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val)
/* USB Channel 4 Config Registers */
#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL)
#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val)
#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW)
#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val)
#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH)
#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val)
#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW)
#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val)
#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH)
#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val)
/* USB Channel 5 Config Registers */
#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL)
#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val)
#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW)
#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val)
#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH)
#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW)
#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val)
#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH)
#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
/* USB Channel 6 Config Registers */
#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL)
#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val)
#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW)
#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val)
#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH)
#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val)
#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW)
#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val)
#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH)
#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val)
/* USB Channel 7 Config Registers */
#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL)
#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val)
#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW)
#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val)
#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH)
#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val)
#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW)
#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val)
#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH)
#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val)
/* Keybfin_read_()ad Registers */
#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL)
#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val)
#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE)
#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val)
#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL)
#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val)
#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL)
#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val)
#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT)
#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val)
#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL)
#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val)
/* Pixel Combfin_read_()ositor (PIXC) Registers */
#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL)
#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val)
#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL)
#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val)
#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF)
#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val)
#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART)
#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val)
#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND)
#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val)
#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART)
#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val)
#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND)
#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val)
#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP)
#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val)
#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART)
#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val)
#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND)
#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val)
#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART)
#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val)
#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND)
#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val)
#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP)
#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val)
#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT)
#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val)
#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON)
#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val)
#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON)
#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val)
#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON)
#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val)
#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS)
#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val)
#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC)
#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val)
/* Handshake MDMA 0 Registers */
#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
/* Handshake MDMA 1 Registers */
#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
#endif /* _CDEF_BF549_H */
arch/blackfin/mach-bf548/include/mach/defBF548.h
浏览文件 @ 60883e28
......@@ -15,115 +15,8 @@
/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
#include "defBF54x_base.h"
/* The following are the #defines needed by ADSP-BF548 that are not in the common header */
/* Timer Registers */
#define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */
#define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */
#define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */
#define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */
#define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */
#define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */
#define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */
#define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */
#define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */
#define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */
#define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */
#define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */
/* Timer Group of 3 Registers */
#define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */
#define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */
#define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */
/* SPORT0 Registers */
#define SPORT0_TCR1 0xffc00800 /* SPORT0 Transmit Configuration 1 Register */
#define SPORT0_TCR2 0xffc00804 /* SPORT0 Transmit Configuration 2 Register */
#define SPORT0_TCLKDIV 0xffc00808 /* SPORT0 Transmit Serial Clock Divider Register */
#define SPORT0_TFSDIV 0xffc0080c /* SPORT0 Transmit Frame Sync Divider Register */
#define SPORT0_TX 0xffc00810 /* SPORT0 Transmit Data Register */
#define SPORT0_RX 0xffc00818 /* SPORT0 Receive Data Register */
#define SPORT0_RCR1 0xffc00820 /* SPORT0 Receive Configuration 1 Register */
#define SPORT0_RCR2 0xffc00824 /* SPORT0 Receive Configuration 2 Register */
#define SPORT0_RCLKDIV 0xffc00828 /* SPORT0 Receive Serial Clock Divider Register */
#define SPORT0_RFSDIV 0xffc0082c /* SPORT0 Receive Frame Sync Divider Register */
#define SPORT0_STAT 0xffc00830 /* SPORT0 Status Register */
#define SPORT0_CHNL 0xffc00834 /* SPORT0 Current Channel Register */
#define SPORT0_MCMC1 0xffc00838 /* SPORT0 Multi channel Configuration Register 1 */
#define SPORT0_MCMC2 0xffc0083c /* SPORT0 Multi channel Configuration Register 2 */
#define SPORT0_MTCS0 0xffc00840 /* SPORT0 Multi channel Transmit Select Register 0 */
#define SPORT0_MTCS1 0xffc00844 /* SPORT0 Multi channel Transmit Select Register 1 */
#define SPORT0_MTCS2 0xffc00848 /* SPORT0 Multi channel Transmit Select Register 2 */
#define SPORT0_MTCS3 0xffc0084c /* SPORT0 Multi channel Transmit Select Register 3 */
#define SPORT0_MRCS0 0xffc00850 /* SPORT0 Multi channel Receive Select Register 0 */
#define SPORT0_MRCS1 0xffc00854 /* SPORT0 Multi channel Receive Select Register 1 */
#define SPORT0_MRCS2 0xffc00858 /* SPORT0 Multi channel Receive Select Register 2 */
#define SPORT0_MRCS3 0xffc0085c /* SPORT0 Multi channel Receive Select Register 3 */
/* EPPI0 Registers */
#define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */
#define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */
#define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */
#define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */
#define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */
#define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */
#define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */
#define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */
#define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */
#define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
#define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
#define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
#define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
#define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */
/* UART2 Registers */
#define UART2_DLL 0xffc02100 /* Divisor Latch Low Byte */
#define UART2_DLH 0xffc02104 /* Divisor Latch High Byte */
#define UART2_GCTL 0xffc02108 /* Global Control Register */
#define UART2_LCR 0xffc0210c /* Line Control Register */
#define UART2_MCR 0xffc02110 /* Modem Control Register */
#define UART2_LSR 0xffc02114 /* Line Status Register */
#define UART2_MSR 0xffc02118 /* Modem Status Register */
#define UART2_SCR 0xffc0211c /* Scratch Register */
#define UART2_IER_SET 0xffc02120 /* Interrupt Enable Register Set */
#define UART2_IER_CLEAR 0xffc02124 /* Interrupt Enable Register Clear */
#define UART2_RBR 0xffc0212c /* Receive Buffer Register */
/* Two Wire Interface Registers (TWI1) */
#define TWI1_REGBASE 0xffc02200
#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */
#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */
#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */
#define TWI1_MASTER_CTRL 0xffc02214 /* TWI Master Mode Control Register */
#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */
#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */
#define TWI1_FIFO_CTRL 0xffc02228 /* TWI FIFO Control Register */
#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */
#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */
#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */
#define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */
#define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */
/* SPI2 Registers */
#define SPI2_REGBASE 0xffc02400
#define SPI2_CTL 0xffc02400 /* SPI2 Control Register */
#define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */
#define SPI2_STAT 0xffc02408 /* SPI2 Status Register */
#define SPI2_TDBR 0xffc0240c /* SPI2 Transmit Data Buffer Register */
#define SPI2_RDBR 0xffc02410 /* SPI2 Receive Data Buffer Register */
#define SPI2_BAUD 0xffc02414 /* SPI2 Baud Rate Register */
#define SPI2_SHADOW 0xffc02418 /* SPI2 Receive Data Buffer Shadow Register */
/* The BF548 is like the BF547, but has additional CANs */
#include "defBF547.h"
/* CAN Controller 1 Config 1 Registers */
......@@ -508,1096 +401,4 @@
#define CAN1_MB31_ID0 0xffc037f8 /* CAN Controller 1 Mailbox 31 ID0 Register */
#define CAN1_MB31_ID1 0xffc037fc /* CAN Controller 1 Mailbox 31 ID1 Register */
/* ATAPI Registers */
#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */
#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */
#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */
#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */
#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */
#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */
#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */
#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */
#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */
#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */
#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */
#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */
#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */
#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */
#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */
#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */
#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */
#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */
#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */
#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */
#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */
#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */
#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */
#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */
#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */
/* SDH Registers */
#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */
#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */
#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */
#define SDH_COMMAND 0xffc0390c /* SDH Command */
#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */
#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */
#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */
#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */
#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */
#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */
#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */
#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */
#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */
#define SDH_STATUS 0xffc03934 /* SDH Status */
#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */
#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */
#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */
#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */
#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */
#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */
#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */
#define SDH_CFG 0xffc039c8 /* SDH Configuration */
#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */
#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */
#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */
#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */
#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */
#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */
#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */
#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */
#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */
/* HOST Port Registers */
#define HOST_CONTROL 0xffc03a00 /* HOST Control Register */
#define HOST_STATUS 0xffc03a04 /* HOST Status Register */
#define HOST_TIMEOUT 0xffc03a08 /* HOST Acknowledge Mode Timeout Register */
/* USB Control Registers */
#define USB_FADDR 0xffc03c00 /* Function address register */
#define USB_POWER 0xffc03c04 /* Power management register */
#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */
#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */
#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */
#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */
#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */
#define USB_FRAME 0xffc03c20 /* USB frame number */
#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */
#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */
#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */
/* USB Packet Control Registers */
#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */
#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */
#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */
#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
/* USB Endpoint FIFO Registers */
#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */
#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */
#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */
#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */
#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */
#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */
#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */
#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */
/* USB OTG Control Registers */
#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */
#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */
#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */
/* USB Phy Control Registers */
#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */
#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */
#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */
#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */
#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */
/* (APHY_CNTRL is for ADI usage only) */
#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */
/* (APHY_CALIB is for ADI usage only) */
#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */
#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
/* (PHY_TEST is for ADI usage only) */
#define USB_PHY_TEST 0xffc03dec /* Used for reducing simulation time and simplifies FIFO testability */
#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */
#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
/* USB Endpoint 0 Control Registers */
#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */
#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */
#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */
#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */
#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */
#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */
#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
/* USB Endpoint 1 Control Registers */
#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */
#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */
#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */
#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */
#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */
#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */
#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
/* USB Endpoint 2 Control Registers */
#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */
#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */
#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */
#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */
#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */
#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */
#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
/* USB Endpoint 3 Control Registers */
#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */
#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */
#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */
#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */
#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */
#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */
#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
/* USB Endpoint 4 Control Registers */
#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */
#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */
#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */
#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */
#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */
#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */
#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
/* USB Endpoint 5 Control Registers */
#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */
#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */
#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */
#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */
#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */
#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */
#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
/* USB Endpoint 6 Control Registers */
#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */
#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */
#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */
#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */
#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */
#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */
#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
/* USB Endpoint 7 Control Registers */
#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */
#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */
#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */
#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */
#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */
#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */
#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
#define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
#define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */
/* USB Channel 0 Config Registers */
#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */
#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
/* USB Channel 1 Config Registers */
#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */
#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
/* USB Channel 2 Config Registers */
#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */
#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
/* USB Channel 3 Config Registers */
#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */
#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
/* USB Channel 4 Config Registers */
#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */
#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
/* USB Channel 5 Config Registers */
#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */
#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
/* USB Channel 6 Config Registers */
#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */
#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
/* USB Channel 7 Config Registers */
#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */
#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
/* Keypad Registers */
#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */
#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */
#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */
#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */
#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */
#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */
/* Pixel Compositor (PIXC) Registers */
#define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
#define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */
#define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */
#define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */
#define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */
#define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */
#define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */
#define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */
#define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */
#define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */
#define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */
#define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */
#define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */
#define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */
#define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
#define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
#define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
#define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */
#define PIXC_TC 0xffc04450 /* Holds the transparent color value */
/* Handshake MDMA 0 Registers */
#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */
#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */
#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */
#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshold Register */
#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */
#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */
/* Handshake MDMA 1 Registers */
#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */
#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */
#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */
#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshold Register */
#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */
#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */
/* ********************************************************** */
/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
/* and MULTI BIT READ MACROS */
/* ********************************************************** */
/* Bit masks for PIXC_CTL */
#define PIXC_EN 0x1 /* Pixel Compositor Enable */
#define OVR_A_EN 0x2 /* Overlay A Enable */
#define OVR_B_EN 0x4 /* Overlay B Enable */
#define IMG_FORM 0x8 /* Image Data Format */
#define OVR_FORM 0x10 /* Overlay Data Format */
#define OUT_FORM 0x20 /* Output Data Format */
#define UDS_MOD 0x40 /* Resampling Mode */
#define TC_EN 0x80 /* Transparent Color Enable */
#define IMG_STAT 0x300 /* Image FIFO Status */
#define OVR_STAT 0xc00 /* Overlay FIFO Status */
#define WM_LVL 0x3000 /* FIFO Watermark Level */
/* Bit masks for PIXC_AHSTART */
#define A_HSTART 0xfff /* Horizontal Start Coordinates */
/* Bit masks for PIXC_AHEND */
#define A_HEND 0xfff /* Horizontal End Coordinates */
/* Bit masks for PIXC_AVSTART */
#define A_VSTART 0x3ff /* Vertical Start Coordinates */
/* Bit masks for PIXC_AVEND */
#define A_VEND 0x3ff /* Vertical End Coordinates */
/* Bit masks for PIXC_ATRANSP */
#define A_TRANSP 0xf /* Transparency Value */
/* Bit masks for PIXC_BHSTART */
#define B_HSTART 0xfff /* Horizontal Start Coordinates */
/* Bit masks for PIXC_BHEND */
#define B_HEND 0xfff /* Horizontal End Coordinates */
/* Bit masks for PIXC_BVSTART */
#define B_VSTART 0x3ff /* Vertical Start Coordinates */
/* Bit masks for PIXC_BVEND */
#define B_VEND 0x3ff /* Vertical End Coordinates */
/* Bit masks for PIXC_BTRANSP */
#define B_TRANSP 0xf /* Transparency Value */
/* Bit masks for PIXC_INTRSTAT */
#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */
#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */
#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */
#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */
/* Bit masks for PIXC_RYCON */
#define A11 0x3ff /* A11 in the Coefficient Matrix */
#define A12 0xffc00 /* A12 in the Coefficient Matrix */
#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */
#define RY_MULT4 0x40000000 /* Multiply Row by 4 */
/* Bit masks for PIXC_GUCON */
#define A21 0x3ff /* A21 in the Coefficient Matrix */
#define A22 0xffc00 /* A22 in the Coefficient Matrix */
#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */
#define GU_MULT4 0x40000000 /* Multiply Row by 4 */
/* Bit masks for PIXC_BVCON */
#define A31 0x3ff /* A31 in the Coefficient Matrix */
#define A32 0xffc00 /* A32 in the Coefficient Matrix */
#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */
#define BV_MULT4 0x40000000 /* Multiply Row by 4 */
/* Bit masks for PIXC_CCBIAS */
#define A14 0x3ff /* A14 in the Bias Vector */
#define A24 0xffc00 /* A24 in the Bias Vector */
#define A34 0x3ff00000 /* A34 in the Bias Vector */
/* Bit masks for PIXC_TC */
#define RY_TRANS 0xff /* Transparent Color - R/Y Component */
#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */
#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */
/* Bit masks for HOST_CONTROL */
#define HOST_EN 0x1 /* Host Enable */
#define HOST_END 0x2 /* Host Endianess */
#define DATA_SIZE 0x4 /* Data Size */
#define HOST_RST 0x8 /* Host Reset */
#define HRDY_OVR 0x20 /* Host Ready Override */
#define INT_MODE 0x40 /* Interrupt Mode */
#define BT_EN 0x80 /* Bus Timeout Enable */
#define EHW 0x100 /* Enable Host Write */
#define EHR 0x200 /* Enable Host Read */
#define BDR 0x400 /* Burst DMA Requests */
/* Bit masks for HOST_STATUS */
#define DMA_READY 0x1 /* DMA Ready */
#define FIFOFULL 0x2 /* FIFO Full */
#define FIFOEMPTY 0x4 /* FIFO Empty */
#define DMA_COMPLETE 0x8 /* DMA Complete */
#define HSHK 0x10 /* Host Handshake */
#define HSTIMEOUT 0x20 /* Host Timeout */
#define HIRQ 0x40 /* Host Interrupt Request */
#define ALLOW_CNFG 0x80 /* Allow New Configuration */
#define DMA_DIR 0x100 /* DMA Direction */
#define BTE 0x200 /* Bus Timeout Enabled */
/* Bit masks for HOST_TIMEOUT */
#define COUNT_TIMEOUT 0x7ff /* Host Timeout count */
/* Bit masks for KPAD_CTL */
#define KPAD_EN 0x1 /* Keypad Enable */
#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
#define KPAD_COLEN 0xe000 /* Column Enable Width */
/* Bit masks for KPAD_PRESCALE */
#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */
/* Bit masks for KPAD_MSEL */
#define DBON_SCALE 0xff /* Debounce Scale Value */
#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */
/* Bit masks for KPAD_ROWCOL */
#define KPAD_ROW 0xff /* Rows Pressed */
#define KPAD_COL 0xff00 /* Columns Pressed */
/* Bit masks for KPAD_STAT */
#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
#define KPAD_PRESSED 0x8 /* Key press current status */
/* Bit masks for KPAD_SOFTEVAL */
#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
/* Bit masks for SDH_COMMAND */
#define CMD_IDX 0x3f /* Command Index */
#define CMD_RSP 0x40 /* Response */
#define CMD_L_RSP 0x80 /* Long Response */
#define CMD_INT_E 0x100 /* Command Interrupt */
#define CMD_PEND_E 0x200 /* Command Pending */
#define CMD_E 0x400 /* Command Enable */
/* Bit masks for SDH_PWR_CTL */
#define PWR_ON 0x3 /* Power On */
#if 0
#define TBD 0x3c /* TBD */
#endif
#define SD_CMD_OD 0x40 /* Open Drain Output */
#define ROD_CTL 0x80 /* Rod Control */
/* Bit masks for SDH_CLK_CTL */
#define CLKDIV 0xff /* MC_CLK Divisor */
#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
#define PWR_SV_E 0x200 /* Power Save Enable */
#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
/* Bit masks for SDH_RESP_CMD */
#define RESP_CMD 0x3f /* Response Command */
/* Bit masks for SDH_DATA_CTL */
#define DTX_E 0x1 /* Data Transfer Enable */
#define DTX_DIR 0x2 /* Data Transfer Direction */
#define DTX_MODE 0x4 /* Data Transfer Mode */
#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
/* Bit masks for SDH_STATUS */
#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
#define CMD_TIME_OUT 0x4 /* CMD Time Out */
#define DAT_TIME_OUT 0x8 /* Data Time Out */
#define TX_UNDERRUN 0x10 /* Transmit Underrun */
#define RX_OVERRUN 0x20 /* Receive Overrun */
#define CMD_RESP_END 0x40 /* CMD Response End */
#define CMD_SENT 0x80 /* CMD Sent */
#define DAT_END 0x100 /* Data End */
#define START_BIT_ERR 0x200 /* Start Bit Error */
#define DAT_BLK_END 0x400 /* Data Block End */
#define CMD_ACT 0x800 /* CMD Active */
#define TX_ACT 0x1000 /* Transmit Active */
#define RX_ACT 0x2000 /* Receive Active */
#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
/* Bit masks for SDH_STATUS_CLR */
#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
#define DAT_END_STAT 0x100 /* Data End Status */
#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
/* Bit masks for SDH_MASK0 */
#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
#define DAT_END_MASK 0x100 /* Data End Mask */
#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
/* Bit masks for SDH_FIFO_CNT */
#define FIFO_COUNT 0x7fff /* FIFO Count */
/* Bit masks for SDH_E_STATUS */
#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
#define SD_CARD_DET 0x10 /* SD Card Detect */
/* Bit masks for SDH_E_MASK */
#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
#define SCD_MSK 0x40 /* Mask Card Detect */
/* Bit masks for SDH_CFG */
#define CLKS_EN 0x1 /* Clocks Enable */
#define SD4E 0x4 /* SDIO 4-Bit Enable */
#define MWE 0x8 /* Moving Window Enable */
#define SD_RST 0x10 /* SDMMC Reset */
#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
/* Bit masks for SDH_RD_WAIT_EN */
#define RWR 0x1 /* Read Wait Request */
/* Bit masks for ATAPI_CONTROL */
#define PIO_START 0x1 /* Start PIO/Reg Op */
#define MULTI_START 0x2 /* Start Multi-DMA Op */
#define ULTRA_START 0x4 /* Start Ultra-DMA Op */
#define XFER_DIR 0x8 /* Transfer Direction */
#define IORDY_EN 0x10 /* IORDY Enable */
#define FIFO_FLUSH 0x20 /* Flush FIFOs */
#define SOFT_RST 0x40 /* Soft Reset */
#define DEV_RST 0x80 /* Device Reset */
#define TFRCNT_RST 0x100 /* Trans Count Reset */
#define END_ON_TERM 0x200 /* End/Terminate Select */
#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
/* Bit masks for ATAPI_STATUS */
#define PIO_XFER_ON 0x1 /* PIO transfer in progress */
#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
/* Bit masks for ATAPI_DEV_ADDR */
#define DEV_ADDR 0x1f /* Device Address */
/* Bit masks for ATAPI_INT_MASK */
#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
/* Bit masks for ATAPI_INT_STATUS */
#define ATAPI_DEV_INT 0x1 /* Device interrupt status */
#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
/* Bit masks for ATAPI_LINE_STATUS */
#define ATAPI_INTR 0x1 /* Device interrupt to host line status */
#define ATAPI_DASP 0x2 /* Device dasp to host line status */
#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
#define ATAPI_ADDR 0x70 /* ATAPI address line status */
#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
#define ATAPI_DIOWN 0x200 /* ATAPI write line status */
#define ATAPI_DIORN 0x400 /* ATAPI read line status */
#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
/* Bit masks for ATAPI_SM_STATE */
#define PIO_CSTATE 0xf /* PIO mode state machine current state */
#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */
#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */
#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */
/* Bit masks for ATAPI_TERMINATE */
#define ATAPI_HOST_TERM 0x1 /* Host terminationation */
/* Bit masks for ATAPI_REG_TIM_0 */
#define T2_REG 0xff /* End of cycle time for register access transfers */
#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */
/* Bit masks for ATAPI_PIO_TIM_0 */
#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */
#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */
#define T4_REG 0xf000 /* DIOW data hold */
/* Bit masks for ATAPI_PIO_TIM_1 */
#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */
/* Bit masks for ATAPI_MULTI_TIM_0 */
#define TD 0xff /* DIOR/DIOW asserted pulsewidth */
#define TM 0xff00 /* Time from address valid to DIOR/DIOW */
/* Bit masks for ATAPI_MULTI_TIM_1 */
#define TKW 0xff /* Selects DIOW negated pulsewidth */
#define TKR 0xff00 /* Selects DIOR negated pulsewidth */
/* Bit masks for ATAPI_MULTI_TIM_2 */
#define TH 0xff /* Selects DIOW data hold */
#define TEOC 0xff00 /* Selects end of cycle for DMA */
/* Bit masks for ATAPI_ULTRA_TIM_0 */
#define TACK 0xff /* Selects setup and hold times for TACK */
#define TENV 0xff00 /* Selects envelope time */
/* Bit masks for ATAPI_ULTRA_TIM_1 */
#define TDVS 0xff /* Selects data valid setup time */
#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */
/* Bit masks for ATAPI_ULTRA_TIM_2 */
#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
#define TMLI 0xff00 /* Selects interlock time */
/* Bit masks for ATAPI_ULTRA_TIM_3 */
#define TZAH 0xff /* Selects minimum delay required for output */
#define READY_PAUSE 0xff00 /* Selects ready to pause */
/* Bit masks for TIMER_ENABLE1 */
#define TIMEN8 0x1 /* Timer 8 Enable */
#define TIMEN9 0x2 /* Timer 9 Enable */
#define TIMEN10 0x4 /* Timer 10 Enable */
/* Bit masks for TIMER_DISABLE1 */
#define TIMDIS8 0x1 /* Timer 8 Disable */
#define TIMDIS9 0x2 /* Timer 9 Disable */
#define TIMDIS10 0x4 /* Timer 10 Disable */
/* Bit masks for TIMER_STATUS1 */
#define TIMIL8 0x1 /* Timer 8 Interrupt */
#define TIMIL9 0x2 /* Timer 9 Interrupt */
#define TIMIL10 0x4 /* Timer 10 Interrupt */
#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */
#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */
#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */
#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */
#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */
#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */
/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
/* Bit masks for USB_FADDR */
#define FUNCTION_ADDRESS 0x7f /* Function address */
/* Bit masks for USB_POWER */
#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
#define RESUME_MODE 0x4 /* DMA Mode */
#define RESET 0x8 /* Reset indicator */
#define HS_MODE 0x10 /* High Speed mode indicator */
#define HS_ENABLE 0x20 /* high Speed Enable */
#define SOFT_CONN 0x40 /* Soft connect */
#define ISO_UPDATE 0x80 /* Isochronous update */
/* Bit masks for USB_INTRTX */
#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
/* Bit masks for USB_INTRRX */
#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
/* Bit masks for USB_INTRTXE */
#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
/* Bit masks for USB_INTRRXE */
#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
/* Bit masks for USB_INTRUSB */
#define SUSPEND_B 0x1 /* Suspend indicator */
#define RESUME_B 0x2 /* Resume indicator */
#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
#define SOF_B 0x8 /* Start of frame */
#define CONN_B 0x10 /* Connection indicator */
#define DISCON_B 0x20 /* Disconnect indicator */
#define SESSION_REQ_B 0x40 /* Session Request */
#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
/* Bit masks for USB_INTRUSBE */
#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
#define RESUME_BE 0x2 /* Resume indicator int enable */
#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
#define SOF_BE 0x8 /* Start of frame int enable */
#define CONN_BE 0x10 /* Connection indicator int enable */
#define DISCON_BE 0x20 /* Disconnect indicator int enable */
#define SESSION_REQ_BE 0x40 /* Session Request int enable */
#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
/* Bit masks for USB_FRAME */
#define FRAME_NUMBER 0x7ff /* Frame number */
/* Bit masks for USB_INDEX */
#define SELECTED_ENDPOINT 0xf /* selected endpoint */
/* Bit masks for USB_GLOBAL_CTL */
#define GLOBAL_ENA 0x1 /* enables USB module */
#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
/* Bit masks for USB_OTG_DEV_CTL */
#define SESSION 0x1 /* session indicator */
#define HOST_REQ 0x2 /* Host negotiation request */
#define HOST_MODE 0x4 /* indicates USBDRC is a host */
#define VBUS0 0x8 /* Vbus level indicator[0] */
#define VBUS1 0x10 /* Vbus level indicator[1] */
#define LSDEV 0x20 /* Low-speed indicator */
#define FSDEV 0x40 /* Full or High-speed indicator */
#define B_DEVICE 0x80 /* A' or 'B' device indicator */
/* Bit masks for USB_OTG_VBUS_IRQ */
#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
/* Bit masks for USB_OTG_VBUS_MASK */
#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
/* Bit masks for USB_CSR0 */
#define RXPKTRDY 0x1 /* data packet receive indicator */
#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
#define STALL_SENT 0x4 /* STALL handshake sent */
#define DATAEND 0x8 /* Data end indicator */
#define SETUPEND 0x10 /* Setup end */
#define SENDSTALL 0x20 /* Send STALL handshake */
#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
#define SETUPPKT_H 0x8 /* send Setup token host mode */
#define ERROR_H 0x10 /* timeout error indicator host mode */
#define REQPKT_H 0x20 /* Request an IN transaction host mode */
#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
/* Bit masks for USB_COUNT0 */
#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
/* Bit masks for USB_NAKLIMIT0 */
#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
/* Bit masks for USB_TX_MAX_PACKET */
#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
/* Bit masks for USB_RX_MAX_PACKET */
#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
/* Bit masks for USB_TXCSR */
#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
#define STALL_SEND_T 0x10 /* issue a Stall handshake */
#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
#define ISO_T 0x4000 /* enable Isochronous transfers */
#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
#define ERROR_TH 0x4 /* error condition host mode */
#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
/* Bit masks for USB_TXCOUNT */
#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
/* Bit masks for USB_RXCSR */
#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
#define FIFO_FULL_R 0x2 /* FIFO not empty */
#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
#define STALL_SEND_R 0x20 /* issue a Stall handshake */
#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
#define DISNYET_R 0x1000 /* disable Nyet handshakes */
#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
#define ISO_R 0x4000 /* enable Isochronous transfers */
#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
#define REQPKT_RH 0x20 /* request an IN transaction host mode */
#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
/* Bit masks for USB_RXCOUNT */
#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
/* Bit masks for USB_TXTYPE */
#define TARGET_EP_NO_T 0xf /* EP number */
#define PROTOCOL_T 0xc /* transfer type */
/* Bit masks for USB_TXINTERVAL */
#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
/* Bit masks for USB_RXTYPE */
#define TARGET_EP_NO_R 0xf /* EP number */
#define PROTOCOL_R 0xc /* transfer type */
/* Bit masks for USB_RXINTERVAL */
#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
/* Bit masks for USB_DMA_INTERRUPT */
#define DMA0_INT 0x1 /* DMA0 pending interrupt */
#define DMA1_INT 0x2 /* DMA1 pending interrupt */
#define DMA2_INT 0x4 /* DMA2 pending interrupt */
#define DMA3_INT 0x8 /* DMA3 pending interrupt */
#define DMA4_INT 0x10 /* DMA4 pending interrupt */
#define DMA5_INT 0x20 /* DMA5 pending interrupt */
#define DMA6_INT 0x40 /* DMA6 pending interrupt */
#define DMA7_INT 0x80 /* DMA7 pending interrupt */
/* Bit masks for USB_DMAxCONTROL */
#define DMA_ENA 0x1 /* DMA enable */
#define DIRECTION 0x2 /* direction of DMA transfer */
#define MODE 0x4 /* DMA Bus error */
#define INT_ENA 0x8 /* Interrupt enable */
#define EPNUM 0xf0 /* EP number */
#define BUSERROR 0x100 /* DMA Bus error */
/* Bit masks for USB_DMAxADDRHIGH */
#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
/* Bit masks for USB_DMAxADDRLOW */
#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
/* Bit masks for USB_DMAxCOUNTHIGH */
#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
/* Bit masks for USB_DMAxCOUNTLOW */
#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
/* Bit masks for HMDMAx_CONTROL */
#define HMDMAEN 0x1 /* Handshake MDMA Enable */
#define REP 0x2 /* Handshake MDMA Request Polarity */
#define UTE 0x8 /* Urgency Threshold Enable */
#define OIE 0x10 /* Overflow Interrupt Enable */
#define BDIE 0x20 /* Block Done Interrupt Enable */
#define MBDI 0x40 /* Mask Block Done Interrupt */
#define DRQ 0x300 /* Handshake MDMA Request Type */
#define RBC 0x1000 /* Force Reload of BCOUNT */
#define PS 0x2000 /* Pin Status */
#define OI 0x4000 /* Overflow Interrupt Generated */
#define BDI 0x8000 /* Block Done Interrupt Generated */
/* ******************************************* */
/* MULTI BIT MACRO ENUMERATIONS */
/* ******************************************* */
#endif /* _DEF_BF548_H */
arch/blackfin/mach-bf548/include/mach/defBF549.h
浏览文件 @ 60883e28
......@@ -10,121 +10,13 @@
/* Include all Core registers and bit definitions */
#include <asm/def_LPBlackfin.h>
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF549 */
/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
#include "defBF54x_base.h"
/* The following are the #defines needed by ADSP-BF549 that are not in the common header */
/* Timer Registers */
#define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */
#define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */
#define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */
#define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */
#define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */
#define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */
#define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */
#define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */
#define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */
#define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */
#define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */
#define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */
/* Timer Group of 3 Registers */
#define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */
#define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */
#define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */
/* SPORT0 Registers */
#define SPORT0_TCR1 0xffc00800 /* SPORT0 Transmit Configuration 1 Register */
#define SPORT0_TCR2 0xffc00804 /* SPORT0 Transmit Configuration 2 Register */
#define SPORT0_TCLKDIV 0xffc00808 /* SPORT0 Transmit Serial Clock Divider Register */
#define SPORT0_TFSDIV 0xffc0080c /* SPORT0 Transmit Frame Sync Divider Register */
#define SPORT0_TX 0xffc00810 /* SPORT0 Transmit Data Register */
#define SPORT0_RX 0xffc00818 /* SPORT0 Receive Data Register */
#define SPORT0_RCR1 0xffc00820 /* SPORT0 Receive Configuration 1 Register */
#define SPORT0_RCR2 0xffc00824 /* SPORT0 Receive Configuration 2 Register */
#define SPORT0_RCLKDIV 0xffc00828 /* SPORT0 Receive Serial Clock Divider Register */
#define SPORT0_RFSDIV 0xffc0082c /* SPORT0 Receive Frame Sync Divider Register */
#define SPORT0_STAT 0xffc00830 /* SPORT0 Status Register */
#define SPORT0_CHNL 0xffc00834 /* SPORT0 Current Channel Register */
#define SPORT0_MCMC1 0xffc00838 /* SPORT0 Multi channel Configuration Register 1 */
#define SPORT0_MCMC2 0xffc0083c /* SPORT0 Multi channel Configuration Register 2 */
#define SPORT0_MTCS0 0xffc00840 /* SPORT0 Multi channel Transmit Select Register 0 */
#define SPORT0_MTCS1 0xffc00844 /* SPORT0 Multi channel Transmit Select Register 1 */
#define SPORT0_MTCS2 0xffc00848 /* SPORT0 Multi channel Transmit Select Register 2 */
#define SPORT0_MTCS3 0xffc0084c /* SPORT0 Multi channel Transmit Select Register 3 */
#define SPORT0_MRCS0 0xffc00850 /* SPORT0 Multi channel Receive Select Register 0 */
#define SPORT0_MRCS1 0xffc00854 /* SPORT0 Multi channel Receive Select Register 1 */
#define SPORT0_MRCS2 0xffc00858 /* SPORT0 Multi channel Receive Select Register 2 */
#define SPORT0_MRCS3 0xffc0085c /* SPORT0 Multi channel Receive Select Register 3 */
/* EPPI0 Registers */
#define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */
#define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */
#define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */
#define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */
#define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */
#define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */
#define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */
#define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */
#define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */
#define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
#define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
#define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
#define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
#define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */
/* UART2 Registers */
#define UART2_DLL 0xffc02100 /* Divisor Latch Low Byte */
#define UART2_DLH 0xffc02104 /* Divisor Latch High Byte */
#define UART2_GCTL 0xffc02108 /* Global Control Register */
#define UART2_LCR 0xffc0210c /* Line Control Register */
#define UART2_MCR 0xffc02110 /* Modem Control Register */
#define UART2_LSR 0xffc02114 /* Line Status Register */
#define UART2_MSR 0xffc02118 /* Modem Status Register */
#define UART2_SCR 0xffc0211c /* Scratch Register */
#define UART2_IER_SET 0xffc02120 /* Interrupt Enable Register Set */
#define UART2_IER_CLEAR 0xffc02124 /* Interrupt Enable Register Clear */
#define UART2_RBR 0xffc0212c /* Receive Buffer Register */
/* Two Wire Interface Registers (TWI1) */
#define TWI1_REGBASE 0xffc02200
#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */
#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */
#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */
#define TWI1_MASTER_CTRL 0xffc02214 /* TWI Master Mode Control Register */
#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */
#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */
#define TWI1_FIFO_CTRL 0xffc02228 /* TWI FIFO Control Register */
#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */
#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */
#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */
#define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */
#define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */
/* SPI2 Registers */
#define SPI2_REGBASE 0xffc02400
#define SPI2_CTL 0xffc02400 /* SPI2 Control Register */
#define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */
#define SPI2_STAT 0xffc02408 /* SPI2 Status Register */
#define SPI2_TDBR 0xffc0240c /* SPI2 Transmit Data Buffer Register */
#define SPI2_RDBR 0xffc02410 /* SPI2 Receive Data Buffer Register */
#define SPI2_BAUD 0xffc02414 /* SPI2 Baud Rate Register */
#define SPI2_SHADOW 0xffc02418 /* SPI2 Receive Data Buffer Shadow Register */
/* The BF549 is like the BF544, but has MXVR */
#include "defBF547.h"
/* MXVR Registers */
......@@ -296,879 +188,6 @@
#define MXVR_PIN_CTL 0xffc028dc /* MXVR Pin Control Register */
#define MXVR_SCLK_CNT 0xffc028e0 /* MXVR System Clock Counter Register */
/* CAN Controller 1 Config 1 Registers */
#define CAN1_MC1 0xffc03200 /* CAN Controller 1 Mailbox Configuration Register 1 */
#define CAN1_MD1 0xffc03204 /* CAN Controller 1 Mailbox Direction Register 1 */
#define CAN1_TRS1 0xffc03208 /* CAN Controller 1 Transmit Request Set Register 1 */
#define CAN1_TRR1 0xffc0320c /* CAN Controller 1 Transmit Request Reset Register 1 */
#define CAN1_TA1 0xffc03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */
#define CAN1_AA1 0xffc03214 /* CAN Controller 1 Abort Acknowledge Register 1 */
#define CAN1_RMP1 0xffc03218 /* CAN Controller 1 Receive Message Pending Register 1 */
#define CAN1_RML1 0xffc0321c /* CAN Controller 1 Receive Message Lost Register 1 */
#define CAN1_MBTIF1 0xffc03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
#define CAN1_MBRIF1 0xffc03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
#define CAN1_MBIM1 0xffc03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
#define CAN1_RFH1 0xffc0322c /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
#define CAN1_OPSS1 0xffc03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
/* CAN Controller 1 Config 2 Registers */
#define CAN1_MC2 0xffc03240 /* CAN Controller 1 Mailbox Configuration Register 2 */
#define CAN1_MD2 0xffc03244 /* CAN Controller 1 Mailbox Direction Register 2 */
#define CAN1_TRS2 0xffc03248 /* CAN Controller 1 Transmit Request Set Register 2 */
#define CAN1_TRR2 0xffc0324c /* CAN Controller 1 Transmit Request Reset Register 2 */
#define CAN1_TA2 0xffc03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */
#define CAN1_AA2 0xffc03254 /* CAN Controller 1 Abort Acknowledge Register 2 */
#define CAN1_RMP2 0xffc03258 /* CAN Controller 1 Receive Message Pending Register 2 */
#define CAN1_RML2 0xffc0325c /* CAN Controller 1 Receive Message Lost Register 2 */
#define CAN1_MBTIF2 0xffc03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
#define CAN1_MBRIF2 0xffc03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
#define CAN1_MBIM2 0xffc03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
#define CAN1_RFH2 0xffc0326c /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
#define CAN1_OPSS2 0xffc03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
/* CAN Controller 1 Clock/Interrupt/Counter Registers */
#define CAN1_CLOCK 0xffc03280 /* CAN Controller 1 Clock Register */
#define CAN1_TIMING 0xffc03284 /* CAN Controller 1 Timing Register */
#define CAN1_DEBUG 0xffc03288 /* CAN Controller 1 Debug Register */
#define CAN1_STATUS 0xffc0328c /* CAN Controller 1 Global Status Register */
#define CAN1_CEC 0xffc03290 /* CAN Controller 1 Error Counter Register */
#define CAN1_GIS 0xffc03294 /* CAN Controller 1 Global Interrupt Status Register */
#define CAN1_GIM 0xffc03298 /* CAN Controller 1 Global Interrupt Mask Register */
#define CAN1_GIF 0xffc0329c /* CAN Controller 1 Global Interrupt Flag Register */
#define CAN1_CONTROL 0xffc032a0 /* CAN Controller 1 Master Control Register */
#define CAN1_INTR 0xffc032a4 /* CAN Controller 1 Interrupt Pending Register */
#define CAN1_MBTD 0xffc032ac /* CAN Controller 1 Mailbox Temporary Disable Register */
#define CAN1_EWR 0xffc032b0 /* CAN Controller 1 Programmable Warning Level Register */
#define CAN1_ESR 0xffc032b4 /* CAN Controller 1 Error Status Register */
#define CAN1_UCCNT 0xffc032c4 /* CAN Controller 1 Universal Counter Register */
#define CAN1_UCRC 0xffc032c8 /* CAN Controller 1 Universal Counter Force Reload Register */
#define CAN1_UCCNF 0xffc032cc /* CAN Controller 1 Universal Counter Configuration Register */
/* CAN Controller 1 Mailbox Acceptance Registers */
#define CAN1_AM00L 0xffc03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
#define CAN1_AM00H 0xffc03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
#define CAN1_AM01L 0xffc03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
#define CAN1_AM01H 0xffc0330c /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
#define CAN1_AM02L 0xffc03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
#define CAN1_AM02H 0xffc03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
#define CAN1_AM03L 0xffc03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
#define CAN1_AM03H 0xffc0331c /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
#define CAN1_AM04L 0xffc03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
#define CAN1_AM04H 0xffc03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
#define CAN1_AM05L 0xffc03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
#define CAN1_AM05H 0xffc0332c /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
#define CAN1_AM06L 0xffc03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
#define CAN1_AM06H 0xffc03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
#define CAN1_AM07L 0xffc03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
#define CAN1_AM07H 0xffc0333c /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
#define CAN1_AM08L 0xffc03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
#define CAN1_AM08H 0xffc03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
#define CAN1_AM09L 0xffc03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
#define CAN1_AM09H 0xffc0334c /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
#define CAN1_AM10L 0xffc03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
#define CAN1_AM10H 0xffc03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
#define CAN1_AM11L 0xffc03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
#define CAN1_AM11H 0xffc0335c /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
#define CAN1_AM12L 0xffc03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
#define CAN1_AM12H 0xffc03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
#define CAN1_AM13L 0xffc03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
#define CAN1_AM13H 0xffc0336c /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
#define CAN1_AM14L 0xffc03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
#define CAN1_AM14H 0xffc03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
#define CAN1_AM15L 0xffc03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
#define CAN1_AM15H 0xffc0337c /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
/* CAN Controller 1 Mailbox Acceptance Registers */
#define CAN1_AM16L 0xffc03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
#define CAN1_AM16H 0xffc03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
#define CAN1_AM17L 0xffc03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
#define CAN1_AM17H 0xffc0338c /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
#define CAN1_AM18L 0xffc03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
#define CAN1_AM18H 0xffc03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
#define CAN1_AM19L 0xffc03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
#define CAN1_AM19H 0xffc0339c /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
#define CAN1_AM20L 0xffc033a0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
#define CAN1_AM20H 0xffc033a4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
#define CAN1_AM21L 0xffc033a8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
#define CAN1_AM21H 0xffc033ac /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
#define CAN1_AM22L 0xffc033b0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
#define CAN1_AM22H 0xffc033b4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
#define CAN1_AM23L 0xffc033b8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
#define CAN1_AM23H 0xffc033bc /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
#define CAN1_AM24L 0xffc033c0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
#define CAN1_AM24H 0xffc033c4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
#define CAN1_AM25L 0xffc033c8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
#define CAN1_AM25H 0xffc033cc /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
#define CAN1_AM26L 0xffc033d0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
#define CAN1_AM26H 0xffc033d4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
#define CAN1_AM27L 0xffc033d8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
#define CAN1_AM27H 0xffc033dc /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
#define CAN1_AM28L 0xffc033e0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
#define CAN1_AM28H 0xffc033e4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
#define CAN1_AM29L 0xffc033e8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
#define CAN1_AM29H 0xffc033ec /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
#define CAN1_AM30L 0xffc033f0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
#define CAN1_AM30H 0xffc033f4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
#define CAN1_AM31L 0xffc033f8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
#define CAN1_AM31H 0xffc033fc /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
/* CAN Controller 1 Mailbox Data Registers */
#define CAN1_MB00_DATA0 0xffc03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */
#define CAN1_MB00_DATA1 0xffc03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */
#define CAN1_MB00_DATA2 0xffc03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */
#define CAN1_MB00_DATA3 0xffc0340c /* CAN Controller 1 Mailbox 0 Data 3 Register */
#define CAN1_MB00_LENGTH 0xffc03410 /* CAN Controller 1 Mailbox 0 Length Register */
#define CAN1_MB00_TIMESTAMP 0xffc03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */
#define CAN1_MB00_ID0 0xffc03418 /* CAN Controller 1 Mailbox 0 ID0 Register */
#define CAN1_MB00_ID1 0xffc0341c /* CAN Controller 1 Mailbox 0 ID1 Register */
#define CAN1_MB01_DATA0 0xffc03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */
#define CAN1_MB01_DATA1 0xffc03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */
#define CAN1_MB01_DATA2 0xffc03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */
#define CAN1_MB01_DATA3 0xffc0342c /* CAN Controller 1 Mailbox 1 Data 3 Register */
#define CAN1_MB01_LENGTH 0xffc03430 /* CAN Controller 1 Mailbox 1 Length Register */
#define CAN1_MB01_TIMESTAMP 0xffc03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */
#define CAN1_MB01_ID0 0xffc03438 /* CAN Controller 1 Mailbox 1 ID0 Register */
#define CAN1_MB01_ID1 0xffc0343c /* CAN Controller 1 Mailbox 1 ID1 Register */
#define CAN1_MB02_DATA0 0xffc03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */
#define CAN1_MB02_DATA1 0xffc03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */
#define CAN1_MB02_DATA2 0xffc03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */
#define CAN1_MB02_DATA3 0xffc0344c /* CAN Controller 1 Mailbox 2 Data 3 Register */
#define CAN1_MB02_LENGTH 0xffc03450 /* CAN Controller 1 Mailbox 2 Length Register */
#define CAN1_MB02_TIMESTAMP 0xffc03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */
#define CAN1_MB02_ID0 0xffc03458 /* CAN Controller 1 Mailbox 2 ID0 Register */
#define CAN1_MB02_ID1 0xffc0345c /* CAN Controller 1 Mailbox 2 ID1 Register */
#define CAN1_MB03_DATA0 0xffc03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */
#define CAN1_MB03_DATA1 0xffc03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */
#define CAN1_MB03_DATA2 0xffc03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */
#define CAN1_MB03_DATA3 0xffc0346c /* CAN Controller 1 Mailbox 3 Data 3 Register */
#define CAN1_MB03_LENGTH 0xffc03470 /* CAN Controller 1 Mailbox 3 Length Register */
#define CAN1_MB03_TIMESTAMP 0xffc03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */
#define CAN1_MB03_ID0 0xffc03478 /* CAN Controller 1 Mailbox 3 ID0 Register */
#define CAN1_MB03_ID1 0xffc0347c /* CAN Controller 1 Mailbox 3 ID1 Register */
#define CAN1_MB04_DATA0 0xffc03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */
#define CAN1_MB04_DATA1 0xffc03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */
#define CAN1_MB04_DATA2 0xffc03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */
#define CAN1_MB04_DATA3 0xffc0348c /* CAN Controller 1 Mailbox 4 Data 3 Register */
#define CAN1_MB04_LENGTH 0xffc03490 /* CAN Controller 1 Mailbox 4 Length Register */
#define CAN1_MB04_TIMESTAMP 0xffc03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */
#define CAN1_MB04_ID0 0xffc03498 /* CAN Controller 1 Mailbox 4 ID0 Register */
#define CAN1_MB04_ID1 0xffc0349c /* CAN Controller 1 Mailbox 4 ID1 Register */
#define CAN1_MB05_DATA0 0xffc034a0 /* CAN Controller 1 Mailbox 5 Data 0 Register */
#define CAN1_MB05_DATA1 0xffc034a4 /* CAN Controller 1 Mailbox 5 Data 1 Register */
#define CAN1_MB05_DATA2 0xffc034a8 /* CAN Controller 1 Mailbox 5 Data 2 Register */
#define CAN1_MB05_DATA3 0xffc034ac /* CAN Controller 1 Mailbox 5 Data 3 Register */
#define CAN1_MB05_LENGTH 0xffc034b0 /* CAN Controller 1 Mailbox 5 Length Register */
#define CAN1_MB05_TIMESTAMP 0xffc034b4 /* CAN Controller 1 Mailbox 5 Timestamp Register */
#define CAN1_MB05_ID0 0xffc034b8 /* CAN Controller 1 Mailbox 5 ID0 Register */
#define CAN1_MB05_ID1 0xffc034bc /* CAN Controller 1 Mailbox 5 ID1 Register */
#define CAN1_MB06_DATA0 0xffc034c0 /* CAN Controller 1 Mailbox 6 Data 0 Register */
#define CAN1_MB06_DATA1 0xffc034c4 /* CAN Controller 1 Mailbox 6 Data 1 Register */
#define CAN1_MB06_DATA2 0xffc034c8 /* CAN Controller 1 Mailbox 6 Data 2 Register */
#define CAN1_MB06_DATA3 0xffc034cc /* CAN Controller 1 Mailbox 6 Data 3 Register */
#define CAN1_MB06_LENGTH 0xffc034d0 /* CAN Controller 1 Mailbox 6 Length Register */
#define CAN1_MB06_TIMESTAMP 0xffc034d4 /* CAN Controller 1 Mailbox 6 Timestamp Register */
#define CAN1_MB06_ID0 0xffc034d8 /* CAN Controller 1 Mailbox 6 ID0 Register */
#define CAN1_MB06_ID1 0xffc034dc /* CAN Controller 1 Mailbox 6 ID1 Register */
#define CAN1_MB07_DATA0 0xffc034e0 /* CAN Controller 1 Mailbox 7 Data 0 Register */
#define CAN1_MB07_DATA1 0xffc034e4 /* CAN Controller 1 Mailbox 7 Data 1 Register */
#define CAN1_MB07_DATA2 0xffc034e8 /* CAN Controller 1 Mailbox 7 Data 2 Register */
#define CAN1_MB07_DATA3 0xffc034ec /* CAN Controller 1 Mailbox 7 Data 3 Register */
#define CAN1_MB07_LENGTH 0xffc034f0 /* CAN Controller 1 Mailbox 7 Length Register */
#define CAN1_MB07_TIMESTAMP 0xffc034f4 /* CAN Controller 1 Mailbox 7 Timestamp Register */
#define CAN1_MB07_ID0 0xffc034f8 /* CAN Controller 1 Mailbox 7 ID0 Register */
#define CAN1_MB07_ID1 0xffc034fc /* CAN Controller 1 Mailbox 7 ID1 Register */
#define CAN1_MB08_DATA0 0xffc03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */
#define CAN1_MB08_DATA1 0xffc03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */
#define CAN1_MB08_DATA2 0xffc03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */
#define CAN1_MB08_DATA3 0xffc0350c /* CAN Controller 1 Mailbox 8 Data 3 Register */
#define CAN1_MB08_LENGTH 0xffc03510 /* CAN Controller 1 Mailbox 8 Length Register */
#define CAN1_MB08_TIMESTAMP 0xffc03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */
#define CAN1_MB08_ID0 0xffc03518 /* CAN Controller 1 Mailbox 8 ID0 Register */
#define CAN1_MB08_ID1 0xffc0351c /* CAN Controller 1 Mailbox 8 ID1 Register */
#define CAN1_MB09_DATA0 0xffc03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */
#define CAN1_MB09_DATA1 0xffc03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */
#define CAN1_MB09_DATA2 0xffc03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */
#define CAN1_MB09_DATA3 0xffc0352c /* CAN Controller 1 Mailbox 9 Data 3 Register */
#define CAN1_MB09_LENGTH 0xffc03530 /* CAN Controller 1 Mailbox 9 Length Register */
#define CAN1_MB09_TIMESTAMP 0xffc03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */
#define CAN1_MB09_ID0 0xffc03538 /* CAN Controller 1 Mailbox 9 ID0 Register */
#define CAN1_MB09_ID1 0xffc0353c /* CAN Controller 1 Mailbox 9 ID1 Register */
#define CAN1_MB10_DATA0 0xffc03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */
#define CAN1_MB10_DATA1 0xffc03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */
#define CAN1_MB10_DATA2 0xffc03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */
#define CAN1_MB10_DATA3 0xffc0354c /* CAN Controller 1 Mailbox 10 Data 3 Register */
#define CAN1_MB10_LENGTH 0xffc03550 /* CAN Controller 1 Mailbox 10 Length Register */
#define CAN1_MB10_TIMESTAMP 0xffc03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */
#define CAN1_MB10_ID0 0xffc03558 /* CAN Controller 1 Mailbox 10 ID0 Register */
#define CAN1_MB10_ID1 0xffc0355c /* CAN Controller 1 Mailbox 10 ID1 Register */
#define CAN1_MB11_DATA0 0xffc03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */
#define CAN1_MB11_DATA1 0xffc03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */
#define CAN1_MB11_DATA2 0xffc03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */
#define CAN1_MB11_DATA3 0xffc0356c /* CAN Controller 1 Mailbox 11 Data 3 Register */
#define CAN1_MB11_LENGTH 0xffc03570 /* CAN Controller 1 Mailbox 11 Length Register */
#define CAN1_MB11_TIMESTAMP 0xffc03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */
#define CAN1_MB11_ID0 0xffc03578 /* CAN Controller 1 Mailbox 11 ID0 Register */
#define CAN1_MB11_ID1 0xffc0357c /* CAN Controller 1 Mailbox 11 ID1 Register */
#define CAN1_MB12_DATA0 0xffc03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */
#define CAN1_MB12_DATA1 0xffc03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */
#define CAN1_MB12_DATA2 0xffc03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */
#define CAN1_MB12_DATA3 0xffc0358c /* CAN Controller 1 Mailbox 12 Data 3 Register */
#define CAN1_MB12_LENGTH 0xffc03590 /* CAN Controller 1 Mailbox 12 Length Register */
#define CAN1_MB12_TIMESTAMP 0xffc03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */
#define CAN1_MB12_ID0 0xffc03598 /* CAN Controller 1 Mailbox 12 ID0 Register */
#define CAN1_MB12_ID1 0xffc0359c /* CAN Controller 1 Mailbox 12 ID1 Register */
#define CAN1_MB13_DATA0 0xffc035a0 /* CAN Controller 1 Mailbox 13 Data 0 Register */
#define CAN1_MB13_DATA1 0xffc035a4 /* CAN Controller 1 Mailbox 13 Data 1 Register */
#define CAN1_MB13_DATA2 0xffc035a8 /* CAN Controller 1 Mailbox 13 Data 2 Register */
#define CAN1_MB13_DATA3 0xffc035ac /* CAN Controller 1 Mailbox 13 Data 3 Register */
#define CAN1_MB13_LENGTH 0xffc035b0 /* CAN Controller 1 Mailbox 13 Length Register */
#define CAN1_MB13_TIMESTAMP 0xffc035b4 /* CAN Controller 1 Mailbox 13 Timestamp Register */
#define CAN1_MB13_ID0 0xffc035b8 /* CAN Controller 1 Mailbox 13 ID0 Register */
#define CAN1_MB13_ID1 0xffc035bc /* CAN Controller 1 Mailbox 13 ID1 Register */
#define CAN1_MB14_DATA0 0xffc035c0 /* CAN Controller 1 Mailbox 14 Data 0 Register */
#define CAN1_MB14_DATA1 0xffc035c4 /* CAN Controller 1 Mailbox 14 Data 1 Register */
#define CAN1_MB14_DATA2 0xffc035c8 /* CAN Controller 1 Mailbox 14 Data 2 Register */
#define CAN1_MB14_DATA3 0xffc035cc /* CAN Controller 1 Mailbox 14 Data 3 Register */
#define CAN1_MB14_LENGTH 0xffc035d0 /* CAN Controller 1 Mailbox 14 Length Register */
#define CAN1_MB14_TIMESTAMP 0xffc035d4 /* CAN Controller 1 Mailbox 14 Timestamp Register */
#define CAN1_MB14_ID0 0xffc035d8 /* CAN Controller 1 Mailbox 14 ID0 Register */
#define CAN1_MB14_ID1 0xffc035dc /* CAN Controller 1 Mailbox 14 ID1 Register */
#define CAN1_MB15_DATA0 0xffc035e0 /* CAN Controller 1 Mailbox 15 Data 0 Register */
#define CAN1_MB15_DATA1 0xffc035e4 /* CAN Controller 1 Mailbox 15 Data 1 Register */
#define CAN1_MB15_DATA2 0xffc035e8 /* CAN Controller 1 Mailbox 15 Data 2 Register */
#define CAN1_MB15_DATA3 0xffc035ec /* CAN Controller 1 Mailbox 15 Data 3 Register */
#define CAN1_MB15_LENGTH 0xffc035f0 /* CAN Controller 1 Mailbox 15 Length Register */
#define CAN1_MB15_TIMESTAMP 0xffc035f4 /* CAN Controller 1 Mailbox 15 Timestamp Register */
#define CAN1_MB15_ID0 0xffc035f8 /* CAN Controller 1 Mailbox 15 ID0 Register */
#define CAN1_MB15_ID1 0xffc035fc /* CAN Controller 1 Mailbox 15 ID1 Register */
/* CAN Controller 1 Mailbox Data Registers */
#define CAN1_MB16_DATA0 0xffc03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */
#define CAN1_MB16_DATA1 0xffc03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */
#define CAN1_MB16_DATA2 0xffc03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */
#define CAN1_MB16_DATA3 0xffc0360c /* CAN Controller 1 Mailbox 16 Data 3 Register */
#define CAN1_MB16_LENGTH 0xffc03610 /* CAN Controller 1 Mailbox 16 Length Register */
#define CAN1_MB16_TIMESTAMP 0xffc03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */
#define CAN1_MB16_ID0 0xffc03618 /* CAN Controller 1 Mailbox 16 ID0 Register */
#define CAN1_MB16_ID1 0xffc0361c /* CAN Controller 1 Mailbox 16 ID1 Register */
#define CAN1_MB17_DATA0 0xffc03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */
#define CAN1_MB17_DATA1 0xffc03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */
#define CAN1_MB17_DATA2 0xffc03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */
#define CAN1_MB17_DATA3 0xffc0362c /* CAN Controller 1 Mailbox 17 Data 3 Register */
#define CAN1_MB17_LENGTH 0xffc03630 /* CAN Controller 1 Mailbox 17 Length Register */
#define CAN1_MB17_TIMESTAMP 0xffc03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */
#define CAN1_MB17_ID0 0xffc03638 /* CAN Controller 1 Mailbox 17 ID0 Register */
#define CAN1_MB17_ID1 0xffc0363c /* CAN Controller 1 Mailbox 17 ID1 Register */
#define CAN1_MB18_DATA0 0xffc03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */
#define CAN1_MB18_DATA1 0xffc03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */
#define CAN1_MB18_DATA2 0xffc03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */
#define CAN1_MB18_DATA3 0xffc0364c /* CAN Controller 1 Mailbox 18 Data 3 Register */
#define CAN1_MB18_LENGTH 0xffc03650 /* CAN Controller 1 Mailbox 18 Length Register */
#define CAN1_MB18_TIMESTAMP 0xffc03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */
#define CAN1_MB18_ID0 0xffc03658 /* CAN Controller 1 Mailbox 18 ID0 Register */
#define CAN1_MB18_ID1 0xffc0365c /* CAN Controller 1 Mailbox 18 ID1 Register */
#define CAN1_MB19_DATA0 0xffc03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */
#define CAN1_MB19_DATA1 0xffc03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */
#define CAN1_MB19_DATA2 0xffc03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */
#define CAN1_MB19_DATA3 0xffc0366c /* CAN Controller 1 Mailbox 19 Data 3 Register */
#define CAN1_MB19_LENGTH 0xffc03670 /* CAN Controller 1 Mailbox 19 Length Register */
#define CAN1_MB19_TIMESTAMP 0xffc03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */
#define CAN1_MB19_ID0 0xffc03678 /* CAN Controller 1 Mailbox 19 ID0 Register */
#define CAN1_MB19_ID1 0xffc0367c /* CAN Controller 1 Mailbox 19 ID1 Register */
#define CAN1_MB20_DATA0 0xffc03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */
#define CAN1_MB20_DATA1 0xffc03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */
#define CAN1_MB20_DATA2 0xffc03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */
#define CAN1_MB20_DATA3 0xffc0368c /* CAN Controller 1 Mailbox 20 Data 3 Register */
#define CAN1_MB20_LENGTH 0xffc03690 /* CAN Controller 1 Mailbox 20 Length Register */
#define CAN1_MB20_TIMESTAMP 0xffc03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */
#define CAN1_MB20_ID0 0xffc03698 /* CAN Controller 1 Mailbox 20 ID0 Register */
#define CAN1_MB20_ID1 0xffc0369c /* CAN Controller 1 Mailbox 20 ID1 Register */
#define CAN1_MB21_DATA0 0xffc036a0 /* CAN Controller 1 Mailbox 21 Data 0 Register */
#define CAN1_MB21_DATA1 0xffc036a4 /* CAN Controller 1 Mailbox 21 Data 1 Register */
#define CAN1_MB21_DATA2 0xffc036a8 /* CAN Controller 1 Mailbox 21 Data 2 Register */
#define CAN1_MB21_DATA3 0xffc036ac /* CAN Controller 1 Mailbox 21 Data 3 Register */
#define CAN1_MB21_LENGTH 0xffc036b0 /* CAN Controller 1 Mailbox 21 Length Register */
#define CAN1_MB21_TIMESTAMP 0xffc036b4 /* CAN Controller 1 Mailbox 21 Timestamp Register */
#define CAN1_MB21_ID0 0xffc036b8 /* CAN Controller 1 Mailbox 21 ID0 Register */
#define CAN1_MB21_ID1 0xffc036bc /* CAN Controller 1 Mailbox 21 ID1 Register */
#define CAN1_MB22_DATA0 0xffc036c0 /* CAN Controller 1 Mailbox 22 Data 0 Register */
#define CAN1_MB22_DATA1 0xffc036c4 /* CAN Controller 1 Mailbox 22 Data 1 Register */
#define CAN1_MB22_DATA2 0xffc036c8 /* CAN Controller 1 Mailbox 22 Data 2 Register */
#define CAN1_MB22_DATA3 0xffc036cc /* CAN Controller 1 Mailbox 22 Data 3 Register */
#define CAN1_MB22_LENGTH 0xffc036d0 /* CAN Controller 1 Mailbox 22 Length Register */
#define CAN1_MB22_TIMESTAMP 0xffc036d4 /* CAN Controller 1 Mailbox 22 Timestamp Register */
#define CAN1_MB22_ID0 0xffc036d8 /* CAN Controller 1 Mailbox 22 ID0 Register */
#define CAN1_MB22_ID1 0xffc036dc /* CAN Controller 1 Mailbox 22 ID1 Register */
#define CAN1_MB23_DATA0 0xffc036e0 /* CAN Controller 1 Mailbox 23 Data 0 Register */
#define CAN1_MB23_DATA1 0xffc036e4 /* CAN Controller 1 Mailbox 23 Data 1 Register */
#define CAN1_MB23_DATA2 0xffc036e8 /* CAN Controller 1 Mailbox 23 Data 2 Register */
#define CAN1_MB23_DATA3 0xffc036ec /* CAN Controller 1 Mailbox 23 Data 3 Register */
#define CAN1_MB23_LENGTH 0xffc036f0 /* CAN Controller 1 Mailbox 23 Length Register */
#define CAN1_MB23_TIMESTAMP 0xffc036f4 /* CAN Controller 1 Mailbox 23 Timestamp Register */
#define CAN1_MB23_ID0 0xffc036f8 /* CAN Controller 1 Mailbox 23 ID0 Register */
#define CAN1_MB23_ID1 0xffc036fc /* CAN Controller 1 Mailbox 23 ID1 Register */
#define CAN1_MB24_DATA0 0xffc03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */
#define CAN1_MB24_DATA1 0xffc03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */
#define CAN1_MB24_DATA2 0xffc03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */
#define CAN1_MB24_DATA3 0xffc0370c /* CAN Controller 1 Mailbox 24 Data 3 Register */
#define CAN1_MB24_LENGTH 0xffc03710 /* CAN Controller 1 Mailbox 24 Length Register */
#define CAN1_MB24_TIMESTAMP 0xffc03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */
#define CAN1_MB24_ID0 0xffc03718 /* CAN Controller 1 Mailbox 24 ID0 Register */
#define CAN1_MB24_ID1 0xffc0371c /* CAN Controller 1 Mailbox 24 ID1 Register */
#define CAN1_MB25_DATA0 0xffc03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */
#define CAN1_MB25_DATA1 0xffc03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */
#define CAN1_MB25_DATA2 0xffc03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */
#define CAN1_MB25_DATA3 0xffc0372c /* CAN Controller 1 Mailbox 25 Data 3 Register */
#define CAN1_MB25_LENGTH 0xffc03730 /* CAN Controller 1 Mailbox 25 Length Register */
#define CAN1_MB25_TIMESTAMP 0xffc03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */
#define CAN1_MB25_ID0 0xffc03738 /* CAN Controller 1 Mailbox 25 ID0 Register */
#define CAN1_MB25_ID1 0xffc0373c /* CAN Controller 1 Mailbox 25 ID1 Register */
#define CAN1_MB26_DATA0 0xffc03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */
#define CAN1_MB26_DATA1 0xffc03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */
#define CAN1_MB26_DATA2 0xffc03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */
#define CAN1_MB26_DATA3 0xffc0374c /* CAN Controller 1 Mailbox 26 Data 3 Register */
#define CAN1_MB26_LENGTH 0xffc03750 /* CAN Controller 1 Mailbox 26 Length Register */
#define CAN1_MB26_TIMESTAMP 0xffc03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */
#define CAN1_MB26_ID0 0xffc03758 /* CAN Controller 1 Mailbox 26 ID0 Register */
#define CAN1_MB26_ID1 0xffc0375c /* CAN Controller 1 Mailbox 26 ID1 Register */
#define CAN1_MB27_DATA0 0xffc03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */
#define CAN1_MB27_DATA1 0xffc03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */
#define CAN1_MB27_DATA2 0xffc03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */
#define CAN1_MB27_DATA3 0xffc0376c /* CAN Controller 1 Mailbox 27 Data 3 Register */
#define CAN1_MB27_LENGTH 0xffc03770 /* CAN Controller 1 Mailbox 27 Length Register */
#define CAN1_MB27_TIMESTAMP 0xffc03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */
#define CAN1_MB27_ID0 0xffc03778 /* CAN Controller 1 Mailbox 27 ID0 Register */
#define CAN1_MB27_ID1 0xffc0377c /* CAN Controller 1 Mailbox 27 ID1 Register */
#define CAN1_MB28_DATA0 0xffc03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */
#define CAN1_MB28_DATA1 0xffc03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */
#define CAN1_MB28_DATA2 0xffc03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */
#define CAN1_MB28_DATA3 0xffc0378c /* CAN Controller 1 Mailbox 28 Data 3 Register */
#define CAN1_MB28_LENGTH 0xffc03790 /* CAN Controller 1 Mailbox 28 Length Register */
#define CAN1_MB28_TIMESTAMP 0xffc03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */
#define CAN1_MB28_ID0 0xffc03798 /* CAN Controller 1 Mailbox 28 ID0 Register */
#define CAN1_MB28_ID1 0xffc0379c /* CAN Controller 1 Mailbox 28 ID1 Register */
#define CAN1_MB29_DATA0 0xffc037a0 /* CAN Controller 1 Mailbox 29 Data 0 Register */
#define CAN1_MB29_DATA1 0xffc037a4 /* CAN Controller 1 Mailbox 29 Data 1 Register */
#define CAN1_MB29_DATA2 0xffc037a8 /* CAN Controller 1 Mailbox 29 Data 2 Register */
#define CAN1_MB29_DATA3 0xffc037ac /* CAN Controller 1 Mailbox 29 Data 3 Register */
#define CAN1_MB29_LENGTH 0xffc037b0 /* CAN Controller 1 Mailbox 29 Length Register */
#define CAN1_MB29_TIMESTAMP 0xffc037b4 /* CAN Controller 1 Mailbox 29 Timestamp Register */
#define CAN1_MB29_ID0 0xffc037b8 /* CAN Controller 1 Mailbox 29 ID0 Register */
#define CAN1_MB29_ID1 0xffc037bc /* CAN Controller 1 Mailbox 29 ID1 Register */
#define CAN1_MB30_DATA0 0xffc037c0 /* CAN Controller 1 Mailbox 30 Data 0 Register */
#define CAN1_MB30_DATA1 0xffc037c4 /* CAN Controller 1 Mailbox 30 Data 1 Register */
#define CAN1_MB30_DATA2 0xffc037c8 /* CAN Controller 1 Mailbox 30 Data 2 Register */
#define CAN1_MB30_DATA3 0xffc037cc /* CAN Controller 1 Mailbox 30 Data 3 Register */
#define CAN1_MB30_LENGTH 0xffc037d0 /* CAN Controller 1 Mailbox 30 Length Register */
#define CAN1_MB30_TIMESTAMP 0xffc037d4 /* CAN Controller 1 Mailbox 30 Timestamp Register */
#define CAN1_MB30_ID0 0xffc037d8 /* CAN Controller 1 Mailbox 30 ID0 Register */
#define CAN1_MB30_ID1 0xffc037dc /* CAN Controller 1 Mailbox 30 ID1 Register */
#define CAN1_MB31_DATA0 0xffc037e0 /* CAN Controller 1 Mailbox 31 Data 0 Register */
#define CAN1_MB31_DATA1 0xffc037e4 /* CAN Controller 1 Mailbox 31 Data 1 Register */
#define CAN1_MB31_DATA2 0xffc037e8 /* CAN Controller 1 Mailbox 31 Data 2 Register */
#define CAN1_MB31_DATA3 0xffc037ec /* CAN Controller 1 Mailbox 31 Data 3 Register */
#define CAN1_MB31_LENGTH 0xffc037f0 /* CAN Controller 1 Mailbox 31 Length Register */
#define CAN1_MB31_TIMESTAMP 0xffc037f4 /* CAN Controller 1 Mailbox 31 Timestamp Register */
#define CAN1_MB31_ID0 0xffc037f8 /* CAN Controller 1 Mailbox 31 ID0 Register */
#define CAN1_MB31_ID1 0xffc037fc /* CAN Controller 1 Mailbox 31 ID1 Register */
/* ATAPI Registers */
#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */
#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */
#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */
#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */
#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */
#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */
#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */
#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */
#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */
#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */
#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */
#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */
#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */
#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */
#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */
#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */
#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */
#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */
#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */
#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */
#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */
#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */
#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */
#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */
#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */
/* SDH Registers */
#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */
#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */
#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */
#define SDH_COMMAND 0xffc0390c /* SDH Command */
#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */
#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */
#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */
#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */
#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */
#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */
#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */
#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */
#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */
#define SDH_STATUS 0xffc03934 /* SDH Status */
#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */
#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */
#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */
#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */
#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */
#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */
#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */
#define SDH_CFG 0xffc039c8 /* SDH Configuration */
#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */
#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */
#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */
#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */
#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */
#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */
#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */
#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */
#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */
/* HOST Port Registers */
#define HOST_CONTROL 0xffc03a00 /* HOST Control Register */
#define HOST_STATUS 0xffc03a04 /* HOST Status Register */
#define HOST_TIMEOUT 0xffc03a08 /* HOST Acknowledge Mode Timeout Register */
/* USB Control Registers */
#define USB_FADDR 0xffc03c00 /* Function address register */
#define USB_POWER 0xffc03c04 /* Power management register */
#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */
#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */
#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */
#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */
#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */
#define USB_FRAME 0xffc03c20 /* USB frame number */
#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */
#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */
#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */
/* USB Packet Control Registers */
#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */
#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */
#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */
#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
/* USB Endpoint FIFO Registers */
#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */
#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */
#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */
#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */
#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */
#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */
#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */
#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */
/* USB OTG Control Registers */
#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */
#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */
#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */
/* USB Phy Control Registers */
#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */
#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */
#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */
#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */
#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */
/* (APHY_CNTRL is for ADI usage only) */
#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */
/* (APHY_CALIB is for ADI usage only) */
#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */
#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
/* (PHY_TEST is for ADI usage only) */
#define USB_PHY_TEST 0xffc03dec /* Used for reducing simulation time and simplifies FIFO testability */
#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */
#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
/* USB Endpoint 0 Control Registers */
#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */
#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */
#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */
#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */
#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */
#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */
#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
/* USB Endpoint 1 Control Registers */
#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */
#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */
#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */
#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */
#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */
#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */
#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
/* USB Endpoint 2 Control Registers */
#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */
#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */
#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */
#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */
#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */
#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */
#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
/* USB Endpoint 3 Control Registers */
#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */
#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */
#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */
#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */
#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */
#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */
#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
/* USB Endpoint 4 Control Registers */
#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */
#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */
#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */
#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */
#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */
#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */
#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
/* USB Endpoint 5 Control Registers */
#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */
#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */
#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */
#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */
#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */
#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */
#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
/* USB Endpoint 6 Control Registers */
#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */
#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */
#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */
#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */
#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */
#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */
#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
/* USB Endpoint 7 Control Registers */
#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */
#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */
#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */
#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */
#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */
#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */
#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
#define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
#define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */
/* USB Channel 0 Config Registers */
#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */
#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
/* USB Channel 1 Config Registers */
#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */
#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
/* USB Channel 2 Config Registers */
#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */
#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
/* USB Channel 3 Config Registers */
#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */
#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
/* USB Channel 4 Config Registers */
#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */
#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
/* USB Channel 5 Config Registers */
#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */
#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
/* USB Channel 6 Config Registers */
#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */
#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
/* USB Channel 7 Config Registers */
#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */
#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
/* Keypad Registers */
#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */
#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */
#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */
#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */
#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */
#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */
/* Pixel Compositor (PIXC) Registers */
#define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
#define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */
#define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */
#define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */
#define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */
#define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */
#define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */
#define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */
#define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */
#define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */
#define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */
#define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */
#define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */
#define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */
#define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
#define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
#define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
#define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */
#define PIXC_TC 0xffc04450 /* Holds the transparent color value */
/* Handshake MDMA 0 Registers */
#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */
#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */
#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */
#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshold Register */
#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */
#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */
/* Handshake MDMA 1 Registers */
#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */
#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */
#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */
#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshold Register */
#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */
#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */
/* ********************************************************** */
/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
/* and MULTI BIT READ MACROS */
/* ********************************************************** */
/* Bit masks for PIXC_CTL */
#define PIXC_EN 0x1 /* Pixel Compositor Enable */
#define OVR_A_EN 0x2 /* Overlay A Enable */
#define OVR_B_EN 0x4 /* Overlay B Enable */
#define IMG_FORM 0x8 /* Image Data Format */
#define OVR_FORM 0x10 /* Overlay Data Format */
#define OUT_FORM 0x20 /* Output Data Format */
#define UDS_MOD 0x40 /* Resampling Mode */
#define TC_EN 0x80 /* Transparent Color Enable */
#define IMG_STAT 0x300 /* Image FIFO Status */
#define OVR_STAT 0xc00 /* Overlay FIFO Status */
#define WM_LVL 0x3000 /* FIFO Watermark Level */
/* Bit masks for PIXC_AHSTART */
#define A_HSTART 0xfff /* Horizontal Start Coordinates */
/* Bit masks for PIXC_AHEND */
#define A_HEND 0xfff /* Horizontal End Coordinates */
/* Bit masks for PIXC_AVSTART */
#define A_VSTART 0x3ff /* Vertical Start Coordinates */
/* Bit masks for PIXC_AVEND */
#define A_VEND 0x3ff /* Vertical End Coordinates */
/* Bit masks for PIXC_ATRANSP */
#define A_TRANSP 0xf /* Transparency Value */
/* Bit masks for PIXC_BHSTART */
#define B_HSTART 0xfff /* Horizontal Start Coordinates */
/* Bit masks for PIXC_BHEND */
#define B_HEND 0xfff /* Horizontal End Coordinates */
/* Bit masks for PIXC_BVSTART */
#define B_VSTART 0x3ff /* Vertical Start Coordinates */
/* Bit masks for PIXC_BVEND */
#define B_VEND 0x3ff /* Vertical End Coordinates */
/* Bit masks for PIXC_BTRANSP */
#define B_TRANSP 0xf /* Transparency Value */
/* Bit masks for PIXC_INTRSTAT */
#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */
#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */
#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */
#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */
/* Bit masks for PIXC_RYCON */
#define A11 0x3ff /* A11 in the Coefficient Matrix */
#define A12 0xffc00 /* A12 in the Coefficient Matrix */
#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */
#define RY_MULT4 0x40000000 /* Multiply Row by 4 */
/* Bit masks for PIXC_GUCON */
#define A21 0x3ff /* A21 in the Coefficient Matrix */
#define A22 0xffc00 /* A22 in the Coefficient Matrix */
#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */
#define GU_MULT4 0x40000000 /* Multiply Row by 4 */
/* Bit masks for PIXC_BVCON */
#define A31 0x3ff /* A31 in the Coefficient Matrix */
#define A32 0xffc00 /* A32 in the Coefficient Matrix */
#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */
#define BV_MULT4 0x40000000 /* Multiply Row by 4 */
/* Bit masks for PIXC_CCBIAS */
#define A14 0x3ff /* A14 in the Bias Vector */
#define A24 0xffc00 /* A24 in the Bias Vector */
#define A34 0x3ff00000 /* A34 in the Bias Vector */
/* Bit masks for PIXC_TC */
#define RY_TRANS 0xff /* Transparent Color - R/Y Component */
#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */
#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */
/* Bit masks for HOST_CONTROL */
#define HOST_EN 0x1 /* Host Enable */
#define HOST_END 0x2 /* Host Endianess */
#define DATA_SIZE 0x4 /* Data Size */
#define HOST_RST 0x8 /* Host Reset */
#define HRDY_OVR 0x20 /* Host Ready Override */
#define INT_MODE 0x40 /* Interrupt Mode */
#define BT_EN 0x80 /* Bus Timeout Enable */
#define EHW 0x100 /* Enable Host Write */
#define EHR 0x200 /* Enable Host Read */
#define BDR 0x400 /* Burst DMA Requests */
/* Bit masks for HOST_STATUS */
#define DMA_READY 0x1 /* DMA Ready */
#define FIFOFULL 0x2 /* FIFO Full */
#define FIFOEMPTY 0x4 /* FIFO Empty */
#define DMA_COMPLETE 0x8 /* DMA Complete */
#define HSHK 0x10 /* Host Handshake */
#define TIMEOUT 0x20 /* Host Timeout */
#define HIRQ 0x40 /* Host Interrupt Request */
#define ALLOW_CNFG 0x80 /* Allow New Configuration */
#define DMA_DIR 0x100 /* DMA Direction */
#define BTE 0x200 /* Bus Timeout Enabled */
/* Bit masks for HOST_TIMEOUT */
#define COUNT_TIMEOUT 0x7ff /* Host Timeout count */
/* Bit masks for MXVR_CONFIG */
#define MXVREN 0x1 /* MXVR Enable */
......@@ -2031,603 +1050,6 @@
#define SCNT 0xffff /* System Clock Count */
/* Bit masks for KPAD_CTL */
#define KPAD_EN 0x1 /* Keypad Enable */
#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
#define KPAD_COLEN 0xe000 /* Column Enable Width */
/* Bit masks for KPAD_PRESCALE */
#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */
/* Bit masks for KPAD_MSEL */
#define DBON_SCALE 0xff /* Debounce Scale Value */
#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */
/* Bit masks for KPAD_ROWCOL */
#define KPAD_ROW 0xff /* Rows Pressed */
#define KPAD_COL 0xff00 /* Columns Pressed */
/* Bit masks for KPAD_STAT */
#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
#define KPAD_PRESSED 0x8 /* Key press current status */
/* Bit masks for KPAD_SOFTEVAL */
#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
/* Bit masks for SDH_COMMAND */
#define CMD_IDX 0x3f /* Command Index */
#define CMD_RSP 0x40 /* Response */
#define CMD_L_RSP 0x80 /* Long Response */
#define CMD_INT_E 0x100 /* Command Interrupt */
#define CMD_PEND_E 0x200 /* Command Pending */
#define CMD_E 0x400 /* Command Enable */
/* Bit masks for SDH_PWR_CTL */
#define PWR_ON 0x3 /* Power On */
#if 0
#define TBD 0x3c /* TBD */
#endif
#define SD_CMD_OD 0x40 /* Open Drain Output */
#define ROD_CTL 0x80 /* Rod Control */
/* Bit masks for SDH_CLK_CTL */
#define CLKDIV 0xff /* MC_CLK Divisor */
#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
#define PWR_SV_E 0x200 /* Power Save Enable */
#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
/* Bit masks for SDH_RESP_CMD */
#define RESP_CMD 0x3f /* Response Command */
/* Bit masks for SDH_DATA_CTL */
#define DTX_E 0x1 /* Data Transfer Enable */
#define DTX_DIR 0x2 /* Data Transfer Direction */
#define DTX_MODE 0x4 /* Data Transfer Mode */
#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
/* Bit masks for SDH_STATUS */
#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
#define CMD_TIME_OUT 0x4 /* CMD Time Out */
#define DAT_TIME_OUT 0x8 /* Data Time Out */
#define TX_UNDERRUN 0x10 /* Transmit Underrun */
#define RX_OVERRUN 0x20 /* Receive Overrun */
#define CMD_RESP_END 0x40 /* CMD Response End */
#define CMD_SENT 0x80 /* CMD Sent */
#define DAT_END 0x100 /* Data End */
#define START_BIT_ERR 0x200 /* Start Bit Error */
#define DAT_BLK_END 0x400 /* Data Block End */
#define CMD_ACT 0x800 /* CMD Active */
#define TX_ACT 0x1000 /* Transmit Active */
#define RX_ACT 0x2000 /* Receive Active */
#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
/* Bit masks for SDH_STATUS_CLR */
#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
#define DAT_END_STAT 0x100 /* Data End Status */
#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
/* Bit masks for SDH_MASK0 */
#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
#define DAT_END_MASK 0x100 /* Data End Mask */
#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
/* Bit masks for SDH_FIFO_CNT */
#define FIFO_COUNT 0x7fff /* FIFO Count */
/* Bit masks for SDH_E_STATUS */
#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
#define SD_CARD_DET 0x10 /* SD Card Detect */
/* Bit masks for SDH_E_MASK */
#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
#define SCD_MSK 0x40 /* Mask Card Detect */
/* Bit masks for SDH_CFG */
#define CLKS_EN 0x1 /* Clocks Enable */
#define SD4E 0x4 /* SDIO 4-Bit Enable */
#define MWE 0x8 /* Moving Window Enable */
#define SD_RST 0x10 /* SDMMC Reset */
#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
/* Bit masks for SDH_RD_WAIT_EN */
#define RWR 0x1 /* Read Wait Request */
/* Bit masks for ATAPI_CONTROL */
#define PIO_START 0x1 /* Start PIO/Reg Op */
#define MULTI_START 0x2 /* Start Multi-DMA Op */
#define ULTRA_START 0x4 /* Start Ultra-DMA Op */
#define XFER_DIR 0x8 /* Transfer Direction */
#define IORDY_EN 0x10 /* IORDY Enable */
#define FIFO_FLUSH 0x20 /* Flush FIFOs */
#define SOFT_RST 0x40 /* Soft Reset */
#define DEV_RST 0x80 /* Device Reset */
#define TFRCNT_RST 0x100 /* Trans Count Reset */
#define END_ON_TERM 0x200 /* End/Terminate Select */
#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
/* Bit masks for ATAPI_STATUS */
#define PIO_XFER_ON 0x1 /* PIO transfer in progress */
#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
/* Bit masks for ATAPI_DEV_ADDR */
#define DEV_ADDR 0x1f /* Device Address */
/* Bit masks for ATAPI_INT_MASK */
#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
/* Bit masks for ATAPI_INT_STATUS */
#define ATAPI_DEV_INT 0x1 /* Device interrupt status */
#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
/* Bit masks for ATAPI_LINE_STATUS */
#define ATAPI_INTR 0x1 /* Device interrupt to host line status */
#define ATAPI_DASP 0x2 /* Device dasp to host line status */
#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
#define ATAPI_ADDR 0x70 /* ATAPI address line status */
#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
#define ATAPI_DIOWN 0x200 /* ATAPI write line status */
#define ATAPI_DIORN 0x400 /* ATAPI read line status */
#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
/* Bit masks for ATAPI_SM_STATE */
#define PIO_CSTATE 0xf /* PIO mode state machine current state */
#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */
#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */
#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */
/* Bit masks for ATAPI_TERMINATE */
#define ATAPI_HOST_TERM 0x1 /* Host terminationation */
/* Bit masks for ATAPI_REG_TIM_0 */
#define T2_REG 0xff /* End of cycle time for register access transfers */
#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */
/* Bit masks for ATAPI_PIO_TIM_0 */
#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */
#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */
#define T4_REG 0xf000 /* DIOW data hold */
/* Bit masks for ATAPI_PIO_TIM_1 */
#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */
/* Bit masks for ATAPI_MULTI_TIM_0 */
#define TD 0xff /* DIOR/DIOW asserted pulsewidth */
#define TM 0xff00 /* Time from address valid to DIOR/DIOW */
/* Bit masks for ATAPI_MULTI_TIM_1 */
#define TKW 0xff /* Selects DIOW negated pulsewidth */
#define TKR 0xff00 /* Selects DIOR negated pulsewidth */
/* Bit masks for ATAPI_MULTI_TIM_2 */
#define TH 0xff /* Selects DIOW data hold */
#define TEOC 0xff00 /* Selects end of cycle for DMA */
/* Bit masks for ATAPI_ULTRA_TIM_0 */
#define TACK 0xff /* Selects setup and hold times for TACK */
#define TENV 0xff00 /* Selects envelope time */
/* Bit masks for ATAPI_ULTRA_TIM_1 */
#define TDVS 0xff /* Selects data valid setup time */
#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */
/* Bit masks for ATAPI_ULTRA_TIM_2 */
#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
#define TMLI 0xff00 /* Selects interlock time */
/* Bit masks for ATAPI_ULTRA_TIM_3 */
#define TZAH 0xff /* Selects minimum delay required for output */
#define READY_PAUSE 0xff00 /* Selects ready to pause */
/* Bit masks for TIMER_ENABLE1 */
#define TIMEN8 0x1 /* Timer 8 Enable */
#define TIMEN9 0x2 /* Timer 9 Enable */
#define TIMEN10 0x4 /* Timer 10 Enable */
/* Bit masks for TIMER_DISABLE1 */
#define TIMDIS8 0x1 /* Timer 8 Disable */
#define TIMDIS9 0x2 /* Timer 9 Disable */
#define TIMDIS10 0x4 /* Timer 10 Disable */
/* Bit masks for TIMER_STATUS1 */
#define TIMIL8 0x1 /* Timer 8 Interrupt */
#define TIMIL9 0x2 /* Timer 9 Interrupt */
#define TIMIL10 0x4 /* Timer 10 Interrupt */
#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */
#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */
#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */
#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */
#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */
#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */
/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
/* Bit masks for USB_FADDR */
#define FUNCTION_ADDRESS 0x7f /* Function address */
/* Bit masks for USB_POWER */
#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
#define RESUME_MODE 0x4 /* DMA Mode */
#define RESET 0x8 /* Reset indicator */
#define HS_MODE 0x10 /* High Speed mode indicator */
#define HS_ENABLE 0x20 /* high Speed Enable */
#define SOFT_CONN 0x40 /* Soft connect */
#define ISO_UPDATE 0x80 /* Isochronous update */
/* Bit masks for USB_INTRTX */
#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
/* Bit masks for USB_INTRRX */
#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
/* Bit masks for USB_INTRTXE */
#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
/* Bit masks for USB_INTRRXE */
#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
/* Bit masks for USB_INTRUSB */
#define SUSPEND_B 0x1 /* Suspend indicator */
#define RESUME_B 0x2 /* Resume indicator */
#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
#define SOF_B 0x8 /* Start of frame */
#define CONN_B 0x10 /* Connection indicator */
#define DISCON_B 0x20 /* Disconnect indicator */
#define SESSION_REQ_B 0x40 /* Session Request */
#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
/* Bit masks for USB_INTRUSBE */
#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
#define RESUME_BE 0x2 /* Resume indicator int enable */
#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
#define SOF_BE 0x8 /* Start of frame int enable */
#define CONN_BE 0x10 /* Connection indicator int enable */
#define DISCON_BE 0x20 /* Disconnect indicator int enable */
#define SESSION_REQ_BE 0x40 /* Session Request int enable */
#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
/* Bit masks for USB_FRAME */
#define FRAME_NUMBER 0x7ff /* Frame number */
/* Bit masks for USB_INDEX */
#define SELECTED_ENDPOINT 0xf /* selected endpoint */
/* Bit masks for USB_GLOBAL_CTL */
#define GLOBAL_ENA 0x1 /* enables USB module */
#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
/* Bit masks for USB_OTG_DEV_CTL */
#define SESSION 0x1 /* session indicator */
#define HOST_REQ 0x2 /* Host negotiation request */
#define HOST_MODE 0x4 /* indicates USBDRC is a host */
#define VBUS0 0x8 /* Vbus level indicator[0] */
#define VBUS1 0x10 /* Vbus level indicator[1] */
#define LSDEV 0x20 /* Low-speed indicator */
#define FSDEV 0x40 /* Full or High-speed indicator */
#define B_DEVICE 0x80 /* A' or 'B' device indicator */
/* Bit masks for USB_OTG_VBUS_IRQ */
#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
/* Bit masks for USB_OTG_VBUS_MASK */
#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
/* Bit masks for USB_CSR0 */
#define RXPKTRDY 0x1 /* data packet receive indicator */
#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
#define STALL_SENT 0x4 /* STALL handshake sent */
#define DATAEND 0x8 /* Data end indicator */
#define SETUPEND 0x10 /* Setup end */
#define SENDSTALL 0x20 /* Send STALL handshake */
#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
#define SETUPPKT_H 0x8 /* send Setup token host mode */
#define ERROR_H 0x10 /* timeout error indicator host mode */
#define REQPKT_H 0x20 /* Request an IN transaction host mode */
#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
/* Bit masks for USB_COUNT0 */
#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
/* Bit masks for USB_NAKLIMIT0 */
#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
/* Bit masks for USB_TX_MAX_PACKET */
#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
/* Bit masks for USB_RX_MAX_PACKET */
#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
/* Bit masks for USB_TXCSR */
#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
#define STALL_SEND_T 0x10 /* issue a Stall handshake */
#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
#define ISO_T 0x4000 /* enable Isochronous transfers */
#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
#define ERROR_TH 0x4 /* error condition host mode */
#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
/* Bit masks for USB_TXCOUNT */
#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
/* Bit masks for USB_RXCSR */
#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
#define FIFO_FULL_R 0x2 /* FIFO not empty */
#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
#define STALL_SEND_R 0x20 /* issue a Stall handshake */
#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
#define DISNYET_R 0x1000 /* disable Nyet handshakes */
#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
#define ISO_R 0x4000 /* enable Isochronous transfers */
#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
#define REQPKT_RH 0x20 /* request an IN transaction host mode */
#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
/* Bit masks for USB_RXCOUNT */
#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
/* Bit masks for USB_TXTYPE */
#define TARGET_EP_NO_T 0xf /* EP number */
#define PROTOCOL_T 0xc /* transfer type */
/* Bit masks for USB_TXINTERVAL */
#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
/* Bit masks for USB_RXTYPE */
#define TARGET_EP_NO_R 0xf /* EP number */
#define PROTOCOL_R 0xc /* transfer type */
/* Bit masks for USB_RXINTERVAL */
#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
/* Bit masks for USB_DMA_INTERRUPT */
#define DMA0_INT 0x1 /* DMA0 pending interrupt */
#define DMA1_INT 0x2 /* DMA1 pending interrupt */
#define DMA2_INT 0x4 /* DMA2 pending interrupt */
#define DMA3_INT 0x8 /* DMA3 pending interrupt */
#define DMA4_INT 0x10 /* DMA4 pending interrupt */
#define DMA5_INT 0x20 /* DMA5 pending interrupt */
#define DMA6_INT 0x40 /* DMA6 pending interrupt */
#define DMA7_INT 0x80 /* DMA7 pending interrupt */
/* Bit masks for USB_DMAxCONTROL */
#define DMA_ENA 0x1 /* DMA enable */
#define DIRECTION 0x2 /* direction of DMA transfer */
#define MODE 0x4 /* DMA Bus error */
#define INT_ENA 0x8 /* Interrupt enable */
#define EPNUM 0xf0 /* EP number */
#define BUSERROR 0x100 /* DMA Bus error */
/* Bit masks for USB_DMAxADDRHIGH */
#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
/* Bit masks for USB_DMAxADDRLOW */
#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
/* Bit masks for USB_DMAxCOUNTHIGH */
#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
/* Bit masks for USB_DMAxCOUNTLOW */
#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
/* Bit masks for HMDMAx_CONTROL */
#define HMDMAEN 0x1 /* Handshake MDMA Enable */
#define REP 0x2 /* Handshake MDMA Request Polarity */
#define UTE 0x8 /* Urgency Threshold Enable */
#define OIE 0x10 /* Overflow Interrupt Enable */
#define BDIE 0x20 /* Block Done Interrupt Enable */
#define MBDI 0x40 /* Mask Block Done Interrupt */
#define DRQ 0x300 /* Handshake MDMA Request Type */
#define RBC 0x1000 /* Force Reload of BCOUNT */
#define PS 0x2000 /* Pin Status */
#define OI 0x4000 /* Overflow Interrupt Generated */
#define BDI 0x8000 /* Block Done Interrupt Generated */
/* ******************************************* */
/* MULTI BIT MACRO ENUMERATIONS */
/* ******************************************* */
......
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