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kernel_linux
提交 500b9fc9 编写于 作者: R Russell King
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Merge master.kernel.org:/pub/scm/linux/kernel/git/lethal/genesis-2.6 into devel-stable 

Conflicts:
	drivers/net/irda/sh_irda.c
上级 f165eb77 beccb12f
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浏览文件 @ 500b9fc9
...@@ -955,8 +955,9 @@ ARM/SHMOBILE ARM ARCHITECTURE ...@@ -955,8 +955,9 @@ ARM/SHMOBILE ARM ARCHITECTURE
M: Paul Mundt <lethal@linux-sh.org> M: Paul Mundt <lethal@linux-sh.org>
M: Magnus Damm <magnus.damm@gmail.com> M: Magnus Damm <magnus.damm@gmail.com>
L: linux-sh@vger.kernel.org L: linux-sh@vger.kernel.org
T: git git://git.kernel.org/pub/scm/linux/kernel/git/lethal/genesis-2.6.git
W: http://oss.renesas.com W: http://oss.renesas.com
Q: http://patchwork.kernel.org/project/linux-sh/list/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/lethal/genesis-2.6.git
S: Supported S: Supported
F: arch/arm/mach-shmobile/ F: arch/arm/mach-shmobile/
F: drivers/sh/ F: drivers/sh/
......
arch/arm/mach-shmobile/Kconfig
浏览文件 @ 500b9fc9
...@@ -7,6 +7,7 @@ config ARCH_SH7367 ...@@ -7,6 +7,7 @@ config ARCH_SH7367
select CPU_V6 select CPU_V6
select HAVE_CLK select HAVE_CLK
select COMMON_CLKDEV select COMMON_CLKDEV
select SH_CLK_CPG
select GENERIC_CLOCKEVENTS select GENERIC_CLOCKEVENTS
config ARCH_SH7377 config ARCH_SH7377
...@@ -14,6 +15,7 @@ config ARCH_SH7377 ...@@ -14,6 +15,7 @@ config ARCH_SH7377
select CPU_V7 select CPU_V7
select HAVE_CLK select HAVE_CLK
select COMMON_CLKDEV select COMMON_CLKDEV
select SH_CLK_CPG
select GENERIC_CLOCKEVENTS select GENERIC_CLOCKEVENTS
config ARCH_SH7372 config ARCH_SH7372
...@@ -21,6 +23,7 @@ config ARCH_SH7372 ...@@ -21,6 +23,7 @@ config ARCH_SH7372
select CPU_V7 select CPU_V7
select HAVE_CLK select HAVE_CLK
select COMMON_CLKDEV select COMMON_CLKDEV
select SH_CLK_CPG
select GENERIC_CLOCKEVENTS select GENERIC_CLOCKEVENTS
comment "SH-Mobile Board Type" comment "SH-Mobile Board Type"
...@@ -39,6 +42,20 @@ config MACH_AP4EVB ...@@ -39,6 +42,20 @@ config MACH_AP4EVB
bool "AP4EVB board" bool "AP4EVB board"
depends on ARCH_SH7372 depends on ARCH_SH7372
select ARCH_REQUIRE_GPIOLIB select ARCH_REQUIRE_GPIOLIB
select SH_LCD_MIPI_DSI
choice
prompt "AP4EVB LCD panel selection"
default AP4EVB_QHD
depends on MACH_AP4EVB
config AP4EVB_QHD
bool "MIPI-DSI QHD (960x540)"
config AP4EVB_WVGA
bool "Parallel WVGA (800x480)"
endchoice
comment "SH-Mobile System Configuration" comment "SH-Mobile System Configuration"
...@@ -88,6 +105,15 @@ config SH_TIMER_CMT ...@@ -88,6 +105,15 @@ config SH_TIMER_CMT
help help
This enables build of the CMT timer driver. This enables build of the CMT timer driver.
config SH_TIMER_TMU
bool "TMU timer driver"
default y
help
This enables build of the TMU timer driver.
endmenu endmenu
config SH_CLK_CPG
bool
endif endif
arch/arm/mach-shmobile/Makefile
浏览文件 @ 500b9fc9
...@@ -3,12 +3,12 @@ ...@@ -3,12 +3,12 @@
# #
# Common objects # Common objects
obj-y := timer.o console.o obj-y := timer.o console.o clock.o
# CPU objects # CPU objects
obj-$(CONFIG_ARCH_SH7367) += setup-sh7367.o clock-sh7367.o intc-sh7367.o obj-$(CONFIG_ARCH_SH7367) += setup-sh7367.o clock-sh7367.o intc-sh7367.o
obj-$(CONFIG_ARCH_SH7377) += setup-sh7377.o clock-sh7367.o intc-sh7377.o obj-$(CONFIG_ARCH_SH7377) += setup-sh7377.o clock-sh7377.o intc-sh7377.o
obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7367.o intc-sh7372.o obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7372.o intc-sh7372.o
# Pinmux setup # Pinmux setup
pfc-$(CONFIG_ARCH_SH7367) := pfc-sh7367.o pfc-$(CONFIG_ARCH_SH7367) := pfc-sh7367.o
......
arch/arm/mach-shmobile/board-g3evm.c
浏览文件 @ 500b9fc9
...@@ -37,6 +37,15 @@ ...@@ -37,6 +37,15 @@
#include <asm/mach-types.h> #include <asm/mach-types.h>
#include <asm/mach/arch.h> #include <asm/mach/arch.h>
#include <asm/mach/map.h> #include <asm/mach/map.h>
#include <asm/mach/time.h>
/*
* IrDA
*
* S67: 5bit : ON power
* : 6bit : ON remote control
* OFF IrDA
*/
static struct mtd_partition nor_flash_partitions[] = { static struct mtd_partition nor_flash_partitions[] = {
{ {
...@@ -91,7 +100,7 @@ static struct platform_device nor_flash_device = { ...@@ -91,7 +100,7 @@ static struct platform_device nor_flash_device = {
}; };
/* USBHS */ /* USBHS */
void usb_host_port_power(int port, int power) static void usb_host_port_power(int port, int power)
{ {
if (!power) /* only power-on supported for now */ if (!power) /* only power-on supported for now */
return; return;
...@@ -113,7 +122,7 @@ static struct resource usb_host_resources[] = { ...@@ -113,7 +122,7 @@ static struct resource usb_host_resources[] = {
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
[1] = { [1] = {
.start = 65, .start = evt2irq(0xa20), /* USBHS_USHI0 */
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
}, },
}; };
...@@ -153,7 +162,7 @@ static struct resource keysc_resources[] = { ...@@ -153,7 +162,7 @@ static struct resource keysc_resources[] = {
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
[1] = { [1] = {
.start = 79, .start = evt2irq(0xbe0), /* KEYSC_KEY */
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
}, },
}; };
...@@ -209,11 +218,31 @@ static struct platform_device nand_flash_device = { ...@@ -209,11 +218,31 @@ static struct platform_device nand_flash_device = {
}, },
}; };
static struct resource irda_resources[] = {
[0] = {
.start = 0xE6D00000,
.end = 0xE6D01FD4 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0x480), /* IRDA */
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device irda_device = {
.name = "sh_irda",
.id = -1,
.resource = irda_resources,
.num_resources = ARRAY_SIZE(irda_resources),
};
static struct platform_device *g3evm_devices[] __initdata = { static struct platform_device *g3evm_devices[] __initdata = {
&nor_flash_device, &nor_flash_device,
&usb_host_device, &usb_host_device,
&keysc_device, &keysc_device,
&nand_flash_device, &nand_flash_device,
&irda_device,
}; };
static struct map_desc g3evm_io_desc[] __initdata = { static struct map_desc g3evm_io_desc[] __initdata = {
...@@ -232,9 +261,8 @@ static void __init g3evm_map_io(void) ...@@ -232,9 +261,8 @@ static void __init g3evm_map_io(void)
{ {
iotable_init(g3evm_io_desc, ARRAY_SIZE(g3evm_io_desc)); iotable_init(g3evm_io_desc, ARRAY_SIZE(g3evm_io_desc));
/* setup early devices, clocks and console here as well */ /* setup early devices and console here as well */
sh7367_add_early_devices(); sh7367_add_early_devices();
sh7367_clock_init();
shmobile_setup_console(); shmobile_setup_console();
} }
...@@ -271,9 +299,6 @@ static void __init g3evm_init(void) ...@@ -271,9 +299,6 @@ static void __init g3evm_init(void)
gpio_request(GPIO_FN_EXTLP, NULL); gpio_request(GPIO_FN_EXTLP, NULL);
gpio_request(GPIO_FN_IDIN, NULL); gpio_request(GPIO_FN_IDIN, NULL);
/* enable clock in SYMSTPCR2 */
__raw_writel(__raw_readl(0xe6158048) & ~(1 << 22), 0xe6158048);
/* setup USB phy */ /* setup USB phy */
__raw_writew(0x0300, 0xe605810a); /* USBCR1 */ __raw_writew(0x0300, 0xe605810a); /* USBCR1 */
__raw_writew(0x00e0, 0xe60581c0); /* CPFCH */ __raw_writew(0x00e0, 0xe60581c0); /* CPFCH */
...@@ -318,16 +343,32 @@ static void __init g3evm_init(void) ...@@ -318,16 +343,32 @@ static void __init g3evm_init(void)
/* FOE, FCDE, FSC on dedicated pins */ /* FOE, FCDE, FSC on dedicated pins */
__raw_writel(__raw_readl(0xe6158048) & ~(1 << 15), 0xe6158048); __raw_writel(__raw_readl(0xe6158048) & ~(1 << 15), 0xe6158048);
/* IrDA */
gpio_request(GPIO_FN_IRDA_OUT, NULL);
gpio_request(GPIO_FN_IRDA_IN, NULL);
gpio_request(GPIO_FN_IRDA_FIRSEL, NULL);
set_irq_type(evt2irq(0x480), IRQ_TYPE_LEVEL_LOW);
sh7367_add_standard_devices(); sh7367_add_standard_devices();
platform_add_devices(g3evm_devices, ARRAY_SIZE(g3evm_devices)); platform_add_devices(g3evm_devices, ARRAY_SIZE(g3evm_devices));
} }
static void __init g3evm_timer_init(void)
{
sh7367_clock_init();
shmobile_timer.init();
}
static struct sys_timer g3evm_timer = {
.init = g3evm_timer_init,
};
MACHINE_START(G3EVM, "g3evm") MACHINE_START(G3EVM, "g3evm")
.phys_io = 0xe6000000, .phys_io = 0xe6000000,
.io_pg_offst = ((0xe6000000) >> 18) & 0xfffc, .io_pg_offst = ((0xe6000000) >> 18) & 0xfffc,
.map_io = g3evm_map_io, .map_io = g3evm_map_io,
.init_irq = sh7367_init_irq, .init_irq = sh7367_init_irq,
.init_machine = g3evm_init, .init_machine = g3evm_init,
.timer = &shmobile_timer, .timer = &g3evm_timer,
MACHINE_END MACHINE_END
arch/arm/mach-shmobile/board-g4evm.c
浏览文件 @ 500b9fc9
...@@ -30,12 +30,39 @@ ...@@ -30,12 +30,39 @@
#include <linux/io.h> #include <linux/io.h>
#include <linux/input.h> #include <linux/input.h>
#include <linux/input/sh_keysc.h> #include <linux/input/sh_keysc.h>
#include <linux/mfd/sh_mobile_sdhi.h>
#include <linux/gpio.h> #include <linux/gpio.h>
#include <mach/sh7377.h> #include <mach/sh7377.h>
#include <mach/common.h> #include <mach/common.h>
#include <asm/mach-types.h> #include <asm/mach-types.h>
#include <asm/mach/arch.h> #include <asm/mach/arch.h>
#include <asm/mach/map.h> #include <asm/mach/map.h>
#include <asm/mach/time.h>
/*
* SDHI
*
* SDHI0 : card detection is possible
* SDHI1 : card detection is impossible
*
* [G4-MAIN-BOARD]
* JP74 : short # DBG_2V8A for SDHI0
* JP75 : NC # DBG_3V3A for SDHI0
* JP76 : NC # DBG_3V3A_SD for SDHI0
* JP77 : NC # 3V3A_SDIO for SDHI1
* JP78 : short # DBG_2V8A for SDHI1
* JP79 : NC # DBG_3V3A for SDHI1
* JP80 : NC # DBG_3V3A_SD for SDHI1
*
* [G4-CORE-BOARD]
* S32 : all off # to dissever from G3-CORE_DBG board
* S33 : all off # to dissever from G3-CORE_DBG board
*
* [G3-CORE_DBG-BOARD]
* S1 : all off # to dissever from G3-CORE_DBG board
* S3 : all off # to dissever from G3-CORE_DBG board
* S4 : all off # to dissever from G3-CORE_DBG board
*/
static struct mtd_partition nor_flash_partitions[] = { static struct mtd_partition nor_flash_partitions[] = {
{ {
...@@ -90,7 +117,7 @@ static struct platform_device nor_flash_device = { ...@@ -90,7 +117,7 @@ static struct platform_device nor_flash_device = {
}; };
/* USBHS */ /* USBHS */
void usb_host_port_power(int port, int power) static void usb_host_port_power(int port, int power)
{ {
if (!power) /* only power-on supported for now */ if (!power) /* only power-on supported for now */
return; return;
...@@ -112,8 +139,7 @@ static struct resource usb_host_resources[] = { ...@@ -112,8 +139,7 @@ static struct resource usb_host_resources[] = {
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
[1] = { [1] = {
.start = 65, .start = evt2irq(0x0a20), /* USBHS_USHI0 */
.end = 65,
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
}, },
}; };
...@@ -154,7 +180,7 @@ static struct resource keysc_resources[] = { ...@@ -154,7 +180,7 @@ static struct resource keysc_resources[] = {
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
[1] = { [1] = {
.start = 79, .start = evt2irq(0x0be0), /* KEYSC_KEY */
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
}, },
}; };
...@@ -169,10 +195,53 @@ static struct platform_device keysc_device = { ...@@ -169,10 +195,53 @@ static struct platform_device keysc_device = {
}, },
}; };
/* SDHI */
static struct resource sdhi0_resources[] = {
[0] = {
.name = "SDHI0",
.start = 0xe6d50000,
.end = 0xe6d501ff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0x0e00), /* SDHI0 */
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device sdhi0_device = {
.name = "sh_mobile_sdhi",
.num_resources = ARRAY_SIZE(sdhi0_resources),
.resource = sdhi0_resources,
.id = 0,
};
static struct resource sdhi1_resources[] = {
[0] = {
.name = "SDHI1",
.start = 0xe6d60000,
.end = 0xe6d601ff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0x0e80), /* SDHI1 */
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device sdhi1_device = {
.name = "sh_mobile_sdhi",
.num_resources = ARRAY_SIZE(sdhi1_resources),
.resource = sdhi1_resources,
.id = 1,
};
static struct platform_device *g4evm_devices[] __initdata = { static struct platform_device *g4evm_devices[] __initdata = {
&nor_flash_device, &nor_flash_device,
&usb_host_device, &usb_host_device,
&keysc_device, &keysc_device,
&sdhi0_device,
&sdhi1_device,
}; };
static struct map_desc g4evm_io_desc[] __initdata = { static struct map_desc g4evm_io_desc[] __initdata = {
...@@ -191,12 +260,41 @@ static void __init g4evm_map_io(void) ...@@ -191,12 +260,41 @@ static void __init g4evm_map_io(void)
{ {
iotable_init(g4evm_io_desc, ARRAY_SIZE(g4evm_io_desc)); iotable_init(g4evm_io_desc, ARRAY_SIZE(g4evm_io_desc));
/* setup early devices, clocks and console here as well */ /* setup early devices and console here as well */
sh7377_add_early_devices(); sh7377_add_early_devices();
sh7367_clock_init(); /* use g3 clocks for now */
shmobile_setup_console(); shmobile_setup_console();
} }
#define GPIO_SDHID0_D0 0xe60520fc
#define GPIO_SDHID0_D1 0xe60520fd
#define GPIO_SDHID0_D2 0xe60520fe
#define GPIO_SDHID0_D3 0xe60520ff
#define GPIO_SDHICMD0 0xe6052100
#define GPIO_SDHID1_D0 0xe6052103
#define GPIO_SDHID1_D1 0xe6052104
#define GPIO_SDHID1_D2 0xe6052105
#define GPIO_SDHID1_D3 0xe6052106
#define GPIO_SDHICMD1 0xe6052107
/*
* FIXME !!
*
* gpio_pull_up is quick_hack.
*
* current gpio frame work doesn't have
* the method to control only pull up/down/free.
* this function should be replaced by correct gpio function
*/
static void __init gpio_pull_up(u32 addr)
{
u8 data = __raw_readb(addr);
data &= 0x0F;
data |= 0xC0;
__raw_writeb(data, addr);
}
static void __init g4evm_init(void) static void __init g4evm_init(void)
{ {
sh7377_pinmux_init(); sh7377_pinmux_init();
...@@ -229,9 +327,6 @@ static void __init g4evm_init(void) ...@@ -229,9 +327,6 @@ static void __init g4evm_init(void)
gpio_request(GPIO_FN_EXTLP, NULL); gpio_request(GPIO_FN_EXTLP, NULL);
gpio_request(GPIO_FN_IDIN, NULL); gpio_request(GPIO_FN_IDIN, NULL);
/* enable clock in SMSTPCR3 */
__raw_writel(__raw_readl(0xe615013c) & ~(1 << 22), 0xe615013c);
/* setup USB phy */ /* setup USB phy */
__raw_writew(0x0200, 0xe605810a); /* USBCR1 */ __raw_writew(0x0200, 0xe605810a); /* USBCR1 */
__raw_writew(0x00e0, 0xe60581c0); /* CPFCH */ __raw_writew(0x00e0, 0xe60581c0); /* CPFCH */
...@@ -253,16 +348,54 @@ static void __init g4evm_init(void) ...@@ -253,16 +348,54 @@ static void __init g4evm_init(void)
gpio_request(GPIO_FN_PORT71_KEYIN5_PU, NULL); gpio_request(GPIO_FN_PORT71_KEYIN5_PU, NULL);
gpio_request(GPIO_FN_PORT72_KEYIN6_PU, NULL); gpio_request(GPIO_FN_PORT72_KEYIN6_PU, NULL);
/* SDHI0 */
gpio_request(GPIO_FN_SDHICLK0, NULL);
gpio_request(GPIO_FN_SDHICD0, NULL);
gpio_request(GPIO_FN_SDHID0_0, NULL);
gpio_request(GPIO_FN_SDHID0_1, NULL);
gpio_request(GPIO_FN_SDHID0_2, NULL);
gpio_request(GPIO_FN_SDHID0_3, NULL);
gpio_request(GPIO_FN_SDHICMD0, NULL);
gpio_request(GPIO_FN_SDHIWP0, NULL);
gpio_pull_up(GPIO_SDHID0_D0);
gpio_pull_up(GPIO_SDHID0_D1);
gpio_pull_up(GPIO_SDHID0_D2);
gpio_pull_up(GPIO_SDHID0_D3);
gpio_pull_up(GPIO_SDHICMD0);
/* SDHI1 */
gpio_request(GPIO_FN_SDHICLK1, NULL);
gpio_request(GPIO_FN_SDHID1_0, NULL);
gpio_request(GPIO_FN_SDHID1_1, NULL);
gpio_request(GPIO_FN_SDHID1_2, NULL);
gpio_request(GPIO_FN_SDHID1_3, NULL);
gpio_request(GPIO_FN_SDHICMD1, NULL);
gpio_pull_up(GPIO_SDHID1_D0);
gpio_pull_up(GPIO_SDHID1_D1);
gpio_pull_up(GPIO_SDHID1_D2);
gpio_pull_up(GPIO_SDHID1_D3);
gpio_pull_up(GPIO_SDHICMD1);
sh7377_add_standard_devices(); sh7377_add_standard_devices();
platform_add_devices(g4evm_devices, ARRAY_SIZE(g4evm_devices)); platform_add_devices(g4evm_devices, ARRAY_SIZE(g4evm_devices));
} }
static void __init g4evm_timer_init(void)
{
sh7377_clock_init();
shmobile_timer.init();
}
static struct sys_timer g4evm_timer = {
.init = g4evm_timer_init,
};
MACHINE_START(G4EVM, "g4evm") MACHINE_START(G4EVM, "g4evm")
.phys_io = 0xe6000000, .phys_io = 0xe6000000,
.io_pg_offst = ((0xe6000000) >> 18) & 0xfffc, .io_pg_offst = ((0xe6000000) >> 18) & 0xfffc,
.map_io = g4evm_map_io, .map_io = g4evm_map_io,
.init_irq = sh7377_init_irq, .init_irq = sh7377_init_irq,
.init_machine = g4evm_init, .init_machine = g4evm_init,
.timer = &shmobile_timer, .timer = &g4evm_timer,
MACHINE_END MACHINE_END
arch/arm/mach-shmobile/clock-sh7367.c
浏览文件 @ 500b9fc9
/* /*
* Preliminary clock framework support for sh7367 * SH7367 clock framework support
* *
* Copyright (C) 2010 Magnus Damm * Copyright (C) 2010 Magnus Damm
* *
...@@ -17,87 +17,342 @@ ...@@ -17,87 +17,342 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#include <linux/init.h> #include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/list.h> #include <linux/io.h>
#include <linux/clk.h> #include <linux/sh_clk.h>
#include <mach/common.h>
#include <asm/clkdev.h>
/* SH7367 registers */
#define RTFRQCR 0xe6150000
#define SYFRQCR 0xe6150004
#define CMFRQCR 0xe61500E0
#define VCLKCR1 0xe6150008
#define VCLKCR2 0xe615000C
#define VCLKCR3 0xe615001C
#define SCLKACR 0xe6150010
#define SCLKBCR 0xe6150014
#define SUBUSBCKCR 0xe6158080
#define SPUCKCR 0xe6150084
#define MSUCKCR 0xe6150088
#define MVI3CKCR 0xe6150090
#define VOUCKCR 0xe6150094
#define MFCK1CR 0xe6150098
#define MFCK2CR 0xe615009C
#define PLLC1CR 0xe6150028
#define PLLC2CR 0xe615002C
#define RTMSTPCR0 0xe6158030
#define RTMSTPCR2 0xe6158038
#define SYMSTPCR0 0xe6158040
#define SYMSTPCR2 0xe6158048
#define CMMSTPCR0 0xe615804c
struct clk { /* Fixed 32 KHz root clock from EXTALR pin */
const char *name; static struct clk r_clk = {
unsigned long rate; .rate = 32768,
}; };
#include <asm/clkdev.h> /*
* 26MHz default rate for the EXTALB1 root input clock.
* If needed, reset this with clk_set_rate() from the platform code.
*/
struct clk sh7367_extalb1_clk = {
.rate = 26666666,
};
int __clk_get(struct clk *clk) /*
{ * 48MHz default rate for the EXTAL2 root input clock.
return 1; * If needed, reset this with clk_set_rate() from the platform code.
} */
EXPORT_SYMBOL(__clk_get); struct clk sh7367_extal2_clk = {
.rate = 48000000,
};
void __clk_put(struct clk *clk) /* A fixed divide-by-2 block */
static unsigned long div2_recalc(struct clk *clk)
{ {
return clk->parent->rate / 2;
} }
EXPORT_SYMBOL(__clk_put);
static struct clk_ops div2_clk_ops = {
.recalc = div2_recalc,
};
/* Divide extalb1 by two */
static struct clk extalb1_div2_clk = {
.ops = &div2_clk_ops,
.parent = &sh7367_extalb1_clk,
};
int clk_enable(struct clk *clk) /* Divide extal2 by two */
static struct clk extal2_div2_clk = {
.ops = &div2_clk_ops,
.parent = &sh7367_extal2_clk,
};
/* PLLC1 */
static unsigned long pllc1_recalc(struct clk *clk)
{ {
return 0; unsigned long mult = 1;
if (__raw_readl(PLLC1CR) & (1 << 14))
mult = (((__raw_readl(RTFRQCR) >> 24) & 0x3f) + 1) * 2;
return clk->parent->rate * mult;
} }
EXPORT_SYMBOL(clk_enable);
void clk_disable(struct clk *clk) static struct clk_ops pllc1_clk_ops = {
.recalc = pllc1_recalc,
};
static struct clk pllc1_clk = {
.ops = &pllc1_clk_ops,
.flags = CLK_ENABLE_ON_INIT,
.parent = &extalb1_div2_clk,
};
/* Divide PLLC1 by two */
static struct clk pllc1_div2_clk = {
.ops = &div2_clk_ops,
.parent = &pllc1_clk,
};
/* PLLC2 */
static unsigned long pllc2_recalc(struct clk *clk)
{ {
unsigned long mult = 1;
if (__raw_readl(PLLC2CR) & (1 << 31))
mult = (((__raw_readl(PLLC2CR) >> 24) & 0x3f) + 1) * 2;
return clk->parent->rate * mult;
} }
EXPORT_SYMBOL(clk_disable);
unsigned long clk_get_rate(struct clk *clk) static struct clk_ops pllc2_clk_ops = {
.recalc = pllc2_recalc,
};
static struct clk pllc2_clk = {
.ops = &pllc2_clk_ops,
.flags = CLK_ENABLE_ON_INIT,
.parent = &extalb1_div2_clk,
};
static struct clk *main_clks[] = {
&r_clk,
&sh7367_extalb1_clk,
&sh7367_extal2_clk,
&extalb1_div2_clk,
&extal2_div2_clk,
&pllc1_clk,
&pllc1_div2_clk,
&pllc2_clk,
};
static void div4_kick(struct clk *clk)
{ {
return clk ? clk->rate : 0; unsigned long value;
/* set KICK bit in SYFRQCR to update hardware setting */
value = __raw_readl(SYFRQCR);
value |= (1 << 31);
__raw_writel(value, SYFRQCR);
} }
EXPORT_SYMBOL(clk_get_rate);
/* a static peripheral clock for now - enough to get sh-sci working */ static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
static struct clk peripheral_clk = { 24, 32, 36, 48, 0, 72, 0, 0 };
.name = "peripheral_clk",
.rate = 48000000, static struct clk_div_mult_table div4_div_mult_table = {
.divisors = divisors,
.nr_divisors = ARRAY_SIZE(divisors),
}; };
/* a static rclk for now - enough to get sh_cmt working */ static struct clk_div4_table div4_table = {
static struct clk r_clk = { .div_mult_table = &div4_div_mult_table,
.name = "r_clk", .kick = div4_kick,
.rate = 32768, };
enum { DIV4_I, DIV4_G, DIV4_S, DIV4_B,
DIV4_ZX, DIV4_ZT, DIV4_Z, DIV4_ZD, DIV4_HP,
DIV4_ZS, DIV4_ZB, DIV4_ZB3, DIV4_CP, DIV4_NR };
#define DIV4(_reg, _bit, _mask, _flags) \
SH_CLK_DIV4(&pllc1_clk, _reg, _bit, _mask, _flags)
static struct clk div4_clks[DIV4_NR] = {
[DIV4_I] = DIV4(RTFRQCR, 20, 0x6fff, CLK_ENABLE_ON_INIT),
[DIV4_G] = DIV4(RTFRQCR, 16, 0x6fff, CLK_ENABLE_ON_INIT),
[DIV4_S] = DIV4(RTFRQCR, 12, 0x6fff, CLK_ENABLE_ON_INIT),
[DIV4_B] = DIV4(RTFRQCR, 8, 0x6fff, CLK_ENABLE_ON_INIT),
[DIV4_ZX] = DIV4(SYFRQCR, 20, 0x6fff, 0),
[DIV4_ZT] = DIV4(SYFRQCR, 16, 0x6fff, 0),
[DIV4_Z] = DIV4(SYFRQCR, 12, 0x6fff, 0),
[DIV4_ZD] = DIV4(SYFRQCR, 8, 0x6fff, 0),
[DIV4_HP] = DIV4(SYFRQCR, 4, 0x6fff, 0),
[DIV4_ZS] = DIV4(CMFRQCR, 12, 0x6fff, 0),
[DIV4_ZB] = DIV4(CMFRQCR, 8, 0x6fff, 0),
[DIV4_ZB3] = DIV4(CMFRQCR, 4, 0x6fff, 0),
[DIV4_CP] = DIV4(CMFRQCR, 0, 0x6fff, 0),
}; };
/* a static usb0 for now - enough to get r8a66597 working */ enum { DIV6_SUB, DIV6_SIUA, DIV6_SIUB, DIV6_MSU, DIV6_SPU,
static struct clk usb0_clk = { DIV6_MVI3, DIV6_MF1, DIV6_MF2,
.name = "usb0", DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_VOU,
DIV6_NR };
static struct clk div6_clks[DIV6_NR] = {
[DIV6_SUB] = SH_CLK_DIV6(&sh7367_extal2_clk, SUBUSBCKCR, 0),
[DIV6_SIUA] = SH_CLK_DIV6(&pllc1_div2_clk, SCLKACR, 0),
[DIV6_SIUB] = SH_CLK_DIV6(&pllc1_div2_clk, SCLKBCR, 0),
[DIV6_MSU] = SH_CLK_DIV6(&pllc1_div2_clk, MSUCKCR, 0),
[DIV6_SPU] = SH_CLK_DIV6(&pllc1_div2_clk, SPUCKCR, 0),
[DIV6_MVI3] = SH_CLK_DIV6(&pllc1_div2_clk, MVI3CKCR, 0),
[DIV6_MF1] = SH_CLK_DIV6(&pllc1_div2_clk, MFCK1CR, 0),
[DIV6_MF2] = SH_CLK_DIV6(&pllc1_div2_clk, MFCK2CR, 0),
[DIV6_VCK1] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR1, 0),
[DIV6_VCK2] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR2, 0),
[DIV6_VCK3] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR3, 0),
[DIV6_VOU] = SH_CLK_DIV6(&pllc1_div2_clk, VOUCKCR, 0),
}; };
/* a static keysc0 clk for now - enough to get sh_keysc working */ enum { RTMSTP001,
static struct clk keysc0_clk = { RTMSTP231, RTMSTP230, RTMSTP229, RTMSTP228, RTMSTP226,
.name = "keysc0", RTMSTP216, RTMSTP206, RTMSTP205, RTMSTP201,
SYMSTP023, SYMSTP007, SYMSTP006, SYMSTP004,
SYMSTP003, SYMSTP002, SYMSTP001, SYMSTP000,
SYMSTP231, SYMSTP229, SYMSTP225, SYMSTP223, SYMSTP222,
SYMSTP215, SYMSTP214, SYMSTP213, SYMSTP211,
CMMSTP003,
MSTP_NR };
#define MSTP(_parent, _reg, _bit, _flags) \
SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
static struct clk mstp_clks[MSTP_NR] = {
[RTMSTP001] = MSTP(&div6_clks[DIV6_SUB], RTMSTPCR0, 1, 0), /* IIC2 */
[RTMSTP231] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 31, 0), /* VEU3 */
[RTMSTP230] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 30, 0), /* VEU2 */
[RTMSTP229] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 29, 0), /* VEU1 */
[RTMSTP228] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 28, 0), /* VEU0 */
[RTMSTP226] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 26, 0), /* VEU2H */
[RTMSTP216] = MSTP(&div6_clks[DIV6_SUB], RTMSTPCR2, 16, 0), /* IIC0 */
[RTMSTP206] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 6, 0), /* JPU */
[RTMSTP205] = MSTP(&div6_clks[DIV6_VOU], RTMSTPCR2, 5, 0), /* VOU */
[RTMSTP201] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 1, 0), /* VPU */
[SYMSTP023] = MSTP(&div6_clks[DIV6_SPU], SYMSTPCR0, 23, 0), /* SPU1 */
[SYMSTP007] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 7, 0), /* SCIFA5 */
[SYMSTP006] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 6, 0), /* SCIFB */
[SYMSTP004] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 4, 0), /* SCIFA0 */
[SYMSTP003] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 3, 0), /* SCIFA1 */
[SYMSTP002] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 2, 0), /* SCIFA2 */
[SYMSTP001] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 1, 0), /* SCIFA3 */
[SYMSTP000] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 0, 0), /* SCIFA4 */
[SYMSTP231] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR2, 31, 0), /* SIU */
[SYMSTP229] = MSTP(&r_clk, SYMSTPCR2, 29, 0), /* CMT10 */
[SYMSTP225] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR2, 25, 0), /* IRDA */
[SYMSTP223] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR2, 23, 0), /* IIC1 */
[SYMSTP222] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR2, 22, 0), /* USBHS */
[SYMSTP215] = MSTP(&div4_clks[DIV4_HP], SYMSTPCR2, 15, 0), /* FLCTL */
[SYMSTP214] = MSTP(&div4_clks[DIV4_HP], SYMSTPCR2, 14, 0), /* SDHI0 */
[SYMSTP213] = MSTP(&div4_clks[DIV4_HP], SYMSTPCR2, 13, 0), /* SDHI1 */
[SYMSTP211] = MSTP(&div4_clks[DIV4_HP], SYMSTPCR2, 11, 0), /* SDHI2 */
[CMMSTP003] = MSTP(&r_clk, CMMSTPCR0, 3, 0), /* KEYSC */
}; };
#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
static struct clk_lookup lookups[] = { static struct clk_lookup lookups[] = {
{ /* main clocks */
.clk = &peripheral_clk, CLKDEV_CON_ID("r_clk", &r_clk),
}, { CLKDEV_CON_ID("extalb1", &sh7367_extalb1_clk),
.clk = &r_clk, CLKDEV_CON_ID("extal2", &sh7367_extal2_clk),
}, { CLKDEV_CON_ID("extalb1_div2_clk", &extalb1_div2_clk),
.clk = &usb0_clk, CLKDEV_CON_ID("extal2_div2_clk", &extal2_div2_clk),
}, { CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
.clk = &keysc0_clk, CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
} CLKDEV_CON_ID("pllc2_clk", &pllc2_clk),
/* DIV4 clocks */
CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
CLKDEV_CON_ID("g_clk", &div4_clks[DIV4_G]),
CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
CLKDEV_CON_ID("zx_clk", &div4_clks[DIV4_ZX]),
CLKDEV_CON_ID("zt_clk", &div4_clks[DIV4_ZT]),
CLKDEV_CON_ID("z_clk", &div4_clks[DIV4_Z]),
CLKDEV_CON_ID("zd_clk", &div4_clks[DIV4_ZD]),
CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]),
CLKDEV_CON_ID("zs_clk", &div4_clks[DIV4_ZS]),
CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]),
CLKDEV_CON_ID("zb3_clk", &div4_clks[DIV4_ZB3]),
CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]),
/* DIV6 clocks */
CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]),
CLKDEV_CON_ID("siua_clk", &div6_clks[DIV6_SIUA]),
CLKDEV_CON_ID("siub_clk", &div6_clks[DIV6_SIUB]),
CLKDEV_CON_ID("msu_clk", &div6_clks[DIV6_MSU]),
CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]),
CLKDEV_CON_ID("mvi3_clk", &div6_clks[DIV6_MVI3]),
CLKDEV_CON_ID("mf1_clk", &div6_clks[DIV6_MF1]),
CLKDEV_CON_ID("mf2_clk", &div6_clks[DIV6_MF2]),
CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]),
CLKDEV_CON_ID("vou_clk", &div6_clks[DIV6_VOU]),
/* MSTP32 clocks */
CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[RTMSTP001]), /* IIC2 */
CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[RTMSTP231]), /* VEU3 */
CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[RTMSTP230]), /* VEU2 */
CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[RTMSTP229]), /* VEU1 */
CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[RTMSTP228]), /* VEU0 */
CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[RTMSTP226]), /* VEU2H */
CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[RTMSTP216]), /* IIC0 */
CLKDEV_DEV_ID("uio_pdrv_genirq.6", &mstp_clks[RTMSTP206]), /* JPU */
CLKDEV_DEV_ID("sh-vou", &mstp_clks[RTMSTP205]), /* VOU */
CLKDEV_DEV_ID("uio_pdrv_genirq.0", &mstp_clks[RTMSTP201]), /* VPU */
CLKDEV_DEV_ID("uio_pdrv_genirq.7", &mstp_clks[SYMSTP023]), /* SPU1 */
CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[SYMSTP007]), /* SCIFA5 */
CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[SYMSTP006]), /* SCIFB */
CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[SYMSTP004]), /* SCIFA0 */
CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[SYMSTP003]), /* SCIFA1 */
CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[SYMSTP002]), /* SCIFA2 */
CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[SYMSTP001]), /* SCIFA3 */
CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[SYMSTP000]), /* SCIFA4 */
CLKDEV_DEV_ID("sh_siu", &mstp_clks[SYMSTP231]), /* SIU */
CLKDEV_CON_ID("cmt1", &mstp_clks[SYMSTP229]), /* CMT10 */
CLKDEV_DEV_ID("sh_irda", &mstp_clks[SYMSTP225]), /* IRDA */
CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[SYMSTP223]), /* IIC1 */
CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[SYMSTP222]), /* USBHS */
CLKDEV_DEV_ID("r8a66597_udc.0", &mstp_clks[SYMSTP222]), /* USBHS */
CLKDEV_DEV_ID("sh_flctl", &mstp_clks[SYMSTP215]), /* FLCTL */
CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[SYMSTP214]), /* SDHI0 */
CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[SYMSTP213]), /* SDHI1 */
CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[SYMSTP211]), /* SDHI2 */
CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[CMMSTP003]), /* KEYSC */
}; };
void __init sh7367_clock_init(void) void __init sh7367_clock_init(void)
{ {
int i; int k, ret = 0;
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
ret = clk_register(main_clks[k]);
if (!ret)
ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
if (!ret)
ret = sh_clk_div6_register(div6_clks, DIV6_NR);
if (!ret)
ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
for (i = 0; i < ARRAY_SIZE(lookups); i++) { if (!ret)
lookups[i].con_id = lookups[i].clk->name; clk_init();
clkdev_add(&lookups[i]); else
} panic("failed to setup sh7367 clocks\n");
} }
arch/arm/mach-shmobile/clock-sh7372.c 0 → 100644
浏览文件 @ 500b9fc9
/*
* SH7372 clock framework support
*
* Copyright (C) 2010 Magnus Damm
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/sh_clk.h>
#include <mach/common.h>
#include <asm/clkdev.h>
/* SH7372 registers */
#define FRQCRA 0xe6150000
#define FRQCRB 0xe6150004
#define FRQCRC 0xe61500e0
#define FRQCRD 0xe61500e4
#define VCLKCR1 0xe6150008
#define VCLKCR2 0xe615000c
#define VCLKCR3 0xe615001c
#define FMSICKCR 0xe6150010
#define FMSOCKCR 0xe6150014
#define FSIACKCR 0xe6150018
#define FSIBCKCR 0xe6150090
#define SUBCKCR 0xe6150080
#define SPUCKCR 0xe6150084
#define VOUCKCR 0xe6150088
#define HDMICKCR 0xe6150094
#define DSITCKCR 0xe6150060
#define DSI0PCKCR 0xe6150064
#define DSI1PCKCR 0xe6150098
#define PLLC01CR 0xe6150028
#define PLLC2CR 0xe615002c
#define SMSTPCR0 0xe6150130
#define SMSTPCR1 0xe6150134
#define SMSTPCR2 0xe6150138
#define SMSTPCR3 0xe615013c
#define SMSTPCR4 0xe6150140
/* Platforms must set frequency on their DV_CLKI pin */
struct clk dv_clki_clk = {
};
/* Fixed 32 KHz root clock from EXTALR pin */
static struct clk r_clk = {
.rate = 32768,
};
/*
* 26MHz default rate for the EXTAL1 root input clock.
* If needed, reset this with clk_set_rate() from the platform code.
*/
struct clk sh7372_extal1_clk = {
.rate = 26000000,
};
/*
* 48MHz default rate for the EXTAL2 root input clock.
* If needed, reset this with clk_set_rate() from the platform code.
*/
struct clk sh7372_extal2_clk = {
.rate = 48000000,
};
/* A fixed divide-by-2 block */
static unsigned long div2_recalc(struct clk *clk)
{
return clk->parent->rate / 2;
}
static struct clk_ops div2_clk_ops = {
.recalc = div2_recalc,
};
/* Divide dv_clki by two */
struct clk dv_clki_div2_clk = {
.ops = &div2_clk_ops,
.parent = &dv_clki_clk,
};
/* Divide extal1 by two */
static struct clk extal1_div2_clk = {
.ops = &div2_clk_ops,
.parent = &sh7372_extal1_clk,
};
/* Divide extal2 by two */
static struct clk extal2_div2_clk = {
.ops = &div2_clk_ops,
.parent = &sh7372_extal2_clk,
};
/* Divide extal2 by four */
static struct clk extal2_div4_clk = {
.ops = &div2_clk_ops,
.parent = &extal2_div2_clk,
};
/* PLLC0 and PLLC1 */
static unsigned long pllc01_recalc(struct clk *clk)
{
unsigned long mult = 1;
if (__raw_readl(PLLC01CR) & (1 << 14))
mult = (((__raw_readl(clk->enable_reg) >> 24) & 0x3f) + 1) * 2;
return clk->parent->rate * mult;
}
static struct clk_ops pllc01_clk_ops = {
.recalc = pllc01_recalc,
};
static struct clk pllc0_clk = {
.ops = &pllc01_clk_ops,
.flags = CLK_ENABLE_ON_INIT,
.parent = &extal1_div2_clk,
.enable_reg = (void __iomem *)FRQCRC,
};
static struct clk pllc1_clk = {
.ops = &pllc01_clk_ops,
.flags = CLK_ENABLE_ON_INIT,
.parent = &extal1_div2_clk,
.enable_reg = (void __iomem *)FRQCRA,
};
/* Divide PLLC1 by two */
static struct clk pllc1_div2_clk = {
.ops = &div2_clk_ops,
.parent = &pllc1_clk,
};
/* PLLC2 */
/* Indices are important - they are the actual src selecting values */
static struct clk *pllc2_parent[] = {
[0] = &extal1_div2_clk,
[1] = &extal2_div2_clk,
[2] = &dv_clki_div2_clk,
};
/* Only multipliers 20 * 2 to 46 * 2 are valid, last entry for CPUFREQ_TABLE_END */
static struct cpufreq_frequency_table pllc2_freq_table[29];
static void pllc2_table_rebuild(struct clk *clk)
{
int i;
/* Initialise PLLC2 frequency table */
for (i = 0; i < ARRAY_SIZE(pllc2_freq_table) - 2; i++) {
pllc2_freq_table[i].frequency = clk->parent->rate * (i + 20) * 2;
pllc2_freq_table[i].index = i;
}
/* This is a special entry - switching PLL off makes it a repeater */
pllc2_freq_table[i].frequency = clk->parent->rate;
pllc2_freq_table[i].index = i;
pllc2_freq_table[++i].frequency = CPUFREQ_TABLE_END;
pllc2_freq_table[i].index = i;
}
static unsigned long pllc2_recalc(struct clk *clk)
{
unsigned long mult = 1;
pllc2_table_rebuild(clk);
/*
* If the PLL is off, mult == 1, clk->rate will be updated in
* pllc2_enable().
*/
if (__raw_readl(PLLC2CR) & (1 << 31))
mult = (((__raw_readl(PLLC2CR) >> 24) & 0x3f) + 1) * 2;
return clk->parent->rate * mult;
}
static long pllc2_round_rate(struct clk *clk, unsigned long rate)
{
return clk_rate_table_round(clk, clk->freq_table, rate);
}
static int pllc2_enable(struct clk *clk)
{
int i;
__raw_writel(__raw_readl(PLLC2CR) | 0x80000000, PLLC2CR);
for (i = 0; i < 100; i++)
if (__raw_readl(PLLC2CR) & 0x80000000) {
clk->rate = pllc2_recalc(clk);
return 0;
}
pr_err("%s(): timeout!\n", __func__);
return -ETIMEDOUT;
}
static void pllc2_disable(struct clk *clk)
{
__raw_writel(__raw_readl(PLLC2CR) & ~0x80000000, PLLC2CR);
}
static int pllc2_set_rate(struct clk *clk,
unsigned long rate, int algo_id)
{
unsigned long value;
int idx;
idx = clk_rate_table_find(clk, clk->freq_table, rate);
if (idx < 0)
return idx;
if (rate == clk->parent->rate) {
pllc2_disable(clk);
return 0;
}
value = __raw_readl(PLLC2CR) & ~(0x3f << 24);
if (value & 0x80000000)
pllc2_disable(clk);
__raw_writel((value & ~0x80000000) | ((idx + 19) << 24), PLLC2CR);
if (value & 0x80000000)
return pllc2_enable(clk);
return 0;
}
static int pllc2_set_parent(struct clk *clk, struct clk *parent)
{
u32 value;
int ret, i;
if (!clk->parent_table || !clk->parent_num)
return -EINVAL;
/* Search the parent */
for (i = 0; i < clk->parent_num; i++)
if (clk->parent_table[i] == parent)
break;
if (i == clk->parent_num)
return -ENODEV;
ret = clk_reparent(clk, parent);
if (ret < 0)
return ret;
value = __raw_readl(PLLC2CR) & ~(3 << 6);
__raw_writel(value | (i << 6), PLLC2CR);
/* Rebiuld the frequency table */
pllc2_table_rebuild(clk);
return 0;
}
static struct clk_ops pllc2_clk_ops = {
.recalc = pllc2_recalc,
.round_rate = pllc2_round_rate,
.set_rate = pllc2_set_rate,
.enable = pllc2_enable,
.disable = pllc2_disable,
.set_parent = pllc2_set_parent,
};
struct clk pllc2_clk = {
.ops = &pllc2_clk_ops,
.flags = CLK_ENABLE_ON_INIT,
.parent = &extal1_div2_clk,
.freq_table = pllc2_freq_table,
.parent_table = pllc2_parent,
.parent_num = ARRAY_SIZE(pllc2_parent),
};
static struct clk *main_clks[] = {
&dv_clki_clk,
&r_clk,
&sh7372_extal1_clk,
&sh7372_extal2_clk,
&dv_clki_div2_clk,
&extal1_div2_clk,
&extal2_div2_clk,
&extal2_div4_clk,
&pllc0_clk,
&pllc1_clk,
&pllc1_div2_clk,
&pllc2_clk,
};
static void div4_kick(struct clk *clk)
{
unsigned long value;
/* set KICK bit in FRQCRB to update hardware setting */
value = __raw_readl(FRQCRB);
value |= (1 << 31);
__raw_writel(value, FRQCRB);
}
static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
24, 32, 36, 48, 0, 72, 96, 0 };
static struct clk_div_mult_table div4_div_mult_table = {
.divisors = divisors,
.nr_divisors = ARRAY_SIZE(divisors),
};
static struct clk_div4_table div4_table = {
.div_mult_table = &div4_div_mult_table,
.kick = div4_kick,
};
enum { DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_CSIR,
DIV4_ZTR, DIV4_ZT, DIV4_ZX, DIV4_HP,
DIV4_ISPB, DIV4_S, DIV4_ZB, DIV4_ZB3, DIV4_CP,
DIV4_DDRP, DIV4_NR };
#define DIV4(_reg, _bit, _mask, _flags) \
SH_CLK_DIV4(&pllc1_clk, _reg, _bit, _mask, _flags)
static struct clk div4_clks[DIV4_NR] = {
[DIV4_I] = DIV4(FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT),
[DIV4_ZG] = DIV4(FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT),
[DIV4_B] = DIV4(FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT),
[DIV4_M1] = DIV4(FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT),
[DIV4_CSIR] = DIV4(FRQCRA, 0, 0x6fff, 0),
[DIV4_ZTR] = DIV4(FRQCRB, 20, 0x6fff, 0),
[DIV4_ZT] = DIV4(FRQCRB, 16, 0x6fff, 0),
[DIV4_ZX] = DIV4(FRQCRB, 12, 0x6fff, 0),
[DIV4_HP] = DIV4(FRQCRB, 4, 0x6fff, 0),
[DIV4_ISPB] = DIV4(FRQCRC, 20, 0x6fff, 0),
[DIV4_S] = DIV4(FRQCRC, 12, 0x6fff, 0),
[DIV4_ZB] = DIV4(FRQCRC, 8, 0x6fff, 0),
[DIV4_ZB3] = DIV4(FRQCRC, 4, 0x6fff, 0),
[DIV4_CP] = DIV4(FRQCRC, 0, 0x6fff, 0),
[DIV4_DDRP] = DIV4(FRQCRD, 0, 0x677c, 0),
};
enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_FMSI, DIV6_FMSO,
DIV6_FSIA, DIV6_FSIB, DIV6_SUB, DIV6_SPU,
DIV6_VOU, DIV6_DSIT, DIV6_DSI0P, DIV6_DSI1P,
DIV6_NR };
static struct clk div6_clks[DIV6_NR] = {
[DIV6_VCK1] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR1, 0),
[DIV6_VCK2] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR2, 0),
[DIV6_VCK3] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR3, 0),
[DIV6_FMSI] = SH_CLK_DIV6(&pllc1_div2_clk, FMSICKCR, 0),
[DIV6_FMSO] = SH_CLK_DIV6(&pllc1_div2_clk, FMSOCKCR, 0),
[DIV6_FSIA] = SH_CLK_DIV6(&pllc1_div2_clk, FSIACKCR, 0),
[DIV6_FSIB] = SH_CLK_DIV6(&pllc1_div2_clk, FSIBCKCR, 0),
[DIV6_SUB] = SH_CLK_DIV6(&sh7372_extal2_clk, SUBCKCR, 0),
[DIV6_SPU] = SH_CLK_DIV6(&pllc1_div2_clk, SPUCKCR, 0),
[DIV6_VOU] = SH_CLK_DIV6(&pllc1_div2_clk, VOUCKCR, 0),
[DIV6_DSIT] = SH_CLK_DIV6(&pllc1_div2_clk, DSITCKCR, 0),
[DIV6_DSI0P] = SH_CLK_DIV6(&pllc1_div2_clk, DSI0PCKCR, 0),
[DIV6_DSI1P] = SH_CLK_DIV6(&pllc1_div2_clk, DSI1PCKCR, 0),
};
enum { DIV6_HDMI, DIV6_REPARENT_NR };
/* Indices are important - they are the actual src selecting values */
static struct clk *hdmi_parent[] = {
[0] = &pllc1_div2_clk,
[1] = &pllc2_clk,
[2] = &dv_clki_clk,
[3] = NULL, /* pllc2_div4 not implemented yet */
};
static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
[DIV6_HDMI] = SH_CLK_DIV6_EXT(&pllc1_div2_clk, HDMICKCR, 0,
hdmi_parent, ARRAY_SIZE(hdmi_parent), 6, 2),
};
enum { MSTP001,
MSTP131, MSTP130,
MSTP129, MSTP128,
MSTP118, MSTP117, MSTP116,
MSTP106, MSTP101, MSTP100,
MSTP223,
MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
MSTP329, MSTP328, MSTP323, MSTP322, MSTP314, MSTP313, MSTP312,
MSTP415, MSTP413, MSTP411, MSTP410, MSTP406, MSTP403,
MSTP_NR };
#define MSTP(_parent, _reg, _bit, _flags) \
SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
static struct clk mstp_clks[MSTP_NR] = {
[MSTP001] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR0, 1, 0), /* IIC2 */
[MSTP131] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 31, 0), /* VEU3 */
[MSTP130] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 30, 0), /* VEU2 */
[MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* VEU1 */
[MSTP128] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 28, 0), /* VEU0 */
[MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX */
[MSTP117] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */
[MSTP116] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */
[MSTP106] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 6, 0), /* JPU */
[MSTP101] = MSTP(&div4_clks[DIV4_M1], SMSTPCR1, 1, 0), /* VPU */
[MSTP100] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
[MSTP223] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR2, 23, 0), /* SPU2 */
[MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
[MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
[MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
[MSTP203] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */
[MSTP202] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */
[MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
[MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
[MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
[MSTP328] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR3, 28, CLK_ENABLE_ON_INIT), /* FSIA */
[MSTP323] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
[MSTP322] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 22, 0), /* USB0 */
[MSTP314] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 14, 0), /* SDHI0 */
[MSTP313] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 13, 0), /* SDHI1 */
[MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMC */
[MSTP415] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 15, 0), /* SDHI2 */
[MSTP413] = MSTP(&pllc1_div2_clk, SMSTPCR4, 13, 0), /* HDMI */
[MSTP411] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 11, 0), /* IIC3 */
[MSTP410] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 10, 0), /* IIC4 */
[MSTP406] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 6, 0), /* USB1 */
[MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */
};
#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
static struct clk_lookup lookups[] = {
/* main clocks */
CLKDEV_CON_ID("dv_clki_div2_clk", &dv_clki_div2_clk),
CLKDEV_CON_ID("r_clk", &r_clk),
CLKDEV_CON_ID("extal1", &sh7372_extal1_clk),
CLKDEV_CON_ID("extal2", &sh7372_extal2_clk),
CLKDEV_CON_ID("extal1_div2_clk", &extal1_div2_clk),
CLKDEV_CON_ID("extal2_div2_clk", &extal2_div2_clk),
CLKDEV_CON_ID("extal2_div4_clk", &extal2_div4_clk),
CLKDEV_CON_ID("pllc0_clk", &pllc0_clk),
CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
CLKDEV_CON_ID("pllc2_clk", &pllc2_clk),
/* DIV4 clocks */
CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
CLKDEV_CON_ID("zg_clk", &div4_clks[DIV4_ZG]),
CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]),
CLKDEV_CON_ID("csir_clk", &div4_clks[DIV4_CSIR]),
CLKDEV_CON_ID("ztr_clk", &div4_clks[DIV4_ZTR]),
CLKDEV_CON_ID("zt_clk", &div4_clks[DIV4_ZT]),
CLKDEV_CON_ID("zx_clk", &div4_clks[DIV4_ZX]),
CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]),
CLKDEV_CON_ID("ispb_clk", &div4_clks[DIV4_ISPB]),
CLKDEV_CON_ID("s_clk", &div4_clks[DIV4_S]),
CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]),
CLKDEV_CON_ID("zb3_clk", &div4_clks[DIV4_ZB3]),
CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]),
CLKDEV_CON_ID("ddrp_clk", &div4_clks[DIV4_DDRP]),
/* DIV6 clocks */
CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]),
CLKDEV_CON_ID("fmsi_clk", &div6_clks[DIV6_FMSI]),
CLKDEV_CON_ID("fmso_clk", &div6_clks[DIV6_FMSO]),
CLKDEV_CON_ID("fsia_clk", &div6_clks[DIV6_FSIA]),
CLKDEV_CON_ID("fsib_clk", &div6_clks[DIV6_FSIB]),
CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]),
CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]),
CLKDEV_CON_ID("vou_clk", &div6_clks[DIV6_VOU]),
CLKDEV_CON_ID("hdmi_clk", &div6_reparent_clks[DIV6_HDMI]),
CLKDEV_CON_ID("dsit_clk", &div6_clks[DIV6_DSIT]),
CLKDEV_CON_ID("dsi0p_clk", &div6_clks[DIV6_DSI0P]),
CLKDEV_CON_ID("dsi1p_clk", &div6_clks[DIV6_DSI1P]),
/* MSTP32 clocks */
CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* IIC2 */
CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[MSTP131]), /* VEU3 */
CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[MSTP130]), /* VEU2 */
CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[MSTP129]), /* VEU1 */
CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[MSTP128]), /* VEU0 */
CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX */
CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]), /* LCDC1 */
CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* IIC0 */
CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[MSTP106]), /* JPU */
CLKDEV_DEV_ID("uio_pdrv_genirq.0", &mstp_clks[MSTP101]), /* VPU */
CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), /* LCDC0 */
CLKDEV_DEV_ID("uio_pdrv_genirq.6", &mstp_clks[MSTP223]), /* SPU2DSP0 */
CLKDEV_DEV_ID("uio_pdrv_genirq.7", &mstp_clks[MSTP223]), /* SPU2DSP1 */
CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP206]), /* SCIFB */
CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */
CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */
CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
CLKDEV_CON_ID("cmt1", &mstp_clks[MSTP329]), /* CMT10 */
CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI2 */
CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* IIC1 */
CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP323]), /* USB0 */
CLKDEV_DEV_ID("r8a66597_udc.0", &mstp_clks[MSTP323]), /* USB0 */
CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMC */
CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]), /* SDHI2 */
CLKDEV_DEV_ID("sh-mobile-hdmi", &mstp_clks[MSTP413]), /* HDMI */
CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* IIC3 */
CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* IIC4 */
CLKDEV_DEV_ID("r8a66597_hcd.1", &mstp_clks[MSTP406]), /* USB1 */
CLKDEV_DEV_ID("r8a66597_udc.1", &mstp_clks[MSTP406]), /* USB1 */
CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
{.con_id = "ick", .dev_id = "sh-mobile-hdmi", .clk = &div6_reparent_clks[DIV6_HDMI]},
};
void __init sh7372_clock_init(void)
{
int k, ret = 0;
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
ret = clk_register(main_clks[k]);
if (!ret)
ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
if (!ret)
ret = sh_clk_div6_register(div6_clks, DIV6_NR);
if (!ret)
ret = sh_clk_div6_reparent_register(div6_reparent_clks, DIV6_NR);
if (!ret)
ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
if (!ret)
clk_init();
else
panic("failed to setup sh7372 clocks\n");
}
arch/arm/mach-shmobile/clock-sh7377.c 0 → 100644
浏览文件 @ 500b9fc9
/*
* SH7377 clock framework support
*
* Copyright (C) 2010 Magnus Damm
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/sh_clk.h>
#include <mach/common.h>
#include <asm/clkdev.h>
/* SH7377 registers */
#define RTFRQCR 0xe6150000
#define SYFRQCR 0xe6150004
#define CMFRQCR 0xe61500E0
#define VCLKCR1 0xe6150008
#define VCLKCR2 0xe615000C
#define VCLKCR3 0xe615001C
#define FMSICKCR 0xe6150010
#define FMSOCKCR 0xe6150014
#define FSICKCR 0xe6150018
#define PLLC1CR 0xe6150028
#define PLLC2CR 0xe615002C
#define SUBUSBCKCR 0xe6150080
#define SPUCKCR 0xe6150084
#define MSUCKCR 0xe6150088
#define MVI3CKCR 0xe6150090
#define HDMICKCR 0xe6150094
#define MFCK1CR 0xe6150098
#define MFCK2CR 0xe615009C
#define DSITCKCR 0xe6150060
#define DSIPCKCR 0xe6150064
#define SMSTPCR0 0xe6150130
#define SMSTPCR1 0xe6150134
#define SMSTPCR2 0xe6150138
#define SMSTPCR3 0xe615013C
#define SMSTPCR4 0xe6150140
/* Fixed 32 KHz root clock from EXTALR pin */
static struct clk r_clk = {
.rate = 32768,
};
/*
* 26MHz default rate for the EXTALC1 root input clock.
* If needed, reset this with clk_set_rate() from the platform code.
*/
struct clk sh7377_extalc1_clk = {
.rate = 26666666,
};
/*
* 48MHz default rate for the EXTAL2 root input clock.
* If needed, reset this with clk_set_rate() from the platform code.
*/
struct clk sh7377_extal2_clk = {
.rate = 48000000,
};
/* A fixed divide-by-2 block */
static unsigned long div2_recalc(struct clk *clk)
{
return clk->parent->rate / 2;
}
static struct clk_ops div2_clk_ops = {
.recalc = div2_recalc,
};
/* Divide extalc1 by two */
static struct clk extalc1_div2_clk = {
.ops = &div2_clk_ops,
.parent = &sh7377_extalc1_clk,
};
/* Divide extal2 by two */
static struct clk extal2_div2_clk = {
.ops = &div2_clk_ops,
.parent = &sh7377_extal2_clk,
};
/* Divide extal2 by four */
static struct clk extal2_div4_clk = {
.ops = &div2_clk_ops,
.parent = &extal2_div2_clk,
};
/* PLLC1 */
static unsigned long pllc1_recalc(struct clk *clk)
{
unsigned long mult = 1;
if (__raw_readl(PLLC1CR) & (1 << 14))
mult = (((__raw_readl(RTFRQCR) >> 24) & 0x3f) + 1) * 2;
return clk->parent->rate * mult;
}
static struct clk_ops pllc1_clk_ops = {
.recalc = pllc1_recalc,
};
static struct clk pllc1_clk = {
.ops = &pllc1_clk_ops,
.flags = CLK_ENABLE_ON_INIT,
.parent = &extalc1_div2_clk,
};
/* Divide PLLC1 by two */
static struct clk pllc1_div2_clk = {
.ops = &div2_clk_ops,
.parent = &pllc1_clk,
};
/* PLLC2 */
static unsigned long pllc2_recalc(struct clk *clk)
{
unsigned long mult = 1;
if (__raw_readl(PLLC2CR) & (1 << 31))
mult = (((__raw_readl(PLLC2CR) >> 24) & 0x3f) + 1) * 2;
return clk->parent->rate * mult;
}
static struct clk_ops pllc2_clk_ops = {
.recalc = pllc2_recalc,
};
static struct clk pllc2_clk = {
.ops = &pllc2_clk_ops,
.flags = CLK_ENABLE_ON_INIT,
.parent = &extalc1_div2_clk,
};
static struct clk *main_clks[] = {
&r_clk,
&sh7377_extalc1_clk,
&sh7377_extal2_clk,
&extalc1_div2_clk,
&extal2_div2_clk,
&extal2_div4_clk,
&pllc1_clk,
&pllc1_div2_clk,
&pllc2_clk,
};
static void div4_kick(struct clk *clk)
{
unsigned long value;
/* set KICK bit in SYFRQCR to update hardware setting */
value = __raw_readl(SYFRQCR);
value |= (1 << 31);
__raw_writel(value, SYFRQCR);
}
static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
24, 32, 36, 48, 0, 72, 96, 0 };
static struct clk_div_mult_table div4_div_mult_table = {
.divisors = divisors,
.nr_divisors = ARRAY_SIZE(divisors),
};
static struct clk_div4_table div4_table = {
.div_mult_table = &div4_div_mult_table,
.kick = div4_kick,
};
enum { DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_CSIR,
DIV4_ZTR, DIV4_ZT, DIV4_Z, DIV4_HP,
DIV4_ZS, DIV4_ZB, DIV4_ZB3, DIV4_CP, DIV4_NR };
#define DIV4(_reg, _bit, _mask, _flags) \
SH_CLK_DIV4(&pllc1_clk, _reg, _bit, _mask, _flags)
static struct clk div4_clks[DIV4_NR] = {
[DIV4_I] = DIV4(RTFRQCR, 20, 0x6fff, CLK_ENABLE_ON_INIT),
[DIV4_ZG] = DIV4(RTFRQCR, 16, 0x6fff, CLK_ENABLE_ON_INIT),
[DIV4_B] = DIV4(RTFRQCR, 8, 0x6fff, CLK_ENABLE_ON_INIT),
[DIV4_M1] = DIV4(RTFRQCR, 4, 0x6fff, CLK_ENABLE_ON_INIT),
[DIV4_CSIR] = DIV4(RTFRQCR, 0, 0x6fff, 0),
[DIV4_ZTR] = DIV4(SYFRQCR, 20, 0x6fff, 0),
[DIV4_ZT] = DIV4(SYFRQCR, 16, 0x6fff, 0),
[DIV4_Z] = DIV4(SYFRQCR, 12, 0x6fff, 0),
[DIV4_HP] = DIV4(SYFRQCR, 4, 0x6fff, 0),
[DIV4_ZS] = DIV4(CMFRQCR, 12, 0x6fff, 0),
[DIV4_ZB] = DIV4(CMFRQCR, 8, 0x6fff, 0),
[DIV4_ZB3] = DIV4(CMFRQCR, 4, 0x6fff, 0),
[DIV4_CP] = DIV4(CMFRQCR, 0, 0x6fff, 0),
};
enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_FMSI, DIV6_FMSO,
DIV6_FSI, DIV6_SUB, DIV6_SPU, DIV6_MSU, DIV6_MVI3, DIV6_HDMI,
DIV6_MF1, DIV6_MF2, DIV6_DSIT, DIV6_DSIP,
DIV6_NR };
static struct clk div6_clks[] = {
[DIV6_VCK1] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR1, 0),
[DIV6_VCK2] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR2, 0),
[DIV6_VCK3] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR3, 0),
[DIV6_FMSI] = SH_CLK_DIV6(&pllc1_div2_clk, FMSICKCR, 0),
[DIV6_FMSO] = SH_CLK_DIV6(&pllc1_div2_clk, FMSOCKCR, 0),
[DIV6_FSI] = SH_CLK_DIV6(&pllc1_div2_clk, FSICKCR, 0),
[DIV6_SUB] = SH_CLK_DIV6(&sh7377_extal2_clk, SUBUSBCKCR, 0),
[DIV6_SPU] = SH_CLK_DIV6(&pllc1_div2_clk, SPUCKCR, 0),
[DIV6_MSU] = SH_CLK_DIV6(&pllc1_div2_clk, MSUCKCR, 0),
[DIV6_MVI3] = SH_CLK_DIV6(&pllc1_div2_clk, MVI3CKCR, 0),
[DIV6_HDMI] = SH_CLK_DIV6(&pllc1_div2_clk, HDMICKCR, 0),
[DIV6_MF1] = SH_CLK_DIV6(&pllc1_div2_clk, MFCK1CR, 0),
[DIV6_MF2] = SH_CLK_DIV6(&pllc1_div2_clk, MFCK2CR, 0),
[DIV6_DSIT] = SH_CLK_DIV6(&pllc1_div2_clk, DSITCKCR, 0),
[DIV6_DSIP] = SH_CLK_DIV6(&pllc1_div2_clk, DSIPCKCR, 0),
};
enum { MSTP001,
MSTP131, MSTP130, MSTP129, MSTP128, MSTP116, MSTP106, MSTP101,
MSTP223, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
MSTP331, MSTP329, MSTP325, MSTP323, MSTP322,
MSTP315, MSTP314, MSTP313,
MSTP403,
MSTP_NR };
#define MSTP(_parent, _reg, _bit, _flags) \
SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
static struct clk mstp_clks[] = {
[MSTP001] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR0, 1, 0), /* IIC2 */
[MSTP131] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 31, 0), /* VEU3 */
[MSTP130] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 30, 0), /* VEU2 */
[MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* VEU1 */
[MSTP128] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 28, 0), /* VEU0 */
[MSTP116] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */
[MSTP106] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 6, 0), /* JPU */
[MSTP101] = MSTP(&div4_clks[DIV4_M1], SMSTPCR1, 1, 0), /* VPU */
[MSTP223] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR2, 23, 0), /* SPU2 */
[MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
[MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
[MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
[MSTP203] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */
[MSTP202] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */
[MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
[MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
[MSTP331] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 31, 0), /* SCIFA6 */
[MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
[MSTP325] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 25, 0), /* IRDA */
[MSTP323] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
[MSTP322] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 22, 0), /* USB0 */
[MSTP315] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 15, 0), /* FLCTL */
[MSTP314] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 14, 0), /* SDHI0 */
[MSTP313] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 13, 0), /* SDHI1 */
[MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */
};
#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
static struct clk_lookup lookups[] = {
/* main clocks */
CLKDEV_CON_ID("r_clk", &r_clk),
CLKDEV_CON_ID("extalc1", &sh7377_extalc1_clk),
CLKDEV_CON_ID("extal2", &sh7377_extal2_clk),
CLKDEV_CON_ID("extalc1_div2_clk", &extalc1_div2_clk),
CLKDEV_CON_ID("extal2_div2_clk", &extal2_div2_clk),
CLKDEV_CON_ID("extal2_div4_clk", &extal2_div4_clk),
CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
CLKDEV_CON_ID("pllc2_clk", &pllc2_clk),
/* DIV4 clocks */
CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
CLKDEV_CON_ID("zg_clk", &div4_clks[DIV4_ZG]),
CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]),
CLKDEV_CON_ID("csir_clk", &div4_clks[DIV4_CSIR]),
CLKDEV_CON_ID("ztr_clk", &div4_clks[DIV4_ZTR]),
CLKDEV_CON_ID("zt_clk", &div4_clks[DIV4_ZT]),
CLKDEV_CON_ID("z_clk", &div4_clks[DIV4_Z]),
CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]),
CLKDEV_CON_ID("zs_clk", &div4_clks[DIV4_ZS]),
CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]),
CLKDEV_CON_ID("zb3_clk", &div4_clks[DIV4_ZB3]),
CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]),
/* DIV6 clocks */
CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]),
CLKDEV_CON_ID("fmsi_clk", &div6_clks[DIV6_FMSI]),
CLKDEV_CON_ID("fmso_clk", &div6_clks[DIV6_FMSO]),
CLKDEV_CON_ID("fsi_clk", &div6_clks[DIV6_FSI]),
CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]),
CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]),
CLKDEV_CON_ID("msu_clk", &div6_clks[DIV6_MSU]),
CLKDEV_CON_ID("mvi3_clk", &div6_clks[DIV6_MVI3]),
CLKDEV_CON_ID("hdmi_clk", &div6_clks[DIV6_HDMI]),
CLKDEV_CON_ID("mf1_clk", &div6_clks[DIV6_MF1]),
CLKDEV_CON_ID("mf2_clk", &div6_clks[DIV6_MF2]),
CLKDEV_CON_ID("dsit_clk", &div6_clks[DIV6_DSIT]),
CLKDEV_CON_ID("dsip_clk", &div6_clks[DIV6_DSIP]),
/* MSTP32 clocks */
CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* IIC2 */
CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[MSTP131]), /* VEU3 */
CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[MSTP130]), /* VEU2 */
CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[MSTP129]), /* VEU1 */
CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[MSTP128]), /* VEU0 */
CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* IIC0 */
CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[MSTP106]), /* JPU */
CLKDEV_DEV_ID("uio_pdrv_genirq.0", &mstp_clks[MSTP101]), /* VPU */
CLKDEV_DEV_ID("uio_pdrv_genirq.6", &mstp_clks[MSTP223]), /* SPU2DSP0 */
CLKDEV_DEV_ID("uio_pdrv_genirq.7", &mstp_clks[MSTP223]), /* SPU2DSP1 */
CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP206]), /* SCIFB */
CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */
CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */
CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */
CLKDEV_CON_ID("cmt1", &mstp_clks[MSTP329]), /* CMT10 */
CLKDEV_DEV_ID("sh_irda", &mstp_clks[MSTP325]), /* IRDA */
CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* IIC1 */
CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP322]), /* USBHS */
CLKDEV_DEV_ID("r8a66597_udc.0", &mstp_clks[MSTP322]), /* USBHS */
CLKDEV_DEV_ID("sh_flctl", &mstp_clks[MSTP315]), /* FLCTL */
CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
};
void __init sh7377_clock_init(void)
{
int k, ret = 0;
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
ret = clk_register(main_clks[k]);
if (!ret)
ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
if (!ret)
ret = sh_clk_div6_register(div6_clks, DIV6_NR);
if (!ret)
ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
if (!ret)
clk_init();
else
panic("failed to setup sh7377 clocks\n");
}
arch/arm/mach-shmobile/clock.c 0 → 100644
浏览文件 @ 500b9fc9
/*
* SH-Mobile Timer
*
* Copyright (C) 2010 Magnus Damm
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/sh_clk.h>
int __init clk_init(void)
{
/* Kick the child clocks.. */
recalculate_root_clocks();
/* Enable the necessary init clocks */
clk_enable_init_clocks();
return 0;
}
int __clk_get(struct clk *clk)
{
return 1;
}
EXPORT_SYMBOL(__clk_get);
void __clk_put(struct clk *clk)
{
}
EXPORT_SYMBOL(__clk_put);
arch/arm/mach-shmobile/include/mach/common.h
浏览文件 @ 500b9fc9
...@@ -3,21 +3,31 @@ ...@@ -3,21 +3,31 @@
extern struct sys_timer shmobile_timer; extern struct sys_timer shmobile_timer;
extern void shmobile_setup_console(void); extern void shmobile_setup_console(void);
struct clk;
extern int clk_init(void);
extern void sh7367_init_irq(void); extern void sh7367_init_irq(void);
extern void sh7367_add_early_devices(void); extern void sh7367_add_early_devices(void);
extern void sh7367_add_standard_devices(void); extern void sh7367_add_standard_devices(void);
extern void sh7367_clock_init(void); extern void sh7367_clock_init(void);
extern void sh7367_pinmux_init(void); extern void sh7367_pinmux_init(void);
extern struct clk sh7367_extalb1_clk;
extern struct clk sh7367_extal2_clk;
extern void sh7377_init_irq(void); extern void sh7377_init_irq(void);
extern void sh7377_add_early_devices(void); extern void sh7377_add_early_devices(void);
extern void sh7377_add_standard_devices(void); extern void sh7377_add_standard_devices(void);
extern void sh7377_clock_init(void);
extern void sh7377_pinmux_init(void); extern void sh7377_pinmux_init(void);
extern struct clk sh7377_extalc1_clk;
extern struct clk sh7377_extal2_clk;
extern void sh7372_init_irq(void); extern void sh7372_init_irq(void);
extern void sh7372_add_early_devices(void); extern void sh7372_add_early_devices(void);
extern void sh7372_add_standard_devices(void); extern void sh7372_add_standard_devices(void);
extern void sh7372_clock_init(void);
extern void sh7372_pinmux_init(void); extern void sh7372_pinmux_init(void);
extern struct clk sh7372_extal1_clk;
extern struct clk sh7372_extal2_clk;
#endif /* __ARCH_MACH_COMMON_H */ #endif /* __ARCH_MACH_COMMON_H */
arch/arm/mach-shmobile/include/mach/irqs.h
浏览文件 @ 500b9fc9
...@@ -3,7 +3,13 @@ ...@@ -3,7 +3,13 @@
#define NR_IRQS 512 #define NR_IRQS 512
/* INTCA */
#define evt2irq(evt) (((evt) >> 5) - 16) #define evt2irq(evt) (((evt) >> 5) - 16)
#define irq2evt(irq) (((irq) + 16) << 5) #define irq2evt(irq) (((irq) + 16) << 5)
/* INTCS */
#define INTCS_VECT_BASE 0x2200
#define INTCS_VECT(n, vect) INTC_VECT((n), INTCS_VECT_BASE + (vect))
#define intcs_evt2irq(evt) evt2irq(INTCS_VECT_BASE + (evt))
#endif /* __ASM_MACH_IRQS_H */ #endif /* __ASM_MACH_IRQS_H */
arch/arm/mach-shmobile/include/mach/memory.h
浏览文件 @ 500b9fc9
...@@ -4,4 +4,7 @@ ...@@ -4,4 +4,7 @@
#define PHYS_OFFSET UL(CONFIG_MEMORY_START) #define PHYS_OFFSET UL(CONFIG_MEMORY_START)
#define MEM_SIZE UL(CONFIG_MEMORY_SIZE) #define MEM_SIZE UL(CONFIG_MEMORY_SIZE)
/* DMA memory at 0xf6000000 - 0xffdfffff */
#define CONSISTENT_DMA_SIZE (158 << 20)
#endif /* __ASM_MACH_MEMORY_H */ #endif /* __ASM_MACH_MEMORY_H */
arch/arm/mach-shmobile/include/mach/sh7372.h
浏览文件 @ 500b9fc9
...@@ -11,6 +11,8 @@ ...@@ -11,6 +11,8 @@
#ifndef __ASM_SH7372_H__ #ifndef __ASM_SH7372_H__
#define __ASM_SH7372_H__ #define __ASM_SH7372_H__
#include <linux/sh_clk.h>
/* /*
* Pin Function Controller: * Pin Function Controller:
* GPIO_FN_xx - GPIO used to select pin function * GPIO_FN_xx - GPIO used to select pin function
...@@ -431,4 +433,32 @@ enum { ...@@ -431,4 +433,32 @@ enum {
GPIO_FN_SDENC_DV_CLKI, GPIO_FN_SDENC_DV_CLKI,
}; };
/* DMA slave IDs */
enum {
SHDMA_SLAVE_SCIF0_TX,
SHDMA_SLAVE_SCIF0_RX,
SHDMA_SLAVE_SCIF1_TX,
SHDMA_SLAVE_SCIF1_RX,
SHDMA_SLAVE_SCIF2_TX,
SHDMA_SLAVE_SCIF2_RX,
SHDMA_SLAVE_SCIF3_TX,
SHDMA_SLAVE_SCIF3_RX,
SHDMA_SLAVE_SCIF4_TX,
SHDMA_SLAVE_SCIF4_RX,
SHDMA_SLAVE_SCIF5_TX,
SHDMA_SLAVE_SCIF5_RX,
SHDMA_SLAVE_SCIF6_TX,
SHDMA_SLAVE_SCIF6_RX,
SHDMA_SLAVE_SDHI0_RX,
SHDMA_SLAVE_SDHI0_TX,
SHDMA_SLAVE_SDHI1_RX,
SHDMA_SLAVE_SDHI1_TX,
SHDMA_SLAVE_SDHI2_RX,
SHDMA_SLAVE_SDHI2_TX,
};
extern struct clk dv_clki_clk;
extern struct clk dv_clki_div2_clk;
extern struct clk pllc2_clk;
#endif /* __ASM_SH7372_H__ */ #endif /* __ASM_SH7372_H__ */
arch/arm/mach-shmobile/include/mach/vmalloc.h
浏览文件 @ 500b9fc9
#ifndef __ASM_MACH_VMALLOC_H #ifndef __ASM_MACH_VMALLOC_H
#define __ASM_MACH_VMALLOC_H #define __ASM_MACH_VMALLOC_H
#define VMALLOC_END (PAGE_OFFSET + 0x24000000) /* Vmalloc at ... - 0xe5ffffff */
#define VMALLOC_END 0xe6000000
#endif /* __ASM_MACH_VMALLOC_H */ #endif /* __ASM_MACH_VMALLOC_H */
arch/arm/mach-shmobile/intc-sh7367.c
浏览文件 @ 500b9fc9
...@@ -75,7 +75,7 @@ enum { ...@@ -75,7 +75,7 @@ enum {
ETM11, ARM11, USBHS, FLCTL, IIC1 ETM11, ARM11, USBHS, FLCTL, IIC1
}; };
static struct intc_vect intca_vectors[] = { static struct intc_vect intca_vectors[] __initdata = {
INTC_VECT(IRQ0A, 0x0200), INTC_VECT(IRQ1A, 0x0220), INTC_VECT(IRQ0A, 0x0200), INTC_VECT(IRQ1A, 0x0220),
INTC_VECT(IRQ2A, 0x0240), INTC_VECT(IRQ3A, 0x0260), INTC_VECT(IRQ2A, 0x0240), INTC_VECT(IRQ3A, 0x0260),
INTC_VECT(IRQ4A, 0x0280), INTC_VECT(IRQ5A, 0x02a0), INTC_VECT(IRQ4A, 0x0280), INTC_VECT(IRQ5A, 0x02a0),
...@@ -162,7 +162,7 @@ static struct intc_group intca_groups[] __initdata = { ...@@ -162,7 +162,7 @@ static struct intc_group intca_groups[] __initdata = {
INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1), INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1),
}; };
static struct intc_mask_reg intca_mask_registers[] = { static struct intc_mask_reg intca_mask_registers[] __initdata = {
{ 0xe6900040, 0xe6900060, 8, /* INTMSK00A / INTMSKCLR00A */ { 0xe6900040, 0xe6900060, 8, /* INTMSK00A / INTMSKCLR00A */
{ IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
{ 0xe6900044, 0xe6900064, 8, /* INTMSK10A / INTMSKCLR10A */ { 0xe6900044, 0xe6900064, 8, /* INTMSK10A / INTMSKCLR10A */
...@@ -211,7 +211,7 @@ static struct intc_mask_reg intca_mask_registers[] = { ...@@ -211,7 +211,7 @@ static struct intc_mask_reg intca_mask_registers[] = {
MISTY, CMT3, RWDT1, RWDT0 } }, MISTY, CMT3, RWDT1, RWDT0 } },
}; };
static struct intc_prio_reg intca_prio_registers[] = { static struct intc_prio_reg intca_prio_registers[] __initdata = {
{ 0xe6900010, 0, 32, 4, /* INTPRI00A */ { 0xe6900010, 0, 32, 4, /* INTPRI00A */
{ IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
{ 0xe6900014, 0, 32, 4, /* INTPRI10A */ { 0xe6900014, 0, 32, 4, /* INTPRI10A */
...@@ -263,8 +263,178 @@ static struct intc_desc intca_desc __initdata = { ...@@ -263,8 +263,178 @@ static struct intc_desc intca_desc __initdata = {
intca_sense_registers, intca_ack_registers), intca_sense_registers, intca_ack_registers),
}; };
enum {
UNUSED_INTCS = 0,
INTCS,
/* interrupt sources INTCS */
VIO2_VEU0, VIO2_VEU1, VIO2_VEU2, VIO2_VEU3,
VIO3_VOU,
RTDMAC_1_DEI0, RTDMAC_1_DEI1, RTDMAC_1_DEI2, RTDMAC_1_DEI3,
VIO1_CEU, VIO1_BEU0, VIO1_BEU1, VIO1_BEU2,
VPU,
SGX530,
_2DDMAC_2DDM0, _2DDMAC_2DDM1, _2DDMAC_2DDM2, _2DDMAC_2DDM3,
IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2,
IPMMU_IPMMUB, IPMMU_IPMMUS,
RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR,
MSIOF,
IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0,
TMU_TUNI0, TMU_TUNI1, TMU_TUNI2,
CMT,
TSIF,
IPMMUI,
MVI3,
ICB,
PEP,
ASA,
BEM,
VE2HO,
HQE,
JPEG,
LCDC,
/* interrupt groups INTCS */
_2DDMAC, RTDMAC_1, RTDMAC_2, VEU, BEU, IIC0, IPMMU, IIC2,
};
static struct intc_vect intcs_vectors[] = {
INTCS_VECT(VIO2_VEU0, 0x700), INTCS_VECT(VIO2_VEU1, 0x720),
INTCS_VECT(VIO2_VEU2, 0x740), INTCS_VECT(VIO2_VEU3, 0x760),
INTCS_VECT(VIO3_VOU, 0x780),
INTCS_VECT(RTDMAC_1_DEI0, 0x800), INTCS_VECT(RTDMAC_1_DEI1, 0x820),
INTCS_VECT(RTDMAC_1_DEI2, 0x840), INTCS_VECT(RTDMAC_1_DEI3, 0x860),
INTCS_VECT(VIO1_CEU, 0x880), INTCS_VECT(VIO1_BEU0, 0x8a0),
INTCS_VECT(VIO1_BEU1, 0x8c0), INTCS_VECT(VIO1_BEU2, 0x8e0),
INTCS_VECT(VPU, 0x980),
INTCS_VECT(SGX530, 0x9e0),
INTCS_VECT(_2DDMAC_2DDM0, 0xa00), INTCS_VECT(_2DDMAC_2DDM1, 0xa20),
INTCS_VECT(_2DDMAC_2DDM2, 0xa40), INTCS_VECT(_2DDMAC_2DDM3, 0xa60),
INTCS_VECT(IIC2_ALI2, 0xa80), INTCS_VECT(IIC2_TACKI2, 0xaa0),
INTCS_VECT(IIC2_WAITI2, 0xac0), INTCS_VECT(IIC2_DTEI2, 0xae0),
INTCS_VECT(IPMMU_IPMMUB, 0xb20), INTCS_VECT(IPMMU_IPMMUS, 0xb60),
INTCS_VECT(RTDMAC_2_DEI4, 0xb80), INTCS_VECT(RTDMAC_2_DEI5, 0xba0),
INTCS_VECT(RTDMAC_2_DADERR, 0xbc0),
INTCS_VECT(MSIOF, 0xd20),
INTCS_VECT(IIC0_ALI0, 0xe00), INTCS_VECT(IIC0_TACKI0, 0xe20),
INTCS_VECT(IIC0_WAITI0, 0xe40), INTCS_VECT(IIC0_DTEI0, 0xe60),
INTCS_VECT(TMU_TUNI0, 0xe80), INTCS_VECT(TMU_TUNI1, 0xea0),
INTCS_VECT(TMU_TUNI2, 0xec0),
INTCS_VECT(CMT, 0xf00),
INTCS_VECT(TSIF, 0xf20),
INTCS_VECT(IPMMUI, 0xf60),
INTCS_VECT(MVI3, 0x420),
INTCS_VECT(ICB, 0x480),
INTCS_VECT(PEP, 0x4a0),
INTCS_VECT(ASA, 0x4c0),
INTCS_VECT(BEM, 0x4e0),
INTCS_VECT(VE2HO, 0x520),
INTCS_VECT(HQE, 0x540),
INTCS_VECT(JPEG, 0x560),
INTCS_VECT(LCDC, 0x580),
INTC_VECT(INTCS, 0xf80),
};
static struct intc_group intcs_groups[] __initdata = {
INTC_GROUP(_2DDMAC, _2DDMAC_2DDM0, _2DDMAC_2DDM1,
_2DDMAC_2DDM2, _2DDMAC_2DDM3),
INTC_GROUP(RTDMAC_1, RTDMAC_1_DEI0, RTDMAC_1_DEI1,
RTDMAC_1_DEI2, RTDMAC_1_DEI3),
INTC_GROUP(RTDMAC_2, RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR),
INTC_GROUP(VEU, VIO2_VEU0, VIO2_VEU1, VIO2_VEU2, VIO2_VEU3),
INTC_GROUP(BEU, VIO1_BEU0, VIO1_BEU1, VIO1_BEU2),
INTC_GROUP(IIC0, IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0),
INTC_GROUP(IPMMU, IPMMU_IPMMUS, IPMMU_IPMMUB),
INTC_GROUP(IIC2, IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2),
};
static struct intc_mask_reg intcs_mask_registers[] = {
{ 0xffd20184, 0xffd201c4, 8, /* IMR1SA / IMCR1SA */
{ VIO1_BEU2, VIO1_BEU1, VIO1_BEU0, VIO1_CEU,
VIO2_VEU3, VIO2_VEU2, VIO2_VEU1, VIO2_VEU0 } },
{ 0xffd20188, 0xffd201c8, 8, /* IMR2SA / IMCR2SA */
{ VIO3_VOU, 0, VE2HO, VPU,
0, 0, 0, 0 } },
{ 0xffd2018c, 0xffd201cc, 8, /* IMR3SA / IMCR3SA */
{ _2DDMAC_2DDM3, _2DDMAC_2DDM2, _2DDMAC_2DDM1, _2DDMAC_2DDM0,
BEM, ASA, PEP, ICB } },
{ 0xffd20190, 0xffd201d0, 8, /* IMR4SA / IMCR4SA */
{ 0, 0, MVI3, 0,
JPEG, HQE, 0, LCDC } },
{ 0xffd20194, 0xffd201d4, 8, /* IMR5SA / IMCR5SA */
{ 0, RTDMAC_2_DADERR, RTDMAC_2_DEI5, RTDMAC_2_DEI4,
RTDMAC_1_DEI3, RTDMAC_1_DEI2, RTDMAC_1_DEI1, RTDMAC_1_DEI0 } },
{ 0xffd20198, 0xffd201d8, 8, /* IMR6SA / IMCR6SA */
{ 0, 0, MSIOF, 0,
SGX530, 0, 0, 0 } },
{ 0xffd2019c, 0xffd201dc, 8, /* IMR7SA / IMCR7SA */
{ 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0,
0, 0, 0, 0 } },
{ 0xffd201a4, 0xffd201e4, 8, /* IMR9SA / IMCR9SA */
{ 0, 0, 0, CMT,
IIC2_DTEI2, IIC2_WAITI2, IIC2_TACKI2, IIC2_ALI2 } },
{ 0xffd201a8, 0xffd201e8, 8, /* IMR10SA / IMCR10SA */
{ IPMMU_IPMMUS, 0, IPMMU_IPMMUB, 0,
0, 0, 0, 0 } },
{ 0xffd201ac, 0xffd201ec, 8, /* IMR11SA / IMCR11SA */
{ IIC0_DTEI0, IIC0_WAITI0, IIC0_TACKI0, IIC0_ALI0,
0, 0, IPMMUI, TSIF } },
{ 0xffd20104, 0, 16, /* INTAMASK */
{ 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, INTCS } },
};
/* Priority is needed for INTCA to receive the INTCS interrupt */
static struct intc_prio_reg intcs_prio_registers[] = {
{ 0xffd20000, 0, 16, 4, /* IPRAS */ { 0, MVI3, _2DDMAC, ICB } },
{ 0xffd20004, 0, 16, 4, /* IPRBS */ { JPEG, LCDC, 0, 0 } },
{ 0xffd20008, 0, 16, 4, /* IPRCS */ { BBIF2, 0, 0, 0 } },
{ 0xffd20010, 0, 16, 4, /* IPRES */ { RTDMAC_1, VIO1_CEU, 0, VPU } },
{ 0xffd20014, 0, 16, 4, /* IPRFS */ { 0, RTDMAC_2, 0, CMT } },
{ 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU_TUNI0, TMU_TUNI1,
TMU_TUNI2, 0 } },
{ 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, VIO3_VOU, VEU, BEU } },
{ 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, MSIOF, TSIF, IIC0 } },
{ 0xffd20024, 0, 16, 4, /* IPRJS */ { 0, SGX530, 0, 0 } },
{ 0xffd20028, 0, 16, 4, /* IPRKS */ { BEM, ASA, IPMMUI, PEP } },
{ 0xffd2002c, 0, 16, 4, /* IPRLS */ { IPMMU, 0, VE2HO, HQE } },
{ 0xffd20030, 0, 16, 4, /* IPRMS */ { IIC2, 0, 0, 0 } },
};
static struct resource intcs_resources[] __initdata = {
[0] = {
.start = 0xffd20000,
.end = 0xffd2ffff,
.flags = IORESOURCE_MEM,
}
};
static struct intc_desc intcs_desc __initdata = {
.name = "sh7367-intcs",
.resource = intcs_resources,
.num_resources = ARRAY_SIZE(intcs_resources),
.hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers,
intcs_prio_registers, NULL, NULL),
};
static void intcs_demux(unsigned int irq, struct irq_desc *desc)
{
void __iomem *reg = (void *)get_irq_data(irq);
unsigned int evtcodeas = ioread32(reg);
generic_handle_irq(intcs_evt2irq(evtcodeas));
}
void __init sh7367_init_irq(void) void __init sh7367_init_irq(void)
{ {
/* INTCA */ void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
register_intc_controller(&intca_desc); register_intc_controller(&intca_desc);
register_intc_controller(&intcs_desc);
/* demux using INTEVTSA */
set_irq_data(evt2irq(0xf80), (void *)intevtsa);
set_irq_chained_handler(evt2irq(0xf80), intcs_demux);
} }
arch/arm/mach-shmobile/intc-sh7372.c
浏览文件 @ 500b9fc9
...@@ -319,17 +319,17 @@ static struct intc_prio_reg intca_prio_registers[] __initdata = { ...@@ -319,17 +319,17 @@ static struct intc_prio_reg intca_prio_registers[] __initdata = {
{ 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } }, { 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } },
{ 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S, { 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S,
CMT14, CMT15 } }, CMT14, CMT15 } },
{ 0xe694003c, 0, 16, 4, /* IPRPA3 */ { 0, 0, { 0xe695003c, 0, 16, 4, /* IPRPA3 */ { 0, 0,
MMC_MMC_ERR, MMC_MMC_NOR } }, MMC_MMC_ERR, MMC_MMC_NOR } },
{ 0xe6940040, 0, 16, 4, /* IPRQA3 */ { IIC4_ALI4, IIC4_TACKI4, { 0xe6950040, 0, 16, 4, /* IPRQA3 */ { IIC4_ALI4, IIC4_TACKI4,
IIC4_WAITI4, IIC4_DTEI4 } }, IIC4_WAITI4, IIC4_DTEI4 } },
{ 0xe6940044, 0, 16, 4, /* IPRRA3 */ { IIC3_ALI3, IIC3_TACKI3, { 0xe6950044, 0, 16, 4, /* IPRRA3 */ { IIC3_ALI3, IIC3_TACKI3,
IIC3_WAITI3, IIC3_DTEI3 } }, IIC3_WAITI3, IIC3_DTEI3 } },
{ 0xe6940048, 0, 16, 4, /* IPRSA3 */ { 0/*ERI*/, 0/*RXI*/, { 0xe6950048, 0, 16, 4, /* IPRSA3 */ { 0/*ERI*/, 0/*RXI*/,
0/*TXI*/, 0/*TEI*/} }, 0/*TXI*/, 0/*TEI*/} },
{ 0xe694004c, 0, 16, 4, /* IPRTA3 */ { USB0_USB0I1, USB0_USB0I0, { 0xe695004c, 0, 16, 4, /* IPRTA3 */ { USB0_USB0I1, USB0_USB0I0,
USB1_USB1I1, USB1_USB1I0 } }, USB1_USB1I1, USB1_USB1I0 } },
{ 0xe6940050, 0, 16, 4, /* IPRUA3 */ { USBHSDMAC1_USHDMI, 0, 0, 0 } }, { 0xe6950050, 0, 16, 4, /* IPRUA3 */ { USBHSDMAC1_USHDMI, 0, 0, 0 } },
}; };
static struct intc_sense_reg intca_sense_registers[] __initdata = { static struct intc_sense_reg intca_sense_registers[] __initdata = {
...@@ -363,7 +363,227 @@ static struct intc_desc intca_desc __initdata = { ...@@ -363,7 +363,227 @@ static struct intc_desc intca_desc __initdata = {
intca_sense_registers, intca_ack_registers), intca_sense_registers, intca_ack_registers),
}; };
enum {
UNUSED_INTCS = 0,
INTCS,
/* interrupt sources INTCS */
VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3,
RTDMAC_1_DEI0, RTDMAC_1_DEI1, RTDMAC_1_DEI2, RTDMAC_1_DEI3,
CEU, BEU_BEU0, BEU_BEU1, BEU_BEU2,
VPU,
TSIF1,
_3DG_SGX530,
_2DDMAC,
IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2,
IPMMU_IPMMUR, IPMMU_IPMMUR2,
RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR,
MSIOF,
IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0,
TMU_TUNI0, TMU_TUNI1, TMU_TUNI2,
CMT0,
TSIF0,
LMB,
CTI,
ICB,
JPU_JPEG,
LCDC,
LCRC,
RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, RTDMAC2_1_DEI2, RTDMAC2_1_DEI3,
RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR,
ISP,
LCDC1,
CSIRX,
DSITX_DSITX0,
DSITX_DSITX1,
TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2,
CMT4,
DSITX1_DSITX1_0,
DSITX1_DSITX1_1,
CPORTS2R,
JPU6E,
/* interrupt groups INTCS */
RTDMAC_1, RTDMAC_2, VEU, BEU, IIC0, IPMMU, IIC2,
RTDMAC2_1, RTDMAC2_2, TMU1, DSITX,
};
static struct intc_vect intcs_vectors[] = {
INTCS_VECT(VEU_VEU0, 0x700), INTCS_VECT(VEU_VEU1, 0x720),
INTCS_VECT(VEU_VEU2, 0x740), INTCS_VECT(VEU_VEU3, 0x760),
INTCS_VECT(RTDMAC_1_DEI0, 0x800), INTCS_VECT(RTDMAC_1_DEI1, 0x820),
INTCS_VECT(RTDMAC_1_DEI2, 0x840), INTCS_VECT(RTDMAC_1_DEI3, 0x860),
INTCS_VECT(CEU, 0x880), INTCS_VECT(BEU_BEU0, 0x8a0),
INTCS_VECT(BEU_BEU1, 0x8c0), INTCS_VECT(BEU_BEU2, 0x8e0),
INTCS_VECT(VPU, 0x980),
INTCS_VECT(TSIF1, 0x9a0),
INTCS_VECT(_3DG_SGX530, 0x9e0),
INTCS_VECT(_2DDMAC, 0xa00),
INTCS_VECT(IIC2_ALI2, 0xa80), INTCS_VECT(IIC2_TACKI2, 0xaa0),
INTCS_VECT(IIC2_WAITI2, 0xac0), INTCS_VECT(IIC2_DTEI2, 0xae0),
INTCS_VECT(IPMMU_IPMMUR, 0xb00), INTCS_VECT(IPMMU_IPMMUR2, 0xb20),
INTCS_VECT(RTDMAC_2_DEI4, 0xb80), INTCS_VECT(RTDMAC_2_DEI5, 0xba0),
INTCS_VECT(RTDMAC_2_DADERR, 0xbc0),
INTCS_VECT(IIC0_ALI0, 0xe00), INTCS_VECT(IIC0_TACKI0, 0xe20),
INTCS_VECT(IIC0_WAITI0, 0xe40), INTCS_VECT(IIC0_DTEI0, 0xe60),
INTCS_VECT(TMU_TUNI0, 0xe80), INTCS_VECT(TMU_TUNI1, 0xea0),
INTCS_VECT(TMU_TUNI2, 0xec0),
INTCS_VECT(CMT0, 0xf00),
INTCS_VECT(TSIF0, 0xf20),
INTCS_VECT(LMB, 0xf60),
INTCS_VECT(CTI, 0x400),
INTCS_VECT(ICB, 0x480),
INTCS_VECT(JPU_JPEG, 0x560),
INTCS_VECT(LCDC, 0x580),
INTCS_VECT(LCRC, 0x5a0),
INTCS_VECT(RTDMAC2_1_DEI0, 0x1300), INTCS_VECT(RTDMAC2_1_DEI1, 0x1320),
INTCS_VECT(RTDMAC2_1_DEI2, 0x1340), INTCS_VECT(RTDMAC2_1_DEI3, 0x1360),
INTCS_VECT(RTDMAC2_2_DEI4, 0x1380), INTCS_VECT(RTDMAC2_2_DEI5, 0x13a0),
INTCS_VECT(RTDMAC2_2_DADERR, 0x13c0),
INTCS_VECT(ISP, 0x1720),
INTCS_VECT(LCDC1, 0x1780),
INTCS_VECT(CSIRX, 0x17a0),
INTCS_VECT(DSITX_DSITX0, 0x17c0),
INTCS_VECT(DSITX_DSITX1, 0x17e0),
INTCS_VECT(TMU1_TUNI0, 0x1900), INTCS_VECT(TMU1_TUNI1, 0x1920),
INTCS_VECT(TMU1_TUNI2, 0x1940),
INTCS_VECT(CMT4, 0x1980),
INTCS_VECT(DSITX1_DSITX1_0, 0x19a0),
INTCS_VECT(DSITX1_DSITX1_1, 0x19c0),
INTCS_VECT(CPORTS2R, 0x1a20),
INTCS_VECT(JPU6E, 0x1a80),
INTC_VECT(INTCS, 0xf80),
};
static struct intc_group intcs_groups[] __initdata = {
INTC_GROUP(RTDMAC_1, RTDMAC_1_DEI0, RTDMAC_1_DEI1,
RTDMAC_1_DEI2, RTDMAC_1_DEI3),
INTC_GROUP(RTDMAC_2, RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR),
INTC_GROUP(VEU, VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3),
INTC_GROUP(BEU, BEU_BEU0, BEU_BEU1, BEU_BEU2),
INTC_GROUP(IIC0, IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0),
INTC_GROUP(IPMMU, IPMMU_IPMMUR, IPMMU_IPMMUR2),
INTC_GROUP(IIC2, IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2),
INTC_GROUP(RTDMAC2_1, RTDMAC2_1_DEI0, RTDMAC2_1_DEI1,
RTDMAC2_1_DEI2, RTDMAC2_1_DEI3),
INTC_GROUP(RTDMAC2_2, RTDMAC2_2_DEI4,
RTDMAC2_2_DEI5, RTDMAC2_2_DADERR),
INTC_GROUP(TMU1, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0),
INTC_GROUP(DSITX, DSITX_DSITX0, DSITX_DSITX1),
};
static struct intc_mask_reg intcs_mask_registers[] = {
{ 0xffd20184, 0xffd201c4, 8, /* IMR1SA / IMCR1SA */
{ BEU_BEU2, BEU_BEU1, BEU_BEU0, CEU,
VEU_VEU3, VEU_VEU2, VEU_VEU1, VEU_VEU0 } },
{ 0xffd20188, 0xffd201c8, 8, /* IMR2SA / IMCR2SA */
{ 0, 0, 0, VPU,
0, 0, 0, 0 } },
{ 0xffd2018c, 0xffd201cc, 8, /* IMR3SA / IMCR3SA */
{ 0, 0, 0, _2DDMAC,
0, 0, 0, ICB } },
{ 0xffd20190, 0xffd201d0, 8, /* IMR4SA / IMCR4SA */
{ 0, 0, 0, CTI,
JPU_JPEG, 0, LCRC, LCDC } },
{ 0xffd20194, 0xffd201d4, 8, /* IMR5SA / IMCR5SA */
{ 0, RTDMAC_2_DADERR, RTDMAC_2_DEI5, RTDMAC_2_DEI4,
RTDMAC_1_DEI3, RTDMAC_1_DEI2, RTDMAC_1_DEI1, RTDMAC_1_DEI0 } },
{ 0xffd20198, 0xffd201d8, 8, /* IMR6SA / IMCR6SA */
{ 0, 0, MSIOF, 0,
_3DG_SGX530, 0, 0, 0 } },
{ 0xffd2019c, 0xffd201dc, 8, /* IMR7SA / IMCR7SA */
{ 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0,
0, 0, 0, 0 } },
{ 0xffd201a4, 0xffd201e4, 8, /* IMR9SA / IMCR9SA */
{ 0, 0, 0, CMT0,
IIC2_DTEI2, IIC2_WAITI2, IIC2_TACKI2, IIC2_ALI2 } },
{ 0xffd201a8, 0xffd201e8, 8, /* IMR10SA / IMCR10SA */
{ 0, 0, IPMMU_IPMMUR2, IPMMU_IPMMUR,
0, 0, 0, 0 } },
{ 0xffd201ac, 0xffd201ec, 8, /* IMR11SA / IMCR11SA */
{ IIC0_DTEI0, IIC0_WAITI0, IIC0_TACKI0, IIC0_ALI0,
0, TSIF1, LMB, TSIF0 } },
{ 0xffd50180, 0xffd501c0, 8, /* IMR0SA3 / IMCR0SA3 */
{ 0, RTDMAC2_2_DADERR, RTDMAC2_2_DEI5, RTDMAC2_2_DEI4,
RTDMAC2_1_DEI3, RTDMAC2_1_DEI2, RTDMAC2_1_DEI1, RTDMAC2_1_DEI0 } },
{ 0xffd50190, 0xffd501d0, 8, /* IMR4SA3 / IMCR4SA3 */
{ 0, ISP, 0, 0,
LCDC1, CSIRX, DSITX_DSITX0, DSITX_DSITX1 } },
{ 0xffd50198, 0xffd501d8, 8, /* IMR6SA3 / IMCR6SA3 */
{ 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
CMT4, DSITX1_DSITX1_0, DSITX1_DSITX1_1, 0 } },
{ 0xffd5019c, 0xffd501dc, 8, /* IMR7SA3 / IMCR7SA3 */
{ 0, CPORTS2R, 0, 0,
JPU6E, 0, 0, 0 } },
{ 0xffd20104, 0, 16, /* INTAMASK */
{ 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, INTCS } },
};
/* Priority is needed for INTCA to receive the INTCS interrupt */
static struct intc_prio_reg intcs_prio_registers[] = {
{ 0xffd20000, 0, 16, 4, /* IPRAS */ { CTI, 0, _2DDMAC, ICB } },
{ 0xffd20004, 0, 16, 4, /* IPRBS */ { JPU_JPEG, LCDC, 0, LCRC } },
{ 0xffd20010, 0, 16, 4, /* IPRES */ { RTDMAC_1, CEU, 0, VPU } },
{ 0xffd20014, 0, 16, 4, /* IPRFS */ { 0, RTDMAC_2, 0, CMT0 } },
{ 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU_TUNI0, TMU_TUNI1,
TMU_TUNI2, TSIF1 } },
{ 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, 0, VEU, BEU } },
{ 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, MSIOF, TSIF0, IIC0 } },
{ 0xffd20024, 0, 16, 4, /* IPRJS */ { 0, _3DG_SGX530, 0, 0 } },
{ 0xffd20028, 0, 16, 4, /* IPRKS */ { 0, 0, LMB, 0 } },
{ 0xffd2002c, 0, 16, 4, /* IPRLS */ { IPMMU, 0, 0, 0 } },
{ 0xffd20030, 0, 16, 4, /* IPRMS */ { IIC2, 0, 0, 0 } },
{ 0xffd50000, 0, 16, 4, /* IPRAS3 */ { RTDMAC2_1, 0, 0, 0 } },
{ 0xffd50004, 0, 16, 4, /* IPRBS3 */ { RTDMAC2_2, 0, 0, 0 } },
{ 0xffd50020, 0, 16, 4, /* IPRIS3 */ { 0, ISP, 0, 0 } },
{ 0xffd50024, 0, 16, 4, /* IPRJS3 */ { LCDC1, CSIRX, DSITX, 0 } },
{ 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, 0 } },
{ 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, DSITX1_DSITX1_0,
DSITX1_DSITX1_1, 0 } },
{ 0xffd50038, 0, 16, 4, /* IPROS3 */ { 0, CPORTS2R, 0, 0 } },
{ 0xffd5003c, 0, 16, 4, /* IPRPS3 */ { JPU6E, 0, 0, 0 } },
};
static struct resource intcs_resources[] __initdata = {
[0] = {
.start = 0xffd20000,
.end = 0xffd201ff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 0xffd50000,
.end = 0xffd501ff,
.flags = IORESOURCE_MEM,
}
};
static struct intc_desc intcs_desc __initdata = {
.name = "sh7372-intcs",
.resource = intcs_resources,
.num_resources = ARRAY_SIZE(intcs_resources),
.hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers,
intcs_prio_registers, NULL, NULL),
};
static void intcs_demux(unsigned int irq, struct irq_desc *desc)
{
void __iomem *reg = (void *)get_irq_data(irq);
unsigned int evtcodeas = ioread32(reg);
generic_handle_irq(intcs_evt2irq(evtcodeas));
}
void __init sh7372_init_irq(void) void __init sh7372_init_irq(void)
{ {
void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
register_intc_controller(&intca_desc); register_intc_controller(&intca_desc);
register_intc_controller(&intcs_desc);
/* demux using INTEVTSA */
set_irq_data(evt2irq(0xf80), (void *)intevtsa);
set_irq_chained_handler(evt2irq(0xf80), intcs_demux);
} }
arch/arm/mach-shmobile/intc-sh7377.c
浏览文件 @ 500b9fc9
...@@ -90,7 +90,7 @@ enum { ...@@ -90,7 +90,7 @@ enum {
ICUSB, ICUDMC ICUSB, ICUDMC
}; };
static struct intc_vect intca_vectors[] = { static struct intc_vect intca_vectors[] __initdata = {
INTC_VECT(IRQ0A, 0x0200), INTC_VECT(IRQ1A, 0x0220), INTC_VECT(IRQ0A, 0x0200), INTC_VECT(IRQ1A, 0x0220),
INTC_VECT(IRQ2A, 0x0240), INTC_VECT(IRQ3A, 0x0260), INTC_VECT(IRQ2A, 0x0240), INTC_VECT(IRQ3A, 0x0260),
INTC_VECT(IRQ4A, 0x0280), INTC_VECT(IRQ5A, 0x02a0), INTC_VECT(IRQ4A, 0x0280), INTC_VECT(IRQ5A, 0x02a0),
...@@ -202,7 +202,7 @@ static struct intc_group intca_groups[] __initdata = { ...@@ -202,7 +202,7 @@ static struct intc_group intca_groups[] __initdata = {
INTC_GROUP(ICUDMC, ICUDMC_ICUDMC1, ICUDMC_ICUDMC2), INTC_GROUP(ICUDMC, ICUDMC_ICUDMC1, ICUDMC_ICUDMC2),
}; };
static struct intc_mask_reg intca_mask_registers[] = { static struct intc_mask_reg intca_mask_registers[] __initdata = {
{ 0xe6900040, 0xe6900060, 8, /* INTMSK00A / INTMSKCLR00A */ { 0xe6900040, 0xe6900060, 8, /* INTMSK00A / INTMSKCLR00A */
{ IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
{ 0xe6900044, 0xe6900064, 8, /* INTMSK10A / INTMSKCLR10A */ { 0xe6900044, 0xe6900064, 8, /* INTMSK10A / INTMSKCLR10A */
...@@ -272,7 +272,7 @@ static struct intc_mask_reg intca_mask_registers[] = { ...@@ -272,7 +272,7 @@ static struct intc_mask_reg intca_mask_registers[] = {
SCIFA6, 0, 0, 0 } }, SCIFA6, 0, 0, 0 } },
}; };
static struct intc_prio_reg intca_prio_registers[] = { static struct intc_prio_reg intca_prio_registers[] __initdata = {
{ 0xe6900010, 0, 32, 4, /* INTPRI00A */ { 0xe6900010, 0, 32, 4, /* INTPRI00A */
{ IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
{ 0xe6900014, 0, 32, 4, /* INTPRI10A */ { 0xe6900014, 0, 32, 4, /* INTPRI10A */
...@@ -346,7 +346,301 @@ static struct intc_desc intca_desc __initdata = { ...@@ -346,7 +346,301 @@ static struct intc_desc intca_desc __initdata = {
intca_sense_registers, intca_ack_registers), intca_sense_registers, intca_ack_registers),
}; };
/* this macro ignore entry which is also in INTCA */
#define __IGNORE(a...)
#define __IGNORE0(a...) 0
enum {
UNUSED_INTCS = 0,
INTCS,
/* interrupt sources INTCS */
VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3,
RTDMAC1_1_DEI0, RTDMAC1_1_DEI1, RTDMAC1_1_DEI2, RTDMAC1_1_DEI3,
CEU,
BEU_BEU0, BEU_BEU1, BEU_BEU2,
__IGNORE(MFI)
__IGNORE(BBIF2)
VPU,
TSIF1,
__IGNORE(SGX540)
_2DDMAC,
IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2,
IPMMU_IPMMUR, IPMMU_IPMMUR2,
RTDMAC1_2_DEI4, RTDMAC1_2_DEI5, RTDMAC1_2_DADERR,
__IGNORE(KEYSC)
__IGNORE(TTI20)
__IGNORE(MSIOF)
IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0,
TMU_TUNI0, TMU_TUNI1, TMU_TUNI2,
CMT0,
TSIF0,
__IGNORE(CMT2)
LMB,
__IGNORE(MSUG)
__IGNORE(MSU_MSU, MSU_MSU2)
__IGNORE(CTI)
MVI3,
__IGNORE(RWDT0)
__IGNORE(RWDT1)
ICB,
PEP,
ASA,
__IGNORE(_2DG)
HQE,
JPU,
LCDC0,
__IGNORE(LCRC)
RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, RTDMAC2_1_DEI2, RTDMAC2_1_DEI3,
RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR,
FRC,
LCDC1,
CSIRX,
DSITX_DSITX0, DSITX_DSITX1,
__IGNORE(SPU2_SPU0, SPU2_SPU1)
__IGNORE(FSI)
__IGNORE(FMSI)
__IGNORE(SCUV)
TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12,
TSIF2,
CMT4,
__IGNORE(MFIS2)
CPORTS2R,
/* interrupt groups INTCS */
RTDMAC1_1, RTDMAC1_2, VEU, BEU, IIC0, __IGNORE(MSU) IPMMU,
IIC2, RTDMAC2_1, RTDMAC2_2, DSITX, __IGNORE(SPU2) TMU1,
};
#define INTCS_INTVECT 0x0F80
static struct intc_vect intcs_vectors[] __initdata = {
INTCS_VECT(VEU_VEU0, 0x0700), INTCS_VECT(VEU_VEU1, 0x0720),
INTCS_VECT(VEU_VEU2, 0x0740), INTCS_VECT(VEU_VEU3, 0x0760),
INTCS_VECT(RTDMAC1_1_DEI0, 0x0800), INTCS_VECT(RTDMAC1_1_DEI1, 0x0820),
INTCS_VECT(RTDMAC1_1_DEI2, 0x0840), INTCS_VECT(RTDMAC1_1_DEI3, 0x0860),
INTCS_VECT(CEU, 0x0880),
INTCS_VECT(BEU_BEU0, 0x08A0),
INTCS_VECT(BEU_BEU1, 0x08C0),
INTCS_VECT(BEU_BEU2, 0x08E0),
__IGNORE(INTCS_VECT(MFI, 0x0900))
__IGNORE(INTCS_VECT(BBIF2, 0x0960))
INTCS_VECT(VPU, 0x0980),
INTCS_VECT(TSIF1, 0x09A0),
__IGNORE(INTCS_VECT(SGX540, 0x09E0))
INTCS_VECT(_2DDMAC, 0x0A00),
INTCS_VECT(IIC2_ALI2, 0x0A80), INTCS_VECT(IIC2_TACKI2, 0x0AA0),
INTCS_VECT(IIC2_WAITI2, 0x0AC0), INTCS_VECT(IIC2_DTEI2, 0x0AE0),
INTCS_VECT(IPMMU_IPMMUR, 0x0B00), INTCS_VECT(IPMMU_IPMMUR2, 0x0B20),
INTCS_VECT(RTDMAC1_2_DEI4, 0x0B80),
INTCS_VECT(RTDMAC1_2_DEI5, 0x0BA0),
INTCS_VECT(RTDMAC1_2_DADERR, 0x0BC0),
__IGNORE(INTCS_VECT(KEYSC 0x0BE0))
__IGNORE(INTCS_VECT(TTI20, 0x0C80))
__IGNORE(INTCS_VECT(MSIOF, 0x0D20))
INTCS_VECT(IIC0_ALI0, 0x0E00), INTCS_VECT(IIC0_TACKI0, 0x0E20),
INTCS_VECT(IIC0_WAITI0, 0x0E40), INTCS_VECT(IIC0_DTEI0, 0x0E60),
INTCS_VECT(TMU_TUNI0, 0x0E80),
INTCS_VECT(TMU_TUNI1, 0x0EA0),
INTCS_VECT(TMU_TUNI2, 0x0EC0),
INTCS_VECT(CMT0, 0x0F00),
INTCS_VECT(TSIF0, 0x0F20),
__IGNORE(INTCS_VECT(CMT2, 0x0F40))
INTCS_VECT(LMB, 0x0F60),
__IGNORE(INTCS_VECT(MSUG, 0x0F80))
__IGNORE(INTCS_VECT(MSU_MSU, 0x0FA0))
__IGNORE(INTCS_VECT(MSU_MSU2, 0x0FC0))
__IGNORE(INTCS_VECT(CTI, 0x0400))
INTCS_VECT(MVI3, 0x0420),
__IGNORE(INTCS_VECT(RWDT0, 0x0440))
__IGNORE(INTCS_VECT(RWDT1, 0x0460))
INTCS_VECT(ICB, 0x0480),
INTCS_VECT(PEP, 0x04A0),
INTCS_VECT(ASA, 0x04C0),
__IGNORE(INTCS_VECT(_2DG, 0x04E0))
INTCS_VECT(HQE, 0x0540),
INTCS_VECT(JPU, 0x0560),
INTCS_VECT(LCDC0, 0x0580),
__IGNORE(INTCS_VECT(LCRC, 0x05A0))
INTCS_VECT(RTDMAC2_1_DEI0, 0x1300), INTCS_VECT(RTDMAC2_1_DEI1, 0x1320),
INTCS_VECT(RTDMAC2_1_DEI2, 0x1340), INTCS_VECT(RTDMAC2_1_DEI3, 0x1360),
INTCS_VECT(RTDMAC2_2_DEI4, 0x1380), INTCS_VECT(RTDMAC2_2_DEI5, 0x13A0),
INTCS_VECT(RTDMAC2_2_DADERR, 0x13C0),
INTCS_VECT(FRC, 0x1700),
INTCS_VECT(LCDC1, 0x1780),
INTCS_VECT(CSIRX, 0x17A0),
INTCS_VECT(DSITX_DSITX0, 0x17C0), INTCS_VECT(DSITX_DSITX1, 0x17E0),
__IGNORE(INTCS_VECT(SPU2_SPU0, 0x1800))
__IGNORE(INTCS_VECT(SPU2_SPU1, 0x1820))
__IGNORE(INTCS_VECT(FSI, 0x1840))
__IGNORE(INTCS_VECT(FMSI, 0x1860))
__IGNORE(INTCS_VECT(SCUV, 0x1880))
INTCS_VECT(TMU1_TUNI10, 0x1900), INTCS_VECT(TMU1_TUNI11, 0x1920),
INTCS_VECT(TMU1_TUNI12, 0x1940),
INTCS_VECT(TSIF2, 0x1960),
INTCS_VECT(CMT4, 0x1980),
__IGNORE(INTCS_VECT(MFIS2, 0x1A00))
INTCS_VECT(CPORTS2R, 0x1A20),
INTC_VECT(INTCS, INTCS_INTVECT),
};
static struct intc_group intcs_groups[] __initdata = {
INTC_GROUP(RTDMAC1_1,
RTDMAC1_1_DEI0, RTDMAC1_1_DEI1,
RTDMAC1_1_DEI2, RTDMAC1_1_DEI3),
INTC_GROUP(RTDMAC1_2,
RTDMAC1_2_DEI4, RTDMAC1_2_DEI5, RTDMAC1_2_DADERR),
INTC_GROUP(VEU, VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3),
INTC_GROUP(BEU, BEU_BEU0, BEU_BEU1, BEU_BEU2),
INTC_GROUP(IIC0, IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0),
__IGNORE(INTC_GROUP(MSU, MSU_MSU, MSU_MSU2))
INTC_GROUP(IPMMU, IPMMU_IPMMUR, IPMMU_IPMMUR2),
INTC_GROUP(IIC2, IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2),
INTC_GROUP(RTDMAC2_1,
RTDMAC2_1_DEI0, RTDMAC2_1_DEI1,
RTDMAC2_1_DEI2, RTDMAC2_1_DEI3),
INTC_GROUP(RTDMAC2_2, RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR),
INTC_GROUP(DSITX, DSITX_DSITX0, DSITX_DSITX1),
__IGNORE(INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1))
INTC_GROUP(TMU1, TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12),
};
static struct intc_mask_reg intcs_mask_registers[] __initdata = {
{ 0xE6940184, 0xE69401C4, 8, /* IMR1AS / IMCR1AS */
{ BEU_BEU2, BEU_BEU1, BEU_BEU0, CEU,
VEU_VEU3, VEU_VEU2, VEU_VEU1, VEU_VEU0 } },
{ 0xE6940188, 0xE69401C8, 8, /* IMR2AS / IMCR2AS */
{ 0, 0, 0, VPU,
__IGNORE0(BBIF2), 0, 0, __IGNORE0(MFI) } },
{ 0xE694018C, 0xE69401CC, 8, /* IMR3AS / IMCR3AS */
{ 0, 0, 0, _2DDMAC,
__IGNORE0(_2DG), ASA, PEP, ICB } },
{ 0xE6940190, 0xE69401D0, 8, /* IMR4AS / IMCR4AS */
{ 0, 0, MVI3, __IGNORE0(CTI),
JPU, HQE, __IGNORE0(LCRC), LCDC0 } },
{ 0xE6940194, 0xE69401D4, 8, /* IMR5AS / IMCR5AS */
{ __IGNORE0(KEYSC), RTDMAC1_2_DADERR, RTDMAC1_2_DEI5, RTDMAC1_2_DEI4,
RTDMAC1_1_DEI3, RTDMAC1_1_DEI2, RTDMAC1_1_DEI1, RTDMAC1_1_DEI0 } },
__IGNORE({ 0xE6940198, 0xE69401D8, 8, /* IMR6AS / IMCR6AS */
{ 0, 0, MSIOF, 0,
SGX540, 0, TTI20, 0 } })
{ 0xE694019C, 0xE69401DC, 8, /* IMR7AS / IMCR7AS */
{ 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0,
0, 0, 0, 0 } },
__IGNORE({ 0xE69401A0, 0xE69401E0, 8, /* IMR8AS / IMCR8AS */
{ 0, 0, 0, 0,
0, MSU_MSU, MSU_MSU2, MSUG } })
{ 0xE69401A4, 0xE69401E4, 8, /* IMR9AS / IMCR9AS */
{ __IGNORE0(RWDT1), __IGNORE0(RWDT0), __IGNORE0(CMT2), CMT0,
IIC2_DTEI2, IIC2_WAITI2, IIC2_TACKI2, IIC2_ALI2 } },
{ 0xE69401A8, 0xE69401E8, 8, /* IMR10AS / IMCR10AS */
{ 0, 0, IPMMU_IPMMUR, IPMMU_IPMMUR2,
0, 0, 0, 0 } },
{ 0xE69401AC, 0xE69401EC, 8, /* IMR11AS / IMCR11AS */
{ IIC0_DTEI0, IIC0_WAITI0, IIC0_TACKI0, IIC0_ALI0,
0, TSIF1, LMB, TSIF0 } },
{ 0xE6950180, 0xE69501C0, 8, /* IMR0AS3 / IMCR0AS3 */
{ RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, RTDMAC2_1_DEI2, RTDMAC2_1_DEI3,
RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR, 0 } },
{ 0xE6950190, 0xE69501D0, 8, /* IMR4AS3 / IMCR4AS3 */
{ FRC, 0, 0, 0,
LCDC1, CSIRX, DSITX_DSITX0, DSITX_DSITX1 } },
__IGNORE({ 0xE6950194, 0xE69501D4, 8, /* IMR5AS3 / IMCR5AS3 */
{SPU2_SPU0, SPU2_SPU1, FSI, FMSI,
SCUV, 0, 0, 0 } })
{ 0xE6950198, 0xE69501D8, 8, /* IMR6AS3 / IMCR6AS3 */
{ TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12, TSIF2,
CMT4, 0, 0, 0 } },
{ 0xE695019C, 0xE69501DC, 8, /* IMR7AS3 / IMCR7AS3 */
{ __IGNORE0(MFIS2), CPORTS2R, 0, 0,
0, 0, 0, 0 } },
{ 0xFFD20104, 0, 16, /* INTAMASK */
{ 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, INTCS } }
};
static struct intc_prio_reg intcs_prio_registers[] __initdata = {
/* IPRAS */
{ 0xFFD20000, 0, 16, 4, { __IGNORE0(CTI), MVI3, _2DDMAC, ICB } },
/* IPRBS */
{ 0xFFD20004, 0, 16, 4, { JPU, LCDC0, 0, __IGNORE0(LCRC) } },
/* IPRCS */
__IGNORE({ 0xFFD20008, 0, 16, 4, { BBIF2, 0, 0, 0 } })
/* IPRES */
{ 0xFFD20010, 0, 16, 4, { RTDMAC1_1, CEU, __IGNORE0(MFI), VPU } },
/* IPRFS */
{ 0xFFD20014, 0, 16, 4,
{ __IGNORE0(KEYSC), RTDMAC1_2, __IGNORE0(CMT2), CMT0 } },
/* IPRGS */
{ 0xFFD20018, 0, 16, 4, { TMU_TUNI0, TMU_TUNI1, TMU_TUNI2, TSIF1 } },
/* IPRHS */
{ 0xFFD2001C, 0, 16, 4, { __IGNORE0(TTI20), 0, VEU, BEU } },
/* IPRIS */
{ 0xFFD20020, 0, 16, 4, { 0, __IGNORE0(MSIOF), TSIF0, IIC0 } },
/* IPRJS */
__IGNORE({ 0xFFD20024, 0, 16, 4, { 0, SGX540, MSUG, MSU } })
/* IPRKS */
{ 0xFFD20028, 0, 16, 4, { __IGNORE0(_2DG), ASA, LMB, PEP } },
/* IPRLS */
{ 0xFFD2002C, 0, 16, 4, { IPMMU, 0, 0, HQE } },
/* IPRMS */
{ 0xFFD20030, 0, 16, 4,
{ IIC2, 0, __IGNORE0(RWDT1), __IGNORE0(RWDT0) } },
/* IPRAS3 */
{ 0xFFD50000, 0, 16, 4, { RTDMAC2_1, 0, 0, 0 } },
/* IPRBS3 */
{ 0xFFD50004, 0, 16, 4, { RTDMAC2_2, 0, 0, 0 } },
/* IPRIS3 */
{ 0xFFD50020, 0, 16, 4, { FRC, 0, 0, 0 } },
/* IPRJS3 */
{ 0xFFD50024, 0, 16, 4, { LCDC1, CSIRX, DSITX, 0 } },
/* IPRKS3 */
__IGNORE({ 0xFFD50028, 0, 16, 4, { SPU2, 0, FSI, FMSI } })
/* IPRLS3 */
__IGNORE({ 0xFFD5002C, 0, 16, 4, { SCUV, 0, 0, 0 } })
/* IPRMS3 */
{ 0xFFD50030, 0, 16, 4, { TMU1, 0, 0, TSIF2 } },
/* IPRNS3 */
{ 0xFFD50034, 0, 16, 4, { CMT4, 0, 0, 0 } },
/* IPROS3 */
{ 0xFFD50038, 0, 16, 4, { __IGNORE0(MFIS2), CPORTS2R, 0, 0 } },
};
static struct resource intcs_resources[] __initdata = {
[0] = {
.start = 0xffd20000,
.end = 0xffd500ff,
.flags = IORESOURCE_MEM,
}
};
static struct intc_desc intcs_desc __initdata = {
.name = "sh7377-intcs",
.resource = intcs_resources,
.num_resources = ARRAY_SIZE(intcs_resources),
.hw = INTC_HW_DESC(intcs_vectors, intcs_groups,
intcs_mask_registers, intcs_prio_registers,
NULL, NULL),
};
static void intcs_demux(unsigned int irq, struct irq_desc *desc)
{
void __iomem *reg = (void *)get_irq_data(irq);
unsigned int evtcodeas = ioread32(reg);
generic_handle_irq(intcs_evt2irq(evtcodeas));
}
#define INTEVTSA 0xFFD20100
void __init sh7377_init_irq(void) void __init sh7377_init_irq(void)
{ {
void __iomem *intevtsa = ioremap_nocache(INTEVTSA, PAGE_SIZE);
register_intc_controller(&intca_desc); register_intc_controller(&intca_desc);
register_intc_controller(&intcs_desc);
/* demux using INTEVTSA */
set_irq_data(evt2irq(INTCS_INTVECT), (void *)intevtsa);
set_irq_chained_handler(evt2irq(INTCS_INTVECT), intcs_demux);
} }
arch/arm/mach-shmobile/pfc-sh7372.c
浏览文件 @ 500b9fc9
...@@ -1160,6 +1160,9 @@ static struct pinmux_gpio pinmux_gpios[] = { ...@@ -1160,6 +1160,9 @@ static struct pinmux_gpio pinmux_gpios[] = {
GPIO_FN(LCDD18), GPIO_FN(LCDD19), GPIO_FN(LCDD20), GPIO_FN(LCDD18), GPIO_FN(LCDD19), GPIO_FN(LCDD20),
GPIO_FN(LCDD21), GPIO_FN(LCDD22), GPIO_FN(LCDD23), GPIO_FN(LCDD21), GPIO_FN(LCDD22), GPIO_FN(LCDD23),
GPIO_FN(LCDC0_SELECT),
GPIO_FN(LCDC1_SELECT),
/* IRDA */ /* IRDA */
GPIO_FN(IRDA_OUT), GPIO_FN(IRDA_IN), GPIO_FN(IRDA_FIRSEL), GPIO_FN(IRDA_OUT), GPIO_FN(IRDA_IN), GPIO_FN(IRDA_FIRSEL),
GPIO_FN(IROUT_139), GPIO_FN(IROUT_140), GPIO_FN(IROUT_139), GPIO_FN(IROUT_140),
......
arch/arm/mach-shmobile/setup-sh7367.c
浏览文件 @ 500b9fc9
...@@ -31,11 +31,13 @@ ...@@ -31,11 +31,13 @@
#include <asm/mach-types.h> #include <asm/mach-types.h>
#include <asm/mach/arch.h> #include <asm/mach/arch.h>
/* SCIFA0 */
static struct plat_sci_port scif0_platform_data = { static struct plat_sci_port scif0_platform_data = {
.mapbase = 0xe6c40000, .mapbase = 0xe6c40000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 80, 80, 80, 80 }, .irqs = { evt2irq(0xc00), evt2irq(0xc00),
evt2irq(0xc00), evt2irq(0xc00) },
}; };
static struct platform_device scif0_device = { static struct platform_device scif0_device = {
...@@ -46,11 +48,13 @@ static struct platform_device scif0_device = { ...@@ -46,11 +48,13 @@ static struct platform_device scif0_device = {
}, },
}; };
/* SCIFA1 */
static struct plat_sci_port scif1_platform_data = { static struct plat_sci_port scif1_platform_data = {
.mapbase = 0xe6c50000, .mapbase = 0xe6c50000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 81, 81, 81, 81 }, .irqs = { evt2irq(0xc20), evt2irq(0xc20),
evt2irq(0xc20), evt2irq(0xc20) },
}; };
static struct platform_device scif1_device = { static struct platform_device scif1_device = {
...@@ -61,11 +65,13 @@ static struct platform_device scif1_device = { ...@@ -61,11 +65,13 @@ static struct platform_device scif1_device = {
}, },
}; };
/* SCIFA2 */
static struct plat_sci_port scif2_platform_data = { static struct plat_sci_port scif2_platform_data = {
.mapbase = 0xe6c60000, .mapbase = 0xe6c60000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 82, 82, 82, 82 }, .irqs = { evt2irq(0xc40), evt2irq(0xc40),
evt2irq(0xc40), evt2irq(0xc40) },
}; };
static struct platform_device scif2_device = { static struct platform_device scif2_device = {
...@@ -76,11 +82,13 @@ static struct platform_device scif2_device = { ...@@ -76,11 +82,13 @@ static struct platform_device scif2_device = {
}, },
}; };
/* SCIFA3 */
static struct plat_sci_port scif3_platform_data = { static struct plat_sci_port scif3_platform_data = {
.mapbase = 0xe6c70000, .mapbase = 0xe6c70000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 83, 83, 83, 83 }, .irqs = { evt2irq(0xc60), evt2irq(0xc60),
evt2irq(0xc60), evt2irq(0xc60) },
}; };
static struct platform_device scif3_device = { static struct platform_device scif3_device = {
...@@ -91,11 +99,13 @@ static struct platform_device scif3_device = { ...@@ -91,11 +99,13 @@ static struct platform_device scif3_device = {
}, },
}; };
/* SCIFA4 */
static struct plat_sci_port scif4_platform_data = { static struct plat_sci_port scif4_platform_data = {
.mapbase = 0xe6c80000, .mapbase = 0xe6c80000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 89, 89, 89, 89 }, .irqs = { evt2irq(0xd20), evt2irq(0xd20),
evt2irq(0xd20), evt2irq(0xd20) },
}; };
static struct platform_device scif4_device = { static struct platform_device scif4_device = {
...@@ -106,11 +116,13 @@ static struct platform_device scif4_device = { ...@@ -106,11 +116,13 @@ static struct platform_device scif4_device = {
}, },
}; };
/* SCIFA5 */
static struct plat_sci_port scif5_platform_data = { static struct plat_sci_port scif5_platform_data = {
.mapbase = 0xe6cb0000, .mapbase = 0xe6cb0000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 90, 90, 90, 90 }, .irqs = { evt2irq(0xd40), evt2irq(0xd40),
evt2irq(0xd40), evt2irq(0xd40) },
}; };
static struct platform_device scif5_device = { static struct platform_device scif5_device = {
...@@ -121,11 +133,13 @@ static struct platform_device scif5_device = { ...@@ -121,11 +133,13 @@ static struct platform_device scif5_device = {
}, },
}; };
/* SCIFB */
static struct plat_sci_port scif6_platform_data = { static struct plat_sci_port scif6_platform_data = {
.mapbase = 0xe6c30000, .mapbase = 0xe6c30000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 91, 91, 91, 91 }, .irqs = { evt2irq(0xd60), evt2irq(0xd60),
evt2irq(0xd60), evt2irq(0xd60) },
}; };
static struct platform_device scif6_device = { static struct platform_device scif6_device = {
...@@ -153,7 +167,7 @@ static struct resource cmt10_resources[] = { ...@@ -153,7 +167,7 @@ static struct resource cmt10_resources[] = {
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
[1] = { [1] = {
.start = 72, .start = evt2irq(0xb00), /* CMT1_CMT10 */
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
}, },
}; };
......
arch/arm/mach-shmobile/setup-sh7372.c
浏览文件 @ 500b9fc9
...@@ -26,17 +26,21 @@ ...@@ -26,17 +26,21 @@
#include <linux/input.h> #include <linux/input.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/serial_sci.h> #include <linux/serial_sci.h>
#include <linux/sh_dma.h>
#include <linux/sh_intc.h> #include <linux/sh_intc.h>
#include <linux/sh_timer.h> #include <linux/sh_timer.h>
#include <mach/hardware.h> #include <mach/hardware.h>
#include <mach/sh7372.h>
#include <asm/mach-types.h> #include <asm/mach-types.h>
#include <asm/mach/arch.h> #include <asm/mach/arch.h>
/* SCIFA0 */
static struct plat_sci_port scif0_platform_data = { static struct plat_sci_port scif0_platform_data = {
.mapbase = 0xe6c40000, .mapbase = 0xe6c40000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF, .type = PORT_SCIFA,
.irqs = { 80, 80, 80, 80 }, .irqs = { evt2irq(0x0c00), evt2irq(0x0c00),
evt2irq(0x0c00), evt2irq(0x0c00) },
}; };
static struct platform_device scif0_device = { static struct platform_device scif0_device = {
...@@ -47,11 +51,13 @@ static struct platform_device scif0_device = { ...@@ -47,11 +51,13 @@ static struct platform_device scif0_device = {
}, },
}; };
/* SCIFA1 */
static struct plat_sci_port scif1_platform_data = { static struct plat_sci_port scif1_platform_data = {
.mapbase = 0xe6c50000, .mapbase = 0xe6c50000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF, .type = PORT_SCIFA,
.irqs = { 81, 81, 81, 81 }, .irqs = { evt2irq(0x0c20), evt2irq(0x0c20),
evt2irq(0x0c20), evt2irq(0x0c20) },
}; };
static struct platform_device scif1_device = { static struct platform_device scif1_device = {
...@@ -62,11 +68,13 @@ static struct platform_device scif1_device = { ...@@ -62,11 +68,13 @@ static struct platform_device scif1_device = {
}, },
}; };
/* SCIFA2 */
static struct plat_sci_port scif2_platform_data = { static struct plat_sci_port scif2_platform_data = {
.mapbase = 0xe6c60000, .mapbase = 0xe6c60000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF, .type = PORT_SCIFA,
.irqs = { 82, 82, 82, 82 }, .irqs = { evt2irq(0x0c40), evt2irq(0x0c40),
evt2irq(0x0c40), evt2irq(0x0c40) },
}; };
static struct platform_device scif2_device = { static struct platform_device scif2_device = {
...@@ -77,11 +85,13 @@ static struct platform_device scif2_device = { ...@@ -77,11 +85,13 @@ static struct platform_device scif2_device = {
}, },
}; };
/* SCIFA3 */
static struct plat_sci_port scif3_platform_data = { static struct plat_sci_port scif3_platform_data = {
.mapbase = 0xe6c70000, .mapbase = 0xe6c70000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF, .type = PORT_SCIFA,
.irqs = { 83, 83, 83, 83 }, .irqs = { evt2irq(0x0c60), evt2irq(0x0c60),
evt2irq(0x0c60), evt2irq(0x0c60) },
}; };
static struct platform_device scif3_device = { static struct platform_device scif3_device = {
...@@ -92,11 +102,13 @@ static struct platform_device scif3_device = { ...@@ -92,11 +102,13 @@ static struct platform_device scif3_device = {
}, },
}; };
/* SCIFA4 */
static struct plat_sci_port scif4_platform_data = { static struct plat_sci_port scif4_platform_data = {
.mapbase = 0xe6c80000, .mapbase = 0xe6c80000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF, .type = PORT_SCIFA,
.irqs = { 89, 89, 89, 89 }, .irqs = { evt2irq(0x0d20), evt2irq(0x0d20),
evt2irq(0x0d20), evt2irq(0x0d20) },
}; };
static struct platform_device scif4_device = { static struct platform_device scif4_device = {
...@@ -107,11 +119,13 @@ static struct platform_device scif4_device = { ...@@ -107,11 +119,13 @@ static struct platform_device scif4_device = {
}, },
}; };
/* SCIFA5 */
static struct plat_sci_port scif5_platform_data = { static struct plat_sci_port scif5_platform_data = {
.mapbase = 0xe6cb0000, .mapbase = 0xe6cb0000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF, .type = PORT_SCIFA,
.irqs = { 90, 90, 90, 90 }, .irqs = { evt2irq(0x0d40), evt2irq(0x0d40),
evt2irq(0x0d40), evt2irq(0x0d40) },
}; };
static struct platform_device scif5_device = { static struct platform_device scif5_device = {
...@@ -122,11 +136,13 @@ static struct platform_device scif5_device = { ...@@ -122,11 +136,13 @@ static struct platform_device scif5_device = {
}, },
}; };
/* SCIFB */
static struct plat_sci_port scif6_platform_data = { static struct plat_sci_port scif6_platform_data = {
.mapbase = 0xe6c30000, .mapbase = 0xe6c30000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF, .type = PORT_SCIFB,
.irqs = { 91, 91, 91, 91 }, .irqs = { evt2irq(0x0d60), evt2irq(0x0d60),
evt2irq(0x0d60), evt2irq(0x0d60) },
}; };
static struct platform_device scif6_device = { static struct platform_device scif6_device = {
...@@ -137,11 +153,12 @@ static struct platform_device scif6_device = { ...@@ -137,11 +153,12 @@ static struct platform_device scif6_device = {
}, },
}; };
/* CMT */
static struct sh_timer_config cmt10_platform_data = { static struct sh_timer_config cmt10_platform_data = {
.name = "CMT10", .name = "CMT10",
.channel_offset = 0x10, .channel_offset = 0x10,
.timer_bit = 0, .timer_bit = 0,
.clk = "r_clk", .clk = "cmt1",
.clockevent_rating = 125, .clockevent_rating = 125,
.clocksource_rating = 125, .clocksource_rating = 125,
}; };
...@@ -154,7 +171,7 @@ static struct resource cmt10_resources[] = { ...@@ -154,7 +171,7 @@ static struct resource cmt10_resources[] = {
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
[1] = { [1] = {
.start = 72, .start = evt2irq(0x0b00), /* CMT1_CMT10 */
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
}, },
}; };
...@@ -169,6 +186,337 @@ static struct platform_device cmt10_device = { ...@@ -169,6 +186,337 @@ static struct platform_device cmt10_device = {
.num_resources = ARRAY_SIZE(cmt10_resources), .num_resources = ARRAY_SIZE(cmt10_resources),
}; };
/* I2C */
static struct resource iic0_resources[] = {
[0] = {
.name = "IIC0",
.start = 0xFFF20000,
.end = 0xFFF20425 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = intcs_evt2irq(0xe00), /* IIC0_ALI0 */
.end = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device iic0_device = {
.name = "i2c-sh_mobile",
.id = 0, /* "i2c0" clock */
.num_resources = ARRAY_SIZE(iic0_resources),
.resource = iic0_resources,
};
static struct resource iic1_resources[] = {
[0] = {
.name = "IIC1",
.start = 0xE6C20000,
.end = 0xE6C20425 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0x780), /* IIC1_ALI1 */
.end = evt2irq(0x7e0), /* IIC1_DTEI1 */
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device iic1_device = {
.name = "i2c-sh_mobile",
.id = 1, /* "i2c1" clock */
.num_resources = ARRAY_SIZE(iic1_resources),
.resource = iic1_resources,
};
/* DMA */
/* Transmit sizes and respective CHCR register values */
enum {
XMIT_SZ_8BIT = 0,
XMIT_SZ_16BIT = 1,
XMIT_SZ_32BIT = 2,
XMIT_SZ_64BIT = 7,
XMIT_SZ_128BIT = 3,
XMIT_SZ_256BIT = 4,
XMIT_SZ_512BIT = 5,
};
/* log2(size / 8) - used to calculate number of transfers */
#define TS_SHIFT { \
[XMIT_SZ_8BIT] = 0, \
[XMIT_SZ_16BIT] = 1, \
[XMIT_SZ_32BIT] = 2, \
[XMIT_SZ_64BIT] = 3, \
[XMIT_SZ_128BIT] = 4, \
[XMIT_SZ_256BIT] = 5, \
[XMIT_SZ_512BIT] = 6, \
}
#define TS_INDEX2VAL(i) ((((i) & 3) << 3) | \
(((i) & 0xc) << (20 - 2)))
static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
{
.slave_id = SHDMA_SLAVE_SCIF0_TX,
.addr = 0xe6c40020,
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0x21,
}, {
.slave_id = SHDMA_SLAVE_SCIF0_RX,
.addr = 0xe6c40024,
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0x22,
}, {
.slave_id = SHDMA_SLAVE_SCIF1_TX,
.addr = 0xe6c50020,
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0x25,
}, {
.slave_id = SHDMA_SLAVE_SCIF1_RX,
.addr = 0xe6c50024,
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0x26,
}, {
.slave_id = SHDMA_SLAVE_SCIF2_TX,
.addr = 0xe6c60020,
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0x29,
}, {
.slave_id = SHDMA_SLAVE_SCIF2_RX,
.addr = 0xe6c60024,
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0x2a,
}, {
.slave_id = SHDMA_SLAVE_SCIF3_TX,
.addr = 0xe6c70020,
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0x2d,
}, {
.slave_id = SHDMA_SLAVE_SCIF3_RX,
.addr = 0xe6c70024,
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0x2e,
}, {
.slave_id = SHDMA_SLAVE_SCIF4_TX,
.addr = 0xe6c80020,
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0x39,
}, {
.slave_id = SHDMA_SLAVE_SCIF4_RX,
.addr = 0xe6c80024,
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0x3a,
}, {
.slave_id = SHDMA_SLAVE_SCIF5_TX,
.addr = 0xe6cb0020,
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0x35,
}, {
.slave_id = SHDMA_SLAVE_SCIF5_RX,
.addr = 0xe6cb0024,
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0x36,
}, {
.slave_id = SHDMA_SLAVE_SCIF6_TX,
.addr = 0xe6c30040,
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0x3d,
}, {
.slave_id = SHDMA_SLAVE_SCIF6_RX,
.addr = 0xe6c30060,
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0x3e,
}, {
.slave_id = SHDMA_SLAVE_SDHI0_TX,
.addr = 0xe6850030,
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
.mid_rid = 0xc1,
}, {
.slave_id = SHDMA_SLAVE_SDHI0_RX,
.addr = 0xe6850030,
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
.mid_rid = 0xc2,
}, {
.slave_id = SHDMA_SLAVE_SDHI1_TX,
.addr = 0xe6860030,
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
.mid_rid = 0xc9,
}, {
.slave_id = SHDMA_SLAVE_SDHI1_RX,
.addr = 0xe6860030,
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
.mid_rid = 0xca,
}, {
.slave_id = SHDMA_SLAVE_SDHI2_TX,
.addr = 0xe6870030,
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
.mid_rid = 0xcd,
}, {
.slave_id = SHDMA_SLAVE_SDHI2_RX,
.addr = 0xe6870030,
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
.mid_rid = 0xce,
},
};
static const struct sh_dmae_channel sh7372_dmae_channels[] = {
{
.offset = 0,
.dmars = 0,
.dmars_bit = 0,
}, {
.offset = 0x10,
.dmars = 0,
.dmars_bit = 8,
}, {
.offset = 0x20,
.dmars = 4,
.dmars_bit = 0,
}, {
.offset = 0x30,
.dmars = 4,
.dmars_bit = 8,
}, {
.offset = 0x50,
.dmars = 8,
.dmars_bit = 0,
}, {
.offset = 0x60,
.dmars = 8,
.dmars_bit = 8,
}
};
static const unsigned int ts_shift[] = TS_SHIFT;
static struct sh_dmae_pdata dma_platform_data = {
.slave = sh7372_dmae_slaves,
.slave_num = ARRAY_SIZE(sh7372_dmae_slaves),
.channel = sh7372_dmae_channels,
.channel_num = ARRAY_SIZE(sh7372_dmae_channels),
.ts_low_shift = 3,
.ts_low_mask = 0x18,
.ts_high_shift = (20 - 2), /* 2 bits for shifted low TS */
.ts_high_mask = 0x00300000,
.ts_shift = ts_shift,
.ts_shift_num = ARRAY_SIZE(ts_shift),
.dmaor_init = DMAOR_DME,
};
/* Resource order important! */
static struct resource sh7372_dmae0_resources[] = {
{
/* Channel registers and DMAOR */
.start = 0xfe008020,
.end = 0xfe00808f,
.flags = IORESOURCE_MEM,
},
{
/* DMARSx */
.start = 0xfe009000,
.end = 0xfe00900b,
.flags = IORESOURCE_MEM,
},
{
/* DMA error IRQ */
.start = 246,
.end = 246,
.flags = IORESOURCE_IRQ,
},
{
/* IRQ for channels 0-5 */
.start = 240,
.end = 245,
.flags = IORESOURCE_IRQ,
},
};
/* Resource order important! */
static struct resource sh7372_dmae1_resources[] = {
{
/* Channel registers and DMAOR */
.start = 0xfe018020,
.end = 0xfe01808f,
.flags = IORESOURCE_MEM,
},
{
/* DMARSx */
.start = 0xfe019000,
.end = 0xfe01900b,
.flags = IORESOURCE_MEM,
},
{
/* DMA error IRQ */
.start = 254,
.end = 254,
.flags = IORESOURCE_IRQ,
},
{
/* IRQ for channels 0-5 */
.start = 248,
.end = 253,
.flags = IORESOURCE_IRQ,
},
};
/* Resource order important! */
static struct resource sh7372_dmae2_resources[] = {
{
/* Channel registers and DMAOR */
.start = 0xfe028020,
.end = 0xfe02808f,
.flags = IORESOURCE_MEM,
},
{
/* DMARSx */
.start = 0xfe029000,
.end = 0xfe02900b,
.flags = IORESOURCE_MEM,
},
{
/* DMA error IRQ */
.start = 262,
.end = 262,
.flags = IORESOURCE_IRQ,
},
{
/* IRQ for channels 0-5 */
.start = 256,
.end = 261,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device dma0_device = {
.name = "sh-dma-engine",
.id = 0,
.resource = sh7372_dmae0_resources,
.num_resources = ARRAY_SIZE(sh7372_dmae0_resources),
.dev = {
.platform_data = &dma_platform_data,
},
};
static struct platform_device dma1_device = {
.name = "sh-dma-engine",
.id = 1,
.resource = sh7372_dmae1_resources,
.num_resources = ARRAY_SIZE(sh7372_dmae1_resources),
.dev = {
.platform_data = &dma_platform_data,
},
};
static struct platform_device dma2_device = {
.name = "sh-dma-engine",
.id = 2,
.resource = sh7372_dmae2_resources,
.num_resources = ARRAY_SIZE(sh7372_dmae2_resources),
.dev = {
.platform_data = &dma_platform_data,
},
};
static struct platform_device *sh7372_early_devices[] __initdata = { static struct platform_device *sh7372_early_devices[] __initdata = {
&scif0_device, &scif0_device,
&scif1_device, &scif1_device,
...@@ -178,6 +526,11 @@ static struct platform_device *sh7372_early_devices[] __initdata = { ...@@ -178,6 +526,11 @@ static struct platform_device *sh7372_early_devices[] __initdata = {
&scif5_device, &scif5_device,
&scif6_device, &scif6_device,
&cmt10_device, &cmt10_device,
&iic0_device,
&iic1_device,
&dma0_device,
&dma1_device,
&dma2_device,
}; };
void __init sh7372_add_standard_devices(void) void __init sh7372_add_standard_devices(void)
...@@ -186,14 +539,8 @@ void __init sh7372_add_standard_devices(void) ...@@ -186,14 +539,8 @@ void __init sh7372_add_standard_devices(void)
ARRAY_SIZE(sh7372_early_devices)); ARRAY_SIZE(sh7372_early_devices));
} }
#define SMSTPCR3 0xe615013c
#define SMSTPCR3_CMT1 (1 << 29)
void __init sh7372_add_early_devices(void) void __init sh7372_add_early_devices(void)
{ {
/* enable clock to CMT1 */
__raw_writel(__raw_readl(SMSTPCR3) & ~SMSTPCR3_CMT1, SMSTPCR3);
early_platform_add_devices(sh7372_early_devices, early_platform_add_devices(sh7372_early_devices,
ARRAY_SIZE(sh7372_early_devices)); ARRAY_SIZE(sh7372_early_devices));
} }
arch/arm/mach-shmobile/setup-sh7377.c
浏览文件 @ 500b9fc9
...@@ -32,11 +32,13 @@ ...@@ -32,11 +32,13 @@
#include <asm/mach-types.h> #include <asm/mach-types.h>
#include <asm/mach/arch.h> #include <asm/mach/arch.h>
/* SCIFA0 */
static struct plat_sci_port scif0_platform_data = { static struct plat_sci_port scif0_platform_data = {
.mapbase = 0xe6c40000, .mapbase = 0xe6c40000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 80, 80, 80, 80 }, .irqs = { evt2irq(0xc00), evt2irq(0xc00),
evt2irq(0xc00), evt2irq(0xc00) },
}; };
static struct platform_device scif0_device = { static struct platform_device scif0_device = {
...@@ -47,11 +49,13 @@ static struct platform_device scif0_device = { ...@@ -47,11 +49,13 @@ static struct platform_device scif0_device = {
}, },
}; };
/* SCIFA1 */
static struct plat_sci_port scif1_platform_data = { static struct plat_sci_port scif1_platform_data = {
.mapbase = 0xe6c50000, .mapbase = 0xe6c50000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 81, 81, 81, 81 }, .irqs = { evt2irq(0xc20), evt2irq(0xc20),
evt2irq(0xc20), evt2irq(0xc20) },
}; };
static struct platform_device scif1_device = { static struct platform_device scif1_device = {
...@@ -62,11 +66,13 @@ static struct platform_device scif1_device = { ...@@ -62,11 +66,13 @@ static struct platform_device scif1_device = {
}, },
}; };
/* SCIFA2 */
static struct plat_sci_port scif2_platform_data = { static struct plat_sci_port scif2_platform_data = {
.mapbase = 0xe6c60000, .mapbase = 0xe6c60000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 82, 82, 82, 82 }, .irqs = { evt2irq(0xc40), evt2irq(0xc40),
evt2irq(0xc40), evt2irq(0xc40) },
}; };
static struct platform_device scif2_device = { static struct platform_device scif2_device = {
...@@ -77,11 +83,13 @@ static struct platform_device scif2_device = { ...@@ -77,11 +83,13 @@ static struct platform_device scif2_device = {
}, },
}; };
/* SCIFA3 */
static struct plat_sci_port scif3_platform_data = { static struct plat_sci_port scif3_platform_data = {
.mapbase = 0xe6c70000, .mapbase = 0xe6c70000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 83, 83, 83, 83 }, .irqs = { evt2irq(0xc60), evt2irq(0xc60),
evt2irq(0xc60), evt2irq(0xc60) },
}; };
static struct platform_device scif3_device = { static struct platform_device scif3_device = {
...@@ -92,11 +100,13 @@ static struct platform_device scif3_device = { ...@@ -92,11 +100,13 @@ static struct platform_device scif3_device = {
}, },
}; };
/* SCIFA4 */
static struct plat_sci_port scif4_platform_data = { static struct plat_sci_port scif4_platform_data = {
.mapbase = 0xe6c80000, .mapbase = 0xe6c80000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 89, 89, 89, 89 }, .irqs = { evt2irq(0xd20), evt2irq(0xd20),
evt2irq(0xd20), evt2irq(0xd20) },
}; };
static struct platform_device scif4_device = { static struct platform_device scif4_device = {
...@@ -107,11 +117,13 @@ static struct platform_device scif4_device = { ...@@ -107,11 +117,13 @@ static struct platform_device scif4_device = {
}, },
}; };
/* SCIFA5 */
static struct plat_sci_port scif5_platform_data = { static struct plat_sci_port scif5_platform_data = {
.mapbase = 0xe6cb0000, .mapbase = 0xe6cb0000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 90, 90, 90, 90 }, .irqs = { evt2irq(0xd40), evt2irq(0xd40),
evt2irq(0xd40), evt2irq(0xd40) },
}; };
static struct platform_device scif5_device = { static struct platform_device scif5_device = {
...@@ -122,11 +134,13 @@ static struct platform_device scif5_device = { ...@@ -122,11 +134,13 @@ static struct platform_device scif5_device = {
}, },
}; };
/* SCIFA6 */
static struct plat_sci_port scif6_platform_data = { static struct plat_sci_port scif6_platform_data = {
.mapbase = 0xe6cc0000, .mapbase = 0xe6cc0000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 196, 196, 196, 196 }, .irqs = { intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80),
intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80) },
}; };
static struct platform_device scif6_device = { static struct platform_device scif6_device = {
...@@ -137,11 +151,13 @@ static struct platform_device scif6_device = { ...@@ -137,11 +151,13 @@ static struct platform_device scif6_device = {
}, },
}; };
/* SCIFB */
static struct plat_sci_port scif7_platform_data = { static struct plat_sci_port scif7_platform_data = {
.mapbase = 0xe6c30000, .mapbase = 0xe6c30000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 91, 91, 91, 91 }, .irqs = { evt2irq(0xd60), evt2irq(0xd60),
evt2irq(0xd60), evt2irq(0xd60) },
}; };
static struct platform_device scif7_device = { static struct platform_device scif7_device = {
...@@ -169,7 +185,7 @@ static struct resource cmt10_resources[] = { ...@@ -169,7 +185,7 @@ static struct resource cmt10_resources[] = {
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
[1] = { [1] = {
.start = 72, .start = evt2irq(0xb00), /* CMT1_CMT10 */
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
}, },
}; };
......
arch/sh/boards/mach-ap325rxa/setup.c
浏览文件 @ 500b9fc9
...@@ -154,7 +154,7 @@ static struct platform_device nand_flash_device = { ...@@ -154,7 +154,7 @@ static struct platform_device nand_flash_device = {
#define PORT_DRVCRA 0xA405018A #define PORT_DRVCRA 0xA405018A
#define PORT_DRVCRB 0xA405018C #define PORT_DRVCRB 0xA405018C
static void ap320_wvga_power_on(void *board_data) static void ap320_wvga_power_on(void *board_data, struct fb_info *info)
{ {
msleep(100); msleep(100);
......
arch/sh/boards/mach-kfr2r09/Makefile
浏览文件 @ 500b9fc9
obj-y := setup.o sdram.o obj-y := setup.o sdram.o
obj-$(CONFIG_FB_SH_MOBILE_LCDC) += lcd_wqvga.o ifneq ($(CONFIG_FB_SH_MOBILE_LCDC),)
obj-y += lcd_wqvga.o
endif
arch/sh/boards/mach-kfr2r09/lcd_wqvga.c
浏览文件 @ 500b9fc9
...@@ -327,7 +327,7 @@ static int kfr2r09_lcd_backlight(int on) ...@@ -327,7 +327,7 @@ static int kfr2r09_lcd_backlight(int on)
return 0; return 0;
} }
void kfr2r09_lcd_on(void *board_data) void kfr2r09_lcd_on(void *board_data, struct fb_info *info)
{ {
kfr2r09_lcd_backlight(1); kfr2r09_lcd_backlight(1);
} }
......
arch/sh/include/mach-kfr2r09/mach/kfr2r09.h
浏览文件 @ 500b9fc9
...@@ -3,22 +3,22 @@ ...@@ -3,22 +3,22 @@
#include <video/sh_mobile_lcdc.h> #include <video/sh_mobile_lcdc.h>
#ifdef CONFIG_FB_SH_MOBILE_LCDC #if defined(CONFIG_FB_SH_MOBILE_LCDC) || defined(CONFIG_FB_SH_MOBILE_LCDC_MODULE)
void kfr2r09_lcd_on(void *board_data); void kfr2r09_lcd_on(void *board_data, struct fb_info *info);
void kfr2r09_lcd_off(void *board_data); void kfr2r09_lcd_off(void *board_data);
int kfr2r09_lcd_setup(void *board_data, void *sys_ops_handle, int kfr2r09_lcd_setup(void *board_data, void *sys_ops_handle,
struct sh_mobile_lcdc_sys_bus_ops *sys_ops); struct sh_mobile_lcdc_sys_bus_ops *sys_ops);
void kfr2r09_lcd_start(void *board_data, void *sys_ops_handle, void kfr2r09_lcd_start(void *board_data, void *sys_ops_handle,
struct sh_mobile_lcdc_sys_bus_ops *sys_ops); struct sh_mobile_lcdc_sys_bus_ops *sys_ops);
#else #else
static inline void kfr2r09_lcd_on(void *board_data) {} static void kfr2r09_lcd_on(void *board_data) {}
static inline void kfr2r09_lcd_off(void *board_data) {} static void kfr2r09_lcd_off(void *board_data) {}
static inline int kfr2r09_lcd_setup(void *board_data, void *sys_ops_handle, static int kfr2r09_lcd_setup(void *board_data, void *sys_ops_handle,
struct sh_mobile_lcdc_sys_bus_ops *sys_ops) struct sh_mobile_lcdc_sys_bus_ops *sys_ops)
{ {
return -ENODEV; return -ENODEV;
} }
static inline void kfr2r09_lcd_start(void *board_data, void *sys_ops_handle, static void kfr2r09_lcd_start(void *board_data, void *sys_ops_handle,
struct sh_mobile_lcdc_sys_bus_ops *sys_ops) struct sh_mobile_lcdc_sys_bus_ops *sys_ops)
{ {
} }
......
drivers/dma/Kconfig
浏览文件 @ 500b9fc9
...@@ -128,7 +128,7 @@ config TXX9_DMAC ...@@ -128,7 +128,7 @@ config TXX9_DMAC
config SH_DMAE config SH_DMAE
tristate "Renesas SuperH DMAC support" tristate "Renesas SuperH DMAC support"
depends on SUPERH && SH_DMA depends on (SUPERH && SH_DMA) || (ARM && ARCH_SHMOBILE)
depends on !SH_DMA_API depends on !SH_DMA_API
select DMA_ENGINE select DMA_ENGINE
help help
......
drivers/dma/shdma.c
浏览文件 @ 500b9fc9
...@@ -816,7 +816,7 @@ static irqreturn_t sh_dmae_interrupt(int irq, void *data) ...@@ -816,7 +816,7 @@ static irqreturn_t sh_dmae_interrupt(int irq, void *data)
return ret; return ret;
} }
#if defined(CONFIG_CPU_SH4) #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
static irqreturn_t sh_dmae_err(int irq, void *data) static irqreturn_t sh_dmae_err(int irq, void *data)
{ {
struct sh_dmae_device *shdev = (struct sh_dmae_device *)data; struct sh_dmae_device *shdev = (struct sh_dmae_device *)data;
...@@ -1057,7 +1057,7 @@ static int __init sh_dmae_probe(struct platform_device *pdev) ...@@ -1057,7 +1057,7 @@ static int __init sh_dmae_probe(struct platform_device *pdev)
/* Default transfer size of 32 bytes requires 32-byte alignment */ /* Default transfer size of 32 bytes requires 32-byte alignment */
shdev->common.copy_align = LOG2_DEFAULT_XFER_SIZE; shdev->common.copy_align = LOG2_DEFAULT_XFER_SIZE;
#if defined(CONFIG_CPU_SH4) #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
chanirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 1); chanirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
if (!chanirq_res) if (!chanirq_res)
...@@ -1082,7 +1082,7 @@ static int __init sh_dmae_probe(struct platform_device *pdev) ...@@ -1082,7 +1082,7 @@ static int __init sh_dmae_probe(struct platform_device *pdev)
#else #else
chanirq_res = errirq_res; chanirq_res = errirq_res;
#endif /* CONFIG_CPU_SH4 */ #endif /* CONFIG_CPU_SH4 || CONFIG_ARCH_SHMOBILE */
if (chanirq_res->start == chanirq_res->end && if (chanirq_res->start == chanirq_res->end &&
!platform_get_resource(pdev, IORESOURCE_IRQ, 1)) { !platform_get_resource(pdev, IORESOURCE_IRQ, 1)) {
...@@ -1129,7 +1129,7 @@ static int __init sh_dmae_probe(struct platform_device *pdev) ...@@ -1129,7 +1129,7 @@ static int __init sh_dmae_probe(struct platform_device *pdev)
chan_probe_err: chan_probe_err:
sh_dmae_chan_remove(shdev); sh_dmae_chan_remove(shdev);
eirqres: eirqres:
#if defined(CONFIG_CPU_SH4) #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
free_irq(errirq, shdev); free_irq(errirq, shdev);
eirq_err: eirq_err:
#endif #endif
......
drivers/i2c/busses/Kconfig
浏览文件 @ 500b9fc9
...@@ -549,7 +549,7 @@ config I2C_SH7760 ...@@ -549,7 +549,7 @@ config I2C_SH7760
config I2C_SH_MOBILE config I2C_SH_MOBILE
tristate "SuperH Mobile I2C Controller" tristate "SuperH Mobile I2C Controller"
depends on SUPERH depends on SUPERH || ARCH_SHMOBILE
help help
If you say yes to this option, support will be included for the If you say yes to this option, support will be included for the
built-in I2C interface on the Renesas SH-Mobile processor. built-in I2C interface on the Renesas SH-Mobile processor.
......
drivers/i2c/busses/i2c-sh_mobile.c
浏览文件 @ 500b9fc9
...@@ -119,8 +119,10 @@ struct sh_mobile_i2c_data { ...@@ -119,8 +119,10 @@ struct sh_mobile_i2c_data {
struct i2c_adapter adap; struct i2c_adapter adap;
struct clk *clk; struct clk *clk;
u_int8_t icic;
u_int8_t iccl; u_int8_t iccl;
u_int8_t icch; u_int8_t icch;
u_int8_t flags;
spinlock_t lock; spinlock_t lock;
wait_queue_head_t wait; wait_queue_head_t wait;
...@@ -129,15 +131,17 @@ struct sh_mobile_i2c_data { ...@@ -129,15 +131,17 @@ struct sh_mobile_i2c_data {
int sr; int sr;
}; };
#define IIC_FLAG_HAS_ICIC67 (1 << 0)
#define NORMAL_SPEED 100000 /* FAST_SPEED 400000 */ #define NORMAL_SPEED 100000 /* FAST_SPEED 400000 */
/* Register offsets */ /* Register offsets */
#define ICDR(pd) (pd->reg + 0x00) #define ICDR 0x00
#define ICCR(pd) (pd->reg + 0x04) #define ICCR 0x04
#define ICSR(pd) (pd->reg + 0x08) #define ICSR 0x08
#define ICIC(pd) (pd->reg + 0x0c) #define ICIC 0x0c
#define ICCL(pd) (pd->reg + 0x10) #define ICCL 0x10
#define ICCH(pd) (pd->reg + 0x14) #define ICCH 0x14
/* Register bits */ /* Register bits */
#define ICCR_ICE 0x80 #define ICCR_ICE 0x80
...@@ -155,11 +159,32 @@ struct sh_mobile_i2c_data { ...@@ -155,11 +159,32 @@ struct sh_mobile_i2c_data {
#define ICSR_WAIT 0x02 #define ICSR_WAIT 0x02
#define ICSR_DTE 0x01 #define ICSR_DTE 0x01
#define ICIC_ICCLB8 0x80
#define ICIC_ICCHB8 0x40
#define ICIC_ALE 0x08 #define ICIC_ALE 0x08
#define ICIC_TACKE 0x04 #define ICIC_TACKE 0x04
#define ICIC_WAITE 0x02 #define ICIC_WAITE 0x02
#define ICIC_DTEE 0x01 #define ICIC_DTEE 0x01
static void iic_wr(struct sh_mobile_i2c_data *pd, int offs, unsigned char data)
{
if (offs == ICIC)
data |= pd->icic;
iowrite8(data, pd->reg + offs);
}
static unsigned char iic_rd(struct sh_mobile_i2c_data *pd, int offs)
{
return ioread8(pd->reg + offs);
}
static void iic_set_clr(struct sh_mobile_i2c_data *pd, int offs,
unsigned char set, unsigned char clr)
{
iic_wr(pd, offs, (iic_rd(pd, offs) | set) & ~clr);
}
static void activate_ch(struct sh_mobile_i2c_data *pd) static void activate_ch(struct sh_mobile_i2c_data *pd)
{ {
unsigned long i2c_clk; unsigned long i2c_clk;
...@@ -187,6 +212,14 @@ static void activate_ch(struct sh_mobile_i2c_data *pd) ...@@ -187,6 +212,14 @@ static void activate_ch(struct sh_mobile_i2c_data *pd)
else else
pd->iccl = (u_int8_t)(num/denom); pd->iccl = (u_int8_t)(num/denom);
/* one more bit of ICCL in ICIC */
if (pd->flags & IIC_FLAG_HAS_ICIC67) {
if ((num/denom) > 0xff)
pd->icic |= ICIC_ICCLB8;
else
pd->icic &= ~ICIC_ICCLB8;
}
/* Calculate the value for icch. From the data sheet: /* Calculate the value for icch. From the data sheet:
icch = (p clock / transfer rate) * (H / (L + H)) */ icch = (p clock / transfer rate) * (H / (L + H)) */
num = i2c_clk * 4; num = i2c_clk * 4;
...@@ -196,25 +229,33 @@ static void activate_ch(struct sh_mobile_i2c_data *pd) ...@@ -196,25 +229,33 @@ static void activate_ch(struct sh_mobile_i2c_data *pd)
else else
pd->icch = (u_int8_t)(num/denom); pd->icch = (u_int8_t)(num/denom);
/* one more bit of ICCH in ICIC */
if (pd->flags & IIC_FLAG_HAS_ICIC67) {
if ((num/denom) > 0xff)
pd->icic |= ICIC_ICCHB8;
else
pd->icic &= ~ICIC_ICCHB8;
}
/* Enable channel and configure rx ack */ /* Enable channel and configure rx ack */
iowrite8(ioread8(ICCR(pd)) | ICCR_ICE, ICCR(pd)); iic_set_clr(pd, ICCR, ICCR_ICE, 0);
/* Mask all interrupts */ /* Mask all interrupts */
iowrite8(0, ICIC(pd)); iic_wr(pd, ICIC, 0);
/* Set the clock */ /* Set the clock */
iowrite8(pd->iccl, ICCL(pd)); iic_wr(pd, ICCL, pd->iccl);
iowrite8(pd->icch, ICCH(pd)); iic_wr(pd, ICCH, pd->icch);
} }
static void deactivate_ch(struct sh_mobile_i2c_data *pd) static void deactivate_ch(struct sh_mobile_i2c_data *pd)
{ {
/* Clear/disable interrupts */ /* Clear/disable interrupts */
iowrite8(0, ICSR(pd)); iic_wr(pd, ICSR, 0);
iowrite8(0, ICIC(pd)); iic_wr(pd, ICIC, 0);
/* Disable channel */ /* Disable channel */
iowrite8(ioread8(ICCR(pd)) & ~ICCR_ICE, ICCR(pd)); iic_set_clr(pd, ICCR, 0, ICCR_ICE);
/* Disable clock and mark device as idle */ /* Disable clock and mark device as idle */
clk_disable(pd->clk); clk_disable(pd->clk);
...@@ -233,35 +274,35 @@ static unsigned char i2c_op(struct sh_mobile_i2c_data *pd, ...@@ -233,35 +274,35 @@ static unsigned char i2c_op(struct sh_mobile_i2c_data *pd,
switch (op) { switch (op) {
case OP_START: /* issue start and trigger DTE interrupt */ case OP_START: /* issue start and trigger DTE interrupt */
iowrite8(0x94, ICCR(pd)); iic_wr(pd, ICCR, 0x94);
break; break;
case OP_TX_FIRST: /* disable DTE interrupt and write data */ case OP_TX_FIRST: /* disable DTE interrupt and write data */
iowrite8(ICIC_WAITE | ICIC_ALE | ICIC_TACKE, ICIC(pd)); iic_wr(pd, ICIC, ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
iowrite8(data, ICDR(pd)); iic_wr(pd, ICDR, data);
break; break;
case OP_TX: /* write data */ case OP_TX: /* write data */
iowrite8(data, ICDR(pd)); iic_wr(pd, ICDR, data);
break; break;
case OP_TX_STOP: /* write data and issue a stop afterwards */ case OP_TX_STOP: /* write data and issue a stop afterwards */
iowrite8(data, ICDR(pd)); iic_wr(pd, ICDR, data);
iowrite8(0x90, ICCR(pd)); iic_wr(pd, ICCR, 0x90);
break; break;
case OP_TX_TO_RX: /* select read mode */ case OP_TX_TO_RX: /* select read mode */
iowrite8(0x81, ICCR(pd)); iic_wr(pd, ICCR, 0x81);
break; break;
case OP_RX: /* just read data */ case OP_RX: /* just read data */
ret = ioread8(ICDR(pd)); ret = iic_rd(pd, ICDR);
break; break;
case OP_RX_STOP: /* enable DTE interrupt, issue stop */ case OP_RX_STOP: /* enable DTE interrupt, issue stop */
iowrite8(ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE, iic_wr(pd, ICIC,
ICIC(pd)); ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
iowrite8(0xc0, ICCR(pd)); iic_wr(pd, ICCR, 0xc0);
break; break;
case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */ case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */
iowrite8(ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE, iic_wr(pd, ICIC,
ICIC(pd)); ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
ret = ioread8(ICDR(pd)); ret = iic_rd(pd, ICDR);
iowrite8(0xc0, ICCR(pd)); iic_wr(pd, ICCR, 0xc0);
break; break;
} }
...@@ -367,7 +408,7 @@ static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id) ...@@ -367,7 +408,7 @@ static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
unsigned char sr; unsigned char sr;
int wakeup; int wakeup;
sr = ioread8(ICSR(pd)); sr = iic_rd(pd, ICSR);
pd->sr |= sr; /* remember state */ pd->sr |= sr; /* remember state */
dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr, dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr,
...@@ -376,7 +417,7 @@ static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id) ...@@ -376,7 +417,7 @@ static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
if (sr & (ICSR_AL | ICSR_TACK)) { if (sr & (ICSR_AL | ICSR_TACK)) {
/* don't interrupt transaction - continue to issue stop */ /* don't interrupt transaction - continue to issue stop */
iowrite8(sr & ~(ICSR_AL | ICSR_TACK), ICSR(pd)); iic_wr(pd, ICSR, sr & ~(ICSR_AL | ICSR_TACK));
wakeup = 0; wakeup = 0;
} else if (pd->msg->flags & I2C_M_RD) } else if (pd->msg->flags & I2C_M_RD)
wakeup = sh_mobile_i2c_isr_rx(pd); wakeup = sh_mobile_i2c_isr_rx(pd);
...@@ -384,7 +425,7 @@ static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id) ...@@ -384,7 +425,7 @@ static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
wakeup = sh_mobile_i2c_isr_tx(pd); wakeup = sh_mobile_i2c_isr_tx(pd);
if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */ if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */
iowrite8(sr & ~ICSR_WAIT, ICSR(pd)); iic_wr(pd, ICSR, sr & ~ICSR_WAIT);
if (wakeup) { if (wakeup) {
pd->sr |= SW_DONE; pd->sr |= SW_DONE;
...@@ -402,21 +443,21 @@ static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg) ...@@ -402,21 +443,21 @@ static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg)
} }
/* Initialize channel registers */ /* Initialize channel registers */
iowrite8(ioread8(ICCR(pd)) & ~ICCR_ICE, ICCR(pd)); iic_set_clr(pd, ICCR, 0, ICCR_ICE);
/* Enable channel and configure rx ack */ /* Enable channel and configure rx ack */
iowrite8(ioread8(ICCR(pd)) | ICCR_ICE, ICCR(pd)); iic_set_clr(pd, ICCR, ICCR_ICE, 0);
/* Set the clock */ /* Set the clock */
iowrite8(pd->iccl, ICCL(pd)); iic_wr(pd, ICCL, pd->iccl);
iowrite8(pd->icch, ICCH(pd)); iic_wr(pd, ICCH, pd->icch);
pd->msg = usr_msg; pd->msg = usr_msg;
pd->pos = -1; pd->pos = -1;
pd->sr = 0; pd->sr = 0;
/* Enable all interrupts to begin with */ /* Enable all interrupts to begin with */
iowrite8(ICIC_WAITE | ICIC_ALE | ICIC_TACKE | ICIC_DTEE, ICIC(pd)); iic_wr(pd, ICIC, ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
return 0; return 0;
} }
...@@ -451,7 +492,7 @@ static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter, ...@@ -451,7 +492,7 @@ static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
retry_count = 1000; retry_count = 1000;
again: again:
val = ioread8(ICSR(pd)); val = iic_rd(pd, ICSR);
dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr); dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr);
...@@ -576,6 +617,12 @@ static int sh_mobile_i2c_probe(struct platform_device *dev) ...@@ -576,6 +617,12 @@ static int sh_mobile_i2c_probe(struct platform_device *dev)
goto err_irq; goto err_irq;
} }
/* The IIC blocks on SH-Mobile ARM processors
* come with two new bits in ICIC.
*/
if (size > 0x17)
pd->flags |= IIC_FLAG_HAS_ICIC67;
/* Enable Runtime PM for this device. /* Enable Runtime PM for this device.
* *
* Also tell the Runtime PM core to ignore children * Also tell the Runtime PM core to ignore children
......
drivers/net/irda/sh_irda.c
浏览文件 @ 500b9fc9
...@@ -748,7 +748,6 @@ static int __devinit sh_irda_probe(struct platform_device *pdev) ...@@ -748,7 +748,6 @@ static int __devinit sh_irda_probe(struct platform_device *pdev)
struct net_device *ndev; struct net_device *ndev;
struct sh_irda_self *self; struct sh_irda_self *self;
struct resource *res; struct resource *res;
char clk_name[8];
int irq; int irq;
int err = -ENOMEM; int err = -ENOMEM;
...@@ -775,10 +774,9 @@ static int __devinit sh_irda_probe(struct platform_device *pdev) ...@@ -775,10 +774,9 @@ static int __devinit sh_irda_probe(struct platform_device *pdev)
if (err) if (err)
goto err_mem_2; goto err_mem_2;
snprintf(clk_name, sizeof(clk_name), "irda%d", pdev->id); self->clk = clk_get(&pdev->dev, NULL);
self->clk = clk_get(&pdev->dev, clk_name);
if (IS_ERR(self->clk)) { if (IS_ERR(self->clk)) {
dev_err(&pdev->dev, "cannot get clock \"%s\"\n", clk_name); dev_err(&pdev->dev, "cannot get irda clock\n");
goto err_mem_3; goto err_mem_3;
} }
......
drivers/serial/sh-sci.c
浏览文件 @ 500b9fc9
...@@ -346,6 +346,27 @@ static int scif_rxfill(struct uart_port *port) ...@@ -346,6 +346,27 @@ static int scif_rxfill(struct uart_port *port)
return sci_in(port, SCFDR) & SCIF2_RFDC_MASK; return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
} }
} }
#elif defined(CONFIG_ARCH_SH7372)
static int scif_txfill(struct uart_port *port)
{
if (port->type == PORT_SCIFA)
return sci_in(port, SCFDR) >> 8;
else
return sci_in(port, SCTFDR);
}
static int scif_txroom(struct uart_port *port)
{
return port->fifosize - scif_txfill(port);
}
static int scif_rxfill(struct uart_port *port)
{
if (port->type == PORT_SCIFA)
return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
else
return sci_in(port, SCRFDR);
}
#else #else
static int scif_txfill(struct uart_port *port) static int scif_txfill(struct uart_port *port)
{ {
...@@ -683,7 +704,7 @@ static irqreturn_t sci_rx_interrupt(int irq, void *ptr) ...@@ -683,7 +704,7 @@ static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
u16 ssr = sci_in(port, SCxSR); u16 ssr = sci_in(port, SCxSR);
/* Disable future Rx interrupts */ /* Disable future Rx interrupts */
if (port->type == PORT_SCIFA) { if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
disable_irq_nosync(irq); disable_irq_nosync(irq);
scr |= 0x4000; scr |= 0x4000;
} else { } else {
...@@ -928,7 +949,7 @@ static void sci_dma_tx_complete(void *arg) ...@@ -928,7 +949,7 @@ static void sci_dma_tx_complete(void *arg)
if (!uart_circ_empty(xmit)) { if (!uart_circ_empty(xmit)) {
schedule_work(&s->work_tx); schedule_work(&s->work_tx);
} else if (port->type == PORT_SCIFA) { } else if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
u16 ctrl = sci_in(port, SCSCR); u16 ctrl = sci_in(port, SCSCR);
sci_out(port, SCSCR, ctrl & ~SCI_CTRL_FLAGS_TIE); sci_out(port, SCSCR, ctrl & ~SCI_CTRL_FLAGS_TIE);
} }
...@@ -1184,7 +1205,7 @@ static void sci_start_tx(struct uart_port *port) ...@@ -1184,7 +1205,7 @@ static void sci_start_tx(struct uart_port *port)
unsigned short ctrl; unsigned short ctrl;
#ifdef CONFIG_SERIAL_SH_SCI_DMA #ifdef CONFIG_SERIAL_SH_SCI_DMA
if (port->type == PORT_SCIFA) { if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
u16 new, scr = sci_in(port, SCSCR); u16 new, scr = sci_in(port, SCSCR);
if (s->chan_tx) if (s->chan_tx)
new = scr | 0x8000; new = scr | 0x8000;
...@@ -1197,7 +1218,7 @@ static void sci_start_tx(struct uart_port *port) ...@@ -1197,7 +1218,7 @@ static void sci_start_tx(struct uart_port *port)
s->cookie_tx < 0) s->cookie_tx < 0)
schedule_work(&s->work_tx); schedule_work(&s->work_tx);
#endif #endif
if (!s->chan_tx || port->type == PORT_SCIFA) { if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
/* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
ctrl = sci_in(port, SCSCR); ctrl = sci_in(port, SCSCR);
sci_out(port, SCSCR, ctrl | SCI_CTRL_FLAGS_TIE); sci_out(port, SCSCR, ctrl | SCI_CTRL_FLAGS_TIE);
...@@ -1210,7 +1231,7 @@ static void sci_stop_tx(struct uart_port *port) ...@@ -1210,7 +1231,7 @@ static void sci_stop_tx(struct uart_port *port)
/* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
ctrl = sci_in(port, SCSCR); ctrl = sci_in(port, SCSCR);
if (port->type == PORT_SCIFA) if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
ctrl &= ~0x8000; ctrl &= ~0x8000;
ctrl &= ~SCI_CTRL_FLAGS_TIE; ctrl &= ~SCI_CTRL_FLAGS_TIE;
sci_out(port, SCSCR, ctrl); sci_out(port, SCSCR, ctrl);
...@@ -1222,7 +1243,7 @@ static void sci_start_rx(struct uart_port *port) ...@@ -1222,7 +1243,7 @@ static void sci_start_rx(struct uart_port *port)
/* Set RIE (Receive Interrupt Enable) bit in SCSCR */ /* Set RIE (Receive Interrupt Enable) bit in SCSCR */
ctrl |= sci_in(port, SCSCR); ctrl |= sci_in(port, SCSCR);
if (port->type == PORT_SCIFA) if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
ctrl &= ~0x4000; ctrl &= ~0x4000;
sci_out(port, SCSCR, ctrl); sci_out(port, SCSCR, ctrl);
} }
...@@ -1233,7 +1254,7 @@ static void sci_stop_rx(struct uart_port *port) ...@@ -1233,7 +1254,7 @@ static void sci_stop_rx(struct uart_port *port)
/* Clear RIE (Receive Interrupt Enable) bit in SCSCR */ /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */
ctrl = sci_in(port, SCSCR); ctrl = sci_in(port, SCSCR);
if (port->type == PORT_SCIFA) if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
ctrl &= ~0x4000; ctrl &= ~0x4000;
ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE); ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE);
sci_out(port, SCSCR, ctrl); sci_out(port, SCSCR, ctrl);
...@@ -1271,7 +1292,7 @@ static void rx_timer_fn(unsigned long arg) ...@@ -1271,7 +1292,7 @@ static void rx_timer_fn(unsigned long arg)
struct uart_port *port = &s->port; struct uart_port *port = &s->port;
u16 scr = sci_in(port, SCSCR); u16 scr = sci_in(port, SCSCR);
if (port->type == PORT_SCIFA) { if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
scr &= ~0x4000; scr &= ~0x4000;
enable_irq(s->irqs[1]); enable_irq(s->irqs[1]);
} }
...@@ -1524,6 +1545,8 @@ static const char *sci_type(struct uart_port *port) ...@@ -1524,6 +1545,8 @@ static const char *sci_type(struct uart_port *port)
return "scif"; return "scif";
case PORT_SCIFA: case PORT_SCIFA:
return "scifa"; return "scifa";
case PORT_SCIFB:
return "scifb";
} }
return NULL; return NULL;
...@@ -1612,6 +1635,9 @@ static int __devinit sci_init_single(struct platform_device *dev, ...@@ -1612,6 +1635,9 @@ static int __devinit sci_init_single(struct platform_device *dev,
port->line = index; port->line = index;
switch (p->type) { switch (p->type) {
case PORT_SCIFB:
port->fifosize = 256;
break;
case PORT_SCIFA: case PORT_SCIFA:
port->fifosize = 64; port->fifosize = 64;
break; break;
......
drivers/serial/sh-sci.h
浏览文件 @ 500b9fc9
...@@ -322,7 +322,7 @@ ...@@ -322,7 +322,7 @@
#define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\ #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
static inline unsigned int sci_##name##_in(struct uart_port *port) \ static inline unsigned int sci_##name##_in(struct uart_port *port) \
{ \ { \
if (port->type == PORT_SCIF) { \ if (port->type == PORT_SCIF || port->type == PORT_SCIFB) { \
SCI_IN(scif_size, scif_offset) \ SCI_IN(scif_size, scif_offset) \
} else { /* PORT_SCI or PORT_SCIFA */ \ } else { /* PORT_SCI or PORT_SCIFA */ \
SCI_IN(sci_size, sci_offset); \ SCI_IN(sci_size, sci_offset); \
...@@ -330,7 +330,7 @@ ...@@ -330,7 +330,7 @@
} \ } \
static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \ static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
{ \ { \
if (port->type == PORT_SCIF) { \ if (port->type == PORT_SCIF || port->type == PORT_SCIFB) { \
SCI_OUT(scif_size, scif_offset, value) \ SCI_OUT(scif_size, scif_offset, value) \
} else { /* PORT_SCI or PORT_SCIFA */ \ } else { /* PORT_SCI or PORT_SCIFA */ \
SCI_OUT(sci_size, sci_offset, value); \ SCI_OUT(sci_size, sci_offset, value); \
...@@ -384,8 +384,12 @@ ...@@ -384,8 +384,12 @@
defined(CONFIG_CPU_SUBTYPE_SH7720) || \ defined(CONFIG_CPU_SUBTYPE_SH7720) || \
defined(CONFIG_CPU_SUBTYPE_SH7721) || \ defined(CONFIG_CPU_SUBTYPE_SH7721) || \
defined(CONFIG_ARCH_SH7367) || \ defined(CONFIG_ARCH_SH7367) || \
defined(CONFIG_ARCH_SH7377) || \ defined(CONFIG_ARCH_SH7377)
defined(CONFIG_ARCH_SH7372) #define SCIF_FNS(name, scif_offset, scif_size) \
CPU_SCIF_FNS(name, scif_offset, scif_size)
#elif defined(CONFIG_ARCH_SH7372)
#define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scifb_offset, sh4_scifb_size) \
CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scifb_offset, sh4_scifb_size)
#define SCIF_FNS(name, scif_offset, scif_size) \ #define SCIF_FNS(name, scif_offset, scif_size) \
CPU_SCIF_FNS(name, scif_offset, scif_size) CPU_SCIF_FNS(name, scif_offset, scif_size)
#else #else
...@@ -422,8 +426,7 @@ ...@@ -422,8 +426,7 @@
defined(CONFIG_CPU_SUBTYPE_SH7720) || \ defined(CONFIG_CPU_SUBTYPE_SH7720) || \
defined(CONFIG_CPU_SUBTYPE_SH7721) || \ defined(CONFIG_CPU_SUBTYPE_SH7721) || \
defined(CONFIG_ARCH_SH7367) || \ defined(CONFIG_ARCH_SH7367) || \
defined(CONFIG_ARCH_SH7377) || \ defined(CONFIG_ARCH_SH7377)
defined(CONFIG_ARCH_SH7372)
SCIF_FNS(SCSMR, 0x00, 16) SCIF_FNS(SCSMR, 0x00, 16)
SCIF_FNS(SCBRR, 0x04, 8) SCIF_FNS(SCBRR, 0x04, 8)
...@@ -436,6 +439,20 @@ SCIF_FNS(SCFDR, 0x1c, 16) ...@@ -436,6 +439,20 @@ SCIF_FNS(SCFDR, 0x1c, 16)
SCIF_FNS(SCxTDR, 0x20, 8) SCIF_FNS(SCxTDR, 0x20, 8)
SCIF_FNS(SCxRDR, 0x24, 8) SCIF_FNS(SCxRDR, 0x24, 8)
SCIF_FNS(SCLSR, 0x00, 0) SCIF_FNS(SCLSR, 0x00, 0)
#elif defined(CONFIG_ARCH_SH7372)
SCIF_FNS(SCSMR, 0x00, 16)
SCIF_FNS(SCBRR, 0x04, 8)
SCIF_FNS(SCSCR, 0x08, 16)
SCIF_FNS(SCTDSR, 0x0c, 16)
SCIF_FNS(SCFER, 0x10, 16)
SCIF_FNS(SCxSR, 0x14, 16)
SCIF_FNS(SCFCR, 0x18, 16)
SCIF_FNS(SCFDR, 0x1c, 16)
SCIF_FNS(SCTFDR, 0x38, 16)
SCIF_FNS(SCRFDR, 0x3c, 16)
SCIx_FNS(SCxTDR, 0x20, 8, 0x40, 8)
SCIx_FNS(SCxRDR, 0x24, 8, 0x60, 8)
SCIF_FNS(SCLSR, 0x00, 0)
#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\ #elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
defined(CONFIG_CPU_SUBTYPE_SH7724) defined(CONFIG_CPU_SUBTYPE_SH7724)
SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16) SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16)
......
drivers/sh/Makefile
浏览文件 @ 500b9fc9
# #
# Makefile for the SuperH specific drivers. # Makefile for the SuperH specific drivers.
# #
obj-y := clk.o intc.o
obj-$(CONFIG_SUPERHYWAY) += superhyway/ obj-$(CONFIG_SUPERHYWAY) += superhyway/
obj-$(CONFIG_MAPLE) += maple/ obj-$(CONFIG_MAPLE) += maple/
obj-$(CONFIG_GENERIC_GPIO) += pfc.o obj-$(CONFIG_GENERIC_GPIO) += pfc.o
obj-$(CONFIG_SUPERH) += clk.o
obj-$(CONFIG_SH_CLK_CPG) += clk-cpg.o obj-$(CONFIG_SH_CLK_CPG) += clk-cpg.o
obj-y += intc.o
drivers/sh/clk-cpg.c
浏览文件 @ 500b9fc9
...@@ -68,6 +68,39 @@ static unsigned long sh_clk_div6_recalc(struct clk *clk) ...@@ -68,6 +68,39 @@ static unsigned long sh_clk_div6_recalc(struct clk *clk)
return clk->freq_table[idx].frequency; return clk->freq_table[idx].frequency;
} }
static int sh_clk_div6_set_parent(struct clk *clk, struct clk *parent)
{
struct clk_div_mult_table *table = &sh_clk_div6_table;
u32 value;
int ret, i;
if (!clk->parent_table || !clk->parent_num)
return -EINVAL;
/* Search the parent */
for (i = 0; i < clk->parent_num; i++)
if (clk->parent_table[i] == parent)
break;
if (i == clk->parent_num)
return -ENODEV;
ret = clk_reparent(clk, parent);
if (ret < 0)
return ret;
value = __raw_readl(clk->enable_reg) &
~(((1 << clk->src_width) - 1) << clk->src_shift);
__raw_writel(value | (i << clk->src_shift), clk->enable_reg);
/* Rebuild the frequency table */
clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
table, &clk->arch_flags);
return 0;
}
static int sh_clk_div6_set_rate(struct clk *clk, static int sh_clk_div6_set_rate(struct clk *clk,
unsigned long rate, int algo_id) unsigned long rate, int algo_id)
{ {
...@@ -117,7 +150,17 @@ static struct clk_ops sh_clk_div6_clk_ops = { ...@@ -117,7 +150,17 @@ static struct clk_ops sh_clk_div6_clk_ops = {
.disable = sh_clk_div6_disable, .disable = sh_clk_div6_disable,
}; };
int __init sh_clk_div6_register(struct clk *clks, int nr) static struct clk_ops sh_clk_div6_reparent_clk_ops = {
.recalc = sh_clk_div6_recalc,
.round_rate = sh_clk_div_round_rate,
.set_rate = sh_clk_div6_set_rate,
.enable = sh_clk_div6_enable,
.disable = sh_clk_div6_disable,
.set_parent = sh_clk_div6_set_parent,
};
static int __init sh_clk_div6_register_ops(struct clk *clks, int nr,
struct clk_ops *ops)
{ {
struct clk *clkp; struct clk *clkp;
void *freq_table; void *freq_table;
...@@ -136,7 +179,7 @@ int __init sh_clk_div6_register(struct clk *clks, int nr) ...@@ -136,7 +179,7 @@ int __init sh_clk_div6_register(struct clk *clks, int nr)
for (k = 0; !ret && (k < nr); k++) { for (k = 0; !ret && (k < nr); k++) {
clkp = clks + k; clkp = clks + k;
clkp->ops = &sh_clk_div6_clk_ops; clkp->ops = ops;
clkp->id = -1; clkp->id = -1;
clkp->freq_table = freq_table + (k * freq_table_size); clkp->freq_table = freq_table + (k * freq_table_size);
clkp->freq_table[nr_divs].frequency = CPUFREQ_TABLE_END; clkp->freq_table[nr_divs].frequency = CPUFREQ_TABLE_END;
...@@ -147,6 +190,17 @@ int __init sh_clk_div6_register(struct clk *clks, int nr) ...@@ -147,6 +190,17 @@ int __init sh_clk_div6_register(struct clk *clks, int nr)
return ret; return ret;
} }
int __init sh_clk_div6_register(struct clk *clks, int nr)
{
return sh_clk_div6_register_ops(clks, nr, &sh_clk_div6_clk_ops);
}
int __init sh_clk_div6_reparent_register(struct clk *clks, int nr)
{
return sh_clk_div6_register_ops(clks, nr,
&sh_clk_div6_reparent_clk_ops);
}
static unsigned long sh_clk_div4_recalc(struct clk *clk) static unsigned long sh_clk_div4_recalc(struct clk *clk)
{ {
struct clk_div4_table *d4t = clk->priv; struct clk_div4_table *d4t = clk->priv;
......
drivers/video/Kconfig
浏览文件 @ 500b9fc9
...@@ -1896,6 +1896,13 @@ config FB_W100 ...@@ -1896,6 +1896,13 @@ config FB_W100
If unsure, say N. If unsure, say N.
config SH_MIPI_DSI
tristate
depends on (SUPERH || ARCH_SHMOBILE) && HAVE_CLK
config SH_LCD_MIPI_DSI
bool
config FB_SH_MOBILE_LCDC config FB_SH_MOBILE_LCDC
tristate "SuperH Mobile LCDC framebuffer support" tristate "SuperH Mobile LCDC framebuffer support"
depends on FB && (SUPERH || ARCH_SHMOBILE) && HAVE_CLK depends on FB && (SUPERH || ARCH_SHMOBILE) && HAVE_CLK
...@@ -1904,9 +1911,17 @@ config FB_SH_MOBILE_LCDC ...@@ -1904,9 +1911,17 @@ config FB_SH_MOBILE_LCDC
select FB_SYS_IMAGEBLIT select FB_SYS_IMAGEBLIT
select FB_SYS_FOPS select FB_SYS_FOPS
select FB_DEFERRED_IO select FB_DEFERRED_IO
select SH_MIPI_DSI if SH_LCD_MIPI_DSI
---help--- ---help---
Frame buffer driver for the on-chip SH-Mobile LCD controller. Frame buffer driver for the on-chip SH-Mobile LCD controller.
config FB_SH_MOBILE_HDMI
tristate "SuperH Mobile HDMI controller support"
depends on FB_SH_MOBILE_LCDC
select FB_MODE_HELPERS
---help---
Driver for the on-chip SH-Mobile HDMI controller.
config FB_TMIO config FB_TMIO
tristate "Toshiba Mobile IO FrameBuffer support" tristate "Toshiba Mobile IO FrameBuffer support"
depends on FB && MFD_CORE depends on FB && MFD_CORE
......
drivers/video/Makefile
浏览文件 @ 500b9fc9
...@@ -123,6 +123,8 @@ obj-$(CONFIG_FB_IBM_GXT4500) += gxt4500.o ...@@ -123,6 +123,8 @@ obj-$(CONFIG_FB_IBM_GXT4500) += gxt4500.o
obj-$(CONFIG_FB_PS3) += ps3fb.o obj-$(CONFIG_FB_PS3) += ps3fb.o
obj-$(CONFIG_FB_SM501) += sm501fb.o obj-$(CONFIG_FB_SM501) += sm501fb.o
obj-$(CONFIG_FB_XILINX) += xilinxfb.o obj-$(CONFIG_FB_XILINX) += xilinxfb.o
obj-$(CONFIG_SH_MIPI_DSI) += sh_mipi_dsi.o
obj-$(CONFIG_FB_SH_MOBILE_HDMI) += sh_mobile_hdmi.o
obj-$(CONFIG_FB_SH_MOBILE_LCDC) += sh_mobile_lcdcfb.o obj-$(CONFIG_FB_SH_MOBILE_LCDC) += sh_mobile_lcdcfb.o
obj-$(CONFIG_FB_OMAP) += omap/ obj-$(CONFIG_FB_OMAP) += omap/
obj-y += omap2/ obj-y += omap2/
......
drivers/video/sh_mipi_dsi.c 0 → 100644
浏览文件 @ 500b9fc9
此差异已折叠。
drivers/video/sh_mobile_hdmi.c 0 → 100644
浏览文件 @ 500b9fc9
此差异已折叠。
drivers/video/sh_mobile_lcdcfb.c
浏览文件 @ 500b9fc9
此差异已折叠。
include/linux/serial_core.h
浏览文件 @ 500b9fc9
...@@ -186,6 +186,9 @@ ...@@ -186,6 +186,9 @@
#define PORT_ALTERA_JTAGUART 91 #define PORT_ALTERA_JTAGUART 91
#define PORT_ALTERA_UART 92 #define PORT_ALTERA_UART 92
/* SH-SCI */
#define PORT_SCIFB 93
#ifdef __KERNEL__ #ifdef __KERNEL__
#include <linux/compiler.h> #include <linux/compiler.h>
......
include/linux/sh_clk.h
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此差异已折叠。
include/video/mipi_display.h 0 → 100644
浏览文件 @ 500b9fc9
此差异已折叠。
include/video/sh_mipi_dsi.h 0 → 100644
浏览文件 @ 500b9fc9
此差异已折叠。
include/video/sh_mobile_hdmi.h 0 → 100644
浏览文件 @ 500b9fc9
此差异已折叠。
include/video/sh_mobile_lcdc.h
浏览文件 @ 500b9fc9
此差异已折叠。
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