diff --git a/drivers/edac/fsl_ddr_edac.c b/drivers/edac/fsl_ddr_edac.c index 26758337e23ebf5363ff6f9a6fe2b1ad5ec140fc..46b00e15e44288e5467d6b9bfb3d82a4e89af986 100644 --- a/drivers/edac/fsl_ddr_edac.c +++ b/drivers/edac/fsl_ddr_edac.c @@ -371,30 +371,36 @@ static void fsl_ddr_init_csrows(struct mem_ctl_info *mci) sdtype = sdram_ctl & DSC_SDTYPE_MASK; if (sdram_ctl & DSC_RD_EN) { switch (sdtype) { - case DSC_SDTYPE_DDR: + case 0x02000000: mtype = MEM_RDDR; break; - case DSC_SDTYPE_DDR2: + case 0x03000000: mtype = MEM_RDDR2; break; - case DSC_SDTYPE_DDR3: + case 0x07000000: mtype = MEM_RDDR3; break; + case 0x05000000: + mtype = MEM_RDDR4; + break; default: mtype = MEM_UNKNOWN; break; } } else { switch (sdtype) { - case DSC_SDTYPE_DDR: + case 0x02000000: mtype = MEM_DDR; break; - case DSC_SDTYPE_DDR2: + case 0x03000000: mtype = MEM_DDR2; break; - case DSC_SDTYPE_DDR3: + case 0x07000000: mtype = MEM_DDR3; break; + case 0x05000000: + mtype = MEM_DDR4; + break; default: mtype = MEM_UNKNOWN; break; @@ -499,8 +505,10 @@ int fsl_mc_err_probe(struct platform_device *op) } edac_dbg(3, "init mci\n"); - mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_RDDR2 | - MEM_FLAG_DDR | MEM_FLAG_DDR2; + mci->mtype_cap = MEM_FLAG_DDR | MEM_FLAG_RDDR | + MEM_FLAG_DDR2 | MEM_FLAG_RDDR2 | + MEM_FLAG_DDR3 | MEM_FLAG_RDDR3 | + MEM_FLAG_DDR4 | MEM_FLAG_RDDR4; mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; mci->edac_cap = EDAC_FLAG_SECDED; mci->mod_name = EDAC_MOD_STR; diff --git a/drivers/edac/fsl_ddr_edac.h b/drivers/edac/fsl_ddr_edac.h index 1eccc62b5d9340fba99ad992f09153c6ec27d89e..4ccee292eff152ee2f555890f41f0c9b33926f33 100644 --- a/drivers/edac/fsl_ddr_edac.h +++ b/drivers/edac/fsl_ddr_edac.h @@ -50,10 +50,6 @@ #define DSC_DBW_64 0x00000000 #define DSC_SDTYPE_MASK 0x07000000 - -#define DSC_SDTYPE_DDR 0x02000000 -#define DSC_SDTYPE_DDR2 0x03000000 -#define DSC_SDTYPE_DDR3 0x07000000 #define DSC_X32_EN 0x00000020 /* Err_Int_En */