Skip to content

K
kernel_linux

OpenHarmony / kernel_linux
上一次同步 4 年多

通知 15
Star 8
Fork 2
K
kernel_linux
提交 4c2fb44d 编写于 作者: N Niklas Söderlund 提交者： Geert Uytterhoeven
浏览文件
操作

pinctrl: sh-pfc: r8a7795: Support none GPIO pins bias setting 

There are pins on the r8a7795 which are not part of a GPIO bank nor
can be muxed between different functions. They do however allow for the
bias to be configured. Add those pins to the list of pins and
to the bias configuration array.

The pins can now be referred to in DT by function names and their bias
setting set.
Signed-off-by: NNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
上级 2d40bd24
显示空白变更内容
内联 并排
Showing with 249 addition and 201 deletion
drivers/pinctrl/sh-pfc/pfc-r8a7795.c
浏览文件 @ 4c2fb44d
...@@ -538,7 +538,7 @@ MOD_SEL0_2_1 MOD_SEL1_2 \ ...@@ -538,7 +538,7 @@ MOD_SEL0_2_1 MOD_SEL1_2 \
FM(AVB_TXCREFCLK) FM(AVB_MDIO) \ FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
FM(CLKOUT) FM(PRESETOUT) \ FM(CLKOUT) FM(PRESETOUT) \
FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \ FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
enum { enum {
PINMUX_RESERVED = 0, PINMUX_RESERVED = 0,
...@@ -1461,46 +1461,50 @@ static const struct sh_pfc_pin pinmux_pins[] = { ...@@ -1461,46 +1461,50 @@ static const struct sh_pfc_pin pinmux_pins[] = {
* number for each pin. To this end use the pin layout from * number for each pin. To this end use the pin layout from
* R-Car H3SiP to calculate a unique number for each pin. * R-Car H3SiP to calculate a unique number for each pin.
*/ */
SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, SH_PFC_PIN_CFG_DRIVE_STRENGTH), SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, SH_PFC_PIN_CFG_DRIVE_STRENGTH), SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, SH_PFC_PIN_CFG_DRIVE_STRENGTH), SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, SH_PFC_PIN_CFG_DRIVE_STRENGTH), SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, SH_PFC_PIN_CFG_DRIVE_STRENGTH), SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, SH_PFC_PIN_CFG_DRIVE_STRENGTH), SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, SH_PFC_PIN_CFG_DRIVE_STRENGTH), SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, SH_PFC_PIN_CFG_DRIVE_STRENGTH), SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, SH_PFC_PIN_CFG_DRIVE_STRENGTH), SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, SH_PFC_PIN_CFG_DRIVE_STRENGTH), SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, SH_PFC_PIN_CFG_DRIVE_STRENGTH), SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, SH_PFC_PIN_CFG_DRIVE_STRENGTH), SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, SH_PFC_PIN_CFG_DRIVE_STRENGTH), SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, SH_PFC_PIN_CFG_DRIVE_STRENGTH), SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, SH_PFC_PIN_CFG_DRIVE_STRENGTH), SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('F', 1, CLKOUT, SH_PFC_PIN_CFG_DRIVE_STRENGTH), SH_PFC_PIN_NAMED_CFG('F', 1, CLKOUT, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, SH_PFC_PIN_CFG_DRIVE_STRENGTH), SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, SH_PFC_PIN_CFG_DRIVE_STRENGTH), SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, SH_PFC_PIN_CFG_DRIVE_STRENGTH), SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, SH_PFC_PIN_CFG_DRIVE_STRENGTH), SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, SH_PFC_PIN_CFG_DRIVE_STRENGTH), SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, SH_PFC_PIN_CFG_DRIVE_STRENGTH), SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, SH_PFC_PIN_CFG_DRIVE_STRENGTH), SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, SH_PFC_PIN_CFG_DRIVE_STRENGTH), SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, SH_PFC_PIN_CFG_DRIVE_STRENGTH), SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, SH_PFC_PIN_CFG_DRIVE_STRENGTH), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, SH_PFC_PIN_CFG_DRIVE_STRENGTH), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, SH_PFC_PIN_CFG_DRIVE_STRENGTH), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, SH_PFC_PIN_CFG_DRIVE_STRENGTH), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, SH_PFC_PIN_CFG_DRIVE_STRENGTH), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, SH_PFC_PIN_CFG_DRIVE_STRENGTH), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, SH_PFC_PIN_CFG_DRIVE_STRENGTH), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, SH_PFC_PIN_CFG_DRIVE_STRENGTH), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, SH_PFC_PIN_CFG_DRIVE_STRENGTH), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, SH_PFC_PIN_CFG_DRIVE_STRENGTH), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 7, DU_DOTCLKIN2, SH_PFC_PIN_CFG_DRIVE_STRENGTH), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, SH_PFC_PIN_CFG_DRIVE_STRENGTH), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 7, DU_DOTCLKIN2, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, SH_PFC_PIN_CFG_DRIVE_STRENGTH), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, SH_PFC_PIN_CFG_DRIVE_STRENGTH), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
}; };
/* - AUDIO CLOCK ------------------------------------------------------------ */ /* - AUDIO CLOCK ------------------------------------------------------------ */
...@@ -5418,6 +5422,35 @@ static const struct sh_pfc_bias_info bias_info[] = { ...@@ -5418,6 +5422,35 @@ static const struct sh_pfc_bias_info bias_info[] = {
{ RCAR_GP_PIN(2, 11), PU0, 31 }, /* AVB_PHY_INT */ { RCAR_GP_PIN(2, 11), PU0, 31 }, /* AVB_PHY_INT */
{ RCAR_GP_PIN(2, 10), PU0, 30 }, /* AVB_MAGIC */ { RCAR_GP_PIN(2, 10), PU0, 30 }, /* AVB_MAGIC */
{ RCAR_GP_PIN(2, 9), PU0, 29 }, /* AVB_MDC */ { RCAR_GP_PIN(2, 9), PU0, 29 }, /* AVB_MDC */
{ PIN_NUMBER('A', 9), PU0, 28 }, /* AVB_MDIO */
{ PIN_NUMBER('A', 12), PU0, 27 }, /* AVB_TXCREFCLK */
{ PIN_NUMBER('B', 17), PU0, 26 }, /* AVB_TD3 */
{ PIN_NUMBER('A', 17), PU0, 25 }, /* AVB_TD2 */
{ PIN_NUMBER('B', 18), PU0, 24 }, /* AVB_TD1 */
{ PIN_NUMBER('A', 18), PU0, 23 }, /* AVB_TD0 */
{ PIN_NUMBER('A', 19), PU0, 22 }, /* AVB_TXC */
{ PIN_NUMBER('A', 8), PU0, 21 }, /* AVB_TX_CTL */
{ PIN_NUMBER('B', 14), PU0, 20 }, /* AVB_RD3 */
{ PIN_NUMBER('A', 14), PU0, 19 }, /* AVB_RD2 */
{ PIN_NUMBER('B', 13), PU0, 18 }, /* AVB_RD1 */
{ PIN_NUMBER('A', 13), PU0, 17 }, /* AVB_RD0 */
{ PIN_NUMBER('B', 19), PU0, 16 }, /* AVB_RXC */
{ PIN_NUMBER('A', 16), PU0, 15 }, /* AVB_RX_CTL */
{ PIN_NUMBER('V', 7), PU0, 14 }, /* RPC_RESET# */
{ PIN_NUMBER('V', 6), PU0, 13 }, /* RPC_WP# */
{ PIN_NUMBER('Y', 7), PU0, 12 }, /* RPC_INT# */
{ PIN_NUMBER('V', 5), PU0, 11 }, /* QSPI1_SSL */
{ PIN_A_NUMBER('C', 3), PU0, 10 }, /* QSPI1_IO3 */
{ PIN_A_NUMBER('E', 4), PU0, 9 }, /* QSPI1_IO2 */
{ PIN_A_NUMBER('E', 5), PU0, 8 }, /* QSPI1_MISO_IO1 */
{ PIN_A_NUMBER('C', 7), PU0, 7 }, /* QSPI1_MOSI_IO0 */
{ PIN_NUMBER('V', 3), PU0, 6 }, /* QSPI1_SPCLK */
{ PIN_NUMBER('Y', 3), PU0, 5 }, /* QSPI0_SSL */
{ PIN_A_NUMBER('B', 6), PU0, 4 }, /* QSPI0_IO3 */
{ PIN_NUMBER('Y', 6), PU0, 3 }, /* QSPI0_IO2 */
{ PIN_A_NUMBER('B', 4), PU0, 2 }, /* QSPI0_MISO_IO1 */
{ PIN_A_NUMBER('C', 5), PU0, 1 }, /* QSPI0_MOSI_IO0 */
{ PIN_NUMBER('W', 3), PU0, 0 }, /* QSPI0_SPCLK */
{ RCAR_GP_PIN(1, 19), PU1, 31 }, /* A19 */ { RCAR_GP_PIN(1, 19), PU1, 31 }, /* A19 */
{ RCAR_GP_PIN(1, 18), PU1, 30 }, /* A18 */ { RCAR_GP_PIN(1, 18), PU1, 30 }, /* A18 */
...@@ -5452,6 +5485,8 @@ static const struct sh_pfc_bias_info bias_info[] = { ...@@ -5452,6 +5485,8 @@ static const struct sh_pfc_bias_info bias_info[] = {
{ RCAR_GP_PIN(2, 13), PU1, 1 }, /* AVB_AVTP_MATCH_A */ { RCAR_GP_PIN(2, 13), PU1, 1 }, /* AVB_AVTP_MATCH_A */
{ RCAR_GP_PIN(2, 12), PU1, 0 }, /* AVB_LINK */ { RCAR_GP_PIN(2, 12), PU1, 0 }, /* AVB_LINK */
{ PIN_A_NUMBER('P', 8), PU2, 31 }, /* DU_DOTCLKIN1 */
{ PIN_A_NUMBER('P', 7), PU2, 30 }, /* DU_DOTCLKIN0 */
{ RCAR_GP_PIN(7, 3), PU2, 29 }, /* HDMI1_CEC */ { RCAR_GP_PIN(7, 3), PU2, 29 }, /* HDMI1_CEC */
{ RCAR_GP_PIN(7, 2), PU2, 28 }, /* HDMI0_CEC */ { RCAR_GP_PIN(7, 2), PU2, 28 }, /* HDMI0_CEC */
{ RCAR_GP_PIN(7, 1), PU2, 27 }, /* AVS2 */ { RCAR_GP_PIN(7, 1), PU2, 27 }, /* AVS2 */
...@@ -5472,6 +5507,7 @@ static const struct sh_pfc_bias_info bias_info[] = { ...@@ -5472,6 +5507,7 @@ static const struct sh_pfc_bias_info bias_info[] = {
{ RCAR_GP_PIN(0, 2), PU2, 12 }, /* D2 */ { RCAR_GP_PIN(0, 2), PU2, 12 }, /* D2 */
{ RCAR_GP_PIN(0, 1), PU2, 11 }, /* D1 */ { RCAR_GP_PIN(0, 1), PU2, 11 }, /* D1 */
{ RCAR_GP_PIN(0, 0), PU2, 10 }, /* D0 */ { RCAR_GP_PIN(0, 0), PU2, 10 }, /* D0 */
{ PIN_NUMBER('C', 1), PU2, 9 }, /* PRESETOUT# */
{ RCAR_GP_PIN(1, 27), PU2, 8 }, /* EX_WAIT0_A */ { RCAR_GP_PIN(1, 27), PU2, 8 }, /* EX_WAIT0_A */
{ RCAR_GP_PIN(1, 26), PU2, 7 }, /* WE1_N */ { RCAR_GP_PIN(1, 26), PU2, 7 }, /* WE1_N */
{ RCAR_GP_PIN(1, 25), PU2, 6 }, /* WE0_N */ { RCAR_GP_PIN(1, 25), PU2, 6 }, /* WE0_N */
...@@ -5480,6 +5516,7 @@ static const struct sh_pfc_bias_info bias_info[] = { ...@@ -5480,6 +5516,7 @@ static const struct sh_pfc_bias_info bias_info[] = {
{ RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */ { RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */
{ RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N_A26 */ { RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N_A26 */
{ RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */ { RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */
{ PIN_NUMBER('F', 1), PU2, 0 }, /* CLKOUT */
{ RCAR_GP_PIN(4, 9), PU3, 31 }, /* SD3_DAT0 */ { RCAR_GP_PIN(4, 9), PU3, 31 }, /* SD3_DAT0 */
{ RCAR_GP_PIN(4, 8), PU3, 30 }, /* SD3_CMD */ { RCAR_GP_PIN(4, 8), PU3, 30 }, /* SD3_CMD */
...@@ -5503,6 +5540,16 @@ static const struct sh_pfc_bias_info bias_info[] = { ...@@ -5503,6 +5540,16 @@ static const struct sh_pfc_bias_info bias_info[] = {
{ RCAR_GP_PIN(3, 2), PU3, 12 }, /* SD0_DAT0 */ { RCAR_GP_PIN(3, 2), PU3, 12 }, /* SD0_DAT0 */
{ RCAR_GP_PIN(3, 1), PU3, 11 }, /* SD0_CMD */ { RCAR_GP_PIN(3, 1), PU3, 11 }, /* SD0_CMD */
{ RCAR_GP_PIN(3, 0), PU3, 10 }, /* SD0_CLK */ { RCAR_GP_PIN(3, 0), PU3, 10 }, /* SD0_CLK */
{ PIN_A_NUMBER('T', 30), PU3, 9 }, /* ASEBRK */
/* bit 8 n/a */
{ PIN_A_NUMBER('R', 29), PU3, 7 }, /* TDI */
{ PIN_A_NUMBER('R', 30), PU3, 6 }, /* TMS */
{ PIN_A_NUMBER('T', 27), PU3, 5 }, /* TCK */
{ PIN_A_NUMBER('R', 26), PU3, 4 }, /* TRST# */
{ PIN_A_NUMBER('D', 39), PU3, 3 }, /* EXTALR*/
{ PIN_A_NUMBER('D', 38), PU3, 2 }, /* FSCLKST# */
{ PIN_A_NUMBER('R', 8), PU3, 1 }, /* DU_DOTCLKIN3 */
{ PIN_A_NUMBER('R', 7), PU3, 0 }, /* DU_DOTCLKIN2 */
{ RCAR_GP_PIN(5, 19), PU4, 31 }, /* MSIOF0_SS1 */ { RCAR_GP_PIN(5, 19), PU4, 31 }, /* MSIOF0_SS1 */
{ RCAR_GP_PIN(5, 18), PU4, 30 }, /* MSIOF0_SYNC */ { RCAR_GP_PIN(5, 18), PU4, 30 }, /* MSIOF0_SYNC */
...@@ -5562,6 +5609,7 @@ static const struct sh_pfc_bias_info bias_info[] = { ...@@ -5562,6 +5609,7 @@ static const struct sh_pfc_bias_info bias_info[] = {
{ RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */ { RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */
{ RCAR_GP_PIN(6, 1), PU5, 8 }, /* SSI_WS01239 */ { RCAR_GP_PIN(6, 1), PU5, 8 }, /* SSI_WS01239 */
{ RCAR_GP_PIN(6, 0), PU5, 7 }, /* SSI_SCK01239 */ { RCAR_GP_PIN(6, 0), PU5, 7 }, /* SSI_SCK01239 */
{ PIN_NUMBER('H', 37), PU5, 6 }, /* MLB_REF */
{ RCAR_GP_PIN(5, 25), PU5, 5 }, /* MLB_DAT */ { RCAR_GP_PIN(5, 25), PU5, 5 }, /* MLB_DAT */
{ RCAR_GP_PIN(5, 24), PU5, 4 }, /* MLB_SIG */ { RCAR_GP_PIN(5, 24), PU5, 4 }, /* MLB_SIG */
{ RCAR_GP_PIN(5, 23), PU5, 3 }, /* MLB_CLK */ { RCAR_GP_PIN(5, 23), PU5, 3 }, /* MLB_CLK */
......
Markdown is supported
0% 或 .
You are about to add 0 people to the discussion. Proceed with caution.
先完成此消息的编辑！
想要评论请 注册 或