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kernel_linux
“3ad44d2ae574c8a88ea943c06492e94e60889900”上不存在“git@gitcode.net:weixin_47793882/gpt-vue.git”
提交 0cb8a881 编写于 作者: Y Yue Hin Lau 提交者： Alex Deucher
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drm/amd/display: move vm registers to hwsequencer 

Signed-off-by: NYue Hin Lau <Yuehin.Lau@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
上级 992fe94c
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内联 并排
Showing with 172 addition and 143 deletion
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
浏览文件 @ 0cb8a881
...@@ -206,7 +206,20 @@ ...@@ -206,7 +206,20 @@
SR(D1VGA_CONTROL), \ SR(D1VGA_CONTROL), \
SR(D2VGA_CONTROL), \ SR(D2VGA_CONTROL), \
SR(D3VGA_CONTROL), \ SR(D3VGA_CONTROL), \
SR(D4VGA_CONTROL) SR(D4VGA_CONTROL), \
/* todo: get these from GVM instead of reading registers ourselves */\
MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),\
MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),\
MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),\
MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),\
MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),\
MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),\
MMHUB_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32),\
MMHUB_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),\
MMHUB_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),\
MMHUB_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB),\
MMHUB_SR(MC_VM_SYSTEM_APERTURE_LOW_ADDR),\
MMHUB_SR(MC_VM_SYSTEM_APERTURE_HIGH_ADDR)
#define HWSEQ_DCN1_REG_LIST()\ #define HWSEQ_DCN1_REG_LIST()\
HWSEQ_DCN_REG_LIST(), \ HWSEQ_DCN_REG_LIST(), \
...@@ -312,6 +325,19 @@ struct dce_hwseq_registers { ...@@ -312,6 +325,19 @@ struct dce_hwseq_registers {
uint32_t D2VGA_CONTROL; uint32_t D2VGA_CONTROL;
uint32_t D3VGA_CONTROL; uint32_t D3VGA_CONTROL;
uint32_t D4VGA_CONTROL; uint32_t D4VGA_CONTROL;
/* MMHUB registers. read only. temporary hack */
uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32;
uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32;
uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32;
uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32;
uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32;
uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32;
uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32;
uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB;
uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB;
uint32_t MC_VM_SYSTEM_APERTURE_LOW_ADDR;
uint32_t MC_VM_SYSTEM_APERTURE_HIGH_ADDR;
}; };
/* set field name */ /* set field name */
#define HWS_SF(blk_name, reg_name, field_name, post_fix)\ #define HWS_SF(blk_name, reg_name, field_name, post_fix)\
...@@ -432,7 +458,17 @@ struct dce_hwseq_registers { ...@@ -432,7 +458,17 @@ struct dce_hwseq_registers {
HWS_SF(, DCHUBBUB_SDPIF_AGP_BASE, SDPIF_AGP_BASE, mask_sh), \ HWS_SF(, DCHUBBUB_SDPIF_AGP_BASE, SDPIF_AGP_BASE, mask_sh), \
HWS_SF(, DCHUBBUB_SDPIF_AGP_BOT, SDPIF_AGP_BOT, mask_sh), \ HWS_SF(, DCHUBBUB_SDPIF_AGP_BOT, SDPIF_AGP_BOT, mask_sh), \
HWS_SF(, DCHUBBUB_SDPIF_AGP_TOP, SDPIF_AGP_TOP, mask_sh), \ HWS_SF(, DCHUBBUB_SDPIF_AGP_TOP, SDPIF_AGP_TOP, mask_sh), \
HWS_SF(DPP_TOP0_, DPP_CONTROL, DPPCLK_RATE_CONTROL, mask_sh) HWS_SF(DPP_TOP0_, DPP_CONTROL, DPPCLK_RATE_CONTROL, mask_sh), \
/* todo: get these from GVM instead of reading registers ourselves */\
HWS_SF(, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\
HWS_SF(, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\
HWS_SF(, VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, LOGICAL_PAGE_NUMBER_HI4, mask_sh),\
HWS_SF(, VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, LOGICAL_PAGE_NUMBER_LO32, mask_sh),\
HWS_SF(, VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, PHYSICAL_PAGE_ADDR_HI4, mask_sh),\
HWS_SF(, VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, PHYSICAL_PAGE_ADDR_LO32, mask_sh),\
HWS_SF(, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, PHYSICAL_PAGE_NUMBER_MSB, mask_sh),\
HWS_SF(, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, PHYSICAL_PAGE_NUMBER_LSB, mask_sh),\
HWS_SF(, MC_VM_SYSTEM_APERTURE_LOW_ADDR, LOGICAL_ADDR, mask_sh)
#define HWSEQ_REG_FIELD_LIST(type) \ #define HWSEQ_REG_FIELD_LIST(type) \
type DCFE_CLOCK_ENABLE; \ type DCFE_CLOCK_ENABLE; \
...@@ -451,6 +487,18 @@ struct dce_hwseq_registers { ...@@ -451,6 +487,18 @@ struct dce_hwseq_registers {
type PIXEL_RATE_SOURCE; \ type PIXEL_RATE_SOURCE; \
type PHYPLL_PIXEL_RATE_SOURCE; \ type PHYPLL_PIXEL_RATE_SOURCE; \
type PIXEL_RATE_PLL_SOURCE; \ type PIXEL_RATE_PLL_SOURCE; \
/* todo: get these from GVM instead of reading registers ourselves */\
type PAGE_DIRECTORY_ENTRY_HI32;\
type PAGE_DIRECTORY_ENTRY_LO32;\
type LOGICAL_PAGE_NUMBER_HI4;\
type LOGICAL_PAGE_NUMBER_LO32;\
type PHYSICAL_PAGE_ADDR_HI4;\
type PHYSICAL_PAGE_ADDR_LO32;\
type PHYSICAL_PAGE_NUMBER_MSB;\
type PHYSICAL_PAGE_NUMBER_LSB;\
type LOGICAL_ADDR; \
type ENABLE_L1_TLB;\
type SYSTEM_ACCESS_MODE;
#define HWSEQ_DCN_REG_FIELD_LIST(type) \ #define HWSEQ_DCN_REG_FIELD_LIST(type) \
type VUPDATE_NO_LOCK_EVENT_CLEAR; \ type VUPDATE_NO_LOCK_EVENT_CLEAR; \
......
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
浏览文件 @ 0cb8a881
...@@ -2083,6 +2083,93 @@ static void dcn10_get_surface_visual_confirm_color( ...@@ -2083,6 +2083,93 @@ static void dcn10_get_surface_visual_confirm_color(
} }
} }
static void mmhub_read_vm_system_aperture_settings(struct dcn10_mem_input *mi,
struct vm_system_aperture_param *apt,
struct dce_hwseq *hws)
{
PHYSICAL_ADDRESS_LOC physical_page_number;
uint32_t logical_addr_low;
uint32_t logical_addr_high;
REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
PHYSICAL_PAGE_NUMBER_MSB, &physical_page_number.high_part);
REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
PHYSICAL_PAGE_NUMBER_LSB, &physical_page_number.low_part);
REG_GET(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
LOGICAL_ADDR, &logical_addr_low);
REG_GET(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
LOGICAL_ADDR, &logical_addr_high);
apt->sys_default.quad_part = physical_page_number.quad_part << 12;
apt->sys_low.quad_part = (int64_t)logical_addr_low << 18;
apt->sys_high.quad_part = (int64_t)logical_addr_high << 18;
}
/* Temporary read settings, future will get values from kmd directly */
static void mmhub_read_vm_context0_settings(struct dcn10_mem_input *mi,
struct vm_context0_param *vm0,
struct dce_hwseq *hws)
{
PHYSICAL_ADDRESS_LOC fb_base;
PHYSICAL_ADDRESS_LOC fb_offset;
uint32_t fb_base_value;
uint32_t fb_offset_value;
REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, &fb_base_value);
REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, &fb_offset_value);
REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
PAGE_DIRECTORY_ENTRY_HI32, &vm0->pte_base.high_part);
REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
PAGE_DIRECTORY_ENTRY_LO32, &vm0->pte_base.low_part);
REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_start.high_part);
REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_start.low_part);
REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_end.high_part);
REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_end.low_part);
REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
PHYSICAL_PAGE_ADDR_HI4, &vm0->fault_default.high_part);
REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
PHYSICAL_PAGE_ADDR_LO32, &vm0->fault_default.low_part);
/*
* The values in VM_CONTEXT0_PAGE_TABLE_BASE_ADDR is in UMA space.
* Therefore we need to do
* DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
* - DCHUBBUB_SDPIF_FB_OFFSET + DCHUBBUB_SDPIF_FB_BASE
*/
fb_base.quad_part = (uint64_t)fb_base_value << 24;
fb_offset.quad_part = (uint64_t)fb_offset_value << 24;
vm0->pte_base.quad_part += fb_base.quad_part;
vm0->pte_base.quad_part -= fb_offset.quad_part;
}
static void dcn10_program_pte_vm(struct mem_input *mem_input,
enum surface_pixel_format format,
union dc_tiling_info *tiling_info,
enum dc_rotation_angle rotation,
struct dce_hwseq *hws)
{
struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input);
struct vm_system_aperture_param apt = { {{ 0 } } };
struct vm_context0_param vm0 = { { { 0 } } };
mmhub_read_vm_system_aperture_settings(mi, &apt, hws);
mmhub_read_vm_context0_settings(mi, &vm0, hws);
mem_input->funcs->mem_input_set_vm_system_aperture_settings(mem_input, &apt);
mem_input->funcs->mem_input_set_vm_context0_settings(mem_input, &vm0);
}
static void update_dchubp_dpp( static void update_dchubp_dpp(
struct dc *dc, struct dc *dc,
struct pipe_ctx *pipe_ctx, struct pipe_ctx *pipe_ctx,
...@@ -2127,11 +2214,13 @@ static void update_dchubp_dpp( ...@@ -2127,11 +2214,13 @@ static void update_dchubp_dpp(
size.grph.surface_size = pipe_ctx->plane_res.scl_data.viewport; size.grph.surface_size = pipe_ctx->plane_res.scl_data.viewport;
if (dc->config.gpu_vm_support) if (dc->config.gpu_vm_support)
mi->funcs->mem_input_program_pte_vm( dcn10_program_pte_vm(
pipe_ctx->plane_res.mi, pipe_ctx->plane_res.mi,
plane_state->format, plane_state->format,
&plane_state->tiling_info, &plane_state->tiling_info,
plane_state->rotation); plane_state->rotation,
hws
);
ipp->funcs->ipp_setup(ipp, ipp->funcs->ipp_setup(ipp,
plane_state->format, plane_state->format,
...@@ -2674,6 +2763,8 @@ void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx) ...@@ -2674,6 +2763,8 @@ void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
} }
} }
static const struct hw_sequencer_funcs dcn10_funcs = { static const struct hw_sequencer_funcs dcn10_funcs = {
.program_gamut_remap = program_gamut_remap, .program_gamut_remap = program_gamut_remap,
.program_csc_matrix = program_csc_matrix, .program_csc_matrix = program_csc_matrix,
......
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
浏览文件 @ 0cb8a881
...@@ -625,38 +625,10 @@ static bool min10_is_flip_pending(struct mem_input *mem_input) ...@@ -625,38 +625,10 @@ static bool min10_is_flip_pending(struct mem_input *mem_input)
return false; return false;
} }
struct vm_system_aperture_param { static void min10_set_vm_system_aperture_settings(struct mem_input *mem_input,
PHYSICAL_ADDRESS_LOC sys_default;
PHYSICAL_ADDRESS_LOC sys_low;
PHYSICAL_ADDRESS_LOC sys_high;
};
static void min10_read_vm_system_aperture_settings(struct dcn10_mem_input *mi,
struct vm_system_aperture_param *apt)
{
PHYSICAL_ADDRESS_LOC physical_page_number;
uint32_t logical_addr_low;
uint32_t logical_addr_high;
REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
PHYSICAL_PAGE_NUMBER_MSB, &physical_page_number.high_part);
REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
PHYSICAL_PAGE_NUMBER_LSB, &physical_page_number.low_part);
REG_GET(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
LOGICAL_ADDR, &logical_addr_low);
REG_GET(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
LOGICAL_ADDR, &logical_addr_high);
apt->sys_default.quad_part = physical_page_number.quad_part << 12;
apt->sys_low.quad_part = (int64_t)logical_addr_low << 18;
apt->sys_high.quad_part = (int64_t)logical_addr_high << 18;
}
static void min10_set_vm_system_aperture_settings(struct dcn10_mem_input *mi,
struct vm_system_aperture_param *apt) struct vm_system_aperture_param *apt)
{ {
struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input);
PHYSICAL_ADDRESS_LOC mc_vm_apt_default; PHYSICAL_ADDRESS_LOC mc_vm_apt_default;
PHYSICAL_ADDRESS_LOC mc_vm_apt_low; PHYSICAL_ADDRESS_LOC mc_vm_apt_low;
PHYSICAL_ADDRESS_LOC mc_vm_apt_high; PHYSICAL_ADDRESS_LOC mc_vm_apt_high;
...@@ -682,60 +654,10 @@ static void min10_set_vm_system_aperture_settings(struct dcn10_mem_input *mi, ...@@ -682,60 +654,10 @@ static void min10_set_vm_system_aperture_settings(struct dcn10_mem_input *mi,
MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mc_vm_apt_high.low_part); MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mc_vm_apt_high.low_part);
} }
struct vm_context0_param { static void min10_set_vm_context0_settings(struct mem_input *mem_input,
PHYSICAL_ADDRESS_LOC pte_base;
PHYSICAL_ADDRESS_LOC pte_start;
PHYSICAL_ADDRESS_LOC pte_end;
PHYSICAL_ADDRESS_LOC fault_default;
};
/* Temporary read settings, future will get values from kmd directly */
static void min10_read_vm_context0_settings(struct dcn10_mem_input *mi,
struct vm_context0_param *vm0)
{
PHYSICAL_ADDRESS_LOC fb_base;
PHYSICAL_ADDRESS_LOC fb_offset;
uint32_t fb_base_value;
uint32_t fb_offset_value;
REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, &fb_base_value);
REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, &fb_offset_value);
REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
PAGE_DIRECTORY_ENTRY_HI32, &vm0->pte_base.high_part);
REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
PAGE_DIRECTORY_ENTRY_LO32, &vm0->pte_base.low_part);
REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_start.high_part);
REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_start.low_part);
REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_end.high_part);
REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_end.low_part);
REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
PHYSICAL_PAGE_ADDR_HI4, &vm0->fault_default.high_part);
REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
PHYSICAL_PAGE_ADDR_LO32, &vm0->fault_default.low_part);
/*
* The values in VM_CONTEXT0_PAGE_TABLE_BASE_ADDR is in UMA space.
* Therefore we need to do
* DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
* - DCHUBBUB_SDPIF_FB_OFFSET + DCHUBBUB_SDPIF_FB_BASE
*/
fb_base.quad_part = (uint64_t)fb_base_value << 24;
fb_offset.quad_part = (uint64_t)fb_offset_value << 24;
vm0->pte_base.quad_part += fb_base.quad_part;
vm0->pte_base.quad_part -= fb_offset.quad_part;
}
static void min10_set_vm_context0_settings(struct dcn10_mem_input *mi,
const struct vm_context0_param *vm0) const struct vm_context0_param *vm0)
{ {
struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input);
/* pte base */ /* pte base */
REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, 0, REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, 0,
VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, vm0->pte_base.high_part); VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, vm0->pte_base.high_part);
...@@ -760,23 +682,6 @@ static void min10_set_vm_context0_settings(struct dcn10_mem_input *mi, ...@@ -760,23 +682,6 @@ static void min10_set_vm_context0_settings(struct dcn10_mem_input *mi,
/* VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM, 0 */ /* VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM, 0 */
REG_SET(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, 0, REG_SET(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, 0,
VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, vm0->fault_default.low_part); VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, vm0->fault_default.low_part);
}
static void min10_program_pte_vm(struct mem_input *mem_input,
enum surface_pixel_format format,
union dc_tiling_info *tiling_info,
enum dc_rotation_angle rotation)
{
struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input);
struct vm_system_aperture_param apt = { {{ 0 } } };
struct vm_context0_param vm0 = { { { 0 } } };
min10_read_vm_system_aperture_settings(mi, &apt);
min10_read_vm_context0_settings(mi, &vm0);
min10_set_vm_system_aperture_settings(mi, &apt);
min10_set_vm_context0_settings(mi, &vm0);
/* control: enable VM PTE*/ /* control: enable VM PTE*/
REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0,
...@@ -862,7 +767,8 @@ static struct mem_input_funcs dcn10_mem_input_funcs = { ...@@ -862,7 +767,8 @@ static struct mem_input_funcs dcn10_mem_input_funcs = {
min10_program_surface_config, min10_program_surface_config,
.mem_input_is_flip_pending = min10_is_flip_pending, .mem_input_is_flip_pending = min10_is_flip_pending,
.mem_input_setup = min10_setup, .mem_input_setup = min10_setup,
.mem_input_program_pte_vm = min10_program_pte_vm, .mem_input_set_vm_system_aperture_settings = min10_set_vm_system_aperture_settings,
.mem_input_set_vm_context0_settings = min10_set_vm_context0_settings,
.set_blank = min10_set_blank, .set_blank = min10_set_blank,
.dcc_control = min10_dcc_control, .dcc_control = min10_dcc_control,
.mem_program_viewport = min_set_viewport, .mem_program_viewport = min_set_viewport,
......
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
浏览文件 @ 0cb8a881
...@@ -97,20 +97,7 @@ ...@@ -97,20 +97,7 @@
SRI(DCN_SURF0_TTU_CNTL1, HUBPREQ, id),\ SRI(DCN_SURF0_TTU_CNTL1, HUBPREQ, id),\
SRI(DCN_SURF1_TTU_CNTL0, HUBPREQ, id),\ SRI(DCN_SURF1_TTU_CNTL0, HUBPREQ, id),\
SRI(DCN_SURF1_TTU_CNTL1, HUBPREQ, id),\ SRI(DCN_SURF1_TTU_CNTL1, HUBPREQ, id),\
SRI(DCN_VM_MX_L1_TLB_CNTL, HUBPREQ, id),\ SRI(DCN_VM_MX_L1_TLB_CNTL, HUBPREQ, id)
/* todo: get these from GVM instead of reading registers ourselves */\
MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),\
MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),\
MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),\
MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),\
MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),\
MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),\
MMHUB_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32),\
MMHUB_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),\
MMHUB_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),\
MMHUB_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB),\
MMHUB_SR(MC_VM_SYSTEM_APERTURE_LOW_ADDR),\
MMHUB_SR(MC_VM_SYSTEM_APERTURE_HIGH_ADDR)
#define MI_REG_LIST_DCN10(id)\ #define MI_REG_LIST_DCN10(id)\
MI_REG_LIST_DCN(id),\ MI_REG_LIST_DCN(id),\
...@@ -228,20 +215,6 @@ struct dcn_mi_registers { ...@@ -228,20 +215,6 @@ struct dcn_mi_registers {
uint32_t DCN_VM_AGP_BASE; uint32_t DCN_VM_AGP_BASE;
uint32_t DCN_VM_AGP_BOT; uint32_t DCN_VM_AGP_BOT;
uint32_t DCN_VM_AGP_TOP; uint32_t DCN_VM_AGP_TOP;
/* GC registers. read only. temporary hack */
uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32;
uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32;
uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32;
uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32;
uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32;
uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32;
uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32;
uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB;
uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB;
uint32_t MC_VM_SYSTEM_APERTURE_LOW_ADDR;
uint32_t MC_VM_SYSTEM_APERTURE_HIGH_ADDR;
}; };
#define MI_SF(reg_name, field_name, post_fix)\ #define MI_SF(reg_name, field_name, post_fix)\
...@@ -387,17 +360,7 @@ struct dcn_mi_registers { ...@@ -387,17 +360,7 @@ struct dcn_mi_registers {
MI_SF(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh),\ MI_SF(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh),\
MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, mask_sh),\ MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, mask_sh),\
MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mask_sh),\ MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mask_sh),\
MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mask_sh),\ MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mask_sh)
/* todo: get these from GVM instead of reading registers ourselves */\
MI_SF(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\
MI_SF(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\
MI_SF(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, LOGICAL_PAGE_NUMBER_HI4, mask_sh),\
MI_SF(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, LOGICAL_PAGE_NUMBER_LO32, mask_sh),\
MI_SF(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, PHYSICAL_PAGE_ADDR_HI4, mask_sh),\
MI_SF(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, PHYSICAL_PAGE_ADDR_LO32, mask_sh),\
MI_SF(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, PHYSICAL_PAGE_NUMBER_MSB, mask_sh),\
MI_SF(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, PHYSICAL_PAGE_NUMBER_LSB, mask_sh),\
MI_SF(MC_VM_SYSTEM_APERTURE_LOW_ADDR, LOGICAL_ADDR, mask_sh)
#define DCN_MI_REG_FIELD_LIST(type) \ #define DCN_MI_REG_FIELD_LIST(type) \
type HUBP_BLANK_EN;\ type HUBP_BLANK_EN;\
......
drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
浏览文件 @ 0cb8a881
...@@ -74,6 +74,19 @@ struct mem_input { ...@@ -74,6 +74,19 @@ struct mem_input {
struct stutter_modes stutter_mode; struct stutter_modes stutter_mode;
}; };
struct vm_system_aperture_param {
PHYSICAL_ADDRESS_LOC sys_default;
PHYSICAL_ADDRESS_LOC sys_low;
PHYSICAL_ADDRESS_LOC sys_high;
};
struct vm_context0_param {
PHYSICAL_ADDRESS_LOC pte_base;
PHYSICAL_ADDRESS_LOC pte_start;
PHYSICAL_ADDRESS_LOC pte_end;
PHYSICAL_ADDRESS_LOC fault_default;
};
struct mem_input_funcs { struct mem_input_funcs {
void (*mem_input_setup)( void (*mem_input_setup)(
struct mem_input *mem_input, struct mem_input *mem_input,
...@@ -125,6 +138,14 @@ struct mem_input_funcs { ...@@ -125,6 +138,14 @@ struct mem_input_funcs {
union dc_tiling_info *tiling_info, union dc_tiling_info *tiling_info,
enum dc_rotation_angle rotation); enum dc_rotation_angle rotation);
void (*mem_input_set_vm_system_aperture_settings)(
struct mem_input *mem_input,
struct vm_system_aperture_param *apt);
void (*mem_input_set_vm_context0_settings)(
struct mem_input *mem_input,
const struct vm_context0_param *vm0);
void (*mem_input_program_surface_config)( void (*mem_input_program_surface_config)(
struct mem_input *mem_input, struct mem_input *mem_input,
enum surface_pixel_format format, enum surface_pixel_format format,
......
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