ARM data processing instructions which have a register specified shift
are defined as UNPREDICTABLE if PC is used for any register, not just
the shift value as the code was previous assuming. This issue manifests
on A15 devices as either test case failures or undefined instructions
aborts.
Reported-by: NDavid Long <dave.long@linaro.org>
Signed-off-by: NJon Medhurst <tixy@linaro.org>