Don't hard code the cacheline size in the cache control register definitions.
Signed-off-by: NAkira Takeuchi <takeuchi.akr@jp.panasonic.com>
Signed-off-by: NKiyoshi Owada <owada.kiyoshi@jp.panasonic.com>
Signed-off-by: NDavid Howells <dhowells@redhat.com>