From 1eb6107f0481f5e3eabbb795dcf453c3035a119a Mon Sep 17 00:00:00 2001
From: king_he <6384784@qq.com>
Date: Mon, 16 May 2022 02:13:51 +0000
Subject: [PATCH] update en/device-dev/driver/driver-platform-spi-des.md.
Signed-off-by: king_he <6384784@qq.com>
---
.../driver/driver-platform-spi-des.md | 57 +++++++++----------
1 file changed, 28 insertions(+), 29 deletions(-)
diff --git a/en/device-dev/driver/driver-platform-spi-des.md b/en/device-dev/driver/driver-platform-spi-des.md
index 4388fdd99b..a8b35d2682 100644
--- a/en/device-dev/driver/driver-platform-spi-des.md
+++ b/en/device-dev/driver/driver-platform-spi-des.md
@@ -2,46 +2,46 @@
## Overview
-- Serial Peripheral Interface \(SPI\) is a serial bus specification used for high-speed, full-duplex, and synchronous communication.
-- SPI is developed by Motorola. It is commonly used for communication with flash memory, real-time clocks, sensors, and analog-to-digital \(A/D\) converters.
-- SPI works in controller/device mode. Generally, there is one SPI controller that controls one or more SPI devices. They are connected via four wires:
- - SCLK: clock signals output from the SPI controller
- - MOSI: data output from the SPI controller and input into an SPI device
- - MISO: data output from an SPI device and input into the SPI controller
- - CS: signals enabled by an SPI device and controlled by the SPI controller
+Serial Peripheral Interface \(SPI\) is a serial bus specification used for high-speed, full-duplex, and synchronous communication.
+SPI is developed by Motorola. It is commonly used for communication with flash memory, real-time clocks, sensors, and analog-to-digital \(A/D\) converters.
+SPI works in controller/device mode. Generally, there is one SPI controller that controls one or more SPI devices. They are connected via four wires:
+- SCLK: clock signals output from the SPI controller
+- MOSI: data output from the SPI controller and input into an SPI device
+- MISO: data output from an SPI device and input into the SPI controller
+- CS: signals enabled by an SPI device and controlled by the SPI controller
-- [Figure 1](#fig89085710359) shows the connection between one SPI controller and two SPI devices \(device A and device B\). In this figure, device A and device B share three pins \(SCLK, MISO, and MOSI\) of the controller. CS0 of device A and CS1 of device B are connected to CS0 and CS1 of the controller, respectively.
+[Figure 1](#fig89085710359) shows the connection between one SPI controller and two SPI devices \(device A and device B\). In this figure, device A and device B share three pins \(SCLK, MISO, and MOSI\) of the controller. CS0 of device A and CS1 of device B are connected to CS0 and CS1 of the controller, respectively.
-**Figure 1** SPI controller/device connection
+**Figure 1** SPI controller/device connection

-- SPI communication is usually initiated by the SPI controller and is operated as follows:
+SPI communication is usually initiated by the SPI controller and is operated as follows:
1. A single SPI device is selected at a time via the CS to communicate with the SPI controller.
2. Clock signals are provided for the selected SPI device via the SCLK.
3. The SPI controller sends data to SPI devices via the MOSI, and receives data from SPI devices via the MISO.
- SPI can work in one of the following four modes, equivalent to one of the four possible states for Clock Polarity \(CPOL\) and Clock Phase \(CPHA\):
- - If both CPOL and CPHA are **0**, the clock signal level is low in the idle state and data is sampled on the first clock edge.
- - If CPOL is **0** and CPHA is **1**, the clock signal level is low in the idle state and data is sampled on the second clock edge.
- - If CPOL is **1** and CPHA is **0**, the clock signal level is high in the idle state and data is sampled on the first clock edge.
- - If both CPOL and CPHA are **1**, the clock signal level is high in the idle state and data is sampled on the second clock edge.
+ - If both CPOL and CPHA are **0**, the clock signal level is low in the idle state and data is sampled on the first clock edge.
+ - If CPOL is **0** and CPHA is **1**, the clock signal level is low in the idle state and data is sampled on the second clock edge.
+ - If CPOL is **1** and CPHA is **0**, the clock signal level is high in the idle state and data is sampled on the first clock edge.
+ - If both CPOL and CPHA are **1**, the clock signal level is high in the idle state and data is sampled on the second clock edge.
- SPI defines a set of common functions for operating an SPI device, including those for:
- Obtaining and releasing the handle of an SPI device.
- Reading or writing data of a specified length from or into an SPI device.
- - Customizing data reading or writing via **SpiMsg**.
+ - Customizing data reading or writing via **SpiMsg**.
- Obtaining and setting SPI device configuration parameters.
-> **NOTE:**
+> **NOTE**
>Currently, these functions are only applicable in the communication initiated by the SPI controller.
## Available APIs
-**Table 1** APIs for the SPI driver
+**Table 1** APIs for the SPI driver