1. 03 7月, 2009 1 次提交
  2. 02 7月, 2009 1 次提交
    • I
      x86: Fix printk call in print_local_apic() · 251e1e44
      Ingo Molnar 提交于
      Instead of this:
      
      [   75.690022] <7>printing local APIC contents on CPU#0/0:
      [   75.704406] ... APIC ID:      00000000 (0)
      [   75.707905] ... APIC VERSION: 00060015
      [   75.722551] ... APIC TASKPRI: 00000000 (00)
      [   75.725473] ... APIC PROCPRI: 00000000
      [   75.728592] ... APIC LDR: 00000001
      [   75.742137] ... APIC SPIV: 000001ff
      [   75.744101] ... APIC ISR field:
      [   75.746648] 0123456789abcdef0123456789abcdef
      [   75.746649] <7>00000000000000000000000000000000
      
      Improve the code to be saner and simpler and just print out
      the bitfield in a single line using hexa values - not as a
      (rather pointless) binary bitfield.
      
      Partially reused Linus's initial fix for this.
      Reported-and-Tested-by: NYinghai Lu <yinghai@kernel.org>
      Signed-off-by: NYinghai Lu <yinghai@kernel.org>
      Cc: Linus Torvalds <torvalds@linux-foundation.org>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      LKML-Reference: <4A4C43BC.90506@kernel.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      251e1e44
  3. 24 6月, 2009 1 次提交
    • W
      Intel-IOMMU, intr-remap: source-id checking · f007e99c
      Weidong Han 提交于
      To support domain-isolation usages, the platform hardware must be
      capable of uniquely identifying the requestor (source-id) for each
      interrupt message. Without source-id checking for interrupt remapping
      , a rouge guest/VM with assigned devices can launch interrupt attacks
      to bring down anothe guest/VM or the VMM itself.
      
      This patch adds source-id checking for interrupt remapping, and then
      really isolates interrupts for guests/VMs with assigned devices.
      
      Because PCI subsystem is not initialized yet when set up IOAPIC
      entries, use read_pci_config_byte to access PCI config space directly.
      Signed-off-by: NWeidong Han <weidong.han@intel.com>
      Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>
      f007e99c
  4. 18 6月, 2009 2 次提交
    • C
      x86, ioapic: Don't call disconnect_bsp_APIC if no APIC present · 3f4c3955
      Cyrill Gorcunov 提交于
      Vegard Nossum reported:
      
      [  503.576724] ACPI: Preparing to enter system sleep state S5
      [  503.710857] Disabling non-boot CPUs ...
      [  503.716853] Power down.
      [  503.717770] ------------[ cut here ]------------
      [  503.717770] WARNING: at arch/x86/kernel/apic/apic.c:249 native_apic_write_du)
      [  503.717770] Hardware name: OptiPlex GX100
      [  503.717770] Modules linked in:
      [  503.717770] Pid: 2136, comm: halt Not tainted 2.6.30 #443
      [  503.717770] Call Trace:
      [  503.717770]  [<c154d327>] ? printk+0x18/0x1a
      [  503.717770]  [<c1017358>] ? native_apic_write_dummy+0x38/0x50
      [  503.717770]  [<c10360fc>] warn_slowpath_common+0x6c/0xc0
      [  503.717770]  [<c1017358>] ? native_apic_write_dummy+0x38/0x50
      [  503.717770]  [<c1036165>] warn_slowpath_null+0x15/0x20
      [  503.717770]  [<c1017358>] native_apic_write_dummy+0x38/0x50
      [  503.717770]  [<c1017173>] disconnect_bsp_APIC+0x63/0x100
      [  503.717770]  [<c1019e48>] disable_IO_APIC+0xb8/0xc0
      [  503.717770]  [<c1214231>] ? acpi_power_off+0x0/0x29
      [  503.717770]  [<c1015e55>] native_machine_shutdown+0x65/0x80
      [  503.717770]  [<c1015c36>] native_machine_power_off+0x26/0x30
      [  503.717770]  [<c1015c49>] machine_power_off+0x9/0x10
      [  503.717770]  [<c1046596>] kernel_power_off+0x36/0x40
      [  503.717770]  [<c104680d>] sys_reboot+0xfd/0x1f0
      [  503.717770]  [<c109daa0>] ? perf_swcounter_event+0xb0/0x130
      [  503.717770]  [<c109db7d>] ? perf_counter_task_sched_out+0x5d/0x120
      [  503.717770]  [<c102dfc6>] ? finish_task_switch+0x56/0xd0
      [  503.717770]  [<c154da1e>] ? schedule+0x49e/0xb40
      [  503.717770]  [<c10444b0>] ? sys_kill+0x70/0x160
      [  503.717770]  [<c119d9db>] ? selinux_file_ioctl+0x3b/0x50
      [  503.717770]  [<c10dd443>] ? sys_ioctl+0x63/0x70
      [  503.717770]  [<c1003024>] sysenter_do_call+0x12/0x22
      [  503.717770] ---[ end trace 8157b5d0ed378f15 ]---
      
      |
      | That's including this commit:
      |
      | commit 103428e5
      |Author: Cyrill Gorcunov <gorcunov@openvz.org>
      |Date:   Sun Jun 7 16:48:40 2009 +0400
      |
      |    x86, apic: Fix dummy apic read operation together with broken MP handling
      |
      
      If we have apic disabled we don't even switch to APIC mode and do not
      calling for connect_bsp_APIC. Though on SMP compiled kernel the
      native_machine_shutdown does try to write the apic register anyway.
      
      Fix it with explicit check if we really should touch apic registers.
      Reported-by: NVegard Nossum <vegard.nossum@gmail.com>
      Signed-off-by: NCyrill Gorcunov <gorcunov@openvz.org>
      Cc: Yinghai Lu <yinghai@kernel.org>
      LKML-Reference: <20090617181322.GG10822@lenovo>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      3f4c3955
    • H
      x86: Remove duplicated #include's · 8653f88f
      Huang Weiyi 提交于
      Signed-off-by: NHuang Weiyi <weiyi.huang@gmail.com>
      LKML-Reference: <1244895686-2348-1-git-send-email-weiyi.huang@gmail.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      8653f88f
  5. 17 6月, 2009 2 次提交
  6. 12 6月, 2009 3 次提交
  7. 09 6月, 2009 1 次提交
    • J
      x86, UV: Fix macros for multiple coherency domains · c4ed3f04
      Jack Steiner 提交于
      Fix bug in the SGI UV macros that support systems with multiple
      coherency domains.  The macros used for referencing global MMR
      (chipset registers) are failing to correctly "or" the NASID
      (node identifier) bits that reside above M+N. These high bits
      are supplied automatically by the chipset for memory accesses
      coming from the processor socket.
      
      However, the bits must be present for references to the special
      global MMR space used to map chipset registers. (See uv_hub.h
      for more details ...)
      
      The bug results in references to invalid/incorrect nodes.
      Signed-off-by: NJack Steiner <steiner@sgi.com>
      Cc: <stable@kernel.org>
      LKML-Reference: <20090608154405.GA16395@sgi.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      c4ed3f04
  8. 07 6月, 2009 1 次提交
    • C
      x86, apic: Fix dummy apic read operation together with broken MP handling · 103428e5
      Cyrill Gorcunov 提交于
      Ingo Molnar reported that read_apic is buggy novadays:
      
      [    0.000000] Using APIC driver default
      [    0.000000] SMP: Allowing 1 CPUs, 0 hotplug CPUs
      [    0.000000] Local APIC disabled by BIOS -- you can enable it with "lapic"
      [    0.000000] APIC: disable apic facility
      [    0.000000] ------------[ cut here ]------------
      [    0.000000] WARNING: at arch/x86/kernel/apic/apic.c:254 native_apic_read_dummy+0x2d/0x3b()
      [    0.000000] Hardware name: HP OmniBook PC
      
      Indeed we still rely on apic->read operation for SMP compiled
      kernel. And instead of disfigure the SMP code with #ifdef we
      allow to call apic->read. To capture any unexpected results
      we check for apic->read being called for sane reason via
      WARN_ON_ONCE but(!) instead of OR we should use AND logical
      operation (thanks Yinghai for spotting the root of the problem).
      
      Along with that we could be have bad MP table and we are
      to fix it that way no SMP started and no complains about
      BIOS bug if apic was just disabled via command line.
      Signed-off-by: NCyrill Gorcunov <gorcunov@openvz.org>
      Cc: Yinghai Lu <yinghai@kernel.org>
      LKML-Reference: <20090607124840.GD4547@lenovo>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      103428e5
  9. 02 6月, 2009 2 次提交
    • J
      x86, apic: Restore irqs on fail paths · 3d58829b
      Jiri Slaby 提交于
      lapic_resume forgets to restore interrupts on fail paths.
      Fix that.
      Signed-off-by: NJiri Slaby <jirislaby@gmail.com>
      Acked-by: NCyrill Gorcunov <gorcunov@openvz.org>
      LKML-Reference: <1243497289-18591-1-git-send-email-jirislaby@gmail.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      Cc: H. Peter Anvin <hpa@zytor.com>
      3d58829b
    • N
      x86: Print real IOAPIC version for x86-64 · 58f892e0
      Naga Chumbalkar 提交于
      Fix the fact that the IOAPIC version number in the x86_64 code path always
      gets assigned to 0, instead of the correct value.
      
      Before the patch: (from "dmesg" output):
      
       ACPI: IOAPIC (id[0x08] address[0xfec00000] gsi_base[0])
       IOAPIC[0]: apic_id 8, version 0, address 0xfec00000, GSI 0-23     <---
      
       After the patch:
       ACPI: IOAPIC (id[0x08] address[0xfec00000] gsi_base[0])
       IOAPIC[0]: apic_id 8, version 32, address 0xfec00000, GSI 0-23    <---
      
      History:
      
      io_apic_get_version() was compiled out of the x86_64 code path in the commit
      f2c2cca3:
      
      Author: Andi Kleen <ak@suse.de>
      Date:   Tue Sep 26 10:52:37 2006 +0200
      
          [PATCH] Remove APIC version/cpu capability mpparse checking/printing
      
          ACPI went to great trouble to get the APIC version and CPU capabilities
          of different CPUs before passing them to the mpparser. But all
          that data was used was to print it out.  Actually it even faked some data
          based on the boot cpu, not on the actual CPU being booted.
      
          Remove all this code because it's not needed.
      
          Cc: len.brown@intel.com
      
      At the time, the IOAPIC version number was deliberately not printed
      in the x86_64 code path. However, after the x86 and x86_64 files were
      merged, the net result is that the IOAPIC version is printed incorrectly
      in the x86_64 code path.
      
      The patch below provides a fix. I have tested it with acpi, and with
      acpi=off, and did not see any problems.
      Signed-off-by: NNaga Chumbalkar <nagananda.chumbalkar@hp.com>
      Acked-by: NYinghai Lu <yhlu.kernel@gmail.com>
      LKML-Reference: <20090416014230.4885.94926.sendpatchset@localhost.localdomain>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      *************************
      58f892e0
  10. 29 5月, 2009 2 次提交
    • Y
      perf_counter/x86: Always use NMI for performance-monitoring interrupt · c323d95f
      Yong Wang 提交于
      Always use NMI for performance-monitoring interrupt as there could be
      racy situations if we switch between irq and nmi mode frequently.
      Signed-off-by: NYong Wang <yong.y.wang@intel.com>
      LKML-Reference: <20090529052835.GA13657@ywang-moblin2.bj.intel.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      c323d95f
    • A
      x86, mce: use 64bit machine check code on 32bit · 4efc0670
      Andi Kleen 提交于
      The 64bit machine check code is in many ways much better than
      the 32bit machine check code: it is more specification compliant,
      is cleaner, only has a single code base versus one per CPU,
      has better infrastructure for recovery, has a cleaner way to communicate
      with user space etc. etc.
      
      Use the 64bit code for 32bit too.
      
      This is the second attempt to do this. There was one a couple of years
      ago to unify this code for 32bit and 64bit.  Back then this ran into some
      trouble with K7s and was reverted.
      
      I believe this time the K7 problems (and some others) are addressed.
      I went over the old handlers and was very careful to retain
      all quirks.
      
      But of course this needs a lot of testing on old systems. On newer
      64bit capable systems I don't expect much problems because they have been
      already tested with the 64bit kernel.
      
      I made this a CONFIG for now that still allows to select the old
      machine check code. This is mostly to make testing easier,
      if someone runs into a problem we can ask them to try
      with the CONFIG switched.
      
      The new code is default y for more coverage.
      
      Once there is confidence the 64bit code works well on older hardware
      too the CONFIG_X86_OLD_MCE and the associated code can be easily
      removed.
      
      This causes a behaviour change for 32bit installations. They now
      have to install the mcelog package to be able to log
      corrected machine checks.
      
      The 64bit machine check code only handles CPUs which support the
      standard Intel machine check architecture described in the IA32 SDM.
      The 32bit code has special support for some older CPUs which
      have non standard machine check architectures, in particular
      WinChip C3 and Intel P5.  I made those a separate CONFIG option
      and kept them for now. The WinChip variant could be probably
      removed without too much pain, it doesn't really do anything
      interesting. P5 is also disabled by default (like it
      was before) because many motherboards have it miswired, but
      according to Alan Cox a few embedded setups use that one.
      
      Forward ported/heavily changed version of old patch, original patch
      included review/fixes from Thomas Gleixner, Bert Wesarg.
      Signed-off-by: NAndi Kleen <ak@linux.intel.com>
      Signed-off-by: NH. Peter Anvin <hpa@zytor.com>
      Signed-off-by: NHidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
      Signed-off-by: NH. Peter Anvin <hpa@zytor.com>
      4efc0670
  11. 26 5月, 2009 1 次提交
  12. 22 5月, 2009 1 次提交
    • P
      perf_counter: Dynamically allocate tasks' perf_counter_context struct · a63eaf34
      Paul Mackerras 提交于
      This replaces the struct perf_counter_context in the task_struct with
      a pointer to a dynamically allocated perf_counter_context struct.  The
      main reason for doing is this is to allow us to transfer a
      perf_counter_context from one task to another when we do lazy PMU
      switching in a later patch.
      
      This has a few side-benefits: the task_struct becomes a little smaller,
      we save some memory because only tasks that have perf_counters attached
      get a perf_counter_context allocated for them, and we can remove the
      inclusion of <linux/perf_counter.h> in sched.h, meaning that we don't
      end up recompiling nearly everything whenever perf_counter.h changes.
      
      The perf_counter_context structures are reference-counted and freed
      when the last reference is dropped.  A context can have references
      from its task and the counters on its task.  Counters can outlive the
      task so it is possible that a context will be freed well after its
      task has exited.
      
      Contexts are allocated on fork if the parent had a context, or
      otherwise the first time that a per-task counter is created on a task.
      In the latter case, we set the context pointer in the task struct
      locklessly using an atomic compare-and-exchange operation in case we
      raced with some other task in creating a context for the subject task.
      
      This also removes the task pointer from the perf_counter struct.  The
      task pointer was not used anywhere and would make it harder to move a
      context from one task to another.  Anything that needed to know which
      task a counter was attached to was already using counter->ctx->task.
      
      The __perf_counter_init_context function moves up in perf_counter.c
      so that it can be called from find_get_context, and now initializes
      the refcount, but is otherwise unchanged.
      
      We were potentially calling list_del_counter twice: once from
      __perf_counter_exit_task when the task exits and once from
      __perf_counter_remove_from_context when the counter's fd gets closed.
      This adds a check in list_del_counter so it doesn't do anything if
      the counter has already been removed from the lists.
      
      Since perf_counter_task_sched_in doesn't do anything if the task doesn't
      have a context, and leaves cpuctx->task_ctx = NULL, this adds code to
      __perf_install_in_context to set cpuctx->task_ctx if necessary, i.e. in
      the case where the current task adds the first counter to itself and
      thus creates a context for itself.
      
      This also adds similar code to __perf_counter_enable to handle a
      similar situation which can arise when the counters have been disabled
      using prctl; that also leaves cpuctx->task_ctx = NULL.
      
      [ Impact: refactor counter context management to prepare for new feature ]
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      Acked-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Corey Ashford <cjashfor@linux.vnet.ibm.com>
      Cc: Marcelo Tosatti <mtosatti@redhat.com>
      Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
      LKML-Reference: <18966.10075.781053.231153@cargo.ozlabs.ibm.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      a63eaf34
  13. 19 5月, 2009 1 次提交
    • Y
      x86, io-apic: Don't mark pin_programmed early · 4c6f18fc
      Yinghai Lu 提交于
      Peter bisected that:
      
      | commit b9c61b70
      | Date:   Wed May 6 10:10:06 2009 -0700
      |
      |     x86/pci: update pirq_enable_irq() to setup io apic routing
      |
      |     So we can set io apic routing only when enabling the device irq.
      
      wrecked his opteron box, ata1 interrupts fail to get through.
      
      ata1 is using irq 11:
      
      [    1.451839] sata_svw 0000:01:0e.0: version 2.3
      [    1.456333] sata_svw 0000:01:0e.0: PCI INT A -> GSI 11 (level, low) -> IRQ 11
      [    1.463639] scsi0 : sata_svw
      [    1.466949] scsi1 : sata_svw
      [    1.470022] scsi2 : sata_svw
      [    1.473090] scsi3 : sata_svw
      [    1.476112] ata1: SATA max UDMA/133 mmio m8192@0xff3fe000 port 0xff3fe000 irq 11
      [    1.483490] ata2: SATA max UDMA/133 mmio m8192@0xff3fe000 port 0xff3fe100 irq 11
      [    1.490870] ata3: SATA max UDMA/133 mmio m8192@0xff3fe000 port 0xff3fe200 irq 11
      [    1.498247] ata4: SATA max UDMA/133 mmio m8192@0xff3fe000 port 0xff3fe300 irq 11
      
      that pin is overlapped with pin with legacy ones.
      
      We should not set bits in pin_programmed here, so that those bit could
      be set later via io_apic_set_pci_routing().
      
      [ Impact: fix boot hang on certain systems ]
      Reported-by: NPeter Zijlstra <peterz@infradead.org>
      Signed-off-by: NYinghai Lu <yinghai.lu@kernel.org>
      Tested-by: NPeter Zijlstra <peterz@infradead.org>
      Cc: Jack Steiner <steiner@sgi.com>
      LKML-Reference: <4A119990.9020606@kernel.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      4c6f18fc
  14. 18 5月, 2009 2 次提交
  15. 13 5月, 2009 1 次提交
  16. 12 5月, 2009 1 次提交
    • Y
      x86: read apic ID in the !acpi_lapic case · 4797f6b0
      Yinghai Lu 提交于
      Ed found that on 32-bit, boot_cpu_physical_apicid is not read right,
      when the mptable is broken.
      
      Interestingly, actually three paths use/set it:
      
       1. acpi: at that time that is already read from reg
       2. mptable: only read from mptable
       3. no madt, and no mptable, that use default apic id 0 for 64-bit, -1 for 32-bit
      
      so we could read the apic id for the 2/3 path. We trust the hardware
      register more than we trust a BIOS data structure (the mptable).
      
      We can also avoid the double set_fixmap() when acpi_lapic
      is used, and also need to move cpu_has_apic earlier and
      call apic_disable().
      
      Also when need to update the apic id, we'd better read and
      set the apic version as well - so that quirks are applied precisely.
      
      v2: make path 3 with 64bit, use -1 as apic id, so could read it later.
      v3: fix whitespace problem pointed out by Ed Swierk
      v5: fix boot crash
      
      [ Impact: get correct apic id for bsp other than acpi path ]
      Reported-by: NEd Swierk <eswierk@aristanetworks.com>
      Signed-off-by: NYinghai Lu <yinghai@kernel.org>
      Acked-by: NCyrill Gorcunov <gorcunov@openvz.org>
      LKML-Reference: <49FC85A9.2070702@kernel.org>
      [ v4: sanity-check in the ACPI case too ]
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      4797f6b0
  17. 11 5月, 2009 8 次提交
  18. 10 5月, 2009 1 次提交
  19. 03 5月, 2009 2 次提交
  20. 02 5月, 2009 2 次提交
    • C
      x86, apic: use pr_ macro · 6f0aced6
      Cyrill Gorcunov 提交于
      Replace recenly appeared printk with pr_ macro
      (the file already use a lot of them).
      
      [ Impact: cleanup ]
      Signed-off-by: NCyrill Gorcunov <gorcunov@openvz.org>
      LKML-Reference: <20090501195425.GB4633@lenovo>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      6f0aced6
    • Y
      x86/irq: use move_irq_desc() in create_irq_nr() · 15e957d0
      Yinghai Lu 提交于
      move_irq_desc() will try to move irq_desc to the home node if
      the allocated one is not correct, in create_irq_nr().
      
      ( This can happen on devices that are on different nodes that
        are using MSI, when drivers are loaded and unloaded randomly. )
      
      v2: fix non-smp build
      v3: add NUMA_IRQ_DESC to eliminate #ifdefs
      
      [ Impact: improve irq descriptor locality on NUMA systems ]
      Signed-off-by: NYinghai Lu <yinghai@kernel.org>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      Cc: Suresh Siddha <suresh.b.siddha@intel.com>
      Cc: "Eric W. Biederman" <ebiederm@xmission.com>
      Cc: Rusty Russell <rusty@rustcorp.com.au>
      LKML-Reference: <49F95EAE.2050903@kernel.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      15e957d0
  21. 28 4月, 2009 4 次提交
    • Y
      x86/irq: change MSI irq_desc to be more numa aware · d047f53a
      Yinghai Lu 提交于
      Try to get irq_desc on the home node in create_irq_nr().
      
      v2: don't check if we can move it when sparse_irq is not used
      v3: use move_irq_des, if that node is not what we want
      
      [ Impact: optimization, make MSI IRQ descriptors more NUMA aware ]
      Signed-off-by: NYinghai Lu <yinghai@kernel.org>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      Cc: Suresh Siddha <suresh.b.siddha@intel.com>
      Cc: "Eric W. Biederman" <ebiederm@xmission.com>
      Cc: Rusty Russell <rusty@rustcorp.com.au>
      LKML-Reference: <49F6559F.7070005@kernel.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      d047f53a
    • Y
      irq: change io_apic_set_pci_routing() to use device parameter · 024154cf
      Yinghai Lu 提交于
      Make actual use of the device parameter passed down to
      io_apic_set_pci_routing() - to have the IRQ descriptor
      on the home node of the device.
      
      If no device has been passed down, we assume it's a platform
      device and use the boot node ID for the IRQ descriptor.
      
      [ Impact: optimization, make IO-APIC code more NUMA aware ]
      Signed-off-by: NYinghai Lu <yinghai@kernel.org>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      Cc: Suresh Siddha <suresh.b.siddha@intel.com>
      Cc: "Eric W. Biederman" <ebiederm@xmission.com>
      Cc: Rusty Russell <rusty@rustcorp.com.au>
      LKML-Reference: <49F6557E.3080101@kernel.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      024154cf
    • Y
      irq: change ACPI GSI APIs to also take a device argument · a2f809b0
      Yinghai Lu 提交于
      We want to use dev_to_node() later on, to be aware of the 'home node'
      of the GSI in question.
      
      [ Impact: cleanup, prepare the IRQ code to be more NUMA aware ]
      Signed-off-by: NYinghai Lu <yinghai@kernel.org>
      Acked-by: NLen Brown <lenb@kernel.org>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      Cc: Suresh Siddha <suresh.b.siddha@intel.com>
      Cc: "Eric W. Biederman" <ebiederm@xmission.com>
      Cc: Rusty Russell <rusty@rustcorp.com.au>
      Cc: Len Brown <lenb@kernel.org>
      Cc: Bjorn Helgaas <bjorn.helgaas@hp.com>
      Cc: Tony Luck <tony.luck@intel.com>
      Cc: linux-acpi@vger.kernel.org
      Cc: linux-ia64@vger.kernel.org
      LKML-Reference: <49F65560.20904@kernel.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      a2f809b0
    • Y
      x86/irq: change irq_desc_alloc() to take node instead of cpu · 85ac16d0
      Yinghai Lu 提交于
      This simplifies the node awareness of the code. All our allocators
      only deal with a NUMA node ID locality not with CPU ids anyway - so
      there's no need to maintain (and transform) a CPU id all across the
      IRq layer.
      
      v2: keep move_irq_desc related
      
      [ Impact: cleanup, prepare IRQ code to be NUMA-aware ]
      Signed-off-by: NYinghai Lu <yinghai@kernel.org>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      Cc: Suresh Siddha <suresh.b.siddha@intel.com>
      Cc: "Eric W. Biederman" <ebiederm@xmission.com>
      Cc: Rusty Russell <rusty@rustcorp.com.au>
      Cc: Jeremy Fitzhardinge <jeremy@goop.org>
      LKML-Reference: <49F65536.2020300@kernel.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      85ac16d0