1. 11 8月, 2016 1 次提交
  2. 05 8月, 2016 2 次提交
  3. 04 8月, 2016 4 次提交
  4. 03 8月, 2016 7 次提交
  5. 20 7月, 2016 3 次提交
  6. 16 7月, 2016 1 次提交
  7. 05 7月, 2016 1 次提交
  8. 04 7月, 2016 2 次提交
  9. 24 6月, 2016 3 次提交
  10. 18 6月, 2016 4 次提交
    • Z
      drm/i915: Introduce GVT context creation API · c8c35799
      Zhi Wang 提交于
      GVT workload scheduler needs special host LRC contexts, the so called
      "shadow LRC context" to submit guest workload to host i915. During the
      guest workload submission, workload scheduler fills the shadow LRC
      context with the content of guest LRC context: engine context is copied
      without changes, ring context is mostly owned by host i915.
      
      v8:
      
      - Remove the graph temporarily. (Chris)
      - Use interruptible mutex_lock. (Chris)
      - Rename the function name of creating a GVT context. (Chris)
      - Add the missing declaration in i915_drv.h (Chris)
      
      v7:
      
      - Move chart to a better place. (Joonas)
      
      v6:
      
      - Make GVT code as dead code when !CONFIG_DRM_I915_GVT. (Chris)
      
      v5:
      - Only compile this feature when CONFIG_DRM_I915_GVT is enabled. (Tvrtko)
      - Rebase the code into new repo.
      - Add a comment about the ring buffer size. (Joonas)
      
      v2:
      
      Mostly based on Daniel's idea. Call the refactored core logic of GEM
      context creation service and LRC context creation service to create the GVT
      context.
      Reviewed-by: NJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
      Signed-off-by: NZhi Wang <zhi.a.wang@intel.com>
      Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      Link: http://patchwork.freedesktop.org/patch/msgid/1466078825-6662-10-git-send-email-zhi.a.wang@intel.com
      c8c35799
    • Z
      drm/i915: Introduce execlist context status change notification · 3c7ba635
      Zhi Wang 提交于
      This patch introduces an approach to track the execlist context status
      change.
      
      GVT-g uses GVT context as the "shadow context". The content inside GVT
      context will be copied back to guest after the context is idle. And GVT-g
      has to know the status of the execlist context.
      
      This function is configurable when creating a new GEM context. Currently,
      Only GVT-g will create the "status-change-notification" enabled GEM
      context.
      
      v10:
      
      - Fix the identation. (Joonas)
      
      v8:
      
      - Remove the boolean flag in struct i915_gem_context. (Joonas)
      
      v7:
      
      - Remove per-engine ctx status notifiers. Use one status notifier for all
      engines. (Joonas)
      - Add prefix "INTEL_" for related definitions. (Joonas)
      - Refine the comments in execlists_context_status_change(). (Joonas)
      
      v6:
      
      - When !CONFIG_DRM_I915_GVT, make GVT code as dead code then compiler
      could automatically eliminate them for us. (Chris)
      - Always initialize the notifier header, so it could be switched on/off
      at runtime. (Chris)
      
      v5:
      
      - Only compile this feature when CONFIG_DRM_I915_GVT is enabled.(Tvrtko)
      
      Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> (v8)
      Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
      Signed-off-by: NZhi Wang <zhi.a.wang@intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/1466078825-6662-8-git-send-email-zhi.a.wang@intel.comSigned-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      3c7ba635
    • Z
      drm/i915: Make addressing mode bits in context descriptor configurable · c01fc532
      Zhi Wang 提交于
      Currently the addressing mode bit in context descriptor is statically
      generated from the configuration of system-wide PPGTT usage model.
      
      GVT-g will load the PPGTT shadow page table by itself and probably one
      guest is using a different addressing mode with i915 host. The addressing
      mode bits of a LRC context should be configurable under this case.
      
      v10:
      
      - Fix the identation. (Joonas)
      
      v9:
      - Rename the data member in struct i915_gem_context. (Chris)
      
      v8:
      - Rename the data member in struct i915_gem_context. (Chris)
      
      v7:
      - Move context addressing mode bit into i915_reg.h. (Joonas/Chris)
      - Add prefix "INTEL_" for related definitions. (Joonas)
      
      v6:
      - Directly save the addressing mode bits inside i915_gem_context. (Chris)
      - Move the LRC context addressing mode bits into intel_lrc.h. (Chris)
      
      v5:
      - Change USES_FULL_48BIT(dev) to USES_FULL_48BIT(dev_priv) (Tvrtko)
      
      Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> (v9)
      Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
      Signed-off-by: NZhi Wang <zhi.a.wang@intel.com>
      Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      Link: http://patchwork.freedesktop.org/patch/msgid/1466078825-6662-7-git-send-email-zhi.a.wang@intel.com
      c01fc532
    • Z
      drm/i915: Make ring buffer size of a LRC context configurable · bcd794c2
      Zhi Wang 提交于
      This patch introduces an option for configuring the ring buffer size
      of a LRC context after the context creation.
      
      v9:
      - Fix an identation issue. (Chris)
      
      v8:
      - Rename the data member in i915_gem_context. (Chris)
      Reviewed-by: NJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Signed-off-by: NZhi Wang <zhi.a.wang@intel.com>
      Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      Link: http://patchwork.freedesktop.org/patch/msgid/1466078825-6662-6-git-send-email-zhi.a.wang@intel.com
      bcd794c2
  11. 24 5月, 2016 6 次提交
  12. 13 5月, 2016 2 次提交
  13. 09 5月, 2016 1 次提交
  14. 28 4月, 2016 3 次提交