Minor formatting fixup since the information which core was associated
with the MCE is not always valid.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Building for X86_32 produces shift count warnings, so use BIT_64() to
eliminate the warnings.

drivers/edac/mce_amd.c:778: warning: left shift count >= width of type
drivers/edac/mce_amd.c:778: warning: left shift count >= width of type
Signed-off-by: NRandy Dunlap <randy.dunlap@oracle.com>
Cc: Doug Thompson <dougthompson@xmission.com>
Cc: bluesmoke-devel@lists.sourceforge.net
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Now that everything is inplace, enable MCE decoding on F15h. Make
initcall routine a bit more readable.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Shorten up MCi_STATUS flags and add BD's new deferred and poison types.
Also, simplify formatting.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Make macro names shorter thus making code shorter and more clear.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Add decoder for FP MCEs.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Integrate the single FIROB signature into an expanded table along with
the new BD MCE types.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

by (almost) reusing the F10h one since the signatures are the same.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

F15h BD doesn't generate LS MCEs so warn about it.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

MCE bank 2 is redefined from a BU to a CU (Combined Unit) bank on F15h.
Add a decoder function for CU MCEs.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Add support for decoding F15h IC MCEs.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Add a decoder for F15h DC MCEs to support the new types of DC MCEs
introduced by the BD microarchitecture.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

F15h enlarges the extended error code of an MCE to a 5-bit field
(MCi_STATUS[20:16]). Add a mask variable which default 0xf is overridden
on F15h.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Fix

drivers/edac/mce_amd.c:262: warning: left shift count >= width of type

on 32-bit builds.
Reported-by: NRandy Dunlap <randy.dunlap@oracle.com>
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Turn on MCE decoding on F12h.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

F12h is completely covered by the generic path.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

... which is the same as for K8 and F10h.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

F12h DC MCE signatures are a subset of F10h's so reuse them.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

F11h has almost the same MCE signatures as K8 except DRAM ECC and MC5
bank errors. Reuse functionality from the other families.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Now that all decoders have been taught about F14h, models < 0x10
MCEs, enable decoding on this family of CPUs. Also, issue a short
informational message upon boot that MCE decoding gets enabled.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Those are N/A on K8, so don't decode them there.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Add support for decoding F14h BU MCEs and improve decoding of the
remaining families.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

F14h CPUs do not generate LS MCEs so exit early and warn the user in
case this path is ever hit that something else might be going haywire.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Add support for IC MCEs for F14h CPUs. K8 and F10h are almost identical
so use one function for both.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Add a per-family data cache decoders. Since there is a certain overlap
between the different DC MCE signatures, reuse functionality between the
families as far as possible.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Drop "edac_" string from the filenames since they're prefixed with edac/
in their pathname anyway.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Add sysfs injection facilities for testing of the MCE decoding code.
Remove large parts of amd64_edac_dbg.c, as a result, which did only
NB MCE injection anyway and the new injection code supports that
functionality already.

Add an injection module so that MCE decoding code in production kernels
like those in RHEL and SLES can be tested.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

... instead of the MCi_STATUS info only for improved handling of certain
types of errors later.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Clean up error codes names, shorten to mnemonics, add RRRR boundary
checking.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Remove remains from previous functionality.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

.. so that the user knows what she's looking at there in dmesg. Also,
fix a minor cosmetic output inconsistency.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

When the Overflow MCi_STATUS bit is set, EDAC reports the lost error
with a "no information available" message which often puzzles users
parsing the dmesg. This doesn't make much sense since this error has
been lost anyway so no need for reporting it separately. Thus, report
the overflow bit setting in the MCE dump instead. While at it, remove
reporting of MiscV and ErrorEnable (en) which are superfluous.

Now it looks like this:

[ 1501.650024] MC4_STATUS: Corrected error, other errors lost: yes, CPU context corrupt: no, CECC Error
[ 1501.666887] Northbridge Error, node 2
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Limit MCE error decoding to current and older families only (K8-F11h).
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Switch to reusing the mcheck core's machine check polling mechanism
instead of duplicating functionality by using the EDAC polling routine.

Correct formatting while at it.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>
Acked-by: NDoug Thompson <dougthompson@xmission.com>

Correct two mishaps which prevented reporting error type (CECC vs UECC)
and extended error description.

Cc: <stable@kernel.org> # 32.x,  33.x
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

Print the CPU associated with the error only when the field is valid.

Cc: <stable@kernel.org> # .32.x .33.x
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Although reporting of benign GART TLB errors is disabled in
__mcheck_cpu_apply_quirks, those are still being logged, and, as a
result, trip up amd64_edac. Pull up reporting check so that machines
with loaded edac module bail out early and don't spit fragments into
dmesg.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Fix core number reporting with NB MCEs.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

F10h revD start with model number 8.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Add an atomic notifier which ensures proper locking when conveying
MCE info to EDAC for decoding. The actual notifier call overrides a
default, negative priority notifier.

Note: make sure we register the default decoder only once since
mcheck_init() runs on each CPU.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>
LKML-Reference: <20091003065752.GA8935@liondog.tnic>
Signed-off-by: NIngo Molnar <mingo@elte.hu>