This corrects a race with the PHY RST bit not being set properly if the
PLL status changes right before timeout. This resulted in it potentially
failing even if the device came up in time.

Special thanks to Mr. Juha Leppanen and Iwamatsu-san for reporting this
out and reviewing it.
Reported-by: NJuha Leppanen <juha_motorsportcom@luukku.com>
Reviewed-by: NNobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Tested-by: NPaul Mundt <lethal@linux-sh.org>
Signed-off-by: NKuninori Morimoto <morimoto.kuninori@renesas.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Signed-off-by: NKuninori Morimoto <morimoto.kuninori@renesas.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This adds preliminary support for the SH7786 CPU subtype.

While this is a dual-core CPU, only UP is supported for now. L2 cache
support is likewise not yet implemented.

More information on this particular CPU subtype is available at:

	http://www.renesas.com/fmwk.jsp?cnt=sh7786_root.jsp&fp=/products/mpumcu/superh_family/sh7780_series/sh7786_group/Signed-off-by: NKuninori Morimoto <morimoto.kuninori@renesas.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>