diff --git a/arch/mips/au1000/common/time.c b/arch/mips/au1000/common/time.c
index 2bc33824807b7db2978af4a71417f02c4fc84686..2f81a0c00442bd76717879f3f78dcb0aa639d792 100644
--- a/arch/mips/au1000/common/time.c
+++ b/arch/mips/au1000/common/time.c
@@ -57,7 +57,7 @@ unsigned long missed_heart_beats = 0;
 static unsigned long r4k_offset; /* Amount to increment compare reg each time */
 static unsigned long r4k_cur;    /* What counter should be at next timer irq */
 int	no_au1xxx_32khz;
-int allow_au1k_wait = 0; /* default off for CP0 Counter */
+extern int allow_au1k_wait; /* default off for CP0 Counter */
 
 /* Cycle counter value at the previous timer interrupt.. */
 static unsigned int timerhi = 0, timerlo = 0;
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index b7c8346df3ca52b83e4171de3420374cfcd96002..69e5fff00edc810cc1fbc67181e94c3dc803ae3f 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -53,9 +53,10 @@ static void r4k_wait(void)
 
 /* The Au1xxx wait is available only if using 32khz counter or
  * external timer source, but specifically not CP0 Counter. */
+int allow_au1k_wait;
 static void au1k_wait(void)
 {
-	unsigned long addr;
+	unsigned long addr = 0;
 	/* using the wait instruction makes CP0 counter unusable */
 	__asm__("la %0,au1k_wait\n\t"
 		".set mips3\n\t"
@@ -113,14 +114,11 @@ static inline void check_wait(void)
 	case CPU_AU1500:
 	case CPU_AU1550:
 	case CPU_AU1200:
-		{
-			extern int allow_au1k_wait; /* au1000/common/time.c */
-			if (allow_au1k_wait) {
-				cpu_wait = au1k_wait;
-				printk(" available.\n");
-			} else
-				printk(" unavailable.\n");
-		}
+		if (allow_au1k_wait) {
+			cpu_wait = au1k_wait;
+			printk(" available.\n");
+		} else
+			printk(" unavailable.\n");
 		break;
 	default:
 		printk(" unavailable.\n");