From f85b09a3eb86bf5b7987614cdf7edba1c37dd698 Mon Sep 17 00:00:00 2001 From: Hao Fang Date: Thu, 11 Jul 2019 14:41:52 +0800 Subject: [PATCH] ACC: crypto/hisilicon/qm: fix dfx for current_q and current_qm config driver inclusion category: bugfix bugzilla: NA CVE: NA As SQE/CQE dfx regs high 16bits is q_index, low 6bits is qm_index. need to distinguish this. q_index and qm_index need different dfx interface. fix qm_index in zip and hpre. and fix hpre nfe reg enable value. user write decimal val by design. test sample: echo 1 > current_q not like: echo 0x10000 > current_q Signed-off-by: Hao Fang Reviewed-by: wangzhou Signed-off-by: lingmingqiang Signed-off-by: Yang Yingliang --- drivers/crypto/hisilicon/hpre/hpre_main.c | 11 ++++++++++- drivers/crypto/hisilicon/qm.c | 16 +++++++++++----- drivers/crypto/hisilicon/qm.h | 6 ++++++ drivers/crypto/hisilicon/zip/zip_main.c | 10 ++++++++++ 4 files changed, 37 insertions(+), 6 deletions(-) diff --git a/drivers/crypto/hisilicon/hpre/hpre_main.c b/drivers/crypto/hisilicon/hpre/hpre_main.c index 361b95eb45bc..d13f2b2b9c24 100644 --- a/drivers/crypto/hisilicon/hpre/hpre_main.c +++ b/drivers/crypto/hisilicon/hpre/hpre_main.c @@ -59,7 +59,7 @@ #define HPRE_RAS_CE_ENB 0x301410 #define HPRE_HAC_RAS_CE_ENABLE 0x3f #define HPRE_RAS_NFE_ENB 0x301414 -#define HPRE_HAC_RAS_NFE_ENABLE 0xc0 +#define HPRE_HAC_RAS_NFE_ENABLE 0x3fffc0 #define HPRE_RAS_FE_ENB 0x301418 #define HPRE_HAC_RAS_FE_ENABLE 0 @@ -469,6 +469,7 @@ static int current_qm_write(struct hpre_debugfs_file *file, u32 val) { struct hisi_qm *qm = file_to_qm(file); struct hpre_ctrl *ctrl = file->ctrl; + u32 tmp; if (val > ctrl->num_vfs) return -EINVAL; @@ -476,6 +477,14 @@ static int current_qm_write(struct hpre_debugfs_file *file, u32 val) writel(val, qm->io_base + QM_DFX_MB_CNT_VF); writel(val, qm->io_base + QM_DFX_DB_CNT_VF); + tmp = val | + (readl(qm->io_base + QM_DFX_SQE_CNT_VF_SQN) & QM_VF_CNT_MASK); + writel(tmp, qm->io_base + QM_DFX_SQE_CNT_VF_SQN); + + tmp = val | + (readl(qm->io_base + QM_DFX_CQE_CNT_VF_CQN) & QM_VF_CNT_MASK); + writel(tmp, qm->io_base + QM_DFX_CQE_CNT_VF_CQN); + return 0; } diff --git a/drivers/crypto/hisilicon/qm.c b/drivers/crypto/hisilicon/qm.c index 3d075722b117..170595fe1ac4 100644 --- a/drivers/crypto/hisilicon/qm.c +++ b/drivers/crypto/hisilicon/qm.c @@ -106,8 +106,6 @@ #define QM_SQC_VFT_NUM_SHIFT_V2 45 #define QM_SQC_VFT_NUM_MASK_v2 0x3ff -#define QM_DFX_SQE_CNT_VF_SQN 0x104030 -#define QM_DFX_CQE_CNT_VF_CQN 0x104040 #define QM_DFX_CNT_CLR_CE 0x100118 #define QM_ABNORMAL_INT_SOURCE 0x100000 @@ -157,6 +155,8 @@ #define WAIT_PERIOD 20 #define MAX_WAIT_COUNTS 3 +#define CURRENT_Q_MASK 0x0000ffff + #define QM_MK_CQC_DW3_V1(hop_num, pg_sz, buf_sz, cqe_sz) \ (((hop_num) << QM_CQ_HOP_NUM_SHIFT) | \ ((pg_sz) << QM_CQ_PAGE_SIZE_SHIFT) | \ @@ -726,18 +726,24 @@ static u32 current_q_read(struct debugfs_file *file) { struct hisi_qm *qm = file_to_qm(file); - return readl(qm->io_base + QM_DFX_SQE_CNT_VF_SQN); + return (readl(qm->io_base + QM_DFX_SQE_CNT_VF_SQN) >> QM_DFX_QN_SHIFT); } static int current_q_write(struct debugfs_file *file, u32 val) { struct hisi_qm *qm = file_to_qm(file); + u32 tmp; if (val >= qm->qp_num) return -EINVAL; - writel(val, qm->io_base + QM_DFX_SQE_CNT_VF_SQN); - writel(val, qm->io_base + QM_DFX_CQE_CNT_VF_CQN); + tmp = val << QM_DFX_QN_SHIFT | + (readl(qm->io_base + QM_DFX_SQE_CNT_VF_SQN) & CURRENT_Q_MASK); + writel(tmp, qm->io_base + QM_DFX_SQE_CNT_VF_SQN); + + tmp = val << QM_DFX_QN_SHIFT | + (readl(qm->io_base + QM_DFX_CQE_CNT_VF_CQN) & CURRENT_Q_MASK); + writel(tmp, qm->io_base + QM_DFX_CQE_CNT_VF_CQN); return 0; } diff --git a/drivers/crypto/hisilicon/qm.h b/drivers/crypto/hisilicon/qm.h index 0527e0ce2881..1b40fdc3adc7 100644 --- a/drivers/crypto/hisilicon/qm.h +++ b/drivers/crypto/hisilicon/qm.h @@ -58,6 +58,9 @@ #define QM_DFX_MB_CNT_VF 0x104010 #define QM_DFX_DB_CNT_VF 0x104020 +#define QM_DFX_SQE_CNT_VF_SQN 0x104030 +#define QM_DFX_CQE_CNT_VF_CQN 0x104040 + #define QM_AXI_RRESP BIT(0) #define QM_AXI_BRESP BIT(1) #define QM_ECC_MBIT BIT(2) @@ -79,6 +82,9 @@ #define QM_HW_VER1_ID 0x20 #define QM_HW_VER2_ID 0x21 +#define QM_DFX_QN_SHIFT 16 +#define QM_VF_CNT_MASK 0xffffffc0 + #define PCI_BAR_2 2 enum qm_state { diff --git a/drivers/crypto/hisilicon/zip/zip_main.c b/drivers/crypto/hisilicon/zip/zip_main.c index fbe6abb8f3ce..afb4a838187c 100644 --- a/drivers/crypto/hisilicon/zip/zip_main.c +++ b/drivers/crypto/hisilicon/zip/zip_main.c @@ -94,6 +94,7 @@ #define HZIP_BUF_SIZE 20 #define FORMAT_DECIMAL 10 + static const char hisi_zip_name[] = "hisi_zip"; static struct dentry *hzip_debugfs_root; LIST_HEAD(hisi_zip_list); @@ -452,6 +453,7 @@ static int current_qm_write(struct ctrl_debug_file *file, u32 val) { struct hisi_qm *qm = file_to_qm(file); struct hisi_zip_ctrl *ctrl = file->ctrl; + u32 tmp; if (val > ctrl->num_vfs) return -EINVAL; @@ -459,6 +461,14 @@ static int current_qm_write(struct ctrl_debug_file *file, u32 val) writel(val, qm->io_base + QM_DFX_MB_CNT_VF); writel(val, qm->io_base + QM_DFX_DB_CNT_VF); + tmp = val | + (readl(qm->io_base + QM_DFX_SQE_CNT_VF_SQN) & QM_VF_CNT_MASK); + writel(tmp, qm->io_base + QM_DFX_SQE_CNT_VF_SQN); + + tmp = val | + (readl(qm->io_base + QM_DFX_CQE_CNT_VF_CQN) & QM_VF_CNT_MASK); + writel(tmp, qm->io_base + QM_DFX_CQE_CNT_VF_CQN); + return 0; } -- GitLab