diff --git a/drivers/crypto/hisilicon/qm.h b/drivers/crypto/hisilicon/qm.h
index 27fb9c52f1c8c363b6e32ad3ef3a742fdd132483..0527e0ce28817b2fc86f5ccda2cf94613e8f7c6c 100644
--- a/drivers/crypto/hisilicon/qm.h
+++ b/drivers/crypto/hisilicon/qm.h
@@ -52,6 +52,7 @@
 #define AXI_M_CFG_ENABLE		0xffffffff
 #define QM_PEH_AXUSER_CFG		0x1000cc
 #define QM_PEH_AXUSER_CFG_ENABLE	0x1000d0
+#define PEH_AXUSER_CFG			0x401001
 #define PEH_AXUSER_CFG_ENABLE		0xffffffff
 
 #define QM_DFX_MB_CNT_VF		0x104010
diff --git a/drivers/crypto/hisilicon/zip/zip_main.c b/drivers/crypto/hisilicon/zip/zip_main.c
index 58f3e425bdb21377845d3cefb1763ae1f532d6c1..15d4a9b5f513a924f707f0499a9c66a26a50e78f 100644
--- a/drivers/crypto/hisilicon/zip/zip_main.c
+++ b/drivers/crypto/hisilicon/zip/zip_main.c
@@ -371,6 +371,8 @@ static void hisi_zip_set_user_domain_and_cache(struct hisi_zip *hisi_zip)
 	/* qm cache */
 	writel(AXI_M_CFG, hisi_zip->qm.io_base + QM_AXI_M_CFG);
 	writel(AXI_M_CFG_ENABLE, hisi_zip->qm.io_base + QM_AXI_M_CFG_ENABLE);
+	/* disable FLR triggered by BME(bus master enable) */
+	writel(PEH_AXUSER_CFG, hisi_zip->qm.io_base + QM_PEH_AXUSER_CFG);
 	writel(PEH_AXUSER_CFG_ENABLE, hisi_zip->qm.io_base +
 	       QM_PEH_AXUSER_CFG_ENABLE);
 
@@ -419,13 +421,17 @@ static void hisi_zip_hw_error_set_state(struct hisi_zip *hisi_zip, bool state)
 		return;
 	}
 
-	if (state)
+	if (state) {
+		/* clear ZIP hw error source if having */
+		writel(HZIP_CORE_INT_DISABLE, hisi_zip->qm.io_base +
+					      HZIP_CORE_INT_SOURCE);
 		/* enable ZIP hw error interrupts */
 		writel(0, hisi_zip->qm.io_base + HZIP_CORE_INT_MASK);
-	else
+	} else {
 		/* disable ZIP hw error interrupts */
 		writel(HZIP_CORE_INT_DISABLE,
 		       hisi_zip->qm.io_base + HZIP_CORE_INT_MASK);
+	}
 }
 
 static inline struct hisi_qm *file_to_qm(struct ctrl_debug_file *file)