ACC: drivers/crypto/zip: Fix 2ECC bug

driver inclusion
category: bugfix
bugzilla: NA
CVE: NA

As mentioned in this DTS, insmod zip module fails after triggering zip
2ECC error when zip module is not loading.

The reason is when zip 2ECC irq source is not cleared and zip PCI bus
master enable bit is setting which will trigger FLR in hardware level
happen at the same time, hardware(FLR flow) will hange.

And when zip 2ECC irq source is not cleared, zip master interface will
be blocked.

So in this patch, we configure qm register to disable FLR when zip PCI
bus master enable bit is setting, and also clear zip error source in
driver probe flow which will make zip master interface is not blocked
(otherwise even FLR is OK, but master interface is block, mailbox
operation will still fail).
Signed-off-by: NZhou Wang <wangzhou1@hisilicon.com>
Reviewed-by: Nfanghao <fanghao11@huawei.com>
Reviewed-by: Nxuzaibo <xuzaibo@huawei.com>
Signed-off-by: Nlingmingqiang <lingmingqiang@huawei.com>
Signed-off-by: NYang Yingliang <yangyingliang@huawei.com>

drivers/crypto/hisilicon/qm.h

@@ -52,6 +52,7 @@
 #define AXI_M_CFG_ENABLE		0xffffffff
 #define QM_PEH_AXUSER_CFG		0x1000cc
 #define QM_PEH_AXUSER_CFG_ENABLE	0x1000d0
+#define PEH_AXUSER_CFG			0x401001
 #define PEH_AXUSER_CFG_ENABLE		0xffffffff
 
 #define QM_DFX_MB_CNT_VF		0x104010

drivers/crypto/hisilicon/zip/zip_main.c

@@ -371,6 +371,8 @@ static void hisi_zip_set_user_domain_and_cache(struct hisi_zip *hisi_zip)
 	/* qm cache */
 	writel(AXI_M_CFG, hisi_zip->qm.io_base + QM_AXI_M_CFG);
 	writel(AXI_M_CFG_ENABLE, hisi_zip->qm.io_base + QM_AXI_M_CFG_ENABLE);
+	/* disable FLR triggered by BME(bus master enable) */
+	writel(PEH_AXUSER_CFG, hisi_zip->qm.io_base + QM_PEH_AXUSER_CFG);
 	writel(PEH_AXUSER_CFG_ENABLE, hisi_zip->qm.io_base +
 	       QM_PEH_AXUSER_CFG_ENABLE);
 
@@ -419,13 +421,17 @@ static void hisi_zip_hw_error_set_state(struct hisi_zip *hisi_zip, bool state)
 		return;
 	}
 
-	if (state)
+	if (state) {
+		/* clear ZIP hw error source if having */
+		writel(HZIP_CORE_INT_DISABLE, hisi_zip->qm.io_base +
+					      HZIP_CORE_INT_SOURCE);
 		/* enable ZIP hw error interrupts */
 		writel(0, hisi_zip->qm.io_base + HZIP_CORE_INT_MASK);
-	else
+	} else {
 		/* disable ZIP hw error interrupts */
 		writel(HZIP_CORE_INT_DISABLE,
 		       hisi_zip->qm.io_base + HZIP_CORE_INT_MASK);
+	}
 }
 
 static inline struct hisi_qm *file_to_qm(struct ctrl_debug_file *file)