From f08a0c9234c86cf0249a5edd58a7abf69617f29f Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Wed, 31 Aug 2016 19:13:04 +0300 Subject: [PATCH] drm/i915: sseu: Convert slice count field to mask In an upcoming patch we'll need the actual mask of slices in addition to their count, so replace the count field with a mask. v2: - Use hweight8() on u8 typed vars instead of hweight32(). (Ben) Reviewed-by: Robert Bragg (v1) Reviewed-by: Ben Widawsky (v1) Tested-by: Ben Widawsky (v1) Signed-off-by: Imre Deak Link: http://patchwork.freedesktop.org/patch/msgid/1472659987-10417-5-git-send-email-imre.deak@intel.com --- drivers/gpu/drm/i915/i915_debugfs.c | 14 ++++++------ drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/intel_device_info.c | 29 ++++++++++++------------ drivers/gpu/drm/i915/intel_lrc.c | 2 +- 4 files changed, 23 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index cbd9c7625450..0ba28a8ad669 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -5007,7 +5007,7 @@ static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv, /* skip disabled subslice */ continue; - sseu->slice_total = 1; + sseu->slice_mask = BIT(0); sseu->subslice_per_slice++; eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) + ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) + @@ -5055,7 +5055,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv, /* skip disabled slice */ continue; - sseu->slice_total++; + sseu->slice_mask |= BIT(s); if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) ss_cnt = INTEL_INFO(dev_priv)->sseu.subslice_per_slice; @@ -5092,19 +5092,19 @@ static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv, u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO); int s; - sseu->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK); + sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK; - if (sseu->slice_total) { + if (sseu->slice_mask) { sseu->subslice_per_slice = INTEL_INFO(dev_priv)->sseu.subslice_per_slice; - sseu->subslice_total = sseu->slice_total * + sseu->subslice_total = hweight8(sseu->slice_mask) * sseu->subslice_per_slice; sseu->eu_per_subslice = INTEL_INFO(dev_priv)->sseu.eu_per_subslice; sseu->eu_total = sseu->eu_per_subslice * sseu->subslice_total; /* subtract fused off EU(s) from enabled slice(s) */ - for (s = 0; s < sseu->slice_total; s++) { + for (s = 0; s < hweight8(sseu->slice_mask); s++) { u8 subslice_7eu = INTEL_INFO(dev_priv)->sseu.subslice_7eu[s]; @@ -5120,7 +5120,7 @@ static void i915_print_sseu_info(struct seq_file *m, bool is_available_info, const char *type = is_available_info ? "Available" : "Enabled"; seq_printf(m, " %s Slice Total: %u\n", type, - sseu->slice_total); + hweight8(sseu->slice_mask)); seq_printf(m, " %s Subslice Total: %u\n", type, sseu->subslice_total); seq_printf(m, " %s Subslice Per Slice: %u\n", type, diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 0b62d36414bd..1ebc5ba69e34 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -672,7 +672,7 @@ struct intel_csr { #define SEP_SEMICOLON ; struct sseu_dev_info { - u8 slice_total; + u8 slice_mask; u8 subslice_total; u8 subslice_per_slice; u8 eu_total; diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index 5db357110ea1..139d5298cde5 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -51,7 +51,7 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv) fuse = I915_READ(CHV_FUSE_GT); - sseu->slice_total = 1; + sseu->slice_mask = BIT(0); if (!(fuse & CHV_FGT_DISABLE_SS0)) { sseu->subslice_per_slice++; @@ -91,27 +91,27 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv) struct sseu_dev_info *sseu = &info->sseu; int s_max = 3, ss_max = 4, eu_max = 8; int s, ss; - u32 fuse2, s_enable, ss_disable, eu_disable; + u32 fuse2, ss_disable, eu_disable; u8 eu_mask = 0xff; fuse2 = I915_READ(GEN8_FUSE2); - s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; + sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; ss_disable = (fuse2 & GEN9_F2_SS_DIS_MASK) >> GEN9_F2_SS_DIS_SHIFT; - sseu->slice_total = hweight32(s_enable); /* * The subslice disable field is global, i.e. it applies * to each of the enabled slices. */ sseu->subslice_per_slice = ss_max - hweight32(ss_disable); - sseu->subslice_total = sseu->slice_total * sseu->subslice_per_slice; + sseu->subslice_total = hweight8(sseu->slice_mask) * + sseu->subslice_per_slice; /* * Iterate through enabled slices and subslices to * count the total enabled EU. */ for (s = 0; s < s_max; s++) { - if (!(s_enable & BIT(s))) + if (!(sseu->slice_mask & BIT(s))) /* skip disabled slice */ continue; @@ -158,7 +158,7 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv) */ sseu->has_slice_pg = (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) && - sseu->slice_total > 1; + hweight8(sseu->slice_mask) > 1; sseu->has_subslice_pg = IS_BROXTON(dev_priv) && sseu->subslice_total > 1; sseu->has_eu_pg = sseu->eu_per_subslice > 2; @@ -195,10 +195,10 @@ static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv) struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu; const int s_max = 3, ss_max = 3, eu_max = 8; int s, ss; - u32 fuse2, eu_disable[s_max], s_enable, ss_disable; + u32 fuse2, eu_disable[s_max], ss_disable; fuse2 = I915_READ(GEN8_FUSE2); - s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; + sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; ss_disable = (fuse2 & GEN8_F2_SS_DIS_MASK) >> GEN8_F2_SS_DIS_SHIFT; eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK; @@ -209,21 +209,20 @@ static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv) ((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) << (32 - GEN8_EU_DIS1_S2_SHIFT)); - sseu->slice_total = hweight32(s_enable); - /* * The subslice disable field is global, i.e. it applies * to each of the enabled slices. */ sseu->subslice_per_slice = ss_max - hweight32(ss_disable); - sseu->subslice_total = sseu->slice_total * sseu->subslice_per_slice; + sseu->subslice_total = hweight8(sseu->slice_mask) * + sseu->subslice_per_slice; /* * Iterate through enabled slices and subslices to * count the total enabled EU. */ for (s = 0; s < s_max; s++) { - if (!(s_enable & (0x1 << s))) + if (!(sseu->slice_mask & BIT(s))) /* skip disabled slice */ continue; @@ -258,7 +257,7 @@ static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv) * BDW supports slice power gating on devices with more than * one slice. */ - sseu->has_slice_pg = (sseu->slice_total > 1); + sseu->has_slice_pg = hweight8(sseu->slice_mask) > 1; sseu->has_subslice_pg = 0; sseu->has_eu_pg = 0; } @@ -375,7 +374,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) info->has_snoop = false; - DRM_DEBUG_DRIVER("slice total: %u\n", info->sseu.slice_total); + DRM_DEBUG_DRIVER("slice total: %u\n", hweight8(info->sseu.slice_mask)); DRM_DEBUG_DRIVER("subslice total: %u\n", info->sseu.subslice_total); DRM_DEBUG_DRIVER("subslice per slice: %u\n", info->sseu.subslice_per_slice); diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 3b076e2bffd4..7209553ab162 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1898,7 +1898,7 @@ make_rpcs(struct drm_i915_private *dev_priv) */ if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) { rpcs |= GEN8_RPCS_S_CNT_ENABLE; - rpcs |= INTEL_INFO(dev_priv)->sseu.slice_total << + rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask) << GEN8_RPCS_S_CNT_SHIFT; rpcs |= GEN8_RPCS_ENABLE; } -- GitLab