提交 e6fae7ff 编写于 作者: G Gao Xun 提交者: Yang Yingliang

RDMA/hns:security review update

driver inclusion
category: cleanup
bugzilla: NA
CVE: NA

--------------------------------

This patch is dedicated to improve the reliability of code.
Reviewed-by: NHu Chunzhi <huchunzhi@huawei.com>
Reviewed-by: NWang Lin <wanglin137@huawei.com>
Reviewed-by: NZhao Weibo <zhaoweibo3@huawei.com>
Signed-off-by: NGao Xun <gaoxun3@huawei.com>
Signed-off-by: NYang Yingliang <yangyingliang@huawei.com>
上级 8d84475d
......@@ -11,20 +11,15 @@ ifeq ($(CONFIG_INFINIBAND_HNS_DFX), m)
ccflags-y += -DCONFIG_INFINIBAND_HNS_DFX
endif
ifeq ($(CONFIG_INFINIBAND_HNS_TEST), m)
ccflags-y += -DCONFIG_INFINIBAND_HNS_TEST
endif
obj-$(CONFIG_INFINIBAND_HNS) += hns-roce.o
hns-roce-objs := hns_roce_main.o hns_roce_cmd.o hns_roce_pd.o \
hns_roce_ah.o hns_roce_hem.o hns_roce_mr.o hns_roce_qp.o \
hns_roce_sysfs.o \
hns_roce_cq.o hns_roce_alloc.o hns_roce_db.o hns_roce_srq.o hns_roce_restrack.o
hns-roce-$(CONFIG_INFINIBAND_HNS_TEST) += roce-customer/rdfx_intf.o roce-customer/rdfx_entry.o roce-customer/hns_roce_test.o
hns_roce_cq.o hns_roce_alloc.o hns_roce_db.o hns_roce_srq.o hns_roce_restrack.o \
roce-customer/rdfx_intf.o roce-customer/rdfx_entry.o
obj-$(CONFIG_INFINIBAND_HNS_HIP06) += hns-roce-hw-v1.o
hns-roce-hw-v1-objs := hns_roce_hw_v1.o
obj-$(CONFIG_INFINIBAND_HNS_HIP08) += hns-roce-hw-v2.o
hns-roce-hw-v2-objs := hns_roce_hw_v2.o hns_roce_hw_v2_dfx.o hns_roce_hw_sysfs_v2.o
hns-roce-hw-v2-$(CONFIG_INFINIBAND_HNS_TEST) += roce-customer/hns_hw_v2_test.o
obj-$(CONFIG_INFINIBAND_HNS_DFX) += hns-roce-cae.o
hns-roce-cae-$(CONFIG_INFINIBAND_HNS_DFX) := roce-customer/rdfx_sysfs.o roce-customer/rdfx_hw_v2.o roce-customer/rdfx_main.o
......@@ -1569,7 +1569,7 @@ enum {
RDFX_FUNC_REG_UMM_MR,
RDFX_FUNC_DEREG_UMM_MR,
};
void alloc_rdfx_info(struct hns_roce_dev *hr_dev);
int alloc_rdfx_info(struct hns_roce_dev *hr_dev);
void rdfx_set_dev_name(struct hns_roce_dev *hr_dev);
void free_rdfx_info(struct hns_roce_dev *hr_dev);
void rdfx_func_cnt(struct hns_roce_dev *hr_dev, int func);
......@@ -1625,7 +1625,7 @@ void rdfx_cp_cqe_buf(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq,
void rdfx_set_rdfx_cq_ci(struct hns_roce_dev *hr_dev,
struct hns_roce_cq *hr_cq);
#else
#define alloc_rdfx_info(hr_dev)
#define alloc_rdfx_info(hr_dev) (0)
#define rdfx_set_dev_name(hr_dev)
#define free_rdfx_info(hr_dev)
#define rdfx_func_cnt(hr_dev, func)
......
......@@ -47,9 +47,6 @@
#include "hns_roce_hem.h"
#include "hns_roce_hw_v2.h"
#ifdef CONFIG_INFINIBAND_HNS_TEST
#include "hns_hw_v2_test.h"
#endif
static int loopback;
static bool qp_lock = true;
......@@ -374,8 +371,6 @@ static int hns_roce_v2_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
}
v2_spin_lock_irqsave(qp_lock, &qp->sq.lock, &flags);
rdfx_func_cnt(hr_dev, RDFX_FUNC_POST_SEND);
rdfx_get_rdfx_qp(hr_dev, ibqp->qp_num);
if (hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN) {
*bad_wr = wr;
......@@ -681,8 +676,6 @@ static int hns_roce_v2_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
if (ret)
goto out;
}
rdfx_cp_sq_wqe_buf(hr_dev, qp, ind, wqe, rc_sq_wqe, wr);
hns_roce_dfx_record_post_send_wqe(qp, wr);
ind++;
......@@ -727,8 +720,6 @@ static int hns_roce_v2_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
qp->sq_next_wqe = ind;
qp->next_sge = sge_ind;
}
rdfx_inc_sq_db_cnt(hr_dev, ibqp->qp_num);
rdfx_put_rdfx_qp(hr_dev, ibqp->qp_num);
qp->dfx_cnt[HNS_ROCE_QP_DFX_POST_SEND]++;
v2_spin_unlock_irqrestore(qp_lock, &qp->sq.lock, &flags);
......@@ -776,9 +767,6 @@ static int hns_roce_v2_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
return -EINVAL;
}
rdfx_func_cnt(hr_dev, RDFX_FUNC_POST_RECV);
rdfx_get_rdfx_qp(hr_dev, ibqp->qp_num);
for (nreq = 0; wr; ++nreq, wr = wr->next) {
if (hns_roce_wq_overflow(&hr_qp->rq, nreq,
hr_qp->ibqp.recv_cq)) {
......@@ -823,9 +811,6 @@ static int hns_roce_v2_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
}
hr_qp->rq.wrid[ind] = wr->wr_id;
rdfx_cp_rq_wqe_buf(hr_dev, hr_qp, ind, wqe, wr);
ind = (ind + 1) & (hr_qp->rq.wqe_cnt - 1);
}
......@@ -842,11 +827,8 @@ static int hns_roce_v2_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
} else {
*hr_qp->rdb.db_record = hr_qp->rq.head & 0xffff;
}
rdfx_inc_rq_db_cnt(hr_dev, hr_qp->qpn);
}
rdfx_put_rdfx_qp(hr_dev, hr_qp->qpn);
hr_qp->dfx_cnt[HNS_ROCE_QP_DFX_POST_RECV]++;
v2_spin_unlock_irqrestore(qp_lock, &hr_qp->rq.lock, &flags);
......@@ -3110,9 +3092,6 @@ static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev,
unsigned int cq_period = HNS_ROCE_V2_CQ_DEFAULT_INTERVAL;
unsigned int cq_max_cnt = HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM;
#ifdef CONFIG_INFINIBAND_HNS_TEST
test_set_cqc_param(&cq_period, &cq_max_cnt);
#endif
cq_context = mb_buf;
memset(cq_context, 0, sizeof(*cq_context));
......@@ -3194,9 +3173,6 @@ static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq,
doorbell[0] = 0;
doorbell[1] = 0;
rdfx_func_cnt(to_hr_dev(ibcq->device), RDFX_FUNC_REQ_NOTIFY_CQ);
rdfx_inc_arm_cq_cnt(to_hr_dev(ibcq->device), hr_cq, flags);
notification_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL;
/*
......@@ -3597,24 +3573,14 @@ static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries,
v2_spin_lock_irqsave(cq_lock, &hr_cq->lock, &flags);
rdfx_func_cnt(hr_dev, RDFX_FUNC_POLL_CQ);
rdfx_get_rdfx_cq(hr_dev, hr_cq->cqn);
if (hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) {
hns_roce_v2_poll_sw_cq(hr_cq, num_entries, wc, &npolled);
goto out;
}
for (npolled = 0; npolled < num_entries; ++npolled) {
rdfx_cp_cqe_buf(hr_dev, hr_cq,
get_sw_cqe_v2(hr_cq, hr_cq->cons_index));
if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled))
break;
rdfx_set_cqe_info(hr_dev, hr_cq,
get_cqe_v2(hr_cq, (hr_cq->cons_index - 1) &
(hr_cq->ib_cq.cqe)));
}
if (npolled) {
......@@ -3623,10 +3589,7 @@ static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries,
hns_roce_v2_cq_set_ci(hr_cq, hr_cq->cons_index);
}
rdfx_set_rdfx_cq_ci(hr_dev, hr_cq);
out:
rdfx_put_rdfx_cq(hr_dev, hr_cq->cqn);
v2_spin_unlock_irqrestore(cq_lock, &hr_cq->lock, &flags);
return npolled;
......@@ -5971,8 +5934,6 @@ static int hns_roce_v2_ceq_int(struct hns_roce_dev *hr_dev,
if (eq->cons_index > EQ_DEPTH_COEFF * eq->entries - 1)
eq->cons_index = 0;
rdfx_inc_ceqe_cnt(hr_dev, eq->eqn);
}
set_eq_cons_index_v2(eq);
......@@ -6208,9 +6169,6 @@ static void hns_roce_config_eqc(struct hns_roce_dev *hr_dev,
eqc = mb_buf;
memset(eqc, 0, sizeof(struct hns_roce_eq_context));
#ifdef CONFIG_INFINIBAND_HNS_TEST
test_set_eq_param(eq->type_flag, &eq_period, &eq_max_cnt, &eq_arm_st);
#endif
if (eq_period * HNS_ROCE_CLOCK_ADJUST > 0xFFFF) {
dev_info(hr_dev->dev, "Config eq_period param(0x%x) out of range for config_eqc, adjusted to 65.\n",
eq_period);
......
......@@ -1398,10 +1398,14 @@ int hns_roce_init(struct hns_roce_dev *hr_dev)
int ret;
struct device *dev = hr_dev->dev;
alloc_rdfx_info(hr_dev);
ret = alloc_rdfx_info(hr_dev);
if (ret) {
dev_err(dev, "Alloc RoCE DFX failed(%d)!\n", ret);
return ret;
}
ret = hns_roce_reset(hr_dev);
if (ret) {
free_rdfx_info(hr_dev);
dev_err(dev, "Reset RoCE engine failed(%d)!\n", ret);
return ret;
}
......@@ -1509,6 +1513,8 @@ int hns_roce_init(struct hns_roce_dev *hr_dev)
dev_err(dev, "Dereset RoCE engine failed!\n");
}
free_rdfx_info(hr_dev);
return ret;
}
EXPORT_SYMBOL_GPL(hns_roce_init);
......
......@@ -39,10 +39,6 @@
#include "hns_roce_cmd.h"
#include "hns_roce_hem.h"
#ifdef CONFIG_INFINIBAND_HNS_TEST
#include "hns_roce_test.h"
#endif
u32 hw_index_to_key(unsigned long ind)
{
return (u32)(ind >> 24) | (ind << 8);
......@@ -1013,10 +1009,6 @@ struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc)
goto err_free;
}
#ifdef CONFIG_INFINIBAND_HNS_TEST
test_set_mr_access(mr);
#endif
ret = hns_roce_mr_enable(to_hr_dev(pd->device), mr);
if (ret)
goto err_mr;
......
// SPDX-License-Identifier: GPL-2.0+
// Copyright (c) 2016-2017 Hisilicon Limited.
#include <linux/module.h>
#include "hns_roce_device.h"
#include "hnae3.h"
#include "hns_roce_hw_v2.h"
#include "hns_hw_v2_test.h"
unsigned int hr_cq_period = 0xa;
module_param(hr_cq_period, uint, 0644);
MODULE_PARM_DESC(hr_cq_period, "timeout of cqe to ceqe");
unsigned int hr_cq_max_cnt = 0x1;
module_param(hr_cq_max_cnt, uint, 0644);
MODULE_PARM_DESC(hr_cq_max_cnt, "max cnt of cqe to ceqe");
unsigned int hr_ceq_period = 0x1;
module_param(hr_ceq_period, uint, 0644);
MODULE_PARM_DESC(hr_ceq_period, "timeout of ceqe to int");
unsigned int hr_aeq_period = 0x1;
module_param(hr_aeq_period, uint, 0644);
MODULE_PARM_DESC(hr_aeq_period, "timeout of aeqe to int");
unsigned int hr_ceq_max_cnt = 0x1;
module_param(hr_ceq_max_cnt, uint, 0644);
MODULE_PARM_DESC(hr_ceq_max_cnt, "max cnt of ceqe to int");
unsigned int hr_aeq_max_cnt = 0x1;
module_param(hr_aeq_max_cnt, uint, 0644);
MODULE_PARM_DESC(hr_aeq_max_cnt, "max cnt of aeqe to int");
unsigned int hr_ceq_arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED;
module_param(hr_ceq_arm_st, uint, 0644);
MODULE_PARM_DESC(hr_ceq_arm_st, "arm state of ceq");
unsigned int hr_aeq_arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED;
module_param(hr_aeq_arm_st, uint, 0644);
MODULE_PARM_DESC(hr_aeq_arm_st, "arm state of aeq");
void test_set_cqc_param(unsigned int *period, unsigned int *max_cnt)
{
*period = hr_cq_period;
*max_cnt = hr_cq_max_cnt;
}
void test_set_eq_param(int eq_type, unsigned int *eq_period,
unsigned int *eq_max_cnt, unsigned int *eq_arm_st)
{
if (eq_type == HNS_ROCE_AEQ) {
*eq_period = hr_aeq_period;
*eq_max_cnt = hr_aeq_max_cnt;
*eq_arm_st = hr_aeq_arm_st;
} else {
*eq_period = hr_ceq_period;
*eq_max_cnt = hr_ceq_max_cnt;
*eq_arm_st = hr_ceq_arm_st;
}
}
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _HNS_HW_V2_TEST_H
#define _HNS_HW_V2_TEST_H
void test_set_cqc_param(unsigned int *period, unsigned int *max_cnt);
void test_set_eq_param(int eq_type, unsigned int *eq_period,
unsigned int *eq_max_cnt, unsigned int *eq_arm_st);
#endif
// SPDX-License-Identifier: GPL-2.0+
// Copyright (c) 2016-2017 Hisilicon Limited.
#include <linux/module.h>
#include "hns_roce_device.h"
#include "hns_roce_test.h"
unsigned int int_mr_access = 7;
module_param(int_mr_access, uint, 0644);
MODULE_PARM_DESC(int_mr_access, "Mr access for ft test");
void test_set_mr_access(struct hns_roce_mr *mr)
{
if (mr->key > 0)
mr->access = int_mr_access;
}
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _HNS_ROCE_TEST_H
#define _HNS_ROCE_TEST_H
void test_set_mr_access(struct hns_roce_mr *mr);
#endif
......@@ -214,9 +214,9 @@ static int rdfx_v2_pkt_store(const char *p_buf, struct rdfx_info *rdfx)
struct hns_roce_cmq_desc desc_cnp_rx = {0};
struct rdfx_query_cnp_rx_cnt *resp_cnp_rx =
(struct rdfx_query_cnp_rx_cnt *)desc_cnp_rx.data;
int ret;
char *buf = (char *)p_buf;
char str[DEF_OPT_STR_LEN];
char str[DEF_OPT_STR_LEN] = {0};
int ret;
int i;
if (!parg_getopt(buf, "c", str))
......@@ -355,7 +355,7 @@ static int rdfx_v2_ceqc_store(const char *p_buf, struct rdfx_info *rdfx)
struct hns_roce_dev *hr_dev;
long long convert_val;
char *buf = (char *)p_buf;
char str[DEF_OPT_STR_LEN];
char str[DEF_OPT_STR_LEN] = {0};
u32 ceqn = 0;
int ret;
......@@ -433,7 +433,7 @@ static int rdfx_v2_aeqc_store(const char *p_buf, struct rdfx_info *rdfx)
struct hns_roce_dev *hr_dev;
long long convert_val;
char *buf = (char *)p_buf;
char str[DEF_OPT_STR_LEN];
char str[DEF_OPT_STR_LEN] = {0};
u32 aeqn = 0;
int ret;
......@@ -534,7 +534,7 @@ static int rdfx_v2_qpc_store(const char *p_buf, struct rdfx_info *rdfx)
struct hns_roce_dev *hr_dev;
long long convert_val;
char *buf = (char *)p_buf;
char str[DEF_OPT_STR_LEN];
char str[DEF_OPT_STR_LEN] = {0};
u32 qpn = 0;
u64 bt0_ba = 0;
u64 bt1_ba = 0;
......@@ -637,7 +637,7 @@ static int rdfx_v2_cqc_store(const char *p_buf, struct rdfx_info *rdfx)
struct hns_roce_dev *hr_dev;
long long convert_val;
char *buf = (char *)p_buf;
char str[DEF_OPT_STR_LEN];
char str[DEF_OPT_STR_LEN] = {0};
u64 bt0_ba = 0;
u64 bt1_ba = 0;
u32 cqn = 0;
......@@ -740,7 +740,7 @@ static int rdfx_v2_srqc_store(const char *p_buf, struct rdfx_info *rdfx)
struct hns_roce_dev *hr_dev;
long long convert_val;
char *buf = (char *)p_buf;
char str[DEF_OPT_STR_LEN];
char str[DEF_OPT_STR_LEN] = {0};
u64 bt0_ba = 0;
u64 bt1_ba = 0;
u32 srqn = 0;
......@@ -843,7 +843,7 @@ static int rdfx_v2_mpt_store(const char *p_buf, struct rdfx_info *rdfx)
struct hns_roce_dev *hr_dev;
long long convert_val;
char *buf = (char *)p_buf;
char str[DEF_OPT_STR_LEN];
char str[DEF_OPT_STR_LEN] = {0};
u64 bt0_ba = 0;
u64 bt1_ba = 0;
int key;
......
......@@ -80,13 +80,13 @@ static void mr_release(struct kref *ref)
kfree(rdfx_mr);
}
void alloc_rdfx_info(struct hns_roce_dev *hr_dev)
int alloc_rdfx_info(struct hns_roce_dev *hr_dev)
{
struct rdfx_info *rdfx;
rdfx = kzalloc(sizeof(*rdfx), GFP_KERNEL);
if (ZERO_OR_NULL_PTR(rdfx))
return;
return -ENOMEM;
hr_dev->dfx_priv = rdfx;
rdfx->priv = hr_dev;
......@@ -104,6 +104,7 @@ void alloc_rdfx_info(struct hns_roce_dev *hr_dev)
spin_lock_init(&rdfx->mr.mr_lock);
spin_lock_init(&rdfx->eq.eq_lock);
return 0;
}
void rdfx_set_dev_name(struct hns_roce_dev *hr_dev)
......@@ -173,6 +174,8 @@ void free_rdfx_info(struct hns_roce_dev *hr_dev)
{
struct rdfx_info *rdfx = (struct rdfx_info *)hr_dev->dfx_priv;
if (!rdfx)
return;
rdfx_clean_list(rdfx);
kfree(rdfx);
hr_dev->dfx_priv = NULL;
......
......@@ -76,12 +76,15 @@ int parg_getopt(char *input, char *optstring, char *parg)
p++;
cnt++;
}
if (cnt >= DEF_OPT_STR_LEN)
if (cnt >= DEF_OPT_STR_LEN) {
kfree(_input);
return -EINVAL;
}
*p = '\0';
p -= cnt;
strcpy(parg, p);
kfree(_input);
return 0;
}
......@@ -196,7 +199,7 @@ struct rdfx_info *rdfx_find_rdfx_info(char *dev_name)
int i;
if (!strlen(dev_name))
return rdfx_top_info_list[0].rdfx;
return NULL;
for (i = 0; i < MAX_IB_DEV; i++) {
if (!rdfx_top_info_list[i].dev)
......@@ -284,8 +287,11 @@ static void rdfx_add_device(struct ib_device *ib_dev)
ops = (rdfx_top_info_list[i].rdfx)->ops;
ret = ops->add_sysfs(rdfx_top_info_list[i].rdfx);
if (ret)
if (ret) {
rdfx_top_info_list[i].rdfx = NULL;
rdfx_top_info_list[i].dev = NULL;
pr_err("rdfx add hw sysfs failed\n");
}
}
static void rdfx_remove_device(struct ib_device *ib_dev, void *client_data)
......@@ -324,8 +330,16 @@ static int __init rdfx_init(void)
/*default content:/sys/class */
drv_class = class_create(THIS_MODULE, DFX_DEVICE_NAME);
if (IS_ERR(drv_class)) {
pr_err("rdfx register client failed\n");
goto class_create_failed;
}
drv_device = device_create(drv_class, NULL, MKDEV(major, 0),
NULL, DFX_DEVICE_NAME);
if (IS_ERR(drv_device)) {
pr_err("rdfx register device failed\n");
goto device_regist_failed;
}
memset(rdfx_top_info_list, 0, sizeof(rdfx_top_info_list));
......@@ -348,7 +362,9 @@ static int __init rdfx_init(void)
ib_unregister_client(&rdfx_client);
register_client_failed:
device_unregister(drv_device);
device_regist_failed:
class_destroy(drv_class);
class_create_failed:
unregister_chrdev(major, DFX_DEVICE_NAME);
return ret;
......
......@@ -39,8 +39,8 @@ static int rdfx_pd_store(const char *p_buf)
char *buf = (char *)p_buf;
struct rdfx_info *rdfx;
long long convert_val;
char dev_name[DEF_OPT_STR_LEN];
char str[DEF_OPT_STR_LEN];
char dev_name[DEF_OPT_STR_LEN] = {0};
char str[DEF_OPT_STR_LEN] = {0};
u32 pdn = 0;
parg_getopt(buf, "d:", dev_name);
......@@ -121,14 +121,14 @@ static int show_qp_detail(struct rdfx_qp_info *rdfx_qp)
pr_info("\n");
pr_info("sig_wqe_cnt bd_cnt inline_cnt\n");
pr_info("sig_wqe_cnt db_cnt inline_cnt\n");
pr_info(" 0x%x 0x%x 0x%x\n",
atomic_read(&rdfx_qp->sq.sig_wqe_cnt),
atomic_read(&rdfx_qp->sq.db_cnt),
atomic_read(&rdfx_qp->sq.inline_cnt));
pr_info("\n");
pr_info("***************** RQ INFO *****************\n");
pr_info("rq_wqe_cnt bd_cnt inline_cnt\n");
pr_info("rq_wqe_cnt db_cnt inline_cnt\n");
pr_info(" 0x%x 0x%x 0x%x\n",
atomic_read(&rdfx_qp->rq.rq_wqe_cnt),
atomic_read(&rdfx_qp->rq.db_cnt),
......@@ -432,8 +432,8 @@ static int rdfx_cq_store(const char *p_buf)
struct rdfx_cq_info *rdfx_cq = NULL;
struct rdfx_info *rdfx;
char *buf = (char *)p_buf;
char dev_name[DEF_OPT_STR_LEN];
char str[DEF_OPT_STR_LEN];
char dev_name[DEF_OPT_STR_LEN] = {0};
char str[DEF_OPT_STR_LEN] = {0};
u32 cqe_index = 0;
u32 cqn = 0;
......@@ -482,8 +482,8 @@ static int rdfx_mr_store(const char *p_buf)
char *buf = (char *)p_buf;
struct rdfx_info *rdfx;
long long convert_val;
char dev_name[DEF_OPT_STR_LEN];
char str[DEF_OPT_STR_LEN];
char dev_name[DEF_OPT_STR_LEN] = {0};
char str[DEF_OPT_STR_LEN] = {0};
u32 key;
parg_getopt(buf, "d:", dev_name);
......@@ -534,8 +534,8 @@ static int rdfx_eq_store(const char *p_buf)
long long convert_val;
char *buf = (char *)p_buf;
struct rdfx_info *rdfx;
char dev_name[DEF_OPT_STR_LEN];
char str[DEF_OPT_STR_LEN];
char dev_name[DEF_OPT_STR_LEN] = {0};
char str[DEF_OPT_STR_LEN] = {0};
u32 ceqn;
parg_getopt(buf, "d:", dev_name);
......@@ -566,7 +566,7 @@ static int roce_dev_store(const char *p_buf)
{
char *buf = (char *)p_buf;
struct rdfx_info *rdfx;
char dev_name[DEF_OPT_STR_LEN];
char dev_name[DEF_OPT_STR_LEN] = {0};
int i;
parg_getopt(buf, "d:", dev_name);
......
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