RDMA/hns: Export symbol for roce-customer

driver inclusion
category: bugfix
bugzilla: NA
CVE: NA

Add new items for set_mtpt_pbl, It is a
requirement only for Application, and no
need to upstream.

Feature or Bugfix:Feature
Signed-off-by: Nwangsirong <wangsirong@huawei.com>
Signed-off-by: Nliyangyang (M) <liyangyang20@huawei.com>
Reviewed-by: Noulijun <oulijun@huawei.com>
Reviewed-by: Nliuyixian <liuyixian@huawei.com>
Reviewed-by: NYang Yingliang <yangyingliang@huawei.com>
Signed-off-by: NYang Yingliang <yangyingliang@huawei.com>

drivers/infiniband/hw/hns/hns_roce_alloc.c

@@ -63,7 +63,7 @@ int hns_roce_bitmap_alloc(struct hns_roce_bitmap *bitmap, unsigned long *obj)
 
 	return ret;
 }
-
+EXPORT_SYMBOL_GPL(hns_roce_bitmap_alloc);
 void hns_roce_bitmap_free(struct hns_roce_bitmap *bitmap, unsigned long obj,
 			  int rr)
 {

drivers/infiniband/hw/hns/hns_roce_device.h

@@ -106,6 +106,7 @@
 #define MR_TYPE_MR				0x00
 #define MR_TYPE_FRMR				0x01
 #define MR_TYPE_DMA				0x03
+#define MR_TYPE_UMM				0x04
 
 #define PKEY_ID					0xffff
 #define GUID_LEN				8
@@ -1466,6 +1467,17 @@ int hns_roce_fill_res_entry(struct sk_buff *msg,
 int hns_roce_register_sysfs(struct hns_roce_dev *hr_dev);
 void hns_roce_unregister_sysfs(struct hns_roce_dev *hr_dev);
 
+u32 hw_index_to_key(unsigned long ind);
+int hns_roce_mr_enable(struct hns_roce_dev *hr_dev,
+			      struct hns_roce_mr *mr);
+void hns_roce_mr_free(struct hns_roce_dev *hr_dev,
+			     struct hns_roce_mr *mr);
+int hns_roce_ib_umem_write_mr(struct hns_roce_dev *hr_dev,
+				     struct hns_roce_mr *mr,
+				     struct ib_umem *umem);
+int hns_roce_mr_alloc(struct hns_roce_dev *hr_dev, u32 pd, u64 iova,
+			     u64 size, u32 access, int npages,
+			     struct hns_roce_mr *mr);
 enum hns_phy_state {
 	HNS_ROCE_PHY_SLEEP		= 1,
 	HNS_ROCE_PHY_POLLING		= 2,
@@ -1512,7 +1524,9 @@ enum {
 	RDFX_FUNC_REG_USER_MR,
 	RDFX_FUNC_REREG_USER_MR,
 	RDFX_FUNC_DEREG_MR,
-	RDFX_FUNC_PORT_IMMUTABLE
+	RDFX_FUNC_PORT_IMMUTABLE,
+	RDFX_FUNC_REG_UMM_MR,
+	RDFX_FUNC_DEREG_UMM_MR,
 };
 void alloc_rdfx_info(struct hns_roce_dev *hr_dev);
 void rdfx_set_dev_name(struct hns_roce_dev *hr_dev);

drivers/infiniband/hw/hns/hns_roce_hw_v2.c

@@ -2459,10 +2459,17 @@ static int set_mtpt_pbl(struct hns_roce_v2_mpt_entry *mpt_entry,
 	mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1]));
 	roce_set_field(mpt_entry->byte_64_buf_pa1, V2_MPT_BYTE_64_PA1_H_M,
 		       V2_MPT_BYTE_64_PA1_H_S, upper_32_bits(pages[1]));
+
+	if (mr->type != MR_TYPE_UMM)
 		roce_set_field(mpt_entry->byte_64_buf_pa1,
 			       V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M,
 			       V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S,
 			       mr->pbl_buf_pg_sz + PG_SHIFT_OFFSET);
+	else
+		roce_set_field(mpt_entry->byte_64_buf_pa1,
+			       V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M,
+			       V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S,
+			       mr->pbl_buf_pg_sz + mr->umem->page_shift - 12);
 
 	free_page((unsigned long)pages);
 
@@ -2505,7 +2512,7 @@ static int hns_roce_v2_write_mtpt(void *mb_buf, struct hns_roce_mr *mr,
 		     (mr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0));
 
 	roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S,
-		     mr->type == MR_TYPE_MR ? 0 : 1);
+		   (mr->type == MR_TYPE_MR || mr->type == MR_TYPE_UMM) ? 0 : 1);
 	roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_INNER_PA_VLD_S,
 		     1);
 

drivers/infiniband/hw/hns/hns_roce_mr.c

@@ -43,10 +43,11 @@
 #include "hns_roce_test.h"
 #endif
 
-static u32 hw_index_to_key(unsigned long ind)
+u32 hw_index_to_key(unsigned long ind)
 {
 	return (u32)(ind >> 24) | (ind << 8);
 }
+EXPORT_SYMBOL_GPL(hw_index_to_key);
 
 unsigned long key_to_hw_index(u32 key)
 {
@@ -576,7 +577,7 @@ static int hns_roce_mhop_alloc(struct hns_roce_dev *hr_dev, int npages,
 	return -ENOMEM;
 }
 
-static int hns_roce_mr_alloc(struct hns_roce_dev *hr_dev, u32 pd, u64 iova,
+int hns_roce_mr_alloc(struct hns_roce_dev *hr_dev, u32 pd, u64 iova,
 			     u64 size, u32 access, int npages,
 			     struct hns_roce_mr *mr)
 {
@@ -621,6 +622,7 @@ static int hns_roce_mr_alloc(struct hns_roce_dev *hr_dev, u32 pd, u64 iova,
 
 	return ret;
 }
+EXPORT_SYMBOL_GPL(hns_roce_mr_alloc);
 
 static void hns_roce_mhop_free(struct hns_roce_dev *hr_dev,
 			       struct hns_roce_mr *mr)
@@ -704,7 +706,7 @@ static void hns_roce_mhop_free(struct hns_roce_dev *hr_dev,
 	}
 }
 
-static void hns_roce_mr_free(struct hns_roce_dev *hr_dev,
+void hns_roce_mr_free(struct hns_roce_dev *hr_dev,
 			     struct hns_roce_mr *mr)
 {
 	struct device *dev = hr_dev->dev;
@@ -737,8 +739,9 @@ static void hns_roce_mr_free(struct hns_roce_dev *hr_dev,
 	hns_roce_bitmap_free(&hr_dev->mr_table.mtpt_bitmap,
 			     key_to_hw_index(mr->key), BITMAP_NO_RR);
 }
+EXPORT_SYMBOL_GPL(hns_roce_mr_free);
 
-static int hns_roce_mr_enable(struct hns_roce_dev *hr_dev,
+int hns_roce_mr_enable(struct hns_roce_dev *hr_dev,
 			      struct hns_roce_mr *mr)
 {
 	int ret;
@@ -789,6 +792,7 @@ static int hns_roce_mr_enable(struct hns_roce_dev *hr_dev,
 	hns_roce_table_put(hr_dev, &mr_table->mtpt_table, mtpt_idx);
 	return ret;
 }
+EXPORT_SYMBOL_GPL(hns_roce_mr_enable);
 
 static int hns_roce_write_mtt_chunk(struct hns_roce_dev *hr_dev,
 				    struct hns_roce_mtt *mtt, u32 start_index,
@@ -1108,7 +1112,7 @@ int hns_roce_ib_umem_write_mtt(struct hns_roce_dev *hr_dev,
 	return ret;
 }
 
-static int hns_roce_ib_umem_write_mr(struct hns_roce_dev *hr_dev,
+int hns_roce_ib_umem_write_mr(struct hns_roce_dev *hr_dev,
 				     struct hns_roce_mr *mr,
 				     struct ib_umem *umem)
 {
@@ -1154,6 +1158,7 @@ static int hns_roce_ib_umem_write_mr(struct hns_roce_dev *hr_dev,
 
 	return 0;
 }
+EXPORT_SYMBOL_GPL(hns_roce_ib_umem_write_mr);
 
 struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
 				   u64 virt_addr, int access_flags,