diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index 2b62efce73c5ab492137ca39da939ae664a12071..0aa6662650cc5fb6f48729c6b14b5e300f68b8b0 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -791,7 +791,7 @@ bool dcn_validate_bandwidth(
 	v->phyclk_per_state[1] = v->phyclkv_mid0p72;
 	v->phyclk_per_state[0] = v->phyclkv_min0p65;
 
-	if (dc->public.debug.use_max_voltage) {
+	if (dc->public.debug.disable_pipe_split) {
 		v->max_dppclk[1] = v->max_dppclk_vnom0p8;
 		v->max_dppclk[0] = v->max_dppclk_vnom0p8;
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 52c36007382f533a517f3d649879a06f3662340a..62493c4a47d1516b78d783bf6b68eef0ce804d55 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -170,7 +170,7 @@ struct dc_debug {
 	bool disable_hubp_power_gate;
 	bool disable_pplib_wm_range;
 	bool use_dml_wm;
-	bool use_max_voltage;
+	bool disable_pipe_split;
 	int sr_exit_time_ns;
 	int sr_enter_plus_exit_time_ns;
 	int urgent_latency_ns;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 77fc251d45ba2f94b2ee89c4f3e935b2b0317d9f..c7840e0e3ae5555333bbc877d7afec4827360dea 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -443,7 +443,7 @@ static const struct dc_debug debug_defaults_drv = {
 		.disable_pplib_wm_range = false,
 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 		.use_dml_wm = false,
-		.use_max_voltage = false
+		.disable_pipe_split = false
 #endif
 };
 
@@ -456,7 +456,7 @@ static const struct dc_debug debug_defaults_diags = {
 		.disable_pplib_clock_request = true,
 		.disable_pplib_wm_range = true,
 		.use_dml_wm = false,
-		.use_max_voltage = false
+		.disable_pipe_split = false
 #endif
 };