From 8c5288de1ebe82205ca1c2adf7e4aa2f59d21e9a Mon Sep 17 00:00:00 2001 From: Hao Fang Date: Thu, 11 Jul 2019 14:41:36 +0800 Subject: [PATCH] ACC :crypto/hisilicon/qm: mask eqe irq for uacce_q driver inclusion category: bugfix bugzilla: NA CVE: NA crypto/hisilicon/qm: mask eqe irq for uacce_q. Signed-off-by: Hao Fang Reviewed-by: xuzaibo Signed-off-by: lingmingqiang Signed-off-by: Yang Yingliang --- drivers/crypto/hisilicon/qm.c | 5 +++-- drivers/crypto/hisilicon/qm.h | 1 + 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/crypto/hisilicon/qm.c b/drivers/crypto/hisilicon/qm.c index aac9a643f1ab..6ae487014d1c 100644 --- a/drivers/crypto/hisilicon/qm.c +++ b/drivers/crypto/hisilicon/qm.c @@ -1101,6 +1101,7 @@ struct hisi_qp *hisi_qm_create_qp(struct hisi_qm *qm, u8 alg_type) qp->qp_id = qp_id; qp->alg_type = alg_type; + qp->c_flag = 1; init_completion(&qp->completion); return qp; @@ -1221,7 +1222,7 @@ static int qm_cq_ctx_cfg(struct hisi_qp *qp, int qp_id, int pasid) cqc->dw3 = QM_MK_CQC_DW3_V2(QM_QC_CQE_SIZE); cqc->w8 = 0; /* rand_qc */ } - cqc->dw6 = 1 << QM_CQ_PHASE_SHIFT | 1 << QM_CQ_FLAG_SHIFT; + cqc->dw6 = 1 << QM_CQ_PHASE_SHIFT | qp->c_flag << QM_CQ_FLAG_SHIFT; ret = qm_mb(qm, QM_MB_CMD_CQC, cqc_dma, qp_id, 0, 0); if (qm->use_dma_api) { @@ -1620,7 +1621,7 @@ static long hisi_qm_uacce_ioctl(struct uacce_queue *q, unsigned int cmd, qm_set_sqctype(q, qp_ctx.qc_type); qp_ctx.id = qp->qp_id; - + qp->c_flag = 0; if (copy_to_user((void __user *)arg, &qp_ctx, sizeof(struct hisi_qp_ctx))) return -EFAULT; diff --git a/drivers/crypto/hisilicon/qm.h b/drivers/crypto/hisilicon/qm.h index cde27eca44ea..42f76dbb3b24 100644 --- a/drivers/crypto/hisilicon/qm.h +++ b/drivers/crypto/hisilicon/qm.h @@ -281,6 +281,7 @@ struct hisi_qp { u32 qp_id; u8 alg_type; u8 req_type; + u8 c_flag; struct qm_dma qdma; void *sqe; -- GitLab