From 844a3b632b76f5d5e85eb9b9edfbd7de41e4999f Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Thu, 19 Apr 2012 04:04:33 -0600 Subject: [PATCH] ARM: OMAP2+: hwmod data: remove forward declarations, reorganize MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reorganize the hwmod data to declare the IP blocks first and the interconnects second. This allows us to remove the forward declarations, which this patch also does. Saves some lines of source data. While here, take the opportunity to synchronize the order of the OMAP44xx hwmod data with the autogenerator output -- it's slightly different due to past mismerges -- and fix a few minor typos and whitespace problems in the files. Signed-off-by: Paul Walmsley Cc: Benoît Cousson --- arch/arm/mach-omap2/omap_hwmod_2420_data.c | 921 ++-- arch/arm/mach-omap2/omap_hwmod_2430_data.c | 1144 +++-- arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 4400 ++++++++++---------- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 4000 +++++++++--------- 4 files changed, 5080 insertions(+), 5385 deletions(-) diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index 42921ff12e86..f74335ff4097 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -33,55 +33,15 @@ /* * OMAP2420 hardware module integration data * - * ALl of the data in this section should be autogeneratable from the + * All of the data in this section should be autogeneratable from the * TI hardware database or other technical documentation. Data that * is driver-specific or driver-kernel integration-specific belongs * elsewhere. */ -static struct omap_hwmod omap2420_mpu_hwmod; -static struct omap_hwmod omap2420_iva_hwmod; -static struct omap_hwmod omap2420_l3_main_hwmod; -static struct omap_hwmod omap2420_l4_core_hwmod; -static struct omap_hwmod omap2420_dss_core_hwmod; -static struct omap_hwmod omap2420_dss_dispc_hwmod; -static struct omap_hwmod omap2420_dss_rfbi_hwmod; -static struct omap_hwmod omap2420_dss_venc_hwmod; -static struct omap_hwmod omap2420_wd_timer2_hwmod; -static struct omap_hwmod omap2420_gpio1_hwmod; -static struct omap_hwmod omap2420_gpio2_hwmod; -static struct omap_hwmod omap2420_gpio3_hwmod; -static struct omap_hwmod omap2420_gpio4_hwmod; -static struct omap_hwmod omap2420_dma_system_hwmod; -static struct omap_hwmod omap2420_mcspi1_hwmod; -static struct omap_hwmod omap2420_mcspi2_hwmod; - -/* L3 -> L4_CORE interface */ -static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = { - .master = &omap2420_l3_main_hwmod, - .slave = &omap2420_l4_core_hwmod, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* MPU -> L3 interface */ -static struct omap_hwmod_ocp_if omap2420_mpu__l3_main = { - .master = &omap2420_mpu_hwmod, - .slave = &omap2420_l3_main_hwmod, - .user = OCP_USER_MPU, -}; - -/* DSS -> l3 */ -static struct omap_hwmod_ocp_if omap2420_dss__l3 = { - .master = &omap2420_dss_core_hwmod, - .slave = &omap2420_l3_main_hwmod, - .fw = { - .omap2 = { - .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS, - .flags = OMAP_FIREWALL_L3, - } - }, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; +/* + * IP blocks + */ /* L3 */ static struct omap_hwmod omap2420_l3_main_hwmod = { @@ -90,85 +50,6 @@ static struct omap_hwmod omap2420_l3_main_hwmod = { .flags = HWMOD_NO_IDLEST, }; -static struct omap_hwmod omap2420_l4_wkup_hwmod; -static struct omap_hwmod omap2420_uart1_hwmod; -static struct omap_hwmod omap2420_uart2_hwmod; -static struct omap_hwmod omap2420_uart3_hwmod; -static struct omap_hwmod omap2420_i2c1_hwmod; -static struct omap_hwmod omap2420_i2c2_hwmod; -static struct omap_hwmod omap2420_mcbsp1_hwmod; -static struct omap_hwmod omap2420_mcbsp2_hwmod; - -/* l4 core -> mcspi1 interface */ -static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_mcspi1_hwmod, - .clk = "mcspi1_ick", - .addr = omap2_mcspi1_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4 core -> mcspi2 interface */ -static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_mcspi2_hwmod, - .clk = "mcspi2_ick", - .addr = omap2_mcspi2_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4_CORE -> L4_WKUP interface */ -static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_l4_wkup_hwmod, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 CORE -> UART1 interface */ -static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_uart1_hwmod, - .clk = "uart1_ick", - .addr = omap2xxx_uart1_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 CORE -> UART2 interface */ -static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_uart2_hwmod, - .clk = "uart2_ick", - .addr = omap2xxx_uart2_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 PER -> UART3 interface */ -static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_uart3_hwmod, - .clk = "uart3_ick", - .addr = omap2xxx_uart3_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 CORE -> I2C1 interface */ -static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_i2c1_hwmod, - .clk = "i2c1_ick", - .addr = omap2_i2c1_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 CORE -> I2C2 interface */ -static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_i2c2_hwmod, - .clk = "i2c2_ick", - .addr = omap2_i2c2_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* L4 CORE */ static struct omap_hwmod omap2420_l4_core_hwmod = { .name = "l4_core", @@ -190,22 +71,7 @@ static struct omap_hwmod omap2420_mpu_hwmod = { .main_clk = "mpu_ck", }; -/* - * IVA1 interface data - */ - -/* IVA <- L3 interface */ -static struct omap_hwmod_ocp_if omap2420_l3__iva = { - .master = &omap2420_l3_main_hwmod, - .slave = &omap2420_iva_hwmod, - .clk = "iva1_ifck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* - * IVA2 (IVA2) - */ - +/* IVA2 (IVA2) */ static struct omap_hwmod omap2420_iva_hwmod = { .name = "iva", .class = &iva_hwmod_class, @@ -213,36 +79,15 @@ static struct omap_hwmod omap2420_iva_hwmod = { /* always-on timers dev attribute */ static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { - .timer_capability = OMAP_TIMER_ALWON, + .timer_capability = OMAP_TIMER_ALWON, }; /* pwm timers dev attribute */ static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { - .timer_capability = OMAP_TIMER_HAS_PWM, + .timer_capability = OMAP_TIMER_HAS_PWM, }; /* timer1 */ -static struct omap_hwmod omap2420_timer1_hwmod; - -static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = { - { - .pa_start = 0x48028000, - .pa_end = 0x48028000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_wkup -> timer1 */ -static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = { - .master = &omap2420_l4_wkup_hwmod, - .slave = &omap2420_timer1_hwmod, - .clk = "gpt1_ick", - .addr = omap2420_timer1_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer1 hwmod */ static struct omap_hwmod omap2420_timer1_hwmod = { .name = "timer1", .mpu_irqs = omap2_timer1_mpu_irqs, @@ -261,18 +106,6 @@ static struct omap_hwmod omap2420_timer1_hwmod = { }; /* timer2 */ -static struct omap_hwmod omap2420_timer2_hwmod; - -/* l4_core -> timer2 */ -static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_timer2_hwmod, - .clk = "gpt2_ick", - .addr = omap2xxx_timer2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer2 hwmod */ static struct omap_hwmod omap2420_timer2_hwmod = { .name = "timer2", .mpu_irqs = omap2_timer2_mpu_irqs, @@ -291,18 +124,6 @@ static struct omap_hwmod omap2420_timer2_hwmod = { }; /* timer3 */ -static struct omap_hwmod omap2420_timer3_hwmod; - -/* l4_core -> timer3 */ -static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_timer3_hwmod, - .clk = "gpt3_ick", - .addr = omap2xxx_timer3_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer3 hwmod */ static struct omap_hwmod omap2420_timer3_hwmod = { .name = "timer3", .mpu_irqs = omap2_timer3_mpu_irqs, @@ -321,18 +142,6 @@ static struct omap_hwmod omap2420_timer3_hwmod = { }; /* timer4 */ -static struct omap_hwmod omap2420_timer4_hwmod; - -/* l4_core -> timer4 */ -static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_timer4_hwmod, - .clk = "gpt4_ick", - .addr = omap2xxx_timer4_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer4 hwmod */ static struct omap_hwmod omap2420_timer4_hwmod = { .name = "timer4", .mpu_irqs = omap2_timer4_mpu_irqs, @@ -351,18 +160,6 @@ static struct omap_hwmod omap2420_timer4_hwmod = { }; /* timer5 */ -static struct omap_hwmod omap2420_timer5_hwmod; - -/* l4_core -> timer5 */ -static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_timer5_hwmod, - .clk = "gpt5_ick", - .addr = omap2xxx_timer5_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer5 hwmod */ static struct omap_hwmod omap2420_timer5_hwmod = { .name = "timer5", .mpu_irqs = omap2_timer5_mpu_irqs, @@ -380,20 +177,7 @@ static struct omap_hwmod omap2420_timer5_hwmod = { .class = &omap2xxx_timer_hwmod_class, }; - /* timer6 */ -static struct omap_hwmod omap2420_timer6_hwmod; - -/* l4_core -> timer6 */ -static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_timer6_hwmod, - .clk = "gpt6_ick", - .addr = omap2xxx_timer6_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer6 hwmod */ static struct omap_hwmod omap2420_timer6_hwmod = { .name = "timer6", .mpu_irqs = omap2_timer6_mpu_irqs, @@ -412,18 +196,6 @@ static struct omap_hwmod omap2420_timer6_hwmod = { }; /* timer7 */ -static struct omap_hwmod omap2420_timer7_hwmod; - -/* l4_core -> timer7 */ -static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_timer7_hwmod, - .clk = "gpt7_ick", - .addr = omap2xxx_timer7_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer7 hwmod */ static struct omap_hwmod omap2420_timer7_hwmod = { .name = "timer7", .mpu_irqs = omap2_timer7_mpu_irqs, @@ -442,18 +214,6 @@ static struct omap_hwmod omap2420_timer7_hwmod = { }; /* timer8 */ -static struct omap_hwmod omap2420_timer8_hwmod; - -/* l4_core -> timer8 */ -static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_timer8_hwmod, - .clk = "gpt8_ick", - .addr = omap2xxx_timer8_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer8 hwmod */ static struct omap_hwmod omap2420_timer8_hwmod = { .name = "timer8", .mpu_irqs = omap2_timer8_mpu_irqs, @@ -472,18 +232,6 @@ static struct omap_hwmod omap2420_timer8_hwmod = { }; /* timer9 */ -static struct omap_hwmod omap2420_timer9_hwmod; - -/* l4_core -> timer9 */ -static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_timer9_hwmod, - .clk = "gpt9_ick", - .addr = omap2xxx_timer9_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer9 hwmod */ static struct omap_hwmod omap2420_timer9_hwmod = { .name = "timer9", .mpu_irqs = omap2_timer9_mpu_irqs, @@ -502,18 +250,6 @@ static struct omap_hwmod omap2420_timer9_hwmod = { }; /* timer10 */ -static struct omap_hwmod omap2420_timer10_hwmod; - -/* l4_core -> timer10 */ -static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_timer10_hwmod, - .clk = "gpt10_ick", - .addr = omap2_timer10_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer10 hwmod */ static struct omap_hwmod omap2420_timer10_hwmod = { .name = "timer10", .mpu_irqs = omap2_timer10_mpu_irqs, @@ -532,18 +268,6 @@ static struct omap_hwmod omap2420_timer10_hwmod = { }; /* timer11 */ -static struct omap_hwmod omap2420_timer11_hwmod; - -/* l4_core -> timer11 */ -static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_timer11_hwmod, - .clk = "gpt11_ick", - .addr = omap2_timer11_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer11 hwmod */ static struct omap_hwmod omap2420_timer11_hwmod = { .name = "timer11", .mpu_irqs = omap2_timer11_mpu_irqs, @@ -562,18 +286,6 @@ static struct omap_hwmod omap2420_timer11_hwmod = { }; /* timer12 */ -static struct omap_hwmod omap2420_timer12_hwmod; - -/* l4_core -> timer12 */ -static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_timer12_hwmod, - .clk = "gpt12_ick", - .addr = omap2xxx_timer12_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer12 hwmod */ static struct omap_hwmod omap2420_timer12_hwmod = { .name = "timer12", .mpu_irqs = omap2xxx_timer12_mpu_irqs, @@ -591,24 +303,6 @@ static struct omap_hwmod omap2420_timer12_hwmod = { .class = &omap2xxx_timer_hwmod_class, }; -/* l4_wkup -> wd_timer2 */ -static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = { - { - .pa_start = 0x48022000, - .pa_end = 0x4802207f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = { - .master = &omap2420_l4_wkup_hwmod, - .slave = &omap2420_wd_timer2_hwmod, - .clk = "mpu_wdt_ick", - .addr = omap2420_wd_timer2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap2420_wd_timer2_hwmod = { .name = "wd_timer2", .class = &omap2xxx_wd_timer_hwmod_class, @@ -625,7 +319,6 @@ static struct omap_hwmod omap2420_wd_timer2_hwmod = { }; /* UART1 */ - static struct omap_hwmod omap2420_uart1_hwmod = { .name = "uart1", .mpu_irqs = omap2_uart1_mpu_irqs, @@ -644,7 +337,6 @@ static struct omap_hwmod omap2420_uart1_hwmod = { }; /* UART2 */ - static struct omap_hwmod omap2420_uart2_hwmod = { .name = "uart2", .mpu_irqs = omap2_uart2_mpu_irqs, @@ -663,7 +355,6 @@ static struct omap_hwmod omap2420_uart2_hwmod = { }; /* UART3 */ - static struct omap_hwmod omap2420_uart3_hwmod = { .name = "uart3", .mpu_irqs = omap2_uart3_mpu_irqs, @@ -683,21 +374,6 @@ static struct omap_hwmod omap2420_uart3_hwmod = { /* dss */ -/* l4_core -> dss */ -static struct omap_hwmod_ocp_if omap2420_l4_core__dss = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_dss_core_hwmod, - .clk = "dss_ick", - .addr = omap2_dss_addrs, - .fw = { - .omap2 = { - .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, - .flags = OMAP_FIREWALL_L4, - } - }, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod_opt_clk dss_opt_clks[] = { /* * The DSS HW needs all DSS clocks enabled during reset. The dss_core @@ -726,21 +402,6 @@ static struct omap_hwmod omap2420_dss_core_hwmod = { .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET, }; -/* l4_core -> dss_dispc */ -static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_dss_dispc_hwmod, - .clk = "dss_ick", - .addr = omap2_dss_dispc_addrs, - .fw = { - .omap2 = { - .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION, - .flags = OMAP_FIREWALL_L4, - } - }, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap2420_dss_dispc_hwmod = { .name = "dss_dispc", .class = &omap2_dispc_hwmod_class, @@ -759,21 +420,6 @@ static struct omap_hwmod omap2420_dss_dispc_hwmod = { .dev_attr = &omap2_3_dss_dispc_dev_attr }; -/* l4_core -> dss_rfbi */ -static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_dss_rfbi_hwmod, - .clk = "dss_ick", - .addr = omap2_dss_rfbi_addrs, - .fw = { - .omap2 = { - .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, - .flags = OMAP_FIREWALL_L4, - } - }, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { { .role = "ick", .clk = "dss_ick" }, }; @@ -794,21 +440,6 @@ static struct omap_hwmod omap2420_dss_rfbi_hwmod = { .flags = HWMOD_NO_IDLEST, }; -/* l4_core -> dss_venc */ -static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_dss_venc_hwmod, - .clk = "dss_ick", - .addr = omap2_dss_venc_addrs, - .fw = { - .omap2 = { - .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION, - .flags = OMAP_FIREWALL_L4, - } - }, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap2420_dss_venc_hwmod = { .name = "dss_venc", .class = &omap2_venc_hwmod_class, @@ -847,7 +478,6 @@ static struct omap_i2c_dev_attr i2c_dev_attr = { }; /* I2C1 */ - static struct omap_hwmod omap2420_i2c1_hwmod = { .name = "i2c1", .mpu_irqs = omap2_i2c1_mpu_irqs, @@ -868,7 +498,6 @@ static struct omap_hwmod omap2420_i2c1_hwmod = { }; /* I2C2 */ - static struct omap_hwmod omap2420_i2c2_hwmod = { .name = "i2c2", .mpu_irqs = omap2_i2c2_mpu_irqs, @@ -888,78 +517,6 @@ static struct omap_hwmod omap2420_i2c2_hwmod = { .flags = HWMOD_16BIT_REG, }; -/* l4_wkup -> gpio1 */ -static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = { - { - .pa_start = 0x48018000, - .pa_end = 0x480181ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = { - .master = &omap2420_l4_wkup_hwmod, - .slave = &omap2420_gpio1_hwmod, - .clk = "gpios_ick", - .addr = omap2420_gpio1_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_wkup -> gpio2 */ -static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = { - { - .pa_start = 0x4801a000, - .pa_end = 0x4801a1ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = { - .master = &omap2420_l4_wkup_hwmod, - .slave = &omap2420_gpio2_hwmod, - .clk = "gpios_ick", - .addr = omap2420_gpio2_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_wkup -> gpio3 */ -static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = { - { - .pa_start = 0x4801c000, - .pa_end = 0x4801c1ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = { - .master = &omap2420_l4_wkup_hwmod, - .slave = &omap2420_gpio3_hwmod, - .clk = "gpios_ick", - .addr = omap2420_gpio3_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_wkup -> gpio4 */ -static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = { - { - .pa_start = 0x4801e000, - .pa_end = 0x4801e1ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = { - .master = &omap2420_l4_wkup_hwmod, - .slave = &omap2420_gpio4_hwmod, - .clk = "gpios_ick", - .addr = omap2420_gpio4_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* gpio dev_attr */ static struct omap_gpio_dev_attr gpio_dev_attr = { .bank_width = 32, @@ -1049,23 +606,6 @@ static struct omap_dma_dev_attr dma_dev_attr = { .lch_count = 32, }; -/* dma_system -> L3 */ -static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = { - .master = &omap2420_dma_system_hwmod, - .slave = &omap2420_l3_main_hwmod, - .clk = "core_l3_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_core -> dma_system */ -static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_dma_system_hwmod, - .clk = "sdma_ick", - .addr = omap2_dma_system_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap2420_dma_system_hwmod = { .name = "dma", .class = &omap2xxx_dma_hwmod_class, @@ -1076,21 +616,12 @@ static struct omap_hwmod omap2420_dma_system_hwmod = { }; /* mailbox */ -static struct omap_hwmod omap2420_mailbox_hwmod; static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = { { .name = "dsp", .irq = 26 }, { .name = "iva", .irq = 34 }, { .irq = -1 } }; -/* l4_core -> mailbox */ -static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_mailbox_hwmod, - .addr = omap2_mailbox_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap2420_mailbox_hwmod = { .name = "mailbox", .class = &omap2xxx_mailbox_hwmod_class, @@ -1169,15 +700,6 @@ static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = { { .irq = -1 } }; -/* l4_core -> mcbsp1 */ -static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_mcbsp1_hwmod, - .clk = "mcbsp1_ick", - .addr = omap2_mcbsp1_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap2420_mcbsp1_hwmod = { .name = "mcbsp1", .class = &omap2420_mcbsp_hwmod_class, @@ -1202,15 +724,6 @@ static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = { { .irq = -1 } }; -/* l4_core -> mcbsp2 */ -static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_mcbsp2_hwmod, - .clk = "mcbsp2_ick", - .addr = omap2xxx_mcbsp2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap2420_mcbsp2_hwmod = { .name = "mcbsp2", .class = &omap2420_mcbsp_hwmod_class, @@ -1228,6 +741,426 @@ static struct omap_hwmod omap2420_mcbsp2_hwmod = { }, }; +/* + * interfaces + */ + +/* L3 -> L4_CORE interface */ +static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = { + .master = &omap2420_l3_main_hwmod, + .slave = &omap2420_l4_core_hwmod, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* MPU -> L3 interface */ +static struct omap_hwmod_ocp_if omap2420_mpu__l3_main = { + .master = &omap2420_mpu_hwmod, + .slave = &omap2420_l3_main_hwmod, + .user = OCP_USER_MPU, +}; + +/* DSS -> l3 */ +static struct omap_hwmod_ocp_if omap2420_dss__l3 = { + .master = &omap2420_dss_core_hwmod, + .slave = &omap2420_l3_main_hwmod, + .fw = { + .omap2 = { + .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS, + .flags = OMAP_FIREWALL_L3, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4 core -> mcspi1 interface */ +static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_mcspi1_hwmod, + .clk = "mcspi1_ick", + .addr = omap2_mcspi1_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4 core -> mcspi2 interface */ +static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_mcspi2_hwmod, + .clk = "mcspi2_ick", + .addr = omap2_mcspi2_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4_CORE -> L4_WKUP interface */ +static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_l4_wkup_hwmod, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> UART1 interface */ +static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_uart1_hwmod, + .clk = "uart1_ick", + .addr = omap2xxx_uart1_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> UART2 interface */ +static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_uart2_hwmod, + .clk = "uart2_ick", + .addr = omap2xxx_uart2_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 PER -> UART3 interface */ +static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_uart3_hwmod, + .clk = "uart3_ick", + .addr = omap2xxx_uart3_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> I2C1 interface */ +static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_i2c1_hwmod, + .clk = "i2c1_ick", + .addr = omap2_i2c1_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> I2C2 interface */ +static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_i2c2_hwmod, + .clk = "i2c2_ick", + .addr = omap2_i2c2_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* IVA <- L3 interface */ +static struct omap_hwmod_ocp_if omap2420_l3__iva = { + .master = &omap2420_l3_main_hwmod, + .slave = &omap2420_iva_hwmod, + .clk = "iva1_ifck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = { + { + .pa_start = 0x48028000, + .pa_end = 0x48028000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_wkup -> timer1 */ +static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = { + .master = &omap2420_l4_wkup_hwmod, + .slave = &omap2420_timer1_hwmod, + .clk = "gpt1_ick", + .addr = omap2420_timer1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> timer2 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer2_hwmod, + .clk = "gpt2_ick", + .addr = omap2xxx_timer2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> timer3 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer3_hwmod, + .clk = "gpt3_ick", + .addr = omap2xxx_timer3_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> timer4 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer4_hwmod, + .clk = "gpt4_ick", + .addr = omap2xxx_timer4_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> timer5 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer5_hwmod, + .clk = "gpt5_ick", + .addr = omap2xxx_timer5_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> timer6 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer6_hwmod, + .clk = "gpt6_ick", + .addr = omap2xxx_timer6_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> timer7 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer7_hwmod, + .clk = "gpt7_ick", + .addr = omap2xxx_timer7_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> timer8 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer8_hwmod, + .clk = "gpt8_ick", + .addr = omap2xxx_timer8_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> timer9 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer9_hwmod, + .clk = "gpt9_ick", + .addr = omap2xxx_timer9_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> timer10 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer10_hwmod, + .clk = "gpt10_ick", + .addr = omap2_timer10_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> timer11 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer11_hwmod, + .clk = "gpt11_ick", + .addr = omap2_timer11_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> timer12 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer12_hwmod, + .clk = "gpt12_ick", + .addr = omap2xxx_timer12_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> wd_timer2 */ +static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = { + { + .pa_start = 0x48022000, + .pa_end = 0x4802207f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = { + .master = &omap2420_l4_wkup_hwmod, + .slave = &omap2420_wd_timer2_hwmod, + .clk = "mpu_wdt_ick", + .addr = omap2420_wd_timer2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> dss */ +static struct omap_hwmod_ocp_if omap2420_l4_core__dss = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_dss_core_hwmod, + .clk = "dss_ick", + .addr = omap2_dss_addrs, + .fw = { + .omap2 = { + .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> dss_dispc */ +static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_dss_dispc_hwmod, + .clk = "dss_ick", + .addr = omap2_dss_dispc_addrs, + .fw = { + .omap2 = { + .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> dss_rfbi */ +static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_dss_rfbi_hwmod, + .clk = "dss_ick", + .addr = omap2_dss_rfbi_addrs, + .fw = { + .omap2 = { + .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> dss_venc */ +static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_dss_venc_hwmod, + .clk = "dss_ick", + .addr = omap2_dss_venc_addrs, + .fw = { + .omap2 = { + .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION, + .flags = OMAP_FIREWALL_L4, + } + }, + .flags = OCPIF_SWSUP_IDLE, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> gpio1 */ +static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = { + { + .pa_start = 0x48018000, + .pa_end = 0x480181ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = { + .master = &omap2420_l4_wkup_hwmod, + .slave = &omap2420_gpio1_hwmod, + .clk = "gpios_ick", + .addr = omap2420_gpio1_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> gpio2 */ +static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = { + { + .pa_start = 0x4801a000, + .pa_end = 0x4801a1ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = { + .master = &omap2420_l4_wkup_hwmod, + .slave = &omap2420_gpio2_hwmod, + .clk = "gpios_ick", + .addr = omap2420_gpio2_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> gpio3 */ +static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = { + { + .pa_start = 0x4801c000, + .pa_end = 0x4801c1ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = { + .master = &omap2420_l4_wkup_hwmod, + .slave = &omap2420_gpio3_hwmod, + .clk = "gpios_ick", + .addr = omap2420_gpio3_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> gpio4 */ +static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = { + { + .pa_start = 0x4801e000, + .pa_end = 0x4801e1ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = { + .master = &omap2420_l4_wkup_hwmod, + .slave = &omap2420_gpio4_hwmod, + .clk = "gpios_ick", + .addr = omap2420_gpio4_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dma_system -> L3 */ +static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = { + .master = &omap2420_dma_system_hwmod, + .slave = &omap2420_l3_main_hwmod, + .clk = "core_l3_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> dma_system */ +static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_dma_system_hwmod, + .clk = "sdma_ick", + .addr = omap2_dma_system_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> mailbox */ +static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_mailbox_hwmod, + .addr = omap2_mailbox_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> mcbsp1 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_mcbsp1_hwmod, + .clk = "mcbsp1_ick", + .addr = omap2_mcbsp1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> mcbsp2 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_mcbsp2_hwmod, + .clk = "mcbsp2_ick", + .addr = omap2xxx_mcbsp2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = { &omap2420_l3_main__l4_core, &omap2420_mpu__l3_main, diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 5036cbb3913c..da8fef06fae0 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -34,64 +34,15 @@ /* * OMAP2430 hardware module integration data * - * ALl of the data in this section should be autogeneratable from the + * All of the data in this section should be autogeneratable from the * TI hardware database or other technical documentation. Data that * is driver-specific or driver-kernel integration-specific belongs * elsewhere. */ -static struct omap_hwmod omap2430_mpu_hwmod; -static struct omap_hwmod omap2430_iva_hwmod; -static struct omap_hwmod omap2430_l3_main_hwmod; -static struct omap_hwmod omap2430_l4_core_hwmod; -static struct omap_hwmod omap2430_dss_core_hwmod; -static struct omap_hwmod omap2430_dss_dispc_hwmod; -static struct omap_hwmod omap2430_dss_rfbi_hwmod; -static struct omap_hwmod omap2430_dss_venc_hwmod; -static struct omap_hwmod omap2430_wd_timer2_hwmod; -static struct omap_hwmod omap2430_gpio1_hwmod; -static struct omap_hwmod omap2430_gpio2_hwmod; -static struct omap_hwmod omap2430_gpio3_hwmod; -static struct omap_hwmod omap2430_gpio4_hwmod; -static struct omap_hwmod omap2430_gpio5_hwmod; -static struct omap_hwmod omap2430_dma_system_hwmod; -static struct omap_hwmod omap2430_mcbsp1_hwmod; -static struct omap_hwmod omap2430_mcbsp2_hwmod; -static struct omap_hwmod omap2430_mcbsp3_hwmod; -static struct omap_hwmod omap2430_mcbsp4_hwmod; -static struct omap_hwmod omap2430_mcbsp5_hwmod; -static struct omap_hwmod omap2430_mcspi1_hwmod; -static struct omap_hwmod omap2430_mcspi2_hwmod; -static struct omap_hwmod omap2430_mcspi3_hwmod; -static struct omap_hwmod omap2430_mmc1_hwmod; -static struct omap_hwmod omap2430_mmc2_hwmod; - -/* L3 -> L4_CORE interface */ -static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = { - .master = &omap2430_l3_main_hwmod, - .slave = &omap2430_l4_core_hwmod, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* MPU -> L3 interface */ -static struct omap_hwmod_ocp_if omap2430_mpu__l3_main = { - .master = &omap2430_mpu_hwmod, - .slave = &omap2430_l3_main_hwmod, - .user = OCP_USER_MPU, -}; - -/* DSS -> l3 */ -static struct omap_hwmod_ocp_if omap2430_dss__l3 = { - .master = &omap2430_dss_core_hwmod, - .slave = &omap2430_l3_main_hwmod, - .fw = { - .omap2 = { - .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS, - .flags = OMAP_FIREWALL_L3, - } - }, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; +/* + * IP blocks + */ /* L3 */ static struct omap_hwmod omap2430_l3_main_hwmod = { @@ -100,114 +51,6 @@ static struct omap_hwmod omap2430_l3_main_hwmod = { .flags = HWMOD_NO_IDLEST, }; -static struct omap_hwmod omap2430_l4_wkup_hwmod; -static struct omap_hwmod omap2430_uart1_hwmod; -static struct omap_hwmod omap2430_uart2_hwmod; -static struct omap_hwmod omap2430_uart3_hwmod; -static struct omap_hwmod omap2430_i2c1_hwmod; -static struct omap_hwmod omap2430_i2c2_hwmod; - -static struct omap_hwmod omap2430_usbhsotg_hwmod; - -/* l3_core -> usbhsotg interface */ -static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = { - .master = &omap2430_usbhsotg_hwmod, - .slave = &omap2430_l3_main_hwmod, - .clk = "core_l3_ck", - .user = OCP_USER_MPU, -}; - -/* L4 CORE -> I2C1 interface */ -static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_i2c1_hwmod, - .clk = "i2c1_ick", - .addr = omap2_i2c1_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 CORE -> I2C2 interface */ -static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_i2c2_hwmod, - .clk = "i2c2_ick", - .addr = omap2_i2c2_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4_CORE -> L4_WKUP interface */ -static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_l4_wkup_hwmod, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 CORE -> UART1 interface */ -static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_uart1_hwmod, - .clk = "uart1_ick", - .addr = omap2xxx_uart1_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 CORE -> UART2 interface */ -static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_uart2_hwmod, - .clk = "uart2_ick", - .addr = omap2xxx_uart2_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 PER -> UART3 interface */ -static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_uart3_hwmod, - .clk = "uart3_ick", - .addr = omap2xxx_uart3_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* -* usbhsotg interface data -*/ -static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = { - { - .pa_start = OMAP243X_HS_BASE, - .pa_end = OMAP243X_HS_BASE + SZ_4K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_core ->usbhsotg interface */ -static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_usbhsotg_hwmod, - .clk = "usb_l4_ick", - .addr = omap2430_usbhsotg_addrs, - .user = OCP_USER_MPU, -}; - -/* L4 CORE -> MMC1 interface */ -static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_mmc1_hwmod, - .clk = "mmchs1_ick", - .addr = omap2430_mmc1_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 CORE -> MMC2 interface */ -static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_mmc2_hwmod, - .clk = "mmchs2_ick", - .addr = omap2430_mmc2_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* L4 CORE */ static struct omap_hwmod omap2430_l4_core_hwmod = { .name = "l4_core", @@ -215,33 +58,6 @@ static struct omap_hwmod omap2430_l4_core_hwmod = { .flags = HWMOD_NO_IDLEST, }; -/* l4 core -> mcspi1 interface */ -static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_mcspi1_hwmod, - .clk = "mcspi1_ick", - .addr = omap2_mcspi1_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4 core -> mcspi2 interface */ -static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_mcspi2_hwmod, - .clk = "mcspi2_ick", - .addr = omap2_mcspi2_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4 core -> mcspi3 interface */ -static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_mcspi3_hwmod, - .clk = "mcspi3_ick", - .addr = omap2430_mcspi3_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* L4 WKUP */ static struct omap_hwmod omap2430_l4_wkup_hwmod = { .name = "l4_wkup", @@ -256,22 +72,7 @@ static struct omap_hwmod omap2430_mpu_hwmod = { .main_clk = "mpu_ck", }; -/* - * IVA2_1 interface data - */ - -/* IVA2 <- L3 interface */ -static struct omap_hwmod_ocp_if omap2430_l3__iva = { - .master = &omap2430_l3_main_hwmod, - .slave = &omap2430_iva_hwmod, - .clk = "dsp_fck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* - * IVA2 (IVA2) - */ - +/* IVA2 (IVA2) */ static struct omap_hwmod omap2430_iva_hwmod = { .name = "iva", .class = &iva_hwmod_class, @@ -279,36 +80,15 @@ static struct omap_hwmod omap2430_iva_hwmod = { /* always-on timers dev attribute */ static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { - .timer_capability = OMAP_TIMER_ALWON, + .timer_capability = OMAP_TIMER_ALWON, }; /* pwm timers dev attribute */ static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { - .timer_capability = OMAP_TIMER_HAS_PWM, + .timer_capability = OMAP_TIMER_HAS_PWM, }; /* timer1 */ -static struct omap_hwmod omap2430_timer1_hwmod; - -static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = { - { - .pa_start = 0x49018000, - .pa_end = 0x49018000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_wkup -> timer1 */ -static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = { - .master = &omap2430_l4_wkup_hwmod, - .slave = &omap2430_timer1_hwmod, - .clk = "gpt1_ick", - .addr = omap2430_timer1_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer1 hwmod */ static struct omap_hwmod omap2430_timer1_hwmod = { .name = "timer1", .mpu_irqs = omap2_timer1_mpu_irqs, @@ -327,18 +107,6 @@ static struct omap_hwmod omap2430_timer1_hwmod = { }; /* timer2 */ -static struct omap_hwmod omap2430_timer2_hwmod; - -/* l4_core -> timer2 */ -static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_timer2_hwmod, - .clk = "gpt2_ick", - .addr = omap2xxx_timer2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer2 hwmod */ static struct omap_hwmod omap2430_timer2_hwmod = { .name = "timer2", .mpu_irqs = omap2_timer2_mpu_irqs, @@ -357,18 +125,6 @@ static struct omap_hwmod omap2430_timer2_hwmod = { }; /* timer3 */ -static struct omap_hwmod omap2430_timer3_hwmod; - -/* l4_core -> timer3 */ -static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_timer3_hwmod, - .clk = "gpt3_ick", - .addr = omap2xxx_timer3_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer3 hwmod */ static struct omap_hwmod omap2430_timer3_hwmod = { .name = "timer3", .mpu_irqs = omap2_timer3_mpu_irqs, @@ -387,18 +143,6 @@ static struct omap_hwmod omap2430_timer3_hwmod = { }; /* timer4 */ -static struct omap_hwmod omap2430_timer4_hwmod; - -/* l4_core -> timer4 */ -static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_timer4_hwmod, - .clk = "gpt4_ick", - .addr = omap2xxx_timer4_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer4 hwmod */ static struct omap_hwmod omap2430_timer4_hwmod = { .name = "timer4", .mpu_irqs = omap2_timer4_mpu_irqs, @@ -417,18 +161,6 @@ static struct omap_hwmod omap2430_timer4_hwmod = { }; /* timer5 */ -static struct omap_hwmod omap2430_timer5_hwmod; - -/* l4_core -> timer5 */ -static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_timer5_hwmod, - .clk = "gpt5_ick", - .addr = omap2xxx_timer5_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer5 hwmod */ static struct omap_hwmod omap2430_timer5_hwmod = { .name = "timer5", .mpu_irqs = omap2_timer5_mpu_irqs, @@ -447,18 +179,6 @@ static struct omap_hwmod omap2430_timer5_hwmod = { }; /* timer6 */ -static struct omap_hwmod omap2430_timer6_hwmod; - -/* l4_core -> timer6 */ -static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_timer6_hwmod, - .clk = "gpt6_ick", - .addr = omap2xxx_timer6_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer6 hwmod */ static struct omap_hwmod omap2430_timer6_hwmod = { .name = "timer6", .mpu_irqs = omap2_timer6_mpu_irqs, @@ -477,18 +197,6 @@ static struct omap_hwmod omap2430_timer6_hwmod = { }; /* timer7 */ -static struct omap_hwmod omap2430_timer7_hwmod; - -/* l4_core -> timer7 */ -static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_timer7_hwmod, - .clk = "gpt7_ick", - .addr = omap2xxx_timer7_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer7 hwmod */ static struct omap_hwmod omap2430_timer7_hwmod = { .name = "timer7", .mpu_irqs = omap2_timer7_mpu_irqs, @@ -507,18 +215,6 @@ static struct omap_hwmod omap2430_timer7_hwmod = { }; /* timer8 */ -static struct omap_hwmod omap2430_timer8_hwmod; - -/* l4_core -> timer8 */ -static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_timer8_hwmod, - .clk = "gpt8_ick", - .addr = omap2xxx_timer8_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer8 hwmod */ static struct omap_hwmod omap2430_timer8_hwmod = { .name = "timer8", .mpu_irqs = omap2_timer8_mpu_irqs, @@ -537,18 +233,6 @@ static struct omap_hwmod omap2430_timer8_hwmod = { }; /* timer9 */ -static struct omap_hwmod omap2430_timer9_hwmod; - -/* l4_core -> timer9 */ -static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_timer9_hwmod, - .clk = "gpt9_ick", - .addr = omap2xxx_timer9_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer9 hwmod */ static struct omap_hwmod omap2430_timer9_hwmod = { .name = "timer9", .mpu_irqs = omap2_timer9_mpu_irqs, @@ -567,18 +251,6 @@ static struct omap_hwmod omap2430_timer9_hwmod = { }; /* timer10 */ -static struct omap_hwmod omap2430_timer10_hwmod; - -/* l4_core -> timer10 */ -static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_timer10_hwmod, - .clk = "gpt10_ick", - .addr = omap2_timer10_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer10 hwmod */ static struct omap_hwmod omap2430_timer10_hwmod = { .name = "timer10", .mpu_irqs = omap2_timer10_mpu_irqs, @@ -597,18 +269,6 @@ static struct omap_hwmod omap2430_timer10_hwmod = { }; /* timer11 */ -static struct omap_hwmod omap2430_timer11_hwmod; - -/* l4_core -> timer11 */ -static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_timer11_hwmod, - .clk = "gpt11_ick", - .addr = omap2_timer11_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer11 hwmod */ static struct omap_hwmod omap2430_timer11_hwmod = { .name = "timer11", .mpu_irqs = omap2_timer11_mpu_irqs, @@ -627,18 +287,6 @@ static struct omap_hwmod omap2430_timer11_hwmod = { }; /* timer12 */ -static struct omap_hwmod omap2430_timer12_hwmod; - -/* l4_core -> timer12 */ -static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_timer12_hwmod, - .clk = "gpt12_ick", - .addr = omap2xxx_timer12_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer12 hwmod */ static struct omap_hwmod omap2430_timer12_hwmod = { .name = "timer12", .mpu_irqs = omap2xxx_timer12_mpu_irqs, @@ -656,24 +304,6 @@ static struct omap_hwmod omap2430_timer12_hwmod = { .class = &omap2xxx_timer_hwmod_class, }; -/* l4_wkup -> wd_timer2 */ -static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = { - { - .pa_start = 0x49016000, - .pa_end = 0x4901607f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = { - .master = &omap2430_l4_wkup_hwmod, - .slave = &omap2430_wd_timer2_hwmod, - .clk = "mpu_wdt_ick", - .addr = omap2430_wd_timer2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap2430_wd_timer2_hwmod = { .name = "wd_timer2", .class = &omap2xxx_wd_timer_hwmod_class, @@ -726,7 +356,6 @@ static struct omap_hwmod omap2430_uart2_hwmod = { }; /* UART3 */ - static struct omap_hwmod omap2430_uart3_hwmod = { .name = "uart3", .mpu_irqs = omap2_uart3_mpu_irqs, @@ -745,16 +374,6 @@ static struct omap_hwmod omap2430_uart3_hwmod = { }; /* dss */ - -/* l4_core -> dss */ -static struct omap_hwmod_ocp_if omap2430_l4_core__dss = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_dss_core_hwmod, - .clk = "dss_ick", - .addr = omap2_dss_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod_opt_clk dss_opt_clks[] = { /* * The DSS HW needs all DSS clocks enabled during reset. The dss_core @@ -783,15 +402,6 @@ static struct omap_hwmod omap2430_dss_core_hwmod = { .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET, }; -/* l4_core -> dss_dispc */ -static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_dss_dispc_hwmod, - .clk = "dss_ick", - .addr = omap2_dss_dispc_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap2430_dss_dispc_hwmod = { .name = "dss_dispc", .class = &omap2_dispc_hwmod_class, @@ -810,15 +420,6 @@ static struct omap_hwmod omap2430_dss_dispc_hwmod = { .dev_attr = &omap2_3_dss_dispc_dev_attr }; -/* l4_core -> dss_rfbi */ -static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_dss_rfbi_hwmod, - .clk = "dss_ick", - .addr = omap2_dss_rfbi_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { { .role = "ick", .clk = "dss_ick" }, }; @@ -839,15 +440,6 @@ static struct omap_hwmod omap2430_dss_rfbi_hwmod = { .flags = HWMOD_NO_IDLEST, }; -/* l4_core -> dss_venc */ -static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_dss_venc_hwmod, - .clk = "dss_ick", - .addr = omap2_dss_venc_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap2430_dss_venc_hwmod = { .name = "dss_venc", .class = &omap2_venc_hwmod_class, @@ -934,96 +526,6 @@ static struct omap_hwmod omap2430_i2c2_hwmod = { .dev_attr = &i2c_dev_attr, }; -/* l4_wkup -> gpio1 */ -static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = { - { - .pa_start = 0x4900C000, - .pa_end = 0x4900C1ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = { - .master = &omap2430_l4_wkup_hwmod, - .slave = &omap2430_gpio1_hwmod, - .clk = "gpios_ick", - .addr = omap2430_gpio1_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_wkup -> gpio2 */ -static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = { - { - .pa_start = 0x4900E000, - .pa_end = 0x4900E1ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = { - .master = &omap2430_l4_wkup_hwmod, - .slave = &omap2430_gpio2_hwmod, - .clk = "gpios_ick", - .addr = omap2430_gpio2_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_wkup -> gpio3 */ -static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = { - { - .pa_start = 0x49010000, - .pa_end = 0x490101ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = { - .master = &omap2430_l4_wkup_hwmod, - .slave = &omap2430_gpio3_hwmod, - .clk = "gpios_ick", - .addr = omap2430_gpio3_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_wkup -> gpio4 */ -static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = { - { - .pa_start = 0x49012000, - .pa_end = 0x490121ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = { - .master = &omap2430_l4_wkup_hwmod, - .slave = &omap2430_gpio4_hwmod, - .clk = "gpios_ick", - .addr = omap2430_gpio4_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_core -> gpio5 */ -static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = { - { - .pa_start = 0x480B6000, - .pa_end = 0x480B61ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_gpio5_hwmod, - .clk = "gpio5_ick", - .addr = omap2430_gpio5_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* gpio dev_attr */ static struct omap_gpio_dev_attr gpio_dev_attr = { .bank_width = 32, @@ -1137,23 +639,6 @@ static struct omap_dma_dev_attr dma_dev_attr = { .lch_count = 32, }; -/* dma_system -> L3 */ -static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = { - .master = &omap2430_dma_system_hwmod, - .slave = &omap2430_l3_main_hwmod, - .clk = "core_l3_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_core -> dma_system */ -static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_dma_system_hwmod, - .clk = "sdma_ick", - .addr = omap2_dma_system_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap2430_dma_system_hwmod = { .name = "dma", .class = &omap2xxx_dma_hwmod_class, @@ -1164,20 +649,11 @@ static struct omap_hwmod omap2430_dma_system_hwmod = { }; /* mailbox */ -static struct omap_hwmod omap2430_mailbox_hwmod; static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = { { .irq = 26 }, { .irq = -1 } }; -/* l4_core -> mailbox */ -static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_mailbox_hwmod, - .addr = omap2_mailbox_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap2430_mailbox_hwmod = { .name = "mailbox", .class = &omap2xxx_mailbox_hwmod_class, @@ -1276,9 +752,7 @@ static struct omap_hwmod omap2430_mcspi3_hwmod = { .dev_attr = &omap_mcspi3_dev_attr, }; -/* - * usbhsotg - */ +/* usbhsotg */ static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = { .rev_offs = 0x0400, .sysc_offs = 0x0404, @@ -1354,15 +828,6 @@ static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = { { .irq = -1 } }; -/* l4_core -> mcbsp1 */ -static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_mcbsp1_hwmod, - .clk = "mcbsp1_ick", - .addr = omap2_mcbsp1_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap2430_mcbsp1_hwmod = { .name = "mcbsp1", .class = &omap2430_mcbsp_hwmod_class, @@ -1388,15 +853,6 @@ static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = { { .irq = -1 } }; -/* l4_core -> mcbsp2 */ -static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_mcbsp2_hwmod, - .clk = "mcbsp2_ick", - .addr = omap2xxx_mcbsp2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap2430_mcbsp2_hwmod = { .name = "mcbsp2", .class = &omap2430_mcbsp_hwmod_class, @@ -1422,25 +878,6 @@ static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = { { .irq = -1 } }; -static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = { - { - .name = "mpu", - .pa_start = 0x4808C000, - .pa_end = 0x4808C0ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_core -> mcbsp3 */ -static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_mcbsp3_hwmod, - .clk = "mcbsp3_ick", - .addr = omap2430_mcbsp3_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap2430_mcbsp3_hwmod = { .name = "mcbsp3", .class = &omap2430_mcbsp_hwmod_class, @@ -1472,25 +909,6 @@ static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = { - { - .name = "mpu", - .pa_start = 0x4808E000, - .pa_end = 0x4808E0ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_core -> mcbsp4 */ -static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_mcbsp4_hwmod, - .clk = "mcbsp4_ick", - .addr = omap2430_mcbsp4_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap2430_mcbsp4_hwmod = { .name = "mcbsp4", .class = &omap2430_mcbsp_hwmod_class, @@ -1522,25 +940,6 @@ static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = { - { - .name = "mpu", - .pa_start = 0x48096000, - .pa_end = 0x480960ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_core -> mcbsp5 */ -static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_mcbsp5_hwmod, - .clk = "mcbsp5_ick", - .addr = omap2430_mcbsp5_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap2430_mcbsp5_hwmod = { .name = "mcbsp5", .class = &omap2430_mcbsp_hwmod_class, @@ -1559,7 +958,6 @@ static struct omap_hwmod omap2430_mcbsp5_hwmod = { }; /* MMC/SD/SDIO common */ - static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = { .rev_offs = 0x1fc, .sysc_offs = 0x10, @@ -1577,7 +975,6 @@ static struct omap_hwmod_class omap2430_mmc_class = { }; /* MMC/SD/SDIO1 */ - static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = { { .irq = 83 }, { .irq = -1 } @@ -1619,7 +1016,6 @@ static struct omap_hwmod omap2430_mmc1_hwmod = { }; /* MMC/SD/SDIO2 */ - static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = { { .irq = 86 }, { .irq = -1 } @@ -1655,6 +1051,530 @@ static struct omap_hwmod omap2430_mmc2_hwmod = { .class = &omap2430_mmc_class, }; +/* + * interfaces + */ + +/* L3 -> L4_CORE interface */ +static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = { + .master = &omap2430_l3_main_hwmod, + .slave = &omap2430_l4_core_hwmod, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* MPU -> L3 interface */ +static struct omap_hwmod_ocp_if omap2430_mpu__l3_main = { + .master = &omap2430_mpu_hwmod, + .slave = &omap2430_l3_main_hwmod, + .user = OCP_USER_MPU, +}; + +/* DSS -> l3 */ +static struct omap_hwmod_ocp_if omap2430_dss__l3 = { + .master = &omap2430_dss_core_hwmod, + .slave = &omap2430_l3_main_hwmod, + .fw = { + .omap2 = { + .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS, + .flags = OMAP_FIREWALL_L3, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_core -> usbhsotg interface */ +static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = { + .master = &omap2430_usbhsotg_hwmod, + .slave = &omap2430_l3_main_hwmod, + .clk = "core_l3_ck", + .user = OCP_USER_MPU, +}; + +/* L4 CORE -> I2C1 interface */ +static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_i2c1_hwmod, + .clk = "i2c1_ick", + .addr = omap2_i2c1_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> I2C2 interface */ +static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_i2c2_hwmod, + .clk = "i2c2_ick", + .addr = omap2_i2c2_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4_CORE -> L4_WKUP interface */ +static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_l4_wkup_hwmod, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> UART1 interface */ +static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_uart1_hwmod, + .clk = "uart1_ick", + .addr = omap2xxx_uart1_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> UART2 interface */ +static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_uart2_hwmod, + .clk = "uart2_ick", + .addr = omap2xxx_uart2_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 PER -> UART3 interface */ +static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_uart3_hwmod, + .clk = "uart3_ick", + .addr = omap2xxx_uart3_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = { + { + .pa_start = OMAP243X_HS_BASE, + .pa_end = OMAP243X_HS_BASE + SZ_4K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_core ->usbhsotg interface */ +static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_usbhsotg_hwmod, + .clk = "usb_l4_ick", + .addr = omap2430_usbhsotg_addrs, + .user = OCP_USER_MPU, +}; + +/* L4 CORE -> MMC1 interface */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_mmc1_hwmod, + .clk = "mmchs1_ick", + .addr = omap2430_mmc1_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> MMC2 interface */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_mmc2_hwmod, + .clk = "mmchs2_ick", + .addr = omap2430_mmc2_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4 core -> mcspi1 interface */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_mcspi1_hwmod, + .clk = "mcspi1_ick", + .addr = omap2_mcspi1_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4 core -> mcspi2 interface */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_mcspi2_hwmod, + .clk = "mcspi2_ick", + .addr = omap2_mcspi2_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4 core -> mcspi3 interface */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_mcspi3_hwmod, + .clk = "mcspi3_ick", + .addr = omap2430_mcspi3_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* IVA2 <- L3 interface */ +static struct omap_hwmod_ocp_if omap2430_l3__iva = { + .master = &omap2430_l3_main_hwmod, + .slave = &omap2430_iva_hwmod, + .clk = "dsp_fck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = { + { + .pa_start = 0x49018000, + .pa_end = 0x49018000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_wkup -> timer1 */ +static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = { + .master = &omap2430_l4_wkup_hwmod, + .slave = &omap2430_timer1_hwmod, + .clk = "gpt1_ick", + .addr = omap2430_timer1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> timer2 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_timer2_hwmod, + .clk = "gpt2_ick", + .addr = omap2xxx_timer2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> timer3 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_timer3_hwmod, + .clk = "gpt3_ick", + .addr = omap2xxx_timer3_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> timer4 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_timer4_hwmod, + .clk = "gpt4_ick", + .addr = omap2xxx_timer4_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> timer5 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_timer5_hwmod, + .clk = "gpt5_ick", + .addr = omap2xxx_timer5_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> timer6 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_timer6_hwmod, + .clk = "gpt6_ick", + .addr = omap2xxx_timer6_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> timer7 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_timer7_hwmod, + .clk = "gpt7_ick", + .addr = omap2xxx_timer7_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> timer8 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_timer8_hwmod, + .clk = "gpt8_ick", + .addr = omap2xxx_timer8_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> timer9 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_timer9_hwmod, + .clk = "gpt9_ick", + .addr = omap2xxx_timer9_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> timer10 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_timer10_hwmod, + .clk = "gpt10_ick", + .addr = omap2_timer10_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> timer11 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_timer11_hwmod, + .clk = "gpt11_ick", + .addr = omap2_timer11_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> timer12 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_timer12_hwmod, + .clk = "gpt12_ick", + .addr = omap2xxx_timer12_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> wd_timer2 */ +static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = { + { + .pa_start = 0x49016000, + .pa_end = 0x4901607f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = { + .master = &omap2430_l4_wkup_hwmod, + .slave = &omap2430_wd_timer2_hwmod, + .clk = "mpu_wdt_ick", + .addr = omap2430_wd_timer2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> dss */ +static struct omap_hwmod_ocp_if omap2430_l4_core__dss = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_dss_core_hwmod, + .clk = "dss_ick", + .addr = omap2_dss_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> dss_dispc */ +static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_dss_dispc_hwmod, + .clk = "dss_ick", + .addr = omap2_dss_dispc_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> dss_rfbi */ +static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_dss_rfbi_hwmod, + .clk = "dss_ick", + .addr = omap2_dss_rfbi_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> dss_venc */ +static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_dss_venc_hwmod, + .clk = "dss_ick", + .addr = omap2_dss_venc_addrs, + .flags = OCPIF_SWSUP_IDLE, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> gpio1 */ +static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = { + { + .pa_start = 0x4900C000, + .pa_end = 0x4900C1ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = { + .master = &omap2430_l4_wkup_hwmod, + .slave = &omap2430_gpio1_hwmod, + .clk = "gpios_ick", + .addr = omap2430_gpio1_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> gpio2 */ +static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = { + { + .pa_start = 0x4900E000, + .pa_end = 0x4900E1ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = { + .master = &omap2430_l4_wkup_hwmod, + .slave = &omap2430_gpio2_hwmod, + .clk = "gpios_ick", + .addr = omap2430_gpio2_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> gpio3 */ +static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = { + { + .pa_start = 0x49010000, + .pa_end = 0x490101ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = { + .master = &omap2430_l4_wkup_hwmod, + .slave = &omap2430_gpio3_hwmod, + .clk = "gpios_ick", + .addr = omap2430_gpio3_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> gpio4 */ +static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = { + { + .pa_start = 0x49012000, + .pa_end = 0x490121ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = { + .master = &omap2430_l4_wkup_hwmod, + .slave = &omap2430_gpio4_hwmod, + .clk = "gpios_ick", + .addr = omap2430_gpio4_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> gpio5 */ +static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = { + { + .pa_start = 0x480B6000, + .pa_end = 0x480B61ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_gpio5_hwmod, + .clk = "gpio5_ick", + .addr = omap2430_gpio5_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dma_system -> L3 */ +static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = { + .master = &omap2430_dma_system_hwmod, + .slave = &omap2430_l3_main_hwmod, + .clk = "core_l3_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> dma_system */ +static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_dma_system_hwmod, + .clk = "sdma_ick", + .addr = omap2_dma_system_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> mailbox */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_mailbox_hwmod, + .addr = omap2_mailbox_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> mcbsp1 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_mcbsp1_hwmod, + .clk = "mcbsp1_ick", + .addr = omap2_mcbsp1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> mcbsp2 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_mcbsp2_hwmod, + .clk = "mcbsp2_ick", + .addr = omap2xxx_mcbsp2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = { + { + .name = "mpu", + .pa_start = 0x4808C000, + .pa_end = 0x4808C0ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_core -> mcbsp3 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_mcbsp3_hwmod, + .clk = "mcbsp3_ick", + .addr = omap2430_mcbsp3_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = { + { + .name = "mpu", + .pa_start = 0x4808E000, + .pa_end = 0x4808E0ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_core -> mcbsp4 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_mcbsp4_hwmod, + .clk = "mcbsp4_ick", + .addr = omap2430_mcbsp4_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = { + { + .name = "mpu", + .pa_start = 0x48096000, + .pa_end = 0x480960ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_core -> mcbsp5 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_mcbsp5_hwmod, + .clk = "mcbsp5_ick", + .addr = omap2430_mcbsp5_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = { &omap2430_l3_main__l4_core, &omap2430_mpu__l3_main, diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index a3eeff733682..7fd34b377555 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -39,116 +39,23 @@ /* * OMAP3xxx hardware module integration data * - * ALl of the data in this section should be autogeneratable from the + * All of the data in this section should be autogeneratable from the * TI hardware database or other technical documentation. Data that * is driver-specific or driver-kernel integration-specific belongs * elsewhere. */ -static struct omap_hwmod omap3xxx_mpu_hwmod; -static struct omap_hwmod omap3xxx_iva_hwmod; -static struct omap_hwmod omap3xxx_l3_main_hwmod; -static struct omap_hwmod omap3xxx_l4_core_hwmod; -static struct omap_hwmod omap3xxx_l4_per_hwmod; -static struct omap_hwmod omap3xxx_wd_timer2_hwmod; -static struct omap_hwmod omap3430es1_dss_core_hwmod; -static struct omap_hwmod omap3xxx_dss_core_hwmod; -static struct omap_hwmod omap3xxx_dss_dispc_hwmod; -static struct omap_hwmod omap3xxx_dss_dsi1_hwmod; -static struct omap_hwmod omap3xxx_dss_rfbi_hwmod; -static struct omap_hwmod omap3xxx_dss_venc_hwmod; -static struct omap_hwmod omap3xxx_i2c1_hwmod; -static struct omap_hwmod omap3xxx_i2c2_hwmod; -static struct omap_hwmod omap3xxx_i2c3_hwmod; -static struct omap_hwmod omap3xxx_gpio1_hwmod; -static struct omap_hwmod omap3xxx_gpio2_hwmod; -static struct omap_hwmod omap3xxx_gpio3_hwmod; -static struct omap_hwmod omap3xxx_gpio4_hwmod; -static struct omap_hwmod omap3xxx_gpio5_hwmod; -static struct omap_hwmod omap3xxx_gpio6_hwmod; -static struct omap_hwmod omap34xx_sr1_hwmod; -static struct omap_hwmod omap34xx_sr2_hwmod; -static struct omap_hwmod omap34xx_mcspi1; -static struct omap_hwmod omap34xx_mcspi2; -static struct omap_hwmod omap34xx_mcspi3; -static struct omap_hwmod omap34xx_mcspi4; -static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod; -static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod; -static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod; -static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod; -static struct omap_hwmod omap3xxx_mmc3_hwmod; -static struct omap_hwmod am35xx_usbhsotg_hwmod; - -static struct omap_hwmod omap3xxx_dma_system_hwmod; - -static struct omap_hwmod omap3xxx_mcbsp1_hwmod; -static struct omap_hwmod omap3xxx_mcbsp2_hwmod; -static struct omap_hwmod omap3xxx_mcbsp3_hwmod; -static struct omap_hwmod omap3xxx_mcbsp4_hwmod; -static struct omap_hwmod omap3xxx_mcbsp5_hwmod; -static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod; -static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod; -static struct omap_hwmod omap3xxx_usb_host_hs_hwmod; -static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod; - -/* L3 -> L4_CORE interface */ -static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { - .master = &omap3xxx_l3_main_hwmod, - .slave = &omap3xxx_l4_core_hwmod, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L3 -> L4_PER interface */ -static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = { - .master = &omap3xxx_l3_main_hwmod, - .slave = &omap3xxx_l4_per_hwmod, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; +/* + * IP blocks + */ -/* L3 taret configuration and error log registers */ +/* L3 */ static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = { { .irq = INT_34XX_L3_DBG_IRQ }, { .irq = INT_34XX_L3_APP_IRQ }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = { - { - .pa_start = 0x68000000, - .pa_end = 0x6800ffff, - .flags = ADDR_TYPE_RT, - }, - { } -}; - -/* MPU -> L3 interface */ -static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = { - .master = &omap3xxx_mpu_hwmod, - .slave = &omap3xxx_l3_main_hwmod, - .addr = omap3xxx_l3_main_addrs, - .user = OCP_USER_MPU, -}; - -/* DSS -> l3 */ -static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = { - .master = &omap3430es1_dss_core_hwmod, - .slave = &omap3xxx_l3_main_hwmod, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = { - .master = &omap3xxx_dss_core_hwmod, - .slave = &omap3xxx_l3_main_hwmod, - .fw = { - .omap2 = { - .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS, - .flags = OMAP_FIREWALL_L3, - } - }, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L3 */ static struct omap_hwmod omap3xxx_l3_main_hwmod = { .name = "l3_main", .class = &l3_hwmod_class, @@ -156,2795 +63,2939 @@ static struct omap_hwmod omap3xxx_l3_main_hwmod = { .flags = HWMOD_NO_IDLEST, }; -static struct omap_hwmod omap3xxx_l4_wkup_hwmod; -static struct omap_hwmod omap3xxx_l4_sec_hwmod; -static struct omap_hwmod omap3xxx_uart1_hwmod; -static struct omap_hwmod omap3xxx_uart2_hwmod; -static struct omap_hwmod omap3xxx_uart3_hwmod; -static struct omap_hwmod omap36xx_uart4_hwmod; -static struct omap_hwmod am35xx_uart4_hwmod; -static struct omap_hwmod omap3xxx_usbhsotg_hwmod; - -/* l3_core -> usbhsotg interface */ -static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = { - .master = &omap3xxx_usbhsotg_hwmod, - .slave = &omap3xxx_l3_main_hwmod, - .clk = "core_l3_ick", - .user = OCP_USER_MPU, +/* L4 CORE */ +static struct omap_hwmod omap3xxx_l4_core_hwmod = { + .name = "l4_core", + .class = &l4_hwmod_class, + .flags = HWMOD_NO_IDLEST, }; -/* l3_core -> am35xx_usbhsotg interface */ -static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = { - .master = &am35xx_usbhsotg_hwmod, - .slave = &omap3xxx_l3_main_hwmod, - .clk = "core_l3_ick", - .user = OCP_USER_MPU, +/* L4 PER */ +static struct omap_hwmod omap3xxx_l4_per_hwmod = { + .name = "l4_per", + .class = &l4_hwmod_class, + .flags = HWMOD_NO_IDLEST, }; -/* L4_CORE -> L4_WKUP interface */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_l4_wkup_hwmod, - .user = OCP_USER_MPU | OCP_USER_SDMA, + +/* L4 WKUP */ +static struct omap_hwmod omap3xxx_l4_wkup_hwmod = { + .name = "l4_wkup", + .class = &l4_hwmod_class, + .flags = HWMOD_NO_IDLEST, }; -/* L4 CORE -> MMC1 interface */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_pre_es3_mmc1_hwmod, - .clk = "mmchs1_ick", - .addr = omap2430_mmc1_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, - .flags = OMAP_FIREWALL_L4 +/* L4 SEC */ +static struct omap_hwmod omap3xxx_l4_sec_hwmod = { + .name = "l4_sec", + .class = &l4_hwmod_class, + .flags = HWMOD_NO_IDLEST, }; -static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_es3plus_mmc1_hwmod, - .clk = "mmchs1_ick", - .addr = omap2430_mmc1_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, - .flags = OMAP_FIREWALL_L4 +/* MPU */ +static struct omap_hwmod omap3xxx_mpu_hwmod = { + .name = "mpu", + .class = &mpu_hwmod_class, + .main_clk = "arm_fck", }; -/* L4 CORE -> MMC2 interface */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_pre_es3_mmc2_hwmod, - .clk = "mmchs2_ick", - .addr = omap2430_mmc2_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, - .flags = OMAP_FIREWALL_L4 +/* IVA2 (IVA2) */ +static struct omap_hwmod omap3xxx_iva_hwmod = { + .name = "iva", + .class = &iva_hwmod_class, }; -static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_es3plus_mmc2_hwmod, - .clk = "mmchs2_ick", - .addr = omap2430_mmc2_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, - .flags = OMAP_FIREWALL_L4 +/* timer class */ +static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, }; -/* L4 CORE -> MMC3 interface */ -static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = { - { - .pa_start = 0x480ad000, - .pa_end = 0x480ad1ff, - .flags = ADDR_TYPE_RT, - }, - { } +static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = { + .name = "timer", + .sysc = &omap3xxx_timer_1ms_sysc, + .rev = OMAP_TIMER_IP_VERSION_1, }; -static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_mmc3_hwmod, - .clk = "mmchs3_ick", - .addr = omap3xxx_mmc3_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, - .flags = OMAP_FIREWALL_L4 +static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, }; -/* L4 CORE -> UART1 interface */ -static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = { - { - .pa_start = OMAP3_UART1_BASE, - .pa_end = OMAP3_UART1_BASE + SZ_8K - 1, - .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, - }, - { } +static struct omap_hwmod_class omap3xxx_timer_hwmod_class = { + .name = "timer", + .sysc = &omap3xxx_timer_sysc, + .rev = OMAP_TIMER_IP_VERSION_1, }; -static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_uart1_hwmod, - .clk = "uart1_ick", - .addr = omap3xxx_uart1_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, +/* secure timers dev attribute */ +static struct omap_timer_capability_dev_attr capability_secure_dev_attr = { + .timer_capability = OMAP_TIMER_SECURE, }; -/* L4 CORE -> UART2 interface */ -static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = { - { - .pa_start = OMAP3_UART2_BASE, - .pa_end = OMAP3_UART2_BASE + SZ_1K - 1, - .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, - }, - { } +/* always-on timers dev attribute */ +static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { + .timer_capability = OMAP_TIMER_ALWON, }; -static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_uart2_hwmod, - .clk = "uart2_ick", - .addr = omap3xxx_uart2_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, +/* pwm timers dev attribute */ +static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { + .timer_capability = OMAP_TIMER_HAS_PWM, }; -/* L4 PER -> UART3 interface */ -static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = { - { - .pa_start = OMAP3_UART3_BASE, - .pa_end = OMAP3_UART3_BASE + SZ_1K - 1, - .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, +/* timer1 */ +static struct omap_hwmod omap3xxx_timer1_hwmod = { + .name = "timer1", + .mpu_irqs = omap2_timer1_mpu_irqs, + .main_clk = "gpt1_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPT1_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT, + }, }, - { } + .dev_attr = &capability_alwon_dev_attr, + .class = &omap3xxx_timer_1ms_hwmod_class, }; -static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_uart3_hwmod, - .clk = "uart3_ick", - .addr = omap3xxx_uart3_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, +/* timer2 */ +static struct omap_hwmod omap3xxx_timer2_hwmod = { + .name = "timer2", + .mpu_irqs = omap2_timer2_mpu_irqs, + .main_clk = "gpt2_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPT2_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT, + }, + }, + .dev_attr = &capability_alwon_dev_attr, + .class = &omap3xxx_timer_1ms_hwmod_class, }; -/* L4 PER -> UART4 interface */ -static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = { - { - .pa_start = OMAP3_UART4_BASE, - .pa_end = OMAP3_UART4_BASE + SZ_1K - 1, - .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, - }, - { } +/* timer3 */ +static struct omap_hwmod omap3xxx_timer3_hwmod = { + .name = "timer3", + .mpu_irqs = omap2_timer3_mpu_irqs, + .main_clk = "gpt3_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPT3_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT, + }, + }, + .dev_attr = &capability_alwon_dev_attr, + .class = &omap3xxx_timer_hwmod_class, }; -static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap36xx_uart4_hwmod, - .clk = "uart4_ick", - .addr = omap36xx_uart4_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, +/* timer4 */ +static struct omap_hwmod omap3xxx_timer4_hwmod = { + .name = "timer4", + .mpu_irqs = omap2_timer4_mpu_irqs, + .main_clk = "gpt4_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPT4_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT, + }, + }, + .dev_attr = &capability_alwon_dev_attr, + .class = &omap3xxx_timer_hwmod_class, }; -/* AM35xx: L4 CORE -> UART4 interface */ -static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = { - { - .pa_start = OMAP3_UART4_AM35XX_BASE, - .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1, - .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, +/* timer5 */ +static struct omap_hwmod omap3xxx_timer5_hwmod = { + .name = "timer5", + .mpu_irqs = omap2_timer5_mpu_irqs, + .main_clk = "gpt5_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPT5_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT, + }, }, + .dev_attr = &capability_alwon_dev_attr, + .class = &omap3xxx_timer_hwmod_class, }; -static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &am35xx_uart4_hwmod, - .clk = "uart4_ick", - .addr = am35xx_uart4_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, +/* timer6 */ +static struct omap_hwmod omap3xxx_timer6_hwmod = { + .name = "timer6", + .mpu_irqs = omap2_timer6_mpu_irqs, + .main_clk = "gpt6_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPT6_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT, + }, + }, + .dev_attr = &capability_alwon_dev_attr, + .class = &omap3xxx_timer_hwmod_class, }; -/* L4 CORE -> I2C1 interface */ -static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_i2c1_hwmod, - .clk = "i2c1_ick", - .addr = omap2_i2c1_addr_space, - .fw = { +/* timer7 */ +static struct omap_hwmod omap3xxx_timer7_hwmod = { + .name = "timer7", + .mpu_irqs = omap2_timer7_mpu_irqs, + .main_clk = "gpt7_fck", + .prcm = { .omap2 = { - .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION, - .l4_prot_group = 7, - .flags = OMAP_FIREWALL_L4, - } + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPT7_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT, + }, }, - .user = OCP_USER_MPU | OCP_USER_SDMA, + .dev_attr = &capability_alwon_dev_attr, + .class = &omap3xxx_timer_hwmod_class, }; -/* L4 CORE -> I2C2 interface */ -static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_i2c2_hwmod, - .clk = "i2c2_ick", - .addr = omap2_i2c2_addr_space, - .fw = { +/* timer8 */ +static struct omap_hwmod omap3xxx_timer8_hwmod = { + .name = "timer8", + .mpu_irqs = omap2_timer8_mpu_irqs, + .main_clk = "gpt8_fck", + .prcm = { .omap2 = { - .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION, - .l4_prot_group = 7, - .flags = OMAP_FIREWALL_L4, - } + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPT8_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT, + }, }, - .user = OCP_USER_MPU | OCP_USER_SDMA, + .dev_attr = &capability_pwm_dev_attr, + .class = &omap3xxx_timer_hwmod_class, }; -/* L4 CORE -> I2C3 interface */ -static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = { - { - .pa_start = 0x48060000, - .pa_end = 0x48060000 + SZ_128 - 1, - .flags = ADDR_TYPE_RT, +/* timer9 */ +static struct omap_hwmod omap3xxx_timer9_hwmod = { + .name = "timer9", + .mpu_irqs = omap2_timer9_mpu_irqs, + .main_clk = "gpt9_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPT9_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT, + }, }, - { } + .dev_attr = &capability_pwm_dev_attr, + .class = &omap3xxx_timer_hwmod_class, }; -static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_i2c3_hwmod, - .clk = "i2c3_ick", - .addr = omap3xxx_i2c3_addr_space, - .fw = { +/* timer10 */ +static struct omap_hwmod omap3xxx_timer10_hwmod = { + .name = "timer10", + .mpu_irqs = omap2_timer10_mpu_irqs, + .main_clk = "gpt10_fck", + .prcm = { .omap2 = { - .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION, - .l4_prot_group = 7, - .flags = OMAP_FIREWALL_L4, - } + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPT10_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT, + }, }, - .user = OCP_USER_MPU | OCP_USER_SDMA, + .dev_attr = &capability_pwm_dev_attr, + .class = &omap3xxx_timer_1ms_hwmod_class, }; -static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = { - { .irq = 18}, - { .irq = -1 } +/* timer11 */ +static struct omap_hwmod omap3xxx_timer11_hwmod = { + .name = "timer11", + .mpu_irqs = omap2_timer11_mpu_irqs, + .main_clk = "gpt11_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPT11_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT, + }, + }, + .dev_attr = &capability_pwm_dev_attr, + .class = &omap3xxx_timer_hwmod_class, }; -static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = { - { .irq = 19}, +/* timer12 */ +static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = { + { .irq = 95, }, { .irq = -1 } }; -/* L4 CORE -> SR1 interface */ -static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = { - { - .pa_start = OMAP34XX_SR1_BASE, - .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1, - .flags = ADDR_TYPE_RT, +static struct omap_hwmod omap3xxx_timer12_hwmod = { + .name = "timer12", + .mpu_irqs = omap3xxx_timer12_mpu_irqs, + .main_clk = "gpt12_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPT12_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT, + }, }, - { } + .dev_attr = &capability_secure_dev_attr, + .class = &omap3xxx_timer_hwmod_class, }; -static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap34xx_sr1_hwmod, - .clk = "sr_l4_ick", - .addr = omap3_sr1_addr_space, - .user = OCP_USER_MPU, +/* + * 'wd_timer' class + * 32-bit watchdog upward counter that generates a pulse on the reset pin on + * overflow condition + */ + +static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | + SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, }; -/* L4 CORE -> SR1 interface */ -static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = { - { - .pa_start = OMAP34XX_SR2_BASE, - .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1, - .flags = ADDR_TYPE_RT, - }, - { } +/* I2C common */ +static struct omap_hwmod_class_sysconfig i2c_sysc = { + .rev_offs = 0x00, + .sysc_offs = 0x20, + .syss_offs = 0x10, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .clockact = CLOCKACT_TEST_ICLK, + .sysc_fields = &omap_hwmod_sysc_type1, }; -static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap34xx_sr2_hwmod, - .clk = "sr_l4_ick", - .addr = omap3_sr2_addr_space, - .user = OCP_USER_MPU, +static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = { + .name = "wd_timer", + .sysc = &omap3xxx_wd_timer_sysc, + .pre_shutdown = &omap2_wd_timer_disable }; -/* -* usbhsotg interface data -*/ +static struct omap_hwmod omap3xxx_wd_timer2_hwmod = { + .name = "wd_timer2", + .class = &omap3xxx_wd_timer_hwmod_class, + .main_clk = "wdt2_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_WDT2_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT, + }, + }, + /* + * XXX: Use software supervised mode, HW supervised smartidle seems to + * block CORE power domain idle transitions. Maybe a HW bug in wdt2? + */ + .flags = HWMOD_SWSUP_SIDLE, +}; -static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = { - { - .pa_start = OMAP34XX_HSUSB_OTG_BASE, - .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1, - .flags = ADDR_TYPE_RT +/* UART1 */ +static struct omap_hwmod omap3xxx_uart1_hwmod = { + .name = "uart1", + .mpu_irqs = omap2_uart1_mpu_irqs, + .sdma_reqs = omap2_uart1_sdma_reqs, + .main_clk = "uart1_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_UART1_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT, + }, }, - { } + .class = &omap2_uart_class, }; -/* l4_core -> usbhsotg */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_usbhsotg_hwmod, - .clk = "l4_ick", - .addr = omap3xxx_usbhsotg_addrs, - .user = OCP_USER_MPU, +/* UART2 */ +static struct omap_hwmod omap3xxx_uart2_hwmod = { + .name = "uart2", + .mpu_irqs = omap2_uart2_mpu_irqs, + .sdma_reqs = omap2_uart2_sdma_reqs, + .main_clk = "uart2_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_UART2_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT, + }, + }, + .class = &omap2_uart_class, }; -static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = { - { - .pa_start = AM35XX_IPSS_USBOTGSS_BASE, - .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1, - .flags = ADDR_TYPE_RT +/* UART3 */ +static struct omap_hwmod omap3xxx_uart3_hwmod = { + .name = "uart3", + .mpu_irqs = omap2_uart3_mpu_irqs, + .sdma_reqs = omap2_uart3_sdma_reqs, + .main_clk = "uart3_fck", + .prcm = { + .omap2 = { + .module_offs = OMAP3430_PER_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_UART3_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT, + }, }, - { } + .class = &omap2_uart_class, }; -/* l4_core -> usbhsotg */ -static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &am35xx_usbhsotg_hwmod, - .clk = "l4_ick", - .addr = am35xx_usbhsotg_addrs, - .user = OCP_USER_MPU, +/* UART4 */ +static struct omap_hwmod_irq_info uart4_mpu_irqs[] = { + { .irq = INT_36XX_UART4_IRQ, }, + { .irq = -1 } }; -/* L4 CORE */ -static struct omap_hwmod omap3xxx_l4_core_hwmod = { - .name = "l4_core", - .class = &l4_hwmod_class, - .flags = HWMOD_NO_IDLEST, +static struct omap_hwmod_dma_info uart4_sdma_reqs[] = { + { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, }, + { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, }, + { .dma_req = -1 } }; -/* L4 PER */ -static struct omap_hwmod omap3xxx_l4_per_hwmod = { - .name = "l4_per", - .class = &l4_hwmod_class, - .flags = HWMOD_NO_IDLEST, +static struct omap_hwmod omap36xx_uart4_hwmod = { + .name = "uart4", + .mpu_irqs = uart4_mpu_irqs, + .sdma_reqs = uart4_sdma_reqs, + .main_clk = "uart4_fck", + .prcm = { + .omap2 = { + .module_offs = OMAP3430_PER_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3630_EN_UART4_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT, + }, + }, + .class = &omap2_uart_class, }; -/* L4_WKUP -> L4_SEC interface */ -static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = { - .master = &omap3xxx_l4_wkup_hwmod, - .slave = &omap3xxx_l4_sec_hwmod, - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = { + { .irq = INT_35XX_UART4_IRQ, }, }; -/* L4 WKUP */ -static struct omap_hwmod omap3xxx_l4_wkup_hwmod = { - .name = "l4_wkup", - .class = &l4_hwmod_class, - .flags = HWMOD_NO_IDLEST, +static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = { + { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, }, + { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, }, }; -/* L4 SEC */ -static struct omap_hwmod omap3xxx_l4_sec_hwmod = { - .name = "l4_sec", - .class = &l4_hwmod_class, - .flags = HWMOD_NO_IDLEST, +static struct omap_hwmod am35xx_uart4_hwmod = { + .name = "uart4", + .mpu_irqs = am35xx_uart4_mpu_irqs, + .sdma_reqs = am35xx_uart4_sdma_reqs, + .main_clk = "uart4_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_UART4_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_EN_UART4_SHIFT, + }, + }, + .class = &omap2_uart_class, +}; + +static struct omap_hwmod_class i2c_class = { + .name = "i2c", + .sysc = &i2c_sysc, + .rev = OMAP_I2C_IP_VERSION_1, + .reset = &omap_i2c_reset, +}; + +static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = { + { .name = "dispc", .dma_req = 5 }, + { .name = "dsi1", .dma_req = 74 }, + { .dma_req = -1 } }; -/* MPU */ -static struct omap_hwmod omap3xxx_mpu_hwmod = { - .name = "mpu", - .class = &mpu_hwmod_class, - .main_clk = "arm_fck", +/* dss */ +static struct omap_hwmod_opt_clk dss_opt_clks[] = { + /* + * The DSS HW needs all DSS clocks enabled during reset. The dss_core + * driver does not use these clocks. + */ + { .role = "sys_clk", .clk = "dss2_alwon_fck" }, + { .role = "tv_clk", .clk = "dss_tv_fck" }, + /* required only on OMAP3430 */ + { .role = "tv_dac_clk", .clk = "dss_96m_fck" }, }; -/* - * IVA2_2 interface data - */ +static struct omap_hwmod omap3430es1_dss_core_hwmod = { + .name = "dss_core", + .class = &omap2_dss_hwmod_class, + .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ + .sdma_reqs = omap3xxx_dss_sdma_chs, + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_DSS1_SHIFT, + .module_offs = OMAP3430_DSS_MOD, + .idlest_reg_id = 1, + .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT, + }, + }, + .opt_clks = dss_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), + .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET, +}; -/* IVA2 <- L3 interface */ -static struct omap_hwmod_ocp_if omap3xxx_l3__iva = { - .master = &omap3xxx_l3_main_hwmod, - .slave = &omap3xxx_iva_hwmod, - .clk = "iva2_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap_hwmod omap3xxx_dss_core_hwmod = { + .name = "dss_core", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .class = &omap2_dss_hwmod_class, + .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ + .sdma_reqs = omap3xxx_dss_sdma_chs, + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_DSS1_SHIFT, + .module_offs = OMAP3430_DSS_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT, + .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT, + }, + }, + .opt_clks = dss_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), }; /* - * IVA2 (IVA2) + * 'dispc' class + * display controller */ -static struct omap_hwmod omap3xxx_iva_hwmod = { - .name = "iva", - .class = &iva_hwmod_class, -}; - -/* timer class */ -static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = { +static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = { .rev_offs = 0x0000, .sysc_offs = 0x0010, .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | - SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | - SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | + SYSC_HAS_ENAWAKEUP), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), .sysc_fields = &omap_hwmod_sysc_type1, }; -static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = { - .name = "timer", - .sysc = &omap3xxx_timer_1ms_sysc, - .rev = OMAP_TIMER_IP_VERSION_1, +static struct omap_hwmod_class omap3_dispc_hwmod_class = { + .name = "dispc", + .sysc = &omap3_dispc_sysc, }; -static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | - SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, +static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { + .name = "dss_dispc", + .class = &omap3_dispc_hwmod_class, + .mpu_irqs = omap2_dispc_irqs, + .main_clk = "dss1_alwon_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_DSS1_SHIFT, + .module_offs = OMAP3430_DSS_MOD, + }, + }, + .flags = HWMOD_NO_IDLEST, + .dev_attr = &omap2_3_dss_dispc_dev_attr }; -static struct omap_hwmod_class omap3xxx_timer_hwmod_class = { - .name = "timer", - .sysc = &omap3xxx_timer_sysc, - .rev = OMAP_TIMER_IP_VERSION_1, -}; +/* + * 'dsi' class + * display serial interface controller + */ -/* secure timers dev attribute */ -static struct omap_timer_capability_dev_attr capability_secure_dev_attr = { - .timer_capability = OMAP_TIMER_SECURE, +static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = { + .name = "dsi", }; -/* always-on timers dev attribute */ -static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { - .timer_capability = OMAP_TIMER_ALWON, +static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = { + { .irq = 25 }, + { .irq = -1 } }; -/* pwm timers dev attribute */ -static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { - .timer_capability = OMAP_TIMER_HAS_PWM, +/* dss_dsi1 */ +static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { + { .role = "sys_clk", .clk = "dss2_alwon_fck" }, }; -/* timer1 */ -static struct omap_hwmod omap3xxx_timer1_hwmod; - -static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = { - { - .pa_start = 0x48318000, - .pa_end = 0x48318000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT +static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = { + .name = "dss_dsi1", + .class = &omap3xxx_dsi_hwmod_class, + .mpu_irqs = omap3xxx_dsi1_irqs, + .main_clk = "dss1_alwon_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_DSS1_SHIFT, + .module_offs = OMAP3430_DSS_MOD, + }, }, - { } + .opt_clks = dss_dsi1_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), + .flags = HWMOD_NO_IDLEST, }; -/* l4_wkup -> timer1 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = { - .master = &omap3xxx_l4_wkup_hwmod, - .slave = &omap3xxx_timer1_hwmod, - .clk = "gpt1_ick", - .addr = omap3xxx_timer1_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { + { .role = "ick", .clk = "dss_ick" }, }; -/* timer1 hwmod */ -static struct omap_hwmod omap3xxx_timer1_hwmod = { - .name = "timer1", - .mpu_irqs = omap2_timer1_mpu_irqs, - .main_clk = "gpt1_fck", +static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = { + .name = "dss_rfbi", + .class = &omap2_rfbi_hwmod_class, + .main_clk = "dss1_alwon_fck", .prcm = { .omap2 = { .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPT1_SHIFT, - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT, + .module_bit = OMAP3430_EN_DSS1_SHIFT, + .module_offs = OMAP3430_DSS_MOD, }, }, - .dev_attr = &capability_alwon_dev_attr, - .class = &omap3xxx_timer_1ms_hwmod_class, -}; - -/* timer2 */ -static struct omap_hwmod omap3xxx_timer2_hwmod; - -static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = { - { - .pa_start = 0x49032000, - .pa_end = 0x49032000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } + .opt_clks = dss_rfbi_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), + .flags = HWMOD_NO_IDLEST, }; -/* l4_per -> timer2 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_timer2_hwmod, - .clk = "gpt2_ick", - .addr = omap3xxx_timer2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = { + /* required only on OMAP3430 */ + { .role = "tv_dac_clk", .clk = "dss_96m_fck" }, }; -/* timer2 hwmod */ -static struct omap_hwmod omap3xxx_timer2_hwmod = { - .name = "timer2", - .mpu_irqs = omap2_timer2_mpu_irqs, - .main_clk = "gpt2_fck", +static struct omap_hwmod omap3xxx_dss_venc_hwmod = { + .name = "dss_venc", + .class = &omap2_venc_hwmod_class, + .main_clk = "dss_tv_fck", .prcm = { .omap2 = { .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPT2_SHIFT, - .module_offs = OMAP3430_PER_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT, + .module_bit = OMAP3430_EN_DSS1_SHIFT, + .module_offs = OMAP3430_DSS_MOD, }, }, - .dev_attr = &capability_alwon_dev_attr, - .class = &omap3xxx_timer_1ms_hwmod_class, -}; - -/* timer3 */ -static struct omap_hwmod omap3xxx_timer3_hwmod; - -static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = { - { - .pa_start = 0x49034000, - .pa_end = 0x49034000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } + .opt_clks = dss_venc_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks), + .flags = HWMOD_NO_IDLEST, }; -/* l4_per -> timer3 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_timer3_hwmod, - .clk = "gpt3_ick", - .addr = omap3xxx_timer3_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, +/* I2C1 */ +static struct omap_i2c_dev_attr i2c1_dev_attr = { + .fifo_depth = 8, /* bytes */ + .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | + OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | + OMAP_I2C_FLAG_BUS_SHIFT_2, }; -/* timer3 hwmod */ -static struct omap_hwmod omap3xxx_timer3_hwmod = { - .name = "timer3", - .mpu_irqs = omap2_timer3_mpu_irqs, - .main_clk = "gpt3_fck", +static struct omap_hwmod omap3xxx_i2c1_hwmod = { + .name = "i2c1", + .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, + .mpu_irqs = omap2_i2c1_mpu_irqs, + .sdma_reqs = omap2_i2c1_sdma_reqs, + .main_clk = "i2c1_fck", .prcm = { .omap2 = { + .module_offs = CORE_MOD, .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPT3_SHIFT, - .module_offs = OMAP3430_PER_MOD, + .module_bit = OMAP3430_EN_I2C1_SHIFT, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT, + .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT, }, }, - .dev_attr = &capability_alwon_dev_attr, - .class = &omap3xxx_timer_hwmod_class, -}; - -/* timer4 */ -static struct omap_hwmod omap3xxx_timer4_hwmod; - -static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = { - { - .pa_start = 0x49036000, - .pa_end = 0x49036000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } + .class = &i2c_class, + .dev_attr = &i2c1_dev_attr, }; -/* l4_per -> timer4 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_timer4_hwmod, - .clk = "gpt4_ick", - .addr = omap3xxx_timer4_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, +/* I2C2 */ +static struct omap_i2c_dev_attr i2c2_dev_attr = { + .fifo_depth = 8, /* bytes */ + .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | + OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | + OMAP_I2C_FLAG_BUS_SHIFT_2, }; -/* timer4 hwmod */ -static struct omap_hwmod omap3xxx_timer4_hwmod = { - .name = "timer4", - .mpu_irqs = omap2_timer4_mpu_irqs, - .main_clk = "gpt4_fck", +static struct omap_hwmod omap3xxx_i2c2_hwmod = { + .name = "i2c2", + .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, + .mpu_irqs = omap2_i2c2_mpu_irqs, + .sdma_reqs = omap2_i2c2_sdma_reqs, + .main_clk = "i2c2_fck", .prcm = { .omap2 = { + .module_offs = CORE_MOD, .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPT4_SHIFT, - .module_offs = OMAP3430_PER_MOD, + .module_bit = OMAP3430_EN_I2C2_SHIFT, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT, + .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT, }, }, - .dev_attr = &capability_alwon_dev_attr, - .class = &omap3xxx_timer_hwmod_class, + .class = &i2c_class, + .dev_attr = &i2c2_dev_attr, }; -/* timer5 */ -static struct omap_hwmod omap3xxx_timer5_hwmod; +/* I2C3 */ +static struct omap_i2c_dev_attr i2c3_dev_attr = { + .fifo_depth = 64, /* bytes */ + .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | + OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | + OMAP_I2C_FLAG_BUS_SHIFT_2, +}; -static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = { - { - .pa_start = 0x49038000, - .pa_end = 0x49038000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } +static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = { + { .irq = INT_34XX_I2C3_IRQ, }, + { .irq = -1 } }; -/* l4_per -> timer5 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_timer5_hwmod, - .clk = "gpt5_ick", - .addr = omap3xxx_timer5_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = { + { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX }, + { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX }, + { .dma_req = -1 } }; -/* timer5 hwmod */ -static struct omap_hwmod omap3xxx_timer5_hwmod = { - .name = "timer5", - .mpu_irqs = omap2_timer5_mpu_irqs, - .main_clk = "gpt5_fck", +static struct omap_hwmod omap3xxx_i2c3_hwmod = { + .name = "i2c3", + .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, + .mpu_irqs = i2c3_mpu_irqs, + .sdma_reqs = i2c3_sdma_reqs, + .main_clk = "i2c3_fck", .prcm = { .omap2 = { + .module_offs = CORE_MOD, .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPT5_SHIFT, - .module_offs = OMAP3430_PER_MOD, + .module_bit = OMAP3430_EN_I2C3_SHIFT, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT, + .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT, }, }, - .dev_attr = &capability_alwon_dev_attr, - .class = &omap3xxx_timer_hwmod_class, + .class = &i2c_class, + .dev_attr = &i2c3_dev_attr, }; -/* timer6 */ -static struct omap_hwmod omap3xxx_timer6_hwmod; +/* + * 'gpio' class + * general purpose io module + */ -static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = { - { - .pa_start = 0x4903A000, - .pa_end = 0x4903A000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } +static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | + SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, }; -/* l4_per -> timer6 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_timer6_hwmod, - .clk = "gpt6_ick", - .addr = omap3xxx_timer6_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = { + .name = "gpio", + .sysc = &omap3xxx_gpio_sysc, + .rev = 1, }; -/* timer6 hwmod */ -static struct omap_hwmod omap3xxx_timer6_hwmod = { - .name = "timer6", - .mpu_irqs = omap2_timer6_mpu_irqs, - .main_clk = "gpt6_fck", +/* gpio_dev_attr */ +static struct omap_gpio_dev_attr gpio_dev_attr = { + .bank_width = 32, + .dbck_flag = true, +}; + +/* gpio1 */ +static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { + { .role = "dbclk", .clk = "gpio1_dbck", }, +}; + +static struct omap_hwmod omap3xxx_gpio1_hwmod = { + .name = "gpio1", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .mpu_irqs = omap2_gpio1_irqs, + .main_clk = "gpio1_ick", + .opt_clks = gpio1_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), .prcm = { .omap2 = { .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPT6_SHIFT, - .module_offs = OMAP3430_PER_MOD, + .module_bit = OMAP3430_EN_GPIO1_SHIFT, + .module_offs = WKUP_MOD, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT, + .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT, }, }, - .dev_attr = &capability_alwon_dev_attr, - .class = &omap3xxx_timer_hwmod_class, -}; - -/* timer7 */ -static struct omap_hwmod omap3xxx_timer7_hwmod; - -static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = { - { - .pa_start = 0x4903C000, - .pa_end = 0x4903C000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } + .class = &omap3xxx_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, }; -/* l4_per -> timer7 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_timer7_hwmod, - .clk = "gpt7_ick", - .addr = omap3xxx_timer7_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, +/* gpio2 */ +static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { + { .role = "dbclk", .clk = "gpio2_dbck", }, }; -/* timer7 hwmod */ -static struct omap_hwmod omap3xxx_timer7_hwmod = { - .name = "timer7", - .mpu_irqs = omap2_timer7_mpu_irqs, - .main_clk = "gpt7_fck", +static struct omap_hwmod omap3xxx_gpio2_hwmod = { + .name = "gpio2", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .mpu_irqs = omap2_gpio2_irqs, + .main_clk = "gpio2_ick", + .opt_clks = gpio2_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), .prcm = { .omap2 = { .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPT7_SHIFT, + .module_bit = OMAP3430_EN_GPIO2_SHIFT, .module_offs = OMAP3430_PER_MOD, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT, + .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT, }, }, - .dev_attr = &capability_alwon_dev_attr, - .class = &omap3xxx_timer_hwmod_class, -}; - -/* timer8 */ -static struct omap_hwmod omap3xxx_timer8_hwmod; - -static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = { - { - .pa_start = 0x4903E000, - .pa_end = 0x4903E000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } + .class = &omap3xxx_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, }; -/* l4_per -> timer8 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_timer8_hwmod, - .clk = "gpt8_ick", - .addr = omap3xxx_timer8_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, +/* gpio3 */ +static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { + { .role = "dbclk", .clk = "gpio3_dbck", }, }; -/* timer8 hwmod */ -static struct omap_hwmod omap3xxx_timer8_hwmod = { - .name = "timer8", - .mpu_irqs = omap2_timer8_mpu_irqs, - .main_clk = "gpt8_fck", +static struct omap_hwmod omap3xxx_gpio3_hwmod = { + .name = "gpio3", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .mpu_irqs = omap2_gpio3_irqs, + .main_clk = "gpio3_ick", + .opt_clks = gpio3_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), .prcm = { .omap2 = { .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPT8_SHIFT, + .module_bit = OMAP3430_EN_GPIO3_SHIFT, .module_offs = OMAP3430_PER_MOD, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT, + .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT, }, }, - .dev_attr = &capability_pwm_dev_attr, - .class = &omap3xxx_timer_hwmod_class, -}; - -/* timer9 */ -static struct omap_hwmod omap3xxx_timer9_hwmod; - -static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = { - { - .pa_start = 0x49040000, - .pa_end = 0x49040000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } + .class = &omap3xxx_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, }; -/* l4_per -> timer9 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_timer9_hwmod, - .clk = "gpt9_ick", - .addr = omap3xxx_timer9_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, +/* gpio4 */ +static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { + { .role = "dbclk", .clk = "gpio4_dbck", }, }; -/* timer9 hwmod */ -static struct omap_hwmod omap3xxx_timer9_hwmod = { - .name = "timer9", - .mpu_irqs = omap2_timer9_mpu_irqs, - .main_clk = "gpt9_fck", +static struct omap_hwmod omap3xxx_gpio4_hwmod = { + .name = "gpio4", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .mpu_irqs = omap2_gpio4_irqs, + .main_clk = "gpio4_ick", + .opt_clks = gpio4_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), .prcm = { .omap2 = { .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPT9_SHIFT, + .module_bit = OMAP3430_EN_GPIO4_SHIFT, .module_offs = OMAP3430_PER_MOD, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT, + .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT, }, }, - .dev_attr = &capability_pwm_dev_attr, - .class = &omap3xxx_timer_hwmod_class, + .class = &omap3xxx_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, }; -/* timer10 */ -static struct omap_hwmod omap3xxx_timer10_hwmod; +/* gpio5 */ +static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = { + { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */ + { .irq = -1 } +}; -/* l4_core -> timer10 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_timer10_hwmod, - .clk = "gpt10_ick", - .addr = omap2_timer10_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { + { .role = "dbclk", .clk = "gpio5_dbck", }, }; -/* timer10 hwmod */ -static struct omap_hwmod omap3xxx_timer10_hwmod = { - .name = "timer10", - .mpu_irqs = omap2_timer10_mpu_irqs, - .main_clk = "gpt10_fck", +static struct omap_hwmod omap3xxx_gpio5_hwmod = { + .name = "gpio5", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .mpu_irqs = omap3xxx_gpio5_irqs, + .main_clk = "gpio5_ick", + .opt_clks = gpio5_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), .prcm = { .omap2 = { .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPT10_SHIFT, - .module_offs = CORE_MOD, + .module_bit = OMAP3430_EN_GPIO5_SHIFT, + .module_offs = OMAP3430_PER_MOD, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT, + .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT, }, }, - .dev_attr = &capability_pwm_dev_attr, - .class = &omap3xxx_timer_1ms_hwmod_class, + .class = &omap3xxx_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, }; -/* timer11 */ -static struct omap_hwmod omap3xxx_timer11_hwmod; +/* gpio6 */ +static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = { + { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */ + { .irq = -1 } +}; -/* l4_core -> timer11 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_timer11_hwmod, - .clk = "gpt11_ick", - .addr = omap2_timer11_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { + { .role = "dbclk", .clk = "gpio6_dbck", }, }; -/* timer11 hwmod */ -static struct omap_hwmod omap3xxx_timer11_hwmod = { - .name = "timer11", - .mpu_irqs = omap2_timer11_mpu_irqs, - .main_clk = "gpt11_fck", +static struct omap_hwmod omap3xxx_gpio6_hwmod = { + .name = "gpio6", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .mpu_irqs = omap3xxx_gpio6_irqs, + .main_clk = "gpio6_ick", + .opt_clks = gpio6_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), .prcm = { .omap2 = { .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPT11_SHIFT, - .module_offs = CORE_MOD, + .module_bit = OMAP3430_EN_GPIO6_SHIFT, + .module_offs = OMAP3430_PER_MOD, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT, + .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT, }, }, - .dev_attr = &capability_pwm_dev_attr, - .class = &omap3xxx_timer_hwmod_class, + .class = &omap3xxx_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, }; -/* timer12 */ -static struct omap_hwmod omap3xxx_timer12_hwmod; -static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = { - { .irq = 95, }, - { .irq = -1 } +/* dma attributes */ +static struct omap_dma_dev_attr dma_dev_attr = { + .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | + IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, + .lch_count = 32, }; -static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = { - { - .pa_start = 0x48304000, - .pa_end = 0x48304000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } +static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x002c, + .syss_offs = 0x0028, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | + SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | + SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE | + SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, }; -/* l4_core -> timer12 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = { - .master = &omap3xxx_l4_sec_hwmod, - .slave = &omap3xxx_timer12_hwmod, - .clk = "gpt12_ick", - .addr = omap3xxx_timer12_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap_hwmod_class omap3xxx_dma_hwmod_class = { + .name = "dma", + .sysc = &omap3xxx_dma_sysc, }; -/* timer12 hwmod */ -static struct omap_hwmod omap3xxx_timer12_hwmod = { - .name = "timer12", - .mpu_irqs = omap3xxx_timer12_mpu_irqs, - .main_clk = "gpt12_fck", - .prcm = { +/* dma_system */ +static struct omap_hwmod omap3xxx_dma_system_hwmod = { + .name = "dma", + .class = &omap3xxx_dma_hwmod_class, + .mpu_irqs = omap2_dma_system_irqs, + .main_clk = "core_l3_ick", + .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPT12_SHIFT, - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT, + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_ST_SDMA_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT, }, }, - .dev_attr = &capability_secure_dev_attr, - .class = &omap3xxx_timer_hwmod_class, + .dev_attr = &dma_dev_attr, + .flags = HWMOD_NO_IDLEST, }; -/* l4_wkup -> wd_timer2 */ -static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = { - { - .pa_start = 0x48314000, - .pa_end = 0x4831407f, - .flags = ADDR_TYPE_RT - }, - { } +/* + * 'mcbsp' class + * multi channel buffered serial port controller + */ + +static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = { + .sysc_offs = 0x008c, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, + .clockact = 0x2, }; -static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = { - .master = &omap3xxx_l4_wkup_hwmod, - .slave = &omap3xxx_wd_timer2_hwmod, - .clk = "wdt2_ick", - .addr = omap3xxx_wd_timer2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = { + .name = "mcbsp", + .sysc = &omap3xxx_mcbsp_sysc, + .rev = MCBSP_CONFIG_TYPE3, }; -/* - * 'wd_timer' class - * 32-bit watchdog upward counter that generates a pulse on the reset pin on - * overflow condition - */ +/* mcbsp1 */ +static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = { + { .name = "irq", .irq = 16 }, + { .name = "tx", .irq = 59 }, + { .name = "rx", .irq = 60 }, + { .irq = -1 } +}; -static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE | - SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | - SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | - SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, +static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { + .name = "mcbsp1", + .class = &omap3xxx_mcbsp_hwmod_class, + .mpu_irqs = omap3xxx_mcbsp1_irqs, + .sdma_reqs = omap2_mcbsp1_sdma_reqs, + .main_clk = "mcbsp1_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MCBSP1_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT, + }, + }, }; -/* I2C common */ -static struct omap_hwmod_class_sysconfig i2c_sysc = { - .rev_offs = 0x00, - .sysc_offs = 0x20, - .syss_offs = 0x10, - .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | - SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | - SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .clockact = CLOCKACT_TEST_ICLK, - .sysc_fields = &omap_hwmod_sysc_type1, +/* mcbsp2 */ +static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = { + { .name = "irq", .irq = 17 }, + { .name = "tx", .irq = 62 }, + { .name = "rx", .irq = 63 }, + { .irq = -1 } }; -static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = { - .name = "wd_timer", - .sysc = &omap3xxx_wd_timer_sysc, - .pre_shutdown = &omap2_wd_timer_disable +static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = { + .sidetone = "mcbsp2_sidetone", }; -static struct omap_hwmod omap3xxx_wd_timer2_hwmod = { - .name = "wd_timer2", - .class = &omap3xxx_wd_timer_hwmod_class, - .main_clk = "wdt2_fck", +static struct omap_hwmod omap3xxx_mcbsp2_hwmod = { + .name = "mcbsp2", + .class = &omap3xxx_mcbsp_hwmod_class, + .mpu_irqs = omap3xxx_mcbsp2_irqs, + .sdma_reqs = omap2_mcbsp2_sdma_reqs, + .main_clk = "mcbsp2_fck", .prcm = { .omap2 = { .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_WDT2_SHIFT, - .module_offs = WKUP_MOD, + .module_bit = OMAP3430_EN_MCBSP2_SHIFT, + .module_offs = OMAP3430_PER_MOD, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT, + .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, }, }, - /* - * XXX: Use software supervised mode, HW supervised smartidle seems to - * block CORE power domain idle transitions. Maybe a HW bug in wdt2? - */ - .flags = HWMOD_SWSUP_SIDLE, + .dev_attr = &omap34xx_mcbsp2_dev_attr, }; -/* UART1 */ -static struct omap_hwmod omap3xxx_uart1_hwmod = { - .name = "uart1", - .mpu_irqs = omap2_uart1_mpu_irqs, - .sdma_reqs = omap2_uart1_sdma_reqs, - .main_clk = "uart1_fck", +/* mcbsp3 */ +static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = { + { .name = "irq", .irq = 22 }, + { .name = "tx", .irq = 89 }, + { .name = "rx", .irq = 90 }, + { .irq = -1 } +}; + +static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = { + .sidetone = "mcbsp3_sidetone", +}; + +static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { + .name = "mcbsp3", + .class = &omap3xxx_mcbsp_hwmod_class, + .mpu_irqs = omap3xxx_mcbsp3_irqs, + .sdma_reqs = omap2_mcbsp3_sdma_reqs, + .main_clk = "mcbsp3_fck", .prcm = { .omap2 = { - .module_offs = CORE_MOD, .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_UART1_SHIFT, + .module_bit = OMAP3430_EN_MCBSP3_SHIFT, + .module_offs = OMAP3430_PER_MOD, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT, + .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, }, }, - .class = &omap2_uart_class, + .dev_attr = &omap34xx_mcbsp3_dev_attr, }; -/* UART2 */ -static struct omap_hwmod omap3xxx_uart2_hwmod = { - .name = "uart2", - .mpu_irqs = omap2_uart2_mpu_irqs, - .sdma_reqs = omap2_uart2_sdma_reqs, - .main_clk = "uart2_fck", +/* mcbsp4 */ +static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = { + { .name = "irq", .irq = 23 }, + { .name = "tx", .irq = 54 }, + { .name = "rx", .irq = 55 }, + { .irq = -1 } +}; + +static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = { + { .name = "rx", .dma_req = 20 }, + { .name = "tx", .dma_req = 19 }, + { .dma_req = -1 } +}; + +static struct omap_hwmod omap3xxx_mcbsp4_hwmod = { + .name = "mcbsp4", + .class = &omap3xxx_mcbsp_hwmod_class, + .mpu_irqs = omap3xxx_mcbsp4_irqs, + .sdma_reqs = omap3xxx_mcbsp4_sdma_chs, + .main_clk = "mcbsp4_fck", .prcm = { .omap2 = { - .module_offs = CORE_MOD, .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_UART2_SHIFT, + .module_bit = OMAP3430_EN_MCBSP4_SHIFT, + .module_offs = OMAP3430_PER_MOD, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT, + .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT, }, }, - .class = &omap2_uart_class, }; -/* UART3 */ -static struct omap_hwmod omap3xxx_uart3_hwmod = { - .name = "uart3", - .mpu_irqs = omap2_uart3_mpu_irqs, - .sdma_reqs = omap2_uart3_sdma_reqs, - .main_clk = "uart3_fck", +/* mcbsp5 */ +static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = { + { .name = "irq", .irq = 27 }, + { .name = "tx", .irq = 81 }, + { .name = "rx", .irq = 82 }, + { .irq = -1 } +}; + +static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = { + { .name = "rx", .dma_req = 22 }, + { .name = "tx", .dma_req = 21 }, + { .dma_req = -1 } +}; + +static struct omap_hwmod omap3xxx_mcbsp5_hwmod = { + .name = "mcbsp5", + .class = &omap3xxx_mcbsp_hwmod_class, + .mpu_irqs = omap3xxx_mcbsp5_irqs, + .sdma_reqs = omap3xxx_mcbsp5_sdma_chs, + .main_clk = "mcbsp5_fck", .prcm = { .omap2 = { - .module_offs = OMAP3430_PER_MOD, .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_UART3_SHIFT, + .module_bit = OMAP3430_EN_MCBSP5_SHIFT, + .module_offs = CORE_MOD, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT, + .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT, }, }, - .class = &omap2_uart_class, }; -/* UART4 */ +/* 'mcbsp sidetone' class */ +static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = { + .sysc_offs = 0x0010, + .sysc_flags = SYSC_HAS_AUTOIDLE, + .sysc_fields = &omap_hwmod_sysc_type1, +}; -static struct omap_hwmod_irq_info uart4_mpu_irqs[] = { - { .irq = INT_36XX_UART4_IRQ, }, - { .irq = -1 } +static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = { + .name = "mcbsp_sidetone", + .sysc = &omap3xxx_mcbsp_sidetone_sysc, }; -static struct omap_hwmod_dma_info uart4_sdma_reqs[] = { - { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, }, - { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, }, - { .dma_req = -1 } +/* mcbsp2_sidetone */ +static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = { + { .name = "irq", .irq = 4 }, + { .irq = -1 } }; -static struct omap_hwmod omap36xx_uart4_hwmod = { - .name = "uart4", - .mpu_irqs = uart4_mpu_irqs, - .sdma_reqs = uart4_sdma_reqs, - .main_clk = "uart4_fck", +static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { + .name = "mcbsp2_sidetone", + .class = &omap3xxx_mcbsp_sidetone_hwmod_class, + .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs, + .main_clk = "mcbsp2_fck", .prcm = { .omap2 = { - .module_offs = OMAP3430_PER_MOD, .prcm_reg_id = 1, - .module_bit = OMAP3630_EN_UART4_SHIFT, + .module_bit = OMAP3430_EN_MCBSP2_SHIFT, + .module_offs = OMAP3430_PER_MOD, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT, + .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, }, }, - .class = &omap2_uart_class, -}; - -static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = { - { .irq = INT_35XX_UART4_IRQ, }, }; -static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = { - { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, }, - { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, }, +/* mcbsp3_sidetone */ +static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = { + { .name = "irq", .irq = 5 }, + { .irq = -1 } }; -static struct omap_hwmod am35xx_uart4_hwmod = { - .name = "uart4", - .mpu_irqs = am35xx_uart4_mpu_irqs, - .sdma_reqs = am35xx_uart4_sdma_reqs, - .main_clk = "uart4_fck", +static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = { + .name = "mcbsp3_sidetone", + .class = &omap3xxx_mcbsp_sidetone_hwmod_class, + .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs, + .main_clk = "mcbsp3_fck", .prcm = { .omap2 = { - .module_offs = CORE_MOD, .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_UART4_SHIFT, + .module_bit = OMAP3430_EN_MCBSP3_SHIFT, + .module_offs = OMAP3430_PER_MOD, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_EN_UART4_SHIFT, + .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, }, }, - .class = &omap2_uart_class, }; +/* SR common */ +static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = { + .clkact_shift = 20, +}; -static struct omap_hwmod_class i2c_class = { - .name = "i2c", - .sysc = &i2c_sysc, - .rev = OMAP_I2C_IP_VERSION_1, - .reset = &omap_i2c_reset, +static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = { + .sysc_offs = 0x24, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE), + .clockact = CLOCKACT_TEST_ICLK, + .sysc_fields = &omap34xx_sr_sysc_fields, }; -static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = { - { .name = "dispc", .dma_req = 5 }, - { .name = "dsi1", .dma_req = 74 }, - { .dma_req = -1 } +static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = { + .name = "smartreflex", + .sysc = &omap34xx_sr_sysc, + .rev = 1, }; -/* dss */ +static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = { + .sidle_shift = 24, + .enwkup_shift = 26, +}; -/* l4_core -> dss */ -static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3430es1_dss_core_hwmod, - .clk = "dss_ick", - .addr = omap2_dss_addrs, - .fw = { +static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = { + .sysc_offs = 0x38, + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | + SYSC_NO_CACHE), + .sysc_fields = &omap36xx_sr_sysc_fields, +}; + +static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = { + .name = "smartreflex", + .sysc = &omap36xx_sr_sysc, + .rev = 2, +}; + +/* SR1 */ +static struct omap_smartreflex_dev_attr sr1_dev_attr = { + .sensor_voltdm_name = "mpu_iva", +}; + +static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = { + { .irq = 18 }, + { .irq = -1 } +}; + +static struct omap_hwmod omap34xx_sr1_hwmod = { + .name = "sr1", + .class = &omap34xx_smartreflex_hwmod_class, + .main_clk = "sr1_fck", + .prcm = { .omap2 = { - .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION, - .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, - .flags = OMAP_FIREWALL_L4, - } + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_SR1_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, + }, }, - .user = OCP_USER_MPU | OCP_USER_SDMA, + .dev_attr = &sr1_dev_attr, + .mpu_irqs = omap3_smartreflex_mpu_irqs, + .flags = HWMOD_SET_DEFAULT_CLOCKACT, }; -static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_dss_core_hwmod, - .clk = "dss_ick", - .addr = omap2_dss_addrs, - .fw = { +static struct omap_hwmod omap36xx_sr1_hwmod = { + .name = "sr1", + .class = &omap36xx_smartreflex_hwmod_class, + .main_clk = "sr1_fck", + .prcm = { .omap2 = { - .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION, - .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, - .flags = OMAP_FIREWALL_L4, - } + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_SR1_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, + }, }, - .user = OCP_USER_MPU | OCP_USER_SDMA, + .dev_attr = &sr1_dev_attr, + .mpu_irqs = omap3_smartreflex_mpu_irqs, }; -static struct omap_hwmod_opt_clk dss_opt_clks[] = { - /* - * The DSS HW needs all DSS clocks enabled during reset. The dss_core - * driver does not use these clocks. - */ - { .role = "sys_clk", .clk = "dss2_alwon_fck" }, - { .role = "tv_clk", .clk = "dss_tv_fck" }, - /* required only on OMAP3430 */ - { .role = "tv_dac_clk", .clk = "dss_96m_fck" }, +/* SR2 */ +static struct omap_smartreflex_dev_attr sr2_dev_attr = { + .sensor_voltdm_name = "core", }; -static struct omap_hwmod omap3430es1_dss_core_hwmod = { - .name = "dss_core", - .class = &omap2_dss_hwmod_class, - .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ - .sdma_reqs = omap3xxx_dss_sdma_chs, +static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = { + { .irq = 19 }, + { .irq = -1 } +}; + +static struct omap_hwmod omap34xx_sr2_hwmod = { + .name = "sr2", + .class = &omap34xx_smartreflex_hwmod_class, + .main_clk = "sr2_fck", .prcm = { .omap2 = { .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_DSS1_SHIFT, - .module_offs = OMAP3430_DSS_MOD, + .module_bit = OMAP3430_EN_SR2_SHIFT, + .module_offs = WKUP_MOD, .idlest_reg_id = 1, - .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT, + .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, }, }, - .opt_clks = dss_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), - .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .dev_attr = &sr2_dev_attr, + .mpu_irqs = omap3_smartreflex_core_irqs, + .flags = HWMOD_SET_DEFAULT_CLOCKACT, }; -static struct omap_hwmod omap3xxx_dss_core_hwmod = { - .name = "dss_core", - .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .class = &omap2_dss_hwmod_class, - .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ - .sdma_reqs = omap3xxx_dss_sdma_chs, +static struct omap_hwmod omap36xx_sr2_hwmod = { + .name = "sr2", + .class = &omap36xx_smartreflex_hwmod_class, + .main_clk = "sr2_fck", .prcm = { .omap2 = { .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_DSS1_SHIFT, - .module_offs = OMAP3430_DSS_MOD, + .module_bit = OMAP3430_EN_SR2_SHIFT, + .module_offs = WKUP_MOD, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT, - .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT, + .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, }, }, - .opt_clks = dss_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), + .dev_attr = &sr2_dev_attr, + .mpu_irqs = omap3_smartreflex_core_irqs, }; /* - * 'dispc' class - * display controller + * 'mailbox' class + * mailbox module allowing communication between the on-chip processors + * using a queued mailbox-interrupt mechanism. */ -static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | - SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | - SYSC_HAS_ENAWAKEUP), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), +static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = { + .rev_offs = 0x000, + .sysc_offs = 0x010, + .syss_offs = 0x014, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), .sysc_fields = &omap_hwmod_sysc_type1, }; -static struct omap_hwmod_class omap3_dispc_hwmod_class = { - .name = "dispc", - .sysc = &omap3_dispc_sysc, +static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = { + .name = "mailbox", + .sysc = &omap3xxx_mailbox_sysc, }; -/* l4_core -> dss_dispc */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_dss_dispc_hwmod, - .clk = "dss_ick", - .addr = omap2_dss_dispc_addrs, - .fw = { - .omap2 = { - .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION, - .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, - .flags = OMAP_FIREWALL_L4, - } - }, - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = { + { .irq = 26 }, + { .irq = -1 } }; -static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { - .name = "dss_dispc", - .class = &omap3_dispc_hwmod_class, - .mpu_irqs = omap2_dispc_irqs, - .main_clk = "dss1_alwon_fck", +static struct omap_hwmod omap3xxx_mailbox_hwmod = { + .name = "mailbox", + .class = &omap3xxx_mailbox_hwmod_class, + .mpu_irqs = omap3xxx_mailbox_irqs, + .main_clk = "mailboxes_ick", .prcm = { .omap2 = { .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_DSS1_SHIFT, - .module_offs = OMAP3430_DSS_MOD, + .module_bit = OMAP3430_EN_MAILBOXES_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT, }, }, - .flags = HWMOD_NO_IDLEST, - .dev_attr = &omap2_3_dss_dispc_dev_attr }; /* - * 'dsi' class - * display serial interface controller + * 'mcspi' class + * multichannel serial port interface (mcspi) / master/slave synchronous serial + * bus */ -static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = { - .name = "dsi", +static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, }; -static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = { - { .irq = 25 }, - { .irq = -1 } +static struct omap_hwmod_class omap34xx_mcspi_class = { + .name = "mcspi", + .sysc = &omap34xx_mcspi_sysc, + .rev = OMAP3_MCSPI_REV, }; -/* dss_dsi1 */ -static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = { - { - .pa_start = 0x4804FC00, - .pa_end = 0x4804FFFF, - .flags = ADDR_TYPE_RT - }, - { } +/* mcspi1 */ +static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { + .num_chipselect = 4, }; -/* l4_core -> dss_dsi1 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_dss_dsi1_hwmod, - .clk = "dss_ick", - .addr = omap3xxx_dss_dsi1_addrs, - .fw = { +static struct omap_hwmod omap34xx_mcspi1 = { + .name = "mcspi1", + .mpu_irqs = omap2_mcspi1_mpu_irqs, + .sdma_reqs = omap2_mcspi1_sdma_reqs, + .main_clk = "mcspi1_fck", + .prcm = { .omap2 = { - .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION, - .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, - .flags = OMAP_FIREWALL_L4, - } + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MCSPI1_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT, + }, }, - .user = OCP_USER_MPU | OCP_USER_SDMA, + .class = &omap34xx_mcspi_class, + .dev_attr = &omap_mcspi1_dev_attr, }; -static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { - { .role = "sys_clk", .clk = "dss2_alwon_fck" }, +/* mcspi2 */ +static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { + .num_chipselect = 2, }; -static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = { - .name = "dss_dsi1", - .class = &omap3xxx_dsi_hwmod_class, - .mpu_irqs = omap3xxx_dsi1_irqs, - .main_clk = "dss1_alwon_fck", +static struct omap_hwmod omap34xx_mcspi2 = { + .name = "mcspi2", + .mpu_irqs = omap2_mcspi2_mpu_irqs, + .sdma_reqs = omap2_mcspi2_sdma_reqs, + .main_clk = "mcspi2_fck", .prcm = { .omap2 = { + .module_offs = CORE_MOD, .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_DSS1_SHIFT, - .module_offs = OMAP3430_DSS_MOD, + .module_bit = OMAP3430_EN_MCSPI2_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT, }, }, - .opt_clks = dss_dsi1_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), - .flags = HWMOD_NO_IDLEST, + .class = &omap34xx_mcspi_class, + .dev_attr = &omap_mcspi2_dev_attr, }; -/* l4_core -> dss_rfbi */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_dss_rfbi_hwmod, - .clk = "dss_ick", - .addr = omap2_dss_rfbi_addrs, - .fw = { - .omap2 = { - .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION, - .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP , - .flags = OMAP_FIREWALL_L4, - } - }, - .user = OCP_USER_MPU | OCP_USER_SDMA, +/* mcspi3 */ +static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = { + { .name = "irq", .irq = 91 }, /* 91 */ + { .irq = -1 } +}; + +static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = { + { .name = "tx0", .dma_req = 15 }, + { .name = "rx0", .dma_req = 16 }, + { .name = "tx1", .dma_req = 23 }, + { .name = "rx1", .dma_req = 24 }, + { .dma_req = -1 } }; -static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { - { .role = "ick", .clk = "dss_ick" }, +static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { + .num_chipselect = 2, }; -static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = { - .name = "dss_rfbi", - .class = &omap2_rfbi_hwmod_class, - .main_clk = "dss1_alwon_fck", +static struct omap_hwmod omap34xx_mcspi3 = { + .name = "mcspi3", + .mpu_irqs = omap34xx_mcspi3_mpu_irqs, + .sdma_reqs = omap34xx_mcspi3_sdma_reqs, + .main_clk = "mcspi3_fck", .prcm = { .omap2 = { + .module_offs = CORE_MOD, .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_DSS1_SHIFT, - .module_offs = OMAP3430_DSS_MOD, + .module_bit = OMAP3430_EN_MCSPI3_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT, }, }, - .opt_clks = dss_rfbi_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), - .flags = HWMOD_NO_IDLEST, + .class = &omap34xx_mcspi_class, + .dev_attr = &omap_mcspi3_dev_attr, }; -/* l4_core -> dss_venc */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_dss_venc_hwmod, - .clk = "dss_ick", - .addr = omap2_dss_venc_addrs, - .fw = { - .omap2 = { - .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION, - .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, - .flags = OMAP_FIREWALL_L4, - } - }, - .user = OCP_USER_MPU | OCP_USER_SDMA, +/* mcspi4 */ +static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = { + { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */ + { .irq = -1 } }; -static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = { - /* required only on OMAP3430 */ - { .role = "tv_dac_clk", .clk = "dss_96m_fck" }, +static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = { + { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */ + { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */ + { .dma_req = -1 } }; -static struct omap_hwmod omap3xxx_dss_venc_hwmod = { - .name = "dss_venc", - .class = &omap2_venc_hwmod_class, - .main_clk = "dss_tv_fck", +static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = { + .num_chipselect = 1, +}; + +static struct omap_hwmod omap34xx_mcspi4 = { + .name = "mcspi4", + .mpu_irqs = omap34xx_mcspi4_mpu_irqs, + .sdma_reqs = omap34xx_mcspi4_sdma_reqs, + .main_clk = "mcspi4_fck", .prcm = { .omap2 = { + .module_offs = CORE_MOD, .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_DSS1_SHIFT, - .module_offs = OMAP3430_DSS_MOD, + .module_bit = OMAP3430_EN_MCSPI4_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT, }, }, - .opt_clks = dss_venc_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks), - .flags = HWMOD_NO_IDLEST, + .class = &omap34xx_mcspi_class, + .dev_attr = &omap_mcspi4_dev_attr, }; -/* I2C1 */ +/* usbhsotg */ +static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = { + .rev_offs = 0x0400, + .sysc_offs = 0x0404, + .syss_offs = 0x0408, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; -static struct omap_i2c_dev_attr i2c1_dev_attr = { - .fifo_depth = 8, /* bytes */ - .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | - OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | - OMAP_I2C_FLAG_BUS_SHIFT_2, +static struct omap_hwmod_class usbotg_class = { + .name = "usbotg", + .sysc = &omap3xxx_usbhsotg_sysc, }; -static struct omap_hwmod omap3xxx_i2c1_hwmod = { - .name = "i2c1", - .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, - .mpu_irqs = omap2_i2c1_mpu_irqs, - .sdma_reqs = omap2_i2c1_sdma_reqs, - .main_clk = "i2c1_fck", +/* usb_otg_hs */ +static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = { + + { .name = "mc", .irq = 92 }, + { .name = "dma", .irq = 93 }, + { .irq = -1 } +}; + +static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { + .name = "usb_otg_hs", + .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs, + .main_clk = "hsotgusb_ick", .prcm = { .omap2 = { - .module_offs = CORE_MOD, .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_I2C1_SHIFT, + .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT, + .module_offs = CORE_MOD, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT, + .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT, + .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT }, }, - .class = &i2c_class, - .dev_attr = &i2c1_dev_attr, + .class = &usbotg_class, + + /* + * Erratum ID: i479 idle_req / idle_ack mechanism potentially + * broken when autoidle is enabled + * workaround is to disable the autoidle bit at module level. + */ + .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE + | HWMOD_SWSUP_MSTANDBY, }; -/* I2C2 */ +/* usb_otg_hs */ +static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = { -static struct omap_i2c_dev_attr i2c2_dev_attr = { - .fifo_depth = 8, /* bytes */ - .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | - OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | - OMAP_I2C_FLAG_BUS_SHIFT_2, + { .name = "mc", .irq = 71 }, + { .irq = -1 } }; -static struct omap_hwmod omap3xxx_i2c2_hwmod = { - .name = "i2c2", - .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, - .mpu_irqs = omap2_i2c2_mpu_irqs, - .sdma_reqs = omap2_i2c2_sdma_reqs, - .main_clk = "i2c2_fck", - .prcm = { +static struct omap_hwmod_class am35xx_usbotg_class = { + .name = "am35xx_usbotg", + .sysc = NULL, +}; + +static struct omap_hwmod am35xx_usbhsotg_hwmod = { + .name = "am35x_otg_hs", + .mpu_irqs = am35xx_usbhsotg_mpu_irqs, + .main_clk = NULL, + .prcm = { .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_I2C2_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT, }, }, - .class = &i2c_class, - .dev_attr = &i2c2_dev_attr, + .class = &am35xx_usbotg_class, }; -/* I2C3 */ +/* MMC/SD/SDIO common */ +static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = { + .rev_offs = 0x1fc, + .sysc_offs = 0x10, + .syss_offs = 0x14, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; -static struct omap_i2c_dev_attr i2c3_dev_attr = { - .fifo_depth = 64, /* bytes */ - .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | - OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | - OMAP_I2C_FLAG_BUS_SHIFT_2, +static struct omap_hwmod_class omap34xx_mmc_class = { + .name = "mmc", + .sysc = &omap34xx_mmc_sysc, }; -static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = { - { .irq = INT_34XX_I2C3_IRQ, }, +/* MMC/SD/SDIO1 */ + +static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = { + { .irq = 83, }, { .irq = -1 } }; -static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = { - { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX }, - { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX }, +static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = { + { .name = "tx", .dma_req = 61, }, + { .name = "rx", .dma_req = 62, }, { .dma_req = -1 } }; -static struct omap_hwmod omap3xxx_i2c3_hwmod = { - .name = "i2c3", - .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, - .mpu_irqs = i2c3_mpu_irqs, - .sdma_reqs = i2c3_sdma_reqs, - .main_clk = "i2c3_fck", +static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = { + { .role = "dbck", .clk = "omap_32k_fck", }, +}; + +static struct omap_mmc_dev_attr mmc1_dev_attr = { + .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, +}; + +/* See 35xx errata 2.1.1.128 in SPRZ278F */ +static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = { + .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT | + OMAP_HSMMC_BROKEN_MULTIBLOCK_READ), +}; + +static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = { + .name = "mmc1", + .mpu_irqs = omap34xx_mmc1_mpu_irqs, + .sdma_reqs = omap34xx_mmc1_sdma_reqs, + .opt_clks = omap34xx_mmc1_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), + .main_clk = "mmchs1_fck", .prcm = { .omap2 = { .module_offs = CORE_MOD, .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_I2C3_SHIFT, + .module_bit = OMAP3430_EN_MMC1_SHIFT, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT, + .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, }, }, - .class = &i2c_class, - .dev_attr = &i2c3_dev_attr, + .dev_attr = &mmc1_pre_es3_dev_attr, + .class = &omap34xx_mmc_class, }; -/* l4_wkup -> gpio1 */ -static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = { - { - .pa_start = 0x48310000, - .pa_end = 0x483101ff, - .flags = ADDR_TYPE_RT +static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = { + .name = "mmc1", + .mpu_irqs = omap34xx_mmc1_mpu_irqs, + .sdma_reqs = omap34xx_mmc1_sdma_reqs, + .opt_clks = omap34xx_mmc1_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), + .main_clk = "mmchs1_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MMC1_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, + }, }, - { } + .dev_attr = &mmc1_dev_attr, + .class = &omap34xx_mmc_class, }; -static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = { - .master = &omap3xxx_l4_wkup_hwmod, - .slave = &omap3xxx_gpio1_hwmod, - .addr = omap3xxx_gpio1_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; +/* MMC/SD/SDIO2 */ -/* l4_per -> gpio2 */ -static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = { - { - .pa_start = 0x49050000, - .pa_end = 0x490501ff, - .flags = ADDR_TYPE_RT - }, - { } +static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = { + { .irq = INT_24XX_MMC2_IRQ, }, + { .irq = -1 } }; -static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_gpio2_hwmod, - .addr = omap3xxx_gpio2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = { + { .name = "tx", .dma_req = 47, }, + { .name = "rx", .dma_req = 48, }, + { .dma_req = -1 } }; -/* l4_per -> gpio3 */ -static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = { - { - .pa_start = 0x49052000, - .pa_end = 0x490521ff, - .flags = ADDR_TYPE_RT - }, - { } +static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = { + { .role = "dbck", .clk = "omap_32k_fck", }, }; -static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_gpio3_hwmod, - .addr = omap3xxx_gpio3_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, +/* See 35xx errata 2.1.1.128 in SPRZ278F */ +static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = { + .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, }; -/* l4_per -> gpio4 */ -static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = { - { - .pa_start = 0x49054000, - .pa_end = 0x490541ff, - .flags = ADDR_TYPE_RT +static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = { + .name = "mmc2", + .mpu_irqs = omap34xx_mmc2_mpu_irqs, + .sdma_reqs = omap34xx_mmc2_sdma_reqs, + .opt_clks = omap34xx_mmc2_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), + .main_clk = "mmchs2_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MMC2_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, + }, }, - { } + .dev_attr = &mmc2_pre_es3_dev_attr, + .class = &omap34xx_mmc_class, }; -static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_gpio4_hwmod, - .addr = omap3xxx_gpio4_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = { + .name = "mmc2", + .mpu_irqs = omap34xx_mmc2_mpu_irqs, + .sdma_reqs = omap34xx_mmc2_sdma_reqs, + .opt_clks = omap34xx_mmc2_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), + .main_clk = "mmchs2_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MMC2_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, + }, + }, + .class = &omap34xx_mmc_class, }; -/* l4_per -> gpio5 */ -static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = { - { - .pa_start = 0x49056000, - .pa_end = 0x490561ff, - .flags = ADDR_TYPE_RT - }, - { } +/* MMC/SD/SDIO3 */ + +static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = { + { .irq = 94, }, + { .irq = -1 } }; -static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_gpio5_hwmod, - .addr = omap3xxx_gpio5_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = { + { .name = "tx", .dma_req = 77, }, + { .name = "rx", .dma_req = 78, }, + { .dma_req = -1 } }; -/* l4_per -> gpio6 */ -static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = { - { - .pa_start = 0x49058000, - .pa_end = 0x490581ff, - .flags = ADDR_TYPE_RT - }, - { } +static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = { + { .role = "dbck", .clk = "omap_32k_fck", }, }; -static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_gpio6_hwmod, - .addr = omap3xxx_gpio6_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap_hwmod omap3xxx_mmc3_hwmod = { + .name = "mmc3", + .mpu_irqs = omap34xx_mmc3_mpu_irqs, + .sdma_reqs = omap34xx_mmc3_sdma_reqs, + .opt_clks = omap34xx_mmc3_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks), + .main_clk = "mmchs3_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MMC3_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT, + }, + }, + .class = &omap34xx_mmc_class, }; /* - * 'gpio' class - * general purpose io module + * 'usb_host_hs' class + * high-speed multi-port usb host controller */ -static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = { +static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = { .rev_offs = 0x0000, .sysc_offs = 0x0010, .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | - SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, + .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | + SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, }; -static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = { - .name = "gpio", - .sysc = &omap3xxx_gpio_sysc, - .rev = 1, +static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = { + .name = "usb_host_hs", + .sysc = &omap3xxx_usb_host_hs_sysc, }; -/* gpio_dev_attr*/ -static struct omap_gpio_dev_attr gpio_dev_attr = { - .bank_width = 32, - .dbck_flag = true, +static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = { + { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", }, }; -/* gpio1 */ -static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { - { .role = "dbclk", .clk = "gpio1_dbck", }, +static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = { + { .name = "ohci-irq", .irq = 76 }, + { .name = "ehci-irq", .irq = 77 }, + { .irq = -1 } }; -static struct omap_hwmod omap3xxx_gpio1_hwmod = { - .name = "gpio1", - .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap2_gpio1_irqs, - .main_clk = "gpio1_ick", - .opt_clks = gpio1_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), - .prcm = { +static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = { + .name = "usb_host_hs", + .class = &omap3xxx_usb_host_hs_hwmod_class, + .clkdm_name = "l3_init_clkdm", + .mpu_irqs = omap3xxx_usb_host_hs_irqs, + .main_clk = "usbhost_48m_fck", + .prcm = { .omap2 = { + .module_offs = OMAP3430ES2_USBHOST_MOD, .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPIO1_SHIFT, - .module_offs = WKUP_MOD, + .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT, + .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT, + .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT, }, }, - .class = &omap3xxx_gpio_hwmod_class, - .dev_attr = &gpio_dev_attr, -}; + .opt_clks = omap3xxx_usb_host_hs_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks), -/* gpio2 */ -static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { - { .role = "dbclk", .clk = "gpio2_dbck", }, -}; + /* + * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock + * id: i660 + * + * Description: + * In the following configuration : + * - USBHOST module is set to smart-idle mode + * - PRCM asserts idle_req to the USBHOST module ( This typically + * happens when the system is going to a low power mode : all ports + * have been suspended, the master part of the USBHOST module has + * entered the standby state, and SW has cut the functional clocks) + * - an USBHOST interrupt occurs before the module is able to answer + * idle_ack, typically a remote wakeup IRQ. + * Then the USB HOST module will enter a deadlock situation where it + * is no more accessible nor functional. + * + * Workaround: + * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE + */ + + /* + * Errata: USB host EHCI may stall when entering smart-standby mode + * Id: i571 + * + * Description: + * When the USBHOST module is set to smart-standby mode, and when it is + * ready to enter the standby state (i.e. all ports are suspended and + * all attached devices are in suspend mode), then it can wrongly assert + * the Mstandby signal too early while there are still some residual OCP + * transactions ongoing. If this condition occurs, the internal state + * machine may go to an undefined state and the USB link may be stuck + * upon the next resume. + * + * Workaround: + * Don't use smart standby; use only force standby, + * hence HWMOD_SWSUP_MSTANDBY + */ + + /* + * During system boot; If the hwmod framework resets the module + * the module will have smart idle settings; which can lead to deadlock + * (above Errata Id:i660); so, dont reset the module during boot; + * Use HWMOD_INIT_NO_RESET. + */ -static struct omap_hwmod omap3xxx_gpio2_hwmod = { - .name = "gpio2", - .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap2_gpio2_irqs, - .main_clk = "gpio2_ick", - .opt_clks = gpio2_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPIO2_SHIFT, - .module_offs = OMAP3430_PER_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT, - }, - }, - .class = &omap3xxx_gpio_hwmod_class, - .dev_attr = &gpio_dev_attr, + .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY | + HWMOD_INIT_NO_RESET, }; -/* gpio3 */ -static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { - { .role = "dbclk", .clk = "gpio3_dbck", }, +/* + * 'usb_tll_hs' class + * usb_tll_hs module is the adapter on the usb_host_hs ports + */ +static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, }; -static struct omap_hwmod omap3xxx_gpio3_hwmod = { - .name = "gpio3", - .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap2_gpio3_irqs, - .main_clk = "gpio3_ick", - .opt_clks = gpio3_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPIO3_SHIFT, - .module_offs = OMAP3430_PER_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT, - }, - }, - .class = &omap3xxx_gpio_hwmod_class, - .dev_attr = &gpio_dev_attr, +static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = { + .name = "usb_tll_hs", + .sysc = &omap3xxx_usb_tll_hs_sysc, }; -/* gpio4 */ -static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { - { .role = "dbclk", .clk = "gpio4_dbck", }, +static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = { + { .name = "tll-irq", .irq = 78 }, + { .irq = -1 } }; -static struct omap_hwmod omap3xxx_gpio4_hwmod = { - .name = "gpio4", - .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap2_gpio4_irqs, - .main_clk = "gpio4_ick", - .opt_clks = gpio4_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), - .prcm = { +static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = { + .name = "usb_tll_hs", + .class = &omap3xxx_usb_tll_hs_hwmod_class, + .clkdm_name = "l3_init_clkdm", + .mpu_irqs = omap3xxx_usb_tll_hs_irqs, + .main_clk = "usbtll_fck", + .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPIO4_SHIFT, - .module_offs = OMAP3430_PER_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT, + .module_offs = CORE_MOD, + .prcm_reg_id = 3, + .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT, + .idlest_reg_id = 3, + .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT, }, }, - .class = &omap3xxx_gpio_hwmod_class, - .dev_attr = &gpio_dev_attr, }; -/* gpio5 */ -static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = { - { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */ - { .irq = -1 } +/* + * interfaces + */ + +/* L3 -> L4_CORE interface */ +static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { + .master = &omap3xxx_l3_main_hwmod, + .slave = &omap3xxx_l4_core_hwmod, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { - { .role = "dbclk", .clk = "gpio5_dbck", }, +/* L3 -> L4_PER interface */ +static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = { + .master = &omap3xxx_l3_main_hwmod, + .slave = &omap3xxx_l4_per_hwmod, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod omap3xxx_gpio5_hwmod = { - .name = "gpio5", - .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap3xxx_gpio5_irqs, - .main_clk = "gpio5_ick", - .opt_clks = gpio5_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPIO5_SHIFT, - .module_offs = OMAP3430_PER_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT, - }, +static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = { + { + .pa_start = 0x68000000, + .pa_end = 0x6800ffff, + .flags = ADDR_TYPE_RT, }, - .class = &omap3xxx_gpio_hwmod_class, - .dev_attr = &gpio_dev_attr, + { } }; -/* gpio6 */ -static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = { - { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */ - { .irq = -1 } +/* MPU -> L3 interface */ +static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = { + .master = &omap3xxx_mpu_hwmod, + .slave = &omap3xxx_l3_main_hwmod, + .addr = omap3xxx_l3_main_addrs, + .user = OCP_USER_MPU, }; -static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { - { .role = "dbclk", .clk = "gpio6_dbck", }, +/* DSS -> l3 */ +static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = { + .master = &omap3430es1_dss_core_hwmod, + .slave = &omap3xxx_l3_main_hwmod, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod omap3xxx_gpio6_hwmod = { - .name = "gpio6", - .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap3xxx_gpio6_irqs, - .main_clk = "gpio6_ick", - .opt_clks = gpio6_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), - .prcm = { +static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = { + .master = &omap3xxx_dss_core_hwmod, + .slave = &omap3xxx_l3_main_hwmod, + .fw = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPIO6_SHIFT, - .module_offs = OMAP3430_PER_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT, - }, + .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS, + .flags = OMAP_FIREWALL_L3, + } }, - .class = &omap3xxx_gpio_hwmod_class, - .dev_attr = &gpio_dev_attr, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* dma_system -> L3 */ -static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = { - .master = &omap3xxx_dma_system_hwmod, +/* l3_core -> usbhsotg interface */ +static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = { + .master = &omap3xxx_usbhsotg_hwmod, .slave = &omap3xxx_l3_main_hwmod, .clk = "core_l3_ick", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* dma attributes */ -static struct omap_dma_dev_attr dma_dev_attr = { - .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | - IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, - .lch_count = 32, -}; - -static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x002c, - .syss_offs = 0x0028, - .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | - SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | - SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE | - SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, + .user = OCP_USER_MPU, }; -static struct omap_hwmod_class omap3xxx_dma_hwmod_class = { - .name = "dma", - .sysc = &omap3xxx_dma_sysc, +/* l3_core -> am35xx_usbhsotg interface */ +static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = { + .master = &am35xx_usbhsotg_hwmod, + .slave = &omap3xxx_l3_main_hwmod, + .clk = "core_l3_ick", + .user = OCP_USER_MPU, }; - -/* dma_system */ -static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = { - { - .pa_start = 0x48056000, - .pa_end = 0x48056fff, - .flags = ADDR_TYPE_RT - }, - { } +/* L4_CORE -> L4_WKUP interface */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_l4_wkup_hwmod, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4_cfg -> dma_system */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = { +/* L4 CORE -> MMC1 interface */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = { .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_dma_system_hwmod, - .clk = "core_l4_ick", - .addr = omap3xxx_dma_system_addrs, + .slave = &omap3xxx_pre_es3_mmc1_hwmod, + .clk = "mmchs1_ick", + .addr = omap2430_mmc1_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, + .flags = OMAP_FIREWALL_L4 }; -static struct omap_hwmod omap3xxx_dma_system_hwmod = { - .name = "dma", - .class = &omap3xxx_dma_hwmod_class, - .mpu_irqs = omap2_dma_system_irqs, - .main_clk = "core_l3_ick", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP3430_ST_SDMA_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT, - }, - }, - .dev_attr = &dma_dev_attr, - .flags = HWMOD_NO_IDLEST, +static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_es3plus_mmc1_hwmod, + .clk = "mmchs1_ick", + .addr = omap2430_mmc1_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, + .flags = OMAP_FIREWALL_L4 }; -/* - * 'mcbsp' class - * multi channel buffered serial port controller - */ +/* L4 CORE -> MMC2 interface */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_pre_es3_mmc2_hwmod, + .clk = "mmchs2_ick", + .addr = omap2430_mmc2_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, + .flags = OMAP_FIREWALL_L4 +}; -static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = { - .sysc_offs = 0x008c, - .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | - SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, - .clockact = 0x2, +static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_es3plus_mmc2_hwmod, + .clk = "mmchs2_ick", + .addr = omap2430_mmc2_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, + .flags = OMAP_FIREWALL_L4 }; -static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = { - .name = "mcbsp", - .sysc = &omap3xxx_mcbsp_sysc, - .rev = MCBSP_CONFIG_TYPE3, +/* L4 CORE -> MMC3 interface */ +static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = { + { + .pa_start = 0x480ad000, + .pa_end = 0x480ad1ff, + .flags = ADDR_TYPE_RT, + }, + { } }; -/* mcbsp1 */ -static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = { - { .name = "irq", .irq = 16 }, - { .name = "tx", .irq = 59 }, - { .name = "rx", .irq = 60 }, - { .irq = -1 } +static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_mmc3_hwmod, + .clk = "mmchs3_ick", + .addr = omap3xxx_mmc3_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, + .flags = OMAP_FIREWALL_L4 }; -static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = { +/* L4 CORE -> UART1 interface */ +static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = { { - .name = "mpu", - .pa_start = 0x48074000, - .pa_end = 0x480740ff, - .flags = ADDR_TYPE_RT + .pa_start = OMAP3_UART1_BASE, + .pa_end = OMAP3_UART1_BASE + SZ_8K - 1, + .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, }, { } }; -/* l4_core -> mcbsp1 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = { +static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = { .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_mcbsp1_hwmod, - .clk = "mcbsp1_ick", - .addr = omap3xxx_mcbsp1_addrs, + .slave = &omap3xxx_uart1_hwmod, + .clk = "uart1_ick", + .addr = omap3xxx_uart1_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { - .name = "mcbsp1", - .class = &omap3xxx_mcbsp_hwmod_class, - .mpu_irqs = omap3xxx_mcbsp1_irqs, - .sdma_reqs = omap2_mcbsp1_sdma_reqs, - .main_clk = "mcbsp1_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_MCBSP1_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT, - }, +/* L4 CORE -> UART2 interface */ +static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = { + { + .pa_start = OMAP3_UART2_BASE, + .pa_end = OMAP3_UART2_BASE + SZ_1K - 1, + .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, }, + { } }; -/* mcbsp2 */ -static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = { - { .name = "irq", .irq = 17 }, - { .name = "tx", .irq = 62 }, - { .name = "rx", .irq = 63 }, - { .irq = -1 } +static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_uart2_hwmod, + .clk = "uart2_ick", + .addr = omap3xxx_uart2_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = { +/* L4 PER -> UART3 interface */ +static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = { { - .name = "mpu", - .pa_start = 0x49022000, - .pa_end = 0x490220ff, - .flags = ADDR_TYPE_RT + .pa_start = OMAP3_UART3_BASE, + .pa_end = OMAP3_UART3_BASE + SZ_1K - 1, + .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, }, { } }; -/* l4_per -> mcbsp2 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = { +static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = { .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_mcbsp2_hwmod, - .clk = "mcbsp2_ick", - .addr = omap3xxx_mcbsp2_addrs, + .slave = &omap3xxx_uart3_hwmod, + .clk = "uart3_ick", + .addr = omap3xxx_uart3_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = { - .sidetone = "mcbsp2_sidetone", -}; - -static struct omap_hwmod omap3xxx_mcbsp2_hwmod = { - .name = "mcbsp2", - .class = &omap3xxx_mcbsp_hwmod_class, - .mpu_irqs = omap3xxx_mcbsp2_irqs, - .sdma_reqs = omap2_mcbsp2_sdma_reqs, - .main_clk = "mcbsp2_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_MCBSP2_SHIFT, - .module_offs = OMAP3430_PER_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, - }, +/* L4 PER -> UART4 interface */ +static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = { + { + .pa_start = OMAP3_UART4_BASE, + .pa_end = OMAP3_UART4_BASE + SZ_1K - 1, + .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, }, - .dev_attr = &omap34xx_mcbsp2_dev_attr, + { } }; -/* mcbsp3 */ -static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = { - { .name = "irq", .irq = 22 }, - { .name = "tx", .irq = 89 }, - { .name = "rx", .irq = 90 }, - { .irq = -1 } +static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap36xx_uart4_hwmod, + .clk = "uart4_ick", + .addr = omap36xx_uart4_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = { +/* AM35xx: L4 CORE -> UART4 interface */ +static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = { { - .name = "mpu", - .pa_start = 0x49024000, - .pa_end = 0x490240ff, - .flags = ADDR_TYPE_RT + .pa_start = OMAP3_UART4_AM35XX_BASE, + .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1, + .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, }, - { } }; -/* l4_per -> mcbsp3 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_mcbsp3_hwmod, - .clk = "mcbsp3_ick", - .addr = omap3xxx_mcbsp3_addrs, +static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &am35xx_uart4_hwmod, + .clk = "uart4_ick", + .addr = am35xx_uart4_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = { - .sidetone = "mcbsp3_sidetone", +/* L4 CORE -> I2C1 interface */ +static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_i2c1_hwmod, + .clk = "i2c1_ick", + .addr = omap2_i2c1_addr_space, + .fw = { + .omap2 = { + .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION, + .l4_prot_group = 7, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { - .name = "mcbsp3", - .class = &omap3xxx_mcbsp_hwmod_class, - .mpu_irqs = omap3xxx_mcbsp3_irqs, - .sdma_reqs = omap2_mcbsp3_sdma_reqs, - .main_clk = "mcbsp3_fck", - .prcm = { +/* L4 CORE -> I2C2 interface */ +static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_i2c2_hwmod, + .clk = "i2c2_ick", + .addr = omap2_i2c2_addr_space, + .fw = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_MCBSP3_SHIFT, - .module_offs = OMAP3430_PER_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, - }, + .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION, + .l4_prot_group = 7, + .flags = OMAP_FIREWALL_L4, + } }, - .dev_attr = &omap34xx_mcbsp3_dev_attr, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* mcbsp4 */ -static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = { - { .name = "irq", .irq = 23 }, - { .name = "tx", .irq = 54 }, - { .name = "rx", .irq = 55 }, - { .irq = -1 } +/* L4 CORE -> I2C3 interface */ +static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = { + { + .pa_start = 0x48060000, + .pa_end = 0x48060000 + SZ_128 - 1, + .flags = ADDR_TYPE_RT, + }, + { } }; -static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = { - { .name = "rx", .dma_req = 20 }, - { .name = "tx", .dma_req = 19 }, - { .dma_req = -1 } +static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_i2c3_hwmod, + .clk = "i2c3_ick", + .addr = omap3xxx_i2c3_addr_space, + .fw = { + .omap2 = { + .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION, + .l4_prot_group = 7, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = { +/* L4 CORE -> SR1 interface */ +static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = { { - .name = "mpu", - .pa_start = 0x49026000, - .pa_end = 0x490260ff, - .flags = ADDR_TYPE_RT + .pa_start = OMAP34XX_SR1_BASE, + .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1, + .flags = ADDR_TYPE_RT, }, { } }; -/* l4_per -> mcbsp4 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_mcbsp4_hwmod, - .clk = "mcbsp4_ick", - .addr = omap3xxx_mcbsp4_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap34xx_sr1_hwmod, + .clk = "sr_l4_ick", + .addr = omap3_sr1_addr_space, + .user = OCP_USER_MPU, }; -static struct omap_hwmod omap3xxx_mcbsp4_hwmod = { - .name = "mcbsp4", - .class = &omap3xxx_mcbsp_hwmod_class, - .mpu_irqs = omap3xxx_mcbsp4_irqs, - .sdma_reqs = omap3xxx_mcbsp4_sdma_chs, - .main_clk = "mcbsp4_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_MCBSP4_SHIFT, - .module_offs = OMAP3430_PER_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT, - }, +static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap36xx_sr1_hwmod, + .clk = "sr_l4_ick", + .addr = omap3_sr1_addr_space, + .user = OCP_USER_MPU, +}; + +/* L4 CORE -> SR1 interface */ +static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = { + { + .pa_start = OMAP34XX_SR2_BASE, + .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1, + .flags = ADDR_TYPE_RT, }, + { } }; -/* mcbsp5 */ -static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = { - { .name = "irq", .irq = 27 }, - { .name = "tx", .irq = 81 }, - { .name = "rx", .irq = 82 }, - { .irq = -1 } +static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap34xx_sr2_hwmod, + .clk = "sr_l4_ick", + .addr = omap3_sr2_addr_space, + .user = OCP_USER_MPU, }; -static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = { - { .name = "rx", .dma_req = 22 }, - { .name = "tx", .dma_req = 21 }, - { .dma_req = -1 } +static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap36xx_sr2_hwmod, + .clk = "sr_l4_ick", + .addr = omap3_sr2_addr_space, + .user = OCP_USER_MPU, }; -static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = { +static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = { { - .name = "mpu", - .pa_start = 0x48096000, - .pa_end = 0x480960ff, + .pa_start = OMAP34XX_HSUSB_OTG_BASE, + .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1, .flags = ADDR_TYPE_RT }, { } }; -/* l4_core -> mcbsp5 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = { +/* l4_core -> usbhsotg */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = { .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_mcbsp5_hwmod, - .clk = "mcbsp5_ick", - .addr = omap3xxx_mcbsp5_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, + .slave = &omap3xxx_usbhsotg_hwmod, + .clk = "l4_ick", + .addr = omap3xxx_usbhsotg_addrs, + .user = OCP_USER_MPU, }; -static struct omap_hwmod omap3xxx_mcbsp5_hwmod = { - .name = "mcbsp5", - .class = &omap3xxx_mcbsp_hwmod_class, - .mpu_irqs = omap3xxx_mcbsp5_irqs, - .sdma_reqs = omap3xxx_mcbsp5_sdma_chs, - .main_clk = "mcbsp5_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_MCBSP5_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT, - }, +static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = { + { + .pa_start = AM35XX_IPSS_USBOTGSS_BASE, + .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1, + .flags = ADDR_TYPE_RT }, + { } }; -/* 'mcbsp sidetone' class */ -static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = { - .sysc_offs = 0x0010, - .sysc_flags = SYSC_HAS_AUTOIDLE, - .sysc_fields = &omap_hwmod_sysc_type1, +/* l4_core -> usbhsotg */ +static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &am35xx_usbhsotg_hwmod, + .clk = "l4_ick", + .addr = am35xx_usbhsotg_addrs, + .user = OCP_USER_MPU, }; -static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = { - .name = "mcbsp_sidetone", - .sysc = &omap3xxx_mcbsp_sidetone_sysc, +/* L4_WKUP -> L4_SEC interface */ +static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = { + .master = &omap3xxx_l4_wkup_hwmod, + .slave = &omap3xxx_l4_sec_hwmod, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* mcbsp2_sidetone */ -static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = { - { .name = "irq", .irq = 4 }, - { .irq = -1 } +/* IVA2 <- L3 interface */ +static struct omap_hwmod_ocp_if omap3xxx_l3__iva = { + .master = &omap3xxx_l3_main_hwmod, + .slave = &omap3xxx_iva_hwmod, + .clk = "iva2_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = { +static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = { { - .name = "sidetone", - .pa_start = 0x49028000, - .pa_end = 0x490280ff, + .pa_start = 0x48318000, + .pa_end = 0x48318000 + SZ_1K - 1, .flags = ADDR_TYPE_RT }, { } }; -/* l4_per -> mcbsp2_sidetone */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_mcbsp2_sidetone_hwmod, - .clk = "mcbsp2_ick", - .addr = omap3xxx_mcbsp2_sidetone_addrs, - .user = OCP_USER_MPU, +/* l4_wkup -> timer1 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = { + .master = &omap3xxx_l4_wkup_hwmod, + .slave = &omap3xxx_timer1_hwmod, + .clk = "gpt1_ick", + .addr = omap3xxx_timer1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { - .name = "mcbsp2_sidetone", - .class = &omap3xxx_mcbsp_sidetone_hwmod_class, - .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs, - .main_clk = "mcbsp2_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_MCBSP2_SHIFT, - .module_offs = OMAP3430_PER_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, - }, +static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = { + { + .pa_start = 0x49032000, + .pa_end = 0x49032000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT }, + { } }; -/* mcbsp3_sidetone */ -static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = { - { .name = "irq", .irq = 5 }, - { .irq = -1 } +/* l4_per -> timer2 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_timer2_hwmod, + .clk = "gpt2_ick", + .addr = omap3xxx_timer2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = { +static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = { { - .name = "sidetone", - .pa_start = 0x4902A000, - .pa_end = 0x4902A0ff, + .pa_start = 0x49034000, + .pa_end = 0x49034000 + SZ_1K - 1, .flags = ADDR_TYPE_RT }, { } }; -/* l4_per -> mcbsp3_sidetone */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = { +/* l4_per -> timer3 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = { .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_mcbsp3_sidetone_hwmod, - .clk = "mcbsp3_ick", - .addr = omap3xxx_mcbsp3_sidetone_addrs, - .user = OCP_USER_MPU, + .slave = &omap3xxx_timer3_hwmod, + .clk = "gpt3_ick", + .addr = omap3xxx_timer3_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = { - .name = "mcbsp3_sidetone", - .class = &omap3xxx_mcbsp_sidetone_hwmod_class, - .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs, - .main_clk = "mcbsp3_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_MCBSP3_SHIFT, - .module_offs = OMAP3430_PER_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, - }, +static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = { + { + .pa_start = 0x49036000, + .pa_end = 0x49036000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT }, + { } }; - -/* SR common */ -static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = { - .clkact_shift = 20, -}; - -static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = { - .sysc_offs = 0x24, - .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE), - .clockact = CLOCKACT_TEST_ICLK, - .sysc_fields = &omap34xx_sr_sysc_fields, -}; - -static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = { - .name = "smartreflex", - .sysc = &omap34xx_sr_sysc, - .rev = 1, -}; - -static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = { - .sidle_shift = 24, - .enwkup_shift = 26 +/* l4_per -> timer4 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_timer4_hwmod, + .clk = "gpt4_ick", + .addr = omap3xxx_timer4_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = { - .sysc_offs = 0x38, - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | - SYSC_NO_CACHE), - .sysc_fields = &omap36xx_sr_sysc_fields, +static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = { + { + .pa_start = 0x49038000, + .pa_end = 0x49038000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + { } }; -static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = { - .name = "smartreflex", - .sysc = &omap36xx_sr_sysc, - .rev = 2, +/* l4_per -> timer5 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_timer5_hwmod, + .clk = "gpt5_ick", + .addr = omap3xxx_timer5_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* SR1 */ -static struct omap_smartreflex_dev_attr sr1_dev_attr = { - .sensor_voltdm_name = "mpu_iva", +static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = { + { + .pa_start = 0x4903A000, + .pa_end = 0x4903A000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + { } }; -static struct omap_hwmod omap34xx_sr1_hwmod = { - .name = "sr1", - .class = &omap34xx_smartreflex_hwmod_class, - .main_clk = "sr1_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_SR1_SHIFT, - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, - }, - }, - .dev_attr = &sr1_dev_attr, - .mpu_irqs = omap3_smartreflex_mpu_irqs, - .flags = HWMOD_SET_DEFAULT_CLOCKACT, +/* l4_per -> timer6 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_timer6_hwmod, + .clk = "gpt6_ick", + .addr = omap3xxx_timer6_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod omap36xx_sr1_hwmod = { - .name = "sr1", - .class = &omap36xx_smartreflex_hwmod_class, - .main_clk = "sr1_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_SR1_SHIFT, - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, - }, +static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = { + { + .pa_start = 0x4903C000, + .pa_end = 0x4903C000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT }, - .dev_attr = &sr1_dev_attr, - .mpu_irqs = omap3_smartreflex_mpu_irqs, + { } }; -/* SR2 */ -static struct omap_smartreflex_dev_attr sr2_dev_attr = { - .sensor_voltdm_name = "core", +/* l4_per -> timer7 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_timer7_hwmod, + .clk = "gpt7_ick", + .addr = omap3xxx_timer7_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod omap34xx_sr2_hwmod = { - .name = "sr2", - .class = &omap34xx_smartreflex_hwmod_class, - .main_clk = "sr2_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_SR2_SHIFT, - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, - }, +static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = { + { + .pa_start = 0x4903E000, + .pa_end = 0x4903E000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT }, - .dev_attr = &sr2_dev_attr, - .mpu_irqs = omap3_smartreflex_core_irqs, - .flags = HWMOD_SET_DEFAULT_CLOCKACT, + { } }; -static struct omap_hwmod omap36xx_sr2_hwmod = { - .name = "sr2", - .class = &omap36xx_smartreflex_hwmod_class, - .main_clk = "sr2_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_SR2_SHIFT, - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, - }, - }, - .dev_attr = &sr2_dev_attr, - .mpu_irqs = omap3_smartreflex_core_irqs, +/* l4_per -> timer8 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_timer8_hwmod, + .clk = "gpt8_ick", + .addr = omap3xxx_timer8_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* - * 'mailbox' class - * mailbox module allowing communication between the on-chip processors - * using a queued mailbox-interrupt mechanism. - */ +static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = { + { + .pa_start = 0x49040000, + .pa_end = 0x49040000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; -static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = { - .rev_offs = 0x000, - .sysc_offs = 0x010, - .syss_offs = 0x014, - .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, +/* l4_per -> timer9 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_timer9_hwmod, + .clk = "gpt9_ick", + .addr = omap3xxx_timer9_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = { - .name = "mailbox", - .sysc = &omap3xxx_mailbox_sysc, +/* l4_core -> timer10 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_timer10_hwmod, + .clk = "gpt10_ick", + .addr = omap2_timer10_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod omap3xxx_mailbox_hwmod; -static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = { - { .irq = 26 }, - { .irq = -1 } +/* l4_core -> timer11 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_timer11_hwmod, + .clk = "gpt11_ick", + .addr = omap2_timer11_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = { +static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = { { - .pa_start = 0x48094000, - .pa_end = 0x480941ff, - .flags = ADDR_TYPE_RT, + .pa_start = 0x48304000, + .pa_end = 0x48304000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT }, { } }; -/* l4_core -> mailbox */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_mailbox_hwmod, - .addr = omap3xxx_mailbox_addrs, +/* l4_core -> timer12 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = { + .master = &omap3xxx_l4_sec_hwmod, + .slave = &omap3xxx_timer12_hwmod, + .clk = "gpt12_ick", + .addr = omap3xxx_timer12_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod omap3xxx_mailbox_hwmod = { - .name = "mailbox", - .class = &omap3xxx_mailbox_hwmod_class, - .mpu_irqs = omap3xxx_mailbox_irqs, - .main_clk = "mailboxes_ick", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_MAILBOXES_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT, - }, +/* l4_wkup -> wd_timer2 */ +static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = { + { + .pa_start = 0x48314000, + .pa_end = 0x4831407f, + .flags = ADDR_TYPE_RT }, + { } }; -/* l4 core -> mcspi1 interface */ -static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = { +static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = { + .master = &omap3xxx_l4_wkup_hwmod, + .slave = &omap3xxx_wd_timer2_hwmod, + .clk = "wdt2_ick", + .addr = omap3xxx_wd_timer2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> dss */ +static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = { .master = &omap3xxx_l4_core_hwmod, - .slave = &omap34xx_mcspi1, - .clk = "mcspi1_ick", - .addr = omap2_mcspi1_addr_space, + .slave = &omap3430es1_dss_core_hwmod, + .clk = "dss_ick", + .addr = omap2_dss_addrs, + .fw = { + .omap2 = { + .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION, + .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, + .flags = OMAP_FIREWALL_L4, + } + }, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4 core -> mcspi2 interface */ -static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = { +static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = { .master = &omap3xxx_l4_core_hwmod, - .slave = &omap34xx_mcspi2, - .clk = "mcspi2_ick", - .addr = omap2_mcspi2_addr_space, + .slave = &omap3xxx_dss_core_hwmod, + .clk = "dss_ick", + .addr = omap2_dss_addrs, + .fw = { + .omap2 = { + .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION, + .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, + .flags = OMAP_FIREWALL_L4, + } + }, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4 core -> mcspi3 interface */ -static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = { +/* l4_core -> dss_dispc */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = { .master = &omap3xxx_l4_core_hwmod, - .slave = &omap34xx_mcspi3, - .clk = "mcspi3_ick", - .addr = omap2430_mcspi3_addr_space, + .slave = &omap3xxx_dss_dispc_hwmod, + .clk = "dss_ick", + .addr = omap2_dss_dispc_addrs, + .fw = { + .omap2 = { + .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION, + .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, + .flags = OMAP_FIREWALL_L4, + } + }, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4 core -> mcspi4 interface */ -static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = { +static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = { { - .pa_start = 0x480ba000, - .pa_end = 0x480ba0ff, - .flags = ADDR_TYPE_RT, + .pa_start = 0x4804FC00, + .pa_end = 0x4804FFFF, + .flags = ADDR_TYPE_RT }, { } }; -static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = { +/* l4_core -> dss_dsi1 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = { .master = &omap3xxx_l4_core_hwmod, - .slave = &omap34xx_mcspi4, - .clk = "mcspi4_ick", - .addr = omap34xx_mcspi4_addr_space, + .slave = &omap3xxx_dss_dsi1_hwmod, + .clk = "dss_ick", + .addr = omap3xxx_dss_dsi1_addrs, + .fw = { + .omap2 = { + .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION, + .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, + .flags = OMAP_FIREWALL_L4, + } + }, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* - * 'mcspi' class - * multichannel serial port interface (mcspi) / master/slave synchronous serial - * bus - */ - -static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | - SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | - SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class omap34xx_mcspi_class = { - .name = "mcspi", - .sysc = &omap34xx_mcspi_sysc, - .rev = OMAP3_MCSPI_REV, -}; - -/* mcspi1 */ -static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { - .num_chipselect = 4, -}; - -static struct omap_hwmod omap34xx_mcspi1 = { - .name = "mcspi1", - .mpu_irqs = omap2_mcspi1_mpu_irqs, - .sdma_reqs = omap2_mcspi1_sdma_reqs, - .main_clk = "mcspi1_fck", - .prcm = { +/* l4_core -> dss_rfbi */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_dss_rfbi_hwmod, + .clk = "dss_ick", + .addr = omap2_dss_rfbi_addrs, + .fw = { .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_MCSPI1_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT, - }, + .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION, + .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP , + .flags = OMAP_FIREWALL_L4, + } }, - .class = &omap34xx_mcspi_class, - .dev_attr = &omap_mcspi1_dev_attr, -}; - -/* mcspi2 */ -static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { - .num_chipselect = 2, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod omap34xx_mcspi2 = { - .name = "mcspi2", - .mpu_irqs = omap2_mcspi2_mpu_irqs, - .sdma_reqs = omap2_mcspi2_sdma_reqs, - .main_clk = "mcspi2_fck", - .prcm = { +/* l4_core -> dss_venc */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_dss_venc_hwmod, + .clk = "dss_ick", + .addr = omap2_dss_venc_addrs, + .fw = { .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_MCSPI2_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT, - }, + .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION, + .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, + .flags = OMAP_FIREWALL_L4, + } }, - .class = &omap34xx_mcspi_class, - .dev_attr = &omap_mcspi2_dev_attr, -}; - -/* mcspi3 */ -static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = { - { .name = "irq", .irq = 91 }, /* 91 */ - { .irq = -1 } + .flags = OCPIF_SWSUP_IDLE, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = { - { .name = "tx0", .dma_req = 15 }, - { .name = "rx0", .dma_req = 16 }, - { .name = "tx1", .dma_req = 23 }, - { .name = "rx1", .dma_req = 24 }, - { .dma_req = -1 } +/* l4_wkup -> gpio1 */ +static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = { + { + .pa_start = 0x48310000, + .pa_end = 0x483101ff, + .flags = ADDR_TYPE_RT + }, + { } }; -static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { - .num_chipselect = 2, +static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = { + .master = &omap3xxx_l4_wkup_hwmod, + .slave = &omap3xxx_gpio1_hwmod, + .addr = omap3xxx_gpio1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod omap34xx_mcspi3 = { - .name = "mcspi3", - .mpu_irqs = omap34xx_mcspi3_mpu_irqs, - .sdma_reqs = omap34xx_mcspi3_sdma_reqs, - .main_clk = "mcspi3_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_MCSPI3_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT, - }, +/* l4_per -> gpio2 */ +static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = { + { + .pa_start = 0x49050000, + .pa_end = 0x490501ff, + .flags = ADDR_TYPE_RT }, - .class = &omap34xx_mcspi_class, - .dev_attr = &omap_mcspi3_dev_attr, + { } }; -/* SPI4 */ -static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = { - { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */ - { .irq = -1 } +static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_gpio2_hwmod, + .addr = omap3xxx_gpio2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = { - { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */ - { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */ - { .dma_req = -1 } +/* l4_per -> gpio3 */ +static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = { + { + .pa_start = 0x49052000, + .pa_end = 0x490521ff, + .flags = ADDR_TYPE_RT + }, + { } }; -static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = { - .num_chipselect = 1, +static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_gpio3_hwmod, + .addr = omap3xxx_gpio3_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod omap34xx_mcspi4 = { - .name = "mcspi4", - .mpu_irqs = omap34xx_mcspi4_mpu_irqs, - .sdma_reqs = omap34xx_mcspi4_sdma_reqs, - .main_clk = "mcspi4_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_MCSPI4_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT, - }, +/* l4_per -> gpio4 */ +static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = { + { + .pa_start = 0x49054000, + .pa_end = 0x490541ff, + .flags = ADDR_TYPE_RT }, - .class = &omap34xx_mcspi_class, - .dev_attr = &omap_mcspi4_dev_attr, + { } }; -/* - * usbhsotg - */ -static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = { - .rev_offs = 0x0400, - .sysc_offs = 0x0404, - .syss_offs = 0x0408, - .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| - SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | - SYSC_HAS_AUTOIDLE), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, +static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_gpio4_hwmod, + .addr = omap3xxx_gpio4_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_class usbotg_class = { - .name = "usbotg", - .sysc = &omap3xxx_usbhsotg_sysc, +/* l4_per -> gpio5 */ +static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = { + { + .pa_start = 0x49056000, + .pa_end = 0x490561ff, + .flags = ADDR_TYPE_RT + }, + { } }; -/* usb_otg_hs */ -static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = { - { .name = "mc", .irq = 92 }, - { .name = "dma", .irq = 93 }, - { .irq = -1 } +static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_gpio5_hwmod, + .addr = omap3xxx_gpio5_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { - .name = "usb_otg_hs", - .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs, - .main_clk = "hsotgusb_ick", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT, - .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT - }, +/* l4_per -> gpio6 */ +static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = { + { + .pa_start = 0x49058000, + .pa_end = 0x490581ff, + .flags = ADDR_TYPE_RT }, - .class = &usbotg_class, - - /* - * Erratum ID: i479 idle_req / idle_ack mechanism potentially - * broken when autoidle is enabled - * workaround is to disable the autoidle bit at module level. - */ - .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE - | HWMOD_SWSUP_MSTANDBY, + { } }; -/* usb_otg_hs */ -static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = { - - { .name = "mc", .irq = 71 }, - { .irq = -1 } +static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_gpio6_hwmod, + .addr = omap3xxx_gpio6_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_class am35xx_usbotg_class = { - .name = "am35xx_usbotg", - .sysc = NULL, +/* dma_system -> L3 */ +static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = { + .master = &omap3xxx_dma_system_hwmod, + .slave = &omap3xxx_l3_main_hwmod, + .clk = "core_l3_ick", + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod am35xx_usbhsotg_hwmod = { - .name = "am35x_otg_hs", - .mpu_irqs = am35xx_usbhsotg_mpu_irqs, - .main_clk = NULL, - .prcm = { - .omap2 = { - }, +static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = { + { + .pa_start = 0x48056000, + .pa_end = 0x48056fff, + .flags = ADDR_TYPE_RT }, - .class = &am35xx_usbotg_class, + { } }; -/* MMC/SD/SDIO common */ - -static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = { - .rev_offs = 0x1fc, - .sysc_offs = 0x10, - .syss_offs = 0x14, - .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | - SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | - SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, +/* l4_cfg -> dma_system */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_dma_system_hwmod, + .clk = "core_l4_ick", + .addr = omap3xxx_dma_system_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_class omap34xx_mmc_class = { - .name = "mmc", - .sysc = &omap34xx_mmc_sysc, +static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = { + { + .name = "mpu", + .pa_start = 0x48074000, + .pa_end = 0x480740ff, + .flags = ADDR_TYPE_RT + }, + { } }; -/* MMC/SD/SDIO1 */ - -static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = { - { .irq = 83, }, - { .irq = -1 } +/* l4_core -> mcbsp1 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_mcbsp1_hwmod, + .clk = "mcbsp1_ick", + .addr = omap3xxx_mcbsp1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = { - { .name = "tx", .dma_req = 61, }, - { .name = "rx", .dma_req = 62, }, - { .dma_req = -1 } +static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = { + { + .name = "mpu", + .pa_start = 0x49022000, + .pa_end = 0x490220ff, + .flags = ADDR_TYPE_RT + }, + { } }; -static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = { - { .role = "dbck", .clk = "omap_32k_fck", }, +/* l4_per -> mcbsp2 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_mcbsp2_hwmod, + .clk = "mcbsp2_ick", + .addr = omap3xxx_mcbsp2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_mmc_dev_attr mmc1_dev_attr = { - .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, +static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = { + { + .name = "mpu", + .pa_start = 0x49024000, + .pa_end = 0x490240ff, + .flags = ADDR_TYPE_RT + }, + { } }; -/* See 35xx errata 2.1.1.128 in SPRZ278F */ -static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = { - .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT | - OMAP_HSMMC_BROKEN_MULTIBLOCK_READ), +/* l4_per -> mcbsp3 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_mcbsp3_hwmod, + .clk = "mcbsp3_ick", + .addr = omap3xxx_mcbsp3_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = { - .name = "mmc1", - .mpu_irqs = omap34xx_mmc1_mpu_irqs, - .sdma_reqs = omap34xx_mmc1_sdma_reqs, - .opt_clks = omap34xx_mmc1_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), - .main_clk = "mmchs1_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_MMC1_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, - }, +static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = { + { + .name = "mpu", + .pa_start = 0x49026000, + .pa_end = 0x490260ff, + .flags = ADDR_TYPE_RT }, - .dev_attr = &mmc1_pre_es3_dev_attr, - .class = &omap34xx_mmc_class, + { } }; -static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = { - .name = "mmc1", - .mpu_irqs = omap34xx_mmc1_mpu_irqs, - .sdma_reqs = omap34xx_mmc1_sdma_reqs, - .opt_clks = omap34xx_mmc1_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), - .main_clk = "mmchs1_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_MMC1_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, - }, - }, - .dev_attr = &mmc1_dev_attr, - .class = &omap34xx_mmc_class, +/* l4_per -> mcbsp4 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_mcbsp4_hwmod, + .clk = "mcbsp4_ick", + .addr = omap3xxx_mcbsp4_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* MMC/SD/SDIO2 */ +static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = { + { + .name = "mpu", + .pa_start = 0x48096000, + .pa_end = 0x480960ff, + .flags = ADDR_TYPE_RT + }, + { } +}; -static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = { - { .irq = INT_24XX_MMC2_IRQ, }, - { .irq = -1 } +/* l4_core -> mcbsp5 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_mcbsp5_hwmod, + .clk = "mcbsp5_ick", + .addr = omap3xxx_mcbsp5_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = { - { .name = "tx", .dma_req = 47, }, - { .name = "rx", .dma_req = 48, }, - { .dma_req = -1 } +static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = { + { + .name = "sidetone", + .pa_start = 0x49028000, + .pa_end = 0x490280ff, + .flags = ADDR_TYPE_RT + }, + { } }; -static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = { - { .role = "dbck", .clk = "omap_32k_fck", }, +/* l4_per -> mcbsp2_sidetone */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_mcbsp2_sidetone_hwmod, + .clk = "mcbsp2_ick", + .addr = omap3xxx_mcbsp2_sidetone_addrs, + .user = OCP_USER_MPU, }; -/* See 35xx errata 2.1.1.128 in SPRZ278F */ -static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = { - .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, +static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = { + { + .name = "sidetone", + .pa_start = 0x4902A000, + .pa_end = 0x4902A0ff, + .flags = ADDR_TYPE_RT + }, + { } }; -static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = { - .name = "mmc2", - .mpu_irqs = omap34xx_mmc2_mpu_irqs, - .sdma_reqs = omap34xx_mmc2_sdma_reqs, - .opt_clks = omap34xx_mmc2_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), - .main_clk = "mmchs2_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_MMC2_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, - }, - }, - .dev_attr = &mmc2_pre_es3_dev_attr, - .class = &omap34xx_mmc_class, +/* l4_per -> mcbsp3_sidetone */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_mcbsp3_sidetone_hwmod, + .clk = "mcbsp3_ick", + .addr = omap3xxx_mcbsp3_sidetone_addrs, + .user = OCP_USER_MPU, }; -static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = { - .name = "mmc2", - .mpu_irqs = omap34xx_mmc2_mpu_irqs, - .sdma_reqs = omap34xx_mmc2_sdma_reqs, - .opt_clks = omap34xx_mmc2_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), - .main_clk = "mmchs2_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_MMC2_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, - }, +static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = { + { + .pa_start = 0x48094000, + .pa_end = 0x480941ff, + .flags = ADDR_TYPE_RT, }, - .class = &omap34xx_mmc_class, + { } }; -/* MMC/SD/SDIO3 */ +/* l4_core -> mailbox */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_mailbox_hwmod, + .addr = omap3xxx_mailbox_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; -static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = { - { .irq = 94, }, - { .irq = -1 } +/* l4 core -> mcspi1 interface */ +static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap34xx_mcspi1, + .clk = "mcspi1_ick", + .addr = omap2_mcspi1_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = { - { .name = "tx", .dma_req = 77, }, - { .name = "rx", .dma_req = 78, }, - { .dma_req = -1 } +/* l4 core -> mcspi2 interface */ +static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap34xx_mcspi2, + .clk = "mcspi2_ick", + .addr = omap2_mcspi2_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = { - { .role = "dbck", .clk = "omap_32k_fck", }, +/* l4 core -> mcspi3 interface */ +static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap34xx_mcspi3, + .clk = "mcspi3_ick", + .addr = omap2430_mcspi3_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod omap3xxx_mmc3_hwmod = { - .name = "mmc3", - .mpu_irqs = omap34xx_mmc3_mpu_irqs, - .sdma_reqs = omap34xx_mmc3_sdma_reqs, - .opt_clks = omap34xx_mmc3_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks), - .main_clk = "mmchs3_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_MMC3_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT, - }, +/* l4 core -> mcspi4 interface */ +static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = { + { + .pa_start = 0x480ba000, + .pa_end = 0x480ba0ff, + .flags = ADDR_TYPE_RT, }, - .class = &omap34xx_mmc_class, + { } +}; + +static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap34xx_mcspi4, + .clk = "mcspi4_ick", + .addr = omap34xx_mcspi4_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* - * 'usb_host_hs' class - * high-speed multi-port usb host controller - */ static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = { .master = &omap3xxx_usb_host_hs_hwmod, .slave = &omap3xxx_l3_main_hwmod, @@ -2952,23 +3003,6 @@ static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = { .user = OCP_USER_MPU, }; -static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | - SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | - SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = { - .name = "usb_host_hs", - .sysc = &omap3xxx_usb_host_hs_sysc, -}; - static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = { { .name = "uhh", @@ -2997,109 +3031,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = { - { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", }, -}; - -static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = { - { .name = "ohci-irq", .irq = 76 }, - { .name = "ehci-irq", .irq = 77 }, - { .irq = -1 } -}; - -static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = { - .name = "usb_host_hs", - .class = &omap3xxx_usb_host_hs_hwmod_class, - .clkdm_name = "l3_init_clkdm", - .mpu_irqs = omap3xxx_usb_host_hs_irqs, - .main_clk = "usbhost_48m_fck", - .prcm = { - .omap2 = { - .module_offs = OMAP3430ES2_USBHOST_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT, - .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT, - }, - }, - .opt_clks = omap3xxx_usb_host_hs_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks), - - /* - * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock - * id: i660 - * - * Description: - * In the following configuration : - * - USBHOST module is set to smart-idle mode - * - PRCM asserts idle_req to the USBHOST module ( This typically - * happens when the system is going to a low power mode : all ports - * have been suspended, the master part of the USBHOST module has - * entered the standby state, and SW has cut the functional clocks) - * - an USBHOST interrupt occurs before the module is able to answer - * idle_ack, typically a remote wakeup IRQ. - * Then the USB HOST module will enter a deadlock situation where it - * is no more accessible nor functional. - * - * Workaround: - * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE - */ - - /* - * Errata: USB host EHCI may stall when entering smart-standby mode - * Id: i571 - * - * Description: - * When the USBHOST module is set to smart-standby mode, and when it is - * ready to enter the standby state (i.e. all ports are suspended and - * all attached devices are in suspend mode), then it can wrongly assert - * the Mstandby signal too early while there are still some residual OCP - * transactions ongoing. If this condition occurs, the internal state - * machine may go to an undefined state and the USB link may be stuck - * upon the next resume. - * - * Workaround: - * Don't use smart standby; use only force standby, - * hence HWMOD_SWSUP_MSTANDBY - */ - - /* - * During system boot; If the hwmod framework resets the module - * the module will have smart idle settings; which can lead to deadlock - * (above Errata Id:i660); so, dont reset the module during boot; - * Use HWMOD_INIT_NO_RESET. - */ - - .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY | - HWMOD_INIT_NO_RESET, -}; - -/* - * 'usb_tll_hs' class - * usb_tll_hs module is the adapter on the usb_host_hs ports - */ -static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | - SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | - SYSC_HAS_AUTOIDLE), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = { - .name = "usb_tll_hs", - .sysc = &omap3xxx_usb_tll_hs_sysc, -}; - -static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = { - { .name = "tll-irq", .irq = 78 }, - { .irq = -1 } -}; - static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = { { .name = "tll", @@ -3118,23 +3049,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = { - .name = "usb_tll_hs", - .class = &omap3xxx_usb_tll_hs_hwmod_class, - .clkdm_name = "l3_init_clkdm", - .mpu_irqs = omap3xxx_usb_tll_hs_irqs, - .main_clk = "usbtll_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 3, - .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT, - .idlest_reg_id = 3, - .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT, - }, - }, -}; - static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = { &omap3xxx_l3_main__l4_core, &omap3xxx_l3_main__l4_per, diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 6bde469b3df2..0d91dec5b4bc 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -44,38 +44,10 @@ #define OMAP44XX_IRQ_GIC_START 32 /* Base offset for all OMAP4 dma requests */ -#define OMAP44XX_DMA_REQ_START 1 - -/* Backward references (IPs with Bus Master capability) */ -static struct omap_hwmod omap44xx_aess_hwmod; -static struct omap_hwmod omap44xx_dma_system_hwmod; -static struct omap_hwmod omap44xx_dmm_hwmod; -static struct omap_hwmod omap44xx_dsp_hwmod; -static struct omap_hwmod omap44xx_dss_hwmod; -static struct omap_hwmod omap44xx_emif_fw_hwmod; -static struct omap_hwmod omap44xx_hsi_hwmod; -static struct omap_hwmod omap44xx_ipu_hwmod; -static struct omap_hwmod omap44xx_iss_hwmod; -static struct omap_hwmod omap44xx_iva_hwmod; -static struct omap_hwmod omap44xx_l3_instr_hwmod; -static struct omap_hwmod omap44xx_l3_main_1_hwmod; -static struct omap_hwmod omap44xx_l3_main_2_hwmod; -static struct omap_hwmod omap44xx_l3_main_3_hwmod; -static struct omap_hwmod omap44xx_l4_abe_hwmod; -static struct omap_hwmod omap44xx_l4_cfg_hwmod; -static struct omap_hwmod omap44xx_l4_per_hwmod; -static struct omap_hwmod omap44xx_l4_wkup_hwmod; -static struct omap_hwmod omap44xx_mmc1_hwmod; -static struct omap_hwmod omap44xx_mmc2_hwmod; -static struct omap_hwmod omap44xx_mpu_hwmod; -static struct omap_hwmod omap44xx_mpu_private_hwmod; -static struct omap_hwmod omap44xx_usb_otg_hs_hwmod; -static struct omap_hwmod omap44xx_usb_host_hs_hwmod; -static struct omap_hwmod omap44xx_usb_tll_hs_hwmod; +#define OMAP44XX_DMA_REQ_START 1 /* - * Interconnects omap_hwmod structures - * hwmods that compose the global OMAP interconnect + * IP blocks */ /* @@ -92,43 +64,17 @@ static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = { { .irq = -1 } }; -/* l3_main_1 -> dmm */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = { - .master = &omap44xx_l3_main_1_hwmod, - .slave = &omap44xx_dmm_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = { - { - .pa_start = 0x4e000000, - .pa_end = 0x4e0007ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* mpu -> dmm */ -static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = { - .master = &omap44xx_mpu_hwmod, - .slave = &omap44xx_dmm_hwmod, - .clk = "l3_div_ck", - .addr = omap44xx_dmm_addrs, - .user = OCP_USER_MPU, -}; - static struct omap_hwmod omap44xx_dmm_hwmod = { .name = "dmm", .class = &omap44xx_dmm_hwmod_class, .clkdm_name = "l3_emif_clkdm", + .mpu_irqs = omap44xx_dmm_irqs, .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET, }, }, - .mpu_irqs = omap44xx_dmm_irqs, }; /* @@ -140,32 +86,6 @@ static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = { }; /* emif_fw */ -/* dmm -> emif_fw */ -static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = { - .master = &omap44xx_dmm_hwmod, - .slave = &omap44xx_emif_fw_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = { - { - .pa_start = 0x4a20c000, - .pa_end = 0x4a20c0ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_cfg -> emif_fw */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_emif_fw_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_emif_fw_addrs, - .user = OCP_USER_MPU, -}; - static struct omap_hwmod omap44xx_emif_fw_hwmod = { .name = "emif_fw", .class = &omap44xx_emif_fw_hwmod_class, @@ -187,22 +107,6 @@ static struct omap_hwmod_class omap44xx_l3_hwmod_class = { }; /* l3_instr */ -/* iva -> l3_instr */ -static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = { - .master = &omap44xx_iva_hwmod, - .slave = &omap44xx_l3_instr_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l3_main_3 -> l3_instr */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = { - .master = &omap44xx_l3_main_3_hwmod, - .slave = &omap44xx_l3_instr_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap44xx_l3_instr_hwmod = { .name = "l3_instr", .class = &omap44xx_l3_hwmod_class, @@ -223,72 +127,6 @@ static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = { { .irq = -1 } }; -/* dsp -> l3_main_1 */ -static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = { - .master = &omap44xx_dsp_hwmod, - .slave = &omap44xx_l3_main_1_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* dss -> l3_main_1 */ -static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = { - .master = &omap44xx_dss_hwmod, - .slave = &omap44xx_l3_main_1_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l3_main_2 -> l3_main_1 */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_l3_main_1_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_cfg -> l3_main_1 */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_l3_main_1_hwmod, - .clk = "l4_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mmc1 -> l3_main_1 */ -static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = { - .master = &omap44xx_mmc1_hwmod, - .slave = &omap44xx_l3_main_1_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mmc2 -> l3_main_1 */ -static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = { - .master = &omap44xx_mmc2_hwmod, - .slave = &omap44xx_l3_main_1_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = { - { - .pa_start = 0x44000000, - .pa_end = 0x44000fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* mpu -> l3_main_1 */ -static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { - .master = &omap44xx_mpu_hwmod, - .slave = &omap44xx_l3_main_1_hwmod, - .clk = "l3_div_ck", - .addr = omap44xx_l3_main_1_addrs, - .user = OCP_USER_MPU, -}; - static struct omap_hwmod omap44xx_l3_main_1_hwmod = { .name = "l3_main_1", .class = &omap44xx_l3_hwmod_class, @@ -303,80 +141,6 @@ static struct omap_hwmod omap44xx_l3_main_1_hwmod = { }; /* l3_main_2 */ -/* dma_system -> l3_main_2 */ -static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = { - .master = &omap44xx_dma_system_hwmod, - .slave = &omap44xx_l3_main_2_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* hsi -> l3_main_2 */ -static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = { - .master = &omap44xx_hsi_hwmod, - .slave = &omap44xx_l3_main_2_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* ipu -> l3_main_2 */ -static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = { - .master = &omap44xx_ipu_hwmod, - .slave = &omap44xx_l3_main_2_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* iss -> l3_main_2 */ -static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = { - .master = &omap44xx_iss_hwmod, - .slave = &omap44xx_l3_main_2_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* iva -> l3_main_2 */ -static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = { - .master = &omap44xx_iva_hwmod, - .slave = &omap44xx_l3_main_2_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = { - { - .pa_start = 0x44800000, - .pa_end = 0x44801fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l3_main_1 -> l3_main_2 */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = { - .master = &omap44xx_l3_main_1_hwmod, - .slave = &omap44xx_l3_main_2_hwmod, - .clk = "l3_div_ck", - .addr = omap44xx_l3_main_2_addrs, - .user = OCP_USER_MPU, -}; - -/* l4_cfg -> l3_main_2 */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_l3_main_2_hwmod, - .clk = "l4_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* usb_otg_hs -> l3_main_2 */ -static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = { - .master = &omap44xx_usb_otg_hs_hwmod, - .slave = &omap44xx_l3_main_2_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap44xx_l3_main_2_hwmod = { .name = "l3_main_2", .class = &omap44xx_l3_hwmod_class, @@ -390,40 +154,6 @@ static struct omap_hwmod omap44xx_l3_main_2_hwmod = { }; /* l3_main_3 */ -static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = { - { - .pa_start = 0x45000000, - .pa_end = 0x45000fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l3_main_1 -> l3_main_3 */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = { - .master = &omap44xx_l3_main_1_hwmod, - .slave = &omap44xx_l3_main_3_hwmod, - .clk = "l3_div_ck", - .addr = omap44xx_l3_main_3_addrs, - .user = OCP_USER_MPU, -}; - -/* l3_main_2 -> l3_main_3 */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_l3_main_3_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_cfg -> l3_main_3 */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_l3_main_3_hwmod, - .clk = "l4_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap44xx_l3_main_3_hwmod = { .name = "l3_main_3", .class = &omap44xx_l3_hwmod_class, @@ -446,38 +176,6 @@ static struct omap_hwmod_class omap44xx_l4_hwmod_class = { }; /* l4_abe */ -/* aess -> l4_abe */ -static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = { - .master = &omap44xx_aess_hwmod, - .slave = &omap44xx_l4_abe_hwmod, - .clk = "ocp_abe_iclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* dsp -> l4_abe */ -static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = { - .master = &omap44xx_dsp_hwmod, - .slave = &omap44xx_l4_abe_hwmod, - .clk = "ocp_abe_iclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l3_main_1 -> l4_abe */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = { - .master = &omap44xx_l3_main_1_hwmod, - .slave = &omap44xx_l4_abe_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mpu -> l4_abe */ -static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = { - .master = &omap44xx_mpu_hwmod, - .slave = &omap44xx_l4_abe_hwmod, - .clk = "ocp_abe_iclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap44xx_l4_abe_hwmod = { .name = "l4_abe", .class = &omap44xx_l4_hwmod_class, @@ -490,14 +188,6 @@ static struct omap_hwmod omap44xx_l4_abe_hwmod = { }; /* l4_cfg */ -/* l3_main_1 -> l4_cfg */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = { - .master = &omap44xx_l3_main_1_hwmod, - .slave = &omap44xx_l4_cfg_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap44xx_l4_cfg_hwmod = { .name = "l4_cfg", .class = &omap44xx_l4_hwmod_class, @@ -511,14 +201,6 @@ static struct omap_hwmod omap44xx_l4_cfg_hwmod = { }; /* l4_per */ -/* l3_main_2 -> l4_per */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_l4_per_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap44xx_l4_per_hwmod = { .name = "l4_per", .class = &omap44xx_l4_hwmod_class, @@ -532,14 +214,6 @@ static struct omap_hwmod omap44xx_l4_per_hwmod = { }; /* l4_wkup */ -/* l4_cfg -> l4_wkup */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_l4_wkup_hwmod, - .clk = "l4_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap44xx_l4_wkup_hwmod = { .name = "l4_wkup", .class = &omap44xx_l4_hwmod_class, @@ -561,14 +235,6 @@ static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = { }; /* mpu_private */ -/* mpu -> mpu_private */ -static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = { - .master = &omap44xx_mpu_hwmod, - .slave = &omap44xx_mpu_private_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap44xx_mpu_private_hwmod = { .name = "mpu_private", .class = &omap44xx_mpu_bus_hwmod_class, @@ -658,42 +324,6 @@ static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = { - { - .pa_start = 0x401f1000, - .pa_end = 0x401f13ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> aess */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_aess_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_aess_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = { - { - .pa_start = 0x490f1000, - .pa_end = 0x490f13ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> aess (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_aess_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_aess_dma_addrs, - .user = OCP_USER_SDMA, -}; - static struct omap_hwmod omap44xx_aess_hwmod = { .name = "aess", .class = &omap44xx_aess_hwmod_class, @@ -730,25 +360,6 @@ static struct omap_hwmod_class omap44xx_counter_hwmod_class = { }; /* counter_32k */ -static struct omap_hwmod omap44xx_counter_32k_hwmod; -static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = { - { - .pa_start = 0x4a304000, - .pa_end = 0x4a30401f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_wkup -> counter_32k */ -static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = { - .master = &omap44xx_l4_wkup_hwmod, - .slave = &omap44xx_counter_32k_hwmod, - .clk = "l4_wkup_clk_mux_ck", - .addr = omap44xx_counter_32k_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap44xx_counter_32k_hwmod = { .name = "counter_32k", .class = &omap44xx_counter_hwmod_class, @@ -803,24 +414,6 @@ static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = { { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = { - { - .pa_start = 0x4a056000, - .pa_end = 0x4a056fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_cfg -> dma_system */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_dma_system_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_dma_system_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap44xx_dma_system_hwmod = { .name = "dma_system", .class = &omap44xx_dma_hwmod_class, @@ -857,7 +450,6 @@ static struct omap_hwmod_class omap44xx_dmic_hwmod_class = { }; /* dmic */ -static struct omap_hwmod omap44xx_dmic_hwmod; static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = { { .irq = 114 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -868,44 +460,6 @@ static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = { - { - .name = "mpu", - .pa_start = 0x4012e000, - .pa_end = 0x4012e07f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> dmic */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_dmic_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_dmic_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = { - { - .name = "dma", - .pa_start = 0x4902e000, - .pa_end = 0x4902e07f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> dmic (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_dmic_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_dmic_dma_addrs, - .user = OCP_USER_SDMA, -}; - static struct omap_hwmod omap44xx_dmic_hwmod = { .name = "dmic", .class = &omap44xx_dmic_hwmod_class, @@ -942,22 +496,6 @@ static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = { { .name = "mmu_cache", .rst_shift = 1 }, }; -/* dsp -> iva */ -static struct omap_hwmod_ocp_if omap44xx_dsp__iva = { - .master = &omap44xx_dsp_hwmod, - .slave = &omap44xx_iva_hwmod, - .clk = "dpll_iva_m5x2_ck", - .user = OCP_USER_DSP, -}; - -/* l4_cfg -> dsp */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_dsp_hwmod, - .clk = "l4_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap44xx_dsp_hwmod = { .name = "dsp", .class = &omap44xx_dsp_hwmod_class, @@ -994,42 +532,6 @@ static struct omap_hwmod_class omap44xx_dss_hwmod_class = { }; /* dss */ -static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = { - { - .pa_start = 0x58000000, - .pa_end = 0x5800007f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l3_main_2 -> dss */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_dss_hwmod, - .clk = "dss_fck", - .addr = omap44xx_dss_dma_addrs, - .user = OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = { - { - .pa_start = 0x48040000, - .pa_end = 0x4804007f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> dss */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_dss_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_dss_addrs, - .user = OCP_USER_MPU, -}; - static struct omap_hwmod_opt_clk dss_opt_clks[] = { { .role = "sys_clk", .clk = "dss_sys_clk" }, { .role = "tv_clk", .clk = "dss_tv_clk" }, @@ -1076,7 +578,6 @@ static struct omap_hwmod_class omap44xx_dispc_hwmod_class = { }; /* dss_dispc */ -static struct omap_hwmod omap44xx_dss_dispc_hwmod; static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = { { .irq = 25 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -1087,47 +588,11 @@ static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = { - { - .pa_start = 0x58001000, - .pa_end = 0x58001fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l3_main_2 -> dss_dispc */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_dss_dispc_hwmod, - .clk = "dss_fck", - .addr = omap44xx_dss_dispc_dma_addrs, - .user = OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = { - { - .pa_start = 0x48041000, - .pa_end = 0x48041fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = { .manager_count = 3, .has_framedonetv_irq = 1 }; -/* l4_per -> dss_dispc */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_dss_dispc_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_dss_dispc_addrs, - .user = OCP_USER_MPU, -}; - static struct omap_hwmod omap44xx_dss_dispc_hwmod = { .name = "dss_dispc", .class = &omap44xx_dispc_hwmod_class, @@ -1166,7 +631,6 @@ static struct omap_hwmod_class omap44xx_dsi_hwmod_class = { }; /* dss_dsi1 */ -static struct omap_hwmod omap44xx_dss_dsi1_hwmod; static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = { { .irq = 53 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -1177,42 +641,6 @@ static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = { - { - .pa_start = 0x58004000, - .pa_end = 0x580041ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l3_main_2 -> dss_dsi1 */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_dss_dsi1_hwmod, - .clk = "dss_fck", - .addr = omap44xx_dss_dsi1_dma_addrs, - .user = OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = { - { - .pa_start = 0x48044000, - .pa_end = 0x480441ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> dss_dsi1 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_dss_dsi1_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_dss_dsi1_addrs, - .user = OCP_USER_MPU, -}; - static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { { .role = "sys_clk", .clk = "dss_sys_clk" }, }; @@ -1235,7 +663,6 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = { }; /* dss_dsi2 */ -static struct omap_hwmod omap44xx_dss_dsi2_hwmod; static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = { { .irq = 84 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -1246,42 +673,6 @@ static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = { - { - .pa_start = 0x58005000, - .pa_end = 0x580051ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l3_main_2 -> dss_dsi2 */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_dss_dsi2_hwmod, - .clk = "dss_fck", - .addr = omap44xx_dss_dsi2_dma_addrs, - .user = OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = { - { - .pa_start = 0x48045000, - .pa_end = 0x480451ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> dss_dsi2 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_dss_dsi2_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_dss_dsi2_addrs, - .user = OCP_USER_MPU, -}; - static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = { { .role = "sys_clk", .clk = "dss_sys_clk" }, }; @@ -1324,7 +715,6 @@ static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = { }; /* dss_hdmi */ -static struct omap_hwmod omap44xx_dss_hdmi_hwmod; static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = { { .irq = 101 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -1335,42 +725,6 @@ static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = { - { - .pa_start = 0x58006000, - .pa_end = 0x58006fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l3_main_2 -> dss_hdmi */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_dss_hdmi_hwmod, - .clk = "dss_fck", - .addr = omap44xx_dss_hdmi_dma_addrs, - .user = OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = { - { - .pa_start = 0x48046000, - .pa_end = 0x48046fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> dss_hdmi */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_dss_hdmi_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_dss_hdmi_addrs, - .user = OCP_USER_MPU, -}; - static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = { { .role = "sys_clk", .clk = "dss_sys_clk" }, }; @@ -1413,48 +767,11 @@ static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = { }; /* dss_rfbi */ -static struct omap_hwmod omap44xx_dss_rfbi_hwmod; static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = { { .dma_req = 13 + OMAP44XX_DMA_REQ_START }, { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = { - { - .pa_start = 0x58002000, - .pa_end = 0x580020ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l3_main_2 -> dss_rfbi */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_dss_rfbi_hwmod, - .clk = "dss_fck", - .addr = omap44xx_dss_rfbi_dma_addrs, - .user = OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = { - { - .pa_start = 0x48042000, - .pa_end = 0x480420ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> dss_rfbi */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_dss_rfbi_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_dss_rfbi_addrs, - .user = OCP_USER_MPU, -}; - static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { { .role = "ick", .clk = "dss_fck" }, }; @@ -1485,43 +802,6 @@ static struct omap_hwmod_class omap44xx_venc_hwmod_class = { }; /* dss_venc */ -static struct omap_hwmod omap44xx_dss_venc_hwmod; -static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = { - { - .pa_start = 0x58003000, - .pa_end = 0x580030ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l3_main_2 -> dss_venc */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_dss_venc_hwmod, - .clk = "dss_fck", - .addr = omap44xx_dss_venc_dma_addrs, - .user = OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = { - { - .pa_start = 0x48043000, - .pa_end = 0x480430ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> dss_venc */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_dss_venc_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_dss_venc_addrs, - .user = OCP_USER_MPU, -}; - static struct omap_hwmod omap44xx_dss_venc_hwmod = { .name = "dss_venc", .class = &omap44xx_venc_hwmod_class, @@ -1565,30 +845,11 @@ static struct omap_gpio_dev_attr gpio_dev_attr = { }; /* gpio1 */ -static struct omap_hwmod omap44xx_gpio1_hwmod; static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = { { .irq = 29 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = { - { - .pa_start = 0x4a310000, - .pa_end = 0x4a3101ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_wkup -> gpio1 */ -static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = { - .master = &omap44xx_l4_wkup_hwmod, - .slave = &omap44xx_gpio1_hwmod, - .clk = "l4_wkup_clk_mux_ck", - .addr = omap44xx_gpio1_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { { .role = "dbclk", .clk = "gpio1_dbclk" }, }; @@ -1612,30 +873,11 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = { }; /* gpio2 */ -static struct omap_hwmod omap44xx_gpio2_hwmod; static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = { { .irq = 30 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = { - { - .pa_start = 0x48055000, - .pa_end = 0x480551ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> gpio2 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_gpio2_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_gpio2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { { .role = "dbclk", .clk = "gpio2_dbclk" }, }; @@ -1660,30 +902,11 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = { }; /* gpio3 */ -static struct omap_hwmod omap44xx_gpio3_hwmod; static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = { { .irq = 31 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = { - { - .pa_start = 0x48057000, - .pa_end = 0x480571ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> gpio3 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_gpio3_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_gpio3_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { { .role = "dbclk", .clk = "gpio3_dbclk" }, }; @@ -1708,30 +931,11 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = { }; /* gpio4 */ -static struct omap_hwmod omap44xx_gpio4_hwmod; static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = { { .irq = 32 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = { - { - .pa_start = 0x48059000, - .pa_end = 0x480591ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> gpio4 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_gpio4_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_gpio4_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { { .role = "dbclk", .clk = "gpio4_dbclk" }, }; @@ -1756,32 +960,13 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = { }; /* gpio5 */ -static struct omap_hwmod omap44xx_gpio5_hwmod; static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = { { .irq = 33 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = { - { - .pa_start = 0x4805b000, - .pa_end = 0x4805b1ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> gpio5 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_gpio5_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_gpio5_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { - { .role = "dbclk", .clk = "gpio5_dbclk" }, +static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { + { .role = "dbclk", .clk = "gpio5_dbclk" }, }; static struct omap_hwmod omap44xx_gpio5_hwmod = { @@ -1804,30 +989,11 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = { }; /* gpio6 */ -static struct omap_hwmod omap44xx_gpio6_hwmod; static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = { { .irq = 34 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = { - { - .pa_start = 0x4805d000, - .pa_end = 0x4805d1ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> gpio6 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_gpio6_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_gpio6_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { { .role = "dbclk", .clk = "gpio6_dbclk" }, }; @@ -1883,24 +1049,6 @@ static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = { { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = { - { - .pa_start = 0x4a058000, - .pa_end = 0x4a05bfff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_cfg -> hsi */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_hsi_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_hsi_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap44xx_hsi_hwmod = { .name = "hsi", .class = &omap44xx_hsi_hwmod_class, @@ -1945,7 +1093,6 @@ static struct omap_i2c_dev_attr i2c_dev_attr = { }; /* i2c1 */ -static struct omap_hwmod omap44xx_i2c1_hwmod; static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = { { .irq = 56 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -1957,24 +1104,6 @@ static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = { - { - .pa_start = 0x48070000, - .pa_end = 0x480700ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> i2c1 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_i2c1_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_i2c1_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap44xx_i2c1_hwmod = { .name = "i2c1", .class = &omap44xx_i2c_hwmod_class, @@ -1994,7 +1123,6 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = { }; /* i2c2 */ -static struct omap_hwmod omap44xx_i2c2_hwmod; static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = { { .irq = 57 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -2006,24 +1134,6 @@ static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = { - { - .pa_start = 0x48072000, - .pa_end = 0x480720ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> i2c2 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_i2c2_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_i2c2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap44xx_i2c2_hwmod = { .name = "i2c2", .class = &omap44xx_i2c_hwmod_class, @@ -2043,7 +1153,6 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = { }; /* i2c3 */ -static struct omap_hwmod omap44xx_i2c3_hwmod; static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = { { .irq = 61 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -2055,24 +1164,6 @@ static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = { - { - .pa_start = 0x48060000, - .pa_end = 0x480600ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> i2c3 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_i2c3_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_i2c3_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap44xx_i2c3_hwmod = { .name = "i2c3", .class = &omap44xx_i2c_hwmod_class, @@ -2092,7 +1183,6 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = { }; /* i2c4 */ -static struct omap_hwmod omap44xx_i2c4_hwmod; static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = { { .irq = 62 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -2104,24 +1194,6 @@ static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = { - { - .pa_start = 0x48350000, - .pa_end = 0x483500ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> i2c4 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_i2c4_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_i2c4_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap44xx_i2c4_hwmod = { .name = "i2c4", .class = &omap44xx_i2c_hwmod_class, @@ -2161,14 +1233,6 @@ static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = { { .name = "mmu_cache", .rst_shift = 2 }, }; -/* l3_main_2 -> ipu */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_ipu_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap44xx_ipu_hwmod = { .name = "ipu", .class = &omap44xx_ipu_hwmod_class, @@ -2231,24 +1295,6 @@ static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = { - { - .pa_start = 0x52000000, - .pa_end = 0x520000ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l3_main_2 -> iss */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_iss_hwmod, - .clk = "l3_div_ck", - .addr = omap44xx_iss_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod_opt_clk iss_opt_clks[] = { { .role = "ctrlclk", .clk = "iss_ctrlclk" }, }; @@ -2294,24 +1340,6 @@ static struct omap_hwmod_rst_info omap44xx_iva_resets[] = { { .name = "logic", .rst_shift = 2 }, }; -static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = { - { - .pa_start = 0x5a000000, - .pa_end = 0x5a07ffff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l3_main_2 -> iva */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_iva_hwmod, - .clk = "l3_div_ck", - .addr = omap44xx_iva_addrs, - .user = OCP_USER_MPU, -}; - static struct omap_hwmod omap44xx_iva_hwmod = { .name = "iva", .class = &omap44xx_iva_hwmod_class, @@ -2353,30 +1381,11 @@ static struct omap_hwmod_class omap44xx_kbd_hwmod_class = { }; /* kbd */ -static struct omap_hwmod omap44xx_kbd_hwmod; static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = { { .irq = 120 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = { - { - .pa_start = 0x4a31c000, - .pa_end = 0x4a31c07f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_wkup -> kbd */ -static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = { - .master = &omap44xx_l4_wkup_hwmod, - .slave = &omap44xx_kbd_hwmod, - .clk = "l4_wkup_clk_mux_ck", - .addr = omap44xx_kbd_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap44xx_kbd_hwmod = { .name = "kbd", .class = &omap44xx_kbd_hwmod_class, @@ -2413,30 +1422,11 @@ static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = { }; /* mailbox */ -static struct omap_hwmod omap44xx_mailbox_hwmod; static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = { { .irq = 26 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = { - { - .pa_start = 0x4a0f4000, - .pa_end = 0x4a0f41ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_cfg -> mailbox */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_mailbox_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_mailbox_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap44xx_mailbox_hwmod = { .name = "mailbox", .class = &omap44xx_mailbox_hwmod_class, @@ -2470,7 +1460,6 @@ static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = { }; /* mcbsp1 */ -static struct omap_hwmod omap44xx_mcbsp1_hwmod; static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = { { .irq = 17 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -2482,45 +1471,6 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = { - { - .name = "mpu", - .pa_start = 0x40122000, - .pa_end = 0x401220ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> mcbsp1 */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_mcbsp1_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_mcbsp1_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = { - { - .name = "dma", - .pa_start = 0x49022000, - .pa_end = 0x490220ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> mcbsp1 (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_mcbsp1_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_mcbsp1_dma_addrs, - .user = OCP_USER_SDMA, -}; - - static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = { { .role = "pad_fck", .clk = "pad_clks_ck" }, { .role = "prcm_clk", .clk = "mcbsp1_sync_mux_ck" }, @@ -2545,7 +1495,6 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = { }; /* mcbsp2 */ -static struct omap_hwmod omap44xx_mcbsp2_hwmod; static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = { { .irq = 22 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -2557,47 +1506,9 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = { - { - .name = "mpu", - .pa_start = 0x40124000, - .pa_end = 0x401240ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> mcbsp2 */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_mcbsp2_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_mcbsp2_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = { - { - .name = "dma", - .pa_start = 0x49024000, - .pa_end = 0x490240ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> mcbsp2 (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_mcbsp2_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_mcbsp2_dma_addrs, - .user = OCP_USER_SDMA, -}; - -static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = { - { .role = "pad_fck", .clk = "pad_clks_ck" }, - { .role = "prcm_clk", .clk = "mcbsp2_sync_mux_ck" }, +static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = { + { .role = "pad_fck", .clk = "pad_clks_ck" }, + { .role = "prcm_clk", .clk = "mcbsp2_sync_mux_ck" }, }; static struct omap_hwmod omap44xx_mcbsp2_hwmod = { @@ -2619,7 +1530,6 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = { }; /* mcbsp3 */ -static struct omap_hwmod omap44xx_mcbsp3_hwmod; static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = { { .irq = 23 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -2631,44 +1541,6 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = { - { - .name = "mpu", - .pa_start = 0x40126000, - .pa_end = 0x401260ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> mcbsp3 */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_mcbsp3_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_mcbsp3_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = { - { - .name = "dma", - .pa_start = 0x49026000, - .pa_end = 0x490260ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> mcbsp3 (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_mcbsp3_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_mcbsp3_dma_addrs, - .user = OCP_USER_SDMA, -}; - static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = { { .role = "pad_fck", .clk = "pad_clks_ck" }, { .role = "prcm_clk", .clk = "mcbsp3_sync_mux_ck" }, @@ -2693,7 +1565,6 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = { }; /* mcbsp4 */ -static struct omap_hwmod omap44xx_mcbsp4_hwmod; static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = { { .irq = 16 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -2705,24 +1576,6 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = { - { - .pa_start = 0x48096000, - .pa_end = 0x480960ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> mcbsp4 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_mcbsp4_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_mcbsp4_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = { { .role = "pad_fck", .clk = "pad_clks_ck" }, { .role = "prcm_clk", .clk = "mcbsp4_sync_mux_ck" }, @@ -2768,7 +1621,6 @@ static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = { }; /* mcpdm */ -static struct omap_hwmod omap44xx_mcpdm_hwmod; static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = { { .irq = 112 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -2780,42 +1632,6 @@ static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = { - { - .pa_start = 0x40132000, - .pa_end = 0x4013207f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> mcpdm */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_mcpdm_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_mcpdm_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = { - { - .pa_start = 0x49032000, - .pa_end = 0x4903207f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> mcpdm (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_mcpdm_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_mcpdm_dma_addrs, - .user = OCP_USER_SDMA, -}; - static struct omap_hwmod omap44xx_mcpdm_hwmod = { .name = "mcpdm", .class = &omap44xx_mcpdm_hwmod_class, @@ -2855,7 +1671,6 @@ static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = { }; /* mcspi1 */ -static struct omap_hwmod omap44xx_mcspi1_hwmod; static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = { { .irq = 65 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -2873,24 +1688,6 @@ static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = { - { - .pa_start = 0x48098000, - .pa_end = 0x480981ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> mcspi1 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_mcspi1_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_mcspi1_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* mcspi1 dev_attr */ static struct omap2_mcspi_dev_attr mcspi1_dev_attr = { .num_chipselect = 4, @@ -2914,7 +1711,6 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = { }; /* mcspi2 */ -static struct omap_hwmod omap44xx_mcspi2_hwmod; static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = { { .irq = 66 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -2928,24 +1724,6 @@ static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = { - { - .pa_start = 0x4809a000, - .pa_end = 0x4809a1ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> mcspi2 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_mcspi2_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_mcspi2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* mcspi2 dev_attr */ static struct omap2_mcspi_dev_attr mcspi2_dev_attr = { .num_chipselect = 2, @@ -2969,7 +1747,6 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = { }; /* mcspi3 */ -static struct omap_hwmod omap44xx_mcspi3_hwmod; static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = { { .irq = 91 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -2983,24 +1760,6 @@ static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = { - { - .pa_start = 0x480b8000, - .pa_end = 0x480b81ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> mcspi3 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_mcspi3_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_mcspi3_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* mcspi3 dev_attr */ static struct omap2_mcspi_dev_attr mcspi3_dev_attr = { .num_chipselect = 2, @@ -3024,7 +1783,6 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = { }; /* mcspi4 */ -static struct omap_hwmod omap44xx_mcspi4_hwmod; static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = { { .irq = 48 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -3036,24 +1794,6 @@ static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = { - { - .pa_start = 0x480ba000, - .pa_end = 0x480ba1ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> mcspi4 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_mcspi4_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_mcspi4_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* mcspi4 dev_attr */ static struct omap2_mcspi_dev_attr mcspi4_dev_attr = { .num_chipselect = 1, @@ -3110,24 +1850,6 @@ static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = { - { - .pa_start = 0x4809c000, - .pa_end = 0x4809c3ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> mmc1 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_mmc1_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_mmc1_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* mmc1 dev_attr */ static struct omap_mmc_dev_attr mmc1_dev_attr = { .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, @@ -3162,24 +1884,6 @@ static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = { - { - .pa_start = 0x480b4000, - .pa_end = 0x480b43ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> mmc2 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_mmc2_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_mmc2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap44xx_mmc2_hwmod = { .name = "mmc2", .class = &omap44xx_mmc_hwmod_class, @@ -3197,7 +1901,6 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = { }; /* mmc3 */ -static struct omap_hwmod omap44xx_mmc3_hwmod; static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = { { .irq = 94 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -3209,24 +1912,6 @@ static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = { - { - .pa_start = 0x480ad000, - .pa_end = 0x480ad3ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> mmc3 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_mmc3_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_mmc3_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap44xx_mmc3_hwmod = { .name = "mmc3", .class = &omap44xx_mmc_hwmod_class, @@ -3244,7 +1929,6 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = { }; /* mmc4 */ -static struct omap_hwmod omap44xx_mmc4_hwmod; static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = { { .irq = 96 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -3256,30 +1940,11 @@ static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = { - { - .pa_start = 0x480d1000, - .pa_end = 0x480d13ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> mmc4 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_mmc4_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_mmc4_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap44xx_mmc4_hwmod = { .name = "mmc4", .class = &omap44xx_mmc_hwmod_class, .clkdm_name = "l4_per_clkdm", .mpu_irqs = omap44xx_mmc4_irqs, - .sdma_reqs = omap44xx_mmc4_sdma_reqs, .main_clk = "mmc4_fck", .prcm = { @@ -3292,7 +1957,6 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = { }; /* mmc5 */ -static struct omap_hwmod omap44xx_mmc5_hwmod; static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = { { .irq = 59 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -3304,24 +1968,6 @@ static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = { - { - .pa_start = 0x480d5000, - .pa_end = 0x480d53ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> mmc5 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_mmc5_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_mmc5_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap44xx_mmc5_hwmod = { .name = "mmc5", .class = &omap44xx_mmc_hwmod_class, @@ -3401,30 +2047,11 @@ static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = { .sensor_voltdm_name = "core", }; -static struct omap_hwmod omap44xx_smartreflex_core_hwmod; static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = { { .irq = 19 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = { - { - .pa_start = 0x4a0dd000, - .pa_end = 0x4a0dd03f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_cfg -> smartreflex_core */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_smartreflex_core_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_smartreflex_core_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap44xx_smartreflex_core_hwmod = { .name = "smartreflex_core", .class = &omap44xx_smartreflex_hwmod_class, @@ -3447,30 +2074,11 @@ static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = { .sensor_voltdm_name = "iva", }; -static struct omap_hwmod omap44xx_smartreflex_iva_hwmod; static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = { { .irq = 102 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = { - { - .pa_start = 0x4a0db000, - .pa_end = 0x4a0db03f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_cfg -> smartreflex_iva */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_smartreflex_iva_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_smartreflex_iva_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = { .name = "smartreflex_iva", .class = &omap44xx_smartreflex_hwmod_class, @@ -3492,30 +2100,11 @@ static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = { .sensor_voltdm_name = "mpu", }; -static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod; static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = { { .irq = 18 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = { - { - .pa_start = 0x4a0d9000, - .pa_end = 0x4a0d903f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_cfg -> smartreflex_mpu */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_smartreflex_mpu_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_smartreflex_mpu_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = { .name = "smartreflex_mpu", .class = &omap44xx_smartreflex_hwmod_class, @@ -3556,25 +2145,6 @@ static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = { }; /* spinlock */ -static struct omap_hwmod omap44xx_spinlock_hwmod; -static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = { - { - .pa_start = 0x4a0f6000, - .pa_end = 0x4a0f6fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_cfg -> spinlock */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_spinlock_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_spinlock_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap44xx_spinlock_hwmod = { .name = "spinlock", .class = &omap44xx_spinlock_hwmod_class, @@ -3636,30 +2206,11 @@ static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { }; /* timer1 */ -static struct omap_hwmod omap44xx_timer1_hwmod; static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = { { .irq = 37 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = { - { - .pa_start = 0x4a318000, - .pa_end = 0x4a31807f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_wkup -> timer1 */ -static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = { - .master = &omap44xx_l4_wkup_hwmod, - .slave = &omap44xx_timer1_hwmod, - .clk = "l4_wkup_clk_mux_ck", - .addr = omap44xx_timer1_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap44xx_timer1_hwmod = { .name = "timer1", .class = &omap44xx_timer_1ms_hwmod_class, @@ -3677,30 +2228,11 @@ static struct omap_hwmod omap44xx_timer1_hwmod = { }; /* timer2 */ -static struct omap_hwmod omap44xx_timer2_hwmod; static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = { { .irq = 38 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = { - { - .pa_start = 0x48032000, - .pa_end = 0x4803207f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> timer2 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_timer2_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_timer2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap44xx_timer2_hwmod = { .name = "timer2", .class = &omap44xx_timer_1ms_hwmod_class, @@ -3718,30 +2250,11 @@ static struct omap_hwmod omap44xx_timer2_hwmod = { }; /* timer3 */ -static struct omap_hwmod omap44xx_timer3_hwmod; static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = { { .irq = 39 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = { - { - .pa_start = 0x48034000, - .pa_end = 0x4803407f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> timer3 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_timer3_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_timer3_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap44xx_timer3_hwmod = { .name = "timer3", .class = &omap44xx_timer_hwmod_class, @@ -3759,30 +2272,11 @@ static struct omap_hwmod omap44xx_timer3_hwmod = { }; /* timer4 */ -static struct omap_hwmod omap44xx_timer4_hwmod; static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = { { .irq = 40 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = { - { - .pa_start = 0x48036000, - .pa_end = 0x4803607f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> timer4 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_timer4_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_timer4_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap44xx_timer4_hwmod = { .name = "timer4", .class = &omap44xx_timer_hwmod_class, @@ -3800,48 +2294,11 @@ static struct omap_hwmod omap44xx_timer4_hwmod = { }; /* timer5 */ -static struct omap_hwmod omap44xx_timer5_hwmod; static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = { { .irq = 41 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = { - { - .pa_start = 0x40138000, - .pa_end = 0x4013807f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> timer5 */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_timer5_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_timer5_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = { - { - .pa_start = 0x49038000, - .pa_end = 0x4903807f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> timer5 (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_timer5_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_timer5_dma_addrs, - .user = OCP_USER_SDMA, -}; - static struct omap_hwmod omap44xx_timer5_hwmod = { .name = "timer5", .class = &omap44xx_timer_hwmod_class, @@ -3859,48 +2316,11 @@ static struct omap_hwmod omap44xx_timer5_hwmod = { }; /* timer6 */ -static struct omap_hwmod omap44xx_timer6_hwmod; static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = { { .irq = 42 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = { - { - .pa_start = 0x4013a000, - .pa_end = 0x4013a07f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> timer6 */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_timer6_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_timer6_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = { - { - .pa_start = 0x4903a000, - .pa_end = 0x4903a07f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> timer6 (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_timer6_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_timer6_dma_addrs, - .user = OCP_USER_SDMA, -}; - static struct omap_hwmod omap44xx_timer6_hwmod = { .name = "timer6", .class = &omap44xx_timer_hwmod_class, @@ -3919,48 +2339,11 @@ static struct omap_hwmod omap44xx_timer6_hwmod = { }; /* timer7 */ -static struct omap_hwmod omap44xx_timer7_hwmod; static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = { { .irq = 43 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = { - { - .pa_start = 0x4013c000, - .pa_end = 0x4013c07f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> timer7 */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_timer7_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_timer7_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = { - { - .pa_start = 0x4903c000, - .pa_end = 0x4903c07f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> timer7 (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_timer7_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_timer7_dma_addrs, - .user = OCP_USER_SDMA, -}; - static struct omap_hwmod omap44xx_timer7_hwmod = { .name = "timer7", .class = &omap44xx_timer_hwmod_class, @@ -3978,48 +2361,11 @@ static struct omap_hwmod omap44xx_timer7_hwmod = { }; /* timer8 */ -static struct omap_hwmod omap44xx_timer8_hwmod; static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = { { .irq = 44 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = { - { - .pa_start = 0x4013e000, - .pa_end = 0x4013e07f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> timer8 */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_timer8_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_timer8_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = { - { - .pa_start = 0x4903e000, - .pa_end = 0x4903e07f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> timer8 (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_timer8_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_timer8_dma_addrs, - .user = OCP_USER_SDMA, -}; - static struct omap_hwmod omap44xx_timer8_hwmod = { .name = "timer8", .class = &omap44xx_timer_hwmod_class, @@ -4037,30 +2383,11 @@ static struct omap_hwmod omap44xx_timer8_hwmod = { }; /* timer9 */ -static struct omap_hwmod omap44xx_timer9_hwmod; static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = { { .irq = 45 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = { - { - .pa_start = 0x4803e000, - .pa_end = 0x4803e07f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> timer9 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_timer9_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_timer9_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap44xx_timer9_hwmod = { .name = "timer9", .class = &omap44xx_timer_hwmod_class, @@ -4078,30 +2405,11 @@ static struct omap_hwmod omap44xx_timer9_hwmod = { }; /* timer10 */ -static struct omap_hwmod omap44xx_timer10_hwmod; static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = { { .irq = 46 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = { - { - .pa_start = 0x48086000, - .pa_end = 0x4808607f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> timer10 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_timer10_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_timer10_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap44xx_timer10_hwmod = { .name = "timer10", .class = &omap44xx_timer_1ms_hwmod_class, @@ -4119,30 +2427,11 @@ static struct omap_hwmod omap44xx_timer10_hwmod = { }; /* timer11 */ -static struct omap_hwmod omap44xx_timer11_hwmod; static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = { { .irq = 47 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = { - { - .pa_start = 0x48088000, - .pa_end = 0x4808807f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> timer11 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_timer11_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_timer11_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap44xx_timer11_hwmod = { .name = "timer11", .class = &omap44xx_timer_hwmod_class, @@ -4182,7 +2471,6 @@ static struct omap_hwmod_class omap44xx_uart_hwmod_class = { }; /* uart1 */ -static struct omap_hwmod omap44xx_uart1_hwmod; static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = { { .irq = 72 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -4194,24 +2482,6 @@ static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = { - { - .pa_start = 0x4806a000, - .pa_end = 0x4806a0ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> uart1 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_uart1_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_uart1_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap44xx_uart1_hwmod = { .name = "uart1", .class = &omap44xx_uart_hwmod_class, @@ -4229,7 +2499,6 @@ static struct omap_hwmod omap44xx_uart1_hwmod = { }; /* uart2 */ -static struct omap_hwmod omap44xx_uart2_hwmod; static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = { { .irq = 73 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -4241,24 +2510,6 @@ static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = { - { - .pa_start = 0x4806c000, - .pa_end = 0x4806c0ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> uart2 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_uart2_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_uart2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap44xx_uart2_hwmod = { .name = "uart2", .class = &omap44xx_uart_hwmod_class, @@ -4276,7 +2527,6 @@ static struct omap_hwmod omap44xx_uart2_hwmod = { }; /* uart3 */ -static struct omap_hwmod omap44xx_uart3_hwmod; static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = { { .irq = 74 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -4288,24 +2538,6 @@ static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = { - { - .pa_start = 0x48020000, - .pa_end = 0x480200ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> uart3 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_uart3_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_uart3_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap44xx_uart3_hwmod = { .name = "uart3", .class = &omap44xx_uart_hwmod_class, @@ -4324,7 +2556,6 @@ static struct omap_hwmod omap44xx_uart3_hwmod = { }; /* uart4 */ -static struct omap_hwmod omap44xx_uart4_hwmod; static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = { { .irq = 70 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -4336,24 +2567,6 @@ static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = { - { - .pa_start = 0x4806e000, - .pa_end = 0x4806e0ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> uart4 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_uart4_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_uart4_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap44xx_uart4_hwmod = { .name = "uart4", .class = &omap44xx_uart_hwmod_class, @@ -4371,73 +2584,188 @@ static struct omap_hwmod omap44xx_uart4_hwmod = { }; /* - * 'usb_otg_hs' class - * high-speed on-the-go universal serial bus (usb_otg_hs) controller + * 'usb_host_hs' class + * high-speed multi-port usb host controller */ -static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = { - .rev_offs = 0x0400, - .sysc_offs = 0x0404, - .syss_offs = 0x0408, - .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | - SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), +static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET), .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | - MSTANDBY_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, + MSTANDBY_SMART | MSTANDBY_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type2, }; -static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = { - .name = "usb_otg_hs", - .sysc = &omap44xx_usb_otg_hs_sysc, +static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = { + .name = "usb_host_hs", + .sysc = &omap44xx_usb_host_hs_sysc, }; -/* usb_otg_hs */ -static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = { - { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START }, - { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START }, +/* usb_host_hs */ +static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = { + { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START }, + { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = { - { - .pa_start = 0x4a0ab000, - .pa_end = 0x4a0ab003, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_cfg -> usb_otg_hs */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_usb_otg_hs_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_usb_otg_hs_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = { - { .role = "xclk", .clk = "usb_otg_hs_xclk" }, -}; - -static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = { - .name = "usb_otg_hs", - .class = &omap44xx_usb_otg_hs_hwmod_class, +static struct omap_hwmod omap44xx_usb_host_hs_hwmod = { + .name = "usb_host_hs", + .class = &omap44xx_usb_host_hs_hwmod_class, .clkdm_name = "l3_init_clkdm", - .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, - .mpu_irqs = omap44xx_usb_otg_hs_irqs, - .main_clk = "usb_otg_hs_ick", + .main_clk = "usb_host_hs_fck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, + .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET, + .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .mpu_irqs = omap44xx_usb_host_hs_irqs, + + /* + * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock + * id: i660 + * + * Description: + * In the following configuration : + * - USBHOST module is set to smart-idle mode + * - PRCM asserts idle_req to the USBHOST module ( This typically + * happens when the system is going to a low power mode : all ports + * have been suspended, the master part of the USBHOST module has + * entered the standby state, and SW has cut the functional clocks) + * - an USBHOST interrupt occurs before the module is able to answer + * idle_ack, typically a remote wakeup IRQ. + * Then the USB HOST module will enter a deadlock situation where it + * is no more accessible nor functional. + * + * Workaround: + * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE + */ + + /* + * Errata: USB host EHCI may stall when entering smart-standby mode + * Id: i571 + * + * Description: + * When the USBHOST module is set to smart-standby mode, and when it is + * ready to enter the standby state (i.e. all ports are suspended and + * all attached devices are in suspend mode), then it can wrongly assert + * the Mstandby signal too early while there are still some residual OCP + * transactions ongoing. If this condition occurs, the internal state + * machine may go to an undefined state and the USB link may be stuck + * upon the next resume. + * + * Workaround: + * Don't use smart standby; use only force standby, + * hence HWMOD_SWSUP_MSTANDBY + */ + + /* + * During system boot; If the hwmod framework resets the module + * the module will have smart idle settings; which can lead to deadlock + * (above Errata Id:i660); so, dont reset the module during boot; + * Use HWMOD_INIT_NO_RESET. + */ + + .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY | + HWMOD_INIT_NO_RESET, +}; + +/* + * 'usb_otg_hs' class + * high-speed on-the-go universal serial bus (usb_otg_hs) controller + */ + +static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = { + .rev_offs = 0x0400, + .sysc_offs = 0x0404, + .syss_offs = 0x0408, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | + SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | + MSTANDBY_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = { + .name = "usb_otg_hs", + .sysc = &omap44xx_usb_otg_hs_sysc, +}; + +/* usb_otg_hs */ +static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = { + { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START }, + { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START }, + { .irq = -1 } +}; + +static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = { + { .role = "xclk", .clk = "usb_otg_hs_xclk" }, +}; + +static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = { + .name = "usb_otg_hs", + .class = &omap44xx_usb_otg_hs_hwmod_class, + .clkdm_name = "l3_init_clkdm", + .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, + .mpu_irqs = omap44xx_usb_otg_hs_irqs, + .main_clk = "usb_otg_hs_ick", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET, + .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, + .opt_clks = usb_otg_hs_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks), +}; + +/* + * 'usb_tll_hs' class + * usb_tll_hs module is the adapter on the usb_host_hs ports + */ + +static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = { + .name = "usb_tll_hs", + .sysc = &omap44xx_usb_tll_hs_sysc, +}; + +static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = { + { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START }, + { .irq = -1 } +}; + +static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = { + .name = "usb_tll_hs", + .class = &omap44xx_usb_tll_hs_hwmod_class, + .clkdm_name = "l3_init_clkdm", + .mpu_irqs = omap44xx_usb_tll_hs_irqs, + .main_clk = "usb_tll_hs_ick", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET, + .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, }, }, - .opt_clks = usb_otg_hs_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks), }; /* @@ -4464,30 +2792,11 @@ static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = { }; /* wd_timer2 */ -static struct omap_hwmod omap44xx_wd_timer2_hwmod; static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = { { .irq = 80 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = { - { - .pa_start = 0x4a314000, - .pa_end = 0x4a31407f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_wkup -> wd_timer2 */ -static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = { - .master = &omap44xx_l4_wkup_hwmod, - .slave = &omap44xx_wd_timer2_hwmod, - .clk = "l4_wkup_clk_mux_ck", - .addr = omap44xx_wd_timer2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod omap44xx_wd_timer2_hwmod = { .name = "wd_timer2", .class = &omap44xx_wd_timer_hwmod_class, @@ -4504,48 +2813,11 @@ static struct omap_hwmod omap44xx_wd_timer2_hwmod = { }; /* wd_timer3 */ -static struct omap_hwmod omap44xx_wd_timer3_hwmod; static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = { { .irq = 36 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = { - { - .pa_start = 0x40130000, - .pa_end = 0x4013007f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> wd_timer3 */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_wd_timer3_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_wd_timer3_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = { - { - .pa_start = 0x49030000, - .pa_end = 0x4903007f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> wd_timer3 (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_wd_timer3_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_wd_timer3_dma_addrs, - .user = OCP_USER_SDMA, -}; - static struct omap_hwmod omap44xx_wd_timer3_hwmod = { .name = "wd_timer3", .class = &omap44xx_wd_timer_hwmod_class, @@ -4561,154 +2833,1770 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = { }, }; + /* - * 'usb_host_hs' class - * high-speed multi-port usb host controller + * interfaces */ -static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = { - .master = &omap44xx_usb_host_hs_hwmod, - .slave = &omap44xx_l3_main_2_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | - MSTANDBY_SMART | MSTANDBY_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type2, -}; -static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = { - .name = "usb_host_hs", - .sysc = &omap44xx_usb_host_hs_sysc, +/* l3_main_1 -> dmm */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = { + .master = &omap44xx_l3_main_1_hwmod, + .slave = &omap44xx_dmm_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = { +static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = { { - .name = "uhh", - .pa_start = 0x4a064000, - .pa_end = 0x4a0647ff, + .pa_start = 0x4e000000, + .pa_end = 0x4e0007ff, .flags = ADDR_TYPE_RT }, - { - .name = "ohci", - .pa_start = 0x4a064800, - .pa_end = 0x4a064bff, - }, - { - .name = "ehci", - .pa_start = 0x4a064c00, - .pa_end = 0x4a064fff, - }, - {} + { } }; -static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = { - { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START }, - { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } +/* mpu -> dmm */ +static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = { + .master = &omap44xx_mpu_hwmod, + .slave = &omap44xx_dmm_hwmod, + .clk = "l3_div_ck", + .addr = omap44xx_dmm_addrs, + .user = OCP_USER_MPU, }; -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_usb_host_hs_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_usb_host_hs_addrs, +/* dmm -> emif_fw */ +static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = { + .master = &omap44xx_dmm_hwmod, + .slave = &omap44xx_emif_fw_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = { + { + .pa_start = 0x4a20c000, + .pa_end = 0x4a20c0ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_cfg -> emif_fw */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_emif_fw_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_emif_fw_addrs, + .user = OCP_USER_MPU, +}; + +/* iva -> l3_instr */ +static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = { + .master = &omap44xx_iva_hwmod, + .slave = &omap44xx_l3_instr_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_3 -> l3_instr */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = { + .master = &omap44xx_l3_main_3_hwmod, + .slave = &omap44xx_l3_instr_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dsp -> l3_main_1 */ +static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = { + .master = &omap44xx_dsp_hwmod, + .slave = &omap44xx_l3_main_1_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dss -> l3_main_1 */ +static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = { + .master = &omap44xx_dss_hwmod, + .slave = &omap44xx_l3_main_1_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_2 -> l3_main_1 */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_l3_main_1_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_cfg -> l3_main_1 */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_l3_main_1_hwmod, + .clk = "l4_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mmc1 -> l3_main_1 */ +static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = { + .master = &omap44xx_mmc1_hwmod, + .slave = &omap44xx_l3_main_1_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mmc2 -> l3_main_1 */ +static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = { + .master = &omap44xx_mmc2_hwmod, + .slave = &omap44xx_l3_main_1_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = { + { + .pa_start = 0x44000000, + .pa_end = 0x44000fff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* mpu -> l3_main_1 */ +static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { + .master = &omap44xx_mpu_hwmod, + .slave = &omap44xx_l3_main_1_hwmod, + .clk = "l3_div_ck", + .addr = omap44xx_l3_main_1_addrs, + .user = OCP_USER_MPU, +}; + +/* dma_system -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = { + .master = &omap44xx_dma_system_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* hsi -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = { + .master = &omap44xx_hsi_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* ipu -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = { + .master = &omap44xx_ipu_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* iss -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = { + .master = &omap44xx_iss_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* iva -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = { + .master = &omap44xx_iva_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = { + { + .pa_start = 0x44800000, + .pa_end = 0x44801fff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l3_main_1 -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = { + .master = &omap44xx_l3_main_1_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "l3_div_ck", + .addr = omap44xx_l3_main_2_addrs, + .user = OCP_USER_MPU, +}; + +/* l4_cfg -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "l4_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* usb_host_hs -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = { + .master = &omap44xx_usb_host_hs_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* usb_otg_hs -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = { + .master = &omap44xx_usb_otg_hs_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = { + { + .pa_start = 0x45000000, + .pa_end = 0x45000fff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l3_main_1 -> l3_main_3 */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = { + .master = &omap44xx_l3_main_1_hwmod, + .slave = &omap44xx_l3_main_3_hwmod, + .clk = "l3_div_ck", + .addr = omap44xx_l3_main_3_addrs, + .user = OCP_USER_MPU, +}; + +/* l3_main_2 -> l3_main_3 */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_l3_main_3_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_cfg -> l3_main_3 */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_l3_main_3_hwmod, + .clk = "l4_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* aess -> l4_abe */ +static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = { + .master = &omap44xx_aess_hwmod, + .slave = &omap44xx_l4_abe_hwmod, + .clk = "ocp_abe_iclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dsp -> l4_abe */ +static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = { + .master = &omap44xx_dsp_hwmod, + .slave = &omap44xx_l4_abe_hwmod, + .clk = "ocp_abe_iclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_1 -> l4_abe */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = { + .master = &omap44xx_l3_main_1_hwmod, + .slave = &omap44xx_l4_abe_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mpu -> l4_abe */ +static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = { + .master = &omap44xx_mpu_hwmod, + .slave = &omap44xx_l4_abe_hwmod, + .clk = "ocp_abe_iclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_1 -> l4_cfg */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = { + .master = &omap44xx_l3_main_1_hwmod, + .slave = &omap44xx_l4_cfg_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_2 -> l4_per */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_l4_per_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_cfg -> l4_wkup */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_l4_wkup_hwmod, + .clk = "l4_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mpu -> mpu_private */ +static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = { + .master = &omap44xx_mpu_hwmod, + .slave = &omap44xx_mpu_private_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = { + { + .pa_start = 0x401f1000, + .pa_end = 0x401f13ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> aess */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_aess_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_aess_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = { + { + .pa_start = 0x490f1000, + .pa_end = 0x490f13ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> aess (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_aess_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_aess_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = { + { + .pa_start = 0x4a304000, + .pa_end = 0x4a30401f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_wkup -> counter_32k */ +static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = { + .master = &omap44xx_l4_wkup_hwmod, + .slave = &omap44xx_counter_32k_hwmod, + .clk = "l4_wkup_clk_mux_ck", + .addr = omap44xx_counter_32k_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = { + { + .pa_start = 0x4a056000, + .pa_end = 0x4a056fff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_cfg -> dma_system */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_dma_system_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_dma_system_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = { + { + .name = "mpu", + .pa_start = 0x4012e000, + .pa_end = 0x4012e07f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> dmic */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_dmic_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_dmic_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = { + { + .name = "dma", + .pa_start = 0x4902e000, + .pa_end = 0x4902e07f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> dmic (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_dmic_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_dmic_dma_addrs, + .user = OCP_USER_SDMA, +}; + +/* dsp -> iva */ +static struct omap_hwmod_ocp_if omap44xx_dsp__iva = { + .master = &omap44xx_dsp_hwmod, + .slave = &omap44xx_iva_hwmod, + .clk = "dpll_iva_m5x2_ck", + .user = OCP_USER_DSP, +}; + +/* l4_cfg -> dsp */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_dsp_hwmod, + .clk = "l4_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = { + { + .pa_start = 0x58000000, + .pa_end = 0x5800007f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l3_main_2 -> dss */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_dss_hwmod, + .clk = "dss_fck", + .addr = omap44xx_dss_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = { + { + .pa_start = 0x48040000, + .pa_end = 0x4804007f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> dss */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_dss_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_dss_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = { + { + .pa_start = 0x58001000, + .pa_end = 0x58001fff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l3_main_2 -> dss_dispc */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_dss_dispc_hwmod, + .clk = "dss_fck", + .addr = omap44xx_dss_dispc_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = { + { + .pa_start = 0x48041000, + .pa_end = 0x48041fff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> dss_dispc */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_dss_dispc_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_dss_dispc_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = { + { + .pa_start = 0x58004000, + .pa_end = 0x580041ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l3_main_2 -> dss_dsi1 */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_dss_dsi1_hwmod, + .clk = "dss_fck", + .addr = omap44xx_dss_dsi1_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = { + { + .pa_start = 0x48044000, + .pa_end = 0x480441ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> dss_dsi1 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_dss_dsi1_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_dss_dsi1_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = { + { + .pa_start = 0x58005000, + .pa_end = 0x580051ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l3_main_2 -> dss_dsi2 */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_dss_dsi2_hwmod, + .clk = "dss_fck", + .addr = omap44xx_dss_dsi2_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = { + { + .pa_start = 0x48045000, + .pa_end = 0x480451ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> dss_dsi2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_dss_dsi2_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_dss_dsi2_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = { + { + .pa_start = 0x58006000, + .pa_end = 0x58006fff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l3_main_2 -> dss_hdmi */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_dss_hdmi_hwmod, + .clk = "dss_fck", + .addr = omap44xx_dss_hdmi_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = { + { + .pa_start = 0x48046000, + .pa_end = 0x48046fff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> dss_hdmi */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_dss_hdmi_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_dss_hdmi_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = { + { + .pa_start = 0x58002000, + .pa_end = 0x580020ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l3_main_2 -> dss_rfbi */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_dss_rfbi_hwmod, + .clk = "dss_fck", + .addr = omap44xx_dss_rfbi_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = { + { + .pa_start = 0x48042000, + .pa_end = 0x480420ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> dss_rfbi */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_dss_rfbi_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_dss_rfbi_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = { + { + .pa_start = 0x58003000, + .pa_end = 0x580030ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l3_main_2 -> dss_venc */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_dss_venc_hwmod, + .clk = "dss_fck", + .addr = omap44xx_dss_venc_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = { + { + .pa_start = 0x48043000, + .pa_end = 0x480430ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> dss_venc */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_dss_venc_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_dss_venc_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = { + { + .pa_start = 0x4a310000, + .pa_end = 0x4a3101ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_wkup -> gpio1 */ +static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = { + .master = &omap44xx_l4_wkup_hwmod, + .slave = &omap44xx_gpio1_hwmod, + .clk = "l4_wkup_clk_mux_ck", + .addr = omap44xx_gpio1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = { + { + .pa_start = 0x48055000, + .pa_end = 0x480551ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> gpio2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_gpio2_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_gpio2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = { + { + .pa_start = 0x48057000, + .pa_end = 0x480571ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> gpio3 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_gpio3_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_gpio3_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = { + { + .pa_start = 0x48059000, + .pa_end = 0x480591ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> gpio4 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_gpio4_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_gpio4_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = { + { + .pa_start = 0x4805b000, + .pa_end = 0x4805b1ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> gpio5 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_gpio5_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_gpio5_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = { + { + .pa_start = 0x4805d000, + .pa_end = 0x4805d1ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> gpio6 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_gpio6_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_gpio6_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = { + { + .pa_start = 0x4a058000, + .pa_end = 0x4a05bfff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_cfg -> hsi */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_hsi_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_hsi_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = { + { + .pa_start = 0x48070000, + .pa_end = 0x480700ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> i2c1 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_i2c1_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_i2c1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = { + { + .pa_start = 0x48072000, + .pa_end = 0x480720ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> i2c2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_i2c2_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_i2c2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = { + { + .pa_start = 0x48060000, + .pa_end = 0x480600ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> i2c3 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_i2c3_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_i2c3_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = { + { + .pa_start = 0x48350000, + .pa_end = 0x483500ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> i2c4 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_i2c4_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_i2c4_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_2 -> ipu */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_ipu_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = { + { + .pa_start = 0x52000000, + .pa_end = 0x520000ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l3_main_2 -> iss */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_iss_hwmod, + .clk = "l3_div_ck", + .addr = omap44xx_iss_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = { + { + .pa_start = 0x5a000000, + .pa_end = 0x5a07ffff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l3_main_2 -> iva */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_iva_hwmod, + .clk = "l3_div_ck", + .addr = omap44xx_iva_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = { + { + .pa_start = 0x4a31c000, + .pa_end = 0x4a31c07f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_wkup -> kbd */ +static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = { + .master = &omap44xx_l4_wkup_hwmod, + .slave = &omap44xx_kbd_hwmod, + .clk = "l4_wkup_clk_mux_ck", + .addr = omap44xx_kbd_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = { + { + .pa_start = 0x4a0f4000, + .pa_end = 0x4a0f41ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_cfg -> mailbox */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_mailbox_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mailbox_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = { + { + .name = "mpu", + .pa_start = 0x40122000, + .pa_end = 0x401220ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> mcbsp1 */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_mcbsp1_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_mcbsp1_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = { + { + .name = "dma", + .pa_start = 0x49022000, + .pa_end = 0x490220ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> mcbsp1 (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_mcbsp1_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_mcbsp1_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = { + { + .name = "mpu", + .pa_start = 0x40124000, + .pa_end = 0x401240ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> mcbsp2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_mcbsp2_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_mcbsp2_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = { + { + .name = "dma", + .pa_start = 0x49024000, + .pa_end = 0x490240ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> mcbsp2 (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_mcbsp2_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_mcbsp2_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = { + { + .name = "mpu", + .pa_start = 0x40126000, + .pa_end = 0x401260ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> mcbsp3 */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_mcbsp3_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_mcbsp3_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = { + { + .name = "dma", + .pa_start = 0x49026000, + .pa_end = 0x490260ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> mcbsp3 (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_mcbsp3_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_mcbsp3_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = { + { + .pa_start = 0x48096000, + .pa_end = 0x480960ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> mcbsp4 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_mcbsp4_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mcbsp4_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = { + { + .pa_start = 0x40132000, + .pa_end = 0x4013207f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> mcpdm */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_mcpdm_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_mcpdm_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = { + { + .pa_start = 0x49032000, + .pa_end = 0x4903207f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> mcpdm (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_mcpdm_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_mcpdm_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = { + { + .pa_start = 0x48098000, + .pa_end = 0x480981ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> mcspi1 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_mcspi1_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mcspi1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = { + { + .pa_start = 0x4809a000, + .pa_end = 0x4809a1ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> mcspi2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_mcspi2_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mcspi2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = { + { + .pa_start = 0x480b8000, + .pa_end = 0x480b81ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> mcspi3 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_mcspi3_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mcspi3_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = { + { + .pa_start = 0x480ba000, + .pa_end = 0x480ba1ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> mcspi4 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_mcspi4_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mcspi4_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = { + { + .pa_start = 0x4809c000, + .pa_end = 0x4809c3ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> mmc1 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_mmc1_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mmc1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = { + { + .pa_start = 0x480b4000, + .pa_end = 0x480b43ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> mmc2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_mmc2_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mmc2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = { + { + .pa_start = 0x480ad000, + .pa_end = 0x480ad3ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> mmc3 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_mmc3_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mmc3_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = { + { + .pa_start = 0x480d1000, + .pa_end = 0x480d13ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> mmc4 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_mmc4_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mmc4_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = { + { + .pa_start = 0x480d5000, + .pa_end = 0x480d53ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> mmc5 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_mmc5_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mmc5_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = { + { + .pa_start = 0x4a0dd000, + .pa_end = 0x4a0dd03f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_cfg -> smartreflex_core */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_smartreflex_core_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_smartreflex_core_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = { + { + .pa_start = 0x4a0db000, + .pa_end = 0x4a0db03f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_cfg -> smartreflex_iva */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_smartreflex_iva_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_smartreflex_iva_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = { + { + .pa_start = 0x4a0d9000, + .pa_end = 0x4a0d903f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_cfg -> smartreflex_mpu */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_smartreflex_mpu_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_smartreflex_mpu_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = { + { + .pa_start = 0x4a0f6000, + .pa_end = 0x4a0f6fff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_cfg -> spinlock */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_spinlock_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_spinlock_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = { + { + .pa_start = 0x4a318000, + .pa_end = 0x4a31807f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_wkup -> timer1 */ +static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = { + .master = &omap44xx_l4_wkup_hwmod, + .slave = &omap44xx_timer1_hwmod, + .clk = "l4_wkup_clk_mux_ck", + .addr = omap44xx_timer1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = { + { + .pa_start = 0x48032000, + .pa_end = 0x4803207f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> timer2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_timer2_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_timer2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = { + { + .pa_start = 0x48034000, + .pa_end = 0x4803407f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> timer3 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_timer3_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_timer3_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = { + { + .pa_start = 0x48036000, + .pa_end = 0x4803607f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> timer4 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_timer4_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_timer4_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = { + { + .pa_start = 0x40138000, + .pa_end = 0x4013807f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> timer5 */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_timer5_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_timer5_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = { + { + .pa_start = 0x49038000, + .pa_end = 0x4903807f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> timer5 (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_timer5_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_timer5_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = { + { + .pa_start = 0x4013a000, + .pa_end = 0x4013a07f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> timer6 */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_timer6_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_timer6_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = { + { + .pa_start = 0x4903a000, + .pa_end = 0x4903a07f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> timer6 (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_timer6_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_timer6_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = { + { + .pa_start = 0x4013c000, + .pa_end = 0x4013c07f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> timer7 */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_timer7_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_timer7_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = { + { + .pa_start = 0x4903c000, + .pa_end = 0x4903c07f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> timer7 (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_timer7_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_timer7_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = { + { + .pa_start = 0x4013e000, + .pa_end = 0x4013e07f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> timer8 */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_timer8_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_timer8_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = { + { + .pa_start = 0x4903e000, + .pa_end = 0x4903e07f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> timer8 (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_timer8_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_timer8_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = { + { + .pa_start = 0x4803e000, + .pa_end = 0x4803e07f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> timer9 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_timer9_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_timer9_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = { + { + .pa_start = 0x48086000, + .pa_end = 0x4808607f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> timer10 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_timer10_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_timer10_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = { + { + .pa_start = 0x48088000, + .pa_end = 0x4808807f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> timer11 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_timer11_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_timer11_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod omap44xx_usb_host_hs_hwmod = { - .name = "usb_host_hs", - .class = &omap44xx_usb_host_hs_hwmod_class, - .clkdm_name = "l3_init_clkdm", - .main_clk = "usb_host_hs_fck", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, +static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = { + { + .pa_start = 0x4806a000, + .pa_end = 0x4806a0ff, + .flags = ADDR_TYPE_RT }, - .mpu_irqs = omap44xx_usb_host_hs_irqs, + { } +}; - /* - * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock - * id: i660 - * - * Description: - * In the following configuration : - * - USBHOST module is set to smart-idle mode - * - PRCM asserts idle_req to the USBHOST module ( This typically - * happens when the system is going to a low power mode : all ports - * have been suspended, the master part of the USBHOST module has - * entered the standby state, and SW has cut the functional clocks) - * - an USBHOST interrupt occurs before the module is able to answer - * idle_ack, typically a remote wakeup IRQ. - * Then the USB HOST module will enter a deadlock situation where it - * is no more accessible nor functional. - * - * Workaround: - * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE - */ +/* l4_per -> uart1 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_uart1_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_uart1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; - /* - * Errata: USB host EHCI may stall when entering smart-standby mode - * Id: i571 - * - * Description: - * When the USBHOST module is set to smart-standby mode, and when it is - * ready to enter the standby state (i.e. all ports are suspended and - * all attached devices are in suspend mode), then it can wrongly assert - * the Mstandby signal too early while there are still some residual OCP - * transactions ongoing. If this condition occurs, the internal state - * machine may go to an undefined state and the USB link may be stuck - * upon the next resume. - * - * Workaround: - * Don't use smart standby; use only force standby, - * hence HWMOD_SWSUP_MSTANDBY - */ +static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = { + { + .pa_start = 0x4806c000, + .pa_end = 0x4806c0ff, + .flags = ADDR_TYPE_RT + }, + { } +}; - /* - * During system boot; If the hwmod framework resets the module - * the module will have smart idle settings; which can lead to deadlock - * (above Errata Id:i660); so, dont reset the module during boot; - * Use HWMOD_INIT_NO_RESET. - */ +/* l4_per -> uart2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_uart2_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_uart2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; - .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY | - HWMOD_INIT_NO_RESET, +static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = { + { + .pa_start = 0x48020000, + .pa_end = 0x480200ff, + .flags = ADDR_TYPE_RT + }, + { } }; -/* - * 'usb_tll_hs' class - * usb_tll_hs module is the adapter on the usb_host_hs ports - */ -static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | - SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | - SYSC_HAS_AUTOIDLE), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, +/* l4_per -> uart3 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_uart3_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_uart3_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = { - .name = "usb_tll_hs", - .sysc = &omap44xx_usb_tll_hs_sysc, +static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = { + { + .pa_start = 0x4806e000, + .pa_end = 0x4806e0ff, + .flags = ADDR_TYPE_RT + }, + { } }; -static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = { - { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } +/* l4_per -> uart4 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_uart4_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_uart4_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = { + { + .name = "uhh", + .pa_start = 0x4a064000, + .pa_end = 0x4a0647ff, + .flags = ADDR_TYPE_RT + }, + { + .name = "ohci", + .pa_start = 0x4a064800, + .pa_end = 0x4a064bff, + }, + { + .name = "ehci", + .pa_start = 0x4a064c00, + .pa_end = 0x4a064fff, + }, + {} +}; + +/* l4_cfg -> usb_host_hs */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_usb_host_hs_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_usb_host_hs_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = { + { + .pa_start = 0x4a0ab000, + .pa_end = 0x4a0ab003, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_cfg -> usb_otg_hs */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_usb_otg_hs_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_usb_otg_hs_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = { @@ -4721,6 +4609,7 @@ static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = { {} }; +/* l4_cfg -> usb_tll_hs */ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = { .master = &omap44xx_l4_cfg_hwmod, .slave = &omap44xx_usb_tll_hs_hwmod, @@ -4729,19 +4618,58 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = { - .name = "usb_tll_hs", - .class = &omap44xx_usb_tll_hs_hwmod_class, - .clkdm_name = "l3_init_clkdm", - .main_clk = "usb_tll_hs_ick", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, - }, +static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = { + { + .pa_start = 0x4a314000, + .pa_end = 0x4a31407f, + .flags = ADDR_TYPE_RT }, - .mpu_irqs = omap44xx_usb_tll_hs_irqs, + { } +}; + +/* l4_wkup -> wd_timer2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = { + .master = &omap44xx_l4_wkup_hwmod, + .slave = &omap44xx_wd_timer2_hwmod, + .clk = "l4_wkup_clk_mux_ck", + .addr = omap44xx_wd_timer2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = { + { + .pa_start = 0x40130000, + .pa_end = 0x4013007f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> wd_timer3 */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_wd_timer3_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_wd_timer3_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = { + { + .pa_start = 0x49030000, + .pa_end = 0x4903007f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> wd_timer3 (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_wd_timer3_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_wd_timer3_dma_addrs, + .user = OCP_USER_SDMA, }; static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { -- GitLab