From 7f97f4d0b4639cddcaad08b0b957b63ff4dcfc18 Mon Sep 17 00:00:00 2001 From: Hao Fang Date: Thu, 11 Jul 2019 14:41:51 +0800 Subject: [PATCH] ACC: crypto/hisilicon: fix for RAS err print level and add RAS enable after control reset driver inclusion category: bugfix bugzilla: NA CVE: NA RAS err print level from dev_warn to dev_err. RAS CE/NFE/FE err enable need reconfig after control reset. Signed-off-by: Hao Fang Reviewed-by: wangzhou Signed-off-by: lingmingqiang Signed-off-by: Yang Yingliang --- drivers/crypto/hisilicon/hpre/hpre_main.c | 19 +++++++++++++++---- drivers/crypto/hisilicon/qm.c | 10 +++++----- drivers/crypto/hisilicon/zip/zip_main.c | 8 ++++---- 3 files changed, 24 insertions(+), 13 deletions(-) diff --git a/drivers/crypto/hisilicon/hpre/hpre_main.c b/drivers/crypto/hisilicon/hpre/hpre_main.c index 8083f9fb39d8..361b95eb45bc 100644 --- a/drivers/crypto/hisilicon/hpre/hpre_main.c +++ b/drivers/crypto/hisilicon/hpre/hpre_main.c @@ -56,6 +56,13 @@ #define HPRE_CORE_HTBT_WARN_OFFSET 0x8c #define HPRE_CORE_IS_SCHD_OFFSET 0x90 +#define HPRE_RAS_CE_ENB 0x301410 +#define HPRE_HAC_RAS_CE_ENABLE 0x3f +#define HPRE_RAS_NFE_ENB 0x301414 +#define HPRE_HAC_RAS_NFE_ENABLE 0xc0 +#define HPRE_RAS_FE_ENB 0x301418 +#define HPRE_HAC_RAS_FE_ENABLE 0 + #define HPRE_CORE_ENB (HPRE_CLSTR_BASE + HPRE_CORE_EN_OFFSET) #define HPRE_CORE_INI_CFG (HPRE_CLSTR_BASE + HPRE_CORE_INI_CFG_OFFSET) #define HPRE_CORE_INI_STATUS (HPRE_CLSTR_BASE + HPRE_CORE_INI_STATUS_OFFSET) @@ -432,12 +439,16 @@ static void hpre_hw_error_set_state(struct hpre *hpre, bool state) { struct hisi_qm *qm = &hpre->qm; - if (state) + if (state) { /* enable hpre hw error interrupts */ writel(HPRE_CORE_INT_ENABLE, qm->io_base + HPRE_INT_MASK); - else + writel(HPRE_HAC_RAS_CE_ENABLE, qm->io_base + HPRE_RAS_CE_ENB); + writel(HPRE_HAC_RAS_NFE_ENABLE, qm->io_base + HPRE_RAS_NFE_ENB); + writel(HPRE_HAC_RAS_FE_ENABLE, qm->io_base + HPRE_RAS_FE_ENB); + } else { /* disable hpre hw error interrupts */ writel(HPRE_CORE_INT_DISABLE, qm->io_base + HPRE_INT_MASK); + } } static inline struct hisi_qm *file_to_qm(struct hpre_debugfs_file *file) @@ -1006,7 +1017,7 @@ static void hpre_log_hw_error(struct hpre *hpre, u32 err_sts) while (err->msg) { if (err->int_msk & err_sts) - dev_warn(dev, "%s [error status=0x%x] found\n", + dev_err(dev, "%s [error status=0x%x] found\n", err->msg, err->int_msk); err++; } @@ -1219,7 +1230,7 @@ static pci_ers_result_t hpre_slot_reset(struct pci_dev *pdev) /* reset hpre controller */ ret = hpre_controller_reset(hpre); if (ret) { - dev_warn(&pdev->dev, "hpre controller reset failed (%d)\n", + dev_err(&pdev->dev, "hpre controller reset failed (%d)\n", ret); return PCI_ERS_RESULT_DISCONNECT; } diff --git a/drivers/crypto/hisilicon/qm.c b/drivers/crypto/hisilicon/qm.c index 7317853f3695..3d075722b117 100644 --- a/drivers/crypto/hisilicon/qm.c +++ b/drivers/crypto/hisilicon/qm.c @@ -535,7 +535,7 @@ static irqreturn_t qm_abnormal_irq(int irq, void *data) while (err->msg) { if (err->int_msk & error_status) - dev_warn(dev, "%s [error status=0x%x] found\n", + dev_err(dev, "%s [error status=0x%x] found\n", err->msg, err->int_msk); err++; @@ -971,7 +971,7 @@ static void qm_log_hw_error(struct hisi_qm *qm, u32 error_status) while (err->msg) { if (err->int_msk & error_status) { - dev_warn(dev, "%s [error status=0x%x] found\n", + dev_err(dev, "%s [error status=0x%x] found\n", err->msg, err->int_msk); if (err->int_msk & QM_DB_TIMEOUT) { @@ -980,7 +980,7 @@ static void qm_log_hw_error(struct hisi_qm *qm, u32 error_status) type = (reg_val & QM_DB_TIMEOUT_TYPE) >> QM_DB_TIMEOUT_TYPE_SHIFT; vf_num = reg_val & QM_DB_TIMEOUT_VF; - dev_warn(dev, "qm %s doorbell timeout in function %u\n", + dev_err(dev, "qm %s doorbell timeout in function %u\n", qm_db_timeout[type], vf_num); } else if (err->int_msk & QM_OF_FIFO_OF) { reg_val = readl(qm->io_base + @@ -990,7 +990,7 @@ static void qm_log_hw_error(struct hisi_qm *qm, u32 error_status) vf_num = reg_val & QM_FIFO_OVERFLOW_VF; if (type < ARRAY_SIZE(qm_fifo_overflow)) - dev_warn(dev, "qm %s fifo overflow in function %u\n", + dev_err(dev, "qm %s fifo overflow in function %u\n", qm_fifo_overflow[type], vf_num); else @@ -1517,7 +1517,7 @@ static int hisi_qm_uacce_mmap(struct uacce_queue *q, case UACCE_QFRT_DUS: if (qm->use_dma_api) { if (sz != qp->qdma.size) { - dev_warn(dev, "wrong queue size %ld vs %ld\n", + dev_err(dev, "wrong queue size %ld vs %ld\n", sz, qp->qdma.size); return -EINVAL; } diff --git a/drivers/crypto/hisilicon/zip/zip_main.c b/drivers/crypto/hisilicon/zip/zip_main.c index 15d4a9b5f513..fbe6abb8f3ce 100644 --- a/drivers/crypto/hisilicon/zip/zip_main.c +++ b/drivers/crypto/hisilicon/zip/zip_main.c @@ -930,16 +930,16 @@ static void hisi_zip_log_hw_error(struct hisi_zip *hisi_zip, u32 err_sts) while (err->msg) { if (err->int_msk & err_sts) { - dev_warn(dev, "%s [error status=0x%x] found\n", + dev_err(dev, "%s [error status=0x%x] found\n", err->msg, err->int_msk); if (err->int_msk & HZIP_CORE_INT_STATUS_M_ECC) { err_val = readl(hisi_zip->qm.io_base + HZIP_CORE_SRAM_ECC_ERR_INFO); - dev_warn(dev, "hisi-zip multi ecc sram num=0x%x\n", + dev_err(dev, "hisi-zip multi ecc sram num=0x%x\n", ((err_val >> SRAM_ECC_ERR_NUM_SHIFT) & 0xFF)); - dev_warn(dev, "hisi-zip multi ecc sram addr=0x%x\n", + dev_err(dev, "hisi-zip multi ecc sram addr=0x%x\n", (err_val >> SRAM_ECC_ERR_ADDR_SHIFT)); } } @@ -1280,7 +1280,7 @@ static pci_ers_result_t hisi_zip_slot_reset(struct pci_dev *pdev) /* reset zip controller */ ret = hisi_zip_controller_reset(hisi_zip); if (ret) { - dev_warn(&pdev->dev, "hisi_zip controller reset failed (%d)\n", + dev_err(&pdev->dev, "hisi_zip controller reset failed (%d)\n", ret); return PCI_ERS_RESULT_DISCONNECT; } -- GitLab