net: hinic: Add Hardware Abstract Layer

driver inclusion
category:bugfix
bugzilla:4472
CVE:NA
------------------------------------------------------------------

Add Hardware Abstract Layer support (Hi1822 SDK layer), include:
1. device initialization
2. configuration management
3. basic management and IO infrastructure
4. provide common NIC and stateful services APIs
5. etc.
Signed-off-by: NXue <xuechaojing@huawei.com>
Reviewed-by: Nchiqijun <chiqijun@huawei.com>
Signed-off-by: NYang Yingliang <yangyingliang@huawei.com>

drivers/net/ethernet/huawei/Kconfig

@@ -5,6 +5,7 @@
 config NET_VENDOR_HUAWEI
 	bool "Huawei devices"
 	default y
+	depends on ARM64
 	---help---
 	  If you have a network (Ethernet) card belonging to this class, say Y.
 	  Note that the answer to this question doesn't directly affect the

drivers/net/ethernet/huawei/hinic/Kconfig

@@ -4,9 +4,10 @@
 
 config HINIC
 	tristate "Huawei Intelligent PCIE Network Interface Card"
-	depends on (PCI_MSI && (X86 || ARM64))
+	default n
+	depends on PCI_MSI && NUMA && PCI_IOV && DCB
 	---help---
 	  This driver supports HiNIC PCIE Ethernet cards.
 	  To compile this driver as part of the kernel, choose Y here.
 	  If unsure, choose N.
-	  The default is compiled as module.
+	  The default is N.

drivers/net/ethernet/huawei/hinic/Makefile

 obj-$(CONFIG_HINIC) += hinic.o
 
-hinic-y := hinic_main.o hinic_tx.o hinic_rx.o hinic_port.o hinic_hw_dev.o \
-	   hinic_hw_io.o hinic_hw_qp.o hinic_hw_cmdq.o hinic_hw_wq.o \
-	   hinic_hw_mgmt.o hinic_hw_api_cmd.o hinic_hw_eqs.o hinic_hw_if.o \
-	   hinic_common.o
+hinic-y := hinic_nic_cfg.o hinic_nic_io.o hinic_nic_dbg.o \
+	   hinic_hwif.o hinic_msix_attr.o hinic_eqs.o \
+	   hinic_mbox.o hinic_api_cmd.o hinic_mgmt.o \
+	   hinic_wq.o hinic_cmdq.o hinic_hwdev.o hinic_cfg.o \
+	   ossl_knl_linux.o \
+	   hinic_sml_counter.o hinic_sml_lt.o \
+	   hinic_multi_host_mgmt.o

drivers/net/ethernet/huawei/hinic/hinic_api_cmd.h

+/* SPDX-License-Identifier: GPL-2.0*/
+/* Huawei HiNIC PCI Express Linux driver
+ * Copyright(c) 2017 Huawei Technologies Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ *
+ */
+
+#ifndef HINIC_API_CMD_H_
+#define HINIC_API_CMD_H_
+
+#define HINIC_API_CMD_CELL_CTRL_CELL_LEN_SHIFT			0
+#define HINIC_API_CMD_CELL_CTRL_RD_DMA_ATTR_OFF_SHIFT		16
+#define HINIC_API_CMD_CELL_CTRL_WR_DMA_ATTR_OFF_SHIFT		24
+#define HINIC_API_CMD_CELL_CTRL_XOR_CHKSUM_SHIFT		56
+
+#define HINIC_API_CMD_CELL_CTRL_CELL_LEN_MASK			0x3FU
+#define HINIC_API_CMD_CELL_CTRL_RD_DMA_ATTR_OFF_MASK		0x3FU
+#define HINIC_API_CMD_CELL_CTRL_WR_DMA_ATTR_OFF_MASK		0x3FU
+#define HINIC_API_CMD_CELL_CTRL_XOR_CHKSUM_MASK			0xFFU
+
+#define HINIC_API_CMD_CELL_CTRL_SET(val, member)		\
+		((((u64)val) & HINIC_API_CMD_CELL_CTRL_##member##_MASK) << \
+		HINIC_API_CMD_CELL_CTRL_##member##_SHIFT)
+
+#define HINIC_API_CMD_DESC_API_TYPE_SHIFT			0
+#define HINIC_API_CMD_DESC_RD_WR_SHIFT				1
+#define HINIC_API_CMD_DESC_MGMT_BYPASS_SHIFT			2
+#define HINIC_API_CMD_DESC_RESP_AEQE_EN_SHIFT			3
+#define HINIC_API_CMD_DESC_PRIV_DATA_SHIFT			8
+#define HINIC_API_CMD_DESC_DEST_SHIFT				32
+#define HINIC_API_CMD_DESC_SIZE_SHIFT				40
+#define HINIC_API_CMD_DESC_XOR_CHKSUM_SHIFT			56
+
+#define HINIC_API_CMD_DESC_API_TYPE_MASK			0x1U
+#define HINIC_API_CMD_DESC_RD_WR_MASK				0x1U
+#define HINIC_API_CMD_DESC_MGMT_BYPASS_MASK			0x1U
+#define HINIC_API_CMD_DESC_RESP_AEQE_EN_MASK			0x1U
+#define HINIC_API_CMD_DESC_DEST_MASK				0x1FU
+#define HINIC_API_CMD_DESC_SIZE_MASK				0x7FFU
+#define HINIC_API_CMD_DESC_XOR_CHKSUM_MASK			0xFFU
+#define HINIC_API_CMD_DESC_PRIV_DATA_MASK			0xFFFFFFU
+
+#define HINIC_API_CMD_DESC_SET(val, member)			\
+		((((u64)val) & HINIC_API_CMD_DESC_##member##_MASK) << \
+		HINIC_API_CMD_DESC_##member##_SHIFT)
+
+#define HINIC_API_CMD_STATUS_HEADER_VALID_SHIFT		0
+#define HINIC_API_CMD_STATUS_HEADER_CHAIN_ID_SHIFT		16
+
+#define HINIC_API_CMD_STATUS_HEADER_VALID_MASK			0xFFU
+#define HINIC_API_CMD_STATUS_HEADER_CHAIN_ID_MASK		0xFFU
+
+#define HINIC_API_CMD_STATUS_VALID_CODE				0xFF
+
+#define HINIC_API_CMD_STATUS_HEADER_GET(val, member)		\
+	      (((val) >> HINIC_API_CMD_STATUS_HEADER_##member##_SHIFT) & \
+	      HINIC_API_CMD_STATUS_HEADER_##member##_MASK)
+
+#define HINIC_API_CMD_CHAIN_REQ_RESTART_SHIFT			1
+#define HINIC_API_CMD_CHAIN_REQ_WB_TRIGGER_SHIFT		2
+
+#define HINIC_API_CMD_CHAIN_REQ_RESTART_MASK			0x1U
+#define HINIC_API_CMD_CHAIN_REQ_WB_TRIGGER_MASK			0x1U
+
+#define HINIC_API_CMD_CHAIN_REQ_SET(val, member)		\
+	       (((val) & HINIC_API_CMD_CHAIN_REQ_##member##_MASK) << \
+	       HINIC_API_CMD_CHAIN_REQ_##member##_SHIFT)
+
+#define HINIC_API_CMD_CHAIN_REQ_GET(val, member)		\
+	      (((val) >> HINIC_API_CMD_CHAIN_REQ_##member##_SHIFT) & \
+	      HINIC_API_CMD_CHAIN_REQ_##member##_MASK)
+
+#define HINIC_API_CMD_CHAIN_REQ_CLEAR(val, member)		\
+	((val) & (~(HINIC_API_CMD_CHAIN_REQ_##member##_MASK	\
+		<< HINIC_API_CMD_CHAIN_REQ_##member##_SHIFT)))
+
+#define HINIC_API_CMD_CHAIN_CTRL_RESTART_EN_SHIFT		1
+#define HINIC_API_CMD_CHAIN_CTRL_XOR_ERR_SHIFT			2
+#define HINIC_API_CMD_CHAIN_CTRL_AEQE_EN_SHIFT			4
+#define HINIC_API_CMD_CHAIN_CTRL_AEQ_ID_SHIFT			8
+#define HINIC_API_CMD_CHAIN_CTRL_XOR_CHK_EN_SHIFT		28
+#define HINIC_API_CMD_CHAIN_CTRL_CELL_SIZE_SHIFT		30
+
+#define HINIC_API_CMD_CHAIN_CTRL_RESTART_EN_MASK		0x1U
+#define HINIC_API_CMD_CHAIN_CTRL_XOR_ERR_MASK			0x1U
+#define HINIC_API_CMD_CHAIN_CTRL_AEQE_EN_MASK			0x1U
+#define HINIC_API_CMD_CHAIN_CTRL_AEQ_ID_MASK			0x3U
+#define HINIC_API_CMD_CHAIN_CTRL_XOR_CHK_EN_MASK		0x3U
+#define HINIC_API_CMD_CHAIN_CTRL_CELL_SIZE_MASK			0x3U
+
+#define HINIC_API_CMD_CHAIN_CTRL_SET(val, member)		\
+	(((val) & HINIC_API_CMD_CHAIN_CTRL_##member##_MASK) << \
+	HINIC_API_CMD_CHAIN_CTRL_##member##_SHIFT)
+
+#define HINIC_API_CMD_CHAIN_CTRL_CLEAR(val, member)		\
+	((val) & (~(HINIC_API_CMD_CHAIN_CTRL_##member##_MASK	\
+		<< HINIC_API_CMD_CHAIN_CTRL_##member##_SHIFT)))
+
+#define HINIC_API_CMD_RESP_HEAD_VALID_MASK		0xFF
+#define HINIC_API_CMD_RESP_HEAD_VALID_CODE		0xFF
+
+#define HINIC_API_CMD_RESP_HEADER_VALID(val)	\
+		(((val) & HINIC_API_CMD_RESP_HEAD_VALID_MASK) == \
+		HINIC_API_CMD_RESP_HEAD_VALID_CODE)
+
+#define HINIC_API_CMD_RESP_HEAD_STATUS_SHIFT		8
+#define HINIC_API_CMD_RESP_HEAD_STATUS_MASK		0xFFU
+
+#define HINIC_API_CMD_RESP_HEAD_ERR_CODE		0x1
+#define HINIC_API_CMD_RESP_HEAD_ERR(val)	\
+		((((val) >> HINIC_API_CMD_RESP_HEAD_STATUS_SHIFT) & \
+		HINIC_API_CMD_RESP_HEAD_STATUS_MASK) == \
+		HINIC_API_CMD_RESP_HEAD_ERR_CODE)
+
+#define HINIC_API_CMD_RESP_HEAD_CHAIN_ID_SHIFT		16
+#define HINIC_API_CMD_RESP_HEAD_CHAIN_ID_MASK		0xFF
+
+#define HINIC_API_CMD_RESP_RESERVED			3
+#define HINIC_API_CMD_RESP_HEAD_CHAIN_ID(val)	\
+		(((val) >> HINIC_API_CMD_RESP_HEAD_CHAIN_ID_SHIFT) & \
+		HINIC_API_CMD_RESP_HEAD_CHAIN_ID_MASK)
+
+#define HINIC_API_CMD_RESP_HEAD_DRIVER_PRIV_SHIFT	40
+#define HINIC_API_CMD_RESP_HEAD_DRIVER_PRIV_MASK	0xFFFFFFU
+
+#define HINIC_API_CMD_RESP_HEAD_DRIVER_PRIV(val)	\
+		(u16)(((val) >> HINIC_API_CMD_RESP_HEAD_DRIVER_PRIV_SHIFT) & \
+		HINIC_API_CMD_RESP_HEAD_DRIVER_PRIV_MASK)
+
+#define HINIC_API_CMD_STATUS_HEAD_VALID_MASK		0xFFU
+#define HINIC_API_CMD_STATUS_HEAD_VALID_SHIFT		0
+
+#define HINIC_API_CMD_STATUS_HEAD_CHAIN_ID_MASK	0xFFU
+#define HINIC_API_CMD_STATUS_HEAD_CHAIN_ID_VALID_SHIFT	16
+
+#define HINIC_API_CMD_STATUS_CONS_IDX_MASK		0xFFFFFFU
+#define HINIC_API_CMD_STATUS_CONS_IDX_SHIFT		0
+
+#define HINIC_API_CMD_STATUS_FSM_MASK			0xFU
+#define HINIC_API_CMD_STATUS_FSM_SHIFT			24
+
+#define HINIC_API_CMD_STATUS_CHKSUM_ERR_MASK		0x3U
+#define HINIC_API_CMD_STATUS_CHKSUM_ERR_SHIFT		28
+
+#define HINIC_API_CMD_STATUS_CPLD_ERR_MASK		0x1U
+#define HINIC_API_CMD_STATUS_CPLD_ERR_SHIFT		30
+
+#define HINIC_API_CMD_STATUS_CHAIN_ID(val) \
+		(((val) >> HINIC_API_CMD_STATUS_HEAD_CHAIN_ID_VALID_SHIFT) & \
+		HINIC_API_CMD_STATUS_HEAD_VALID_MASK)
+
+#define HINIC_API_CMD_STATUS_CONS_IDX(val) \
+		((val) & HINIC_API_CMD_STATUS_CONS_IDX_MASK)
+
+#define HINIC_API_CMD_STATUS_CHKSUM_ERR(val) \
+		(((val) >> HINIC_API_CMD_STATUS_CHKSUM_ERR_SHIFT) & \
+		HINIC_API_CMD_STATUS_CHKSUM_ERR_MASK)
+
+#define HINIC_API_CMD_STATUS_GET(val, member)			\
+		(((val) >> HINIC_API_CMD_STATUS_##member##_SHIFT) & \
+		HINIC_API_CMD_STATUS_##member##_MASK)
+
+enum hinic_api_cmd_chain_type {
+	/* write command with completion notification */
+	HINIC_API_CMD_WRITE			= 0,
+	/* read command with completion notification */
+	HINIC_API_CMD_READ			= 1,
+	/* write to mgmt cpu command with completion  */
+	HINIC_API_CMD_WRITE_TO_MGMT_CPU		= 2,
+	/* multi read command with completion notification - not used */
+	HINIC_API_CMD_MULTI_READ		= 3,
+	/* write command without completion notification */
+	HINIC_API_CMD_POLL_WRITE		= 4,
+	/* read command without completion notification */
+	HINIC_API_CMD_POLL_READ			= 5,
+	/* read from mgmt cpu command with completion */
+	HINIC_API_CMD_WRITE_ASYNC_TO_MGMT_CPU	= 6,
+	HINIC_API_CMD_MAX,
+};
+
+struct hinic_api_cmd_status {
+	u64 header;
+	u32 buf_desc;
+	u32 cell_addr_hi;
+	u32 cell_addr_lo;
+	u32 rsvd0;
+	u64 rsvd1;
+};
+
+/* HW struct */
+struct hinic_api_cmd_cell {
+	u64 ctrl;
+
+	/* address is 64 bit in HW struct */
+	u64 next_cell_paddr;
+
+	u64 desc;
+
+	/* HW struct */
+	union {
+		struct {
+			u64 hw_cmd_paddr;
+		} write;
+
+		struct {
+			u64 hw_wb_resp_paddr;
+			u64 hw_cmd_paddr;
+		} read;
+	};
+};
+
+struct hinic_api_cmd_resp_fmt {
+	u64				header;
+	u64				rsvd[3];
+	u64				resp_data;
+};
+
+struct hinic_api_cmd_cell_ctxt {
+	struct hinic_api_cmd_cell	*cell_vaddr;
+
+	void				*api_cmd_vaddr;
+
+	struct hinic_api_cmd_resp_fmt	*resp;
+
+	struct completion		done;
+	int				status;
+
+	u32				saved_prod_idx;
+};
+
+struct hinic_api_cmd_chain_attr {
+	struct hinic_hwdev		*hwdev;
+	enum hinic_api_cmd_chain_type	chain_type;
+
+	u32				num_cells;
+	u16				rsp_size;
+	u16				cell_size;
+};
+
+struct hinic_api_cmd_chain {
+	struct hinic_hwdev		*hwdev;
+	enum hinic_api_cmd_chain_type	chain_type;
+
+	u32				num_cells;
+	u16				cell_size;
+	u16				rsp_size;
+
+	/* HW members is 24 bit format */
+	u32				prod_idx;
+	u32				cons_idx;
+
+	struct semaphore		sem;
+	/* Async cmd can not be scheduling */
+	spinlock_t			async_lock;
+
+	dma_addr_t			wb_status_paddr;
+	struct hinic_api_cmd_status	*wb_status;
+
+	dma_addr_t			head_cell_paddr;
+	struct hinic_api_cmd_cell	*head_node;
+
+	struct hinic_api_cmd_cell_ctxt	*cell_ctxt;
+	struct hinic_api_cmd_cell	*curr_node;
+
+	struct hinic_dma_addr_align	cells_addr;
+
+	u8				*cell_vaddr_base;
+	u64				cell_paddr_base;
+	u8				*rsp_vaddr_base;
+	u64				rsp_paddr_base;
+	u8				*buf_vaddr_base;
+	u64				buf_paddr_base;
+	u64				cell_size_align;
+	u64				rsp_size_align;
+	u64				buf_size_align;
+};
+
+int hinic_api_cmd_write(struct hinic_api_cmd_chain *chain,
+			enum hinic_node_id dest, void *cmd, u16 size);
+
+int hinic_api_cmd_read(struct hinic_api_cmd_chain *chain,
+		       enum hinic_node_id dest, void *cmd, u16 size,
+		       void *ack, u16 ack_size);
+
+int hinic_api_cmd_init(struct hinic_hwdev *hwdev,
+		       struct hinic_api_cmd_chain **chain);
+
+void hinic_api_cmd_free(struct hinic_api_cmd_chain **chain);
+
+#endif

drivers/net/ethernet/huawei/hinic/hinic_cfg.h

+/* SPDX-License-Identifier: GPL-2.0*/
+/* Huawei HiNIC PCI Express Linux driver
+ * Copyright(c) 2017 Huawei Technologies Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ *
+ */
+
+#ifndef __CFG_MGT_H__
+#define __CFG_MGT_H__
+
+#include "hinic_ctx_def.h"
+
+#define CFG_MAX_CMD_TIMEOUT     1000 /* ms */
+
+enum {
+	CFG_FREE = 0,
+	CFG_BUSY = 1
+};
+
+/* start position for CEQs allocation, Max number of CEQs is 32 */
+/*lint -save -e849*/
+enum {
+	CFG_RDMA_CEQ_BASE       = 0
+};
+
+/*lint -restore*/
+enum {
+	CFG_NET_MODE_ETH = 0, /* Eth */
+	CFG_NET_MODE_FIC = 1, /* FIC */
+	CFG_NET_MODE_FC = 2   /* FC */
+};
+
+enum {
+	SF_SVC_FT_BIT = (1 << 0),
+	SF_SVC_RDMA_BIT = (1 << 1),
+};
+
+/* RDMA resource */
+#define K_UNIT              BIT(10)
+#define M_UNIT              BIT(20)
+#define G_UNIT              BIT(30)
+
+/* number of PFs and VFs */
+#define HOST_PF_NUM         4
+#define HOST_VF_NUM         0
+#define HOST_OQID_MASK_VAL  2
+
+//#define MAX_NUM_AEQ         1
+
+/* L2NIC */
+#define L2NIC_SQ_DEPTH      (4 * K_UNIT)
+#define L2NIC_RQ_DEPTH      (4 * K_UNIT)
+
+#define HINIC_CFG_MAX_QP	64
+
+/* RDMA */
+#define RDMA_RSVD_QPS       2
+#define ROCE_MAX_WQES       (16 * K_UNIT - 1)
+#define IWARP_MAX_WQES      (8 * K_UNIT)
+
+#define RDMA_MAX_SQ_SGE     8
+
+#define ROCE_MAX_RQ_SGE     8
+#define IWARP_MAX_RQ_SGE    2
+
+#define RDMA_MAX_SQ_DESC_SZ (1 * K_UNIT)
+
+/* (256B(cache_line_len) - 16B(ctrl_seg_len) - 64B(max_task_seg_len)) */
+#define ROCE_MAX_SQ_INLINE_DATA_SZ   192
+
+#define IWARP_MAX_SQ_INLINE_DATA_SZ  108
+
+#define ROCE_MAX_RQ_DESC_SZ     128
+#define IWARP_MAX_RQ_DESC_SZ    64
+
+#define IWARP_MAX_IRQ_DEPTH     1024
+#define IWARP_IRQ_ENTRY_SZ      64
+
+#define IWARP_MAX_ORQ_DEPTH     1024
+#define IWARP_ORQ_ENTRY_SZ      32
+
+#define IWARP_MAX_RTOQ_DEPTH    1024
+#define IWARP_RTOQ_ENTRY_SZ     32
+
+#define IWARP_MAX_ACKQ_DEPTH    1024
+#define IWARP_ACKQ_ENTRY_SZ     16
+
+#define ROCE_QPC_ENTRY_SZ       512
+#define IWARP_QPC_ENTRY_SZ      1024
+
+#define WQEBB_SZ                64
+
+#define ROCE_RDMARC_ENTRY_SZ    32
+#define ROCE_MAX_QP_INIT_RDMA   128
+#define ROCE_MAX_QP_DEST_RDMA   128
+
+#define ROCE_MAX_SRQ_WQES       (16 * K_UNIT - 1)
+#define ROCE_RSVD_SRQS          0
+#define ROCE_MAX_SRQ_SGE        7
+#define ROCE_SRQC_ENTERY_SZ     64
+
+#define RDMA_MAX_CQES       (64 * K_UNIT - 1)
+#define RDMA_RSVD_CQS       0
+
+#define RDMA_CQC_ENTRY_SZ   128
+
+#define RDMA_CQE_SZ         32
+#define RDMA_RSVD_MRWS      128
+#define RDMA_MPT_ENTRY_SZ   64
+#define RDMA_NUM_MTTS       (1 * G_UNIT)
+#define LOG_MTT_SEG         5
+#define MTT_ENTRY_SZ        8
+#define LOG_RDMARC_SEG      3
+
+#define LOCAL_ACK_DELAY     15
+#define RDMA_NUM_PORTS      1
+#define ROCE_MAX_MSG_SZ     (2 * G_UNIT) /*  */
+#define IWARP_MAX_MSG_SZ    (1 * G_UNIT)
+
+#define DB_PAGE_SZ          (4 * K_UNIT)
+#define DWQE_SZ             256
+
+#define NUM_PD              (128 * K_UNIT)
+#define RSVD_PD             0
+
+#define MAX_XRCDS           (64 * K_UNIT)
+#define RSVD_XRCDS          0
+
+#define MAX_GID_PER_PORT    16
+#define GID_ENTRY_SZ        32
+#define RSVD_LKEY           ((RDMA_RSVD_MRWS - 1) << 8)
+#define NUM_COMP_VECTORS    32
+#define PAGE_SZ_CAP         ((1UL << 12) | (1UL << 13) | (1UL << 14) | \
+			     (1UL << 16) | (1UL << 18) | (1UL << 20) | \
+			     (1UL << 22))
+#define ROCE_MODE           1
+
+#define MAX_FRPL_LEN        511
+#define MAX_PKEYS           1
+
+/* FCoE */
+#define FCOE_PCTX_SZ        256
+#define FCOE_CCTX_SZ        256
+#define FCOE_SQE_SZ         128
+#define FCOE_SCQC_SZ        64
+#define FCOE_SCQE_SZ        64
+#define FCOE_SRQC_SZ        64
+#define FCOE_SRQE_SZ        32
+
+/* ToE */
+#define TOE_PCTX_SZ         1024
+#define TOE_CQC_SZ          64
+
+/* IoE */
+#define IOE_PCTX_SZ         512
+
+/* FC */
+#define FC_PCTX_SZ          256
+#define FC_CCTX_SZ          256
+#define FC_SQE_SZ           128
+#define FC_SCQC_SZ          64
+#define FC_SCQE_SZ          64
+#define FC_SRQC_SZ          64
+#define FC_SRQE_SZ          32
+
+/* OVS */
+#define OVS_PCTX_SZ         256
+#define OVS_SCQC_SZ         64
+
+/* ACL */
+#define ACL_PCTX_SZ		512
+#define ACL_SCQC_SZ		64
+
+struct dev_sf_svc_attr {
+	bool ft_en;     /* business enable flag (not include RDMA) */
+	bool ft_pf_en;  /* In FPGA Test VF resource is in PF or not,
+			 * 0 - VF, 1 - PF, VF doesn't need this bit.
+			 */
+	bool rdma_en;
+	bool rdma_pf_en;/* In FPGA Test VF RDMA resource is in PF or not,
+			 * 0 - VF, 1 - PF, VF doesn't need this bit.
+			 */
+	u8 sf_en_vf;    /* SF_EN for PPF/PF's VF */
+};
+
+struct host_shared_resource_cap {
+	u32 host_pctxs; /* Parent Context max 1M, IOE and FCoE max 8K flows */
+	u32 host_cctxs; /* Child Context: max 8K */
+	u32 host_scqs;  /* shared CQ, chip interface module uses 1 SCQ
+			 * TOE/IOE/FCoE each uses 1 SCQ
+			 * RoCE/IWARP uses multiple SCQs
+			 * So 6 SCQ least
+			 */
+	u32 host_srqs; /* SRQ number: 256K */
+	u32 host_mpts; /* MR number:1M */
+};
+
+/* device capability */
+struct service_cap {
+	struct dev_sf_svc_attr sf_svc_attr;
+	enum cfg_svc_type_en svc_type;      /* user input service type */
+	enum cfg_svc_type_en chip_svc_type; /* HW supported service type */
+
+	/* Host global resources */
+	u16 host_total_function;
+	u8 host_oq_id_mask_val;
+	u8 host_id;
+	u8 ep_id;
+	/* DO NOT get interrupt_type from firmware */
+	enum intr_type interrupt_type;
+	u8 intr_chip_en;
+	u8 max_cos_id;  /* PF/VF's max cos id */
+	u8 cos_valid_bitmap;
+	u8 er_id;       /* PF/VF's ER */
+	u8 port_id;     /* PF/VF's physical port */
+	u8 max_vf;      /* max VF number that PF supported */
+	bool sf_en;     /* stateful business status */
+	u8 timer_en;    /* 0:disable, 1:enable */
+	u8 bloomfilter_en; /* 0:disable, 1:enable*/
+	u16 max_sqs;
+	u16 max_rqs;
+
+	/* For test */
+	u32 test_qpc_num;
+	u32 test_qpc_resvd_num;
+	u32 test_page_size_reorder;
+	bool test_xid_alloc_mode;
+	bool test_gpa_check_enable;
+	u8 test_qpc_alloc_mode;
+	u8 test_scqc_alloc_mode;
+
+	u32 test_max_conn_num;
+	u32 test_max_cache_conn_num;
+	u32 test_scqc_num;
+	u32 test_mpt_num;
+	u32 test_scq_resvd_num;
+	u32 test_mpt_recvd_num;
+	u32 test_hash_num;
+	u32 test_reorder_num;
+
+	u32 max_connect_num; /* PF/VF maximum connection number(1M) */
+	/* The maximum connections which can be stick to cache memory, max 1K */
+	u16 max_stick2cache_num;
+	/* Starting address in cache memory for bloom filter, 64Bytes aligned */
+	u16 bfilter_start_addr;
+	/* Length for bloom filter, aligned on 64Bytes. The size is length*64B.
+	 * Bloom filter memory size + 1 must be power of 2.
+	 * The maximum memory size of bloom filter is 4M
+	 */
+	u16 bfilter_len;
+	/* The size of hash bucket tables, align on 64 entries.
+	 * Be used to AND (&) the hash value. Bucket Size +1 must be power of 2.
+	 * The maximum number of hash bucket is 4M
+	 */
+	u16 hash_bucket_num;
+	u8 net_port_mode; /* 0:ETH,1:FIC,2:4FC */
+
+	u32 pf_num;
+	u32 pf_id_start;
+	u32 vf_num;	/* max numbers of vf in current host */
+	u32 vf_id_start;
+
+	struct host_shared_resource_cap shared_res_cap; /* shared capability */
+	struct dev_version_info     dev_ver_info;       /* version */
+	struct nic_service_cap      nic_cap;            /* NIC capability */
+	struct rdma_service_cap     rdma_cap;           /* RDMA capability */
+	struct fcoe_service_cap     fcoe_cap;           /* FCoE capability */
+	struct toe_service_cap      toe_cap;            /* ToE capability */
+	struct fc_service_cap       fc_cap;             /* FC capability */
+	struct ovs_service_cap      ovs_cap;            /* OVS capability */
+	struct acl_service_cap      acl_cap;            /* ACL capability */
+};
+
+struct cfg_eq {
+	enum hinic_service_type type;
+	int eqn;
+	int free; /* 1 - alocated, 0- freed */
+};
+
+struct cfg_eq_info {
+	struct cfg_eq *eq;
+
+	u8 num_ceq;
+	//u8 num_aeq;
+	//u8 num_eq; /* num_eq = num_ceq + num_aeq */
+
+	u8 num_ceq_remain;
+
+	/* mutex used for allocate EQs */
+	struct mutex eq_mutex;
+};
+
+struct irq_alloc_info_st {
+	enum hinic_service_type type;
+	int free;                /* 1 - alocated, 0- freed */
+	struct irq_info info;
+};
+
+struct cfg_irq_info {
+	struct irq_alloc_info_st *alloc_info;
+	u16 num_total;
+	u16 num_irq_remain;
+	u16 num_irq_hw;          /* device max irq number */
+
+	/* mutex used for allocate EQs */
+	struct mutex irq_mutex;
+};
+
+#define VECTOR_THRESHOLD	2
+
+struct cfg_mgmt_info {
+	struct hinic_hwdev *hwdev;
+	struct service_cap  svc_cap;
+	struct cfg_eq_info  eq_info;        /* EQ */
+	struct cfg_irq_info irq_param_info; /* IRQ */
+	u32 func_seq_num;                   /* temporary */
+};
+
+enum cfg_sub_cmd {
+	/* PPF(PF) <-> FW */
+	HINIC_CFG_NIC_CAP = 0,
+	CFG_FW_VERSION,
+	CFG_UCODE_VERSION,
+	HINIC_CFG_FUNC_CAP,
+	HINIC_CFG_MBOX_CAP = 6,
+};
+
+struct hinic_dev_cap {
+	u8	status;
+	u8	version;
+	u8	rsvd0[6];
+
+	/* Public resource */
+	u8 sf_svc_attr;
+	u8 host_id;
+	u8 sf_en_pf;
+	u8 sf_en_vf;
+
+	u8 ep_id;
+	u8 intr_type;
+	u8 max_cos_id;
+	u8 er_id;
+	u8 port_id;
+	u8 max_vf;
+	u16 svc_cap_en;
+	u16 host_total_func;
+	u8 host_oq_id_mask_val;
+	u8 max_vf_cos_id;
+
+	u32 max_conn_num;
+	u16 max_stick2cache_num;
+	u16 max_bfilter_start_addr;
+	u16 bfilter_len;
+	u16 hash_bucket_num;
+	u8 cfg_file_ver;
+	u8 net_port_mode;
+	u8 valid_cos_bitmap;	/* every bit indicate cos is valid */
+	u8 rsvd1;
+	u32 pf_num;
+	u32 pf_id_start;
+	u32 vf_num;
+	u32 vf_id_start;
+
+	/* shared resource */
+	u32 host_pctx_num;
+	u8 host_sf_en;
+	u8 rsvd2[3];
+	u32 host_ccxt_num;
+	u32 host_scq_num;
+	u32 host_srq_num;
+	u32 host_mpt_num;
+
+	/* l2nic */
+	u16 nic_max_sq;
+	u16 nic_max_rq;
+	u16 nic_vf_max_sq;
+	u16 nic_vf_max_rq;
+	u8 nic_lro_en;
+	u8 nic_lro_sz;
+	u8 nic_tso_sz;
+	u8 rsvd3;
+
+	/* RoCE */
+	u32 roce_max_qp;
+	u32 roce_max_cq;
+	u32 roce_max_srq;
+	u32 roce_max_mpt;
+
+	u32 roce_vf_max_qp;
+	u32 roce_vf_max_cq;
+	u32 roce_vf_max_srq;
+	u32 roce_vf_max_mpt;
+
+	u32 roce_cmtt_cl_start;
+	u32 roce_cmtt_cl_end;
+	u32 roce_cmtt_cl_size;
+
+	u32 roce_dmtt_cl_start;
+	u32 roce_dmtt_cl_end;
+	u32 roce_dmtt_cl_size;
+
+	u32 roce_wqe_cl_start;
+	u32 roce_wqe_cl_end;
+	u32 roce_wqe_cl_size;
+
+	/* IWARP */
+	u32 iwarp_max_qp;
+	u32 iwarp_max_cq;
+	u32 iwarp_max_mpt;
+
+	u32 iwarp_vf_max_qp;
+	u32 iwarp_vf_max_cq;
+	u32 iwarp_vf_max_mpt;
+
+	u32 iwarp_cmtt_cl_start;
+	u32 iwarp_cmtt_cl_end;
+	u32 iwarp_cmtt_cl_size;
+
+	u32 iwarp_dmtt_cl_start;
+	u32 iwarp_dmtt_cl_end;
+	u32 iwarp_dmtt_cl_size;
+
+	u32 iwarp_wqe_cl_start;
+	u32 iwarp_wqe_cl_end;
+	u32 iwarp_wqe_cl_size;
+
+	/* FCoE */
+	u32 fcoe_max_qp;
+	u32 fcoe_max_cq;
+	u32 fcoe_max_srq;
+
+	u32 fcoe_max_cctx;
+	u32 fcoe_cctx_id_start;
+
+	u8 fcoe_vp_id_start;
+	u8 fcoe_vp_id_end;
+	u8 rsvd4[2];
+
+	/* OVS */
+	u32 ovs_max_qpc;
+	u32 rsvd6;
+
+	/* ToE */
+	u32 toe_max_pctx;
+	u32 toe_max_cq;
+	u32 toe_max_srq;
+	u32 toe_srq_id_start;
+
+	/* FC */
+	u32 fc_max_pctx;
+	u32 fc_max_scq;
+	u32 fc_max_srq;
+
+	u32 fc_max_cctx;
+	u32 fc_cctx_id_start;
+
+	u8 fc_vp_id_start;
+	u8 fc_vp_id_end;
+	u16 func_id;
+};
+
+#define VSW_UP_CFG_TIMEOUT      (0xFF00000)
+
+#define VSW_SET_STATEFUL_BITS_TOE(flag)       \
+	((flag) << VSW_STATEFUL_TOE_EN)
+#define VSW_SET_STATEFUL_BITS_FCOE(flag)      \
+	((flag) << VSW_STATEFUL_FCOE_EN)
+#define VSW_SET_STATEFUL_BITS_IWARP(flag)     \
+	((flag) << VSW_STATEFUL_IWARP_EN)
+#define VSW_SET_STATEFUL_BITS_ROCE(flag)      \
+	((flag) << VSW_STATEFUL_ROCE_EN)
+
+#define VSW_GET_STATEFUL_BITS_TOE(flag)       \
+	((bool)(((flag) >> VSW_STATEFUL_TOE_EN) & 0x1U))
+#define VSW_GET_STATEFUL_BITS_FCOE(flag)      \
+	((bool)(((flag) >> VSW_STATEFUL_FCOE_EN) & 0x1U))
+#define VSW_GET_STATEFUL_BITS_IWARP(flag)     \
+	((bool)(((flag) >> VSW_STATEFUL_IWARP_EN) & 0x1U))
+#define VSW_GET_STATEFUL_BITS_ROCE(flag)      \
+	((bool)(((flag) >> VSW_STATEFUL_ROCE_EN) & 0x1U))
+
+enum tag_vsw_major_cmd {
+	VSW_MAJOR_MISC = 10,    /* 0~9 reserved for driver */
+	VSW_MAJOR_L2SWITCH,
+	VSW_MAJOR_L2MULTICAST,
+	VSW_MAJOR_QOS,
+	VSW_MAJOR_PKTSUPS,
+	VSW_MAJOR_VLANFILTER,
+	VSW_MAJOR_MACFILTER,
+	VSW_MAJOR_IPFILTER,
+	VSW_MAJOR_VLANMAPPING,
+	VSW_MAJOR_ETHTRUNK,
+	VSW_MAJOR_MIRROR,
+	VSW_MAJOR_DFX,
+	VSW_MAJOR_ACL,
+};
+
+enum tag_vsw_minor_misc_cmd {
+	VSW_MINOR_MISC_INIT_FUNC = 0,
+	VSW_MINOR_MISC_SET_FUNC_SF_ENBITS,
+	VSW_MINOR_MISC_GET_FUNC_SF_ENBITS,
+	VSW_MINOR_MISC_CMD_MAX,
+};
+
+/* vswitch eth-trunk sub-command */
+enum tag_nic_stateful_enbits {
+	VSW_STATEFUL_TOE_EN   = 0,
+	VSW_STATEFUL_FCOE_EN  = 1,
+	VSW_STATEFUL_IWARP_EN = 2,
+	VSW_STATEFUL_ROCE_EN  = 3,
+};
+
+/* function stateful enable parameters */
+struct nic_misc_func_sf_enbits {
+	u8  status;
+	u8  version;
+	u8  rsvd0[6];
+	u32 function_id;
+	u32 stateful_enbits; /* b0:toe, b1:fcoe, b2:iwarp, b3:roce */
+	u32 stateful_enmask; /* b0:toe, b1:fcoe, b2:iwarp, b3:roce */
+};
+
+#endif

drivers/net/ethernet/huawei/hinic/hinic_cmdq.h

+/* SPDX-License-Identifier: GPL-2.0*/
+/* Huawei HiNIC PCI Express Linux driver
+ * Copyright(c) 2017 Huawei Technologies Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ *
+ */
+
+#ifndef HINIC_CMDQ_H_
+#define HINIC_CMDQ_H_
+
+#define HINIC_DB_OFF			0x00000800
+
+#define HINIC_SCMD_DATA_LEN		16
+
+#define	HINIC_CMDQ_DEPTH		4096
+
+#define	HINIC_CMDQ_BUF_SIZE		2048U
+#define HINIC_CMDQ_BUF_HW_RSVD		8
+#define HINIC_CMDQ_MAX_DATA_SIZE	\
+		(HINIC_CMDQ_BUF_SIZE - HINIC_CMDQ_BUF_HW_RSVD)
+
+enum hinic_cmdq_type {
+	HINIC_CMDQ_SYNC,
+	HINIC_CMDQ_ASYNC,
+	HINIC_MAX_CMDQ_TYPES,
+};
+
+enum hinic_db_src_type {
+	HINIC_DB_SRC_CMDQ_TYPE,
+	HINIC_DB_SRC_L2NIC_SQ_TYPE,
+};
+
+enum hinic_cmdq_db_type {
+	HINIC_DB_SQ_RQ_TYPE,
+	HINIC_DB_CMDQ_TYPE,
+};
+
+/* CMDQ WQE CTRLS */
+struct hinic_cmdq_header {
+	u32	header_info;
+	u32	saved_data;
+};
+
+struct hinic_scmd_bufdesc {
+	u32	buf_len;
+	u32	rsvd;
+	u8	data[HINIC_SCMD_DATA_LEN];
+};
+
+struct hinic_lcmd_bufdesc {
+	struct hinic_sge	sge;
+	u32			rsvd1;
+	u64			saved_async_buf;
+	u64			rsvd3;
+};
+
+struct hinic_cmdq_db {
+	u32	db_info;
+	u32	rsvd;
+};
+
+struct hinic_status {
+	u32 status_info;
+};
+
+struct hinic_ctrl {
+	u32 ctrl_info;
+};
+
+struct hinic_sge_resp {
+	struct hinic_sge sge;
+	u32		rsvd;
+};
+
+struct hinic_cmdq_completion {
+	/* HW Format */
+	union {
+		struct hinic_sge_resp	sge_resp;
+		u64			direct_resp;
+	};
+};
+
+struct hinic_cmdq_wqe_scmd {
+	struct hinic_cmdq_header	header;
+	struct hinic_cmdq_db		db;
+	struct hinic_status		status;
+	struct hinic_ctrl		ctrl;
+	struct hinic_cmdq_completion	completion;
+	struct hinic_scmd_bufdesc	buf_desc;
+};
+
+struct hinic_cmdq_wqe_lcmd {
+	struct hinic_cmdq_header	header;
+	struct hinic_status		status;
+	struct hinic_ctrl		ctrl;
+	struct hinic_cmdq_completion	completion;
+	struct hinic_lcmd_bufdesc	buf_desc;
+};
+
+struct hinic_cmdq_inline_wqe {
+	struct hinic_cmdq_wqe_scmd	wqe_scmd;
+};
+
+struct hinic_cmdq_wqe {
+	/* HW Format */
+	union {
+		struct hinic_cmdq_inline_wqe	inline_wqe;
+		struct hinic_cmdq_wqe_lcmd	wqe_lcmd;
+	};
+};
+
+struct hinic_cmdq_arm_bit {
+	u32	q_type;
+	u32	q_id;
+};
+
+struct hinic_cmdq_ctxt_info {
+	u64	curr_wqe_page_pfn;
+	u64	wq_block_pfn;
+};
+
+struct hinic_cmdq_ctxt {
+	u8	status;
+	u8	version;
+	u8	rsvd0[6];
+
+	u16	func_idx;
+	u8	cmdq_id;
+	u8	ppf_idx;
+
+	u8	rsvd1[4];
+
+	struct hinic_cmdq_ctxt_info ctxt_info;
+};
+
+enum hinic_cmdq_status {
+	HINIC_CMDQ_ENABLE = BIT(0),
+};
+
+enum hinic_cmdq_cmd_type {
+	HINIC_CMD_TYPE_NONE,
+	HINIC_CMD_TYPE_SET_ARM,
+	HINIC_CMD_TYPE_DIRECT_RESP,
+	HINIC_CMD_TYPE_SGE_RESP,
+	HINIC_CMD_TYPE_ASYNC,
+	HINIC_CMD_TYPE_TIMEOUT,
+	HINIC_CMD_TYPE_FAKE_TIMEOUT,
+};
+
+struct hinic_cmdq_cmd_info {
+	enum hinic_cmdq_cmd_type	cmd_type;
+
+	struct completion		*done;
+	int				*errcode;
+	int				*cmpt_code;
+	u64				*direct_resp;
+	u64				cmdq_msg_id;
+};
+
+struct hinic_cmdq {
+	struct hinic_wq			*wq;
+
+	enum hinic_cmdq_type		cmdq_type;
+	int				wrapped;
+
+	/* spinlock for send cmdq commands */
+	spinlock_t			cmdq_lock;
+
+	/* doorbell area */
+	u8 __iomem			*db_base;
+
+	struct hinic_cmdq_ctxt		cmdq_ctxt;
+
+	struct hinic_cmdq_cmd_info	*cmd_infos;
+
+	struct hinic_hwdev		*hwdev;
+};
+
+struct hinic_cmdqs {
+	struct hinic_hwdev		*hwdev;
+
+	struct pci_pool			*cmd_buf_pool;
+
+	struct hinic_wq			*saved_wqs;
+
+	struct hinic_cmdq_pages		cmdq_pages;
+	struct hinic_cmdq		cmdq[HINIC_MAX_CMDQ_TYPES];
+
+	u32				status;
+	u32				disable_flag;
+};
+
+void hinic_cmdq_ceq_handler(void *hwdev, u32 ceqe_data);
+
+int hinic_reinit_cmdq_ctxts(struct hinic_hwdev *hwdev);
+
+bool hinic_cmdq_idle(struct hinic_cmdq *cmdq);
+
+int hinic_cmdqs_init(struct hinic_hwdev *hwdev);
+
+void hinic_cmdqs_free(struct hinic_hwdev *hwdev);
+
+bool hinic_cmdq_check_vf_ctxt(struct hinic_hwdev *hwdev,
+			      struct hinic_cmdq_ctxt *cmdq_ctxt);
+
+#endif

drivers/net/ethernet/huawei/hinic/hinic_csr.h

+/* SPDX-License-Identifier: GPL-2.0*/
+/* Huawei HiNIC PCI Express Linux driver
+ * Copyright(c) 2017 Huawei Technologies Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ *
+ */
+
+#ifndef HINIC_CSR_H
+#define HINIC_CSR_H
+
+#define HINIC_CSR_GLOBAL_BASE_ADDR			0x4000
+
+/* HW interface registers */
+#define HINIC_CSR_FUNC_ATTR0_ADDR			0x0
+#define HINIC_CSR_FUNC_ATTR1_ADDR			0x4
+#define HINIC_CSR_FUNC_ATTR2_ADDR			0x8
+#define HINIC_CSR_FUNC_ATTR4_ADDR			0x10
+#define HINIC_CSR_FUNC_ATTR5_ADDR			0x14
+
+#define HINIC_FUNC_CSR_MAILBOX_DATA_OFF			0x80
+#define HINIC_FUNC_CSR_MAILBOX_CONTROL_OFF		0x0100
+#define HINIC_FUNC_CSR_MAILBOX_INT_OFFSET_OFF		0x0104
+#define HINIC_FUNC_CSR_MAILBOX_RESULT_H_OFF		0x0108
+#define HINIC_FUNC_CSR_MAILBOX_RESULT_L_OFF		0x010C
+
+#define HINIC_CSR_DMA_ATTR_TBL_BASE			0xC80
+
+#define HINIC_ELECTION_BASE				0x200
+
+#define HINIC_CSR_DMA_ATTR_TBL_STRIDE			0x4
+#define HINIC_CSR_DMA_ATTR_TBL_ADDR(idx)		\
+			(HINIC_CSR_DMA_ATTR_TBL_BASE	\
+			+ (idx) * HINIC_CSR_DMA_ATTR_TBL_STRIDE)
+
+#define HINIC_PPF_ELECTION_STRIDE			0x4
+#define HINIC_CSR_MAX_PORTS				4
+#define HINIC_CSR_PPF_ELECTION_ADDR		\
+			(HINIC_CSR_GLOBAL_BASE_ADDR + HINIC_ELECTION_BASE)
+
+#define HINIC_CSR_GLOBAL_MPF_ELECTION_ADDR		\
+			(HINIC_CSR_GLOBAL_BASE_ADDR + HINIC_ELECTION_BASE + \
+			HINIC_CSR_MAX_PORTS * HINIC_PPF_ELECTION_STRIDE)
+
+/* MSI-X registers */
+#define HINIC_CSR_MSIX_CTRL_BASE			0x2000
+#define HINIC_CSR_MSIX_CNT_BASE				0x2004
+
+#define HINIC_CSR_MSIX_STRIDE				0x8
+
+#define HINIC_CSR_MSIX_CTRL_ADDR(idx)			\
+	(HINIC_CSR_MSIX_CTRL_BASE + (idx) * HINIC_CSR_MSIX_STRIDE)
+
+#define HINIC_CSR_MSIX_CNT_ADDR(idx)			\
+	(HINIC_CSR_MSIX_CNT_BASE + (idx) * HINIC_CSR_MSIX_STRIDE)
+
+/* EQ registers */
+#define HINIC_AEQ_MTT_OFF_BASE_ADDR			0x200
+#define HINIC_CEQ_MTT_OFF_BASE_ADDR			0x400
+
+#define HINIC_EQ_MTT_OFF_STRIDE				0x40
+
+#define HINIC_CSR_AEQ_MTT_OFF(id)			\
+	(HINIC_AEQ_MTT_OFF_BASE_ADDR + (id) * HINIC_EQ_MTT_OFF_STRIDE)
+
+#define HINIC_CSR_CEQ_MTT_OFF(id)			\
+	(HINIC_CEQ_MTT_OFF_BASE_ADDR + (id) * HINIC_EQ_MTT_OFF_STRIDE)
+
+#define HINIC_CSR_EQ_PAGE_OFF_STRIDE			8
+
+#define HINIC_AEQ_HI_PHYS_ADDR_REG(q_id, pg_num)	\
+		(HINIC_CSR_AEQ_MTT_OFF(q_id) + \
+		(pg_num) * HINIC_CSR_EQ_PAGE_OFF_STRIDE)
+
+#define HINIC_AEQ_LO_PHYS_ADDR_REG(q_id, pg_num)	\
+		(HINIC_CSR_AEQ_MTT_OFF(q_id) + \
+		(pg_num) * HINIC_CSR_EQ_PAGE_OFF_STRIDE + 4)
+
+#define HINIC_CEQ_HI_PHYS_ADDR_REG(q_id, pg_num)	\
+		(HINIC_CSR_CEQ_MTT_OFF(q_id) + \
+		(pg_num) * HINIC_CSR_EQ_PAGE_OFF_STRIDE)
+
+#define HINIC_CEQ_LO_PHYS_ADDR_REG(q_id, pg_num)	\
+		(HINIC_CSR_CEQ_MTT_OFF(q_id) + \
+		(pg_num) * HINIC_CSR_EQ_PAGE_OFF_STRIDE + 4)
+
+#define HINIC_EQ_HI_PHYS_ADDR_REG(type, q_id, pg_num)	\
+		((u32)((type == HINIC_AEQ) ? \
+		HINIC_AEQ_HI_PHYS_ADDR_REG(q_id, pg_num) : \
+		HINIC_CEQ_HI_PHYS_ADDR_REG(q_id, pg_num)))
+
+#define HINIC_EQ_LO_PHYS_ADDR_REG(type, q_id, pg_num)	\
+		((u32)((type == HINIC_AEQ) ? \
+		HINIC_AEQ_LO_PHYS_ADDR_REG(q_id, pg_num) : \
+		HINIC_CEQ_LO_PHYS_ADDR_REG(q_id, pg_num)))
+
+#define HINIC_AEQ_CTRL_0_ADDR_BASE			0xE00
+#define HINIC_AEQ_CTRL_1_ADDR_BASE			0xE04
+#define HINIC_AEQ_CONS_IDX_0_ADDR_BASE			0xE08
+#define HINIC_AEQ_CONS_IDX_1_ADDR_BASE			0xE0C
+
+#define HINIC_EQ_OFF_STRIDE				0x80
+
+#define HINIC_CSR_AEQ_CTRL_0_ADDR(idx) \
+	(HINIC_AEQ_CTRL_0_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
+
+#define HINIC_CSR_AEQ_CTRL_1_ADDR(idx) \
+	(HINIC_AEQ_CTRL_1_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
+
+#define HINIC_CSR_AEQ_CONS_IDX_ADDR(idx) \
+	(HINIC_AEQ_CONS_IDX_0_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
+
+#define HINIC_CSR_AEQ_PROD_IDX_ADDR(idx) \
+	(HINIC_AEQ_CONS_IDX_1_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
+
+#define HINIC_CEQ_CTRL_0_ADDR_BASE			0x1000
+#define HINIC_CEQ_CTRL_1_ADDR_BASE			0x1004
+#define HINIC_CEQ_CONS_IDX_0_ADDR_BASE			0x1008
+#define HINIC_CEQ_CONS_IDX_1_ADDR_BASE			0x100C
+
+#define HINIC_CSR_CEQ_CTRL_0_ADDR(idx) \
+	(HINIC_CEQ_CTRL_0_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
+
+#define HINIC_CSR_CEQ_CTRL_1_ADDR(idx) \
+	(HINIC_CEQ_CTRL_1_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
+
+#define HINIC_CSR_CEQ_CONS_IDX_ADDR(idx) \
+	(HINIC_CEQ_CONS_IDX_0_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
+
+#define HINIC_CSR_CEQ_PROD_IDX_ADDR(idx) \
+	(HINIC_CEQ_CONS_IDX_1_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
+
+/* API CMD registers */
+#define HINIC_CSR_API_CMD_BASE				0xF000
+
+#define HINIC_CSR_API_CMD_STRIDE			0x100
+
+#define HINIC_CSR_API_CMD_CHAIN_HEAD_HI_ADDR(idx)	\
+	(HINIC_CSR_API_CMD_BASE + 0x0 + (idx) * HINIC_CSR_API_CMD_STRIDE)
+
+#define HINIC_CSR_API_CMD_CHAIN_HEAD_LO_ADDR(idx)	\
+	(HINIC_CSR_API_CMD_BASE + 0x4 + (idx) * HINIC_CSR_API_CMD_STRIDE)
+
+#define HINIC_CSR_API_CMD_STATUS_HI_ADDR(idx)		\
+	(HINIC_CSR_API_CMD_BASE + 0x8 + (idx) * HINIC_CSR_API_CMD_STRIDE)
+
+#define HINIC_CSR_API_CMD_STATUS_LO_ADDR(idx)		\
+	(HINIC_CSR_API_CMD_BASE + 0xC + (idx) * HINIC_CSR_API_CMD_STRIDE)
+
+#define HINIC_CSR_API_CMD_CHAIN_NUM_CELLS_ADDR(idx)	\
+	(HINIC_CSR_API_CMD_BASE + 0x10 + (idx) * HINIC_CSR_API_CMD_STRIDE)
+
+#define HINIC_CSR_API_CMD_CHAIN_CTRL_ADDR(idx)		\
+	(HINIC_CSR_API_CMD_BASE + 0x14 + (idx) * HINIC_CSR_API_CMD_STRIDE)
+
+#define HINIC_CSR_API_CMD_CHAIN_PI_ADDR(idx)		\
+	(HINIC_CSR_API_CMD_BASE + 0x1C + (idx) * HINIC_CSR_API_CMD_STRIDE)
+
+#define HINIC_CSR_API_CMD_CHAIN_REQ_ADDR(idx)		\
+	(HINIC_CSR_API_CMD_BASE + 0x20 + (idx) * HINIC_CSR_API_CMD_STRIDE)
+
+#define HINIC_CSR_API_CMD_STATUS_0_ADDR(idx)		\
+	(HINIC_CSR_API_CMD_BASE + 0x30 + (idx) * HINIC_CSR_API_CMD_STRIDE)
+
+/* VF control registers in pf */
+#define HINIC_PF_CSR_VF_FLUSH_BASE		0x1F400
+#define HINIC_PF_CSR_VF_FLUSH_STRIDE		0x4
+
+#define HINIC_GLB_DMA_SO_RO_REPLACE_ADDR	0x488C
+
+#define HINIC_ICPL_RESERVD_ADDR			0x9204
+
+#define HINIC_PF_CSR_VF_FLUSH_OFF(idx)			\
+	(HINIC_PF_CSR_VF_FLUSH_BASE + (idx) * HINIC_PF_CSR_VF_FLUSH_STRIDE)
+
+#define HINIC_IPSU_CHANNEL_NUM		7
+#define HINIC_IPSU_CHANNEL0_ADDR	0x404
+#define HINIC_IPSU_CHANNEL_OFFSET	0x14
+#define HINIC_IPSU_DIP_OFFSET		13
+#define HINIC_IPSU_SIP_OFFSET		14
+#define HINIC_IPSU_DIP_SIP_MASK		\
+	((0x1 << HINIC_IPSU_SIP_OFFSET) | (0x1 << HINIC_IPSU_DIP_OFFSET))
+
+/* For multi-host mgmt
+ * 0x75C0: bit0~3: uP write, host mode is bmwg or normal host
+ *	   bit4~7: master host ppf write when function initializing
+ *	   bit8~23: only for slave host PXE
+ * 0x75C4: slave host status
+ *	   bit0~7: host 0~7 functions status
+ */
+#define HINIC_HOST_MODE_ADDR			0x75C0
+#define HINIC_MULT_HOST_SLAVE_STATUS_ADDR	0x75C4
+
+#endif

drivers/net/ethernet/huawei/hinic/hinic_dbg.h

+/* SPDX-License-Identifier: GPL-2.0*/
+/* Huawei HiNIC PCI Express Linux driver
+ * Copyright(c) 2017 Huawei Technologies Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ *
+ */
+
+#ifndef HINIC_NIC_DBG_H_
+#define HINIC_NIC_DBG_H_
+
+u16 hinic_dbg_get_qp_num(void *hwdev);
+
+void *hinic_dbg_get_qp_handle(void *hwdev, u16 q_id);
+
+void *hinic_dbg_get_sq_wq_handle(void *hwdev, u16 q_id);
+
+void *hinic_dbg_get_rq_wq_handle(void *hwdev, u16 q_id);
+
+u16 hinic_dbg_get_sq_pi(void *hwdev, u16 q_id);
+
+u16 hinic_dbg_get_rq_hw_pi(void *hwdev, u16 q_id);
+
+u16 hinic_dbg_get_rq_sw_pi(void *hwdev, u16 q_id);
+
+void *hinic_dbg_get_sq_ci_addr(void *hwdev, u16 q_id);
+
+u64 hinic_dbg_get_sq_cla_addr(void *hwdev, u16 q_id);
+
+u64 hinic_dbg_get_rq_cla_addr(void *hwdev, u16 q_id);
+
+int hinic_dbg_get_sq_db_addr(void *hwdev, u16 q_id, u64 **map_addr,
+			     u64 *phy_addr, u32 *pg_idx);
+
+u16 hinic_dbg_get_global_qpn(void *hwdev);
+
+int hinic_dbg_get_sq_wqe_info(void *hwdev, u16 q_id, u16 idx, u16 wqebb_cnt,
+			      u8 *wqe, u16 *wqe_size);
+
+int hinic_dbg_get_rq_wqe_info(void *hwdev, u16 q_id, u16 idx, u16 wqebb_cnt,
+			      u8 *wqe, u16 *wqe_size);
+
+int hinic_dbg_lt_rd_16byte(void *hwdev, u8 dest, u8 instance,
+			   u32 lt_index, u8 *data);
+
+int hinic_dbg_lt_wr_16byte_mask(void *hwdev, u8 dest, u8 instance,
+				u32 lt_index, u8 *data, u16 mask);
+
+int hinic_sm_ctr_rd32(void *hwdev, u8 node, u8 instance,
+		      u32 ctr_id, u32 *value);
+
+int hinic_sm_ctr_rd32_clear(void *hwdev, u8 node, u8 instance,
+			    u32 ctr_id, u32 *value);
+
+int hinic_sm_ctr_wr32(void *hwdev, u8 node, u8 instance, u32 ctr_id, u32 value);
+
+int hinic_sm_ctr_rd64(void *hwdev, u8 node, u8 instance,
+		      u32 ctr_id, u64 *value);
+
+int hinic_sm_ctr_wr64(void *hwdev, u8 node, u8 instance,
+		      u32 ctr_id, u64 value);
+
+int hinic_sm_ctr_rd64_pair(void *hwdev, u8 node, u8 instance, u32 ctr_id,
+			   u64 *value1, u64 *value2);
+
+int hinic_sm_ctr_wr64_pair(void *hwdev, u8 node, u8 instance, u32 ctr_id,
+			   u64 value1, u64 value2);
+
+int hinic_api_csr_rd32(void *hwdev, u8 dest, u32 addr, u32 *val);
+
+int hinic_api_csr_wr32(void *hwdev, u8 dest, u32 addr, u32 val);
+
+int hinic_api_csr_rd64(void *hwdev, u8 dest, u32 addr, u64 *val);
+
+int hinic_dbg_get_hw_stats(void *hwdev, u8 *hw_stats, u16 *out_size);
+
+u16 hinic_dbg_clear_hw_stats(void *hwdev);
+
+void hinic_get_chip_fault_stats(void *hwdev, u8 *chip_fault_stats, int offset);
+
+int hinic_dbg_get_pf_bw_limit(void *hwdev, u32 *pf_bw_limit);
+
+#endif

drivers/net/ethernet/huawei/hinic/hinic_hwif.h

+/* SPDX-License-Identifier: GPL-2.0*/
+/* Huawei HiNIC PCI Express Linux driver
+ * Copyright(c) 2017 Huawei Technologies Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ *
+ */
+
+#ifndef HINIC_HWIF_H
+#define HINIC_HWIF_H
+
+#include "hinic_hwdev.h"
+
+#define HINIC_WAIT_DOORBELL_AND_OUTBOUND_TIMEOUT	2000
+
+struct hinic_free_db_area {
+	u32		db_idx[HINIC_DB_MAX_AREAS];
+
+	u32		num_free;
+
+	u32		alloc_pos;
+	u32		return_pos;
+
+	/* spinlock for allocating doorbell area */
+	spinlock_t	idx_lock;
+};
+
+struct hinic_func_attr {
+	u16			func_global_idx;
+	u8			port_to_port_idx;
+	u8			pci_intf_idx;
+	u8			vf_in_pf;
+	enum func_type		func_type;
+
+	u8			mpf_idx;
+
+	u8			ppf_idx;
+
+	u16			num_irqs;		/* max: 2 ^ 15 */
+	u8			num_aeqs;		/* max: 2 ^ 3 */
+	u8			num_ceqs;		/* max: 2 ^ 7 */
+
+	u8			num_dma_attr;		/* max: 2 ^ 6 */
+
+	u16			global_vf_id_of_pf;
+};
+
+struct hinic_hwif {
+	u8 __iomem			*cfg_regs_base;
+	u8 __iomem			*intr_regs_base;
+	u64				db_base_phy;
+	u8 __iomem			*db_base;
+
+	void __iomem			*dwqe_mapping;
+	struct hinic_free_db_area	free_db_area;
+
+	struct hinic_func_attr		attr;
+
+	void				*pdev;
+};
+
+struct hinic_dma_addr_align {
+	u32		real_size;
+
+	void		*ori_vaddr;
+	dma_addr_t	ori_paddr;
+
+	void		*align_vaddr;
+	dma_addr_t	align_paddr;
+};
+
+u32 hinic_hwif_read_reg(struct hinic_hwif *hwif, u32 reg);
+
+void hinic_hwif_write_reg(struct hinic_hwif *hwif, u32 reg, u32 val);
+
+void hinic_set_pf_status(struct hinic_hwif *hwif, enum hinic_pf_status status);
+
+enum hinic_pf_status hinic_get_pf_status(struct hinic_hwif *hwif);
+
+enum hinic_doorbell_ctrl
+	hinic_get_doorbell_ctrl_status(struct hinic_hwif *hwif);
+
+enum hinic_outbound_ctrl
+	hinic_get_outbound_ctrl_status(struct hinic_hwif *hwif);
+
+void hinic_enable_doorbell(struct hinic_hwif *hwif);
+
+void hinic_disable_doorbell(struct hinic_hwif *hwif);
+
+void hinic_enable_outbound(struct hinic_hwif *hwif);
+
+void hinic_disable_outbound(struct hinic_hwif *hwif);
+
+int hinic_init_hwif(struct hinic_hwdev *hwdev, void *cfg_reg_base,
+		    void *intr_reg_base, u64 db_base_phy,
+		    void *db_base, void *dwqe_mapping);
+
+void hinic_free_hwif(struct hinic_hwdev *hwdev);
+
+int wait_until_doorbell_flush_states(struct hinic_hwif *hwif,
+				     enum hinic_doorbell_ctrl states);
+
+int hinic_dma_zalloc_coherent_align(void *dev_hdl, u64 size, u64 align,
+				    unsigned int flag,
+				    struct hinic_dma_addr_align *mem_align);
+
+void hinic_dma_free_coherent_align(void *dev_hdl,
+				   struct hinic_dma_addr_align *mem_align);
+
+#endif