From 711933a7cb3424efb9ffe4c292c3005f354d387c Mon Sep 17 00:00:00 2001 From: Huazhong Tan Date: Tue, 30 Jul 2019 10:58:32 +0800 Subject: [PATCH] net: hns3: check reset interrupt status when reset fails driver inclusion category: bugfix bugzilla: NA CVE: NA Currently, the reset interrupt will be cleared firstly, so when reset fails, if interrupt status register has reset interrupt, it means there is a new coming reset. Fixes: 764a6254ce5c ("net: hns3: clear reset interrupt status in hclge_irq_handle()") Feature or Bugfix:Bugfix Signed-off-by: Huazhong Tan Reviewed-by: lipeng Reviewed-by: Yunsheng Lin Reviewed-by: Yang Yingliang Signed-off-by: Yang Yingliang --- drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 7 +++---- drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h | 1 + 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c index c1c7e7fec6d1..b164067a6023 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c @@ -3429,11 +3429,10 @@ static bool hclge_reset_err_handle(struct hclge_dev *hdev) dev_info(&hdev->pdev->dev, "Reset pending %lu\n", hdev->reset_pending); return true; - } else if ((hdev->reset_type != HNAE3_IMP_RESET) && - (hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG) & - BIT(HCLGE_IMP_RESET_BIT))) { + } else if (hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS) & + HCLGE_RESET_INT_M) { dev_info(&hdev->pdev->dev, - "reset failed because IMP Reset is pending\n"); + "reset failed because new reset interrupt\n"); hclge_clear_reset_cause(hdev); return false; } else if (hdev->reset_fail_cnt < HCLGE_RESET_MAX_FAIL_CNT) { diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h index af442c55693b..335dc26322ab 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h @@ -169,6 +169,7 @@ enum HLCGE_PORT_TYPE { #define HCLGE_GLOBAL_RESET_BIT 0 #define HCLGE_CORE_RESET_BIT 1 #define HCLGE_IMP_RESET_BIT 2 +#define HCLGE_RESET_INT_M GENMASK(2, 0) #define HCLGE_FUN_RST_ING 0x20C00 #define HCLGE_FUN_RST_ING_B 0 -- GitLab