提交 6cd6cede 编写于 作者: P Peter Ujfalusi 提交者: Mark Brown

ASoC: tlv320dac33: BCLK divider fix

The BCLK divider was not configured in case of mode7.
This leads to unpredictable behavior when switching between FIFO modes.
Configure the BCLK divider depending on the fifo_mode (FIFO is in use,
or FIFO bypass).
Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: NLiam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
上级 84740ac1
...@@ -845,11 +845,14 @@ static int dac33_prepare_chip(struct snd_pcm_substream *substream) ...@@ -845,11 +845,14 @@ static int dac33_prepare_chip(struct snd_pcm_substream *substream)
dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a); dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b); dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
switch (dac33->fifo_mode) { /* BCLK divide ratio */
case DAC33_FIFO_MODE1: if (dac33->fifo_mode)
/* 20: BCLK divide ratio */
dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 3); dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 3);
else
dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32);
switch (dac33->fifo_mode) {
case DAC33_FIFO_MODE1:
dac33_write16(codec, DAC33_ATHR_MSB, dac33_write16(codec, DAC33_ATHR_MSB,
DAC33_THRREG(dac33->alarm_threshold)); DAC33_THRREG(dac33->alarm_threshold));
break; break;
...@@ -864,8 +867,6 @@ static int dac33_prepare_chip(struct snd_pcm_substream *substream) ...@@ -864,8 +867,6 @@ static int dac33_prepare_chip(struct snd_pcm_substream *substream)
DAC33_THRREG(10)); DAC33_THRREG(10));
break; break;
default: default:
/* BYPASS mode */
dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32);
break; break;
} }
......
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