diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 88d67ce3f88dfd62f5aa97ee40f28aa09e3785b9..6497a96d96c4f9d0e384135ca40b193ba7884d35 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -2420,6 +2420,7 @@ static void its_cpu_init_lpis_others(void __iomem *rbase, int cpu)
 static void its_cpu_init_collection_others(void __iomem *rbase,
 					   phys_addr_t phys_base, int cpu)
 {
+	u32 count;
 	struct its_node *its;
 
 	raw_spin_lock(&its_lock);
@@ -2445,6 +2446,32 @@ static void its_cpu_init_collection_others(void __iomem *rbase,
 			target = GICR_TYPER_CPU_NUMBER(target) << 16;
 		}
 
+		dsb(sy);
+
+		/* In FPGA, We need to check if the gicr has been cut,
+		 * and if it is, it can't be initialized
+		 */
+		count = 2000;
+		while (1) {
+			if (readl_relaxed(rbase + GICR_SYNCR) == 0)
+				break;
+
+			count--;
+			if (!count) {
+				pr_err("this gicr does not exist, or it's abnormal:%pK\n",
+					&phys_base);
+				break;
+			}
+			cpu_relax();
+			udelay(1);
+		}
+
+		if (count == 0)
+			break;
+
+		pr_info("its init other collection table, ITS:%pK, GICR:%pK, coreId:%u\n",
+			&its->phys_base, &phys_base, cpu);
+
 		/* Perform collection mapping */
 		its->collections[cpu].target_address = target;
 		its->collections[cpu].col_id = cpu;