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raspberrypi-kernel
提交 4b4ffac3 编写于 作者: F fengsheng 提交者： Xie XiuQi
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drivers : sysctl LPC renamed TDH 

driver inclusion
category: feature
bugzilla: NA
CVE: NA

sysctl: 1. LPC renamed TDH
        2. Add SATA RAS printing
Signed-off-by: Nfengsheng <fengsheng5@huawei.com>
Reviewed-by: Nzhangmu <zhangmu1@huawei.com>
Reviewed-by: NYang Yingliang <yangyingliang@huawei.com>
Signed-off-by: NYang Yingliang <yangyingliang@huawei.com>
上级 1cea86cc
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Showing with 110 addition and 137 deletion
drivers/soc/hisilicon/sysctl/sysctl_drv.c
浏览文件 @ 4b4ffac3
...@@ -50,8 +50,10 @@ ...@@ -50,8 +50,10 @@
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#define DEBUG #define DEBUG
#define SYSCTL_DRIVER_VERSION "1.7.8.0" #define SYSCTL_DRIVER_VERSION "1.8.8.0"
/* debug?a1? */
#define CHIP_VER_BASE (0x20107E238)
unsigned int g_sysctrl_debug; unsigned int g_sysctrl_debug;
/* sysctrl reg base address */ /* sysctrl reg base address */
...@@ -86,60 +88,72 @@ int hisi_sysctl_print_debug(u32 print_debug_en) ...@@ -86,60 +88,72 @@ int hisi_sysctl_print_debug(u32 print_debug_en)
return 0; return 0;
} }
int his_hllc_init(void) u64 get_chip_base(void)
{ {
u32 hllc_num;
u32 chip_id;
u32 ddrc_num;
u64 addr;
u32 chip_ver; u32 chip_ver;
u64 chip_module_base;
void __iomem *chip_ver_addr; void __iomem *chip_ver_addr;
u64 chip_module_base;
pr_info("[INFO] %s start.\n", __func__); chip_ver_addr = ioremap(CHIP_VER_BASE, (u64)4);
chip_ver_addr = ioremap(0x20107E238, (u64)4);
if (!chip_ver_addr) { if (!chip_ver_addr) {
pr_err("[ERROR] %s chip_ver_base is error.\n", __func__); pr_err("sysctl [ERROR] %s chip_ver_base is error.\n", __func__);
return ERR_FAILED; return ERR_FAILED;
} }
chip_ver = readl(chip_ver_addr); chip_ver = readl(chip_ver_addr);
chip_ver = chip_ver>>28; chip_ver = chip_ver>>28;
if (chip_ver == CHIP_VERSION_ES) { if (chip_ver == CHIP_VERSION_ES) {
pr_info("[sysctl hllc] chip is es\n"); pr_info("sysctl [INFO] chip is es\n");
chip_module_base = HLLC_CHIP_MODULE_ES; chip_module_base = HLLC_CHIP_MODULE_ES;
} else { } else {
chip_module_base = HLLC_CHIP_MODULE_CS; chip_module_base = HLLC_CHIP_MODULE_CS;
pr_info("[sysctl hllc] chip is cs\n"); pr_info("sysctl [INFO] chip is cs\n");
} }
pr_info("[sysctl hllc] chip ver=%x\n", chip_ver); iounmap((void *)chip_ver_addr);
pr_info("sysctl [INFO] chip ver=%x\n", chip_ver);
return chip_module_base;
}
int his_hllc_init(void)
{
u32 hllc_num;
u32 chip_id;
u32 ddrc_num;
u64 addr;
u64 chip_module_base;
pr_info("[INFO] %s start.\n", __func__);
chip_module_base = get_chip_base();
for (chip_id = 0; chip_id < CHIP_ID_NUM_MAX; chip_id++) { for (chip_id = 0; chip_id < CHIP_ID_NUM_MAX; chip_id++) {
for (hllc_num = 0; hllc_num < HLLC_NUM_MAX; hllc_num++) { for (hllc_num = 0; hllc_num < HLLC_NUM_MAX; hllc_num++) {
addr = (u64)chip_id * chip_module_base + HLLC0_REG_BASE + (u64)hllc_num * 0x10000; addr = (u64)chip_id * chip_module_base + HLLC0_REG_BASE + (u64)hllc_num * 0x10000;
hip_hllc_priv.hllc_base[chip_id][hllc_num] = ioremap(addr, (u64)0x10000); hip_hllc_priv.hllc_base[chip_id][hllc_num] = ioremap(addr, (u64)0x10000);
debug_sysctrl_print("[DBG] hllc_base: %p.\n", debug_sysctrl_print("[DBG] hllc_base: %pK.\n",
hip_hllc_priv.hllc_base[chip_id][hllc_num]); hip_hllc_priv.hllc_base[chip_id][hllc_num]);
addr = (u64)chip_id * chip_module_base + PCS0_REG_BASE + (u64)hllc_num * 0x10000; addr = (u64)chip_id * chip_module_base + PCS0_REG_BASE + (u64)hllc_num * 0x10000;
hip_hllc_priv.pcs_base[chip_id][hllc_num] = ioremap(addr, (u64)0x10000); hip_hllc_priv.pcs_base[chip_id][hllc_num] = ioremap(addr, (u64)0x10000);
debug_sysctrl_print("[DBG] pcs_base: %p.\n", debug_sysctrl_print("[DBG] pcs_base: %pK.\n",
hip_hllc_priv.pcs_base[chip_id][hllc_num]); hip_hllc_priv.pcs_base[chip_id][hllc_num]);
} }
addr = (u64)chip_id * chip_module_base + PA_REG_BASE; addr = (u64)chip_id * chip_module_base + PA_REG_BASE;
hip_hllc_priv.pa_base[chip_id] = ioremap(addr, (u64)0x10000); hip_hllc_priv.pa_base[chip_id] = ioremap(addr, (u64)0x10000);
debug_sysctrl_print("[DBG] pa_base: %p.\n", debug_sysctrl_print("[DBG] pa_base: %pK.\n",
hip_hllc_priv.pa_base[chip_id]); hip_hllc_priv.pa_base[chip_id]);
addr = (u64)chip_id * chip_module_base + PM_REG_BASE; addr = (u64)chip_id * chip_module_base + PM_REG_BASE;
hip_hllc_priv.pm_base[chip_id] = ioremap(addr, (u64)0x10000); hip_hllc_priv.pm_base[chip_id] = ioremap(addr, (u64)0x10000);
debug_sysctrl_print("[DBG] pm_base: %p.\n", debug_sysctrl_print("[DBG] pm_base: %pK.\n",
hip_hllc_priv.pm_base[chip_id]); hip_hllc_priv.pm_base[chip_id]);
for (ddrc_num = 0; ddrc_num < DDRC_CH_NUM_MAX; ddrc_num++) { for (ddrc_num = 0; ddrc_num < DDRC_CH_NUM_MAX; ddrc_num++) {
...@@ -148,16 +162,14 @@ int his_hllc_init(void) ...@@ -148,16 +162,14 @@ int his_hllc_init(void)
addr = (u64)chip_id * chip_module_base + DDRC0_TA_REG_BASE + (u64)ddrc_num * 0x10000; addr = (u64)chip_id * chip_module_base + DDRC0_TA_REG_BASE + (u64)ddrc_num * 0x10000;
hip_hllc_priv.ddrc_ta_base[chip_id][ddrc_num] = ioremap(addr, (u64)0x10000); hip_hllc_priv.ddrc_ta_base[chip_id][ddrc_num] = ioremap(addr, (u64)0x10000);
debug_sysctrl_print("[DBG] ddrc_tb_base: %p.\n", debug_sysctrl_print("[DBG] ddrc_tb_base: %pK.\n",
hip_hllc_priv.ddrc_tb_base[chip_id][ddrc_num]); hip_hllc_priv.ddrc_tb_base[chip_id][ddrc_num]);
debug_sysctrl_print("[DBG] ddrc_ta_base: %p.\n", debug_sysctrl_print("[DBG] ddrc_ta_base: %pK.\n",
hip_hllc_priv.ddrc_ta_base[chip_id][ddrc_num]); hip_hllc_priv.ddrc_ta_base[chip_id][ddrc_num]);
} }
} }
iounmap((void *)chip_ver_addr);
return ERR_OK; return ERR_OK;
} }
...@@ -217,7 +229,7 @@ int hisi_sysctl_get_intlv_mode_cfg(u8 chip_id, u8 *intlv_mode_cfg) ...@@ -217,7 +229,7 @@ int hisi_sysctl_get_intlv_mode_cfg(u8 chip_id, u8 *intlv_mode_cfg)
addr = hip_hllc_priv.pa_base[chip_id] + PA_PA_GLOBAL_CFG_REG; addr = hip_hllc_priv.pa_base[chip_id] + PA_PA_GLOBAL_CFG_REG;
pa_global_cfg.u32 = readl(addr); pa_global_cfg.u32 = readl(addr);
debug_sysctrl_print("addr:%p, val:0x%x.\n", debug_sysctrl_print("addr:%pK, val:0x%x.\n",
addr, pa_global_cfg.u32); addr, pa_global_cfg.u32);
*intlv_mode_cfg = (u8)pa_global_cfg.bits.intlv_mode_cfg; *intlv_mode_cfg = (u8)pa_global_cfg.bits.intlv_mode_cfg;
...@@ -247,7 +259,7 @@ int hisi_sysctl_get_hllc_enable_cfg(u8 chip_id, u8 intlv_mode_cfg, u8 *hllc_eanb ...@@ -247,7 +259,7 @@ int hisi_sysctl_get_hllc_enable_cfg(u8 chip_id, u8 intlv_mode_cfg, u8 *hllc_eanb
addr = hip_hllc_priv.pa_base[chip_id] + PA_PA_GLOBAL_CFG_REG; addr = hip_hllc_priv.pa_base[chip_id] + PA_PA_GLOBAL_CFG_REG;
pa_global_cfg.u32 = readl(addr); pa_global_cfg.u32 = readl(addr);
debug_sysctrl_print("addr:%p, val:0x%x.\n", debug_sysctrl_print("addr:%pK, val:0x%x.\n",
addr, pa_global_cfg.u32); addr, pa_global_cfg.u32);
*hllc_eanble_cfg = (u8)pa_global_cfg.bits.hydra_port_en_cfg; *hllc_eanble_cfg = (u8)pa_global_cfg.bits.hydra_port_en_cfg;
...@@ -403,7 +415,7 @@ int hisi_sysctl_get_hllc_crc_ecc(u8 chip_id, hllc_crc_ecc_info *hllc_crc_ecc) ...@@ -403,7 +415,7 @@ int hisi_sysctl_get_hllc_crc_ecc(u8 chip_id, hllc_crc_ecc_info *hllc_crc_ecc)
addr = hip_hllc_priv.hllc_base[chip_id][hllc_num] + HLLC_HLLC_REGS_HLLC_PHY_RX_FLIT_CRC_ERR_CNT_REG; addr = hip_hllc_priv.hllc_base[chip_id][hllc_num] + HLLC_HLLC_REGS_HLLC_PHY_RX_FLIT_CRC_ERR_CNT_REG;
phy_rx_flit_crc_err_cnt = readl(addr); phy_rx_flit_crc_err_cnt = readl(addr);
debug_sysctrl_print("addr:%p, crc_err_cnt:0x%x.\n", debug_sysctrl_print("addr:%pK, crc_err_cnt:0x%x.\n",
addr, phy_rx_flit_crc_err_cnt); addr, phy_rx_flit_crc_err_cnt);
hllc_crc_ecc->hllc_crc_ecc[hllc_num] = phy_rx_flit_crc_err_cnt; hllc_crc_ecc->hllc_crc_ecc[hllc_num] = phy_rx_flit_crc_err_cnt;
...@@ -461,7 +473,7 @@ int hisi_sysctl_get_hllc_link_status(u8 chip_id, hllc_link_sta_info *hllc_link_s ...@@ -461,7 +473,7 @@ int hisi_sysctl_get_hllc_link_status(u8 chip_id, hllc_link_sta_info *hllc_link_s
addr = hip_hllc_priv.pcs_base[chip_id][hllc_num] + HLLC_HLLC_PCS_PCS_TX_TRAINING_STS_0_REG + lane_num * 4; addr = hip_hllc_priv.pcs_base[chip_id][hllc_num] + HLLC_HLLC_PCS_PCS_TX_TRAINING_STS_0_REG + lane_num * 4;
pcs_tx_training_sts.u32 = readl(addr); pcs_tx_training_sts.u32 = readl(addr);
debug_sysctrl_print("addr:%p, val:0x%x.\n", debug_sysctrl_print("addr:%pK, val:0x%x.\n",
addr, pcs_tx_training_sts.u32); addr, pcs_tx_training_sts.u32);
hllc_link_status &= pcs_tx_training_sts.bits.tx_training_succeed; hllc_link_status &= pcs_tx_training_sts.bits.tx_training_succeed;
...@@ -504,7 +516,7 @@ int hisi_sysctl_set_hllc_mem_ecc(u8 chip_id, u8 hllc_id, u8 hllc_ch_bitmap, u8 e ...@@ -504,7 +516,7 @@ int hisi_sysctl_set_hllc_mem_ecc(u8 chip_id, u8 hllc_id, u8 hllc_ch_bitmap, u8 e
hllc_inject_ecc_type.bits.inject_ecc_err_type = ecc_err_type & 0x3; hllc_inject_ecc_type.bits.inject_ecc_err_type = ecc_err_type & 0x3;
writel(hllc_inject_ecc_type.u32, addr); writel(hllc_inject_ecc_type.u32, addr);
debug_sysctrl_print("addr:%p, val:0x%x.\n", debug_sysctrl_print("addr:%pK, val:0x%x.\n",
addr, hllc_inject_ecc_type.u32); addr, hllc_inject_ecc_type.u32);
addr = hip_hllc_priv.hllc_base[chip_id][hllc_id] + HLLC_HLLC_REGS_HLLC_INJECT_ECC_EN_REG; addr = hip_hllc_priv.hllc_base[chip_id][hllc_id] + HLLC_HLLC_REGS_HLLC_INJECT_ECC_EN_REG;
...@@ -512,7 +524,7 @@ int hisi_sysctl_set_hllc_mem_ecc(u8 chip_id, u8 hllc_id, u8 hllc_ch_bitmap, u8 e ...@@ -512,7 +524,7 @@ int hisi_sysctl_set_hllc_mem_ecc(u8 chip_id, u8 hllc_id, u8 hllc_ch_bitmap, u8 e
hllc_inject_ecc_en.bits.hydra_tx_inject_ecc_err_en = hllc_ch_bitmap & 0x7; hllc_inject_ecc_en.bits.hydra_tx_inject_ecc_err_en = hllc_ch_bitmap & 0x7;
writel(hllc_inject_ecc_en.u32, addr); writel(hllc_inject_ecc_en.u32, addr);
debug_sysctrl_print("addr:%p, val:0x%x.\n", debug_sysctrl_print("addr:%pK, val:0x%x.\n",
addr, hllc_inject_ecc_en.u32); addr, hllc_inject_ecc_en.u32);
debug_sysctrl_print("%s: set_hllc_mem_ecc success\n", __func__); debug_sysctrl_print("%s: set_hllc_mem_ecc success\n", __func__);
...@@ -546,13 +558,13 @@ int hisi_sysctl_get_hllc_mem_ecc(u8 chip_id, u8 hllc_id, hllc_mem_ecc_info *hllc ...@@ -546,13 +558,13 @@ int hisi_sysctl_get_hllc_mem_ecc(u8 chip_id, u8 hllc_id, hllc_mem_ecc_info *hllc
addr = hip_hllc_priv.hllc_base[chip_id][hllc_id] + HLLC_HLLC_RAS_HLLC_ERR_MISC1H_REG; addr = hip_hllc_priv.hllc_base[chip_id][hllc_id] + HLLC_HLLC_RAS_HLLC_ERR_MISC1H_REG;
hllc_ras_err_misc1h.u32 = readl(addr); hllc_ras_err_misc1h.u32 = readl(addr);
hllc_mem_ecc->u32 = hllc_ras_err_misc1h.u32 & 0x7f; hllc_mem_ecc->u32 = hllc_ras_err_misc1h.u32 & 0x7f;
debug_sysctrl_print("addr:%p, val:0x%x.\n", debug_sysctrl_print("addr:%pK, val:0x%x.\n",
addr, hllc_ras_err_misc1h.u32); addr, hllc_ras_err_misc1h.u32);
addr = hip_hllc_priv.hllc_base[chip_id][hllc_id] + HLLC_HLLC_RAS_HLLC_ERR_MISC1L_REG; addr = hip_hllc_priv.hllc_base[chip_id][hllc_id] + HLLC_HLLC_RAS_HLLC_ERR_MISC1L_REG;
hllc_ras_err_misc1l.u32 = readl(addr); hllc_ras_err_misc1l.u32 = readl(addr);
hllc_mem_ecc->u32 |= (hllc_ras_err_misc1l.u32 & 0x7f) << 0x7; hllc_mem_ecc->u32 |= (hllc_ras_err_misc1l.u32 & 0x7f) << 0x7;
debug_sysctrl_print("addr:%p, val:0x%x.\n", debug_sysctrl_print("addr:%pK, val:0x%x.\n",
addr, hllc_ras_err_misc1l.u32); addr, hllc_ras_err_misc1l.u32);
debug_sysctrl_print("hllc_mem_ecc:0x%x.\n", debug_sysctrl_print("hllc_mem_ecc:0x%x.\n",
...@@ -602,7 +614,7 @@ int hisi_sysctl_clr_ddrc_mem_ecc(u8 chip_id, u8 totem, u8 ddrc_ch_id, u32 rasc_c ...@@ -602,7 +614,7 @@ int hisi_sysctl_clr_ddrc_mem_ecc(u8 chip_id, u8 totem, u8 ddrc_ch_id, u32 rasc_c
ddrc_rasc_cfg_clr.u32 = rasc_cfg_clr; ddrc_rasc_cfg_clr.u32 = rasc_cfg_clr;
writel(ddrc_rasc_cfg_clr.u32, addr_ecc_clr); writel(ddrc_rasc_cfg_clr.u32, addr_ecc_clr);
debug_sysctrl_print("addr:%p, val:0x%x.\n", debug_sysctrl_print("addr:%pK, val:0x%x.\n",
addr_ecc_clr, ddrc_rasc_cfg_clr.u32); addr_ecc_clr, ddrc_rasc_cfg_clr.u32);
return ret; return ret;
...@@ -652,7 +664,7 @@ int hisi_sysctl_get_ddrc_mem_ecc(u8 chip_id, u8 totem, u8 ddrc_ch_id, u8 rank_id ...@@ -652,7 +664,7 @@ int hisi_sysctl_get_ddrc_mem_ecc(u8 chip_id, u8 totem, u8 ddrc_ch_id, u8 rank_id
addr_ecc_cfg_ecc = hip_hllc_priv.ddrc_tb_base[chip_id][ddrc_ch_id] + DMC_DMC_DDRC_CFG_ECC_REG; addr_ecc_cfg_ecc = hip_hllc_priv.ddrc_tb_base[chip_id][ddrc_ch_id] + DMC_DMC_DDRC_CFG_ECC_REG;
} }
debug_sysctrl_print("addr_ecc_cfg_info_rnk:%p.\n", debug_sysctrl_print("addr_ecc_cfg_info_rnk:%pK.\n",
addr_ecc_cfg_info_rnk); addr_ecc_cfg_info_rnk);
memset(&ddrc_rasc_cfg_info_rnk, 0, sizeof(ddrc_rasc_u_cfg_info_rnk)); memset(&ddrc_rasc_cfg_info_rnk, 0, sizeof(ddrc_rasc_u_cfg_info_rnk));
...@@ -661,9 +673,9 @@ int hisi_sysctl_get_ddrc_mem_ecc(u8 chip_id, u8 totem, u8 ddrc_ch_id, u8 rank_id ...@@ -661,9 +673,9 @@ int hisi_sysctl_get_ddrc_mem_ecc(u8 chip_id, u8 totem, u8 ddrc_ch_id, u8 rank_id
ddrc_rasc_his_ha_rankcnt_inf.u32 = readl(addr_ecc_cnt); ddrc_rasc_his_ha_rankcnt_inf.u32 = readl(addr_ecc_cnt);
ddrc_mem_ecc->ddrc_mem_secc = ddrc_rasc_his_ha_rankcnt_inf.u32; ddrc_mem_ecc->ddrc_mem_secc = ddrc_rasc_his_ha_rankcnt_inf.u32;
debug_sysctrl_print("addr:%p, ddrc_serr_cnt.funnel_corr_cnt:0x%x.\n", debug_sysctrl_print("addr:%pK, ddrc_serr_cnt.funnel_corr_cnt:0x%x.\n",
addr_ecc_cnt, ddrc_rasc_his_ha_rankcnt_inf.bits.ha_rnk_funnel_corr_cnt); addr_ecc_cnt, ddrc_rasc_his_ha_rankcnt_inf.bits.ha_rnk_funnel_corr_cnt);
debug_sysctrl_print("addr:%p, ddrc_serr_cnt.corr_cnt:0x%x.\n", debug_sysctrl_print("addr:%pK, ddrc_serr_cnt.corr_cnt:0x%x.\n",
addr_ecc_cnt, ddrc_rasc_his_ha_rankcnt_inf.bits.ha_rnk_corr_cnt); addr_ecc_cnt, ddrc_rasc_his_ha_rankcnt_inf.bits.ha_rnk_corr_cnt);
dmc_ddrc_cfg_ecc.u32 = readl(addr_ecc_cfg_ecc); dmc_ddrc_cfg_ecc.u32 = readl(addr_ecc_cfg_ecc);
...@@ -673,7 +685,7 @@ int hisi_sysctl_get_ddrc_mem_ecc(u8 chip_id, u8 totem, u8 ddrc_ch_id, u8 rank_id ...@@ -673,7 +685,7 @@ int hisi_sysctl_get_ddrc_mem_ecc(u8 chip_id, u8 totem, u8 ddrc_ch_id, u8 rank_id
ddrc_mem_ecc->ddrc_mem_secc_en = 0x0; ddrc_mem_ecc->ddrc_mem_secc_en = 0x0;
} }
debug_sysctrl_print("addr:%p, dmc_ddrc_cfg_ecc:0x%x.\n", debug_sysctrl_print("addr:%pK, dmc_ddrc_cfg_ecc:0x%x.\n",
addr_ecc_cfg_ecc, dmc_ddrc_cfg_ecc.u32); addr_ecc_cfg_ecc, dmc_ddrc_cfg_ecc.u32);
debug_sysctrl_print("%s: get_ddrc_mem_ecc success\n", debug_sysctrl_print("%s: get_ddrc_mem_ecc success\n",
......
drivers/soc/hisilicon/sysctl/sysctl_drv.h
浏览文件 @ 4b4ffac3
...@@ -230,4 +230,6 @@ enum { ...@@ -230,4 +230,6 @@ enum {
CPU_VOUT_MODE_MAX, CPU_VOUT_MODE_MAX,
}; };
u64 get_chip_base(void);
#endif /* _HIS_SYSCTL_H_ */ #endif /* _HIS_SYSCTL_H_ */
drivers/soc/hisilicon/sysctl/sysctl_local_ras.c
浏览文件 @ 4b4ffac3
...@@ -49,106 +49,87 @@ static DEFINE_MUTEX(hisi_ghes_mutex); ...@@ -49,106 +49,87 @@ static DEFINE_MUTEX(hisi_ghes_mutex);
0xFD, 0x1D, 0xC5, 0xF7, 0xC5) 0xFD, 0x1D, 0xC5, 0xF7, 0xC5)
#define SUBCTRL_REG_BASE (0x000201070000) #define SUBCTRL_REG_BASE (0x000201070000)
#define SUBCTRL_LPC_RESET_OFFSET (0xa58) #define SUBCTRL_TDH_RESET_OFFSET (0xa58)
#define SUBCTRL_LPC_UNRESET_OFFSET (0xa5c) #define SUBCTRL_TDH_UNRESET_OFFSET (0xa5c)
#define LPC_REG_BASE (0x000201190000) #define TDH_REG_BASE (0x000201190000)
#define LPC_MEM_ACCESS_OFFSET (0x140) #define TDH_MEM_ACCESS_OFFSET (0x140)
#define LPC_IRQ_CNT_MAX (0x1000) #define TDH_IRQ_CNT_MAX (0x1000)
static u32 sysctl_lpc_irq_cnt; static u32 sysctl_tdh_irq_cnt;
static void __iomem *sysctl_subctrl_lpc_priv[CHIP_ID_NUM_MAX]; static void __iomem *sysctl_subctrl_tdh_priv[CHIP_ID_NUM_MAX];
static void __iomem *sysctl_lpc_priv[CHIP_ID_NUM_MAX]; static void __iomem *sysctl_tdh_priv[CHIP_ID_NUM_MAX];
static int sysctl_lpc_init(void) static int sysctl_tdh_init(void)
{ {
u32 chip_id; u32 chip_id;
u64 addr; u64 addr;
u64 lpc_addr; u64 tdh_addr;
u32 chip_ver;
u64 chip_module_base; u64 chip_module_base;
void __iomem *chip_ver_addr;
pr_info("[INFO] %s start.\n", __func__); pr_info("[INFO] %s start.\n", __func__);
chip_ver_addr = ioremap(0x20107E238, (u64)4); chip_module_base = get_chip_base();
if (!chip_ver_addr) {
pr_err("[ERROR] %s chip_ver_base is error.\n", __func__);
return ERR_FAILED;
}
chip_ver = readl(chip_ver_addr);
chip_ver = chip_ver>>28;
if (chip_ver == CHIP_VERSION_ES) {
pr_info("[sysctl lpc] chip is es\n");
chip_module_base = HLLC_CHIP_MODULE_ES;
} else {
chip_module_base = HLLC_CHIP_MODULE_CS;
pr_info("[sysctl lpc] chip is cs\n");
}
pr_info("[sysctl lpc] chip ver=%x\n", chip_ver);
for (chip_id = 0; chip_id < CHIP_ID_NUM_MAX; chip_id++) { for (chip_id = 0; chip_id < CHIP_ID_NUM_MAX; chip_id++) {
addr = (u64)chip_id * chip_module_base + SUBCTRL_REG_BASE; addr = (u64)chip_id * chip_module_base + SUBCTRL_REG_BASE;
sysctl_subctrl_lpc_priv[chip_id] = ioremap(addr, (u64)0x10000); sysctl_subctrl_tdh_priv[chip_id] = ioremap(addr, (u64)0x10000);
debug_sysctrl_print("[DBG] subctl lpc reset addr of chip[%d]: %p.\n", debug_sysctrl_print("[DBG] subctl tdh reset addr of chip[%d]: %pK.\n",
chip_id, sysctl_subctrl_lpc_priv[chip_id]); chip_id, sysctl_subctrl_tdh_priv[chip_id]);
lpc_addr = (u64)chip_id * chip_module_base + LPC_REG_BASE;
sysctl_lpc_priv[chip_id] = ioremap(lpc_addr, (u64)0x10000);
debug_sysctrl_print("[DBG] lpc mem access ctrl addr of chip[%d]: %p.\n",
chip_id, sysctl_lpc_priv[chip_id]);
}
iounmap((void *)chip_ver_addr); tdh_addr = (u64)chip_id * chip_module_base + TDH_REG_BASE;
sysctl_tdh_priv[chip_id] = ioremap(tdh_addr, (u64)0x10000);
debug_sysctrl_print("[DBG] tdh mem access ctrl addr of chip[%d]: %pK.\n",
chip_id, sysctl_tdh_priv[chip_id]);
}
return ERR_OK; return ERR_OK;
} }
static int sysctl_lpc_deinit(void) static int sysctl_tdh_deinit(void)
{ {
u8 chip_id; u8 chip_id;
for (chip_id = 0; chip_id < CHIP_ID_NUM_MAX; chip_id++) { for (chip_id = 0; chip_id < CHIP_ID_NUM_MAX; chip_id++) {
if (sysctl_subctrl_lpc_priv[chip_id]) if (sysctl_subctrl_tdh_priv[chip_id])
iounmap((void *)sysctl_subctrl_lpc_priv[chip_id]); iounmap((void *)sysctl_subctrl_tdh_priv[chip_id]);
if (sysctl_lpc_priv[chip_id]) if (sysctl_tdh_priv[chip_id])
iounmap((void *)sysctl_lpc_priv[chip_id]); iounmap((void *)sysctl_tdh_priv[chip_id]);
} }
return ERR_OK; return ERR_OK;
} }
static int sysctl_lpc_reset(u8 chip_id) static int sysctl_tdh_reset(u8 chip_id)
{ {
void __iomem *addr; void __iomem *addr;
addr = sysctl_subctrl_lpc_priv[chip_id] + SUBCTRL_LPC_RESET_OFFSET; addr = sysctl_subctrl_tdh_priv[chip_id] + SUBCTRL_TDH_RESET_OFFSET;
writel(0x3, addr); writel(0x3, addr);
return ERR_OK; return ERR_OK;
} }
static int sysctl_lpc_unreset(u8 chip_id) static int sysctl_tdh_unreset(u8 chip_id)
{ {
void __iomem *addr; void __iomem *addr;
addr = sysctl_subctrl_lpc_priv[chip_id] + SUBCTRL_LPC_UNRESET_OFFSET; addr = sysctl_subctrl_tdh_priv[chip_id] + SUBCTRL_TDH_UNRESET_OFFSET;
writel(0x3, addr); writel(0x3, addr);
return ERR_OK; return ERR_OK;
} }
static int sysctl_lpc_mem_access_open(u8 chip_id) static int sysctl_tdh_mem_access_open(u8 chip_id)
{ {
void __iomem *addr; void __iomem *addr;
if (!sysctl_lpc_priv[chip_id]) if (!sysctl_tdh_priv[chip_id])
return ERR_PARAM; return ERR_PARAM;
addr = sysctl_lpc_priv[chip_id] + LPC_MEM_ACCESS_OFFSET; addr = sysctl_tdh_priv[chip_id] + TDH_MEM_ACCESS_OFFSET;
writel(0x0, addr); writel(0x0, addr);
return ERR_OK; return ERR_OK;
...@@ -171,8 +152,8 @@ static void unmap_gen_v2(const struct ghes *ghes) ...@@ -171,8 +152,8 @@ static void unmap_gen_v2(const struct ghes *ghes)
static int sysctl_correlation_reg_report(const struct sysctl_local_ras_cper *ras_cper) static int sysctl_correlation_reg_report(const struct sysctl_local_ras_cper *ras_cper)
{ {
switch (ras_cper->module_id) { switch (ras_cper->module_id) {
case MODULE_LPC_ERR: case MODULE_TDH_ERR:
pr_info("[INFO] SYSCTL RAS lpc correlation_reg info:\n"); pr_info("[INFO] SYSCTL RAS tdh correlation_reg info:\n");
break; break;
case MODULE_USB_ERR: case MODULE_USB_ERR:
if (ras_cper->sub_mod_id == MODULE_USB0_ERR) { if (ras_cper->sub_mod_id == MODULE_USB0_ERR) {
...@@ -187,16 +168,8 @@ static int sysctl_correlation_reg_report(const struct sysctl_local_ras_cper *ras ...@@ -187,16 +168,8 @@ static int sysctl_correlation_reg_report(const struct sysctl_local_ras_cper *ras
return -1; return -1;
} }
break; break;
case MODULE_SAS_ERR: case MODULE_SATA_ERR:
if (ras_cper->sub_mod_id == MODULE_SAS0_ERR) { pr_info("[INFO] SYSCTL RAS sata correlation_reg info:\n");
pr_info("[INFO] SYSCTL RAS sas0 correlation_reg info:\n");
} else if (ras_cper->sub_mod_id == MODULE_SAS1_ERR) {
pr_info("[INFO] SYSCTL RAS sas1 correlation_reg info:\n");
} else {
pr_err("[ERROR] SYSCTL RAS sas sub_module_id[0x%x] is error.\n",
ras_cper->sub_mod_id);
return -1;
}
break; break;
default: default:
pr_err("[ERROR] SYSCTL RAS module_id[0x%x] is error.\n", pr_err("[ERROR] SYSCTL RAS module_id[0x%x] is error.\n",
...@@ -231,25 +204,25 @@ static int sysctl_do_recovery(const struct sysctl_local_ras_cper *ras_cper) ...@@ -231,25 +204,25 @@ static int sysctl_do_recovery(const struct sysctl_local_ras_cper *ras_cper)
int ret = 0; int ret = 0;
switch (ras_cper->module_id) { switch (ras_cper->module_id) {
case MODULE_LPC_ERR: case MODULE_TDH_ERR:
sysctl_lpc_irq_cnt++; sysctl_tdh_irq_cnt++;
sysctl_lpc_reset(ras_cper->socket_id); sysctl_tdh_reset(ras_cper->socket_id);
pr_info("[INFO] SYSCTL RAS lpc of chip[%d] reset.\n", ras_cper->socket_id); pr_info("[INFO] SYSCTL RAS tdh of chip[%d] reset.\n", ras_cper->socket_id);
pr_info("[INFO] SYSCTL RAS sysctl_lpc_irq_cnt[%d].\n", sysctl_lpc_irq_cnt); pr_info("[INFO] SYSCTL RAS sysctl_tdh_irq_cnt[%d].\n", sysctl_tdh_irq_cnt);
udelay((unsigned long)20); udelay((unsigned long)20);
if (sysctl_lpc_irq_cnt <= LPC_IRQ_CNT_MAX) { if (sysctl_tdh_irq_cnt <= TDH_IRQ_CNT_MAX) {
sysctl_lpc_unreset(ras_cper->socket_id); sysctl_tdh_unreset(ras_cper->socket_id);
pr_info("[INFO] SYSCTL RAS lpc of chip[%d] unreset.\n", pr_info("[INFO] SYSCTL RAS tdh of chip[%d] unreset.\n",
ras_cper->socket_id); ras_cper->socket_id);
sysctl_lpc_mem_access_open(ras_cper->socket_id); sysctl_tdh_mem_access_open(ras_cper->socket_id);
pr_info("[INFO] SYSCTL RAS lpc of chip[%d] mem access open.\n", pr_info("[INFO] SYSCTL RAS tdh of chip[%d] mem access open.\n",
ras_cper->socket_id); ras_cper->socket_id);
} else { } else {
pr_err("[ERROR] SYSCTL RAS lpc of chip[%d] unreset %d times, won't unreset.\n", pr_err("[ERROR] SYSCTL RAS tdh of chip[%d] unreset %d times, won't unreset.\n",
ras_cper->socket_id, LPC_IRQ_CNT_MAX); ras_cper->socket_id, TDH_IRQ_CNT_MAX);
} }
break; break;
case MODULE_USB_ERR: case MODULE_USB_ERR:
...@@ -265,16 +238,8 @@ static int sysctl_do_recovery(const struct sysctl_local_ras_cper *ras_cper) ...@@ -265,16 +238,8 @@ static int sysctl_do_recovery(const struct sysctl_local_ras_cper *ras_cper)
return ret; return ret;
} }
break; break;
case MODULE_SAS_ERR: case MODULE_SATA_ERR:
if (ras_cper->sub_mod_id == MODULE_SAS0_ERR) { pr_info("[INFO] SYSCTL RAS sata error.\n");
pr_info("[INFO] SYSCTL RAS sas0 error.\n");
} else if (ras_cper->sub_mod_id == MODULE_SAS1_ERR) {
pr_info("[INFO] SYSCTL RAS sas1 error.\n");
} else {
pr_err("[ERROR] SYSCTL RAS sas sub_module_id[0x%x] is error.\n",
ras_cper->sub_mod_id);
return ret;
}
break; break;
default: default:
pr_err("[ERROR] SYSCTL RAS module_id[0x%x] is error, has not match process in sysctl.\n", pr_err("[ERROR] SYSCTL RAS module_id[0x%x] is error, has not match process in sysctl.\n",
...@@ -348,7 +313,7 @@ static struct ghes *sysctl_ghes_new(struct acpi_hest_generic *sysctl_generic) ...@@ -348,7 +313,7 @@ static struct ghes *sysctl_ghes_new(struct acpi_hest_generic *sysctl_generic)
static int sysctl_hest_hisi_parse_ghes(struct acpi_hest_header *hest_hdr, void *data) static int sysctl_hest_hisi_parse_ghes(struct acpi_hest_header *hest_hdr, void *data)
{ {
struct acpi_hest_generic *sysctl_generic; struct acpi_hest_generic *sysctl_generic;
struct ghes *sysctl_ghes; struct ghes *sysctl_ghes = NULL;
(void)data; (void)data;
sysctl_generic = container_of(hest_hdr, struct acpi_hest_generic, header); sysctl_generic = container_of(hest_hdr, struct acpi_hest_generic, header);
...@@ -414,7 +379,6 @@ static int sysctl_ghes_read_estatus(struct ghes *sysctl_ghes, int silent) ...@@ -414,7 +379,6 @@ static int sysctl_ghes_read_estatus(struct ghes *sysctl_ghes, int silent)
} }
if (!sysctl_ghes->estatus->block_status) { if (!sysctl_ghes->estatus->block_status) {
pr_err("[ERROR] SYSCTL RAS sysctl_ghes->estatus->block_status is 0.\n");
iounmap(sysctl_ghes->estatus); iounmap(sysctl_ghes->estatus);
return -ENOENT; return -ENOENT;
} }
...@@ -482,9 +446,9 @@ static void sysctl_ghes_do_proc(struct ghes *sysctl_ghes, ...@@ -482,9 +446,9 @@ static void sysctl_ghes_do_proc(struct ghes *sysctl_ghes,
{ {
struct acpi_hest_generic_data *gdata = NULL; struct acpi_hest_generic_data *gdata = NULL;
guid_t *sec_type; guid_t *sec_type = NULL;
struct sysctl_local_ras_cper *ras_cper; struct sysctl_local_ras_cper *ras_cper = NULL;
struct cper_sec_proc_arm *arm_ras_cper; struct cper_sec_proc_arm *arm_ras_cper = NULL;
(void)sysctl_ghes; (void)sysctl_ghes;
apei_estatus_for_each_section(sysct_estatus, gdata) { apei_estatus_for_each_section(sysct_estatus, gdata) {
...@@ -527,7 +491,7 @@ static int sysctl_hisi_error_handler(struct work_struct *work) ...@@ -527,7 +491,7 @@ static int sysctl_hisi_error_handler(struct work_struct *work)
{ {
int ret = 0; int ret = 0;
struct ghes *sysctl_ghes; struct ghes *sysctl_ghes = NULL;
(void)work; (void)work;
pr_info("[INFO] SYSCTL RAS %s start.\n", __func__); pr_info("[INFO] SYSCTL RAS %s start.\n", __func__);
...@@ -597,20 +561,20 @@ int hip_sysctl_local_ras_init(void) ...@@ -597,20 +561,20 @@ int hip_sysctl_local_ras_init(void)
{ {
int ret; int ret;
sysctl_lpc_init(); sysctl_tdh_init();
sysctl_acpi_hisi_hest_init(); sysctl_acpi_hisi_hest_init();
ret = register_acpi_hed_notifier(&sysctl_ghes_hisi_notifier_hed); ret = register_acpi_hed_notifier(&sysctl_ghes_hisi_notifier_hed);
sysctl_lpc_mem_access_open(0); sysctl_tdh_mem_access_open(0);
return ret; return ret;
} }
static void his_ghes_list_free(void) static void his_ghes_list_free(void)
{ {
struct ghes *sysctl_ghes; struct ghes *sysctl_ghes = NULL;
rcu_read_lock(); rcu_read_lock();
list_for_each_entry_rcu(sysctl_ghes, &hisi_ghes_list, list) { list_for_each_entry_rcu(sysctl_ghes, &hisi_ghes_list, list) {
...@@ -623,7 +587,7 @@ static void his_ghes_list_free(void) ...@@ -623,7 +587,7 @@ static void his_ghes_list_free(void)
void hip_sysctl_local_ras_exit(void) void hip_sysctl_local_ras_exit(void)
{ {
sysctl_lpc_deinit(); sysctl_tdh_deinit();
his_ghes_list_free(); his_ghes_list_free();
unregister_acpi_hed_notifier(&sysctl_ghes_hisi_notifier_hed); unregister_acpi_hed_notifier(&sysctl_ghes_hisi_notifier_hed);
......
drivers/soc/hisilicon/sysctl/sysctl_local_ras.h
浏览文件 @ 4b4ffac3
...@@ -20,8 +20,8 @@ ...@@ -20,8 +20,8 @@
#define _RP_INTERRUPT_H #define _RP_INTERRUPT_H
enum sysctl_bios_err { enum sysctl_bios_err {
MODULE_LPC_ERR = 9, MODULE_TDH_ERR = 9,
MODULE_SAS_ERR = 15, MODULE_SATA_ERR = 16,
MODULE_USB_ERR = 17, MODULE_USB_ERR = 17,
}; };
...@@ -31,11 +31,6 @@ enum sysctl_sub_usb_err { ...@@ -31,11 +31,6 @@ enum sysctl_sub_usb_err {
MODULE_USB2_ERR, MODULE_USB2_ERR,
}; };
enum sysctl_sub_sas_err {
MODULE_SAS0_ERR = 0,
MODULE_SAS1_ERR,
};
struct sysctl_validation_bits { struct sysctl_validation_bits {
u32 soc_id_vald : 1; u32 soc_id_vald : 1;
u32 socket_id_vald : 1; u32 socket_id_vald : 1;
......
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