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raspberrypi-kernel
提交 457dd4e3 编写于 作者: Y yekai13 提交者： Xie XiuQi
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acc:Revert "hisi_sec2:refactor the sec2 module code." 

driver inclusion
category: bugfix
bugzilla: NA
CVE: NA

This reverts commit f6a275ced40b7689f01ed5e72a11c7be466bda21.
There is a problem with current code.need to revert.
Signed-off-by: Nyekai13 <yekai13@huawei.com>
Reviewed-by: NZhang Wei <zhangwei375@huawei.com>
Signed-off-by: NYang Yingliang <yangyingliang@huawei.com>
上级 130bab9e
隐藏空白更改
内联 并排
Showing with 1989 addition and 2094 deletion
drivers/crypto/hisilicon/sec2/sec.h
浏览文件 @ 457dd4e3
/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2018-2019 HiSilicon Limited. */
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (c) 2018-2019 HiSilicon Limited.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#ifndef __HISI_SEC_V2_H
#define __HISI_SEC_V2_H
#ifndef HISI_SEC_H
#define HISI_SEC_H
#include <linux/list.h>
#include "../qm.h"
#include "sec_crypto.h"
#include "sec_usr_if.h"
/* Cipher resource per hardware SEC queue */
struct sec_cipher_res {
u8 *c_ivin;
dma_addr_t c_ivin_dma;
#ifdef CONFIG_CRYPTO_DEV_HISI_SEC2_FUSION
struct skcipher_request **sk_reqs;
struct scatterlist *src;
struct scatterlist *dst;
#endif
};
#undef pr_fmt
#define pr_fmt(fmt) "hisi_sec: " fmt
/* Cipher request of SEC private */
struct sec_cipher_req {
struct hisi_acc_hw_sgl *c_in;
dma_addr_t c_in_dma;
struct hisi_acc_hw_sgl *c_out;
dma_addr_t c_out_dma;
u8 *c_ivin;
dma_addr_t c_ivin_dma;
struct skcipher_request *sk_req;
u32 c_len;
#ifdef CONFIG_CRYPTO_DEV_HISI_SEC2_FUSION
u32 gran_num;
u64 lba;
struct scatterlist *src;
struct scatterlist *dst;
#endif
bool encrypt;
};
/* SEC request of Crypto */
struct sec_req {
struct sec_sqe sec_sqe;
struct sec_ctx *ctx;
struct sec_qp_ctx *qp_ctx;
/* Cipher supported only at present */
struct sec_cipher_req c_req;
int err_type;
int req_id;
/* Status of the SEC request */
int fake_busy;
#ifdef CONFIG_CRYPTO_DEV_HISI_SEC2_FUSION
struct skcipher_request **sk_reqs;
struct scatterlist *src;
struct scatterlist *dst;
int fusion_num;
ktime_t st_time;
#endif
};
/**
* struct sec_req_op - Operations for SEC request
* @get_res: Get resources for TFM on the SEC device
* @resource_alloc: Allocate resources for queue context on the SEC device
* @resource_free: Free resources for queue context on the SEC device
* @buf_map: DMA map the SGL buffers of the request
* @buf_unmap: DMA unmap the SGL buffers of the request
* @bd_fill: Fill the SEC queue BD
* @bd_send: Send the SEC BD into the hardware queue
* @callback: Call back for the request
* @process: Main processing logic of Skcipher
*/
struct sec_req_op {
int (*get_res)(struct sec_ctx *ctx, struct sec_req *req);
int (*resource_alloc)(struct sec_ctx *ctx, struct sec_qp_ctx *qp_ctx);
void (*resource_free)(struct sec_ctx *ctx, struct sec_qp_ctx *qp_ctx);
int (*buf_map)(struct sec_ctx *ctx, struct sec_req *req);
void (*buf_unmap)(struct sec_ctx *ctx, struct sec_req *req);
void (*do_transfer)(struct sec_ctx *ctx, struct sec_req *req);
int (*bd_fill)(struct sec_ctx *ctx, struct sec_req *req);
int (*bd_send)(struct sec_ctx *ctx, struct sec_req *req);
void (*callback)(struct sec_ctx *ctx, struct sec_req *req);
int (*process)(struct sec_ctx *ctx, struct sec_req *req);
};
/* SEC cipher context which cipher's relatives */
struct sec_cipher_ctx {
u8 *c_key;
dma_addr_t c_key_dma;
sector_t iv_offset;
u32 c_gran_size;
u32 ivsize;
u8 c_mode;
u8 c_alg;
u8 c_key_len;
};
/* SEC queue context which defines queue's relatives */
struct sec_qp_ctx {
struct hisi_qp *qp;
struct sec_req **req_list;
struct idr req_idr;
void *alg_meta_data;
struct sec_ctx *ctx;
struct mutex req_lock;
struct hisi_acc_sgl_pool *c_in_pool;
struct hisi_acc_sgl_pool *c_out_pool;
atomic_t pending_reqs;
#ifdef CONFIG_CRYPTO_DEV_HISI_SEC2_FUSION
struct sec_req *fusion_req;
int fusion_num;
#endif
};
/* SEC Crypto TFM context which defines queue and cipher .etc relatives */
struct sec_ctx {
struct sec_qp_ctx *qp_ctx;
struct sec_dev *sec;
const struct sec_req_op *req_op;
/* Half queues for encipher, and half for decipher */
u32 hlf_q_num;
/* Threshold for fake busy, trigger to return -EBUSY to user */
u32 fake_req_limit;
/* Currrent cyclic index to select a queue for encipher */
atomic_t enc_qcyclic;
/* Currrent cyclic index to select a queue for decipher */
atomic_t dec_qcyclic;
struct sec_cipher_ctx c_ctx;
#ifdef CONFIG_CRYPTO_DEV_HISI_SEC2_FUSION
atomic_t thread_cnt;
bool is_fusion;
struct hrtimer timer;
struct work_struct work;
#endif
};
#define CTX_Q_NUM_DEF 24
#define FUSION_LIMIT_DEF 1
#define FUSION_LIMIT_MAX 64
#define FUSION_TMOUT_NSEC_DEF (400 * 1000)
enum sec_endian {
SEC_LE = 0,
......@@ -147,24 +30,17 @@ enum sec_endian {
SEC_64BE
};
enum sec_debug_file_index {
SEC_CURRENT_QM,
SEC_CLEAR_ENABLE,
SEC_DEBUG_FILE_NUM,
};
struct hisi_sec_ctrl;
struct sec_debug_file {
enum sec_debug_file_index index;
spinlock_t lock;
struct hisi_qm *qm;
enum hisi_sec_status {
HISI_SEC_RESET,
};
struct sec_dfx {
struct hisi_sec_dfx {
u64 send_cnt;
u64 recv_cnt;
#ifdef CONFIG_CRYPTO_DEV_HISI_SEC2_FUSION
u64 send_by_tmout;
u64 send_by_full;
u64 recv_cnt;
u64 get_task_cnt;
u64 put_task_cnt;
u64 gran_task_cnt;
......@@ -172,29 +48,20 @@ struct sec_dfx {
u64 fake_busy_cnt;
u64 busy_comp_cnt;
u64 sec_ctrl;
#endif
};
struct sec_debug {
struct sec_dfx dfx;
struct sec_debug_file files[SEC_DEBUG_FILE_NUM];
};
struct sec_dev {
struct hisi_sec {
struct hisi_qm qm;
struct list_head list;
struct sec_debug debug;
u32 ctx_q_num;
u32 num_vfs;
struct hisi_sec_dfx sec_dfx;
struct hisi_sec_ctrl *ctrl;
struct mutex *hisi_sec_list_lock;
int q_ref;
int ctx_q_num;
int fusion_limit;
int fusion_tmout_nsec;
unsigned long status;
#ifdef CONFIG_CRYPTO_DEV_HISI_SEC2_FUSION
struct workqueue_struct *wq;
u32 fusion_limit;
u32 fusion_time;
#endif
};
struct sec_dev *sec_find_device(int node);
int sec_register_to_crypto(void);
void sec_unregister_from_crypto(void);
struct hisi_sec *find_sec_device(int node);
#endif
drivers/crypto/hisilicon/sec2/sec_crypto.c
浏览文件 @ 457dd4e3
// SPDX-License-Identifier: GPL-2.0
/* Copyright (c) 2019 HiSilicon Limited. */
#include <linux/crypto.h>
#include <linux/hrtimer.h>
#include <linux/dma-mapping.h>
#include <linux/ktime.h>
#include <crypto/aes.h>
#include <crypto/algapi.h>
#include <crypto/des.h>
#include <crypto/skcipher.h>
#include <crypto/xts.h>
#include <linux/crypto.h>
#include <linux/dma-mapping.h>
#include <linux/idr.h>
#include <crypto/internal/skcipher.h>
#include "sec.h"
#include "sec_crypto.h"
#define SEC_PRIORITY 4001
#define SEC_XTS_MIN_KEY_SIZE (2 * AES_MIN_KEY_SIZE)
#define SEC_XTS_MAX_KEY_SIZE (2 * AES_MAX_KEY_SIZE)
#define SEC_DES3_2KEY_SIZE (2 * DES_KEY_SIZE)
#define SEC_DES3_3KEY_SIZE (3 * DES_KEY_SIZE)
/* SEC sqe(bd) bit operational relative MACRO */
#define SEC_DE_OFFSET 1
#define SEC_CI_GEN_OFFSET 6
#define SEC_CIPHER_OFFSET 4
#define SEC_SCENE_OFFSET 3
#define SEC_DST_SGL_OFFSET 2
#define SEC_SRC_SGL_OFFSET 7
#define SEC_CKEY_OFFSET 9
#define SEC_CMODE_OFFSET 12
#define SEC_FLAG_OFFSET 7
#define SEC_FLAG_MASK 0x0780
#define SEC_TYPE_MASK 0x0F
#define SEC_DONE_MASK 0x0001
#define SEC_TOTAL_IV_SZ (SEC_IV_SIZE * QM_Q_DEPTH)
#define SEC_SGL_SGE_NR 128
#define SEC_CTX_DEV(ctx) (&(ctx)->sec->qm.pdev->dev)
static DEFINE_MUTEX(sec_algs_lock);
static unsigned int sec_active_devs;
/* Get an en/de-cipher queue cyclically to balance load over queues of TFM */
static inline int sec_get_queue_id(struct sec_ctx *ctx, struct sec_req *req)
{
if (req->c_req.encrypt)
return (u32)atomic_inc_return(&ctx->enc_qcyclic) %
ctx->hlf_q_num;
#define SEC_ASYNC
return (u32)atomic_inc_return(&ctx->dec_qcyclic) % ctx->hlf_q_num +
ctx->hlf_q_num;
}
#define SEC_INVLD_REQ_ID (-1)
#define SEC_PRIORITY (4001)
#define SEC_XTS_MIN_KEY_SIZE (2 * AES_MIN_KEY_SIZE)
#define SEC_XTS_MAX_KEY_SIZE (2 * AES_MAX_KEY_SIZE)
#define SEC_DES3_2KEY_SIZE (2 * DES_KEY_SIZE)
#define SEC_DES3_3KEY_SIZE (3 * DES_KEY_SIZE)
#define BUF_MAP_PER_SGL 64
#define SEC_FUSION_BD
enum C_ALG {
C_ALG_DES = 0x0,
C_ALG_3DES = 0x1,
C_ALG_AES = 0x2,
C_ALG_SM4 = 0x3,
};
enum C_MODE {
C_MODE_ECB = 0x0,
C_MODE_CBC = 0x1,
C_MODE_CTR = 0x4,
C_MODE_CCM = 0x5,
C_MODE_GCM = 0x6,
C_MODE_XTS = 0x7,
C_MODE_CBC_CS = 0x9,
};
enum CKEY_LEN {
CKEY_LEN_128_BIT = 0x0,
CKEY_LEN_192_BIT = 0x1,
CKEY_LEN_256_BIT = 0x2,
CKEY_LEN_DES = 0x1,
CKEY_LEN_3DES_3KEY = 0x1,
CKEY_LEN_3DES_2KEY = 0x3,
};
enum SEC_BD_TYPE {
BD_TYPE1 = 0x1,
BD_TYPE2 = 0x2,
};
enum SEC_CIPHER_TYPE {
SEC_CIPHER_ENC = 0x1,
SEC_CIPHER_DEC = 0x2,
};
enum SEC_ADDR_TYPE {
PBUF = 0x0,
SGL = 0x1,
PRP = 0x2,
};
enum SEC_CI_GEN {
CI_GEN_BY_ADDR = 0x0,
CI_GEN_BY_LBA = 0X3,
};
enum SEC_SCENE {
SCENE_IPSEC = 0x0,
SCENE_STORAGE = 0x5,
};
enum {
SEC_NO_FUSION = 0x0,
SEC_IV_FUSION = 0x1,
SEC_FUSION_BUTT
};
enum SEC_REQ_OPS_TYPE {
SEC_OPS_SKCIPHER_ALG = 0x0,
SEC_OPS_MULTI_IV = 0x1,
SEC_OPS_BUTT
};
struct cipher_res {
struct skcipher_request_ctx **sk_reqs;
u8 *c_ivin;
dma_addr_t c_ivin_dma;
struct scatterlist *src;
struct scatterlist *dst;
};
struct hisi_sec_cipher_req {
struct hisi_acc_hw_sgl *c_in;
dma_addr_t c_in_dma;
struct hisi_acc_hw_sgl *c_out;
dma_addr_t c_out_dma;
u8 *c_ivin;
dma_addr_t c_ivin_dma;
struct skcipher_request *sk_req;
struct scatterlist *src;
struct scatterlist *dst;
u32 c_len;
u32 gran_num;
u64 lba;
bool encrypt;
};
static inline void sec_put_queue_id(struct sec_ctx *ctx, struct sec_req *req)
struct hisi_sec_ctx;
struct hisi_sec_qp_ctx;
struct hisi_sec_req {
struct hisi_sec_sqe sec_sqe;
struct hisi_sec_ctx *ctx;
struct hisi_sec_qp_ctx *qp_ctx;
void **priv;
struct hisi_sec_cipher_req c_req;
ktime_t st_time;
int err_type;
int req_id;
int req_cnt;
int fusion_num;
int fake_busy;
};
struct hisi_sec_req_op {
int fusion_type;
int (*get_res)(struct hisi_sec_ctx *ctx, struct hisi_sec_req *req);
int (*queue_alloc)(struct hisi_sec_ctx *ctx,
struct hisi_sec_qp_ctx *qp_ctx);
int (*queue_free)(struct hisi_sec_ctx *ctx,
struct hisi_sec_qp_ctx *qp_ctx);
int (*buf_map)(struct hisi_sec_ctx *ctx, struct hisi_sec_req *req);
int (*buf_unmap)(struct hisi_sec_ctx *ctx, struct hisi_sec_req *req);
int (*do_transfer)(struct hisi_sec_ctx *ctx, struct hisi_sec_req *req);
int (*bd_fill)(struct hisi_sec_ctx *ctx, struct hisi_sec_req *req);
int (*bd_send)(struct hisi_sec_ctx *ctx, struct hisi_sec_req *req);
int (*callback)(struct hisi_sec_ctx *ctx, struct hisi_sec_req *req);
};
struct hisi_sec_cipher_ctx {
u8 *c_key;
dma_addr_t c_key_dma;
sector_t iv_offset;
u32 c_gran_size;
u8 c_mode;
u8 c_alg;
u8 c_key_len;
};
struct hisi_sec_qp_ctx {
struct hisi_qp *qp;
struct hisi_sec_req **req_list;
struct hisi_sec_req *fusion_req;
unsigned long *req_bitmap;
void *priv_req_res;
struct hisi_sec_ctx *ctx;
struct mutex req_lock;
atomic_t req_cnt;
struct hisi_sec_sqe *sqe_list;
struct hisi_acc_sgl_pool *c_in_pool;
struct hisi_acc_sgl_pool *c_out_pool;
int fusion_num;
int fusion_limit;
};
struct hisi_sec_ctx {
struct hisi_sec_qp_ctx *qp_ctx;
struct hisi_sec *sec;
struct device *dev;
struct hisi_sec_req_op *req_op;
struct hrtimer timer;
struct work_struct work;
atomic_t thread_cnt;
int req_fake_limit;
int req_limit;
int q_num;
int enc_q_num;
atomic_t enc_qid;
atomic_t dec_qid;
struct hisi_sec_cipher_ctx c_ctx;
int fusion_tmout_nsec;
int fusion_limit;
u64 enc_fusion_num;
u64 dec_fusion_num;
bool is_fusion;
};
#define DES_WEAK_KEY_NUM (4)
u64 des_weak_key[DES_WEAK_KEY_NUM] = {0x0101010101010101, 0xFEFEFEFEFEFEFEFE,
0xE0E0E0E0F1F1F1F1, 0x1F1F1F1F0E0E0E0E};
static void sec_update_iv(struct hisi_sec_req *req, u8 *iv)
{
if (req->c_req.encrypt)
atomic_dec(&ctx->enc_qcyclic);
else
atomic_dec(&ctx->dec_qcyclic);
// todo: update iv by cbc/ctr mode
}
static int sec_alloc_req_id(struct sec_req *req, struct sec_qp_ctx *qp_ctx)
static void hisi_sec_req_cb(struct hisi_qp *qp, void *);
static int hisi_sec_alloc_req_id(struct hisi_sec_req *req,
struct hisi_sec_qp_ctx *qp_ctx)
{
struct hisi_sec_ctx *ctx = req->ctx;
int req_id;
mutex_lock(&qp_ctx->req_lock);
req_id = idr_alloc_cyclic(&qp_ctx->req_idr, NULL,
0, QM_Q_DEPTH, GFP_ATOMIC);
mutex_unlock(&qp_ctx->req_lock);
if (req_id < 0) {
dev_err(SEC_CTX_DEV(req->ctx), "alloc req id fail!\n");
return req_id;
req_id = find_first_zero_bit(qp_ctx->req_bitmap, ctx->req_limit);
if (req_id >= ctx->req_limit || req_id < 0) {
dev_err(ctx->dev, "no free req id\n");
return -ENOBUFS;
}
set_bit(req_id, qp_ctx->req_bitmap);
req->qp_ctx = qp_ctx;
qp_ctx->req_list[req_id] = req;
return req_id;
req->req_id = req_id;
req->qp_ctx = qp_ctx;
return 0;
}
static void sec_free_req_id(struct sec_req *req)
static void hisi_sec_free_req_id(struct hisi_sec_qp_ctx *qp_ctx, int req_id)
{
struct sec_qp_ctx *qp_ctx = req->qp_ctx;
int req_id = req->req_id;
if (req_id < 0 || req_id >= QM_Q_DEPTH) {
dev_err(SEC_CTX_DEV(req->ctx), "free request id invalid!\n");
if (req_id < 0 || req_id >= qp_ctx->ctx->req_limit) {
pr_err("invalid req_id[%d]\n", req_id);
return;
}
qp_ctx->req_list[req_id] = NULL;
req->qp_ctx = NULL;
mutex_lock(&qp_ctx->req_lock);
idr_remove(&qp_ctx->req_idr, req_id);
clear_bit(req_id, qp_ctx->req_bitmap);
atomic_dec(&qp_ctx->req_cnt);
mutex_unlock(&qp_ctx->req_lock);
}
static void sec_req_cb(struct hisi_qp *qp, void *resp)
static int sec_request_transfer(struct hisi_sec_ctx *, struct hisi_sec_req *);
static int sec_request_send(struct hisi_sec_ctx *, struct hisi_sec_req *);
void qp_ctx_work_process(struct hisi_sec_qp_ctx *qp_ctx)
{
struct sec_qp_ctx *qp_ctx = qp->qp_ctx;
struct sec_sqe *bd = resp;
u16 done, flag;
u8 type;
struct sec_req *req;
type = bd->type_cipher_auth & SEC_TYPE_MASK;
if (type == SEC_BD_TYPE2) {
req = qp_ctx->req_list[le16_to_cpu(bd->type2.tag)];
req->err_type = bd->type2.error_type;
done = le16_to_cpu(bd->type2.done_flag) & SEC_DONE_MASK;
flag = (le16_to_cpu(bd->type2.done_flag) &
SEC_FLAG_MASK) >> SEC_FLAG_OFFSET;
if (req->err_type || done != 0x1 || flag != 0x2)
dev_err(SEC_CTX_DEV(req->ctx),
"err_type[%d],done[%d],flag[%d]\n",
req->err_type, done, flag);
} else {
pr_err("err bd type [%d]\n", type);
struct hisi_sec_req *req;
struct hisi_sec_ctx *ctx;
ktime_t cur_time = ktime_get();
int ret;
mutex_lock(&qp_ctx->req_lock);
req = qp_ctx->fusion_req;
if (req == NULL) {
mutex_unlock(&qp_ctx->req_lock);
return;
}
__sync_add_and_fetch(&req->ctx->sec->debug.dfx.recv_cnt, 1);
ctx = req->ctx;
if (ctx == NULL || req->fusion_num == qp_ctx->fusion_limit) {
mutex_unlock(&qp_ctx->req_lock);
return;
}
req->ctx->req_op->buf_unmap(req->ctx, req);
if (cur_time - qp_ctx->fusion_req->st_time < ctx->fusion_tmout_nsec) {
mutex_unlock(&qp_ctx->req_lock);
return;
}
req->ctx->req_op->callback(req->ctx, req);
qp_ctx->fusion_req = NULL;
mutex_unlock(&qp_ctx->req_lock);
ret = sec_request_transfer(ctx, req);
if (ret)
goto err_free_req;
ret = sec_request_send(ctx, req);
__sync_add_and_fetch(&ctx->sec->sec_dfx.send_by_tmout, 1);
if (ret != -EBUSY && ret != -EINPROGRESS) {
dev_err(ctx->dev, "[%s][%d] ret[%d]\n", __func__,
__LINE__, ret);
goto err_unmap_req;
}
return;
err_unmap_req:
ctx->req_op->buf_unmap(ctx, req);
err_free_req:
hisi_sec_free_req_id(qp_ctx, req->req_id);
atomic_dec(&ctx->thread_cnt);
}
static int sec_bd_send(struct sec_ctx *ctx, struct sec_req *req)
void ctx_work_process(struct work_struct *work)
{
struct sec_qp_ctx *qp_ctx = req->qp_ctx;
int ret;
struct hisi_sec_ctx *ctx;
int i;
mutex_lock(&qp_ctx->req_lock);
ret = hisi_qp_send(qp_ctx->qp, &req->sec_sqe);
mutex_unlock(&qp_ctx->req_lock);
__sync_add_and_fetch(&ctx->sec->debug.dfx.send_cnt, 1);
ctx = container_of(work, struct hisi_sec_ctx, work);
for (i = 0; i < ctx->q_num; i++)
qp_ctx_work_process(&ctx->qp_ctx[i]);
}
if (ret == -EBUSY)
return -ENOBUFS;
static enum hrtimer_restart hrtimer_handler(struct hrtimer *timer)
{
struct hisi_sec_ctx *ctx;
ktime_t tim;
if (!ret) {
if (req->fake_busy)
ret = -EBUSY;
else
ret = -EINPROGRESS;
}
ctx = container_of(timer, struct hisi_sec_ctx, timer);
tim = ktime_set(0, ctx->fusion_tmout_nsec);
return ret;
if (ctx->sec->qm.wq)
queue_work(ctx->sec->qm.wq, &ctx->work);
else
schedule_work(&ctx->work);
hrtimer_forward(timer, timer->base->get_time(), tim);
return HRTIMER_RESTART;
}
static int sec_create_qp_ctx(struct hisi_qm *qm, struct sec_ctx *ctx,
int qp_ctx_id, int alg_type)
static int hisi_sec_create_qp_ctx(struct hisi_qm *qm, struct hisi_sec_ctx *ctx,
int qp_ctx_id, int alg_type, int req_type)
{
struct device *dev = SEC_CTX_DEV(ctx);
struct sec_qp_ctx *qp_ctx;
struct hisi_qp *qp;
int ret = -ENOMEM;
struct hisi_sec_qp_ctx *qp_ctx;
struct device *dev = ctx->dev;
int ret;
qp = hisi_qm_create_qp(qm, alg_type);
if (IS_ERR(qp))
return PTR_ERR(qp);
qp_ctx = &ctx->qp_ctx[qp_ctx_id];
qp->req_type = 0;
qp->req_type = req_type;
qp->qp_ctx = qp_ctx;
qp->req_cb = sec_req_cb;
#ifdef SEC_ASYNC
qp->req_cb = hisi_sec_req_cb;
#endif
qp_ctx->qp = qp;
qp_ctx->fusion_num = 0;
qp_ctx->fusion_req = NULL;
qp_ctx->fusion_limit = ctx->fusion_limit;
qp_ctx->ctx = ctx;
mutex_init(&qp_ctx->req_lock);
atomic_set(&qp_ctx->pending_reqs, 0);
idr_init(&qp_ctx->req_idr);
atomic_set(&qp_ctx->req_cnt, 0);
qp_ctx->req_bitmap = kcalloc(BITS_TO_LONGS(QM_Q_DEPTH), sizeof(long),
GFP_ATOMIC);
if (!qp_ctx->req_bitmap) {
ret = -ENOMEM;
goto err_qm_release_qp;
}
qp_ctx->req_list = kcalloc(QM_Q_DEPTH, sizeof(void *), GFP_ATOMIC);
if (!qp_ctx->req_list)
goto err_destroy_idr;
if (!qp_ctx->req_list) {
ret = -ENOMEM;
goto err_free_req_bitmap;
}
qp_ctx->c_in_pool = hisi_acc_create_sgl_pool(dev, QM_Q_DEPTH,
SEC_SGL_SGE_NR);
if (!qp_ctx->c_in_pool) {
dev_err(dev, "fail to create sgl pool for input!\n");
qp_ctx->sqe_list = kcalloc(ctx->fusion_limit,
sizeof(struct hisi_sec_sqe), GFP_KERNEL);
if (!qp_ctx->sqe_list) {
ret = -ENOMEM;
goto err_free_req_list;
}
qp_ctx->c_in_pool = hisi_acc_create_sgl_pool(dev, QM_Q_DEPTH,
FUSION_LIMIT_MAX);
if (IS_ERR(qp_ctx->c_in_pool)) {
ret = PTR_ERR(qp_ctx->c_in_pool);
goto err_free_sqe_list;
}
qp_ctx->c_out_pool = hisi_acc_create_sgl_pool(dev, QM_Q_DEPTH,
SEC_SGL_SGE_NR);
if (!qp_ctx->c_out_pool) {
dev_err(dev, "fail to create sgl pool for output!\n");
FUSION_LIMIT_MAX);
if (IS_ERR(qp_ctx->c_out_pool)) {
ret = PTR_ERR(qp_ctx->c_out_pool);
goto err_free_c_in_pool;
}
ret = ctx->req_op->resource_alloc(ctx, qp_ctx);
ret = ctx->req_op->queue_alloc(ctx, qp_ctx);
if (ret)
goto err_free_c_out_pool;
......@@ -202,122 +396,302 @@ static int sec_create_qp_ctx(struct hisi_qm *qm, struct sec_ctx *ctx,
return 0;
err_queue_free:
ctx->req_op->resource_free(ctx, qp_ctx);
ctx->req_op->queue_free(ctx, qp_ctx);
err_free_c_out_pool:
hisi_acc_free_sgl_pool(dev, qp_ctx->c_out_pool);
err_free_c_in_pool:
hisi_acc_free_sgl_pool(dev, qp_ctx->c_in_pool);
err_free_sqe_list:
kfree(qp_ctx->sqe_list);
err_free_req_list:
kfree(qp_ctx->req_list);
err_destroy_idr:
idr_destroy(&qp_ctx->req_idr);
err_free_req_bitmap:
kfree(qp_ctx->req_bitmap);
err_qm_release_qp:
hisi_qm_release_qp(qp);
return ret;
}
static void sec_release_qp_ctx(struct sec_ctx *ctx,
struct sec_qp_ctx *qp_ctx)
static void hisi_sec_release_qp_ctx(struct hisi_sec_ctx *ctx,
struct hisi_sec_qp_ctx *qp_ctx)
{
struct device *dev = SEC_CTX_DEV(ctx);
struct device *dev = ctx->dev;
hisi_qm_stop_qp(qp_ctx->qp);
ctx->req_op->resource_free(ctx, qp_ctx);
ctx->req_op->queue_free(ctx, qp_ctx);
hisi_acc_free_sgl_pool(dev, qp_ctx->c_out_pool);
hisi_acc_free_sgl_pool(dev, qp_ctx->c_in_pool);
idr_destroy(&qp_ctx->req_idr);
kfree(qp_ctx->req_bitmap);
kfree(qp_ctx->req_list);
kfree(qp_ctx->sqe_list);
hisi_qm_release_qp(qp_ctx->qp);
}
static int sec_skcipher_init(struct crypto_skcipher *tfm)
static int __hisi_sec_ctx_init(struct hisi_sec_ctx *ctx, int qlen)
{
struct sec_ctx *ctx = crypto_skcipher_ctx(tfm);
struct sec_cipher_ctx *c_ctx;
struct sec_dev *sec;
struct device *dev;
if (!ctx || qlen < 0)
return -EINVAL;
ctx->req_limit = qlen;
ctx->req_fake_limit = qlen / 2;
atomic_set(&ctx->thread_cnt, 0);
atomic_set(&ctx->enc_qid, 0);
atomic_set(&ctx->dec_qid, ctx->enc_q_num);
if (ctx->fusion_limit > 1 && ctx->fusion_tmout_nsec > 0) {
ktime_t tim = ktime_set(0, ctx->fusion_tmout_nsec);
hrtimer_init(&ctx->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
ctx->timer.function = hrtimer_handler;
hrtimer_start(&ctx->timer, tim, HRTIMER_MODE_REL);
INIT_WORK(&ctx->work, ctx_work_process);
}
return 0;
}
static void hisi_sec_get_fusion_param(struct hisi_sec_ctx *ctx,
struct hisi_sec *sec)
{
if (ctx->is_fusion) {
ctx->fusion_tmout_nsec = sec->fusion_tmout_nsec;
ctx->fusion_limit = sec->fusion_limit;
} else {
ctx->fusion_tmout_nsec = 0;
ctx->fusion_limit = 1;
}
}
static int hisi_sec_cipher_ctx_init(struct crypto_skcipher *tfm)
{
struct hisi_sec_ctx *ctx = crypto_skcipher_ctx(tfm);
struct hisi_qm *qm;
struct hisi_sec_cipher_ctx *c_ctx;
struct hisi_sec *sec;
int i, ret;
crypto_skcipher_set_reqsize(tfm, sizeof(struct sec_req));
crypto_skcipher_set_reqsize(tfm, sizeof(struct hisi_sec_req));
sec = sec_find_device(cpu_to_node(smp_processor_id()));
sec = find_sec_device(cpu_to_node(smp_processor_id()));
if (!sec) {
pr_err("find no Hisilicon SEC device!\n");
pr_err("failed to find a proper sec device!\n");
return -ENODEV;
}
ctx->sec = sec;
qm = &sec->qm;
dev = &qm->pdev->dev;
ctx->hlf_q_num = sec->ctx_q_num >> 0x1;
ctx->dev = &qm->pdev->dev;
ctx->q_num = sec->ctx_q_num;
/* Half of queue depth is taken as fake requests limit in the queue. */
ctx->fake_req_limit = QM_Q_DEPTH >> 0x1;
ctx->qp_ctx = kcalloc(sec->ctx_q_num, sizeof(struct sec_qp_ctx),
GFP_KERNEL);
ctx->enc_q_num = ctx->q_num / 2;
ctx->qp_ctx = kcalloc(ctx->q_num, sizeof(struct hisi_sec_qp_ctx),
GFP_KERNEL);
if (!ctx->qp_ctx)
return -ENOMEM;
for (i = 0; i < sec->ctx_q_num; i++) {
ret = sec_create_qp_ctx(qm, ctx, i, 0);
hisi_sec_get_fusion_param(ctx, sec);
for (i = 0; i < ctx->q_num; i++) {
ret = hisi_sec_create_qp_ctx(qm, ctx, i, 0, 0);
if (ret)
goto err_sec_release_qp_ctx;
}
c_ctx = &ctx->c_ctx;
c_ctx->ivsize = crypto_skcipher_ivsize(tfm);
if (c_ctx->ivsize > SEC_IV_SIZE) {
dev_err(dev, "get error iv size!\n");
ret = -EINVAL;
goto err_sec_release_qp_ctx;
}
c_ctx->c_key = dma_alloc_coherent(dev, SEC_MAX_KEY_SIZE,
&c_ctx->c_key_dma, GFP_KERNEL);
if (!c_ctx->c_key) {
c_ctx->c_key = dma_alloc_coherent(ctx->dev,
SEC_MAX_KEY_SIZE, &c_ctx->c_key_dma, GFP_KERNEL);
if (!ctx->c_ctx.c_key) {
ret = -ENOMEM;
goto err_sec_release_qp_ctx;
}
return 0;
return __hisi_sec_ctx_init(ctx, QM_Q_DEPTH);
err_sec_release_qp_ctx:
for (i = i - 1; i >= 0; i--)
sec_release_qp_ctx(ctx, &ctx->qp_ctx[i]);
hisi_sec_release_qp_ctx(ctx, &ctx->qp_ctx[i]);
kfree(ctx->qp_ctx);
return ret;
}
static void sec_skcipher_exit(struct crypto_skcipher *tfm)
static void hisi_sec_cipher_ctx_exit(struct crypto_skcipher *tfm)
{
struct sec_ctx *ctx = crypto_skcipher_ctx(tfm);
struct sec_cipher_ctx *c_ctx = &ctx->c_ctx;
struct hisi_sec_ctx *ctx = crypto_skcipher_ctx(tfm);
struct hisi_sec_cipher_ctx *c_ctx;
int i = 0;
c_ctx = &ctx->c_ctx;
if (ctx->fusion_limit > 1 && ctx->fusion_tmout_nsec > 0)
hrtimer_cancel(&ctx->timer);
if (c_ctx->c_key) {
dma_free_coherent(SEC_CTX_DEV(ctx), SEC_MAX_KEY_SIZE,
c_ctx->c_key, c_ctx->c_key_dma);
dma_free_coherent(ctx->dev, SEC_MAX_KEY_SIZE, c_ctx->c_key,
c_ctx->c_key_dma);
c_ctx->c_key = NULL;
}
for (i = 0; i < ctx->sec->ctx_q_num; i++)
sec_release_qp_ctx(ctx, &ctx->qp_ctx[i]);
for (i = 0; i < ctx->q_num; i++)
hisi_sec_release_qp_ctx(ctx, &ctx->qp_ctx[i]);
kfree(ctx->qp_ctx);
mutex_lock(ctx->sec->hisi_sec_list_lock);
ctx->sec->q_ref -= ctx->sec->ctx_q_num;
mutex_unlock(ctx->sec->hisi_sec_list_lock);
}
static int hisi_sec_skcipher_get_res(struct hisi_sec_ctx *ctx,
struct hisi_sec_req *req);
static int hisi_sec_skcipher_queue_alloc(struct hisi_sec_ctx *ctx,
struct hisi_sec_qp_ctx *qp_ctx);
static int hisi_sec_skcipher_queue_free(struct hisi_sec_ctx *ctx,
struct hisi_sec_qp_ctx *qp_ctx);
static int hisi_sec_skcipher_buf_map(struct hisi_sec_ctx *ctx,
struct hisi_sec_req *req);
static int hisi_sec_skcipher_buf_unmap(struct hisi_sec_ctx *ctx,
struct hisi_sec_req *req);
static int hisi_sec_skcipher_copy_iv(struct hisi_sec_ctx *ctx,
struct hisi_sec_req *req);
static int hisi_sec_skcipher_bd_fill_base(struct hisi_sec_ctx *ctx,
struct hisi_sec_req *req);
static int hisi_sec_skcipher_bd_fill_storage(struct hisi_sec_ctx *ctx,
struct hisi_sec_req *req);
static int hisi_sec_skcipher_bd_fill_multi_iv(struct hisi_sec_ctx *ctx,
struct hisi_sec_req *req);
static int hisi_sec_bd_send_asyn(struct hisi_sec_ctx *ctx,
struct hisi_sec_req *req);
static int hisi_sec_skcipher_callback(struct hisi_sec_ctx *ctx,
struct hisi_sec_req *req);
struct hisi_sec_req_op sec_req_ops_tbl[] = {
{
.fusion_type = SEC_NO_FUSION,
.get_res = hisi_sec_skcipher_get_res,
.queue_alloc = hisi_sec_skcipher_queue_alloc,
.queue_free = hisi_sec_skcipher_queue_free,
.buf_map = hisi_sec_skcipher_buf_map,
.buf_unmap = hisi_sec_skcipher_buf_unmap,
.do_transfer = hisi_sec_skcipher_copy_iv,
.bd_fill = hisi_sec_skcipher_bd_fill_base,
.bd_send = hisi_sec_bd_send_asyn,
.callback = hisi_sec_skcipher_callback,
}, {
.fusion_type = SEC_IV_FUSION,
.get_res = hisi_sec_skcipher_get_res,
.queue_alloc = hisi_sec_skcipher_queue_alloc,
.queue_free = hisi_sec_skcipher_queue_free,
.buf_map = hisi_sec_skcipher_buf_map,
.buf_unmap = hisi_sec_skcipher_buf_unmap,
.do_transfer = hisi_sec_skcipher_copy_iv,
.bd_fill = hisi_sec_skcipher_bd_fill_multi_iv,
.bd_send = hisi_sec_bd_send_asyn,
.callback = hisi_sec_skcipher_callback,
}
};
static int hisi_sec_cipher_ctx_init_alg(struct crypto_skcipher *tfm)
{
struct hisi_sec_ctx *ctx = crypto_skcipher_ctx(tfm);
ctx->req_op = &sec_req_ops_tbl[SEC_OPS_SKCIPHER_ALG];
ctx->is_fusion = ctx->req_op->fusion_type;
return hisi_sec_cipher_ctx_init(tfm);
}
static int hisi_sec_cipher_ctx_init_multi_iv(struct crypto_skcipher *tfm)
{
struct hisi_sec_ctx *ctx = crypto_skcipher_ctx(tfm);
ctx->req_op = &sec_req_ops_tbl[SEC_OPS_MULTI_IV];
ctx->is_fusion = ctx->req_op->fusion_type;
return hisi_sec_cipher_ctx_init(tfm);
}
static void hisi_sec_req_cb(struct hisi_qp *qp, void *resp)
{
struct hisi_sec_sqe *sec_sqe = (struct hisi_sec_sqe *)resp;
u32 req_id;
struct hisi_sec_qp_ctx *qp_ctx = qp->qp_ctx;
struct hisi_sec_req *req;
struct hisi_sec_dfx *dfx;
if (sec_sqe->type == 1) {
req_id = sec_sqe->type1.tag;
req = qp_ctx->req_list[req_id];
req->err_type = sec_sqe->type1.error_type;
if (req->err_type || sec_sqe->type1.done != 0x1 ||
sec_sqe->type1.flag != 0x2) {
pr_err("err_type[%d] done[%d] flag[%d]\n",
req->err_type, sec_sqe->type1.done,
sec_sqe->type1.flag);
}
} else if (sec_sqe->type == 2) {
req_id = sec_sqe->type2.tag;
req = qp_ctx->req_list[req_id];
req->err_type = sec_sqe->type2.error_type;
if (req->err_type || sec_sqe->type2.done != 0x1 ||
sec_sqe->type2.flag != 0x2) {
pr_err("err_type[%d] done[%d] flag[%d]\n",
req->err_type, sec_sqe->type2.done,
sec_sqe->type2.flag);
}
} else {
pr_err("err bd type [%d]\n", sec_sqe->type);
return;
}
dfx = &req->ctx->sec->sec_dfx;
sec_update_iv(req, req->c_req.sk_req->iv);
req->ctx->req_op->buf_unmap(req->ctx, req);
req->ctx->req_op->callback(req->ctx, req);
__sync_add_and_fetch(&dfx->recv_cnt, 1);
}
static int sec_skcipher_3des_setkey(struct sec_cipher_ctx *c_ctx,
const u32 keylen,
const enum sec_cmode c_mode)
static int sec_des_weak_key(const u64 *key, const u32 keylen)
{
int i;
for (i = 0; i < DES_WEAK_KEY_NUM; i++)
if (*key == des_weak_key[i])
return 1;
return 0;
}
static int sec_skcipher_des_setkey(struct hisi_sec_cipher_ctx *c_ctx,
const u32 keylen, const u8 *key)
{
if (keylen != DES_KEY_SIZE)
return -EINVAL;
if (sec_des_weak_key((const u64 *)key, keylen))
return -EKEYREJECTED;
c_ctx->c_key_len = CKEY_LEN_DES;
return 0;
}
static int sec_skcipher_3des_setkey(struct hisi_sec_cipher_ctx *c_ctx,
const u32 keylen, const enum C_MODE c_mode)
{
switch (keylen) {
case SEC_DES3_2KEY_SIZE:
c_ctx->c_key_len = SEC_CKEY_3DES_2KEY;
c_ctx->c_key_len = CKEY_LEN_3DES_2KEY;
break;
case SEC_DES3_3KEY_SIZE:
c_ctx->c_key_len = SEC_CKEY_3DES_3KEY;
c_ctx->c_key_len = CKEY_LEN_3DES_3KEY;
break;
default:
return -EINVAL;
......@@ -326,35 +700,32 @@ static int sec_skcipher_3des_setkey(struct sec_cipher_ctx *c_ctx,
return 0;
}
static int sec_skcipher_aes_sm4_setkey(struct sec_cipher_ctx *c_ctx,
const u32 keylen,
const enum sec_cmode c_mode)
static int sec_skcipher_aes_sm4_setkey(struct hisi_sec_cipher_ctx *c_ctx,
const u32 keylen, const enum C_MODE c_mode)
{
if (c_mode == SEC_CMODE_XTS) {
if (c_mode == C_MODE_XTS) {
switch (keylen) {
case SEC_XTS_MIN_KEY_SIZE:
c_ctx->c_key_len = SEC_CKEY_128BIT;
c_ctx->c_key_len = CKEY_LEN_128_BIT;
break;
case SEC_XTS_MAX_KEY_SIZE:
c_ctx->c_key_len = SEC_CKEY_256BIT;
c_ctx->c_key_len = CKEY_LEN_256_BIT;
break;
default:
pr_err("hisi_sec2: xts mode key error!\n");
return -EINVAL;
}
} else {
switch (keylen) {
case AES_KEYSIZE_128:
c_ctx->c_key_len = SEC_CKEY_128BIT;
c_ctx->c_key_len = CKEY_LEN_128_BIT;
break;
case AES_KEYSIZE_192:
c_ctx->c_key_len = SEC_CKEY_192BIT;
c_ctx->c_key_len = CKEY_LEN_192_BIT;
break;
case AES_KEYSIZE_256:
c_ctx->c_key_len = SEC_CKEY_256BIT;
c_ctx->c_key_len = CKEY_LEN_256_BIT;
break;
default:
pr_err("hisi_sec2: aes key error!\n");
return -EINVAL;
}
}
......@@ -363,40 +734,38 @@ static int sec_skcipher_aes_sm4_setkey(struct sec_cipher_ctx *c_ctx,
}
static int sec_skcipher_setkey(struct crypto_skcipher *tfm, const u8 *key,
const u32 keylen, const enum sec_calg c_alg,
const enum sec_cmode c_mode)
const u32 keylen, const enum C_ALG c_alg, const enum C_MODE c_mode)
{
struct sec_ctx *ctx = crypto_skcipher_ctx(tfm);
struct sec_cipher_ctx *c_ctx = &ctx->c_ctx;
struct hisi_sec_ctx *ctx = crypto_skcipher_ctx(tfm);
struct hisi_sec_cipher_ctx *c_ctx = &ctx->c_ctx;
int ret;
if (c_mode == SEC_CMODE_XTS) {
if (c_mode == C_MODE_XTS) {
ret = xts_verify_key(tfm, key, keylen);
if (ret) {
dev_err(SEC_CTX_DEV(ctx), "xts mode key err!\n");
if (ret)
return ret;
}
}
c_ctx->c_alg = c_alg;
c_ctx->c_mode = c_mode;
switch (c_alg) {
case SEC_CALG_3DES:
case C_ALG_DES:
ret = sec_skcipher_des_setkey(c_ctx, keylen, key);
break;
case C_ALG_3DES:
ret = sec_skcipher_3des_setkey(c_ctx, keylen, c_mode);
break;
case SEC_CALG_AES:
case SEC_CALG_SM4:
case C_ALG_AES:
case C_ALG_SM4:
ret = sec_skcipher_aes_sm4_setkey(c_ctx, keylen, c_mode);
break;
default:
return -EINVAL;
}
if (ret) {
dev_err(SEC_CTX_DEV(ctx), "set sec key err!\n");
if (ret)
return ret;
}
memcpy(c_ctx->c_key, key, keylen);
......@@ -405,495 +774,495 @@ static int sec_skcipher_setkey(struct crypto_skcipher *tfm, const u8 *key,
#define GEN_SEC_SETKEY_FUNC(name, c_alg, c_mode) \
static int sec_setkey_##name(struct crypto_skcipher *tfm, const u8 *key,\
u32 keylen) \
u32 keylen)\
{ \
return sec_skcipher_setkey(tfm, key, keylen, c_alg, c_mode); \
}
GEN_SEC_SETKEY_FUNC(aes_ecb, SEC_CALG_AES, SEC_CMODE_ECB)
GEN_SEC_SETKEY_FUNC(aes_cbc, SEC_CALG_AES, SEC_CMODE_CBC)
GEN_SEC_SETKEY_FUNC(aes_xts, SEC_CALG_AES, SEC_CMODE_XTS)
GEN_SEC_SETKEY_FUNC(aes_ecb, C_ALG_AES, C_MODE_ECB)
GEN_SEC_SETKEY_FUNC(aes_cbc, C_ALG_AES, C_MODE_CBC)
GEN_SEC_SETKEY_FUNC(sm4_cbc, C_ALG_SM4, C_MODE_CBC)
GEN_SEC_SETKEY_FUNC(des_ecb, C_ALG_DES, C_MODE_ECB)
GEN_SEC_SETKEY_FUNC(des_cbc, C_ALG_DES, C_MODE_CBC)
GEN_SEC_SETKEY_FUNC(3des_ecb, C_ALG_3DES, C_MODE_ECB)
GEN_SEC_SETKEY_FUNC(3des_cbc, C_ALG_3DES, C_MODE_CBC)
GEN_SEC_SETKEY_FUNC(3des_ecb, SEC_CALG_3DES, SEC_CMODE_ECB)
GEN_SEC_SETKEY_FUNC(3des_cbc, SEC_CALG_3DES, SEC_CMODE_CBC)
GEN_SEC_SETKEY_FUNC(aes_xts, C_ALG_AES, C_MODE_XTS)
GEN_SEC_SETKEY_FUNC(sm4_xts, C_ALG_SM4, C_MODE_XTS)
static int hisi_sec_get_async_ret(int ret, int req_cnt, int req_fake_limit)
{
if (ret == 0) {
if (req_cnt >= req_fake_limit)
ret = -EBUSY;
else
ret = -EINPROGRESS;
} else {
if (ret == -EBUSY)
ret = -ENOBUFS;
}
GEN_SEC_SETKEY_FUNC(sm4_xts, SEC_CALG_SM4, SEC_CMODE_XTS)
GEN_SEC_SETKEY_FUNC(sm4_cbc, SEC_CALG_SM4, SEC_CMODE_CBC)
return ret;
}
static int sec_skcipher_get_res(struct sec_ctx *ctx,
struct sec_req *req)
static int hisi_sec_skcipher_get_res(struct hisi_sec_ctx *ctx,
struct hisi_sec_req *req)
{
struct sec_qp_ctx *qp_ctx = req->qp_ctx;
struct sec_cipher_res *c_res = qp_ctx->alg_meta_data;
struct sec_cipher_req *c_req = &req->c_req;
struct hisi_sec_cipher_req *c_req = &req->c_req;
struct hisi_sec_qp_ctx *qp_ctx = req->qp_ctx;
struct cipher_res *c_res = (struct cipher_res *)qp_ctx->priv_req_res;
int req_id = req->req_id;
c_req->c_ivin = c_res[req_id].c_ivin;
c_req->c_ivin_dma = c_res[req_id].c_ivin_dma;
req->priv = (void **)c_res[req_id].sk_reqs;
c_req->src = c_res[req_id].src;
c_req->dst = c_res[req_id].dst;
return 0;
}
static int sec_skcipher_resource_alloc(struct sec_ctx *ctx,
struct sec_qp_ctx *qp_ctx)
static int hisi_sec_skcipher_queue_alloc(struct hisi_sec_ctx *ctx,
struct hisi_sec_qp_ctx *qp_ctx)
{
struct device *dev = SEC_CTX_DEV(ctx);
struct sec_cipher_res *res;
int i;
struct cipher_res *c_res;
int req_num = ctx->fusion_limit;
int alloc_num = QM_Q_DEPTH * ctx->fusion_limit;
int buf_map_num = QM_Q_DEPTH * ctx->fusion_limit;
struct device *dev = ctx->dev;
int i, ret;
res = kcalloc(QM_Q_DEPTH, sizeof(struct sec_cipher_res), GFP_KERNEL);
if (!res)
c_res = kcalloc(QM_Q_DEPTH, sizeof(struct cipher_res), GFP_KERNEL);
if (!c_res)
return -ENOMEM;
res->c_ivin = dma_alloc_coherent(dev, SEC_TOTAL_IV_SZ,
&res->c_ivin_dma, GFP_KERNEL);
if (!res->c_ivin) {
kfree(res);
return -ENOMEM;
qp_ctx->priv_req_res = (void *)c_res;
c_res[0].sk_reqs = kcalloc(alloc_num,
sizeof(struct skcipher_request_ctx *), GFP_KERNEL);
if (!c_res[0].sk_reqs) {
ret = -ENOMEM;
goto err_free_c_res;
}
c_res[0].c_ivin = dma_alloc_coherent(dev,
SEC_IV_SIZE * alloc_num, &c_res[0].c_ivin_dma, GFP_KERNEL);
if (!c_res[0].c_ivin) {
ret = -ENOMEM;
goto err_free_sk_reqs;
}
c_res[0].src = kcalloc(buf_map_num, sizeof(struct scatterlist),
GFP_KERNEL);
if (!c_res[0].src) {
ret = -ENOMEM;
goto err_free_c_ivin;
}
c_res[0].dst = kcalloc(buf_map_num, sizeof(struct scatterlist),
GFP_KERNEL);
if (!c_res[0].dst) {
ret = -ENOMEM;
goto err_free_src;
}
for (i = 1; i < QM_Q_DEPTH; i++) {
res[i].c_ivin_dma = res->c_ivin_dma + i * SEC_IV_SIZE;
res[i].c_ivin = res->c_ivin + i * SEC_IV_SIZE;
c_res[i].sk_reqs = c_res[0].sk_reqs + i * req_num;
c_res[i].c_ivin = c_res[0].c_ivin
+ i * req_num * SEC_IV_SIZE;
c_res[i].c_ivin_dma = c_res[0].c_ivin_dma
+ i * req_num * SEC_IV_SIZE;
c_res[i].src = c_res[0].src + i * req_num;
c_res[i].dst = c_res[0].dst + i * req_num;
}
qp_ctx->alg_meta_data = res;
return 0;
err_free_src:
kfree(c_res[0].src);
err_free_c_ivin:
dma_free_coherent(dev, SEC_IV_SIZE * alloc_num, c_res[0].c_ivin,
c_res[0].c_ivin_dma);
err_free_sk_reqs:
kfree(c_res[0].sk_reqs);
err_free_c_res:
kfree(c_res);
return ret;
}
static void sec_skcipher_resource_free(struct sec_ctx *ctx,
struct sec_qp_ctx *qp_ctx)
static int hisi_sec_skcipher_queue_free(struct hisi_sec_ctx *ctx,
struct hisi_sec_qp_ctx *qp_ctx)
{
struct sec_cipher_res *res = qp_ctx->alg_meta_data;
struct device *dev = SEC_CTX_DEV(ctx);
struct cipher_res *c_res = (struct cipher_res *)qp_ctx->priv_req_res;
struct device *dev = ctx->dev;
int alloc_num = QM_Q_DEPTH * ctx->fusion_limit;
if (!res)
return;
kfree(c_res[0].dst);
kfree(c_res[0].src);
dma_free_coherent(dev, SEC_IV_SIZE * alloc_num, c_res[0].c_ivin,
c_res[0].c_ivin_dma);
kfree(c_res[0].sk_reqs);
kfree(c_res);
dma_free_coherent(dev, SEC_TOTAL_IV_SZ, res->c_ivin, res->c_ivin_dma);
kfree(res);
return 0;
}
static int sec_skcipher_map(struct device *dev, struct sec_req *req,
struct scatterlist *src, struct scatterlist *dst)
static int hisi_sec_skcipher_buf_map(struct hisi_sec_ctx *ctx,
struct hisi_sec_req *req)
{
struct sec_cipher_req *c_req = &req->c_req;
struct sec_qp_ctx *qp_ctx = req->qp_ctx;
c_req->c_in = hisi_acc_sg_buf_map_to_hw_sgl(dev, src,
qp_ctx->c_in_pool,
req->req_id,
&c_req->c_in_dma);
struct hisi_sec_cipher_req *c_req = &req->c_req;
struct device *dev = ctx->dev;
struct skcipher_request *sk_next;
struct hisi_sec_qp_ctx *qp_ctx = req->qp_ctx;
int src_nents, src_nents_sum, copyed_src_nents;
int dst_nents, dst_nents_sum, copyed_dst_nents;
int i, ret, buf_map_limit;
if (IS_ERR(c_req->c_in)) {
dev_err(dev, "fail to dma map input sgl buffers!\n");
return PTR_ERR(c_req->c_in);
}
src_nents_sum = 0;
dst_nents_sum = 0;
for (i = 0; i < req->fusion_num; i++) {
sk_next = (struct skcipher_request *)req->priv[i];
if (sk_next == NULL) {
dev_err(ctx->dev, "nullptr at [%d]\n", i);
return -EFAULT;
}
src_nents_sum += sg_nents(sk_next->src);
dst_nents_sum += sg_nents(sk_next->dst);
if (sk_next->src == sk_next->dst && i > 0) {
dev_err(ctx->dev, "err: src == dst\n");
return -EFAULT;
}
}
buf_map_limit = FUSION_LIMIT_MAX;
if (src_nents_sum > buf_map_limit || dst_nents_sum > buf_map_limit) {
dev_err(ctx->dev, "src[%d] or dst[%d] bigger than %d\n",
src_nents_sum, dst_nents_sum, buf_map_limit);
return -ENOBUFS;
}
copyed_src_nents = 0;
copyed_dst_nents = 0;
for (i = 0; i < req->fusion_num; i++) {
sk_next = (struct skcipher_request *)req->priv[i];
src_nents = sg_nents(sk_next->src);
dst_nents = sg_nents(sk_next->dst);
if (i != req->fusion_num - 1) {
sg_unmark_end(&sk_next->src[src_nents - 1]);
sg_unmark_end(&sk_next->dst[dst_nents - 1]);
}
memcpy(c_req->src + copyed_src_nents, sk_next->src,
src_nents * sizeof(struct scatterlist));
memcpy(c_req->dst + copyed_dst_nents, sk_next->dst,
dst_nents * sizeof(struct scatterlist));
copyed_src_nents += src_nents;
copyed_dst_nents += dst_nents;
}
c_req->c_in = hisi_acc_sg_buf_map_to_hw_sgl(dev, c_req->src,
qp_ctx->c_in_pool, req->req_id, &c_req->c_in_dma);
if (IS_ERR(c_req->c_in))
return PTR_ERR(c_req->c_in);
if (dst == src) {
if (c_req->dst == c_req->src) {
c_req->c_out = c_req->c_in;
c_req->c_out_dma = c_req->c_in_dma;
} else {
c_req->c_out = hisi_acc_sg_buf_map_to_hw_sgl(dev, dst,
qp_ctx->c_out_pool,
req->req_id,
&c_req->c_out_dma);
c_req->c_out = hisi_acc_sg_buf_map_to_hw_sgl(dev, c_req->dst,
qp_ctx->c_out_pool, req->req_id, &c_req->c_out_dma);
if (IS_ERR(c_req->c_out)) {
dev_err(dev, "fail to dma map output sgl buffers!\n");
hisi_acc_sg_buf_unmap(dev, src, c_req->c_in);
return PTR_ERR(c_req->c_out);
ret = PTR_ERR(c_req->c_out);
goto err_unmap_src;
}
}
return 0;
}
static int sec_skcipher_sgl_map(struct sec_ctx *ctx, struct sec_req *req)
{
struct sec_cipher_req *c_req = &req->c_req;
err_unmap_src:
hisi_acc_sg_buf_unmap(dev, c_req->src, c_req->c_in);
return sec_skcipher_map(SEC_CTX_DEV(ctx), req,
c_req->sk_req->src, c_req->sk_req->dst);
return ret;
}
static void sec_skcipher_sgl_unmap(struct sec_ctx *ctx, struct sec_req *req)
static int hisi_sec_skcipher_buf_unmap(struct hisi_sec_ctx *ctx,
struct hisi_sec_req *req)
{
struct device *dev = SEC_CTX_DEV(ctx);
struct sec_cipher_req *c_req = &req->c_req;
struct skcipher_request *sk_req = c_req->sk_req;
struct hisi_sec_cipher_req *c_req = &req->c_req;
struct device *dev = ctx->dev;
if (sk_req->dst != sk_req->src)
hisi_acc_sg_buf_unmap(dev, sk_req->src, c_req->c_in);
if (c_req->dst != c_req->src)
hisi_acc_sg_buf_unmap(dev, c_req->src, c_req->c_in);
hisi_acc_sg_buf_unmap(dev, sk_req->dst, c_req->c_out);
hisi_acc_sg_buf_unmap(dev, c_req->dst, c_req->c_out);
return 0;
}
static int sec_request_transfer(struct sec_ctx *ctx, struct sec_req *req)
static int hisi_sec_skcipher_copy_iv(struct hisi_sec_ctx *ctx,
struct hisi_sec_req *req)
{
int ret;
struct hisi_sec_cipher_ctx *c_ctx = &ctx->c_ctx;
struct hisi_sec_cipher_req *c_req = &req->c_req;
struct skcipher_request *sk_req =
(struct skcipher_request *)req->priv[0];
struct crypto_skcipher *atfm = crypto_skcipher_reqtfm(sk_req);
struct skcipher_request *sk_next;
int i, iv_size;
ret = ctx->req_op->buf_map(ctx, req);
if (ret)
return ret;
c_req->c_len = sk_req->cryptlen;
ctx->req_op->do_transfer(ctx, req);
iv_size = crypto_skcipher_ivsize(atfm);
if (iv_size > SEC_IV_SIZE)
return -EINVAL;
ret = ctx->req_op->bd_fill(ctx, req);
if (ret)
goto unmap_req_buf;
memcpy(c_req->c_ivin, sk_req->iv, iv_size);
return ret;
if (ctx->is_fusion) {
for (i = 1; i < req->fusion_num; i++) {
sk_next = (struct skcipher_request *)req->priv[i];
memcpy(c_req->c_ivin + i * iv_size, sk_next->iv,
iv_size);
}
unmap_req_buf:
ctx->req_op->buf_unmap(ctx, req);
c_req->gran_num = req->fusion_num;
c_ctx->c_gran_size = sk_req->cryptlen;
}
return ret;
return 0;
}
static void sec_request_untransfer(struct sec_ctx *ctx, struct sec_req *req)
static int hisi_sec_skcipher_bd_fill_storage(struct hisi_sec_ctx *ctx,
struct hisi_sec_req *req)
{
ctx->req_op->buf_unmap(ctx, req);
}
struct hisi_sec_cipher_ctx *c_ctx = &ctx->c_ctx;
struct hisi_sec_cipher_req *c_req = &req->c_req;
struct hisi_sec_sqe *sec_sqe = &req->sec_sqe;
#ifdef CONFIG_CRYPTO_DEV_HISI_SEC2_FUSION
static int sec_alloc_req_id_nolock(struct sec_req *req,
struct sec_qp_ctx *qp_ctx)
{
int req_id;
if (!c_req->c_len)
return -EINVAL;
req_id = idr_alloc_cyclic(&qp_ctx->req_idr, NULL, 0,
QM_Q_DEPTH, GFP_ATOMIC);
if (req_id < 0) {
pr_err("fail to alloc request id[%d]!\n", req_id);
return req_id;
}
sec_sqe->type1.c_key_addr_l = lower_32_bits(c_ctx->c_key_dma);
sec_sqe->type1.c_key_addr_h = upper_32_bits(c_ctx->c_key_dma);
sec_sqe->type1.c_ivin_addr_l = lower_32_bits(c_req->c_ivin_dma);
sec_sqe->type1.c_ivin_addr_h = upper_32_bits(c_req->c_ivin_dma);
sec_sqe->type1.data_src_addr_l = lower_32_bits(c_req->c_in_dma);
sec_sqe->type1.data_src_addr_h = upper_32_bits(c_req->c_in_dma);
sec_sqe->type1.data_dst_addr_l = lower_32_bits(c_req->c_out_dma);
sec_sqe->type1.data_dst_addr_h = upper_32_bits(c_req->c_out_dma);
sec_sqe->type1.c_mode = c_ctx->c_mode;
sec_sqe->type1.c_alg = c_ctx->c_alg;
sec_sqe->type1.c_key_len = c_ctx->c_key_len;
sec_sqe->src_addr_type = SGL;
sec_sqe->dst_addr_type = SGL;
sec_sqe->type = BD_TYPE1;
sec_sqe->scene = SCENE_STORAGE;
sec_sqe->de = c_req->c_in_dma != c_req->c_out_dma;
req->qp_ctx = qp_ctx;
qp_ctx->req_list[req_id] = req;
if (c_req->encrypt)
sec_sqe->cipher = SEC_CIPHER_ENC;
else
sec_sqe->cipher = SEC_CIPHER_DEC;
return req_id;
}
static void sec_fusion_req_cb(struct hisi_qp *qp, void *resp)
{
struct sec_qp_ctx *qp_ctx = qp->qp_ctx;
struct sec_sqe *bd = resp;
struct sec_req *req;
u8 done, flag, type;
type = bd->type_cipher_auth & SEC_TYPE_MASK;
if (type == SEC_BD_TYPE1) {
req = qp_ctx->req_list[bd->type1.tag];
req->err_type = bd->type1.error_type;
done = bd->type1.dn_icvflg_dif & SEC_DONE_MASK;
flag = (bd->type1.dn_icvflg_dif & SEC_FLAG_MASK) >>
SEC_FLAG_OFFSET;
if (req->err_type || done != 0x1 || flag != 0x2)
pr_err("err_type[%d] done[%d] flag[%d]\n",
req->err_type, done, flag);
} else {
pr_err("fusion bd type [%d] error!\n", type);
return;
}
req->ctx->req_op->buf_unmap(req->ctx, req);
req->ctx->req_op->callback(req->ctx, req);
if (c_ctx->c_mode == C_MODE_XTS)
sec_sqe->type1.ci_gen = CI_GEN_BY_LBA;
__sync_add_and_fetch(&req->ctx->sec->debug.dfx.recv_cnt, 1);
}
sec_sqe->type1.cipher_gran_size = c_ctx->c_gran_size;
sec_sqe->type1.gran_num = c_req->gran_num;
__sync_fetch_and_add(&ctx->sec->sec_dfx.gran_task_cnt, c_req->gran_num);
sec_sqe->type1.block_size = c_req->c_len;
static int sec_skcipher_get_fusion_res(struct sec_ctx *ctx,
struct sec_req *req)
{
struct sec_qp_ctx *qp_ctx = req->qp_ctx;
struct sec_cipher_res *c_res = qp_ctx->alg_meta_data;
struct sec_cipher_req *c_req = &req->c_req;
int req_id = req->req_id;
sec_sqe->type1.lba_l = lower_32_bits(c_req->lba);
sec_sqe->type1.lba_h = upper_32_bits(c_req->lba);
c_req->c_ivin = c_res[req_id].c_ivin;
c_req->c_ivin_dma = c_res[req_id].c_ivin_dma;
req->sk_reqs = c_res[req_id].sk_reqs;
c_req->src = c_res[req_id].src;
c_req->dst = c_res[req_id].dst;
sec_sqe->type1.tag = req->req_id;
return 0;
}
void sec_qp_ctx_work_process(struct sec_qp_ctx *qp_ctx)
static int hisi_sec_skcipher_bd_fill_multi_iv(struct hisi_sec_ctx *ctx,
struct hisi_sec_req *req)
{
ktime_t cur_time = ktime_get();
struct sec_req *req;
struct sec_ctx *ctx;
int ret;
mutex_lock(&qp_ctx->req_lock);
ret = hisi_sec_skcipher_bd_fill_storage(ctx, req);
if (ret)
return ret;
req = qp_ctx->fusion_req;
if (!req) {
mutex_unlock(&qp_ctx->req_lock);
return;
}
req->sec_sqe.type1.ci_gen = CI_GEN_BY_ADDR;
ctx = req->ctx;
if (!ctx || req->fusion_num == ctx->sec->fusion_limit) {
mutex_unlock(&qp_ctx->req_lock);
return;
}
return 0;
}
if (cur_time - qp_ctx->fusion_req->st_time < ctx->sec->fusion_time) {
mutex_unlock(&qp_ctx->req_lock);
return;
}
static int hisi_sec_skcipher_bd_fill_base(struct hisi_sec_ctx *ctx,
struct hisi_sec_req *req)
{
struct hisi_sec_cipher_ctx *c_ctx = &ctx->c_ctx;
struct hisi_sec_cipher_req *c_req = &req->c_req;
struct hisi_sec_sqe *sec_sqe = &req->sec_sqe;
qp_ctx->fusion_req = NULL;
if (!c_req->c_len)
return -EINVAL;
mutex_unlock(&qp_ctx->req_lock);
sec_sqe->type2.c_key_addr_l = lower_32_bits(c_ctx->c_key_dma);
sec_sqe->type2.c_key_addr_h = upper_32_bits(c_ctx->c_key_dma);
sec_sqe->type2.c_ivin_addr_l = lower_32_bits(c_req->c_ivin_dma);
sec_sqe->type2.c_ivin_addr_h = upper_32_bits(c_req->c_ivin_dma);
sec_sqe->type2.data_src_addr_l = lower_32_bits(c_req->c_in_dma);
sec_sqe->type2.data_src_addr_h = upper_32_bits(c_req->c_in_dma);
sec_sqe->type2.data_dst_addr_l = lower_32_bits(c_req->c_out_dma);
sec_sqe->type2.data_dst_addr_h = upper_32_bits(c_req->c_out_dma);
ret = sec_request_transfer(ctx, req);
if (ret)
goto err_free_req;
sec_sqe->type2.c_mode = c_ctx->c_mode;
sec_sqe->type2.c_alg = c_ctx->c_alg;
sec_sqe->type2.c_key_len = c_ctx->c_key_len;
ret = ctx->req_op->bd_send(ctx, req);
sec_sqe->src_addr_type = SGL;
sec_sqe->dst_addr_type = SGL;
sec_sqe->type = BD_TYPE2;
sec_sqe->scene = SCENE_IPSEC;
sec_sqe->de = c_req->c_in_dma != c_req->c_out_dma;
if (!ret || ret == -EBUSY || ret == -EINPROGRESS)
atomic_dec(&ctx->thread_cnt);
__sync_fetch_and_add(&ctx->sec->sec_dfx.gran_task_cnt, 1);
__sync_add_and_fetch(&ctx->sec->debug.dfx.send_by_tmout, 1);
if (ret != -EBUSY && ret != -EINPROGRESS) {
dev_err(SEC_CTX_DEV(ctx), "send sqe fail!\n");
goto err_unmap_req;
}
if (c_req->encrypt)
sec_sqe->cipher = SEC_CIPHER_ENC;
else
sec_sqe->cipher = SEC_CIPHER_DEC;
return;
sec_sqe->type2.c_len = c_req->c_len;
sec_sqe->type2.tag = req->req_id;
err_unmap_req:
ctx->req_op->buf_unmap(ctx, req);
err_free_req:
sec_free_req_id(req);
atomic_dec(&ctx->thread_cnt);
return 0;
}
void sec_ctx_work_process(struct work_struct *work)
static int hisi_sec_bd_send_asyn(struct hisi_sec_ctx *ctx,
struct hisi_sec_req *req)
{
struct sec_ctx *ctx;
int i;
struct hisi_sec_qp_ctx *qp_ctx = req->qp_ctx;
int req_cnt = req->req_cnt;
int ret;
mutex_lock(&qp_ctx->req_lock);
ret = hisi_qp_send(qp_ctx->qp, &req->sec_sqe);
__sync_add_and_fetch(&ctx->sec->sec_dfx.send_cnt, 1);
mutex_unlock(&qp_ctx->req_lock);
ctx = container_of(work, struct sec_ctx, work);
for (i = 0; i < ctx->sec->ctx_q_num; i++)
sec_qp_ctx_work_process(&ctx->qp_ctx[i]);
return hisi_sec_get_async_ret(ret, req_cnt, ctx->req_fake_limit);
}
static enum hrtimer_restart sec_hrtimer_handler(struct hrtimer *timer)
static void hisi_sec_skcipher_complete(struct hisi_sec_ctx *ctx,
struct hisi_sec_req *req, int err_code)
{
struct sec_ctx *ctx;
ktime_t tim;
ctx = container_of(timer, struct sec_ctx, timer);
tim = ktime_set(0, ctx->sec->fusion_time);
struct skcipher_request **sk_reqs =
(struct skcipher_request **)req->priv;
int i, req_fusion_num;
if (ctx->sec->wq)
queue_work(ctx->sec->wq, &ctx->work);
if (ctx->is_fusion == SEC_NO_FUSION)
req_fusion_num = 1;
else
schedule_work(&ctx->work);
req_fusion_num = req->fusion_num;
hrtimer_forward(timer, timer->base->get_time(), tim);
for (i = 0; i < req_fusion_num; i++)
sk_reqs[i]->base.complete(&sk_reqs[i]->base, err_code);
return HRTIMER_RESTART;
/* free sk_reqs if this request is completed */
if (err_code != -EINPROGRESS)
__sync_add_and_fetch(&ctx->sec->sec_dfx.put_task_cnt,
req_fusion_num);
else
__sync_add_and_fetch(&ctx->sec->sec_dfx.busy_comp_cnt,
req_fusion_num);
}
static int sec_ctx_fusion_init(struct sec_ctx *ctx, int qlen)
static int hisi_sec_skcipher_callback(struct hisi_sec_ctx *ctx,
struct hisi_sec_req *req)
{
int i;
if (!ctx || qlen < 0)
return -EINVAL;
for (i = 0; i < ctx->sec->ctx_q_num; i++) {
ctx->qp_ctx[i].fusion_num = 0;
ctx->qp_ctx[i].fusion_req = NULL;
struct hisi_sec_qp_ctx *qp_ctx = req->qp_ctx;
int req_id = req->req_id;
/* Replace the call back function set before */
ctx->qp_ctx[i].qp->req_cb = sec_fusion_req_cb;
}
if (__sync_bool_compare_and_swap(&req->fake_busy, 1, 0))
hisi_sec_skcipher_complete(ctx, req, -EINPROGRESS);
ctx->fake_req_limit = qlen >> 0x1;
atomic_set(&ctx->thread_cnt, 0);
hisi_sec_skcipher_complete(ctx, req, req->err_type);
if (ctx->sec->fusion_limit > 1 && ctx->sec->fusion_time > 0) {
ktime_t tim = ktime_set(0, ctx->sec->fusion_time);
hrtimer_init(&ctx->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
ctx->timer.function = sec_hrtimer_handler;
hrtimer_start(&ctx->timer, tim, HRTIMER_MODE_REL);
INIT_WORK(&ctx->work, sec_ctx_work_process);
}
hisi_sec_free_req_id(qp_ctx, req_id);
return 0;
}
static void sec_ctx_fusion_exit(struct crypto_skcipher *tfm)
static int sec_get_issue_id_range(atomic_t *qid, int start, int end)
{
struct sec_ctx *ctx = crypto_skcipher_ctx(tfm);
int issue_id;
int issue_len = end - start;
if (ctx->sec->fusion_limit > 1 && ctx->sec->fusion_time > 0)
hrtimer_cancel(&ctx->timer);
issue_id = (atomic_inc_return(qid) - start) % issue_len + start;
if (issue_id % issue_len == 0 && atomic_read(qid) > issue_len)
atomic_sub(issue_len, qid);
return issue_id;
}
static int sec_fusion_skcipher_bd_fill(struct sec_ctx *ctx,
struct sec_req *req)
static inline int sec_get_issue_id(struct hisi_sec_ctx *ctx,
struct hisi_sec_req *req)
{
struct sec_cipher_ctx *c_ctx = &ctx->c_ctx;
struct sec_cipher_req *c_req = &req->c_req;
struct sec_sqe *sec_sqe = &req->sec_sqe;
u8 de, scene, cipher, ci_gen;
if (!c_req->c_len)
return -EINVAL;
memset(sec_sqe, 0, sizeof(struct sec_sqe));
sec_sqe->type1.c_key_addr = cpu_to_le64(c_ctx->c_key_dma);
sec_sqe->type1.c_ivin_addr = cpu_to_le64(c_req->c_ivin_dma);
sec_sqe->type1.data_src_addr = cpu_to_le64(c_req->c_in_dma);
sec_sqe->type1.data_dst_addr = cpu_to_le64(c_req->c_out_dma);
int issue_id;
sec_sqe->type1.icvw_kmode |=
cpu_to_le16(((u16)c_ctx->c_mode) << SEC_CMODE_OFFSET);
sec_sqe->type1.c_alg = cpu_to_le16((u16)c_ctx->c_alg);
sec_sqe->type1.icvw_kmode |=
cpu_to_le16(((u16)c_ctx->c_key_len) << SEC_CKEY_OFFSET);
if (c_req->encrypt)
cipher = SEC_CIPHER_ENC << SEC_CIPHER_OFFSET;
if (req->c_req.encrypt == 1)
issue_id = sec_get_issue_id_range(&ctx->enc_qid, 0,
ctx->enc_q_num);
else
cipher = SEC_CIPHER_DEC << SEC_CIPHER_OFFSET;
sec_sqe->type_cipher_auth = SEC_BD_TYPE1 | cipher;
scene = SEC_SCENE_STORAGE << SEC_SCENE_OFFSET;
de = (c_req->c_in_dma != c_req->c_out_dma) << SEC_DE_OFFSET;
sec_sqe->sds_sa_type = (de | scene | (SEC_SGL << SEC_SRC_SGL_OFFSET));
sec_sqe->sdm_addr_type |= (SEC_SGL << SEC_DST_SGL_OFFSET);
ci_gen = SEC_CI_GEN_BY_ADDR << SEC_CI_GEN_OFFSET;
if (c_ctx->c_mode == SEC_CMODE_XTS && c_req->lba) {
ci_gen = SEC_CI_GEN_BY_LBA << SEC_CI_GEN_OFFSET;
sec_sqe->type1.lba = cpu_to_le64(c_req->lba);
}
sec_sqe->huk_key_ci = ci_gen;
issue_id = sec_get_issue_id_range(&ctx->dec_qid, ctx->enc_q_num,
ctx->q_num);
sec_sqe->type1.cipher_gran_size = cpu_to_le32(c_ctx->c_gran_size);
sec_sqe->type1.gran_num = cpu_to_le16((u16)c_req->gran_num);
sec_sqe->type1.block_size = cpu_to_le16((u16)c_req->c_len);
sec_sqe->type1.tag = cpu_to_le16((u16)req->req_id);
__sync_fetch_and_add(&ctx->sec->debug.dfx.gran_task_cnt,
c_req->gran_num);
return 0;
return issue_id;
}
static int sec_skcipher_fusion_resource_alloc(struct sec_ctx *ctx,
struct sec_qp_ctx *qp_ctx)
static inline void hisi_sec_inc_thread_cnt(struct hisi_sec_ctx *ctx)
{
int i, ret;
struct device *dev = SEC_CTX_DEV(ctx);
int req_num = ctx->sec->fusion_limit;
struct sec_cipher_res *res = qp_ctx->alg_meta_data;
int alloc_num = QM_Q_DEPTH * req_num;
res = kcalloc(QM_Q_DEPTH, sizeof(struct sec_cipher_res), GFP_KERNEL);
if (!res)
return -ENOMEM;
res->sk_reqs = kcalloc(alloc_num,
sizeof(struct skcipher_request *), GFP_KERNEL);
if (!res->sk_reqs) {
ret = -ENOMEM;
goto err_free_c_res;
}
res->c_ivin = dma_alloc_coherent(dev,
SEC_IV_SIZE * alloc_num, &res->c_ivin_dma, GFP_KERNEL);
if (!res->c_ivin) {
ret = -ENOMEM;
goto err_free_sk_reqs;
}
res->src = kcalloc(alloc_num, sizeof(struct scatterlist), GFP_KERNEL);
if (!res->src) {
ret = -ENOMEM;
goto err_free_c_ivin;
}
res->dst = kcalloc(alloc_num, sizeof(struct scatterlist), GFP_KERNEL);
if (!res->dst) {
ret = -ENOMEM;
goto err_free_src;
}
for (i = 1; i < QM_Q_DEPTH; i++) {
res[i].sk_reqs = res->sk_reqs + i * req_num;
res[i].c_ivin = res->c_ivin + i * req_num * SEC_IV_SIZE;
res[i].c_ivin_dma = res->c_ivin_dma + i * req_num *
SEC_IV_SIZE;
res[i].src = res->src + i * req_num;
res[i].dst = res->dst + i * req_num;
}
qp_ctx->alg_meta_data = res;
return 0;
int thread_cnt = atomic_inc_return(&ctx->thread_cnt);
err_free_src:
kfree(res->src);
err_free_c_ivin:
dma_free_coherent(dev, SEC_IV_SIZE * alloc_num, res->c_ivin,
res->c_ivin_dma);
err_free_sk_reqs:
kfree(res->sk_reqs);
err_free_c_res:
kfree(res);
return ret;
if (thread_cnt > ctx->sec->sec_dfx.thread_cnt)
ctx->sec->sec_dfx.thread_cnt = thread_cnt;
}
static void sec_skcipher_fusion_resource_free(struct sec_ctx *ctx,
struct sec_qp_ctx *qp_ctx)
static struct hisi_sec_req *sec_request_alloc(struct hisi_sec_ctx *ctx,
struct hisi_sec_req *in_req, int *fusion_send, int *fake_busy)
{
struct sec_cipher_res *res = qp_ctx->alg_meta_data;
int alloc_num = QM_Q_DEPTH * ctx->sec->fusion_limit;
struct device *dev = SEC_CTX_DEV(ctx);
if (!res)
return;
kfree(res->dst);
kfree(res->src);
dma_free_coherent(dev, SEC_IV_SIZE * alloc_num, res->c_ivin,
res->c_ivin_dma);
kfree(res->sk_reqs);
kfree(res);
}
struct hisi_sec_qp_ctx *qp_ctx;
struct hisi_sec_req *req;
int issue_id, ret;
static struct sec_req *sec_fusion_request_init(struct sec_ctx *ctx,
struct sec_req *in_req, int *fusion_send)
{
struct sec_qp_ctx *qp_ctx;
int issue_id, ret, thread_cnt;
struct sec_req *req;
__sync_add_and_fetch(&ctx->sec->sec_dfx.get_task_cnt, 1);
__sync_add_and_fetch(&ctx->sec->debug.dfx.get_task_cnt, 1);
issue_id = sec_get_issue_id(ctx, in_req);
hisi_sec_inc_thread_cnt(ctx);
issue_id = sec_get_queue_id(ctx, in_req);
thread_cnt = atomic_inc_return(&ctx->thread_cnt);
if (thread_cnt > ctx->sec->debug.dfx.thread_cnt)
ctx->sec->debug.dfx.thread_cnt = thread_cnt;
qp_ctx = &ctx->qp_ctx[issue_id];
in_req->fusion_num = 1;
mutex_lock(&qp_ctx->req_lock);
if (in_req->c_req.sk_req->src == in_req->c_req.sk_req->dst) {
*fusion_send = 1;
} else if (qp_ctx->fusion_req &&
qp_ctx->fusion_req->fusion_num < ctx->sec->fusion_limit) {
qp_ctx->fusion_req->fusion_num < qp_ctx->fusion_limit) {
req = qp_ctx->fusion_req;
__sync_add_and_fetch(&ctx->sec->debug.dfx.fake_busy_cnt, 1);
*fake_busy = req->fake_busy;
__sync_add_and_fetch(&ctx->sec->sec_dfx.fake_busy_cnt,
*fake_busy);
req->sk_reqs[req->fusion_num] = in_req->c_req.sk_req;
req->priv[req->fusion_num] = in_req->c_req.sk_req;
req->fusion_num++;
in_req->fusion_num = req->fusion_num;
if (req->fusion_num == ctx->sec->fusion_limit) {
if (req->fusion_num == qp_ctx->fusion_limit) {
*fusion_send = 1;
qp_ctx->fusion_req = NULL;
}
......@@ -902,27 +1271,29 @@ static struct sec_req *sec_fusion_request_init(struct sec_ctx *ctx,
}
req = in_req;
req->req_id = sec_alloc_req_id_nolock(req, qp_ctx);
if (req->req_id < 0) {
if (hisi_sec_alloc_req_id(req, qp_ctx)) {
mutex_unlock(&qp_ctx->req_lock);
return NULL;
}
if (ctx->fake_req_limit <= atomic_inc_return(&qp_ctx->pending_reqs)) {
req->fake_busy = 0;
req->req_cnt = atomic_inc_return(&qp_ctx->req_cnt);
if (req->req_cnt >= ctx->req_fake_limit) {
req->fake_busy = 1;
__sync_add_and_fetch(&ctx->sec->debug.dfx.fake_busy_cnt, 1);
} else {
req->fake_busy = 0;
*fake_busy = 1;
__sync_add_and_fetch(&ctx->sec->sec_dfx.fake_busy_cnt, 1);
}
ret = ctx->req_op->get_res(ctx, req);
if (ret) {
dev_err(SEC_CTX_DEV(ctx), "req_op get_res failed\n");
dev_err(ctx->dev, "req_op get_res failed\n");
mutex_unlock(&qp_ctx->req_lock);
goto err_free_req_id;
}
if (ctx->sec->fusion_limit <= 1 || !ctx->sec->fusion_time)
if (ctx->fusion_limit <= 1 || ctx->fusion_tmout_nsec == 0)
*fusion_send = 1;
if (ctx->is_fusion && *fusion_send == 0)
......@@ -930,9 +1301,7 @@ static struct sec_req *sec_fusion_request_init(struct sec_ctx *ctx,
req->fusion_num = 1;
/* Not storage scenario */
req->c_req.lba = 0;
req->sk_reqs[0] = in_req->c_req.sk_req;
req->priv[0] = in_req->c_req.sk_req;
req->st_time = ktime_get();
mutex_unlock(&qp_ctx->req_lock);
......@@ -940,434 +1309,103 @@ static struct sec_req *sec_fusion_request_init(struct sec_ctx *ctx,
return req;
err_free_req_id:
atomic_dec(&qp_ctx->pending_reqs);
sec_free_req_id(req);
sec_put_queue_id(ctx, req);
hisi_sec_free_req_id(qp_ctx, req->req_id);
return NULL;
}
static int sec_fusion_process(struct sec_ctx *ctx, struct sec_req *in_req)
{
struct device *dev = SEC_CTX_DEV(ctx);
struct sec_req *req;
int fusion_send = 0;
int ret;
req = sec_fusion_request_init(ctx, in_req, &fusion_send);
if (!req) {
dev_err(dev, "sec_request_alloc failed\n");
return -ENOMEM;
}
if (ctx->is_fusion && !fusion_send)
return req->fake_busy ? -EBUSY : -EINPROGRESS;
ret = sec_request_transfer(ctx, req);
if (ret) {
dev_err(dev, "sec_transfer failed! ret[%d]\n", ret);
goto err_with_req;
}
ret = ctx->req_op->bd_send(ctx, req);
if (!ret || ret == -EBUSY || ret == -EINPROGRESS)
atomic_dec(&ctx->thread_cnt);
__sync_add_and_fetch(&ctx->sec->debug.dfx.send_by_full, 1);
if (ret != -EBUSY && ret != -EINPROGRESS) {
dev_err(dev, "sec_send failed ret[%d]\n", ret);
goto err_send_req;
}
return ret;
err_send_req:
sec_request_untransfer(ctx, req);
err_with_req:
sec_free_req_id(req);
sec_put_queue_id(ctx, req);
atomic_dec(&ctx->thread_cnt);
return ret;
}
static void sec_fusion_skcipher_copy_iv(struct sec_ctx *ctx,
struct sec_req *req)
{
struct sec_cipher_ctx *c_ctx = &ctx->c_ctx;
struct skcipher_request *sk_req = req->c_req.sk_req;
struct sec_cipher_req *c_req = &req->c_req;
u32 ivsize = ctx->c_ctx.ivsize;
struct skcipher_request *sk_next;
int i;
c_req->c_len = sk_req->cryptlen;
memcpy(c_req->c_ivin, sk_req->iv, ivsize);
if (ctx->is_fusion) {
for (i = 1; i < req->fusion_num; i++) {
sk_next = req->sk_reqs[i];
memcpy(c_req->c_ivin + i * ivsize, sk_next->iv,
ivsize);
}
c_req->gran_num = req->fusion_num;
c_ctx->c_gran_size = sk_req->cryptlen;
}
}
static int sec_fusion_skcipher_sgl_map(struct sec_ctx *ctx, struct sec_req *req)
{
struct sec_cipher_req *c_req = &req->c_req;
struct device *dev = SEC_CTX_DEV(ctx);
struct skcipher_request *sk_next;
int src_nents = 0, dst_nents = 0, i;
int dst_nents_cp = 0;
int src_nents_cp = 0;
for (i = 0; i < req->fusion_num; i++) {
sk_next = req->sk_reqs[i];
if (!sk_next) {
dev_err(dev, "nullptr at [%d]\n", i);
return -EFAULT;
}
src_nents += sg_nents(sk_next->src);
dst_nents += sg_nents(sk_next->dst);
if (sk_next->src == sk_next->dst && !i) {
dev_err(dev, "err: src == dst\n");
return -EFAULT;
}
}
if (src_nents > SEC_FUSION_LIMIT || dst_nents > SEC_FUSION_LIMIT) {
dev_err(dev, "src[%d] or dst[%d] bigger than %d\n",
src_nents, dst_nents, SEC_FUSION_LIMIT);
return -ENOBUFS;
}
for (i = 0; i < req->fusion_num; i++) {
sk_next = req->sk_reqs[i];
src_nents = sg_nents(sk_next->src);
dst_nents = sg_nents(sk_next->dst);
if (i != req->fusion_num - 1) {
sg_unmark_end(&sk_next->src[src_nents - 1]);
sg_unmark_end(&sk_next->dst[dst_nents - 1]);
}
memcpy(c_req->src + src_nents_cp, sk_next->src,
src_nents * sizeof(struct scatterlist));
memcpy(c_req->dst + dst_nents_cp, sk_next->dst,
dst_nents * sizeof(struct scatterlist));
src_nents_cp += src_nents;
dst_nents_cp += dst_nents;
}
return sec_skcipher_map(dev, req, c_req->src, c_req->dst);
}
static void sec_fusion_skcipher_sgl_unmap(struct sec_ctx *ctx,
struct sec_req *req)
static int sec_request_transfer(struct hisi_sec_ctx *ctx,
struct hisi_sec_req *req)
{
struct sec_cipher_req *c_req = &req->c_req;
struct device *dev = SEC_CTX_DEV(ctx);
if (c_req->dst != c_req->src)
hisi_acc_sg_buf_unmap(dev, c_req->src, c_req->c_in);
hisi_acc_sg_buf_unmap(dev, c_req->dst, c_req->c_out);
}
static void sec_fusion_skcipher_complete(struct sec_ctx *ctx,
struct sec_req *req, int err_code)
{
struct skcipher_request **sk_reqs = req->sk_reqs;
int i, req_fusion_num;
req_fusion_num = req->fusion_num;
for (i = 0; i < req_fusion_num; i++)
sk_reqs[i]->base.complete(&sk_reqs[i]->base, err_code);
/* free sk_reqs if this request is completed */
if (err_code != -EINPROGRESS)
__sync_add_and_fetch(&ctx->sec->debug.dfx.put_task_cnt,
req_fusion_num);
else
__sync_add_and_fetch(&ctx->sec->debug.dfx.busy_comp_cnt,
req_fusion_num);
}
static void sec_fusion_skcipher_callback(struct sec_ctx *ctx,
struct sec_req *req)
{
struct sec_qp_ctx *qp_ctx = req->qp_ctx;
atomic_dec(&qp_ctx->pending_reqs);
sec_free_req_id(req);
if (__sync_bool_compare_and_swap(&req->fake_busy, 1, 0))
sec_fusion_skcipher_complete(ctx, req, -EINPROGRESS);
sec_fusion_skcipher_complete(ctx, req, req->err_type);
}
static struct sec_req_op sec_fusion_req_ops = {
.get_res = sec_skcipher_get_fusion_res,
.resource_alloc = sec_skcipher_fusion_resource_alloc,
.resource_free = sec_skcipher_fusion_resource_free,
.buf_map = sec_fusion_skcipher_sgl_map,
.buf_unmap = sec_fusion_skcipher_sgl_unmap,
.do_transfer = sec_fusion_skcipher_copy_iv,
.bd_fill = sec_fusion_skcipher_bd_fill,
.bd_send = sec_bd_send,
.callback = sec_fusion_skcipher_callback,
.process = sec_fusion_process,
};
static int sec_skcipher_fusion_ctx_init(struct crypto_skcipher *tfm)
{
struct sec_ctx *ctx = crypto_skcipher_ctx(tfm);
int ret;
ctx->req_op = &sec_fusion_req_ops;
ctx->is_fusion = SEC_IV_FUSION;
ret = sec_skcipher_init(tfm);
ret = ctx->req_op->buf_map(ctx, req);
if (ret)
return ret;
ret = sec_ctx_fusion_init(ctx, QM_Q_DEPTH);
if (ret) {
(void)sec_skcipher_exit(tfm);
return ret;
}
return ret;
}
static void sec_skcipher_fusion_ctx_exit(struct crypto_skcipher *tfm)
{
sec_ctx_fusion_exit(tfm);
sec_skcipher_exit(tfm);
}
#endif
static void sec_skcipher_copy_iv(struct sec_ctx *ctx, struct sec_req *req)
{
struct skcipher_request *sk_req = req->c_req.sk_req;
struct sec_cipher_req *c_req = &req->c_req;
c_req->c_len = sk_req->cryptlen;
memcpy(c_req->c_ivin, sk_req->iv, ctx->c_ctx.ivsize);
}
static int sec_skcipher_bd_fill(struct sec_ctx *ctx, struct sec_req *req)
{
struct sec_cipher_ctx *c_ctx = &ctx->c_ctx;
struct sec_cipher_req *c_req = &req->c_req;
struct sec_sqe *sec_sqe = &req->sec_sqe;
u8 de = 0;
u8 scene, sa_type, da_type;
u8 bd_type, cipher;
if (!c_req->c_len) {
dev_err(SEC_CTX_DEV(ctx), "cipher length is zero!\n");
return -EINVAL;
}
memset(sec_sqe, 0, sizeof(struct sec_sqe));
sec_sqe->type2.c_key_addr = cpu_to_le64(c_ctx->c_key_dma);
sec_sqe->type2.c_ivin_addr = cpu_to_le64(c_req->c_ivin_dma);
sec_sqe->type2.data_src_addr = cpu_to_le64(c_req->c_in_dma);
sec_sqe->type2.data_dst_addr = cpu_to_le64(c_req->c_out_dma);
sec_sqe->type2.icvw_kmode |= cpu_to_le16(((u16)c_ctx->c_mode) <<
SEC_CMODE_OFFSET);
sec_sqe->type2.c_alg = c_ctx->c_alg;
sec_sqe->type2.icvw_kmode |= cpu_to_le16(((u16)c_ctx->c_key_len) <<
SEC_CKEY_OFFSET);
bd_type = SEC_BD_TYPE2;
if (c_req->encrypt)
cipher = SEC_CIPHER_ENC << SEC_CIPHER_OFFSET;
else
cipher = SEC_CIPHER_DEC << SEC_CIPHER_OFFSET;
sec_sqe->type_cipher_auth = bd_type | cipher;
sa_type = SEC_SGL << SEC_SRC_SGL_OFFSET;
scene = SEC_COMM_SCENE << SEC_SCENE_OFFSET;
if (c_req->c_in_dma != c_req->c_out_dma)
de = 0x1 << SEC_DE_OFFSET;
sec_sqe->sds_sa_type = (de | scene | sa_type);
/* Just set DST address type */
da_type = SEC_SGL << SEC_DST_SGL_OFFSET;
sec_sqe->sdm_addr_type |= da_type;
ret = ctx->req_op->do_transfer(ctx, req);
if (ret)
goto unmap_req_buf;
sec_sqe->type2.clen_ivhlen |= cpu_to_le32(c_req->c_len);
sec_sqe->type2.tag = cpu_to_le16((u16)req->req_id);
memset(&req->sec_sqe, 0, sizeof(struct hisi_sec_sqe));
ret = ctx->req_op->bd_fill(ctx, req);
if (ret)
goto unmap_req_buf;
return 0;
}
static void sec_update_iv(struct sec_req *req)
{
struct skcipher_request *sk_req = req->c_req.sk_req;
u32 iv_size = req->ctx->c_ctx.ivsize;
struct scatterlist *sgl;
size_t sz;
if (req->c_req.encrypt)
sgl = sk_req->dst;
else
sgl = sk_req->src;
sz = sg_pcopy_to_buffer(sgl, sg_nents(sgl), sk_req->iv,
iv_size, sk_req->cryptlen - iv_size);
if (sz != iv_size)
dev_err(SEC_CTX_DEV(req->ctx), "copy output iv error!\n");
unmap_req_buf:
ctx->req_op->buf_unmap(ctx, req);
return ret;
}
static void sec_skcipher_callback(struct sec_ctx *ctx, struct sec_req *req)
static int sec_request_send(struct hisi_sec_ctx *ctx, struct hisi_sec_req *req)
{
struct skcipher_request *sk_req = req->c_req.sk_req;
struct sec_qp_ctx *qp_ctx = req->qp_ctx;
atomic_dec(&qp_ctx->pending_reqs);
sec_free_req_id(req);
int ret;
/* IV output at encrypto of CBC mode */
if (ctx->c_ctx.c_mode == SEC_CMODE_CBC && req->c_req.encrypt)
sec_update_iv(req);
ret = ctx->req_op->bd_send(ctx, req);
if (__sync_bool_compare_and_swap(&req->fake_busy, 1, 0))
sk_req->base.complete(&sk_req->base, -EINPROGRESS);
if (ret == 0 || ret == -EBUSY || ret == -EINPROGRESS)
atomic_dec(&ctx->thread_cnt);
sk_req->base.complete(&sk_req->base, req->err_type);
return ret;
}
static void sec_request_uninit(struct sec_ctx *ctx, struct sec_req *req)
static int sec_io_proc(struct hisi_sec_ctx *ctx, struct hisi_sec_req *in_req)
{
struct sec_qp_ctx *qp_ctx = req->qp_ctx;
atomic_dec(&qp_ctx->pending_reqs);
sec_free_req_id(req);
sec_put_queue_id(ctx, req);
}
struct hisi_sec_req *req;
int fusion_send = 0;
int fake_busy = 0;
int ret;
static int sec_request_init(struct sec_ctx *ctx, struct sec_req *req)
{
struct sec_qp_ctx *qp_ctx;
int issue_id, ret;
in_req->fusion_num = 1;
/* To load balance */
issue_id = sec_get_queue_id(ctx, req);
qp_ctx = &ctx->qp_ctx[issue_id];
req = sec_request_alloc(ctx, in_req, &fusion_send, &fake_busy);
req->req_id = sec_alloc_req_id(req, qp_ctx);
if (req->req_id < 0) {
sec_put_queue_id(ctx, req);
return req->req_id;
if (!req) {
dev_err(ctx->dev, "sec_request_alloc failed\n");
return -ENOMEM;
}
if (ctx->fake_req_limit <= atomic_inc_return(&qp_ctx->pending_reqs))
req->fake_busy = 1;
else
req->fake_busy = 0;
if (ctx->is_fusion && fusion_send == 0)
return fake_busy ? -EBUSY : -EINPROGRESS;
ret = ctx->req_op->get_res(ctx, req);
ret = sec_request_transfer(ctx, req);
if (ret) {
atomic_dec(&qp_ctx->pending_reqs);
sec_request_uninit(ctx, req);
dev_err(SEC_CTX_DEV(ctx), "get resources failed!\n");
dev_err(ctx->dev, "sec_transfer failed! ret[%d]\n", ret);
goto err_free_req;
}
return ret;
}
static int sec_process(struct sec_ctx *ctx, struct sec_req *req)
{
int ret;
ret = sec_request_init(ctx, req);
if (ret)
return ret;
ret = sec_request_transfer(ctx, req);
if (ret)
goto err_uninit_req;
/* Output IV as decrypto */
if (ctx->c_ctx.c_mode == SEC_CMODE_CBC && !req->c_req.encrypt)
sec_update_iv(req);
ret = ctx->req_op->bd_send(ctx, req);
ret = sec_request_send(ctx, req);
__sync_add_and_fetch(&ctx->sec->sec_dfx.send_by_full, 1);
if (ret != -EBUSY && ret != -EINPROGRESS) {
dev_err(SEC_CTX_DEV(ctx), "send sec request failed!\n");
goto err_send_req;
dev_err(ctx->dev, "sec_send failed ret[%d]\n", ret);
goto err_unmap_req;
}
return ret;
err_send_req:
/* As failing, restore the IV from user */
if (ctx->c_ctx.c_mode == SEC_CMODE_CBC && !req->c_req.encrypt)
memcpy(req->c_req.sk_req->iv, req->c_req.c_ivin,
ctx->c_ctx.ivsize);
sec_request_untransfer(ctx, req);
err_uninit_req:
sec_request_uninit(ctx, req);
err_unmap_req:
ctx->req_op->buf_unmap(ctx, req);
err_free_req:
hisi_sec_free_req_id(req->qp_ctx, req->req_id);
atomic_dec(&ctx->thread_cnt);
return ret;
}
static struct sec_req_op sec_req_ops_tbl = {
.get_res = sec_skcipher_get_res,
.resource_alloc = sec_skcipher_resource_alloc,
.resource_free = sec_skcipher_resource_free,
.buf_map = sec_skcipher_sgl_map,
.buf_unmap = sec_skcipher_sgl_unmap,
.do_transfer = sec_skcipher_copy_iv,
.bd_fill = sec_skcipher_bd_fill,
.bd_send = sec_bd_send,
.callback = sec_skcipher_callback,
.process = sec_process,
};
static int sec_skcipher_ctx_init(struct crypto_skcipher *tfm)
{
struct sec_ctx *ctx = crypto_skcipher_ctx(tfm);
ctx->req_op = &sec_req_ops_tbl;
return sec_skcipher_init(tfm);
}
static void sec_skcipher_ctx_exit(struct crypto_skcipher *tfm)
{
sec_skcipher_exit(tfm);
}
static int sec_skcipher_crypto(struct skcipher_request *sk_req, bool encrypt)
{
struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(sk_req);
struct sec_ctx *ctx = crypto_skcipher_ctx(tfm);
struct sec_req *req = skcipher_request_ctx(sk_req);
struct crypto_skcipher *atfm = crypto_skcipher_reqtfm(sk_req);
struct hisi_sec_ctx *ctx = crypto_skcipher_ctx(atfm);
struct hisi_sec_req *req = skcipher_request_ctx(sk_req);
if (!sk_req->src || !sk_req->dst || !sk_req->cryptlen) {
dev_err(SEC_CTX_DEV(ctx), "skcipher input param error!\n");
if (!sk_req->src || !sk_req->dst || !sk_req->cryptlen)
return -EINVAL;
}
req->c_req.sk_req = sk_req;
req->c_req.sk_req = sk_req;
req->c_req.encrypt = encrypt;
req->ctx = ctx;
req->ctx = ctx;
return ctx->req_op->process(ctx, req);
return sec_io_proc(ctx, req);
}
static int sec_skcipher_encrypt(struct skcipher_request *sk_req)
......@@ -1381,7 +1419,7 @@ static int sec_skcipher_decrypt(struct skcipher_request *sk_req)
}
#define SEC_SKCIPHER_GEN_ALG(sec_cra_name, sec_set_key, sec_min_key_size, \
sec_max_key_size, ctx_init, ctx_exit, blk_size, iv_size)\
sec_max_key_size, hisi_sec_cipher_ctx_init_func, blk_size, iv_size)\
{\
.base = {\
.cra_name = sec_cra_name,\
......@@ -1389,11 +1427,12 @@ static int sec_skcipher_decrypt(struct skcipher_request *sk_req)
.cra_priority = SEC_PRIORITY,\
.cra_flags = CRYPTO_ALG_ASYNC,\
.cra_blocksize = blk_size,\
.cra_ctxsize = sizeof(struct sec_ctx),\
.cra_ctxsize = sizeof(struct hisi_sec_ctx),\
.cra_alignmask = 0,\
.cra_module = THIS_MODULE,\
},\
.init = ctx_init,\
.exit = ctx_exit,\
.init = hisi_sec_cipher_ctx_init_func,\
.exit = hisi_sec_cipher_ctx_exit,\
.setkey = sec_set_key,\
.decrypt = sec_skcipher_decrypt,\
.encrypt = sec_skcipher_encrypt,\
......@@ -1402,74 +1441,67 @@ static int sec_skcipher_decrypt(struct skcipher_request *sk_req)
.ivsize = iv_size,\
},
#define SEC_SKCIPHER_ALG(name, key_func, min_key_size, \
#define SEC_SKCIPHER_NORMAL_ALG(name, key_func, min_key_size, \
max_key_size, blk_size, iv_size) \
SEC_SKCIPHER_GEN_ALG(name, key_func, min_key_size, max_key_size, \
sec_skcipher_ctx_init, sec_skcipher_ctx_exit, blk_size, iv_size)
hisi_sec_cipher_ctx_init_alg, blk_size, iv_size)
#define SEC_SKCIPHER_FUSION_ALG(name, key_func, min_key_size, \
max_key_size, blk_size, iv_size) \
SEC_SKCIPHER_GEN_ALG(name, key_func, min_key_size, max_key_size, \
sec_skcipher_fusion_ctx_init, sec_skcipher_fusion_ctx_exit, blk_size, \
iv_size)
static struct skcipher_alg sec_algs[] = {
SEC_SKCIPHER_ALG("ecb(aes)", sec_setkey_aes_ecb,
AES_MIN_KEY_SIZE, AES_MAX_KEY_SIZE,
AES_BLOCK_SIZE, 0)
SEC_SKCIPHER_ALG("cbc(aes)", sec_setkey_aes_cbc,
AES_MIN_KEY_SIZE, AES_MAX_KEY_SIZE,
AES_BLOCK_SIZE, AES_BLOCK_SIZE)
SEC_SKCIPHER_ALG("xts(aes)", sec_setkey_aes_xts,
SEC_XTS_MIN_KEY_SIZE, SEC_XTS_MAX_KEY_SIZE,
AES_BLOCK_SIZE, AES_BLOCK_SIZE)
SEC_SKCIPHER_ALG("ecb(des3_ede)", sec_setkey_3des_ecb,
SEC_DES3_2KEY_SIZE, SEC_DES3_3KEY_SIZE,
DES3_EDE_BLOCK_SIZE, 0)
SEC_SKCIPHER_ALG("cbc(des3_ede)", sec_setkey_3des_cbc,
SEC_DES3_2KEY_SIZE, SEC_DES3_3KEY_SIZE,
DES3_EDE_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE)
#ifndef CONFIG_CRYPTO_DEV_HISI_SEC2_FUSION
SEC_SKCIPHER_ALG("xts(sm4)", sec_setkey_sm4_xts,
SEC_XTS_MIN_KEY_SIZE, SEC_XTS_MIN_KEY_SIZE,
AES_BLOCK_SIZE, AES_BLOCK_SIZE)
SEC_SKCIPHER_ALG("cbc(sm4)", sec_setkey_sm4_cbc,
AES_MIN_KEY_SIZE, AES_MIN_KEY_SIZE,
AES_BLOCK_SIZE, AES_BLOCK_SIZE)
#else
SEC_SKCIPHER_FUSION_ALG("xts(sm4)", sec_setkey_sm4_xts,
SEC_XTS_MIN_KEY_SIZE, SEC_XTS_MIN_KEY_SIZE,
AES_BLOCK_SIZE, AES_BLOCK_SIZE)
hisi_sec_cipher_ctx_init_multi_iv, blk_size, iv_size)
static struct skcipher_alg sec_normal_algs[] = {
SEC_SKCIPHER_NORMAL_ALG("ecb(aes)", sec_setkey_aes_ecb,
AES_MIN_KEY_SIZE, AES_MAX_KEY_SIZE, AES_BLOCK_SIZE, 0)
SEC_SKCIPHER_NORMAL_ALG("cbc(aes)", sec_setkey_aes_cbc,
AES_MIN_KEY_SIZE, AES_MAX_KEY_SIZE, AES_BLOCK_SIZE,
AES_BLOCK_SIZE)
SEC_SKCIPHER_NORMAL_ALG("xts(aes)", sec_setkey_aes_xts,
SEC_XTS_MIN_KEY_SIZE, SEC_XTS_MAX_KEY_SIZE, AES_BLOCK_SIZE,
AES_BLOCK_SIZE)
SEC_SKCIPHER_NORMAL_ALG("ecb(des)", sec_setkey_des_ecb,
DES_KEY_SIZE, DES_KEY_SIZE, DES_BLOCK_SIZE, 0)
SEC_SKCIPHER_NORMAL_ALG("cbc(des)", sec_setkey_des_cbc,
DES_KEY_SIZE, DES_KEY_SIZE, DES_BLOCK_SIZE, DES_BLOCK_SIZE)
SEC_SKCIPHER_NORMAL_ALG("ecb(des3_ede)", sec_setkey_3des_ecb,
SEC_DES3_2KEY_SIZE, SEC_DES3_3KEY_SIZE, DES3_EDE_BLOCK_SIZE, 0)
SEC_SKCIPHER_NORMAL_ALG("cbc(des3_ede)", sec_setkey_3des_cbc,
SEC_DES3_2KEY_SIZE, SEC_DES3_3KEY_SIZE, DES3_EDE_BLOCK_SIZE,
DES3_EDE_BLOCK_SIZE)
SEC_SKCIPHER_NORMAL_ALG("xts(sm4)", sec_setkey_sm4_xts,
SEC_XTS_MIN_KEY_SIZE, SEC_XTS_MIN_KEY_SIZE, AES_BLOCK_SIZE,
AES_BLOCK_SIZE)
SEC_SKCIPHER_NORMAL_ALG("cbc(sm4)", sec_setkey_sm4_cbc,
AES_MIN_KEY_SIZE, AES_MIN_KEY_SIZE, AES_BLOCK_SIZE,
AES_BLOCK_SIZE)
};
static struct skcipher_alg sec_fusion_algs[] = {
SEC_SKCIPHER_FUSION_ALG("xts(sm4)", sec_setkey_sm4_xts,
SEC_XTS_MIN_KEY_SIZE, SEC_XTS_MIN_KEY_SIZE, AES_BLOCK_SIZE,
AES_BLOCK_SIZE)
SEC_SKCIPHER_FUSION_ALG("cbc(sm4)", sec_setkey_sm4_cbc,
AES_MIN_KEY_SIZE, AES_MIN_KEY_SIZE,
AES_BLOCK_SIZE, AES_BLOCK_SIZE)
#endif
AES_MIN_KEY_SIZE, AES_MIN_KEY_SIZE, AES_BLOCK_SIZE,
AES_BLOCK_SIZE)
};
int sec_register_to_crypto(void)
int hisi_sec_register_to_crypto(int fusion_limit)
{
int ret = 0;
/* To avoid repeat register */
mutex_lock(&sec_algs_lock);
if (++sec_active_devs == 1)
ret = crypto_register_skciphers(sec_algs, ARRAY_SIZE(sec_algs));
mutex_unlock(&sec_algs_lock);
return ret;
if (fusion_limit == 1)
return crypto_register_skciphers(sec_normal_algs,
ARRAY_SIZE(sec_normal_algs));
else
return crypto_register_skciphers(sec_fusion_algs,
ARRAY_SIZE(sec_fusion_algs));
}
void sec_unregister_from_crypto(void)
void hisi_sec_unregister_from_crypto(int fusion_limit)
{
mutex_lock(&sec_algs_lock);
if (--sec_active_devs == 0)
crypto_unregister_skciphers(sec_algs, ARRAY_SIZE(sec_algs));
mutex_unlock(&sec_algs_lock);
if (fusion_limit == 1)
crypto_unregister_skciphers(sec_normal_algs,
ARRAY_SIZE(sec_normal_algs));
else
crypto_unregister_skciphers(sec_fusion_algs,
ARRAY_SIZE(sec_fusion_algs));
}
drivers/crypto/hisilicon/sec2/sec_crypto.h
浏览文件 @ 457dd4e3
/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2018-2019 HiSilicon Limited. */
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (c) 2018-2019 HiSilicon Limited.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#ifndef HISI_SEC_CRYPTO_H
#define HISI_SEC_CRYPTO_H
#define SEC_IV_SIZE 24
#define SEC_MAX_KEY_SIZE 64
int hisi_sec_register_to_crypto(int fusion_limit);
void hisi_sec_unregister_from_crypto(int fusion_limit);
#ifndef __HISI_SEC_V2_CRYPTO_H
#define __HISI_SEC_V2_CRYPTO_H
#define SEC_IV_SIZE 24
#define SEC_MAX_KEY_SIZE 64
#define SEC_COMM_SCENE 0
#define SEC_DEF_FUSION 1
#define SEC_FUSION_LIMIT 64
#define SEC_DEF_FUSION_TIME_NS (400 * 1000)
enum sec_calg {
SEC_CALG_3DES = 0x1,
SEC_CALG_AES = 0x2,
SEC_CALG_SM4 = 0x3,
};
enum sec_cmode {
SEC_CMODE_ECB = 0x0,
SEC_CMODE_CBC = 0x1,
SEC_CMODE_CTR = 0x4,
SEC_CMODE_XTS = 0x7,
};
enum sec_ckey_type {
SEC_CKEY_128BIT = 0x0,
SEC_CKEY_192BIT = 0x1,
SEC_CKEY_256BIT = 0x2,
SEC_CKEY_3DES_3KEY = 0x1,
SEC_CKEY_3DES_2KEY = 0x3,
};
enum sec_bd_type {
SEC_BD_TYPE1 = 0x1,
SEC_BD_TYPE2 = 0x2,
};
enum sec_cipher_dir {
SEC_CIPHER_ENC = 0x1,
SEC_CIPHER_DEC = 0x2,
};
enum sec_addr_type {
SEC_PBUF = 0x0,
SEC_SGL = 0x1,
SEC_PRP = 0x2,
};
enum sec_ci_gen {
SEC_CI_GEN_BY_ADDR = 0x0,
SEC_CI_GEN_BY_LBA = 0X3,
};
enum sec_scene {
SEC_SCENE_IPSEC = 0x0,
SEC_SCENE_STORAGE = 0x5,
};
enum sec_work_mode {
SEC_NO_FUSION = 0x0,
SEC_IV_FUSION = 0x1,
SEC_FUSION_BUTT
};
enum sec_req_ops_type {
SEC_OPS_SKCIPHER_ALG = 0x0,
SEC_OPS_DMCRYPT = 0x1,
SEC_OPS_MULTI_IV = 0x2,
SEC_OPS_BUTT
};
struct sec_sqe_type2 {
/*
* mac_len: 0~5 bits
* a_key_len: 6~10 bits
* a_alg: 11~16 bits
*/
__le32 mac_key_alg;
/*
* c_icv_len: 0~5 bits
* c_width: 6~8 bits
* c_key_len: 9~11 bits
* c_mode: 12~15 bits
*/
__le16 icvw_kmode;
/* c_alg: 0~3 bits */
__u8 c_alg;
__u8 rsvd4;
/*
* a_len: 0~23 bits
* iv_offset_l: 24~31 bits
*/
__le32 alen_ivllen;
/*
* c_len: 0~23 bits
* iv_offset_h: 24~31 bits
*/
__le32 clen_ivhlen;
__le16 auth_src_offset;
__le16 cipher_src_offset;
__le16 cs_ip_header_offset;
__le16 cs_udp_header_offset;
__le16 pass_word_len;
__le16 dk_len;
__u8 salt3;
__u8 salt2;
__u8 salt1;
__u8 salt0;
__le16 tag;
__le16 rsvd5;
/*
* c_pad_type: 0~3 bits
* c_pad_len: 4~11 bits
* c_pad_data_type: 12~15 bits
*/
__le16 cph_pad;
/* c_pad_len_field: 0~1 bits */
__le16 c_pad_len_field;
__le64 long_a_data_len;
__le64 a_ivin_addr;
__le64 a_key_addr;
__le64 mac_addr;
__le64 c_ivin_addr;
__le64 c_key_addr;
__le64 data_src_addr;
__le64 data_dst_addr;
/*
* done: 0 bit
* icv: 1~3 bits
* csc: 4~6 bits
* flag: 7-10 bits
* dif_check: 11~13 bits
*/
__le16 done_flag;
__u8 error_type;
__u8 warning_type;
__u8 mac_i3;
__u8 mac_i2;
__u8 mac_i1;
__u8 mac_i0;
__le16 check_sum_i;
__u8 tls_pad_len_i;
__u8 rsvd12;
__le32 counter;
};
#ifdef CONFIG_CRYPTO_DEV_HISI_SEC2_FUSION
struct sec_sqe_type1 {
/*
* mac_len: 0~5 bits
* a_key_len: 6~10 bits
* a_alg: 11~16 bits
*/
__le32 mac_key_alg;
/*
* c_icv_len: 0~5 bits
* c_width: 6~8 bits
* c_key_len: 9~11 bits
* c_mode: 12~15 bits
*/
__le16 icvw_kmode;
/* cipher alg: 0~3 */
__le16 c_alg;
/* auth gran size: 0~23 */
__le32 auth_gran_size;
/* cipher gran size: 0~23 */
__le32 cipher_gran_size;
__le16 auth_src_offset;
__le16 cipher_src_offset;
__le16 gran_num;
__le16 rsvd0;
/* src buffer skip data len: 0~23 */
__le32 src_skip_data_len;
/* dst buffer skip data len: 0~23 */
__le32 dst_skip_data_len;
__le16 tag;
__le16 rsvd1;
/*
* gen_page_pad_ctrl: 0~3 bits
* gen_grd_ctrl: 4~7 bits
* gen_ver_ctrl: 8~11 bits
* gen_app_ctrl: 12~15 bits
* gen_ver_val: 16~23 bits
* gen_app_val: 24~31 bits
*/
__le32 gen_pgvava_area;
__le32 private_info;
/*
* gen_ref_ctrl: 0~3 bits
* page_pad_type: 4~5 bits
*/
__u8 grctrl_pptype;
/*
* chk_grd_ctrl: 0~3 bits
* chk_ref_ctrl: 4~7 bits
*/
__u8 cgrd_cref_ctrl;
__le16 block_size;
__le64 lba;
__le64 a_key_addr;
__le64 mac_addr;
__le64 c_ivin_addr;
__le64 c_key_addr;
__le64 data_src_addr;
__le64 data_dst_addr;
/*
* done: 0 bit
* icv: 1~3 bits
* flag: 7~10 bits
* dif_check: 11~13 bits
*/
__le16 dn_icvflg_dif;
__u8 error_type;
__u8 warning_type;
__le32 dw29;
__le32 dw30;
__le32 dw31;
};
#endif
struct sec_sqe {
/*
* type: 0~3 bits
* cipher: 4~5 bits
* auth: 6~7 bit s
*/
__u8 type_cipher_auth;
/*
* seq: 0 bit
* de: 1~2 bits
* scene: 3~6 bits
* src_addr_type: ~7 bit, with sdm_addr_type 0-1 bits
*/
__u8 sds_sa_type;
/*
* src_addr_type: 0~1 bits, not used now,
* if support PRP, set this field, or set zero.
* dst_addr_type: 2~4 bits
* mac_addr_type: 5~7 bits
*/
__u8 sdm_addr_type;
__u8 rsvd0;
/*
* nonce_len(type2): 0~3 bits
* huk(type2): 4 bit
* key_s(type2): 5 bit
* ci_gen: 6~7 bits
*/
__u8 huk_key_ci;
/*
* ai_gen: 0~1 bits
* a_pad(type2): 2~3 bits
* c_s(type2): 4~5 bits
*/
__u8 ai_apd_cs;
/*
* rhf(type2): 0 bit
* c_key_type: 1~2 bits
* a_key_type: 3~4 bits
* write_frame_len(type2): 5~7 bits
*/
__u8 rca_key_frm;
/*
* cal_iv_addr_en(type2): 0 bit
* tls_up(type2): 1 bit
* inveld: 7 bit
*/
__u8 iv_tls_ld;
union {
#ifdef CONFIG_CRYPTO_DEV_HISI_SEC2_FUSION
struct sec_sqe_type1 type1;
#endif
struct sec_sqe_type2 type2;
};
};
int sec_register_to_crypto(void);
void sec_unregister_from_crypto(void);
#endif
drivers/crypto/hisilicon/sec2/sec_main.c
浏览文件 @ 457dd4e3
// SPDX-License-Identifier: GPL-2.0
/* Copyright (c) 2018-2019 HiSilicon Limited. */
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2018-2019 HiSilicon Limited.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#include <linux/acpi.h>
#include <linux/aer.h>
......@@ -12,44 +20,56 @@
#include <linux/pci.h>
#include <linux/seq_file.h>
#include <linux/topology.h>
#include <linux/uacce.h>
#include "sec.h"
#include "sec_crypto.h"
#define SEC_VF_NUM 63
#define SEC_QUEUE_NUM_V1 4096
#define SEC_QUEUE_NUM_V2 1024
#define SEC_PF_PCI_DEVICE_ID 0xa255
#define SEC_VF_PCI_DEVICE_ID 0xa256
#define SEC_PCI_DEVICE_ID_PF 0xa255
#define SEC_PCI_DEVICE_ID_VF 0xa256
#define SEC_COMMON_REG_OFF 0x1000
#define SEC_MASTER_GLOBAL_CTRL 0x300000
#define SEC_MASTER_GLOBAL_CTRL_SHUTDOWN 0x1
#define SEC_MASTER_TRANS_RETURN 0x300150
#define SEC_MASTER_TRANS_RETURN_RW 0x3
#define SEC_CORE_INT_SOURCE 0x301010
#define SEC_CORE_INT_MASK 0x301000
#define SEC_CORE_INT_STATUS 0x301008
#define SEC_CORE_INT_STATUS_M_ECC BIT(2)
#define SEC_CORE_ECC_INFO 0x301C14
#define SEC_ECC_NUM_SHIFT 16
#define SEC_ECC_ADDR_SHIFT 0
#define SEC_ECC_NUM(err_val) ((err_val >> SEC_ECC_NUM_SHIFT) & 0xFF)
#define SEC_ECC_ADDR(err_val) (err_val >> SEC_ECC_ADDR_SHIFT)
#define SEC_CORE_INT_DISABLE 0x0
#define SEC_CORE_INT_ENABLE 0x1ff
#define SEC_HW_ERROR_IRQ_ENABLE 1
#define SEC_HW_ERROR_IRQ_DISABLE 0
#define SEC_SM4_CTR_ENABLE_REG 0x301380
#define SEC_SM4_CTR_ENABLE_MSK 0xEFFFFFFF
#define SEC_SM4_CTR_DISABLE_MSK 0xFFFFFFFF
#define SEC_XTS_MIV_ENABLE_REG 0x301384
#define SEC_XTS_MIV_ENABLE_MSK 0x7FFFFFFF
#define SEC_XTS_MIV_DISABLE_MSK 0xFFFFFFFF
#define SEC_BD_ERR_CHK_EN1 0xfffff7fd
#define SEC_BD_ERR_CHK_EN2 0xffffbfff
#define SEC_SQE_SIZE 128
#define SEC_SQ_SIZE (SEC_SQE_SIZE * QM_Q_DEPTH)
#define SEC_PF_DEF_Q_NUM 64
#define SEC_PF_DEF_Q_BASE 0
#define SEC_CTX_Q_NUM_DEF 24
#define SEC_MASTER_GLOBAL_CTRL 0x300000
#define SEC_MASTER_GLOBAL_CTRL_SHTDWN 0x1
#define SEC_MASTER_TRANS_RETURN 0x300150
#define SEC_MASTER_TRANS_RETURN_RW 0x3
#define SEC_CTRL_CNT_CLR_CE 0x301120
#define SEC_CTRL_CNT_CLR_CE_BIT BIT(0)
#define SEC_ENGINE_PF_CFG_OFF 0x300000
#define SEC_ACC_COMMON_REG_OFF 0x1000
#define SEC_CORE_INT_SOURCE 0x301010
#define SEC_CORE_INT_MASK 0x301000
#define SEC_CORE_INT_STATUS 0x301008
#define SEC_CORE_SRAM_ECC_ERR_INFO 0x301C14
#define SEC_ECC_NUM(err) (((err) >> 16) & 0xFF)
#define SEC_ECC_ADDR(err) ((err) >> 0)
#define SEC_CORE_INT_DISABLE 0x0
#define SEC_CORE_INT_ENABLE 0x1ff
#define SEC_RAS_CE_REG 0x50
#define SEC_RAS_FE_REG 0x54
......@@ -58,49 +78,121 @@
#define SEC_RAS_FE_ENB_MSK 0x0
#define SEC_RAS_NFE_ENB_MSK 0x177
#define SEC_RAS_DISABLE 0x0
#define SEC_MEM_START_INIT_REG 0x0100
#define SEC_MEM_INIT_DONE_REG 0x0104
#define SEC_CONTROL_REG 0x0200
#define SEC_TRNG_EN_SHIFT 8
#define SEC_CLK_GATE_ENABLE BIT(3)
#define SEC_CLK_GATE_DISABLE (~BIT(3))
#define SEC_AXI_SHUTDOWN_ENABLE BIT(12)
#define SEC_AXI_SHUTDOWN_ENABLE BIT(12)
#define SEC_AXI_SHUTDOWN_DISABLE 0xFFFFEFFF
#define SEC_INTERFACE_USER_CTRL0_REG 0x0220
#define SEC_INTERFACE_USER_CTRL1_REG 0x0224
#define SEC_BD_ERR_CHK_EN_REG1 0x0384
#define SEC_BD_ERR_CHK_EN_REG2 0x038c
#define SEC_BD_ERR_CHK_EN_REG(n) (0x0380 + (n) * 0x04)
#define SEC_USER0_SMMU_NORMAL (BIT(23) | BIT(15))
#define SEC_USER1_SMMU_NORMAL (BIT(31) | BIT(23) | BIT(15) | BIT(7))
#define SEC_CORE_INT_STATUS_M_ECC BIT(2)
#define SEC_DELAY_10_US 10
#define SEC_POLL_TIMEOUT_US 1000
#define SEC_VF_CNT_MASK 0xffffffc0
#define SEC_WAIT_DELAY 1000
#define SEC_DBGFS_VAL_MAX_LEN 20
#define SEC_RESET 0
#define SEC_WAIT_DELAY 1000
#define SEC_CHAIN_ABN_LEN 128UL
#define SEC_ENABLE 1
#define SEC_DISABLE 0
#define SEC_RESET_WAIT_TIMEOUT 400
#define SEC_PCI_COMMAND_INVALID 0xFFFFFFFF
#define SEC_ADDR(qm, offset) ((qm)->io_base + (offset) + \
SEC_ENGINE_PF_CFG_OFF + SEC_ACC_COMMON_REG_OFF)
struct sec_hw_error {
#define FORMAT_DECIMAL 10
static const char hisi_sec_name[] = "hisi_sec";
static struct dentry *sec_debugfs_root;
static u32 pf_q_num = SEC_PF_DEF_Q_NUM;
static struct workqueue_struct *sec_wq;
LIST_HEAD(hisi_sec_list);
DEFINE_MUTEX(hisi_sec_list_lock);
struct hisi_sec_resource {
struct hisi_sec *sec;
int distance;
struct list_head list;
};
static void free_list(struct list_head *head)
{
struct hisi_sec_resource *res, *tmp;
list_for_each_entry_safe(res, tmp, head, list) {
list_del(&res->list);
kfree(res);
}
}
struct hisi_sec *find_sec_device(int node)
{
struct hisi_sec *ret = NULL;
#ifdef CONFIG_NUMA
struct hisi_sec_resource *res, *tmp;
struct hisi_sec *hisi_sec;
struct list_head *n;
struct device *dev;
LIST_HEAD(head);
mutex_lock(&hisi_sec_list_lock);
list_for_each_entry(hisi_sec, &hisi_sec_list, list) {
res = kzalloc(sizeof(*res), GFP_KERNEL);
if (!res)
goto err;
dev = &hisi_sec->qm.pdev->dev;
res->sec = hisi_sec;
res->distance = node_distance(dev->numa_node, node);
n = &head;
list_for_each_entry(tmp, &head, list) {
if (res->distance < tmp->distance) {
n = &tmp->list;
break;
}
}
list_add_tail(&res->list, n);
}
list_for_each_entry(tmp, &head, list) {
if (tmp->sec->q_ref + tmp->sec->ctx_q_num <= pf_q_num) {
tmp->sec->q_ref += tmp->sec->ctx_q_num;
ret = tmp->sec;
break;
}
}
free_list(&head);
#else
mutex_lock(&hisi_sec_list_lock);
ret = list_first_entry(&hisi_sec_list, struct hisi_sec, list);
#endif
mutex_unlock(&hisi_sec_list_lock);
return ret;
err:
free_list(&head);
mutex_unlock(&hisi_sec_list_lock);
return NULL;
}
struct hisi_sec_hw_error {
u32 int_msk;
const char *msg;
};
static const char sec_name[] = "hisi_sec2";
static struct dentry *sec_debugfs_root;
static LIST_HEAD(sec_list);
static DEFINE_MUTEX(sec_list_lock);
static const struct sec_hw_error sec_hw_errors[] = {
static const struct hisi_sec_hw_error sec_hw_error[] = {
{.int_msk = BIT(0), .msg = "sec_axi_rresp_err_rint"},
{.int_msk = BIT(1), .msg = "sec_axi_bresp_err_rint"},
{.int_msk = BIT(2), .msg = "sec_ecc_2bit_err_rint"},
......@@ -113,44 +205,38 @@ static const struct sec_hw_error sec_hw_errors[] = {
{ /* sentinel */ }
};
struct sec_dev *sec_find_device(int node)
{
#define SEC_NUMA_MAX_DISTANCE 100
int min_distance = SEC_NUMA_MAX_DISTANCE;
int dev_node = 0, free_qp_num = 0;
struct sec_dev *sec, *ret = NULL;
struct hisi_qm *qm;
struct device *dev;
mutex_lock(&sec_list_lock);
list_for_each_entry(sec, &sec_list, list) {
qm = &sec->qm;
dev = &qm->pdev->dev;
#ifdef CONFIG_NUMA
dev_node = dev->numa_node;
if (dev_node < 0)
dev_node = 0;
#endif
if (node_distance(dev_node, node) < min_distance) {
free_qp_num = hisi_qm_get_free_qp_num(qm);
if (free_qp_num >= sec->ctx_q_num) {
ret = sec;
min_distance = node_distance(dev_node, node);
}
}
}
mutex_unlock(&sec_list_lock);
return ret;
}
enum ctrl_debug_file_index {
SEC_CURRENT_QM,
SEC_CLEAR_ENABLE,
SEC_DEBUG_FILE_NUM,
};
static const char * const sec_dbg_file_name[] = {
static const char * const ctrl_debug_file_name[] = {
[SEC_CURRENT_QM] = "current_qm",
[SEC_CLEAR_ENABLE] = "clear_enable",
};
struct ctrl_debug_file {
enum ctrl_debug_file_index index;
spinlock_t lock;
struct hisi_sec_ctrl *ctrl;
};
/*
* One SEC controller has one PF and multiple VFs, some global configurations
* which PF has need this structure.
*
* Just relevant for PF.
*/
struct hisi_sec_ctrl {
u32 num_vfs;
struct hisi_sec *hisi_sec;
struct dentry *debug_root;
struct ctrl_debug_file files[SEC_DEBUG_FILE_NUM];
};
static struct debugfs_reg32 sec_dfx_regs[] = {
{"SEC_PF_ABNORMAL_INT_SOURCE ", 0x301010},
{"SEC_PF_ABNORMAL_INT_SOURCE ", 0x301010},
{"SEC_SAA_EN ", 0x301270},
{"SEC_BD_LATENCY_MIN ", 0x301600},
{"SEC_BD_LATENCY_MAX ", 0x301608},
......@@ -173,9 +259,10 @@ static struct debugfs_reg32 sec_dfx_regs[] = {
{"SEC_BD_SAA8 ", 0x301C40},
};
static int sec_pf_q_num_set(const char *val, const struct kernel_param *kp)
static int pf_q_num_set(const char *val, const struct kernel_param *kp)
{
struct pci_dev *pdev;
struct pci_dev *pdev = pci_get_device(PCI_VENDOR_ID_HUAWEI,
SEC_PCI_DEVICE_ID_PF, NULL);
u32 n, q_num;
u8 rev_id;
int ret;
......@@ -183,14 +270,13 @@ static int sec_pf_q_num_set(const char *val, const struct kernel_param *kp)
if (!val)
return -EINVAL;
pdev = pci_get_device(PCI_VENDOR_ID_HUAWEI,
SEC_PF_PCI_DEVICE_ID, NULL);
if (!pdev) {
if (unlikely(!pdev)) {
q_num = min_t(u32, SEC_QUEUE_NUM_V1, SEC_QUEUE_NUM_V2);
pr_info("No device, suppose queue number is %d!\n", q_num);
pr_info
("No device found currently, suppose queue number is %d\n",
q_num);
} else {
rev_id = pdev->revision;
switch (rev_id) {
case QM_HW_V1:
q_num = SEC_QUEUE_NUM_V1;
......@@ -204,78 +290,63 @@ static int sec_pf_q_num_set(const char *val, const struct kernel_param *kp)
}
ret = kstrtou32(val, 10, &n);
if (ret || n > q_num)
if (ret != 0 || n > q_num)
return -EINVAL;
return param_set_int(val, kp);
}
static const struct kernel_param_ops sec_pf_q_num_ops = {
.set = sec_pf_q_num_set,
static const struct kernel_param_ops pf_q_num_ops = {
.set = pf_q_num_set,
.get = param_get_int,
};
static u32 pf_q_num = SEC_PF_DEF_Q_NUM;
module_param_cb(pf_q_num, &sec_pf_q_num_ops, &pf_q_num, 0444);
MODULE_PARM_DESC(pf_q_num, "Number of queues in PF(v1 0-4096, v2 0-1024)");
static int sec_ctx_q_num_set(const char *val, const struct kernel_param *kp)
static int uacce_mode_set(const char *val, const struct kernel_param *kp)
{
u32 ctx_q_num;
u32 n;
int ret;
if (!val)
return -EINVAL;
ret = kstrtou32(val, 10, &ctx_q_num);
if (ret)
return -EINVAL;
if (!ctx_q_num || ctx_q_num > QM_Q_DEPTH || ctx_q_num & 0x1) {
pr_err("ctx queue num[%u] is invalid!\n", ctx_q_num);
ret = kstrtou32(val, FORMAT_DECIMAL, &n);
if (ret != 0 || n > UACCE_MODE_NOIOMMU)
return -EINVAL;
}
return param_set_int(val, kp);
}
static const struct kernel_param_ops sec_ctx_q_num_ops = {
.set = sec_ctx_q_num_set,
static const struct kernel_param_ops uacce_mode_ops = {
.set = uacce_mode_set,
.get = param_get_int,
};
static u32 ctx_q_num = SEC_CTX_Q_NUM_DEF;
module_param_cb(ctx_q_num, &sec_ctx_q_num_ops, &ctx_q_num, 0444);
MODULE_PARM_DESC(ctx_q_num, "Number of queue in ctx (2, 4, 6, ..., 1024)");
#ifdef CONFIG_CRYPTO_QM_UACCE
static int sec_uacce_mode_set(const char *val, const struct kernel_param *kp)
static int ctx_q_num_set(const char *val, const struct kernel_param *kp)
{
u32 n;
u32 ctx_q_num;
int ret;
if (!val)
return -EINVAL;
ret = kstrtou32(val, 10, &n);
if (ret != 0 || n > UACCE_MODE_NOIOMMU)
ret = kstrtou32(val, FORMAT_DECIMAL, &ctx_q_num);
if (ret)
return -EINVAL;
if (ctx_q_num == 0 || ctx_q_num > QM_Q_DEPTH || ctx_q_num % 2 == 1) {
pr_err("ctx_q_num[%u] is invalid\n", ctx_q_num);
return -EINVAL;
}
return param_set_int(val, kp);
}
static const struct kernel_param_ops sec_uacce_mode_ops = {
.set = sec_uacce_mode_set,
static const struct kernel_param_ops ctx_q_num_ops = {
.set = ctx_q_num_set,
.get = param_get_int,
};
static u32 uacce_mode = UACCE_MODE_NOUACCE;
module_param_cb(uacce_mode, &sec_uacce_mode_ops, &uacce_mode, 0444);
MODULE_PARM_DESC(uacce_mode, "Mode of UACCE can be 0(default), 1, 2");
#endif
#ifdef CONFIG_CRYPTO_DEV_HISI_SEC2_FUSION
static struct workqueue_struct *sec_wq;
static int sec_fusion_limit_set(const char *val, const struct kernel_param *kp)
static int fusion_limit_set(const char *val, const struct kernel_param *kp)
{
u32 fusion_limit;
int ret;
......@@ -283,30 +354,25 @@ static int sec_fusion_limit_set(const char *val, const struct kernel_param *kp)
if (!val)
return -EINVAL;
ret = kstrtou32(val, 10, &fusion_limit);
ret = kstrtou32(val, FORMAT_DECIMAL, &fusion_limit);
if (ret)
return ret;
if (!fusion_limit || fusion_limit > SEC_FUSION_LIMIT) {
if (fusion_limit == 0 || fusion_limit > FUSION_LIMIT_MAX) {
pr_err("fusion_limit[%u] is't at range(0, %d)", fusion_limit,
SEC_FUSION_LIMIT);
FUSION_LIMIT_MAX);
return -EINVAL;
}
return param_set_int(val, kp);
}
static const struct kernel_param_ops sec_fusion_limit_ops = {
.set = sec_fusion_limit_set,
static const struct kernel_param_ops fusion_limit_ops = {
.set = fusion_limit_set,
.get = param_get_int,
};
static u32 fusion_limit = SEC_DEF_FUSION;
module_param_cb(fusion_limit, &sec_fusion_limit_ops, &fusion_limit, 0444);
MODULE_PARM_DESC(fusion_limit, "(1, acc_sgl_sge_nr of hisilicon QM)");
static int sec_fusion_tmout_ns_set(const char *val,
const struct kernel_param *kp)
static int fusion_tmout_nsec_set(const char *val, const struct kernel_param *kp)
{
u32 fusion_tmout_nsec;
int ret;
......@@ -314,7 +380,7 @@ static int sec_fusion_tmout_ns_set(const char *val,
if (!val)
return -EINVAL;
ret = kstrtou32(val, 10, &fusion_tmout_nsec);
ret = kstrtou32(val, FORMAT_DECIMAL, &fusion_tmout_nsec);
if (ret)
return ret;
......@@ -326,124 +392,151 @@ static int sec_fusion_tmout_ns_set(const char *val,
return param_set_int(val, kp);
}
static const struct kernel_param_ops sec_fusion_time_ops = {
.set = sec_fusion_tmout_ns_set,
static const struct kernel_param_ops fusion_tmout_nsec_ops = {
.set = fusion_tmout_nsec_set,
.get = param_get_int,
};
static u32 fusion_time = SEC_DEF_FUSION_TIME_NS;/* ns */
module_param_cb(fusion_time, &sec_fusion_time_ops, &fusion_time, 0444);
MODULE_PARM_DESC(fusion_time, "(0, NSEC_PER_SEC)");
#endif
static const struct pci_device_id sec_dev_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, SEC_PF_PCI_DEVICE_ID) },
{ PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, SEC_VF_PCI_DEVICE_ID) },
module_param_cb(pf_q_num, &pf_q_num_ops, &pf_q_num, 0444);
MODULE_PARM_DESC(pf_q_num, "Number of queues in PF(v1 0-4096, v2 0-1024)");
static int uacce_mode = UACCE_MODE_NOUACCE;
module_param_cb(uacce_mode, &uacce_mode_ops, &uacce_mode, 0444);
MODULE_PARM_DESC(uacce_mode, "Mode of UACCE can be 0(default), 1, 2");
static int enable_sm4_ctr;
module_param(enable_sm4_ctr, int, 0444);
MODULE_PARM_DESC(enable_sm4_ctr, "Enable ctr(sm4) algorithm 0(default), 1");
static int ctx_q_num = CTX_Q_NUM_DEF;
module_param_cb(ctx_q_num, &ctx_q_num_ops, &ctx_q_num, 0444);
MODULE_PARM_DESC(ctx_q_num, "Number of queue in ctx (2, 4, 6, ..., 1024)");
static int fusion_limit = FUSION_LIMIT_DEF;
module_param_cb(fusion_limit, &fusion_limit_ops, &fusion_limit, 0444);
MODULE_PARM_DESC(fusion_limit, "(1, acc_sgl_sge_nr)");
static int fusion_tmout_nsec = FUSION_TMOUT_NSEC_DEF;
module_param_cb(fusion_tmout_nsec, &fusion_tmout_nsec_ops, &fusion_tmout_nsec,
0444);
MODULE_PARM_DESC(fusion_tmout_nsec, "(0, NSEC_PER_SEC)");
static const struct pci_device_id hisi_sec_dev_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, SEC_PCI_DEVICE_ID_PF) },
{ PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, SEC_PCI_DEVICE_ID_VF) },
{ 0, }
};
MODULE_DEVICE_TABLE(pci, sec_dev_ids);
MODULE_DEVICE_TABLE(pci, hisi_sec_dev_ids);
static inline void sec_add_to_list(struct sec_dev *sec)
static inline void hisi_sec_add_to_list(struct hisi_sec *hisi_sec)
{
mutex_lock(&sec_list_lock);
list_add_tail(&sec->list, &sec_list);
mutex_unlock(&sec_list_lock);
mutex_lock(&hisi_sec_list_lock);
list_add_tail(&hisi_sec->list, &hisi_sec_list);
mutex_unlock(&hisi_sec_list_lock);
}
static inline void sec_remove_from_list(struct sec_dev *sec)
static inline void hisi_sec_remove_from_list(struct hisi_sec *hisi_sec)
{
mutex_lock(&sec_list_lock);
list_del(&sec->list);
mutex_unlock(&sec_list_lock);
mutex_lock(&hisi_sec_list_lock);
list_del(&hisi_sec->list);
mutex_unlock(&hisi_sec_list_lock);
}
static u8 sec_get_endian(struct sec_dev *sec)
u8 sec_get_endian(struct hisi_sec *hisi_sec)
{
struct hisi_qm *qm = &sec->qm;
u32 reg;
/*
* As for VF, it is a wrong way to get endian setting by
* reading a register of the engine
*/
if (qm->pdev->is_virtfn) {
dev_err_ratelimited(&qm->pdev->dev,
"cannot access a register in VF!\n");
if (hisi_sec->qm.pdev->is_virtfn) {
dev_err_ratelimited(&hisi_sec->qm.pdev->dev,
"error! shouldn't access a register in VF\n");
return SEC_LE;
}
reg = readl_relaxed(qm->io_base + SEC_ENGINE_PF_CFG_OFF +
reg = readl_relaxed(hisi_sec->qm.io_base + SEC_ENGINE_PF_CFG_OFF +
SEC_ACC_COMMON_REG_OFF + SEC_CONTROL_REG);
/* BD little endian mode */
if (!(reg & BIT(0)))
return SEC_LE;
/* BD 32-bits big endian mode */
else if (!(reg & BIT(1)))
return SEC_32BE;
/* BD 64-bits big endian mode */
else
return SEC_64BE;
}
static int sec_engine_init(struct sec_dev *sec)
static int sec_engine_init(struct hisi_sec *hisi_sec)
{
struct hisi_qm *qm = &sec->qm;
int ret;
u32 reg;
struct hisi_qm *qm = &hisi_sec->qm;
void *base = qm->io_base + SEC_ENGINE_PF_CFG_OFF +
SEC_ACC_COMMON_REG_OFF;
/* disable clock gate control */
reg = readl_relaxed(SEC_ADDR(qm, SEC_CONTROL_REG));
reg &= SEC_CLK_GATE_DISABLE;
writel_relaxed(reg, SEC_ADDR(qm, SEC_CONTROL_REG));
writel_relaxed(0x1, SEC_ADDR(qm, SEC_MEM_START_INIT_REG));
ret = readl_relaxed_poll_timeout(SEC_ADDR(qm, SEC_MEM_INIT_DONE_REG),
reg, reg & 0x1, SEC_DELAY_10_US,
SEC_POLL_TIMEOUT_US);
reg = readl_relaxed(base + SEC_CONTROL_REG);
reg &= ~BIT(3);
writel(reg, base + SEC_CONTROL_REG);
writel(0x1, base + SEC_MEM_START_INIT_REG);
ret = readl_relaxed_poll_timeout(base +
SEC_MEM_INIT_DONE_REG, reg, reg & 0x1,
SEC_DELAY_10_US, SEC_POLL_TIMEOUT_US);
if (ret) {
dev_err(&qm->pdev->dev, "fail to init sec mem\n");
return ret;
}
reg = readl_relaxed(SEC_ADDR(qm, SEC_CONTROL_REG));
reg = readl_relaxed(base + SEC_CONTROL_REG);
reg |= (0x1 << SEC_TRNG_EN_SHIFT);
writel_relaxed(reg, SEC_ADDR(qm, SEC_CONTROL_REG));
writel(reg, base + SEC_CONTROL_REG);
reg = readl_relaxed(SEC_ADDR(qm, SEC_INTERFACE_USER_CTRL0_REG));
reg = readl_relaxed(base + SEC_INTERFACE_USER_CTRL0_REG);
reg |= SEC_USER0_SMMU_NORMAL;
writel_relaxed(reg, SEC_ADDR(qm, SEC_INTERFACE_USER_CTRL0_REG));
writel(reg, base + SEC_INTERFACE_USER_CTRL0_REG);
reg = readl_relaxed(SEC_ADDR(qm, SEC_INTERFACE_USER_CTRL1_REG));
reg = readl_relaxed(base + SEC_INTERFACE_USER_CTRL1_REG);
reg |= SEC_USER1_SMMU_NORMAL;
writel_relaxed(reg, SEC_ADDR(qm, SEC_INTERFACE_USER_CTRL1_REG));
writel(reg, base + SEC_INTERFACE_USER_CTRL1_REG);
writel_relaxed(SEC_BD_ERR_CHK_EN1,
SEC_ADDR(qm, SEC_BD_ERR_CHK_EN_REG1));
writel_relaxed(SEC_BD_ERR_CHK_EN2,
SEC_ADDR(qm, SEC_BD_ERR_CHK_EN_REG2));
writel(0xfffff7fd, base + SEC_BD_ERR_CHK_EN_REG(1));
writel(0xffffbfff, base + SEC_BD_ERR_CHK_EN_REG(3));
/* enable clock gate control */
reg = readl_relaxed(SEC_ADDR(qm, SEC_CONTROL_REG));
reg |= SEC_CLK_GATE_ENABLE;
writel_relaxed(reg, SEC_ADDR(qm, SEC_CONTROL_REG));
reg = readl_relaxed(base + SEC_CONTROL_REG);
reg |= BIT(3);
writel(reg, base + SEC_CONTROL_REG);
/* config endian */
reg = readl_relaxed(SEC_ADDR(qm, SEC_CONTROL_REG));
reg |= sec_get_endian(sec);
writel_relaxed(reg, SEC_ADDR(qm, SEC_CONTROL_REG));
reg = readl_relaxed(base + SEC_CONTROL_REG);
reg |= sec_get_endian(hisi_sec);
writel(reg, base + SEC_CONTROL_REG);
/* Enable sm4 xts mode multiple iv */
writel_relaxed(SEC_XTS_MIV_ENABLE_MSK,
qm->io_base + SEC_XTS_MIV_ENABLE_REG);
if (enable_sm4_ctr)
writel(SEC_SM4_CTR_ENABLE_MSK,
qm->io_base + SEC_SM4_CTR_ENABLE_REG);
writel(SEC_XTS_MIV_ENABLE_MSK,
qm->io_base + SEC_XTS_MIV_ENABLE_REG);
return 0;
}
static int sec_set_user_domain_and_cache(struct sec_dev *sec)
static void hisi_sec_disable_sm4_ctr(struct hisi_sec *hisi_sec)
{
struct hisi_qm *qm = &sec->qm;
struct hisi_qm *qm = &hisi_sec->qm;
if (enable_sm4_ctr)
writel(SEC_SM4_CTR_DISABLE_MSK,
qm->io_base + SEC_SM4_CTR_ENABLE_REG);
}
static void hisi_sec_set_user_domain_and_cache(struct hisi_sec *hisi_sec)
{
struct hisi_qm *qm = &hisi_sec->qm;
/* qm user domain */
writel(AXUSER_BASE, qm->io_base + QM_ARUSER_M_CFG_1);
......@@ -455,9 +548,6 @@ static int sec_set_user_domain_and_cache(struct sec_dev *sec)
/* qm cache */
writel(AXI_M_CFG, qm->io_base + QM_AXI_M_CFG);
writel(AXI_M_CFG_ENABLE, qm->io_base + QM_AXI_M_CFG_ENABLE);
/* disable FLR triggered by BME(bus master enable) */
writel(PEH_AXUSER_CFG, qm->io_base + QM_PEH_AXUSER_CFG);
writel(PEH_AXUSER_CFG_ENABLE, qm->io_base + QM_PEH_AXUSER_CFG_ENABLE);
/* enable sqc,cqc writeback */
......@@ -465,12 +555,14 @@ static int sec_set_user_domain_and_cache(struct sec_dev *sec)
CQC_CACHE_WB_ENABLE | FIELD_PREP(SQC_CACHE_WB_THRD, 1) |
FIELD_PREP(CQC_CACHE_WB_THRD, 1), qm->io_base + QM_CACHE_CTL);
return sec_engine_init(sec);
if (sec_engine_init(hisi_sec))
dev_err(&qm->pdev->dev, "sec_engine_init failed");
}
/* sec_debug_regs_clear() - clear the sec debug regs */
static void sec_debug_regs_clear(struct hisi_qm *qm)
static void hisi_sec_debug_regs_clear(struct hisi_sec *hisi_sec)
{
struct hisi_qm *qm = &hisi_sec->qm;
/* clear current_qm */
writel(0x0, qm->io_base + QM_DFX_MB_CNT_VF);
writel(0x0, qm->io_base + QM_DFX_DB_CNT_VF);
......@@ -481,107 +573,87 @@ static void sec_debug_regs_clear(struct hisi_qm *qm)
hisi_qm_debug_regs_clear(qm);
}
static void sec_hw_error_enable(struct sec_dev *sec)
static void hisi_sec_hw_error_set_state(struct hisi_sec *hisi_sec, bool state)
{
struct hisi_qm *qm = &sec->qm;
struct hisi_qm *qm = &hisi_sec->qm;
void *base = qm->io_base + SEC_ENGINE_PF_CFG_OFF +
SEC_ACC_COMMON_REG_OFF;
u32 val;
if (qm->ver == QM_HW_V1) {
writel(SEC_CORE_INT_DISABLE, qm->io_base + SEC_CORE_INT_MASK);
dev_info(&qm->pdev->dev, "V1 not support hw error handle\n");
dev_info(&qm->pdev->dev, "v%d don't support hw error handle\n",
qm->ver);
return;
}
val = readl(qm->io_base + SEC_CONTROL_REG);
val = readl(base + SEC_CONTROL_REG);
if (state) {
/* clear SEC hw error source if having */
writel(SEC_CORE_INT_DISABLE, qm->io_base +
SEC_CORE_INT_SOURCE);
/* clear SEC hw error source if having */
writel(SEC_CORE_INT_DISABLE, qm->io_base + SEC_CORE_INT_SOURCE);
/* enable SEC hw error interrupts */
writel(SEC_CORE_INT_ENABLE, qm->io_base + SEC_CORE_INT_MASK);
/* enable SEC hw error interrupts */
writel(SEC_CORE_INT_ENABLE, qm->io_base + SEC_CORE_INT_MASK);
/* enable RAS int */
writel(SEC_RAS_CE_ENB_MSK, base + SEC_RAS_CE_REG);
writel(SEC_RAS_FE_ENB_MSK, base + SEC_RAS_FE_REG);
writel(SEC_RAS_NFE_ENB_MSK, base + SEC_RAS_NFE_REG);
/* enable RAS int */
writel(SEC_RAS_CE_ENB_MSK, qm->io_base + SEC_RAS_CE_REG);
writel(SEC_RAS_FE_ENB_MSK, qm->io_base + SEC_RAS_FE_REG);
writel(SEC_RAS_NFE_ENB_MSK, qm->io_base + SEC_RAS_NFE_REG);
/* enable SEC block master OOO when m-bit error occur */
val = val | SEC_AXI_SHUTDOWN_ENABLE;
writel(val, qm->io_base + SEC_CONTROL_REG);
}
static void sec_hw_error_disable(struct sec_dev *sec)
{
struct hisi_qm *qm = &sec->qm;
u32 val;
val = readl(qm->io_base + SEC_CONTROL_REG);
/* disable RAS int */
writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_CE_REG);
writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_FE_REG);
writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_NFE_REG);
/* enable SEC block master OOO when m-bit error occur */
val = val | SEC_AXI_SHUTDOWN_ENABLE;
} else {
/* disable RAS int */
writel(SEC_RAS_DISABLE, base + SEC_RAS_CE_REG);
writel(SEC_RAS_DISABLE, base + SEC_RAS_FE_REG);
writel(SEC_RAS_DISABLE, base + SEC_RAS_NFE_REG);
/* disable SEC hw error interrupts */
writel(SEC_CORE_INT_DISABLE, qm->io_base + SEC_CORE_INT_MASK);
/* disable SEC hw error interrupts */
writel(SEC_CORE_INT_DISABLE, qm->io_base + SEC_CORE_INT_MASK);
/* disable SEC block master OOO when m-bit error occur */
val = val & SEC_AXI_SHUTDOWN_DISABLE;
/* disable SEC block master OOO when m-bit error occur */
val = val & SEC_AXI_SHUTDOWN_DISABLE;
}
writel(val, qm->io_base + SEC_CONTROL_REG);
writel(val, base + SEC_CONTROL_REG);
}
static void sec_hw_error_init(struct sec_dev *sec)
static inline struct hisi_qm *file_to_qm(struct ctrl_debug_file *file)
{
if (sec->qm.fun_type == QM_HW_VF)
return;
struct hisi_sec *hisi_sec = file->ctrl->hisi_sec;
hisi_qm_hw_error_init(&sec->qm, QM_BASE_CE,
QM_BASE_NFE | QM_ACC_DO_TASK_TIMEOUT
| QM_ACC_WB_NOT_READY_TIMEOUT, 0,
QM_DB_RANDOM_INVALID);
sec_hw_error_enable(sec);
return &hisi_sec->qm;
}
static void sec_hw_error_uninit(struct sec_dev *sec)
static u32 current_qm_read(struct ctrl_debug_file *file)
{
if (sec->qm.fun_type == QM_HW_VF)
return;
sec_hw_error_disable(sec);
hisi_qm_hw_error_uninit(&sec->qm);
}
static u32 sec_current_qm_read(struct sec_debug_file *file)
{
struct hisi_qm *qm = file->qm;
struct hisi_qm *qm = file_to_qm(file);
return readl(qm->io_base + QM_DFX_MB_CNT_VF);
}
static int sec_current_qm_write(struct sec_debug_file *file, u32 val)
static int current_qm_write(struct ctrl_debug_file *file, u32 val)
{
struct hisi_qm *qm = file->qm;
struct sec_dev *sec = container_of(qm, struct sec_dev, qm);
u32 vfq_num;
u32 tmp;
struct hisi_qm *qm = file_to_qm(file);
struct hisi_sec_ctrl *ctrl = file->ctrl;
u32 tmp, vfq_num;
if (val > sec->num_vfs)
if (val > ctrl->num_vfs)
return -EINVAL;
/* According PF or VF Dev ID to calculation curr_qm_qp_num and store */
if (!val) {
if (val == 0) {
qm->debug.curr_qm_qp_num = qm->qp_num;
} else {
vfq_num = (qm->ctrl_q_num - qm->qp_num) / sec->num_vfs;
if (val == sec->num_vfs)
vfq_num = (qm->ctrl_q_num - qm->qp_num) / ctrl->num_vfs;
if (val == ctrl->num_vfs) {
qm->debug.curr_qm_qp_num =
qm->ctrl_q_num - qm->qp_num -
(sec->num_vfs - 1) * vfq_num;
else
(ctrl->num_vfs - 1) * vfq_num;
} else {
qm->debug.curr_qm_qp_num = vfq_num;
}
}
writel(val, qm->io_base + QM_DFX_MB_CNT_VF);
......@@ -598,20 +670,20 @@ static int sec_current_qm_write(struct sec_debug_file *file, u32 val)
return 0;
}
static u32 sec_clear_enable_read(struct sec_debug_file *file)
static u32 clear_enable_read(struct ctrl_debug_file *file)
{
struct hisi_qm *qm = file->qm;
struct hisi_qm *qm = file_to_qm(file);
return readl(qm->io_base + SEC_CTRL_CNT_CLR_CE) &
SEC_CTRL_CNT_CLR_CE_BIT;
SEC_CTRL_CNT_CLR_CE_BIT;
}
static int sec_clear_enable_write(struct sec_debug_file *file, u32 val)
static int clear_enable_write(struct ctrl_debug_file *file, u32 val)
{
struct hisi_qm *qm = file->qm;
struct hisi_qm *qm = file_to_qm(file);
u32 tmp;
if (val != 1 && val)
if (val != 1 && val != 0)
return -EINVAL;
tmp = (readl(qm->io_base + SEC_CTRL_CNT_CLR_CE) &
......@@ -621,38 +693,35 @@ static int sec_clear_enable_write(struct sec_debug_file *file, u32 val)
return 0;
}
static ssize_t sec_debug_read(struct file *filp, char __user *buf,
static ssize_t ctrl_debug_read(struct file *filp, char __user *buf,
size_t count, loff_t *pos)
{
struct sec_debug_file *file = filp->private_data;
struct ctrl_debug_file *file = filp->private_data;
char tbuf[SEC_DBGFS_VAL_MAX_LEN];
u32 val;
int ret;
spin_lock_irq(&file->lock);
switch (file->index) {
case SEC_CURRENT_QM:
val = sec_current_qm_read(file);
val = current_qm_read(file);
break;
case SEC_CLEAR_ENABLE:
val = sec_clear_enable_read(file);
val = clear_enable_read(file);
break;
default:
spin_unlock_irq(&file->lock);
return -EINVAL;
}
spin_unlock_irq(&file->lock);
ret = snprintf(tbuf, SEC_DBGFS_VAL_MAX_LEN, "%u\n", val);
return simple_read_from_buffer(buf, count, pos, tbuf, ret);
}
static ssize_t sec_debug_write(struct file *filp, const char __user *buf,
size_t count, loff_t *pos)
static ssize_t ctrl_debug_write(struct file *filp, const char __user *buf,
size_t count, loff_t *pos)
{
struct sec_debug_file *file = filp->private_data;
struct ctrl_debug_file *file = filp->private_data;
char tbuf[SEC_DBGFS_VAL_MAX_LEN];
unsigned long val;
int len, ret;
......@@ -664,7 +733,7 @@ static ssize_t sec_debug_write(struct file *filp, const char __user *buf,
return -ENOSPC;
len = simple_write_to_buffer(tbuf, SEC_DBGFS_VAL_MAX_LEN - 1,
pos, buf, count);
pos, buf, count);
if (len < 0)
return len;
......@@ -673,15 +742,14 @@ static ssize_t sec_debug_write(struct file *filp, const char __user *buf,
return -EFAULT;
spin_lock_irq(&file->lock);
switch (file->index) {
case SEC_CURRENT_QM:
ret = sec_current_qm_write(file, val);
ret = current_qm_write(file, val);
if (ret)
goto err_input;
break;
case SEC_CLEAR_ENABLE:
ret = sec_clear_enable_write(file, val);
ret = clear_enable_write(file, val);
if (ret)
goto err_input;
break;
......@@ -689,7 +757,6 @@ static ssize_t sec_debug_write(struct file *filp, const char __user *buf,
ret = -EINVAL;
goto err_input;
}
spin_unlock_irq(&file->lock);
return count;
......@@ -699,22 +766,26 @@ static ssize_t sec_debug_write(struct file *filp, const char __user *buf,
return ret;
}
static const struct file_operations sec_dbg_fops = {
static const struct file_operations ctrl_debug_fops = {
.owner = THIS_MODULE,
.open = simple_open,
.read = sec_debug_read,
.write = sec_debug_write,
.read = ctrl_debug_read,
.write = ctrl_debug_write,
};
static int sec_core_debug_init(struct sec_dev *sec)
static int hisi_sec_core_debug_init(struct hisi_sec_ctrl *ctrl)
{
struct hisi_qm *qm = &sec->qm;
struct hisi_sec *hisi_sec = ctrl->hisi_sec;
struct hisi_qm *qm = &hisi_sec->qm;
struct device *dev = &qm->pdev->dev;
struct sec_dfx *dfx = &sec->debug.dfx;
struct hisi_sec_dfx *dfx = &hisi_sec->sec_dfx;
struct debugfs_regset32 *regset;
struct dentry *tmp_d, *tmp;
char buf[SEC_DBGFS_VAL_MAX_LEN];
snprintf(buf, SEC_DBGFS_VAL_MAX_LEN, "hisi_sec_dfx");
tmp_d = debugfs_create_dir("sec_dfx", sec->qm.debug.debug_root);
tmp_d = debugfs_create_dir(buf, ctrl->debug_root);
if (!tmp_d)
return -ENOENT;
......@@ -734,31 +805,32 @@ static int sec_core_debug_init(struct sec_dev *sec)
if (!tmp)
return -ENOENT;
tmp = debugfs_create_u64("recv_cnt", 0444, tmp_d, &dfx->recv_cnt);
if (!tmp)
return -ENOENT;
#ifdef CONFIG_CRYPTO_DEV_HISI_SEC2_FUSION
tmp = debugfs_create_u64("send_by_tmout", 0444, tmp_d,
&dfx->send_by_tmout);
&dfx->send_by_tmout);
if (!tmp)
return -ENOENT;
tmp = debugfs_create_u64("send_by_full", 0444, tmp_d,
&dfx->send_by_full);
&dfx->send_by_full);
if (!tmp)
return -ENOENT;
tmp = debugfs_create_u64("recv_cnt", 0444, tmp_d, &dfx->recv_cnt);
if (!tmp)
return -ENOENT;
tmp = debugfs_create_u64("get_task_cnt", 0444, tmp_d,
&dfx->get_task_cnt);
&dfx->get_task_cnt);
if (!tmp)
return -ENOENT;
tmp = debugfs_create_u64("put_task_cnt", 0444, tmp_d,
&dfx->put_task_cnt);
&dfx->put_task_cnt);
if (!tmp)
return -ENOENT;
tmp = debugfs_create_u64("gran_task_cnt", 0444, tmp_d,
&dfx->gran_task_cnt);
&dfx->gran_task_cnt);
if (!tmp)
return -ENOENT;
......@@ -767,42 +839,41 @@ static int sec_core_debug_init(struct sec_dev *sec)
return -ENOENT;
tmp = debugfs_create_u64("fake_busy_cnt", 0444,
tmp_d, &dfx->fake_busy_cnt);
tmp_d, &dfx->fake_busy_cnt);
if (!tmp)
return -ENOENT;
tmp = debugfs_create_u64("busy_comp_cnt", 0444, tmp_d,
&dfx->busy_comp_cnt);
&dfx->busy_comp_cnt);
if (!tmp)
return -ENOENT;
#endif
return 0;
}
static int sec_debug_init(struct sec_dev *sec)
static int hisi_sec_ctrl_debug_init(struct hisi_sec_ctrl *ctrl)
{
struct dentry *tmp;
int i;
for (i = SEC_CURRENT_QM; i < SEC_DEBUG_FILE_NUM; i++) {
spin_lock_init(&sec->debug.files[i].lock);
sec->debug.files[i].index = i;
sec->debug.files[i].qm = &sec->qm;
tmp = debugfs_create_file(sec_dbg_file_name[i], 0600,
sec->qm.debug.debug_root,
sec->debug.files + i,
&sec_dbg_fops);
spin_lock_init(&ctrl->files[i].lock);
ctrl->files[i].ctrl = ctrl;
ctrl->files[i].index = i;
tmp = debugfs_create_file(ctrl_debug_file_name[i], 0600,
ctrl->debug_root, ctrl->files + i,
&ctrl_debug_fops);
if (!tmp)
return -ENOENT;
}
return sec_core_debug_init(sec);
return hisi_sec_core_debug_init(ctrl);
}
static int sec_debugfs_init(struct sec_dev *sec)
static int hisi_sec_debugfs_init(struct hisi_sec *hisi_sec)
{
struct hisi_qm *qm = &sec->qm;
struct hisi_qm *qm = &hisi_sec->qm;
struct device *dev = &qm->pdev->dev;
struct dentry *dev_d;
int ret;
......@@ -816,29 +887,51 @@ static int sec_debugfs_init(struct sec_dev *sec)
if (ret)
goto failed_to_create;
if (qm->pdev->device == SEC_PF_PCI_DEVICE_ID) {
ret = sec_debug_init(sec);
if (qm->pdev->device == SEC_PCI_DEVICE_ID_PF) {
hisi_sec->ctrl->debug_root = dev_d;
ret = hisi_sec_ctrl_debug_init(hisi_sec->ctrl);
if (ret)
goto failed_to_create;
}
return 0;
failed_to_create:
failed_to_create:
debugfs_remove_recursive(sec_debugfs_root);
return ret;
}
static void sec_debugfs_exit(struct sec_dev *sec)
static void hisi_sec_debugfs_exit(struct hisi_sec *hisi_sec)
{
debugfs_remove_recursive(sec->qm.debug.debug_root);
struct hisi_qm *qm = &hisi_sec->qm;
debugfs_remove_recursive(qm->debug.debug_root);
if (qm->fun_type == QM_HW_PF) {
hisi_sec_debug_regs_clear(hisi_sec);
qm->debug.curr_qm_qp_num = 0;
}
}
static int sec_pf_probe_init(struct sec_dev *sec)
static void hisi_sec_hw_error_init(struct hisi_sec *hisi_sec)
{
struct hisi_qm *qm = &sec->qm;
int ret;
hisi_qm_hw_error_init(&hisi_sec->qm, QM_BASE_CE,
QM_BASE_NFE | QM_ACC_DO_TASK_TIMEOUT
| QM_ACC_WB_NOT_READY_TIMEOUT, 0,
QM_DB_RANDOM_INVALID);
hisi_sec_hw_error_set_state(hisi_sec, true);
}
static int hisi_sec_pf_probe_init(struct hisi_sec *hisi_sec)
{
struct hisi_qm *qm = &hisi_sec->qm;
struct hisi_sec_ctrl *ctrl;
ctrl = devm_kzalloc(&qm->pdev->dev, sizeof(*ctrl), GFP_KERNEL);
if (!ctrl)
return -ENOMEM;
hisi_sec->ctrl = ctrl;
ctrl->hisi_sec = hisi_sec;
switch (qm->ver) {
case QM_HW_V1:
......@@ -853,17 +946,14 @@ static int sec_pf_probe_init(struct sec_dev *sec)
return -EINVAL;
}
ret = sec_set_user_domain_and_cache(sec);
if (ret)
return ret;
sec_hw_error_init(sec);
sec_debug_regs_clear(qm);
hisi_sec_set_user_domain_and_cache(hisi_sec);
hisi_sec_hw_error_init(hisi_sec);
hisi_sec_debug_regs_clear(hisi_sec);
return 0;
}
static int sec_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)
static int hisi_sec_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)
{
enum qm_hw_ver rev_id;
......@@ -875,12 +965,12 @@ static int sec_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)
qm->ver = rev_id;
qm->sqe_size = SEC_SQE_SIZE;
qm->dev_name = sec_name;
qm->fun_type = (pdev->device == SEC_PF_PCI_DEVICE_ID) ?
QM_HW_PF : QM_HW_VF;
qm->use_dma_api = true;
qm->dev_name = hisi_sec_name;
qm->fun_type = (pdev->device == SEC_PCI_DEVICE_ID_PF) ?
QM_HW_PF : QM_HW_VF;
qm->algs = "sec\ncipher\ndigest\n";
qm->wq = sec_wq;
#ifdef CONFIG_CRYPTO_QM_UACCE
switch (uacce_mode) {
case UACCE_MODE_NOUACCE:
qm->use_dma_api = true;
......@@ -902,30 +992,23 @@ static int sec_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)
default:
return -EINVAL;
}
qm->algs = "sec\ncipher\ndigest\n";
#endif
return hisi_qm_init(qm);
}
static void sec_qm_uninit(struct hisi_qm *qm)
{
hisi_qm_uninit(qm);
}
static int sec_probe_init(struct hisi_qm *qm, struct sec_dev *sec)
static int hisi_sec_probe_init(struct hisi_qm *qm, struct hisi_sec *hisi_sec)
{
if (qm->fun_type == QM_HW_PF) {
qm->qp_base = SEC_PF_DEF_Q_BASE;
qm->qp_num = pf_q_num;
qm->debug.curr_qm_qp_num = pf_q_num;
return sec_pf_probe_init(sec);
return hisi_sec_pf_probe_init(hisi_sec);
} else if (qm->fun_type == QM_HW_VF) {
/*
* have no way to get qm configure in VM in v1 hardware,
* so currently force PF to uses SEC_PF_DEF_Q_NUM, and force
* to trigger only one VF in v1 hardware.
*
* v2 hardware has no such problem.
*/
if (qm->ver == QM_HW_V1) {
......@@ -935,96 +1018,71 @@ static int sec_probe_init(struct hisi_qm *qm, struct sec_dev *sec)
/* v2 starts to support get vft by mailbox */
return hisi_qm_get_vft(qm, &qm->qp_base, &qm->qp_num);
}
} else {
return -ENODEV;
}
return 0;
}
static void sec_probe_uninit(struct sec_dev *sec)
static int hisi_sec_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
sec_hw_error_disable(sec);
}
static int sec_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
struct sec_dev *sec;
struct hisi_sec *hisi_sec;
struct hisi_qm *qm;
int ret;
sec = devm_kzalloc(&pdev->dev, sizeof(*sec), GFP_KERNEL);
if (!sec)
hisi_sec = devm_kzalloc(&pdev->dev, sizeof(*hisi_sec), GFP_KERNEL);
if (!hisi_sec)
return -ENOMEM;
pci_set_drvdata(pdev, sec);
pci_set_drvdata(pdev, hisi_sec);
sec->ctx_q_num = ctx_q_num;
hisi_sec_add_to_list(hisi_sec);
#ifdef CONFIG_CRYPTO_DEV_HISI_SEC2_FUSION
sec->wq = sec_wq;
sec->fusion_time = fusion_time;
sec->fusion_limit = fusion_limit;
#endif
qm = &sec->qm;
ret = sec_qm_init(qm, pdev);
hisi_sec->hisi_sec_list_lock = &hisi_sec_list_lock;
hisi_sec->ctx_q_num = ctx_q_num;
hisi_sec->fusion_limit = fusion_limit;
hisi_sec->fusion_tmout_nsec = fusion_tmout_nsec;
qm = &hisi_sec->qm;
ret = hisi_sec_qm_init(qm, pdev);
if (ret) {
pci_err(pdev, "Failed to pre init qm!\n");
return ret;
dev_err(&pdev->dev, "Failed to pre init qm!\n");
goto err_remove_from_list;
}
ret = sec_probe_init(qm, sec);
ret = hisi_sec_probe_init(qm, hisi_sec);
if (ret) {
pci_err(pdev, "Failed to probe!\n");
dev_err(&pdev->dev, "Failed to probe!\n");
goto err_qm_uninit;
}
ret = hisi_qm_start(qm);
if (ret) {
pci_err(pdev, "Failed to start sec qm!\n");
goto err_probe_uninit;
}
ret = sec_debugfs_init(sec);
if (ret)
pci_warn(pdev, "Failed to init debugfs!\n");
sec_add_to_list(sec);
goto err_qm_uninit;
#if !defined(CONFIG_IOMMU_SVA) && defined(CONFIG_CRYPTO_QM_UACCE)
if (uacce_mode == UACCE_MODE_UACCE)
return 0;
#endif
ret = sec_register_to_crypto();
if (ret < 0) {
pr_err("Failed to register driver to crypto.\n");
goto err_remove_from_list;
}
ret = hisi_sec_debugfs_init(hisi_sec);
if (ret)
dev_err(&pdev->dev, "Failed to init debugfs (%d)!\n", ret);
return 0;
err_remove_from_list:
sec_remove_from_list(sec);
sec_debugfs_exit(sec);
hisi_qm_stop(qm, QM_NORMAL);
err_probe_uninit:
sec_probe_uninit(sec);
err_qm_uninit:
sec_qm_uninit(qm);
err_qm_uninit:
hisi_qm_uninit(qm);
err_remove_from_list:
hisi_sec_remove_from_list(hisi_sec);
return ret;
}
/* now we only support equal assignment */
static int sec_vf_q_assign(struct sec_dev *sec, u32 num_vfs)
static int hisi_sec_vf_q_assign(struct hisi_sec *hisi_sec, u32 num_vfs)
{
struct hisi_qm *qm = &sec->qm;
struct hisi_qm *qm = &hisi_sec->qm;
u32 qp_num = qm->qp_num;
u32 q_base = qp_num;
u32 q_num, remain_q_num;
int i, j, ret;
u32 q_num, remain_q_num, i;
int ret;
if (!num_vfs)
return -EINVAL;
......@@ -1036,21 +1094,19 @@ static int sec_vf_q_assign(struct sec_dev *sec, u32 num_vfs)
if (i == num_vfs)
q_num += remain_q_num % num_vfs;
ret = hisi_qm_set_vft(qm, i, q_base, q_num);
if (ret) {
for (j = i; j > 0; j--)
hisi_qm_set_vft(qm, j, 0, 0);
if (ret)
return ret;
}
q_base += q_num;
}
return 0;
}
static int sec_clear_vft_config(struct sec_dev *sec)
static int hisi_sec_clear_vft_config(struct hisi_sec *hisi_sec)
{
struct hisi_qm *qm = &sec->qm;
u32 num_vfs = sec->num_vfs;
struct hisi_sec_ctrl *ctrl = hisi_sec->ctrl;
struct hisi_qm *qm = &hisi_sec->qm;
u32 num_vfs = ctrl->num_vfs;
int ret;
u32 i;
......@@ -1060,141 +1116,140 @@ static int sec_clear_vft_config(struct sec_dev *sec)
return ret;
}
sec->num_vfs = 0;
ctrl->num_vfs = 0;
return 0;
}
static int sec_sriov_enable(struct pci_dev *pdev, int max_vfs)
static int hisi_sec_sriov_enable(struct pci_dev *pdev, int max_vfs)
{
struct sec_dev *sec = pci_get_drvdata(pdev);
int pre_existing_vfs, ret;
#ifdef CONFIG_PCI_IOV
struct hisi_sec *hisi_sec = pci_get_drvdata(pdev);
u32 num_vfs;
int pre_existing_vfs, ret;
pre_existing_vfs = pci_num_vf(pdev);
if (pre_existing_vfs) {
pci_err(pdev, "Can't enable VF. Please disable at first!\n");
dev_err(&pdev->dev,
"Can't enable VF. Please disable pre-enabled VFs!\n");
return 0;
}
num_vfs = min_t(u32, max_vfs, SEC_VF_NUM);
ret = sec_vf_q_assign(sec, num_vfs);
ret = hisi_sec_vf_q_assign(hisi_sec, num_vfs);
if (ret) {
pci_err(pdev, "Can't assign queues for VF!\n");
dev_err(&pdev->dev, "Can't assign queues for VF!\n");
return ret;
}
sec->num_vfs = num_vfs;
hisi_sec->ctrl->num_vfs = num_vfs;
ret = pci_enable_sriov(pdev, num_vfs);
if (ret) {
pci_err(pdev, "Can't enable VF!\n");
sec_clear_vft_config(sec);
dev_err(&pdev->dev, "Can't enable VF!\n");
hisi_sec_clear_vft_config(hisi_sec);
return ret;
}
return num_vfs;
#else
return 0;
#endif
}
static int sec_sriov_disable(struct pci_dev *pdev)
static int hisi_sec_sriov_disable(struct pci_dev *pdev)
{
struct sec_dev *sec = pci_get_drvdata(pdev);
struct hisi_sec *hisi_sec = pci_get_drvdata(pdev);
if (pci_vfs_assigned(pdev)) {
pci_err(pdev, "Can't disable VFs while VFs are assigned!\n");
dev_err(&pdev->dev,
"Can't disable VFs while VFs are assigned!\n");
return -EPERM;
}
/* remove in sec_pci_driver will be called to free VF resources */
/* remove in hisi_sec_pci_driver will be called to free VF resources */
pci_disable_sriov(pdev);
return sec_clear_vft_config(sec);
return hisi_sec_clear_vft_config(hisi_sec);
}
static int sec_sriov_configure(struct pci_dev *pdev, int num_vfs)
static int hisi_sec_sriov_configure(struct pci_dev *pdev, int num_vfs)
{
if (num_vfs)
return sec_sriov_enable(pdev, num_vfs);
if (num_vfs == 0)
return hisi_sec_sriov_disable(pdev);
else
return sec_sriov_disable(pdev);
return hisi_sec_sriov_enable(pdev, num_vfs);
}
static void sec_remove_wait_delay(struct sec_dev *sec)
static void hisi_sec_remove_wait_delay(struct hisi_sec *hisi_sec)
{
while (hisi_qm_frozen(&sec->qm))
while (hisi_qm_frozen(&hisi_sec->qm))
;
udelay(SEC_WAIT_DELAY);
}
static void sec_remove(struct pci_dev *pdev)
static void hisi_sec_remove(struct pci_dev *pdev)
{
struct sec_dev *sec = pci_get_drvdata(pdev);
struct hisi_qm *qm = &sec->qm;
struct hisi_sec *hisi_sec = pci_get_drvdata(pdev);
struct hisi_qm *qm = &hisi_sec->qm;
#ifdef CONFIG_CRYPTO_QM_UACCE
if (uacce_mode != UACCE_MODE_NOUACCE)
sec_remove_wait_delay(sec);
hisi_sec_remove_wait_delay(hisi_sec);
#ifndef CONFIG_IOMMU_SVA
if (uacce_mode != UACCE_MODE_UACCE)
#endif
#endif
sec_unregister_from_crypto();
sec_remove_from_list(sec);
if (qm->fun_type == QM_HW_PF && sec->num_vfs)
(void)sec_sriov_disable(pdev);
sec_debugfs_exit(sec);
if (qm->fun_type == QM_HW_PF && hisi_sec->ctrl->num_vfs != 0)
(void)hisi_sec_sriov_disable(pdev);
hisi_sec_debugfs_exit(hisi_sec);
(void)hisi_qm_stop(qm, QM_NORMAL);
if (qm->fun_type == QM_HW_PF)
sec_debug_regs_clear(qm);
sec_probe_uninit(sec);
if (qm->fun_type == QM_HW_PF) {
hisi_sec_hw_error_set_state(hisi_sec, false);
hisi_sec_disable_sm4_ctr(hisi_sec);
}
sec_qm_uninit(qm);
hisi_qm_uninit(qm);
hisi_sec_remove_from_list(hisi_sec);
}
static void sec_log_hw_error(struct sec_dev *sec, u32 err_sts)
static void hisi_sec_log_hw_error(struct hisi_sec *hisi_sec, u32 err_sts)
{
const struct sec_hw_error *errs = sec_hw_errors;
struct device *dev = &sec->qm.pdev->dev;
const struct hisi_sec_hw_error *err = sec_hw_error;
struct device *dev = &hisi_sec->qm.pdev->dev;
u32 err_val;
while (errs->msg) {
if (errs->int_msk & err_sts) {
while (err->msg) {
if (err->int_msk & err_sts) {
dev_err(dev, "%s [error status=0x%x] found\n",
errs->msg, errs->int_msk);
err->msg, err->int_msk);
if (SEC_CORE_INT_STATUS_M_ECC & err_sts) {
err_val = readl(sec->qm.io_base +
SEC_CORE_SRAM_ECC_ERR_INFO);
dev_err(dev, "multi ecc sram num=0x%x\n",
err_val = readl(hisi_sec->qm.io_base +
SEC_CORE_ECC_INFO);
dev_err(dev,
"hisi-sec multi ecc sram num=0x%x\n",
SEC_ECC_NUM(err_val));
dev_err(dev, "multi ecc sram addr=0x%x\n",
dev_err(dev,
"hisi-sec multi ecc sram addr=0x%x\n",
SEC_ECC_ADDR(err_val));
}
}
errs++;
err++;
}
}
static pci_ers_result_t sec_hw_error_handle(struct sec_dev *sec)
static pci_ers_result_t hisi_sec_hw_error_handle(struct hisi_sec *hisi_sec)
{
u32 err_sts;
/* read err sts */
err_sts = readl(sec->qm.io_base + SEC_CORE_INT_STATUS);
if (err_sts) {
sec_log_hw_error(sec, err_sts);
err_sts = readl(hisi_sec->qm.io_base + SEC_CORE_INT_STATUS);
if (err_sts) {
hisi_sec_log_hw_error(hisi_sec, err_sts);
/* clear error interrupts */
writel(err_sts, sec->qm.io_base + SEC_CORE_INT_SOURCE);
writel(err_sts, hisi_sec->qm.io_base + SEC_CORE_INT_SOURCE);
return PCI_ERS_RESULT_NEED_RESET;
}
......@@ -1202,47 +1257,49 @@ static pci_ers_result_t sec_hw_error_handle(struct sec_dev *sec)
return PCI_ERS_RESULT_RECOVERED;
}
static pci_ers_result_t sec_process_hw_error(struct pci_dev *pdev)
static pci_ers_result_t hisi_sec_process_hw_error(struct pci_dev *pdev)
{
struct sec_dev *sec = pci_get_drvdata(pdev);
struct hisi_sec *hisi_sec = pci_get_drvdata(pdev);
struct device *dev = &pdev->dev;
pci_ers_result_t qm_ret, sec_ret;
if (!sec) {
pci_err(pdev, "Can't recover error during device init\n");
if (!hisi_sec) {
dev_err(dev,
"Can't recover error occurred during device init\n");
return PCI_ERS_RESULT_NONE;
}
/* log qm error */
qm_ret = hisi_qm_hw_error_handle(&sec->qm);
qm_ret = hisi_qm_hw_error_handle(&hisi_sec->qm);
/* log sec error */
sec_ret = sec_hw_error_handle(sec);
sec_ret = hisi_sec_hw_error_handle(hisi_sec);
return (qm_ret == PCI_ERS_RESULT_NEED_RESET ||
sec_ret == PCI_ERS_RESULT_NEED_RESET) ?
PCI_ERS_RESULT_NEED_RESET : PCI_ERS_RESULT_RECOVERED;
PCI_ERS_RESULT_NEED_RESET : PCI_ERS_RESULT_RECOVERED;
}
static pci_ers_result_t sec_error_detected(struct pci_dev *pdev,
pci_channel_state_t state)
static pci_ers_result_t hisi_sec_error_detected(struct pci_dev *pdev,
pci_channel_state_t state)
{
if (pdev->is_virtfn)
return PCI_ERS_RESULT_NONE;
pci_info(pdev, "PCI error detected, state(=%d)!!\n", state);
dev_info(&pdev->dev, "PCI error detected, state(=%d)!!\n", state);
if (state == pci_channel_io_perm_failure)
return PCI_ERS_RESULT_DISCONNECT;
return sec_process_hw_error(pdev);
return hisi_sec_process_hw_error(pdev);
}
static int sec_reset_prepare_rdy(struct sec_dev *sec)
static int hisi_sec_reset_prepare_ready(struct hisi_sec *hisi_sec)
{
struct pci_dev *pdev = sec->qm.pdev;
struct sec_dev *psec = pci_get_drvdata(pci_physfn(pdev));
struct pci_dev *pdev = hisi_sec->qm.pdev;
struct hisi_sec *sec = pci_get_drvdata(pci_physfn(pdev));
int delay = 0;
while (test_and_set_bit(SEC_RESET, &psec->status)) {
while (test_and_set_bit(HISI_SEC_RESET, &sec->status)) {
msleep(++delay);
if (delay > SEC_RESET_WAIT_TIMEOUT)
return -EBUSY;
......@@ -1251,23 +1308,23 @@ static int sec_reset_prepare_rdy(struct sec_dev *sec)
return 0;
}
static int sec_vf_reset_prepare(struct pci_dev *pdev,
static int hisi_sec_vf_reset_prepare(struct pci_dev *pdev,
enum qm_stop_reason stop_reason)
{
struct sec_dev *sec;
struct hisi_sec *hisi_sec;
struct pci_dev *dev;
struct hisi_qm *qm;
int ret = 0;
mutex_lock(&sec_list_lock);
mutex_lock(&hisi_sec_list_lock);
if (pdev->is_physfn) {
list_for_each_entry(sec, &sec_list, list) {
dev = sec->qm.pdev;
list_for_each_entry(hisi_sec, &hisi_sec_list, list) {
dev = hisi_sec->qm.pdev;
if (dev == pdev)
continue;
if (pci_physfn(dev) == pdev) {
qm = &sec->qm;
qm = &hisi_sec->qm;
ret = hisi_qm_stop(qm, stop_reason);
if (ret)
......@@ -1277,23 +1334,23 @@ static int sec_vf_reset_prepare(struct pci_dev *pdev,
}
prepare_fail:
mutex_unlock(&sec_list_lock);
mutex_unlock(&hisi_sec_list_lock);
return ret;
}
static int sec_controller_reset_prepare(struct sec_dev *sec)
static int hisi_sec_controller_reset_prepare(struct hisi_sec *hisi_sec)
{
struct hisi_qm *qm = &sec->qm;
struct hisi_qm *qm = &hisi_sec->qm;
struct pci_dev *pdev = qm->pdev;
int ret;
ret = sec_reset_prepare_rdy(sec);
ret = hisi_sec_reset_prepare_ready(hisi_sec);
if (ret) {
dev_err(&pdev->dev, "Controller reset not ready!\n");
return ret;
}
ret = sec_vf_reset_prepare(pdev, QM_SOFT_RESET);
ret = hisi_sec_vf_reset_prepare(pdev, QM_SOFT_RESET);
if (ret) {
dev_err(&pdev->dev, "Fails to stop VFs!\n");
return ret;
......@@ -1318,12 +1375,13 @@ static int sec_controller_reset_prepare(struct sec_dev *sec)
return 0;
}
static int sec_soft_reset(struct sec_dev *sec)
static int hisi_sec_soft_reset(struct hisi_sec *hisi_sec)
{
struct hisi_qm *qm = &sec->qm;
struct hisi_qm *qm = &hisi_sec->qm;
struct device *dev = &qm->pdev->dev;
u32 val;
unsigned long long value;
int ret;
u32 val;
ret = hisi_qm_reg_test(qm);
if (ret)
......@@ -1342,14 +1400,16 @@ static int sec_soft_reset(struct sec_dev *sec)
}
/* OOO register set and check */
writel(SEC_MASTER_GLOBAL_CTRL_SHTDWN,
sec->qm.io_base + SEC_MASTER_GLOBAL_CTRL);
writel(SEC_MASTER_GLOBAL_CTRL_SHUTDOWN,
hisi_sec->qm.io_base + SEC_MASTER_GLOBAL_CTRL);
/* If bus lock, reset chip */
ret = readl_relaxed_poll_timeout(sec->qm.io_base +
SEC_MASTER_TRANS_RETURN, val,
(val == SEC_MASTER_TRANS_RETURN_RW),
SEC_DELAY_10_US, SEC_POLL_TIMEOUT_US);
ret = readl_relaxed_poll_timeout(hisi_sec->qm.io_base +
SEC_MASTER_TRANS_RETURN,
val,
(val == SEC_MASTER_TRANS_RETURN_RW),
SEC_DELAY_10_US,
SEC_POLL_TIMEOUT_US);
if (ret) {
dev_emerg(dev, "Bus lock! Please reset system.\n");
return ret;
......@@ -1364,12 +1424,11 @@ static int sec_soft_reset(struct sec_dev *sec)
/* The reset related sub-control registers are not in PCI BAR */
if (ACPI_HANDLE(dev)) {
acpi_status s;
unsigned long long value;
s = acpi_evaluate_object(ACPI_HANDLE(dev), "SRST",
NULL, (struct acpi_buffer *)&value);
if (ACPI_FAILURE(s)) {
dev_err(dev, "Controller reset fails\n");
s = acpi_evaluate_integer(ACPI_HANDLE(dev), "SRST",
NULL, &value);
if (ACPI_FAILURE(s) || value) {
dev_err(dev, "Controller reset fails %lld\n", value);
return -EIO;
}
} else {
......@@ -1380,21 +1439,21 @@ static int sec_soft_reset(struct sec_dev *sec)
return 0;
}
static int sec_vf_reset_done(struct pci_dev *pdev)
static int hisi_sec_vf_reset_done(struct pci_dev *pdev)
{
struct sec_dev *sec;
struct hisi_sec *hisi_sec;
struct pci_dev *dev;
struct hisi_qm *qm;
int ret = 0;
mutex_lock(&sec_list_lock);
list_for_each_entry(sec, &sec_list, list) {
dev = sec->qm.pdev;
mutex_lock(&hisi_sec_list_lock);
list_for_each_entry(hisi_sec, &hisi_sec_list, list) {
dev = hisi_sec->qm.pdev;
if (dev == pdev)
continue;
if (pci_physfn(dev) == pdev) {
qm = &sec->qm;
qm = &hisi_sec->qm;
ret = hisi_qm_restart(qm);
if (ret)
......@@ -1403,115 +1462,135 @@ static int sec_vf_reset_done(struct pci_dev *pdev)
}
reset_fail:
mutex_unlock(&sec_list_lock);
mutex_unlock(&hisi_sec_list_lock);
return ret;
}
static int sec_controller_reset_done(struct sec_dev *sec)
static int hisi_sec_controller_reset_done(struct hisi_sec *hisi_sec)
{
struct hisi_qm *qm = &sec->qm;
struct hisi_qm *qm = &hisi_sec->qm;
struct pci_dev *pdev = qm->pdev;
struct device *dev = &pdev->dev;
int ret;
ret = hisi_qm_set_msi(qm, SEC_ENABLE);
if (ret) {
pci_err(pdev, "Fails to enable peh msi bit!\n");
dev_err(dev, "Fails to enable peh msi bit!\n");
return ret;
}
ret = hisi_qm_set_pf_mse(qm, SEC_ENABLE);
if (ret) {
pci_err(pdev, "Fails to enable pf mse bit!\n");
dev_err(dev, "Fails to enable pf mse bit!\n");
return ret;
}
ret = hisi_qm_set_vf_mse(qm, SEC_ENABLE);
if (ret) {
pci_err(pdev, "Fails to enable vf mse bit!\n");
dev_err(dev, "Fails to enable vf mse bit!\n");
return ret;
}
sec_set_user_domain_and_cache(sec);
sec_hw_error_init(sec);
hisi_sec_set_user_domain_and_cache(hisi_sec);
hisi_sec_hw_error_init(hisi_sec);
ret = hisi_qm_restart(qm);
if (ret) {
pci_err(pdev, "Failed to start QM!\n");
return ret;
dev_err(dev, "Failed to start QM!\n");
return -EPERM;
}
if (sec->num_vfs) {
ret = sec_vf_q_assign(sec, sec->num_vfs);
if (hisi_sec->ctrl->num_vfs) {
ret = hisi_sec_vf_q_assign(hisi_sec, hisi_sec->ctrl->num_vfs);
if (ret) {
pci_err(pdev, "Failed to assign vf queues!\n");
dev_err(dev, "Failed to assign vf queues!\n");
return ret;
}
}
ret = sec_vf_reset_done(pdev);
ret = hisi_sec_vf_reset_done(pdev);
if (ret) {
pci_err(pdev, "Failed to start VFs!\n");
return ret;
dev_err(dev, "Failed to start VFs!\n");
return -EPERM;
}
return 0;
}
static int sec_controller_reset(struct sec_dev *sec)
static int hisi_sec_controller_reset(struct hisi_sec *hisi_sec)
{
struct device *dev = &sec->qm.pdev->dev;
struct device *dev = &hisi_sec->qm.pdev->dev;
int ret;
dev_info(dev, "Controller resetting...\n");
ret = sec_controller_reset_prepare(sec);
ret = hisi_sec_controller_reset_prepare(hisi_sec);
if (ret)
return ret;
ret = sec_soft_reset(sec);
ret = hisi_sec_soft_reset(hisi_sec);
if (ret) {
dev_err(dev, "Controller reset failed (%d)\n", ret);
return ret;
}
ret = sec_controller_reset_done(sec);
ret = hisi_sec_controller_reset_done(hisi_sec);
if (ret)
return ret;
clear_bit(SEC_RESET, &sec->status);
clear_bit(HISI_SEC_RESET, &hisi_sec->status);
dev_info(dev, "Controller reset complete\n");
return 0;
}
static pci_ers_result_t sec_slot_reset(struct pci_dev *pdev)
static pci_ers_result_t hisi_sec_slot_reset(struct pci_dev *pdev)
{
struct sec_dev *sec = pci_get_drvdata(pdev);
struct hisi_sec *hisi_sec = pci_get_drvdata(pdev);
int ret;
if (pdev->is_virtfn)
return PCI_ERS_RESULT_RECOVERED;
pci_info(pdev, "Requesting reset due to PCI error\n");
dev_info(&pdev->dev, "Requesting reset due to PCI error\n");
pci_cleanup_aer_uncorrect_error_status(pdev);
/* reset sec controller */
ret = sec_controller_reset(sec);
ret = hisi_sec_controller_reset(hisi_sec);
if (ret) {
pci_warn(pdev, "hisi_sec controller reset failed (%d)\n", ret);
dev_warn(&pdev->dev, "hisi_sec controller reset failed (%d)\n",
ret);
return PCI_ERS_RESULT_DISCONNECT;
}
return PCI_ERS_RESULT_RECOVERED;
}
static int sec_get_hw_error_status(struct sec_dev *sec)
static void hisi_sec_set_hw_error(struct hisi_sec *hisi_sec, bool state)
{
struct pci_dev *pdev = hisi_sec->qm.pdev;
struct hisi_sec *sec = pci_get_drvdata(pci_physfn(pdev));
struct hisi_qm *qm = &sec->qm;
if (qm->fun_type == QM_HW_VF)
return;
if (state)
hisi_qm_hw_error_init(qm, QM_BASE_CE,
QM_BASE_NFE | QM_ACC_WB_NOT_READY_TIMEOUT,
0, QM_DB_RANDOM_INVALID);
else
hisi_qm_hw_error_uninit(qm);
hisi_sec_hw_error_set_state(sec, state);
}
static int hisi_sec_get_hw_error_status(struct hisi_sec *hisi_sec)
{
u32 err_sts;
err_sts = readl(sec->qm.io_base + SEC_CORE_INT_STATUS) &
err_sts = readl(hisi_sec->qm.io_base + SEC_CORE_INT_STATUS) &
SEC_CORE_INT_STATUS_M_ECC;
if (err_sts)
return err_sts;
......@@ -1519,183 +1598,209 @@ static int sec_get_hw_error_status(struct sec_dev *sec)
return 0;
}
static int sec_check_hw_error(struct sec_dev *sec)
static int hisi_sec_check_hw_error(struct hisi_sec *hisi_sec)
{
struct pci_dev *pdev = sec->qm.pdev;
struct sec_dev *psec = pci_get_drvdata(pci_physfn(pdev));
struct hisi_qm *pf_qm = &psec->qm;
struct pci_dev *pdev = hisi_sec->qm.pdev;
struct hisi_sec *sec = pci_get_drvdata(pci_physfn(pdev));
struct hisi_qm *qm = &sec->qm;
int ret;
if (pf_qm->fun_type == QM_HW_VF)
if (qm->fun_type == QM_HW_VF)
return 0;
ret = hisi_qm_get_hw_error_status(pf_qm);
ret = hisi_qm_get_hw_error_status(qm);
if (ret)
return ret;
return sec_get_hw_error_status(psec);
return hisi_sec_get_hw_error_status(sec);
}
static void sec_reset_prepare(struct pci_dev *pdev)
static void hisi_sec_reset_prepare(struct pci_dev *pdev)
{
struct sec_dev *sec = pci_get_drvdata(pdev);
struct hisi_qm *qm = &sec->qm;
struct hisi_sec *hisi_sec = pci_get_drvdata(pdev);
struct hisi_qm *qm = &hisi_sec->qm;
struct device *dev = &pdev->dev;
u32 delay = 0;
int ret;
sec_hw_error_uninit(sec);
hisi_sec_set_hw_error(hisi_sec, SEC_HW_ERROR_IRQ_DISABLE);
while (sec_check_hw_error(sec)) {
while (hisi_sec_check_hw_error(hisi_sec)) {
msleep(++delay);
if (delay > SEC_RESET_WAIT_TIMEOUT)
return;
}
ret = sec_reset_prepare_rdy(sec);
ret = hisi_sec_reset_prepare_ready(hisi_sec);
if (ret) {
pci_err(pdev, "FLR not ready!\n");
dev_err(dev, "FLR not ready!\n");
return;
}
ret = sec_vf_reset_prepare(pdev, QM_FLR);
ret = hisi_sec_vf_reset_prepare(pdev, QM_FLR);
if (ret) {
pci_err(pdev, "Fails to prepare reset!\n");
dev_err(dev, "Fails to prepare reset!\n");
return;
}
ret = hisi_qm_stop(qm, QM_FLR);
if (ret) {
pci_err(pdev, "Fails to stop QM!\n");
dev_err(dev, "Fails to stop QM!\n");
return;
}
pci_info(pdev, "FLR resetting...\n");
dev_info(dev, "FLR resetting...\n");
}
static void sec_flr_reset_complete(struct pci_dev *pdev)
static void hisi_sec_flr_reset_complete(struct pci_dev *pdev)
{
struct pci_dev *pf_pdev = pci_physfn(pdev);
struct sec_dev *sec = pci_get_drvdata(pf_pdev);
struct hisi_sec *hisi_sec = pci_get_drvdata(pf_pdev);
struct device *dev = &hisi_sec->qm.pdev->dev;
u32 id;
pci_read_config_dword(sec->qm.pdev, PCI_COMMAND, &id);
pci_read_config_dword(hisi_sec->qm.pdev, PCI_COMMAND, &id);
if (id == SEC_PCI_COMMAND_INVALID)
pci_err(pdev, "Device can not be used!\n");
dev_err(dev, "Device can not be used!\n");
clear_bit(SEC_RESET, &sec->status);
clear_bit(HISI_SEC_RESET, &hisi_sec->status);
}
static void sec_reset_done(struct pci_dev *pdev)
static void hisi_sec_reset_done(struct pci_dev *pdev)
{
struct sec_dev *sec = pci_get_drvdata(pdev);
struct hisi_qm *qm = &sec->qm;
struct hisi_sec *hisi_sec = pci_get_drvdata(pdev);
struct hisi_qm *qm = &hisi_sec->qm;
struct device *dev = &pdev->dev;
int ret;
sec_hw_error_init(sec);
hisi_sec_set_hw_error(hisi_sec, SEC_HW_ERROR_IRQ_ENABLE);
ret = hisi_qm_restart(qm);
if (ret) {
pci_err(pdev, "Failed to start QM!\n");
dev_err(dev, "Failed to start QM!\n");
goto flr_done;
}
if (pdev->is_physfn) {
sec_set_user_domain_and_cache(sec);
if (sec->num_vfs) {
ret = sec_vf_q_assign(sec, sec->num_vfs);
hisi_sec_set_user_domain_and_cache(hisi_sec);
if (hisi_sec->ctrl->num_vfs) {
ret = hisi_sec_vf_q_assign(hisi_sec,
hisi_sec->ctrl->num_vfs);
if (ret) {
pci_err(pdev, "Failed to assign vf queue\n");
dev_err(dev, "Failed to assign vf queue\n");
goto flr_done;
}
}
ret = sec_vf_reset_done(pdev);
ret = hisi_sec_vf_reset_done(pdev);
if (ret) {
pci_err(pdev, "Failed to reset vf\n");
dev_err(dev, "Failed to reset vf\n");
goto flr_done;
}
}
flr_done:
sec_flr_reset_complete(pdev);
hisi_sec_flr_reset_complete(pdev);
pci_info(pdev, "FLR reset complete\n");
dev_info(dev, "FLR reset complete\n");
}
static const struct pci_error_handlers sec_err_handler = {
.error_detected = sec_error_detected,
.slot_reset = sec_slot_reset,
.reset_prepare = sec_reset_prepare,
.reset_done = sec_reset_done,
static const struct pci_error_handlers hisi_sec_err_handler = {
.error_detected = hisi_sec_error_detected,
.slot_reset = hisi_sec_slot_reset,
.reset_prepare = hisi_sec_reset_prepare,
.reset_done = hisi_sec_reset_done,
};
static struct pci_driver sec_pci_driver = {
.name = "hisi_sec2",
.id_table = sec_dev_ids,
.probe = sec_probe,
.remove = sec_remove,
.err_handler = &sec_err_handler,
.sriov_configure = sec_sriov_configure,
static struct pci_driver hisi_sec_pci_driver = {
.name = "hisi_sec",
.id_table = hisi_sec_dev_ids,
.probe = hisi_sec_probe,
.remove = hisi_sec_remove,
.sriov_configure = hisi_sec_sriov_configure,
.err_handler = &hisi_sec_err_handler,
};
static void sec_register_debugfs(void)
static void hisi_sec_register_debugfs(void)
{
if (!debugfs_initialized())
return;
sec_debugfs_root = debugfs_create_dir("hisi_sec2", NULL);
sec_debugfs_root = debugfs_create_dir("hisi_sec", NULL);
if (IS_ERR_OR_NULL(sec_debugfs_root))
sec_debugfs_root = NULL;
}
static void sec_unregister_debugfs(void)
static void hisi_sec_unregister_debugfs(void)
{
debugfs_remove_recursive(sec_debugfs_root);
}
static int __init sec_init(void)
static int __init hisi_sec_init(void)
{
int ret;
#ifdef CONFIG_CRYPTO_DEV_HISI_SEC2_FUSION
sec_wq = alloc_workqueue("hisi_sec2", WQ_HIGHPRI | WQ_CPU_INTENSIVE |
sec_wq = alloc_workqueue("hisi_sec", WQ_HIGHPRI | WQ_CPU_INTENSIVE |
WQ_MEM_RECLAIM | WQ_UNBOUND, num_online_cpus());
if (!sec_wq) {
pr_err("Fallied to alloc workqueue\n");
return -ENOMEM;
}
#endif
sec_register_debugfs();
ret = pci_register_driver(&sec_pci_driver);
hisi_sec_register_debugfs();
ret = pci_register_driver(&hisi_sec_pci_driver);
if (ret < 0) {
#ifdef CONFIG_CRYPTO_DEV_HISI_SEC2_FUSION
if (sec_wq)
destroy_workqueue(sec_wq);
#endif
sec_unregister_debugfs();
pr_err("Failed to register pci driver.\n");
return ret;
goto err_pci;
}
#ifndef CONFIG_IOMMU_SVA
if (uacce_mode == UACCE_MODE_UACCE)
return 0;
#endif
if (list_empty(&hisi_sec_list)) {
pr_err("no device!\n");
ret = -ENODEV;
goto err_probe_device;
}
pr_info("hisi_sec: register to crypto\n");
ret = hisi_sec_register_to_crypto(fusion_limit);
if (ret < 0) {
pr_err("Failed to register driver to crypto.\n");
goto err_probe_device;
}
return 0;
err_probe_device:
pci_unregister_driver(&hisi_sec_pci_driver);
err_pci:
hisi_sec_unregister_debugfs();
if (sec_wq)
destroy_workqueue(sec_wq);
return ret;
}
static void __exit sec_exit(void)
static void __exit hisi_sec_exit(void)
{
pci_unregister_driver(&sec_pci_driver);
sec_unregister_debugfs();
#ifdef CONFIG_CRYPTO_DEV_HISI_SEC2_FUSION
#ifndef CONFIG_IOMMU_SVA
if (uacce_mode != UACCE_MODE_UACCE)
hisi_sec_unregister_from_crypto(fusion_limit);
#else
hisi_sec_unregister_from_crypto(fusion_limit);
#endif
pci_unregister_driver(&hisi_sec_pci_driver);
hisi_sec_unregister_debugfs();
if (sec_wq)
destroy_workqueue(sec_wq);
#endif
}
module_init(sec_init);
module_exit(sec_exit);
module_init(hisi_sec_init);
module_exit(hisi_sec_exit);
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Zaibo Xu <xuzaibo@huawei.com");
MODULE_AUTHOR("Longfang Liu <liulongfang@huawei.com>");
MODULE_AUTHOR("Zhang Wei <zhangwei375@huawei.com>");
MODULE_DESCRIPTION("Driver for HiSilicon SEC accelerator");
drivers/crypto/hisilicon/sec2/sec_usr_if.h 0 → 100644
浏览文件 @ 457dd4e3
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (c) 2018-2019 HiSilicon Limited.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#ifndef HISI_SEC_USR_IF_H
#define HISI_SEC_USR_IF_H
struct hisi_sec_sqe_type1 {
__u32 rsvd2:6;
__u32 ci_gen:2;
__u32 ai_gen:2;
__u32 rsvd1:7;
__u32 c_key_type:2;
__u32 a_key_type:2;
__u32 rsvd0:10;
__u32 inveld:1;
__u32 mac_len:6;
__u32 a_key_len:5;
__u32 a_alg:6;
__u32 rsvd3:15;
__u32 c_icv_len:6;
__u32 c_width:3;
__u32 c_key_len:3;
__u32 c_mode:4;
__u32 c_alg:4;
__u32 rsvd4:12;
__u32 auth_gran_size:24;
__u32:8;
__u32 cipher_gran_size:24;
__u32:8;
__u32 auth_src_offset:16;
__u32 cipher_src_offset:16;
__u32 gran_num:16;
__u32 rsvd5:16;
__u32 src_skip_data_len:24;
__u32 rsvd6:8;
__u32 dst_skip_data_len:24;
__u32 rsvd7:8;
__u32 tag:16;
__u32 rsvd8:16;
__u32 gen_page_pad_ctrl:4;
__u32 gen_grd_ctrl:4;
__u32 gen_ver_ctrl:4;
__u32 gen_app_ctrl:4;
__u32 gen_ver_val:8;
__u32 gen_app_val:8;
__u32 private_info;
__u32 gen_ref_ctrl:4;
__u32 page_pad_type:2;
__u32 rsvd9:2;
__u32 chk_grd_ctrl:4;
__u32 chk_ref_ctrl:4;
__u32 block_size:16;
__u32 lba_l;
__u32 lba_h;
__u32 a_key_addr_l;
__u32 a_key_addr_h;
__u32 mac_addr_l;
__u32 mac_addr_h;
__u32 c_ivin_addr_l;
__u32 c_ivin_addr_h;
__u32 c_key_addr_l;
__u32 c_key_addr_h;
__u32 data_src_addr_l;
__u32 data_src_addr_h;
__u32 data_dst_addr_l;
__u32 data_dst_addr_h;
__u32 done:1;
__u32 icv:3;
__u32 rsvd11:3;
__u32 flag:4;
__u32 dif_check:3;
__u32 rsvd10:2;
__u32 error_type:8;
__u32 warning_type:8;
__u32 dw29;
__u32 dw30;
__u32 dw31;
};
struct hisi_sec_sqe_type2 {
__u32 nonce_len:4;
__u32 huk:1;
__u32 key_s:1;
__u32 ci_gen:2;
__u32 ai_gen:2;
__u32 a_pad:2;
__u32 c_s:2;
__u32 rsvd1:2;
__u32 rhf:1;
__u32 c_key_type:2;
__u32 a_key_type:2;
__u32 write_frame_len:3;
__u32 cal_iv_addr_en:1;
__u32 tls_up:1;
__u32 rsvd0:5;
__u32 inveld:1;
__u32 mac_len:5;
__u32 a_key_len:6;
__u32 a_alg:6;
__u32 rsvd3:15;
__u32 c_icv_len:6;
__u32 c_width:3;
__u32 c_key_len:3;
__u32 c_mode:4;
__u32 c_alg:4;
__u32 rsvd4:12;
__u32 a_len:24;
__u32 iv_offset_l:8;
__u32 c_len:24;
__u32 iv_offset_h:8;
__u32 auth_src_offset:16;
__u32 cipher_src_offset:16;
__u32 cs_ip_header_offset:16;
__u32 cs_udp_header_offset:16;
__u32 pass_word_len:16;
__u32 dk_len:16;
__u32 salt3:8;
__u32 salt2:8;
__u32 salt1:8;
__u32 salt0:8;
__u32 tag:16;
__u32 rsvd5:16;
__u32 c_pad_type:4;
__u32 c_pad_len:8;
__u32 c_pad_data_type:4;
__u32 c_pad_len_field:2;
__u32 rsvd6:14;
__u32 long_a_data_len_l;
__u32 long_a_data_len_h;
__u32 a_ivin_addr_l;
__u32 a_ivin_addr_h;
__u32 a_key_addr_l;
__u32 a_key_addr_h;
__u32 mac_addr_l;
__u32 mac_addr_h;
__u32 c_ivin_addr_l;
__u32 c_ivin_addr_h;
__u32 c_key_addr_l;
__u32 c_key_addr_h;
__u32 data_src_addr_l;
__u32 data_src_addr_h;
__u32 data_dst_addr_l;
__u32 data_dst_addr_h;
__u32 done:1;
__u32 icv:3;
__u32 rsvd11:3;
__u32 flag:4;
__u32 rsvd10:5;
__u32 error_type:8;
__u32 warning_type:8;
__u32 mac_i3:8;
__u32 mac_i2:8;
__u32 mac_i1:8;
__u32 mac_i0:8;
__u32 check_sum_i:16;
__u32 tls_pad_len_i:8;
__u32 rsvd12:8;
__u32 counter;
};
struct hisi_sec_sqe {
__u32 type:4;
__u32 cipher:2;
__u32 auth:2;
__u32 seq:1;
__u32 de:2;
__u32 scene:4;
__u32 src_addr_type:3;
__u32 dst_addr_type:3;
__u32 mac_addr_type:3;
__u32 rsvd0:8;
union {
struct hisi_sec_sqe_type1 type1;
struct hisi_sec_sqe_type2 type2;
};
};
#endif
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