i2c: designware: fix race between subsequent xfers
The designware block is not always properly disabled in the case of transfer errors. Interrupts from aborted transfers might be handled after the data structures for the following transfer are initialised but before the hardware is set up. This can corrupt the data structures to the point that the system is stuck in an infinite interrupt loop (where FIFOs are never emptied because dev->msg_read_idx == dev->msgs_num). This patch cleanly disables the designware-i2c hardware at the end of every transfer, be it successful or not. Signed-off-by: NChristian Ruppert <christian.ruppert@abilis.com> [wsa: extended the comment] Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
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