From 37402ccab5353c8f263b655377a9bf40b8467643 Mon Sep 17 00:00:00 2001 From: yumeng18 Date: Thu, 26 Sep 2019 14:49:01 +0800 Subject: [PATCH] crypto/hisilicon/hpre: disable HPRE FLR triggered by BME. driver inclusion category: bugfix bugzilla: NA CVE: NA If not, when u unbind and bind hpre device quickly, it's still in D3 state, (however, the state we need is D0), as its BME FLR hasn't finished yet. Feature or Bugfix: Bugfix Signed-off-by: yumeng18 Reviewed-by: xuzaibo Reviewed-by: Zhou Wang Reviewed-by: Yang Yingliang Signed-off-by: Yang Yingliang --- drivers/crypto/hisilicon/hpre/hpre_main.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/crypto/hisilicon/hpre/hpre_main.c b/drivers/crypto/hisilicon/hpre/hpre_main.c index de676f994c1c..db65b1516f17 100644 --- a/drivers/crypto/hisilicon/hpre/hpre_main.c +++ b/drivers/crypto/hisilicon/hpre/hpre_main.c @@ -385,6 +385,10 @@ static int hpre_set_user_domain_and_cache(struct hpre *hpre) writel(HPRE_QM_USR_CFG_MASK, HPRE_ADDR(QM_AWUSER_M_CFG_ENABLE)); writel_relaxed(HPRE_QM_AXI_CFG_MASK, HPRE_ADDR(QM_AXI_M_CFG)); + /* disable FLR triggered by BME(bus master enable) */ + writel(PEH_AXUSER_CFG, HPRE_ADDR(QM_PEH_AXUSER_CFG)); + writel(PEH_AXUSER_CFG_ENABLE, HPRE_ADDR(QM_PEH_AXUSER_CFG_ENABLE)); + /* HPRE need more time, we close this interrupt */ val = readl_relaxed(HPRE_ADDR(HPRE_QM_ABNML_INT_MASK)); val |= BIT(HPRE_TIMEOUT_ABNML_BIT); @@ -885,8 +889,6 @@ static int hpre_probe(struct pci_dev *pdev, const struct pci_device_id *id) if (!hpre) return -ENOMEM; pci_set_drvdata(pdev, hpre); - if (pci_enable_device(pdev) < 0) - return -ENODEV; qm = &hpre->qm; ret = hpre_qm_pre_init(qm, pdev); if (ret) -- GitLab