From 34991bd48c927712678d0cea77628328f9046923 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Sat, 11 Nov 2017 10:03:36 +0000 Subject: [PATCH] drm/i915: Unify SLICE_UNIT_LEVEL_CLKGATE w/a for cnl gem_workarounds reports that the SLICE_UNIT_LEVEL_CLKGATE write isn't sticking. Commit 0a60797a0efb ("drm/i915: Implement ReadHitWriteOnlyDisable.") presumes that SLICE_UNIT_LEVEL_CLKGATE is a masked register in the context image, but commit 90007bca6162 ("drm/i915/cnl: Introduce initial Cannonlake Workarounds.") lists it as an ordering unmasked register. The masked write will be losing the default settings if we trust the original commit. That gem_workarounds reports the value is lost entirely is more worrying though -- but it clearly suggests that it is not a masked register in the context image, so unify both w/a to use the original rmw. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103705 Fixes: 0a60797a0efb ("drm/i915: Implement ReadHitWriteOnlyDisable.") References: 90007bca6162 ("drm/i915/cnl: Introduce initial Cannonlake Workarounds.") Signed-off-by: Chris Wilson Cc: Rafael Antognolli Cc: Rodrigo Vivi Cc: Oscar Mateo Cc: Mika Kuoppala Cc: Jani Nikula Cc: Joonas Lahtinen Link: https://patchwork.freedesktop.org/patch/msgid/20171111100336.11020-1-chris@chris-wilson.co.uk Reviewed-by: Rafael Antognolli --- drivers/gpu/drm/i915/intel_engine_cs.c | 3 --- drivers/gpu/drm/i915/intel_pm.c | 8 +++++--- 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index 70bbe8ef8f54..1bd9462d206f 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -1326,9 +1326,6 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine) WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_GPGPU_LEVEL_MASK, GEN9_PREEMPT_GPGPU_COMMAND_LEVEL); - /* ReadHitWriteOnlyDisable: cnl */ - WA_SET_BIT_MASKED(SLICE_UNIT_LEVEL_CLKGATE, RCCUNIT_CLKGATE_DIS); - /* WaEnablePreemptionGranularityControlByUMD:cnl */ I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1, _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL)); diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 8e7f02e6008a..8c69ec9eb6ee 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -8471,11 +8471,13 @@ static void cnl_init_clock_gating(struct drm_i915_private *dev_priv) I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | DISP_FBC_MEMORY_WAKE); + val = I915_READ(SLICE_UNIT_LEVEL_CLKGATE); + /* ReadHitWriteOnlyDisable:cnl */ + val |= RCCUNIT_CLKGATE_DIS; /* WaSarbUnitClockGatingDisable:cnl (pre-prod) */ if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0)) - I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE, - I915_READ(SLICE_UNIT_LEVEL_CLKGATE) | - SARBUNIT_CLKGATE_DIS); + val |= SARBUNIT_CLKGATE_DIS; + I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE, val); /* Display WA #1133: WaFbcSkipSegments:cnl */ val = I915_READ(ILK_DPFC_CHICKEN); -- GitLab