提交 2656c076 编写于 作者: L Linus Torvalds
......@@ -598,19 +598,6 @@ config ARCH_MEMORY_PROBE
def_bool y
depends on MEMORY_HOTPLUG
# Some NUMA nodes have memory ranges that span
# other nodes. Even though a pfn is valid and
# between a node's start and end pfns, it may not
# reside on that node.
#
# This is a relatively temporary hack that should
# be able to go away when sparsemem is fully in
# place
config NODES_SPAN_OTHER_NODES
def_bool y
depends on NEED_MULTIPLE_NODES
config PPC_64K_PAGES
bool "64k page size"
depends on PPC64
......
......@@ -33,6 +33,8 @@ endif
export CROSS32CC CROSS32AS CROSS32LD CROSS32OBJCOPY
KBUILD_DEFCONFIG := $(shell uname -m)_defconfig
ifeq ($(CONFIG_PPC64),y)
OLDARCH := ppc64
SZ := 64
......@@ -111,9 +113,6 @@ cpu-as-$(CONFIG_E200) += -Wa,-me200
AFLAGS += $(cpu-as-y)
CFLAGS += $(cpu-as-y)
# Default to the common case.
KBUILD_DEFCONFIG := common_defconfig
head-y := arch/powerpc/kernel/head_32.o
head-$(CONFIG_PPC64) := arch/powerpc/kernel/head_64.o
head-$(CONFIG_8xx) := arch/powerpc/kernel/head_8xx.o
......@@ -125,11 +124,11 @@ head-$(CONFIG_PPC64) += arch/powerpc/kernel/entry_64.o
head-$(CONFIG_PPC_FPU) += arch/powerpc/kernel/fpu.o
core-y += arch/powerpc/kernel/ \
arch/$(OLDARCH)/kernel/ \
arch/powerpc/mm/ \
arch/powerpc/lib/ \
arch/powerpc/sysdev/ \
arch/powerpc/platforms/
core-$(CONFIG_PPC32) += arch/ppc/kernel/
core-$(CONFIG_MATH_EMULATION) += arch/ppc/math-emu/
core-$(CONFIG_XMON) += arch/powerpc/xmon/
core-$(CONFIG_APUS) += arch/ppc/amiga/
......@@ -165,7 +164,7 @@ define archhelp
@echo ' (your) ~/bin/installkernel or'
@echo ' (distribution) /sbin/installkernel or'
@echo ' install to $$(INSTALL_PATH) and run lilo'
@echo ' *_defconfig - Select default config from arch/$(ARCH)/ppc/configs'
@echo ' *_defconfig - Select default config from arch/$(ARCH)/configs'
endef
archclean:
......
......@@ -14,43 +14,42 @@
.text
.globl _zimage_start
_zimage_start:
bl reloc_offset
bl 1f
reloc_offset:
1:
mflr r0
lis r9,reloc_offset@ha
addi r9,r9,reloc_offset@l
lis r9,1b@ha
addi r9,r9,1b@l
subf. r0,r9,r0
beq clear_caches
beq 3f
reloc_got2:
lis r9,__got2_start@ha
addi r9,r9,__got2_start@l
lis r8,__got2_end@ha
addi r8,r8,__got2_end@l
subf. r8,r9,r8
beq clear_caches
beq 3f
srwi. r8,r8,2
mtctr r8
add r9,r0,r9
reloc_got2_loop:
2:
lwz r8,0(r9)
add r8,r8,r0
stw r8,0(r9)
addi r9,r9,4
bdnz reloc_got2_loop
bdnz 2b
clear_caches:
3:
lis r9,_start@h
add r9,r0,r9
lis r8,_etext@ha
addi r8,r8,_etext@l
add r8,r0,r8
1: dcbf r0,r9
4: dcbf r0,r9
icbi r0,r9
addi r9,r9,0x20
cmplwi 0,r9,8
blt 1b
blt 4b
sync
isync
......
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.14-rc4
# Thu Oct 20 08:28:33 2005
# Linux kernel version: 2.6.15-rc1
# Fri Nov 18 16:23:24 2005
#
CONFIG_PPC64=y
CONFIG_64BIT=y
CONFIG_PPC_MERGE=y
CONFIG_MMU=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_RWSEM_XCHGADD_ALGORITHM=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_GENERIC_ISA_DMA=y
CONFIG_PPC=y
CONFIG_EARLY_PRINTK=y
CONFIG_COMPAT=y
CONFIG_SYSVIPC_COMPAT=y
CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
CONFIG_ARCH_MAY_HAVE_PC_FDC=y
CONFIG_FORCE_MAX_ZONEORDER=13
#
# Processor support
#
# CONFIG_POWER4_ONLY is not set
CONFIG_POWER3=y
CONFIG_POWER4=y
CONFIG_PPC_FPU=y
CONFIG_ALTIVEC=y
CONFIG_PPC_STD_MMU=y
CONFIG_SMP=y
CONFIG_NR_CPUS=32
#
# Code maturity level options
......@@ -41,7 +56,7 @@ CONFIG_CPUSETS=y
CONFIG_INITRAMFS_SOURCE=""
# CONFIG_EMBEDDED is not set
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_ALL is not set
CONFIG_KALLSYMS_ALL=y
# CONFIG_KALLSYMS_EXTRA_PASS is not set
CONFIG_PRINTK=y
CONFIG_BUG=y
......@@ -67,78 +82,115 @@ CONFIG_MODVERSIONS=y
CONFIG_MODULE_SRCVERSION_ALL=y
CONFIG_KMOD=y
CONFIG_STOP_MACHINE=y
CONFIG_SYSVIPC_COMPAT=y
#
# Block layer
#
#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_AS=y
CONFIG_IOSCHED_DEADLINE=y
CONFIG_IOSCHED_CFQ=y
CONFIG_DEFAULT_AS=y
# CONFIG_DEFAULT_DEADLINE is not set
# CONFIG_DEFAULT_CFQ is not set
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="anticipatory"
#
# Platform support
#
# CONFIG_PPC_ISERIES is not set
CONFIG_PPC_MULTIPLATFORM=y
# CONFIG_PPC_ISERIES is not set
# CONFIG_EMBEDDED6xx is not set
# CONFIG_APUS is not set
CONFIG_PPC_PSERIES=y
CONFIG_PPC_BPA=y
CONFIG_PPC_PMAC=y
CONFIG_PPC_PMAC64=y
CONFIG_PPC_MAPLE=y
CONFIG_PPC=y
CONFIG_PPC64=y
# CONFIG_PPC_CELL is not set
CONFIG_PPC_OF=y
CONFIG_XICS=y
CONFIG_MPIC=y
CONFIG_BPA_IIC=y
CONFIG_ALTIVEC=y
CONFIG_PPC_SPLPAR=y
CONFIG_KEXEC=y
CONFIG_IBMVIO=y
CONFIG_U3_DART=y
CONFIG_MPIC=y
CONFIG_PPC_RTAS=y
CONFIG_RTAS_ERROR_LOGGING=y
CONFIG_RTAS_PROC=y
CONFIG_RTAS_FLASH=m
# CONFIG_MMIO_NVRAM is not set
CONFIG_MPIC_BROKEN_U3=y
CONFIG_PPC_PMAC64=y
CONFIG_BOOTX_TEXT=y
# CONFIG_POWER4_ONLY is not set
CONFIG_IBMVIO=y
# CONFIG_PPC_MPC106 is not set
CONFIG_GENERIC_TBSYNC=y
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_TABLE=y
# CONFIG_CPU_FREQ_DEBUG is not set
CONFIG_CPU_FREQ_STAT=y
# CONFIG_CPU_FREQ_STAT_DETAILS is not set
CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
CONFIG_CPU_FREQ_GOV_USERSPACE=y
# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
CONFIG_CPU_FREQ_PMAC64=y
# CONFIG_WANT_EARLY_SERIAL is not set
#
# Kernel options
#
# CONFIG_HZ_100 is not set
CONFIG_HZ_250=y
# CONFIG_HZ_1000 is not set
CONFIG_HZ=250
CONFIG_PREEMPT_NONE=y
# CONFIG_PREEMPT_VOLUNTARY is not set
# CONFIG_PREEMPT is not set
# CONFIG_PREEMPT_BKL is not set
CONFIG_BINFMT_ELF=y
CONFIG_BINFMT_MISC=m
CONFIG_FORCE_MAX_ZONEORDER=13
CONFIG_IOMMU_VMERGE=y
CONFIG_SMP=y
CONFIG_NR_CPUS=32
CONFIG_HOTPLUG_CPU=y
CONFIG_KEXEC=y
CONFIG_IRQ_ALL_CPUS=y
CONFIG_PPC_SPLPAR=y
CONFIG_EEH=y
CONFIG_SCANLOG=m
CONFIG_LPARCFG=y
# CONFIG_NUMA is not set
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
CONFIG_ARCH_FLATMEM_ENABLE=y
CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
CONFIG_ARCH_DISCONTIGMEM_DEFAULT=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_SPARSEMEM_DEFAULT=y
CONFIG_SELECT_MEMORY_MODEL=y
# CONFIG_FLATMEM_MANUAL is not set
CONFIG_DISCONTIGMEM_MANUAL=y
# CONFIG_SPARSEMEM_MANUAL is not set
CONFIG_DISCONTIGMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
CONFIG_NEED_MULTIPLE_NODES=y
# CONFIG_DISCONTIGMEM_MANUAL is not set
CONFIG_SPARSEMEM_MANUAL=y
CONFIG_SPARSEMEM=y
CONFIG_HAVE_MEMORY_PRESENT=y
# CONFIG_SPARSEMEM_STATIC is not set
CONFIG_HAVE_ARCH_EARLY_PFN_TO_NID=y
CONFIG_NODES_SPAN_OTHER_NODES=y
# CONFIG_NUMA is not set
CONFIG_SPARSEMEM_EXTREME=y
# CONFIG_MEMORY_HOTPLUG is not set
CONFIG_SPLIT_PTLOCK_CPUS=4096
# CONFIG_PPC_64K_PAGES is not set
# CONFIG_SCHED_SMT is not set
CONFIG_PREEMPT_NONE=y
# CONFIG_PREEMPT_VOLUNTARY is not set
# CONFIG_PREEMPT is not set
# CONFIG_PREEMPT_BKL is not set
# CONFIG_HZ_100 is not set
CONFIG_HZ_250=y
# CONFIG_HZ_1000 is not set
CONFIG_HZ=250
CONFIG_EEH=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_PPC_RTAS=y
CONFIG_RTAS_PROC=y
CONFIG_RTAS_FLASH=m
CONFIG_SCANLOG=m
CONFIG_LPARCFG=y
CONFIG_SECCOMP=y
CONFIG_BINFMT_ELF=y
CONFIG_BINFMT_MISC=m
CONFIG_HOTPLUG_CPU=y
CONFIG_PROC_DEVICETREE=y
# CONFIG_CMDLINE_BOOL is not set
# CONFIG_PM is not set
CONFIG_SECCOMP=y
CONFIG_ISA_DMA_API=y
#
# Bus Options
# Bus options
#
CONFIG_GENERIC_ISA_DMA=y
CONFIG_PPC_I8259=y
# CONFIG_PPC_INDIRECT_PCI is not set
CONFIG_PCI=y
CONFIG_PCI_DOMAINS=y
# CONFIG_PCI_LEGACY_PROC is not set
......@@ -158,6 +210,7 @@ CONFIG_HOTPLUG_PCI=m
# CONFIG_HOTPLUG_PCI_SHPC is not set
CONFIG_HOTPLUG_PCI_RPA=m
CONFIG_HOTPLUG_PCI_RPA_DLPAR=m
CONFIG_KERNEL_START=0xc000000000000000
#
# Networking
......@@ -199,6 +252,10 @@ CONFIG_TCP_CONG_BIC=y
# CONFIG_IPV6 is not set
CONFIG_NETFILTER=y
# CONFIG_NETFILTER_DEBUG is not set
#
# Core Netfilter Configuration
#
CONFIG_NETFILTER_NETLINK=y
CONFIG_NETFILTER_NETLINK_QUEUE=m
CONFIG_NETFILTER_NETLINK_LOG=m
......@@ -301,6 +358,10 @@ CONFIG_LLC=y
# CONFIG_NET_DIVERT is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
#
# QoS and/or fair queueing
#
# CONFIG_NET_SCHED is not set
CONFIG_NET_CLS_ROUTE=y
......@@ -338,13 +399,7 @@ CONFIG_FW_LOADER=y
#
# Parallel port support
#
CONFIG_PARPORT=m
CONFIG_PARPORT_PC=m
# CONFIG_PARPORT_SERIAL is not set
# CONFIG_PARPORT_PC_FIFO is not set
# CONFIG_PARPORT_PC_SUPERIO is not set
# CONFIG_PARPORT_GSC is not set
# CONFIG_PARPORT_1284 is not set
# CONFIG_PARPORT is not set
#
# Plug and Play support
......@@ -354,7 +409,6 @@ CONFIG_PARPORT_PC=m
# Block devices
#
CONFIG_BLK_DEV_FD=y
# CONFIG_PARIDE is not set
# CONFIG_BLK_CPQ_DA is not set
# CONFIG_BLK_CPQ_CISS_DA is not set
# CONFIG_BLK_DEV_DAC960 is not set
......@@ -370,14 +424,6 @@ CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=65536
CONFIG_BLK_DEV_INITRD=y
# CONFIG_CDROM_PKTCDVD is not set
#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_AS=y
CONFIG_IOSCHED_DEADLINE=y
CONFIG_IOSCHED_CFQ=y
# CONFIG_ATA_OVER_ETH is not set
#
......@@ -407,7 +453,7 @@ CONFIG_IDEPCI_SHARE_IRQ=y
# CONFIG_BLK_DEV_OFFBOARD is not set
CONFIG_BLK_DEV_GENERIC=y
# CONFIG_BLK_DEV_OPTI621 is not set
CONFIG_BLK_DEV_SL82C105=y
# CONFIG_BLK_DEV_SL82C105 is not set
CONFIG_BLK_DEV_IDEDMA_PCI=y
# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
CONFIG_IDEDMA_PCI_AUTO=y
......@@ -479,6 +525,7 @@ CONFIG_SCSI_ISCSI_ATTRS=m
#
# SCSI low-level drivers
#
# CONFIG_ISCSI_TCP is not set
# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
# CONFIG_SCSI_3W_9XXX is not set
# CONFIG_SCSI_ACARD is not set
......@@ -495,10 +542,12 @@ CONFIG_SCSI_SATA_SVW=y
# CONFIG_SCSI_ATA_PIIX is not set
# CONFIG_SCSI_SATA_MV is not set
# CONFIG_SCSI_SATA_NV is not set
# CONFIG_SCSI_SATA_PROMISE is not set
# CONFIG_SCSI_PDC_ADMA is not set
# CONFIG_SCSI_SATA_QSTOR is not set
# CONFIG_SCSI_SATA_PROMISE is not set
# CONFIG_SCSI_SATA_SX4 is not set
# CONFIG_SCSI_SATA_SIL is not set
# CONFIG_SCSI_SATA_SIL24 is not set
# CONFIG_SCSI_SATA_SIS is not set
# CONFIG_SCSI_SATA_ULI is not set
# CONFIG_SCSI_SATA_VIA is not set
......@@ -512,8 +561,6 @@ CONFIG_SCSI_SATA_SVW=y
CONFIG_SCSI_IBMVSCSI=y
# CONFIG_SCSI_INITIO is not set
# CONFIG_SCSI_INIA100 is not set
# CONFIG_SCSI_PPA is not set
# CONFIG_SCSI_IMM is not set
CONFIG_SCSI_SYM53C8XX_2=y
CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=0
CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
......@@ -608,6 +655,9 @@ CONFIG_IEEE1394_AMDTP=m
CONFIG_ADB_PMU=y
CONFIG_PMAC_SMU=y
CONFIG_THERM_PM72=y
CONFIG_WINDFARM=y
CONFIG_WINDFARM_PM81=y
CONFIG_WINDFARM_PM91=y
#
# Network device support
......@@ -664,7 +714,6 @@ CONFIG_E100=y
# CONFIG_EPIC100 is not set
# CONFIG_SUNDANCE is not set
# CONFIG_VIA_RHINE is not set
# CONFIG_NET_POCKET is not set
#
# Ethernet (1000 Mbit)
......@@ -684,7 +733,6 @@ CONFIG_E1000=y
# CONFIG_VIA_VELOCITY is not set
CONFIG_TIGON3=y
# CONFIG_BNX2 is not set
# CONFIG_SPIDER_NET is not set
# CONFIG_MV643XX_ETH is not set
#
......@@ -714,7 +762,6 @@ CONFIG_IBMOL=y
# CONFIG_WAN is not set
# CONFIG_FDDI is not set
# CONFIG_HIPPI is not set
# CONFIG_PLIP is not set
CONFIG_PPP=m
# CONFIG_PPP_MULTILINK is not set
# CONFIG_PPP_FILTER is not set
......@@ -722,6 +769,7 @@ CONFIG_PPP_ASYNC=m
CONFIG_PPP_SYNC_TTY=m
CONFIG_PPP_DEFLATE=m
CONFIG_PPP_BSDCOMP=m
# CONFIG_PPP_MPPE is not set
CONFIG_PPPOE=m
# CONFIG_SLIP is not set
# CONFIG_NET_FC is not set
......@@ -784,7 +832,6 @@ CONFIG_INPUT_PCSPKR=m
CONFIG_SERIO=y
CONFIG_SERIO_I8042=y
# CONFIG_SERIO_SERPORT is not set
# CONFIG_SERIO_PARKBD is not set
# CONFIG_SERIO_PCIPS2 is not set
CONFIG_SERIO_LIBPS2=y
# CONFIG_SERIO_RAW is not set
......@@ -817,10 +864,6 @@ CONFIG_SERIAL_JSM=m
CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
CONFIG_PRINTER=m
# CONFIG_LP_CONSOLE is not set
# CONFIG_PPDEV is not set
# CONFIG_TIPAR is not set
CONFIG_HVC_CONSOLE=y
CONFIG_HVCS=m
......@@ -834,6 +877,7 @@ CONFIG_HVCS=m
#
# CONFIG_WATCHDOG is not set
# CONFIG_RTC is not set
# CONFIG_GEN_RTC is not set
# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set
......@@ -851,6 +895,7 @@ CONFIG_MAX_RAW_DEVS=256
# TPM devices
#
# CONFIG_TCG_TPM is not set
# CONFIG_TELCLOCK is not set
#
# I2C support
......@@ -879,7 +924,6 @@ CONFIG_I2C_AMD8111=y
CONFIG_I2C_KEYWEST=y
CONFIG_I2C_PMAC_SMU=y
# CONFIG_I2C_NFORCE2 is not set
# CONFIG_I2C_PARPORT is not set
# CONFIG_I2C_PARPORT_LIGHT is not set
# CONFIG_I2C_PROSAVAGE is not set
# CONFIG_I2C_SAVAGE4 is not set
......@@ -904,6 +948,7 @@ CONFIG_I2C_PMAC_SMU=y
# CONFIG_SENSORS_PCF8591 is not set
# CONFIG_SENSORS_RTC8564 is not set
# CONFIG_SENSORS_MAX6875 is not set
# CONFIG_RTC_X1205_I2C is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
......@@ -945,7 +990,6 @@ CONFIG_FB=y
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_IMAGEBLIT=y
CONFIG_FB_SOFT_CURSOR=y
CONFIG_FB_MACMODES=y
CONFIG_FB_MODE_HELPERS=y
CONFIG_FB_TILEBLITTING=y
......@@ -960,6 +1004,7 @@ CONFIG_FB_OF=y
# CONFIG_FB_ASILIANT is not set
# CONFIG_FB_IMSTT is not set
# CONFIG_FB_VGA16 is not set
# CONFIG_FB_S1D13XXX is not set
# CONFIG_FB_NVIDIA is not set
# CONFIG_FB_RIVA is not set
CONFIG_FB_MATROX=y
......@@ -983,7 +1028,6 @@ CONFIG_FB_RADEON_I2C=y
# CONFIG_FB_VOODOO1 is not set
# CONFIG_FB_CYBLA is not set
# CONFIG_FB_TRIDENT is not set
# CONFIG_FB_S1D13XXX is not set
# CONFIG_FB_VIRTUAL is not set
#
......@@ -992,6 +1036,7 @@ CONFIG_FB_RADEON_I2C=y
# CONFIG_VGA_CONSOLE is not set
CONFIG_DUMMY_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE=y
# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
# CONFIG_FONTS is not set
CONFIG_FONT_8x8=y
CONFIG_FONT_8x16=y
......@@ -1012,7 +1057,94 @@ CONFIG_LCD_DEVICE=y
#
# Sound
#
# CONFIG_SOUND is not set
CONFIG_SOUND=m
#
# Advanced Linux Sound Architecture
#
CONFIG_SND=m
CONFIG_SND_TIMER=m
CONFIG_SND_PCM=m
CONFIG_SND_SEQUENCER=m
CONFIG_SND_SEQ_DUMMY=m
CONFIG_SND_OSSEMUL=y
CONFIG_SND_MIXER_OSS=m
CONFIG_SND_PCM_OSS=m
CONFIG_SND_SEQUENCER_OSS=y
# CONFIG_SND_VERBOSE_PRINTK is not set
# CONFIG_SND_DEBUG is not set
CONFIG_SND_GENERIC_DRIVER=y
#
# Generic devices
#
# CONFIG_SND_DUMMY is not set
# CONFIG_SND_VIRMIDI is not set
# CONFIG_SND_MTPAV is not set
# CONFIG_SND_SERIAL_U16550 is not set
# CONFIG_SND_MPU401 is not set
#
# PCI devices
#
# CONFIG_SND_ALI5451 is not set
# CONFIG_SND_ATIIXP is not set
# CONFIG_SND_ATIIXP_MODEM is not set
# CONFIG_SND_AU8810 is not set
# CONFIG_SND_AU8820 is not set
# CONFIG_SND_AU8830 is not set
# CONFIG_SND_AZT3328 is not set
# CONFIG_SND_BT87X is not set
# CONFIG_SND_CS46XX is not set
# CONFIG_SND_CS4281 is not set
# CONFIG_SND_EMU10K1 is not set
# CONFIG_SND_EMU10K1X is not set
# CONFIG_SND_CA0106 is not set
# CONFIG_SND_KORG1212 is not set
# CONFIG_SND_MIXART is not set
# CONFIG_SND_NM256 is not set
# CONFIG_SND_RME32 is not set
# CONFIG_SND_RME96 is not set
# CONFIG_SND_RME9652 is not set
# CONFIG_SND_HDSP is not set
# CONFIG_SND_HDSPM is not set
# CONFIG_SND_TRIDENT is not set
# CONFIG_SND_YMFPCI is not set
# CONFIG_SND_AD1889 is not set
# CONFIG_SND_ALS4000 is not set
# CONFIG_SND_CMIPCI is not set
# CONFIG_SND_ENS1370 is not set
# CONFIG_SND_ENS1371 is not set
# CONFIG_SND_ES1938 is not set
# CONFIG_SND_ES1968 is not set
# CONFIG_SND_MAESTRO3 is not set
# CONFIG_SND_FM801 is not set
# CONFIG_SND_ICE1712 is not set
# CONFIG_SND_ICE1724 is not set
# CONFIG_SND_INTEL8X0 is not set
# CONFIG_SND_INTEL8X0M is not set
# CONFIG_SND_SONICVIBES is not set
# CONFIG_SND_VIA82XX is not set
# CONFIG_SND_VIA82XX_MODEM is not set
# CONFIG_SND_VX222 is not set
# CONFIG_SND_HDA_INTEL is not set
#
# ALSA PowerMac devices
#
CONFIG_SND_POWERMAC=m
CONFIG_SND_POWERMAC_AUTO_DRC=y
#
# USB devices
#
# CONFIG_SND_USB_AUDIO is not set
# CONFIG_SND_USB_USX2Y is not set
#
# Open Sound System
#
# CONFIG_SOUND_PRIME is not set
#
# USB support
......@@ -1046,12 +1178,16 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y
#
# USB Device Class drivers
#
# CONFIG_USB_BLUETOOTH_TTY is not set
# CONFIG_OBSOLETE_OSS_USB_DRIVER is not set
# CONFIG_USB_ACM is not set
# CONFIG_USB_PRINTER is not set
#
# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
#
#
# may also be needed; see USB_STORAGE Help for more information
#
CONFIG_USB_STORAGE=m
# CONFIG_USB_STORAGE_DEBUG is not set
......@@ -1106,7 +1242,7 @@ CONFIG_USB_HIDDEV=y
#
# CONFIG_USB_CATC is not set
# CONFIG_USB_KAWETH is not set
CONFIG_USB_PEGASUS=y
# CONFIG_USB_PEGASUS is not set
# CONFIG_USB_RTL8150 is not set
# CONFIG_USB_USBNET is not set
# CONFIG_USB_MON is not set
......@@ -1114,7 +1250,6 @@ CONFIG_USB_PEGASUS=y
#
# USB port drivers
#
# CONFIG_USB_USS720 is not set
#
# USB Serial Converter support
......@@ -1163,6 +1298,7 @@ CONFIG_INFINIBAND_MTHCA=m
# CONFIG_INFINIBAND_MTHCA_DEBUG is not set
CONFIG_INFINIBAND_IPOIB=m
# CONFIG_INFINIBAND_IPOIB_DEBUG is not set
# CONFIG_INFINIBAND_SRP is not set
#
# SN Devices
......@@ -1358,10 +1494,25 @@ CONFIG_NLS_KOI8_U=m
CONFIG_NLS_UTF8=m
#
# Profiling support
# Library routines
#
CONFIG_CRC_CCITT=m
# CONFIG_CRC16 is not set
CONFIG_CRC32=y
CONFIG_LIBCRC32C=m
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=m
CONFIG_TEXTSEARCH=y
CONFIG_TEXTSEARCH_KMP=m
CONFIG_TEXTSEARCH_BM=m
CONFIG_TEXTSEARCH_FSM=m
#
# Instrumentation Support
#
CONFIG_PROFILING=y
CONFIG_OPROFILE=y
# CONFIG_KPROBES is not set
#
# Kernel hacking
......@@ -1378,14 +1529,15 @@ CONFIG_DETECT_SOFTLOCKUP=y
# CONFIG_DEBUG_KOBJECT is not set
# CONFIG_DEBUG_INFO is not set
CONFIG_DEBUG_FS=y
# CONFIG_DEBUG_VM is not set
# CONFIG_RCU_TORTURE_TEST is not set
CONFIG_DEBUG_STACKOVERFLOW=y
# CONFIG_KPROBES is not set
CONFIG_DEBUG_STACK_USAGE=y
CONFIG_DEBUGGER=y
CONFIG_XMON=y
# CONFIG_XMON_DEFAULT is not set
# CONFIG_PPCDBG is not set
CONFIG_IRQSTACKS=y
CONFIG_BOOTX_TEXT=y
#
# Security options
......@@ -1425,17 +1577,3 @@ CONFIG_CRYPTO_TEST=m
#
# Hardware crypto devices
#
#
# Library routines
#
CONFIG_CRC_CCITT=m
# CONFIG_CRC16 is not set
CONFIG_CRC32=y
CONFIG_LIBCRC32C=m
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=m
CONFIG_TEXTSEARCH=y
CONFIG_TEXTSEARCH_KMP=m
CONFIG_TEXTSEARCH_BM=m
CONFIG_TEXTSEARCH_FSM=m
......@@ -165,7 +165,6 @@ CONFIG_SPARSEMEM_EXTREME=y
# CONFIG_MEMORY_HOTPLUG is not set
CONFIG_SPLIT_PTLOCK_CPUS=4096
CONFIG_HAVE_ARCH_EARLY_PFN_TO_NID=y
CONFIG_NODES_SPAN_OTHER_NODES=y
# CONFIG_PPC_64K_PAGES is not set
CONFIG_SCHED_SMT=y
CONFIG_PROC_DEVICETREE=y
......
......@@ -12,12 +12,12 @@ CFLAGS_btext.o += -fPIC
endif
obj-y := semaphore.o cputable.o ptrace.o syscalls.o \
irq.o signal_32.o pmc.o vdso.o
irq.o align.o signal_32.o pmc.o vdso.o
obj-y += vdso32/
obj-$(CONFIG_PPC64) += setup_64.o binfmt_elf32.o sys_ppc32.o \
signal_64.o ptrace32.o systbl.o \
paca.o ioctl32.o cpu_setup_power4.o \
firmware.o sysfs.o udbg.o
firmware.o sysfs.o udbg.o idle_64.o
obj-$(CONFIG_PPC64) += vdso64/
obj-$(CONFIG_ALTIVEC) += vecemu.o vector.o
obj-$(CONFIG_POWER4) += idle_power4.o
......@@ -35,6 +35,7 @@ obj-$(CONFIG_PPC_PSERIES) += udbg_16550.o
obj-$(CONFIG_PPC_MAPLE) += udbg_16550.o
udbgscc-$(CONFIG_PPC64) := udbg_scc.o
obj-$(CONFIG_PPC_PMAC) += $(udbgscc-y)
obj64-$(CONFIG_PPC_MULTIPLATFORM) += nvram_64.o
ifeq ($(CONFIG_PPC_MERGE),y)
......@@ -78,5 +79,7 @@ smpobj-$(CONFIG_SMP) += smp.o
endif
obj-$(CONFIG_PPC64) += $(obj64-y)
extra-$(CONFIG_PPC_FPU) += fpu.o
extra-$(CONFIG_PPC64) += entry_64.o
......@@ -7,6 +7,9 @@
* PowerPC 403GCX/405GP modifications.
* Copyright (c) 2001-2002 PPC64 team, IBM Corp
* 64-bit and Power4 support
* Copyright (c) 2005 Benjamin Herrenschmidt, IBM Corp
* <benh@kernel.crashing.org>
* Merge ppc32 and ppc64 implementations
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
......@@ -38,10 +41,15 @@ struct aligninfo {
#define F 8 /* to/from fp regs */
#define U 0x10 /* update index register */
#define M 0x20 /* multiple load/store */
#define SW 0x40 /* byte swap */
#define SW 0x40 /* byte swap int or ... */
#define S 0x40 /* ... single-precision fp */
#define SX 0x40 /* byte count in XER */
#define HARD 0x80 /* string, stwcx. */
#define DCBZ 0x5f /* 8xx/82xx dcbz faults when cache not enabled */
#define SWAP(a, b) (t = (a), (a) = (b), (b) = t)
/*
* The PowerPC stores certain bits of the instruction that caused the
* alignment exception in the DSISR register. This array maps those
......@@ -57,14 +65,14 @@ static struct aligninfo aligninfo[128] = {
{ 2, LD+SE }, /* 00 0 0101: lha */
{ 2, ST }, /* 00 0 0110: sth */
{ 4, LD+M }, /* 00 0 0111: lmw */
{ 4, LD+F }, /* 00 0 1000: lfs */
{ 4, LD+F+S }, /* 00 0 1000: lfs */
{ 8, LD+F }, /* 00 0 1001: lfd */
{ 4, ST+F }, /* 00 0 1010: stfs */
{ 4, ST+F+S }, /* 00 0 1010: stfs */
{ 8, ST+F }, /* 00 0 1011: stfd */
INVALID, /* 00 0 1100 */
{ 8, LD }, /* 00 0 1101: ld */
{ 8, LD }, /* 00 0 1101: ld/ldu/lwa */
INVALID, /* 00 0 1110 */
{ 8, ST }, /* 00 0 1111: std */
{ 8, ST }, /* 00 0 1111: std/stdu */
{ 4, LD+U }, /* 00 1 0000: lwzu */
INVALID, /* 00 1 0001 */
{ 4, ST+U }, /* 00 1 0010: stwu */
......@@ -73,9 +81,9 @@ static struct aligninfo aligninfo[128] = {
{ 2, LD+SE+U }, /* 00 1 0101: lhau */
{ 2, ST+U }, /* 00 1 0110: sthu */
{ 4, ST+M }, /* 00 1 0111: stmw */
{ 4, LD+F+U }, /* 00 1 1000: lfsu */
{ 4, LD+F+S+U }, /* 00 1 1000: lfsu */
{ 8, LD+F+U }, /* 00 1 1001: lfdu */
{ 4, ST+F+U }, /* 00 1 1010: stfsu */
{ 4, ST+F+S+U }, /* 00 1 1010: stfsu */
{ 8, ST+F+U }, /* 00 1 1011: stfdu */
INVALID, /* 00 1 1100 */
INVALID, /* 00 1 1101 */
......@@ -89,10 +97,10 @@ static struct aligninfo aligninfo[128] = {
{ 4, LD+SE }, /* 01 0 0101: lwax */
INVALID, /* 01 0 0110 */
INVALID, /* 01 0 0111 */
{ 0, LD }, /* 01 0 1000: lswx */
{ 0, LD }, /* 01 0 1001: lswi */
{ 0, ST }, /* 01 0 1010: stswx */
{ 0, ST }, /* 01 0 1011: stswi */
{ 4, LD+M+HARD+SX }, /* 01 0 1000: lswx */
{ 4, LD+M+HARD }, /* 01 0 1001: lswi */
{ 4, ST+M+HARD+SX }, /* 01 0 1010: stswx */
{ 4, ST+M+HARD }, /* 01 0 1011: stswi */
INVALID, /* 01 0 1100 */
{ 8, LD+U }, /* 01 0 1101: ldu */
INVALID, /* 01 0 1110 */
......@@ -115,7 +123,7 @@ static struct aligninfo aligninfo[128] = {
INVALID, /* 01 1 1111 */
INVALID, /* 10 0 0000 */
INVALID, /* 10 0 0001 */
{ 0, ST }, /* 10 0 0010: stwcx. */
INVALID, /* 10 0 0010: stwcx. */
INVALID, /* 10 0 0011 */
INVALID, /* 10 0 0100 */
INVALID, /* 10 0 0101 */
......@@ -144,7 +152,7 @@ static struct aligninfo aligninfo[128] = {
INVALID, /* 10 1 1100 */
INVALID, /* 10 1 1101 */
INVALID, /* 10 1 1110 */
{ L1_CACHE_BYTES, ST }, /* 10 1 1111: dcbz */
{ 0, ST+HARD }, /* 10 1 1111: dcbz */
{ 4, LD }, /* 11 0 0000: lwzx */
INVALID, /* 11 0 0001 */
{ 4, ST }, /* 11 0 0010: stwx */
......@@ -153,9 +161,9 @@ static struct aligninfo aligninfo[128] = {
{ 2, LD+SE }, /* 11 0 0101: lhax */
{ 2, ST }, /* 11 0 0110: sthx */
INVALID, /* 11 0 0111 */
{ 4, LD+F }, /* 11 0 1000: lfsx */
{ 4, LD+F+S }, /* 11 0 1000: lfsx */
{ 8, LD+F }, /* 11 0 1001: lfdx */
{ 4, ST+F }, /* 11 0 1010: stfsx */
{ 4, ST+F+S }, /* 11 0 1010: stfsx */
{ 8, ST+F }, /* 11 0 1011: stfdx */
INVALID, /* 11 0 1100 */
{ 8, LD+M }, /* 11 0 1101: lmd */
......@@ -169,9 +177,9 @@ static struct aligninfo aligninfo[128] = {
{ 2, LD+SE+U }, /* 11 1 0101: lhaux */
{ 2, ST+U }, /* 11 1 0110: sthux */
INVALID, /* 11 1 0111 */
{ 4, LD+F+U }, /* 11 1 1000: lfsux */
{ 4, LD+F+S+U }, /* 11 1 1000: lfsux */
{ 8, LD+F+U }, /* 11 1 1001: lfdux */
{ 4, ST+F+U }, /* 11 1 1010: stfsux */
{ 4, ST+F+S+U }, /* 11 1 1010: stfsux */
{ 8, ST+F+U }, /* 11 1 1011: stfdux */
INVALID, /* 11 1 1100 */
INVALID, /* 11 1 1101 */
......@@ -179,45 +187,175 @@ static struct aligninfo aligninfo[128] = {
INVALID, /* 11 1 1111 */
};
#define SWAP(a, b) (t = (a), (a) = (b), (b) = t)
/*
* Create a DSISR value from the instruction
*/
static inline unsigned make_dsisr(unsigned instr)
{
unsigned dsisr;
/* create a DSISR value from the instruction */
dsisr = (instr & 0x03ff0000) >> 16; /* bits 6:15 --> 22:31 */
if ( IS_XFORM(instr) ) {
dsisr |= (instr & 0x00000006) << 14; /* bits 29:30 --> 15:16 */
dsisr |= (instr & 0x00000040) << 8; /* bit 25 --> 17 */
dsisr |= (instr & 0x00000780) << 3; /* bits 21:24 --> 18:21 */
/* bits 6:15 --> 22:31 */
dsisr = (instr & 0x03ff0000) >> 16;
if (IS_XFORM(instr)) {
/* bits 29:30 --> 15:16 */
dsisr |= (instr & 0x00000006) << 14;
/* bit 25 --> 17 */
dsisr |= (instr & 0x00000040) << 8;
/* bits 21:24 --> 18:21 */
dsisr |= (instr & 0x00000780) << 3;
} else {
/* bit 5 --> 17 */
dsisr |= (instr & 0x04000000) >> 12;
/* bits 1: 4 --> 18:21 */
dsisr |= (instr & 0x78000000) >> 17;
/* bits 30:31 --> 12:13 */
if (IS_DSFORM(instr))
dsisr |= (instr & 0x00000003) << 18;
}
return dsisr;
}
/*
* The dcbz (data cache block zero) instruction
* gives an alignment fault if used on non-cacheable
* memory. We handle the fault mainly for the
* case when we are running with the cache disabled
* for debugging.
*/
static int emulate_dcbz(struct pt_regs *regs, unsigned char __user *addr)
{
long __user *p;
int i, size;
#ifdef __powerpc64__
size = ppc64_caches.dline_size;
#else
size = L1_CACHE_BYTES;
#endif
p = (long __user *) (regs->dar & -size);
if (user_mode(regs) && !access_ok(VERIFY_WRITE, p, size))
return -EFAULT;
for (i = 0; i < size / sizeof(long); ++i)
if (__put_user(0, p+i))
return -EFAULT;
return 1;
}
/*
* Emulate load & store multiple instructions
* On 64-bit machines, these instructions only affect/use the
* bottom 4 bytes of each register, and the loads clear the
* top 4 bytes of the affected register.
*/
#ifdef CONFIG_PPC64
#define REG_BYTE(rp, i) *((u8 *)((rp) + ((i) >> 2)) + ((i) & 3) + 4)
#else
#define REG_BYTE(rp, i) *((u8 *)(rp) + (i))
#endif
static int emulate_multiple(struct pt_regs *regs, unsigned char __user *addr,
unsigned int reg, unsigned int nb,
unsigned int flags, unsigned int instr)
{
unsigned long *rptr;
unsigned int nb0, i;
/*
* We do not try to emulate 8 bytes multiple as they aren't really
* available in our operating environments and we don't try to
* emulate multiples operations in kernel land as they should never
* be used/generated there at least not on unaligned boundaries
*/
if (unlikely((nb > 4) || !user_mode(regs)))
return 0;
/* lmw, stmw, lswi/x, stswi/x */
nb0 = 0;
if (flags & HARD) {
if (flags & SX) {
nb = regs->xer & 127;
if (nb == 0)
return 1;
} else {
if (__get_user(instr,
(unsigned int __user *)regs->nip))
return -EFAULT;
nb = (instr >> 11) & 0x1f;
if (nb == 0)
nb = 32;
}
else {
dsisr |= (instr & 0x04000000) >> 12; /* bit 5 --> 17 */
dsisr |= (instr & 0x78000000) >> 17; /* bits 1: 4 --> 18:21 */
if ( IS_DSFORM(instr) ) {
dsisr |= (instr & 0x00000003) << 18; /* bits 30:31 --> 12:13 */
if (nb + reg * 4 > 128) {
nb0 = nb + reg * 4 - 128;
nb = 128 - reg * 4;
}
} else {
/* lwm, stmw */
nb = (32 - reg) * 4;
}
return dsisr;
if (!access_ok((flags & ST ? VERIFY_WRITE: VERIFY_READ), addr, nb+nb0))
return -EFAULT; /* bad address */
rptr = &regs->gpr[reg];
if (flags & LD) {
/*
* This zeroes the top 4 bytes of the affected registers
* in 64-bit mode, and also zeroes out any remaining
* bytes of the last register for lsw*.
*/
memset(rptr, 0, ((nb + 3) / 4) * sizeof(unsigned long));
if (nb0 > 0)
memset(&regs->gpr[0], 0,
((nb0 + 3) / 4) * sizeof(unsigned long));
for (i = 0; i < nb; ++i)
if (__get_user(REG_BYTE(rptr, i), addr + i))
return -EFAULT;
if (nb0 > 0) {
rptr = &regs->gpr[0];
addr += nb;
for (i = 0; i < nb0; ++i)
if (__get_user(REG_BYTE(rptr, i), addr + i))
return -EFAULT;
}
} else {
for (i = 0; i < nb; ++i)
if (__put_user(REG_BYTE(rptr, i), addr + i))
return -EFAULT;
if (nb0 > 0) {
rptr = &regs->gpr[0];
addr += nb;
for (i = 0; i < nb0; ++i)
if (__put_user(REG_BYTE(rptr, i), addr + i))
return -EFAULT;
}
}
return 1;
}
int
fix_alignment(struct pt_regs *regs)
/*
* Called on alignment exception. Attempts to fixup
*
* Return 1 on success
* Return 0 if unable to handle the interrupt
* Return -EFAULT if data address is bad
*/
int fix_alignment(struct pt_regs *regs)
{
unsigned int instr, nb, flags;
int t;
unsigned long reg, areg;
unsigned long i;
int ret;
unsigned dsisr;
unsigned int reg, areg;
unsigned int dsisr;
unsigned char __user *addr;
unsigned char __user *p;
unsigned long __user *lp;
int ret, t;
union {
long ll;
u64 ll;
double dd;
unsigned char v[8];
struct {
......@@ -231,17 +369,21 @@ fix_alignment(struct pt_regs *regs)
} data;
/*
* Return 1 on success
* Return 0 if unable to handle the interrupt
* Return -EFAULT if data address is bad
* We require a complete register set, if not, then our assembly
* is broken
*/
CHECK_FULL_REGS(regs);
dsisr = regs->dsisr;
/* Some processors don't provide us with a DSISR we can use here,
* let's make one up from the instruction
*/
if (cpu_has_feature(CPU_FTR_NODSISRALIGN)) {
unsigned int real_instr;
if (__get_user(real_instr, (unsigned int __user *)regs->nip))
return 0;
if (unlikely(__get_user(real_instr,
(unsigned int __user *)regs->nip)))
return -EFAULT;
dsisr = make_dsisr(real_instr);
}
......@@ -258,33 +400,37 @@ fix_alignment(struct pt_regs *regs)
/* DAR has the operand effective address */
addr = (unsigned char __user *)regs->dar;
/* A size of 0 indicates an instruction we don't support */
/* we also don't support the multiples (lmw, stmw, lmd, stmd) */
if ((nb == 0) || (flags & M))
return 0; /* too hard or invalid instruction */
/*
* Special handling for dcbz
* dcbz may give an alignment exception for accesses to caching inhibited
* storage
/* A size of 0 indicates an instruction we don't support, with
* the exception of DCBZ which is handled as a special case here
*/
if (instr == DCBZ)
addr = (unsigned char __user *) ((unsigned long)addr & -L1_CACHE_BYTES);
return emulate_dcbz(regs, addr);
if (unlikely(nb == 0))
return 0;
/* Load/Store Multiple instructions are handled in their own
* function
*/
if (flags & M)
return emulate_multiple(regs, addr, reg, nb, flags, instr);
/* Verify the address of the operand */
if (user_mode(regs)) {
if (!access_ok((flags & ST? VERIFY_WRITE: VERIFY_READ), addr, nb))
return -EFAULT; /* bad address */
}
if (unlikely(user_mode(regs) &&
!access_ok((flags & ST ? VERIFY_WRITE : VERIFY_READ),
addr, nb)))
return -EFAULT;
/* Force the fprs into the save area so we can reference them */
if (flags & F) {
if (!user_mode(regs))
/* userland only */
if (unlikely(!user_mode(regs)))
return 0;
flush_fp_to_thread(current);
}
/* If we are loading, get the data from user space */
/* If we are loading, get the data from user space, else
* get it from register values
*/
if (flags & LD) {
data.ll = 0;
ret = 0;
......@@ -301,75 +447,62 @@ fix_alignment(struct pt_regs *regs)
case 2:
ret |= __get_user(data.v[6], p++);
ret |= __get_user(data.v[7], p++);
if (ret)
if (unlikely(ret))
return -EFAULT;
}
}
/* If we are storing, get the data from the saved gpr or fpr */
if (flags & ST) {
if (flags & F) {
if (nb == 4) {
/* Doing stfs, have to convert to single */
preempt_disable();
enable_kernel_fp();
cvt_df(&current->thread.fpr[reg], (float *)&data.v[4], &current->thread);
disable_kernel_fp();
preempt_enable();
}
else
} else if (flags & F)
data.dd = current->thread.fpr[reg];
}
else
data.ll = regs->gpr[reg];
}
/* Swap bytes as needed */
if (flags & SW) {
if (nb == 2)
SWAP(data.v[6], data.v[7]);
else { /* nb must be 4 */
SWAP(data.v[4], data.v[7]);
SWAP(data.v[5], data.v[6]);
}
}
/* Sign extend as needed */
if (flags & SE) {
/* Perform other misc operations like sign extension, byteswap,
* or floating point single precision conversion
*/
switch (flags & ~U) {
case LD+SE: /* sign extend */
if ( nb == 2 )
data.ll = data.x16.low16;
else /* nb must be 4 */
data.ll = data.x32.low32;
break;
case LD+S: /* byte-swap */
case ST+S:
if (nb == 2) {
SWAP(data.v[6], data.v[7]);
} else {
SWAP(data.v[4], data.v[7]);
SWAP(data.v[5], data.v[6]);
}
break;
/* If we are loading, move the data to the gpr or fpr */
if (flags & LD) {
if (flags & F) {
if (nb == 4) {
/* Doing lfs, have to convert to double */
/* Single-precision FP load and store require conversions... */
case LD+F+S:
#ifdef CONFIG_PPC_FPU
preempt_disable();
enable_kernel_fp();
cvt_fd((float *)&data.v[4], &current->thread.fpr[reg], &current->thread);
disable_kernel_fp();
cvt_fd((float *)&data.v[4], &data.dd, &current->thread);
preempt_enable();
}
else
current->thread.fpr[reg] = data.dd;
}
else
regs->gpr[reg] = data.ll;
#else
return 0;
#endif
break;
case ST+F+S:
#ifdef CONFIG_PPC_FPU
preempt_disable();
enable_kernel_fp();
cvt_df(&data.dd, (float *)&data.v[4], &current->thread);
preempt_enable();
#else
return 0;
#endif
break;
}
/* If we are storing, copy the data to the user */
/* Store result to memory or update registers */
if (flags & ST) {
ret = 0;
p = addr;
switch (nb) {
case 128: /* Special case - must be dcbz */
lp = (unsigned long __user *)p;
for (i = 0; i < L1_CACHE_BYTES / sizeof(long); ++i)
ret |= __put_user(0, lp++);
break;
case 8:
ret |= __put_user(data.v[0], p++);
ret |= __put_user(data.v[1], p++);
......@@ -382,15 +515,16 @@ fix_alignment(struct pt_regs *regs)
ret |= __put_user(data.v[6], p++);
ret |= __put_user(data.v[7], p++);
}
if (ret)
if (unlikely(ret))
return -EFAULT;
}
} else if (flags & F)
current->thread.fpr[reg] = data.dd;
else
regs->gpr[reg] = data.ll;
/* Update RA as needed */
if (flags & U) {
if (flags & U)
regs->gpr[areg] = regs->dar;
}
return 1;
}
......@@ -27,14 +27,6 @@
.text
.align 5
_GLOBAL(__delay)
cmpwi 0,r3,0
mtctr r3
beqlr
1: bdnz 1b
blr
/*
* This returns the high 64 bits of the product of two 64-bit numbers.
*/
......
......@@ -15,7 +15,7 @@ unsigned long __init rtas_get_boot_time(void)
{
int ret[8];
int error, wait_time;
unsigned long max_wait_tb;
u64 max_wait_tb;
max_wait_tb = get_tb() + tb_ticks_per_usec * 1000 * MAX_RTC_WAIT;
do {
......@@ -45,7 +45,7 @@ void rtas_get_rtc_time(struct rtc_time *rtc_tm)
{
int ret[8];
int error, wait_time;
unsigned long max_wait_tb;
u64 max_wait_tb;
max_wait_tb = get_tb() + tb_ticks_per_usec * 1000 * MAX_RTC_WAIT;
do {
......@@ -80,7 +80,7 @@ void rtas_get_rtc_time(struct rtc_time *rtc_tm)
int rtas_set_rtc_time(struct rtc_time *tm)
{
int error, wait_time;
unsigned long max_wait_tb;
u64 max_wait_tb;
max_wait_tb = get_tb() + tb_ticks_per_usec * 1000 * MAX_RTC_WAIT;
do {
......
......@@ -130,6 +130,34 @@ unsigned long tb_last_stamp;
*/
DEFINE_PER_CPU(unsigned long, last_jiffy);
void __delay(unsigned long loops)
{
unsigned long start;
int diff;
if (__USE_RTC()) {
start = get_rtcl();
do {
/* the RTCL register wraps at 1000000000 */
diff = get_rtcl() - start;
if (diff < 0)
diff += 1000000000;
} while (diff < loops);
} else {
start = get_tbl();
while (get_tbl() - start < loops)
HMT_low();
HMT_medium();
}
}
EXPORT_SYMBOL(__delay);
void udelay(unsigned long usecs)
{
__delay(tb_ticks_per_usec * usecs);
}
EXPORT_SYMBOL(udelay);
static __inline__ void timer_check_rtc(void)
{
/*
......
......@@ -257,6 +257,13 @@ void __init chrp_setup_arch(void)
if (rtas_token("display-character") >= 0)
ppc_md.progress = rtas_progress;
/* use RTAS time-of-day routines if available */
if (rtas_token("get-time-of-day") != RTAS_UNKNOWN_SERVICE) {
ppc_md.get_boot_time = rtas_get_boot_time;
ppc_md.get_rtc_time = rtas_get_rtc_time;
ppc_md.set_rtc_time = rtas_set_rtc_time;
}
#ifdef CONFIG_BOOTX_TEXT
if (ppc_md.progress == NULL && boot_text_mapped)
ppc_md.progress = btext_progress;
......@@ -505,9 +512,11 @@ void __init chrp_init(void)
ppc_md.halt = rtas_halt;
ppc_md.time_init = chrp_time_init;
ppc_md.calibrate_decr = chrp_calibrate_decr;
/* this may get overridden with rtas routines later... */
ppc_md.set_rtc_time = chrp_set_rtc_time;
ppc_md.get_rtc_time = chrp_get_rtc_time;
ppc_md.calibrate_decr = chrp_calibrate_decr;
#ifdef CONFIG_SMP
smp_ops = &chrp_smp_ops;
......
......@@ -34,6 +34,7 @@
#include <asm/machdep.h>
#include <asm/smp.h>
#include <asm/mpic.h>
#include <asm/rtas.h>
static void __devinit smp_chrp_kick_cpu(int nr)
{
......
......@@ -87,7 +87,6 @@ int chrp_set_rtc_time(struct rtc_time *tmarg)
chrp_cmos_clock_write((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
tm.tm_year -= 1900;
if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
BIN_TO_BCD(tm.tm_sec);
BIN_TO_BCD(tm.tm_min);
......@@ -156,7 +155,7 @@ void chrp_get_rtc_time(struct rtc_time *tm)
BCD_TO_BIN(mon);
BCD_TO_BIN(year);
}
if ((year += 1900) < 1970)
if (year < 70)
year += 100;
tm->tm_sec = sec;
tm->tm_min = min;
......
......@@ -158,6 +158,11 @@ int maple_set_rtc_time(struct rtc_time *tm)
return 0;
}
static struct resource rtc_iores = {
.name = "rtc",
.flags = IORESOURCE_BUSY,
};
unsigned long __init maple_get_boot_time(void)
{
struct rtc_time tm;
......@@ -173,6 +178,10 @@ unsigned long __init maple_get_boot_time(void)
"legacy address (0x%x)\n", maple_rtc_addr);
}
rtc_iores.start = maple_rtc_addr;
rtc_iores.end = maple_rtc_addr + 7;
request_resource(&ioport_resource, &rtc_iores);
maple_get_rtc_time(&tm);
return mktime(tm.tm_year+1900, tm.tm_mon+1, tm.tm_mday,
tm.tm_hour, tm.tm_min, tm.tm_sec);
......
......@@ -86,7 +86,8 @@ static int ibm_read_slot_reset_state;
static int ibm_read_slot_reset_state2;
static int ibm_slot_error_detail;
static int eeh_subsystem_enabled;
int eeh_subsystem_enabled;
EXPORT_SYMBOL(eeh_subsystem_enabled);
/* Lock to avoid races due to multiple reports of an error */
static DEFINE_SPINLOCK(confirm_error_lock);
......
......@@ -504,7 +504,7 @@ static void pseries_dedicated_idle(void)
lpaca->lppaca.idle = 1;
if (!need_resched()) {
start_snooze = __get_tb() +
start_snooze = get_tb() +
*smt_snooze_delay * tb_ticks_per_usec;
while (!need_resched() && !cpu_is_offline(cpu)) {
......@@ -518,7 +518,7 @@ static void pseries_dedicated_idle(void)
HMT_very_low();
if (*smt_snooze_delay != 0 &&
__get_tb() > start_snooze) {
get_tb() > start_snooze) {
HMT_medium();
dedicated_idle_sleep(cpu);
}
......
......@@ -13,7 +13,7 @@ extra-$(CONFIG_POWER4) += idle_power4.o
extra-y += vmlinux.lds
obj-y := entry.o traps.o idle.o time.o misc.o \
process.o align.o \
process.o \
setup.o \
ppc_htab.o
obj-$(CONFIG_6xx) += l2cr.o cpu_setup_6xx.o
......@@ -38,7 +38,7 @@ endif
# These are here while we do the architecture merge
else
obj-y := idle.o align.o
obj-y := idle.o
obj-$(CONFIG_6xx) += l2cr.o cpu_setup_6xx.o
obj-$(CONFIG_SOFTWARE_SUSPEND) += swsusp.o
obj-$(CONFIG_MODULES) += module.o
......
/*
* align.c - handle alignment exceptions for the Power PC.
*
* Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
* Copyright (c) 1998-1999 TiVo, Inc.
* PowerPC 403GCX modifications.
* Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
* PowerPC 403GCX/405GP modifications.
*/
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <asm/ptrace.h>
#include <asm/processor.h>
#include <asm/uaccess.h>
#include <asm/system.h>
#include <asm/cache.h>
struct aligninfo {
unsigned char len;
unsigned char flags;
};
#if defined(CONFIG_4xx) || defined(CONFIG_POWER4) || defined(CONFIG_BOOKE)
#define OPCD(inst) (((inst) & 0xFC000000) >> 26)
#define RS(inst) (((inst) & 0x03E00000) >> 21)
#define RA(inst) (((inst) & 0x001F0000) >> 16)
#define IS_XFORM(code) ((code) == 31)
#endif
#define INVALID { 0, 0 }
#define LD 1 /* load */
#define ST 2 /* store */
#define SE 4 /* sign-extend value */
#define F 8 /* to/from fp regs */
#define U 0x10 /* update index register */
#define M 0x20 /* multiple load/store */
#define S 0x40 /* single-precision fp, or byte-swap value */
#define SX 0x40 /* byte count in XER */
#define HARD 0x80 /* string, stwcx. */
#define DCBZ 0x5f /* 8xx/82xx dcbz faults when cache not enabled */
/*
* The PowerPC stores certain bits of the instruction that caused the
* alignment exception in the DSISR register. This array maps those
* bits to information about the operand length and what the
* instruction would do.
*/
static struct aligninfo aligninfo[128] = {
{ 4, LD }, /* 00 0 0000: lwz / lwarx */
INVALID, /* 00 0 0001 */
{ 4, ST }, /* 00 0 0010: stw */
INVALID, /* 00 0 0011 */
{ 2, LD }, /* 00 0 0100: lhz */
{ 2, LD+SE }, /* 00 0 0101: lha */
{ 2, ST }, /* 00 0 0110: sth */
{ 4, LD+M }, /* 00 0 0111: lmw */
{ 4, LD+F+S }, /* 00 0 1000: lfs */
{ 8, LD+F }, /* 00 0 1001: lfd */
{ 4, ST+F+S }, /* 00 0 1010: stfs */
{ 8, ST+F }, /* 00 0 1011: stfd */
INVALID, /* 00 0 1100 */
INVALID, /* 00 0 1101: ld/ldu/lwa */
INVALID, /* 00 0 1110 */
INVALID, /* 00 0 1111: std/stdu */
{ 4, LD+U }, /* 00 1 0000: lwzu */
INVALID, /* 00 1 0001 */
{ 4, ST+U }, /* 00 1 0010: stwu */
INVALID, /* 00 1 0011 */
{ 2, LD+U }, /* 00 1 0100: lhzu */
{ 2, LD+SE+U }, /* 00 1 0101: lhau */
{ 2, ST+U }, /* 00 1 0110: sthu */
{ 4, ST+M }, /* 00 1 0111: stmw */
{ 4, LD+F+S+U }, /* 00 1 1000: lfsu */
{ 8, LD+F+U }, /* 00 1 1001: lfdu */
{ 4, ST+F+S+U }, /* 00 1 1010: stfsu */
{ 8, ST+F+U }, /* 00 1 1011: stfdu */
INVALID, /* 00 1 1100 */
INVALID, /* 00 1 1101 */
INVALID, /* 00 1 1110 */
INVALID, /* 00 1 1111 */
INVALID, /* 01 0 0000: ldx */
INVALID, /* 01 0 0001 */
INVALID, /* 01 0 0010: stdx */
INVALID, /* 01 0 0011 */
INVALID, /* 01 0 0100 */
INVALID, /* 01 0 0101: lwax */
INVALID, /* 01 0 0110 */
INVALID, /* 01 0 0111 */
{ 4, LD+M+HARD+SX }, /* 01 0 1000: lswx */
{ 4, LD+M+HARD }, /* 01 0 1001: lswi */
{ 4, ST+M+HARD+SX }, /* 01 0 1010: stswx */
{ 4, ST+M+HARD }, /* 01 0 1011: stswi */
INVALID, /* 01 0 1100 */
INVALID, /* 01 0 1101 */
INVALID, /* 01 0 1110 */
INVALID, /* 01 0 1111 */
INVALID, /* 01 1 0000: ldux */
INVALID, /* 01 1 0001 */
INVALID, /* 01 1 0010: stdux */
INVALID, /* 01 1 0011 */
INVALID, /* 01 1 0100 */
INVALID, /* 01 1 0101: lwaux */
INVALID, /* 01 1 0110 */
INVALID, /* 01 1 0111 */
INVALID, /* 01 1 1000 */
INVALID, /* 01 1 1001 */
INVALID, /* 01 1 1010 */
INVALID, /* 01 1 1011 */
INVALID, /* 01 1 1100 */
INVALID, /* 01 1 1101 */
INVALID, /* 01 1 1110 */
INVALID, /* 01 1 1111 */
INVALID, /* 10 0 0000 */
INVALID, /* 10 0 0001 */
{ 0, ST+HARD }, /* 10 0 0010: stwcx. */
INVALID, /* 10 0 0011 */
INVALID, /* 10 0 0100 */
INVALID, /* 10 0 0101 */
INVALID, /* 10 0 0110 */
INVALID, /* 10 0 0111 */
{ 4, LD+S }, /* 10 0 1000: lwbrx */
INVALID, /* 10 0 1001 */
{ 4, ST+S }, /* 10 0 1010: stwbrx */
INVALID, /* 10 0 1011 */
{ 2, LD+S }, /* 10 0 1100: lhbrx */
INVALID, /* 10 0 1101 */
{ 2, ST+S }, /* 10 0 1110: sthbrx */
INVALID, /* 10 0 1111 */
INVALID, /* 10 1 0000 */
INVALID, /* 10 1 0001 */
INVALID, /* 10 1 0010 */
INVALID, /* 10 1 0011 */
INVALID, /* 10 1 0100 */
INVALID, /* 10 1 0101 */
INVALID, /* 10 1 0110 */
INVALID, /* 10 1 0111 */
INVALID, /* 10 1 1000 */
INVALID, /* 10 1 1001 */
INVALID, /* 10 1 1010 */
INVALID, /* 10 1 1011 */
INVALID, /* 10 1 1100 */
INVALID, /* 10 1 1101 */
INVALID, /* 10 1 1110 */
{ 0, ST+HARD }, /* 10 1 1111: dcbz */
{ 4, LD }, /* 11 0 0000: lwzx */
INVALID, /* 11 0 0001 */
{ 4, ST }, /* 11 0 0010: stwx */
INVALID, /* 11 0 0011 */
{ 2, LD }, /* 11 0 0100: lhzx */
{ 2, LD+SE }, /* 11 0 0101: lhax */
{ 2, ST }, /* 11 0 0110: sthx */
INVALID, /* 11 0 0111 */
{ 4, LD+F+S }, /* 11 0 1000: lfsx */
{ 8, LD+F }, /* 11 0 1001: lfdx */
{ 4, ST+F+S }, /* 11 0 1010: stfsx */
{ 8, ST+F }, /* 11 0 1011: stfdx */
INVALID, /* 11 0 1100 */
INVALID, /* 11 0 1101: lmd */
INVALID, /* 11 0 1110 */
INVALID, /* 11 0 1111: stmd */
{ 4, LD+U }, /* 11 1 0000: lwzux */
INVALID, /* 11 1 0001 */
{ 4, ST+U }, /* 11 1 0010: stwux */
INVALID, /* 11 1 0011 */
{ 2, LD+U }, /* 11 1 0100: lhzux */
{ 2, LD+SE+U }, /* 11 1 0101: lhaux */
{ 2, ST+U }, /* 11 1 0110: sthux */
INVALID, /* 11 1 0111 */
{ 4, LD+F+S+U }, /* 11 1 1000: lfsux */
{ 8, LD+F+U }, /* 11 1 1001: lfdux */
{ 4, ST+F+S+U }, /* 11 1 1010: stfsux */
{ 8, ST+F+U }, /* 11 1 1011: stfdux */
INVALID, /* 11 1 1100 */
INVALID, /* 11 1 1101 */
INVALID, /* 11 1 1110 */
INVALID, /* 11 1 1111 */
};
#define SWAP(a, b) (t = (a), (a) = (b), (b) = t)
int
fix_alignment(struct pt_regs *regs)
{
int instr, nb, flags;
#if defined(CONFIG_4xx) || defined(CONFIG_POWER4) || defined(CONFIG_BOOKE)
int opcode, f1, f2, f3;
#endif
int i, t;
int reg, areg;
int offset, nb0;
unsigned char __user *addr;
unsigned char *rptr;
union {
long l;
float f;
double d;
unsigned char v[8];
} data;
CHECK_FULL_REGS(regs);
#if defined(CONFIG_4xx) || defined(CONFIG_POWER4) || defined(CONFIG_BOOKE)
/* The 4xx-family & Book-E processors have no DSISR register,
* so we emulate it.
* The POWER4 has a DSISR register but doesn't set it on
* an alignment fault. -- paulus
*/
if (__get_user(instr, (unsigned int __user *) regs->nip))
return 0;
opcode = OPCD(instr);
reg = RS(instr);
areg = RA(instr);
if (!IS_XFORM(opcode)) {
f1 = 0;
f2 = (instr & 0x04000000) >> 26;
f3 = (instr & 0x78000000) >> 27;
} else {
f1 = (instr & 0x00000006) >> 1;
f2 = (instr & 0x00000040) >> 6;
f3 = (instr & 0x00000780) >> 7;
}
instr = ((f1 << 5) | (f2 << 4) | f3);
#else
reg = (regs->dsisr >> 5) & 0x1f; /* source/dest register */
areg = regs->dsisr & 0x1f; /* register to update */
instr = (regs->dsisr >> 10) & 0x7f;
#endif
nb = aligninfo[instr].len;
if (nb == 0) {
long __user *p;
int i;
if (instr != DCBZ)
return 0; /* too hard or invalid instruction */
/*
* The dcbz (data cache block zero) instruction
* gives an alignment fault if used on non-cacheable
* memory. We handle the fault mainly for the
* case when we are running with the cache disabled
* for debugging.
*/
p = (long __user *) (regs->dar & -L1_CACHE_BYTES);
if (user_mode(regs)
&& !access_ok(VERIFY_WRITE, p, L1_CACHE_BYTES))
return -EFAULT;
for (i = 0; i < L1_CACHE_BYTES / sizeof(long); ++i)
if (__put_user(0, p+i))
return -EFAULT;
return 1;
}
flags = aligninfo[instr].flags;
if ((flags & (LD|ST)) == 0)
return 0;
/* For the 4xx-family & Book-E processors, the 'dar' field of the
* pt_regs structure is overloaded and is really from the DEAR.
*/
addr = (unsigned char __user *)regs->dar;
if (flags & M) {
/* lmw, stmw, lswi/x, stswi/x */
nb0 = 0;
if (flags & HARD) {
if (flags & SX) {
nb = regs->xer & 127;
if (nb == 0)
return 1;
} else {
if (__get_user(instr,
(unsigned int __user *)regs->nip))
return 0;
nb = (instr >> 11) & 0x1f;
if (nb == 0)
nb = 32;
}
if (nb + reg * 4 > 128) {
nb0 = nb + reg * 4 - 128;
nb = 128 - reg * 4;
}
} else {
/* lwm, stmw */
nb = (32 - reg) * 4;
}
if (!access_ok((flags & ST? VERIFY_WRITE: VERIFY_READ), addr, nb+nb0))
return -EFAULT; /* bad address */
rptr = (unsigned char *) &regs->gpr[reg];
if (flags & LD) {
for (i = 0; i < nb; ++i)
if (__get_user(rptr[i], addr+i))
return -EFAULT;
if (nb0 > 0) {
rptr = (unsigned char *) &regs->gpr[0];
addr += nb;
for (i = 0; i < nb0; ++i)
if (__get_user(rptr[i], addr+i))
return -EFAULT;
}
for (; (i & 3) != 0; ++i)
rptr[i] = 0;
} else {
for (i = 0; i < nb; ++i)
if (__put_user(rptr[i], addr+i))
return -EFAULT;
if (nb0 > 0) {
rptr = (unsigned char *) &regs->gpr[0];
addr += nb;
for (i = 0; i < nb0; ++i)
if (__put_user(rptr[i], addr+i))
return -EFAULT;
}
}
return 1;
}
offset = 0;
if (nb < 4) {
/* read/write the least significant bits */
data.l = 0;
offset = 4 - nb;
}
/* Verify the address of the operand */
if (user_mode(regs)) {
if (!access_ok((flags & ST? VERIFY_WRITE: VERIFY_READ), addr, nb))
return -EFAULT; /* bad address */
}
if (flags & F) {
preempt_disable();
if (regs->msr & MSR_FP)
giveup_fpu(current);
preempt_enable();
}
/* If we read the operand, copy it in, else get register values */
if (flags & LD) {
for (i = 0; i < nb; ++i)
if (__get_user(data.v[offset+i], addr+i))
return -EFAULT;
} else if (flags & F) {
data.d = current->thread.fpr[reg];
} else {
data.l = regs->gpr[reg];
}
switch (flags & ~U) {
case LD+SE: /* sign extend */
if (data.v[2] >= 0x80)
data.v[0] = data.v[1] = -1;
break;
case LD+S: /* byte-swap */
case ST+S:
if (nb == 2) {
SWAP(data.v[2], data.v[3]);
} else {
SWAP(data.v[0], data.v[3]);
SWAP(data.v[1], data.v[2]);
}
break;
/* Single-precision FP load and store require conversions... */
case LD+F+S:
#ifdef CONFIG_PPC_FPU
preempt_disable();
enable_kernel_fp();
cvt_fd(&data.f, &data.d, &current->thread);
preempt_enable();
#else
return 0;
#endif
break;
case ST+F+S:
#ifdef CONFIG_PPC_FPU
preempt_disable();
enable_kernel_fp();
cvt_df(&data.d, &data.f, &current->thread);
preempt_enable();
#else
return 0;
#endif
break;
}
if (flags & ST) {
for (i = 0; i < nb; ++i)
if (__put_user(data.v[offset+i], addr+i))
return -EFAULT;
} else if (flags & F) {
current->thread.fpr[reg] = data.d;
} else {
regs->gpr[reg] = data.l;
}
if (flags & U)
regs->gpr[areg] = regs->dar;
return 1;
}
......@@ -45,7 +45,6 @@ static void update_bridge_base(struct pci_bus *bus, int i);
static void pcibios_fixup_resources(struct pci_dev* dev);
static void fixup_broken_pcnet32(struct pci_dev* dev);
static int reparent_resources(struct resource *parent, struct resource *res);
static void fixup_rev1_53c810(struct pci_dev* dev);
static void fixup_cpc710_pci64(struct pci_dev* dev);
#ifdef CONFIG_PPC_OF
static u8* pci_to_OF_bus_map;
......
......@@ -69,9 +69,33 @@ struct ppc_sys_spec ppc_sys_specs[] = {
},
},
{
.ppc_sys_name = "8343E",
.ppc_sys_name = "8347E",
.mask = 0xFFFF0000,
.value = 0x80540000,
.num_devices = 9,
.device_list = (enum ppc_sys_devices[])
{
MPC83xx_TSEC1, MPC83xx_TSEC2, MPC83xx_IIC1,
MPC83xx_IIC2, MPC83xx_DUART, MPC83xx_SEC2,
MPC83xx_USB2_DR, MPC83xx_USB2_MPH, MPC83xx_MDIO
},
},
{
.ppc_sys_name = "8347",
.mask = 0xFFFF0000,
.value = 0x80550000,
.num_devices = 8,
.device_list = (enum ppc_sys_devices[])
{
MPC83xx_TSEC1, MPC83xx_TSEC2, MPC83xx_IIC1,
MPC83xx_IIC2, MPC83xx_DUART,
MPC83xx_USB2_DR, MPC83xx_USB2_MPH, MPC83xx_MDIO
},
},
{
.ppc_sys_name = "8343E",
.mask = 0xFFFF0000,
.value = 0x80560000,
.num_devices = 8,
.device_list = (enum ppc_sys_devices[])
{
......@@ -83,7 +107,7 @@ struct ppc_sys_spec ppc_sys_specs[] = {
{
.ppc_sys_name = "8343",
.mask = 0xFFFF0000,
.value = 0x80550000,
.value = 0x80570000,
.num_devices = 7,
.device_list = (enum ppc_sys_devices[])
{
......
menu "Kernel hacking"
source "lib/Kconfig.debug"
config DEBUG_STACKOVERFLOW
bool "Check for stack overflows"
depends on DEBUG_KERNEL
help
This option will cause messages to be printed if free stack space
drops below a certain limit.
config KPROBES
bool "Kprobes"
depends on DEBUG_KERNEL
help
Kprobes allows you to trap at almost any kernel address and
execute a callback function. register_kprobe() establishes
a probepoint and specifies the callback. Kprobes is useful
for kernel debugging, non-intrusive instrumentation and testing.
If in doubt, say "N".
config DEBUG_STACK_USAGE
bool "Stack utilization instrumentation"
depends on DEBUG_KERNEL
help
Enables the display of the minimum amount of free stack which each
task has ever had available in the sysrq-T and sysrq-P debug output.
This option will slow down process creation somewhat.
config DEBUGGER
bool "Enable debugger hooks"
depends on DEBUG_KERNEL
help
Include in-kernel hooks for kernel debuggers. Unless you are
intending to debug the kernel, say N here.
config XMON
bool "Include xmon kernel debugger"
depends on DEBUGGER && !PPC_ISERIES
help
Include in-kernel hooks for the xmon kernel monitor/debugger.
Unless you are intending to debug the kernel, say N here.
Make sure to enable also CONFIG_BOOTX_TEXT on Macs. Otherwise
nothing will appear on the screen (xmon writes directly to the
framebuffer memory).
The cmdline option 'xmon' or 'xmon=early' will drop into xmon very
early during boot. 'xmon=on' will just enable the xmon debugger hooks.
'xmon=off' will disable the debugger hooks if CONFIG_XMON_DEFAULT is set.
config XMON_DEFAULT
bool "Enable xmon by default"
depends on XMON
help
xmon is normally disabled unless booted with 'xmon=on'.
Use 'xmon=off' to disable xmon init during runtime.
config IRQSTACKS
bool "Use separate kernel stacks when processing interrupts"
help
If you say Y here the kernel will use separate kernel stacks
for handling hard and soft interrupts. This can help avoid
overflowing the process kernel stacks.
endmenu
# This file is included by the global makefile so that you can add your own
# architecture-specific flags and dependencies. Remember to do have actions
# for "archclean" and "archdep" for cleaning up and making dependencies for
# this architecture
#
# This file is subject to the terms and conditions of the GNU General Public
# License. See the file "COPYING" in the main directory of this archive
# for more details.
#
# Copyright (C) 1994 by Linus Torvalds
# Changes for PPC by Gary Thomas
# Rewritten by Cort Dougan and Paul Mackerras
# Adjusted for PPC64 by Tom Gall
#
KERNELLOAD := 0xc000000000000000
# Set default 32 bits cross compilers for vdso and boot wrapper
CROSS32_COMPILE ?=
CROSS32CC := $(CROSS32_COMPILE)gcc
CROSS32AS := $(CROSS32_COMPILE)as
CROSS32LD := $(CROSS32_COMPILE)ld
CROSS32OBJCOPY := $(CROSS32_COMPILE)objcopy
# If we have a biarch compiler, use it for 32 bits cross compile if
# CROSS32_COMPILE wasn't explicitely defined, and add proper explicit
# target type to target compilers
HAS_BIARCH := $(call cc-option-yn, -m64)
ifeq ($(HAS_BIARCH),y)
ifeq ($(CROSS32_COMPILE),)
CROSS32CC := $(CC) -m32
CROSS32AS := $(AS) -a32
CROSS32LD := $(LD) -m elf32ppc
CROSS32OBJCOPY := $(OBJCOPY)
endif
override AS += -a64
override LD += -m elf64ppc
override CC += -m64
endif
export CROSS32CC CROSS32AS CROSS32LD CROSS32OBJCOPY
new_nm := $(shell if $(NM) --help 2>&1 | grep -- '--synthetic' > /dev/null; then echo y; else echo n; fi)
ifeq ($(new_nm),y)
NM := $(NM) --synthetic
endif
CHECKFLAGS += -m64 -D__powerpc__ -D__powerpc64__
LDFLAGS := -m elf64ppc
LDFLAGS_vmlinux := -Bstatic -e $(KERNELLOAD) -Ttext $(KERNELLOAD)
CFLAGS += -msoft-float -pipe -mminimal-toc -mtraceback=none \
-mcall-aixdesc
# Temporary hack until we have migrated to asm-powerpc
CPPFLAGS += -Iarch/$(ARCH)/include
GCC_VERSION := $(call cc-version)
GCC_BROKEN_VEC := $(shell if [ $(GCC_VERSION) -lt 0400 ] ; then echo "y"; fi ;)
ifeq ($(CONFIG_POWER4_ONLY),y)
ifeq ($(CONFIG_ALTIVEC),y)
ifeq ($(GCC_BROKEN_VEC),y)
CFLAGS += $(call cc-option,-mcpu=970)
else
CFLAGS += $(call cc-option,-mcpu=power4)
endif
else
CFLAGS += $(call cc-option,-mcpu=power4)
endif
else
CFLAGS += $(call cc-option,-mtune=power4)
endif
# No AltiVec instruction when building kernel
CFLAGS += $(call cc-option, -mno-altivec)
# Enable unit-at-a-time mode when possible. It shrinks the
# kernel considerably.
CFLAGS += $(call cc-option,-funit-at-a-time)
head-y := arch/ppc64/kernel/head.o
head-y += arch/powerpc/kernel/fpu.o
head-y += arch/powerpc/kernel/entry_64.o
core-y += arch/ppc64/kernel/ arch/powerpc/kernel/
core-y += arch/powerpc/mm/
core-y += arch/powerpc/sysdev/
core-y += arch/powerpc/platforms/
core-y += arch/powerpc/lib/
core-$(CONFIG_XMON) += arch/powerpc/xmon/
drivers-$(CONFIG_OPROFILE) += arch/powerpc/oprofile/
boot := arch/ppc64/boot
boottargets-$(CONFIG_PPC_PSERIES) += zImage zImage.initrd
boottargets-$(CONFIG_PPC_PMAC) += zImage.vmode zImage.initrd.vmode
boottargets-$(CONFIG_PPC_MAPLE) += zImage zImage.initrd
boottargets-$(CONFIG_PPC_ISERIES) += vmlinux.sminitrd vmlinux.initrd vmlinux.sm
boottargets-$(CONFIG_PPC_BPA) += zImage zImage.initrd
$(boottargets-y): vmlinux
$(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
bootimage-$(CONFIG_PPC_PSERIES) := $(boot)/zImage
bootimage-$(CONFIG_PPC_PMAC) := vmlinux
bootimage-$(CONFIG_PPC_MAPLE) := $(boot)/zImage
bootimage-$(CONFIG_PPC_BPA) := $(boot)/zImage
bootimage-$(CONFIG_PPC_ISERIES) := vmlinux
BOOTIMAGE := $(bootimage-y)
install: vmlinux
$(Q)$(MAKE) $(build)=$(boot) BOOTIMAGE=$(BOOTIMAGE) $@
defaultimage-$(CONFIG_PPC_PSERIES) := zImage
defaultimage-$(CONFIG_PPC_PMAC) := zImage.vmode
defaultimage-$(CONFIG_PPC_MAPLE) := zImage
defaultimage-$(CONFIG_PPC_ISERIES) := vmlinux
KBUILD_IMAGE := $(defaultimage-y)
all: $(KBUILD_IMAGE)
archclean:
$(Q)$(MAKE) $(clean)=$(boot)
# Temporary hack until we have migrated to asm-powerpc
$(Q)rm -rf arch/$(ARCH)/include
# Temporary hack until we have migrated to asm-powerpc
include/asm: arch/$(ARCH)/include/asm
arch/$(ARCH)/include/asm:
$(Q)if [ ! -d arch/$(ARCH)/include ]; then mkdir -p arch/$(ARCH)/include; fi
$(Q)ln -fsn $(srctree)/include/asm-powerpc arch/$(ARCH)/include/asm
define archhelp
echo ' zImage.vmode - Compressed kernel image (arch/$(ARCH)/boot/zImage.vmode)'
echo ' zImage.initrd.vmode - Compressed kernel image with initrd attached,'
echo ' sourced from arch/$(ARCH)/boot/ramdisk.image.gz'
echo ' (arch/$(ARCH)/boot/zImage.initrd.vmode)'
echo ' zImage - zImage for pSeries machines'
echo ' zImage.initrd - zImage with initrd for pSeries machines'
endef
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#
# Makefile for the linux ppc64 kernel.
#
obj-y += idle.o align.o
obj-$(CONFIG_PPC_MULTIPLATFORM) += nvram.o
......@@ -26,6 +26,7 @@
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/pci.h>
#include <asm/io.h>
#include <asm/prom.h>
......@@ -325,8 +326,8 @@ static void __init offb_init_nodriver(struct device_node *dp)
int *pp, i;
unsigned int len;
int width = 640, height = 480, depth = 8, pitch;
unsigned *up;
unsigned long address;
unsigned int rsize, *up;
unsigned long address = 0;
if ((pp = (int *) get_property(dp, "depth", &len)) != NULL
&& len == sizeof(int))
......@@ -344,10 +345,40 @@ static void __init offb_init_nodriver(struct device_node *dp)
pitch = 0x1000;
} else
pitch = width;
if ((up = (unsigned *) get_property(dp, "address", &len)) != NULL
&& len == sizeof(unsigned))
rsize = (unsigned long)pitch * (unsigned long)height *
(unsigned long)(depth / 8);
/* Try to match device to a PCI device in order to get a properly
* translated address rather then trying to decode the open firmware
* stuff in various incorrect ways
*/
#ifdef CONFIG_PCI
/* First try to locate the PCI device if any */
{
struct pci_dev *pdev = NULL;
for_each_pci_dev(pdev) {
if (dp == pci_device_to_OF_node(pdev))
break;
}
if (pdev) {
for (i = 0; i < 6 && address == 0; i++) {
if ((pci_resource_flags(pdev, i) &
IORESOURCE_MEM) &&
(pci_resource_len(pdev, i) >= rsize))
address = pci_resource_start(pdev, i);
}
pci_dev_put(pdev);
}
}
#endif /* CONFIG_PCI */
if (address == 0 &&
(up = (unsigned *) get_property(dp, "address", &len)) != NULL &&
len == sizeof(unsigned))
address = (u_long) * up;
else {
if (address == 0) {
for (i = 0; i < dp->n_addrs; ++i)
if (dp->addrs[i].size >=
pitch * height * depth / 8)
......
......@@ -90,6 +90,7 @@ extern void do_cpu_ftr_fixups(unsigned long offset);
#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
#define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000)
#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000)
#ifdef __powerpc64__
/* Add the 64b processor unique features in the top half of the word */
......@@ -97,7 +98,6 @@ extern void do_cpu_ftr_fixups(unsigned long offset);
#define CPU_FTR_16M_PAGE ASM_CONST(0x0000000200000000)
#define CPU_FTR_TLBIEL ASM_CONST(0x0000000400000000)
#define CPU_FTR_NOEXECUTE ASM_CONST(0x0000000800000000)
#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000001000000000)
#define CPU_FTR_IABR ASM_CONST(0x0000002000000000)
#define CPU_FTR_MMCRA ASM_CONST(0x0000004000000000)
#define CPU_FTR_CTRL ASM_CONST(0x0000008000000000)
......@@ -113,7 +113,6 @@ extern void do_cpu_ftr_fixups(unsigned long offset);
#define CPU_FTR_16M_PAGE ASM_CONST(0x0)
#define CPU_FTR_TLBIEL ASM_CONST(0x0)
#define CPU_FTR_NOEXECUTE ASM_CONST(0x0)
#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0)
#define CPU_FTR_IABR ASM_CONST(0x0)
#define CPU_FTR_MMCRA ASM_CONST(0x0)
#define CPU_FTR_CTRL ASM_CONST(0x0)
......@@ -273,18 +272,21 @@ enum {
CPU_FTRS_POWER3_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
CPU_FTRS_POWER4_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_NODSISRALIGN,
CPU_FTRS_970_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_ALTIVEC_COMP |
CPU_FTR_MAYBE_CAN_NAP,
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN,
CPU_FTRS_8XX = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
CPU_FTRS_40X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
CPU_FTRS_44X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
CPU_FTRS_E200 = CPU_FTR_USE_TB,
CPU_FTRS_E500 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
CPU_FTRS_40X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
CPU_FTR_NODSISRALIGN,
CPU_FTRS_44X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
CPU_FTR_NODSISRALIGN,
CPU_FTRS_E200 = CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN,
CPU_FTRS_E500 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
CPU_FTR_NODSISRALIGN,
CPU_FTRS_E500_2 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
CPU_FTR_BIG_PHYS,
CPU_FTRS_GENERIC_32 = CPU_FTR_COMMON,
CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN,
CPU_FTRS_GENERIC_32 = CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN,
#ifdef __powerpc64__
CPU_FTRS_POWER3 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
CPU_FTR_HPTE_TABLE | CPU_FTR_IABR,
......
......@@ -13,43 +13,7 @@
* Anton Blanchard.
*/
extern unsigned long tb_ticks_per_usec;
#ifdef CONFIG_PPC64
/* define these here to prevent circular dependencies */
/* these instructions control the thread priority on multi-threaded cpus */
#define __HMT_low() asm volatile("or 1,1,1")
#define __HMT_medium() asm volatile("or 2,2,2")
#else
#define __HMT_low()
#define __HMT_medium()
#endif
#define __barrier() asm volatile("" ::: "memory")
static inline unsigned long __get_tb(void)
{
unsigned long rval;
asm volatile("mftb %0" : "=r" (rval));
return rval;
}
static inline void __delay(unsigned long loops)
{
unsigned long start = __get_tb();
while((__get_tb() - start) < loops)
__HMT_low();
__HMT_medium();
__barrier();
}
static inline void udelay(unsigned long usecs)
{
unsigned long loops = tb_ticks_per_usec * usecs;
__delay(loops);
}
extern void __delay(unsigned long loops);
extern void udelay(unsigned long usecs);
#endif /* _ASM_POWERPC_DELAY_H */
......@@ -30,6 +30,8 @@ struct device_node;
#ifdef CONFIG_EEH
extern int eeh_subsystem_enabled;
/* Values for eeh_mode bits in device_node */
#define EEH_MODE_SUPPORTED (1<<0)
#define EEH_MODE_NOCHECK (1<<1)
......@@ -75,7 +77,7 @@ void eeh_remove_device(struct pci_dev *);
* If this macro yields TRUE, the caller relays to eeh_check_failure()
* which does further tests out of line.
*/
#define EEH_POSSIBLE_ERROR(val, type) ((val) == (type)~0)
#define EEH_POSSIBLE_ERROR(val, type) ((val) == (type)~0 && eeh_subsystem_enabled)
/*
* Reads from a device which has been isolated by EEH will return
......
......@@ -41,6 +41,10 @@ static inline int node_to_first_cpu(int node)
.cache_hot_time = (10*1000000), \
.cache_nice_tries = 1, \
.per_cpu_gain = 100, \
.busy_idx = 3, \
.idle_idx = 1, \
.newidle_idx = 2, \
.wake_idx = 1, \
.flags = SD_LOAD_BALANCE \
| SD_BALANCE_EXEC \
| SD_BALANCE_NEWIDLE \
......
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