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提交 24c1d66a 编写于 作者: F fengsheng 提交者： Xie XiuQi
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sfc: optimize erase and write time 

driver inclusion
category: feature
bugzilla: NA
CVE: NA

optimize erase and write time
Signed-off-by: NFeng Sheng <fengsheng5@huawei.com>
Reviewed-by: Lin Siwei <linsiwei@huawei.com>a
Reviewed-by: NYang Yingliang <yangyingliang@huawei.com>
Signed-off-by: NYang Yingliang <yangyingliang@huawei.com>
上级 32c67b0e
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Showing with 922 addition and 1124 deletion
drivers/mtd/hisilicon/sfc/hrdCommon.h
浏览文件 @ 24c1d66a
......@@ -39,44 +39,42 @@
#define HRD_COMMON_ERR_NOT_ENOUGH_RES (int)(HRD_COMMON_ERR_BASE - 12)
#define HRD_COMMON_ERR_RES_NOT_EXIST (int)(HRD_COMMON_ERR_BASE - 13)
/* Swap tool */
/* 16bit nibble swap. For example 0x1234 -> 0x2143 */
/* 16 bit nibble swap. example 0x1234 -> 0x2143 */
#define HRD_NIBBLE_SWAP_16BIT(X) (((X&0xf) << 4) | \
((X&0xf0) >> 4) | \
((X&0xf00) << 4) | \
((X&0xf000) >> 4))
/* 32bit nibble swap. For example 0x12345678 -> 0x21436587 */
#define HRD_NIBBLE_SWAP_32BIT(X) (((X&0xf) << 4) | \
((X&0xf0) >> 4) | \
((X&0xf00) << 4) | \
((X&0xf000) >> 4) | \
((X&0xf0000) << 4) | \
((X&0xf00000) >> 4) | \
((X&0xf000000) << 4) | \
((X&0xf0000000) >> 4))
/* 16bit byte swap. For example 0x1234->0x3412 */
#define HRD_BYTE_SWAP_16BIT(X) ((((X)&0xff)<<8) | (((X)&0xff00)>>8))
/* 32bit byte swap. For example 0x12345678->0x78563412 */
#define HRD_BYTE_SWAP_32BIT(X) ((((X)&0xff)<<24) | \
(((X)&0xff00)<<8) | \
(((X)&0xff0000)>>8) | \
(((X)&0xff000000)>>24))
/* 64bit byte swap. For example 0x11223344.55667788 -> 0x88776655.44332211 */
#define HRD_BYTE_SWAP_64BIT(X) ((l64) ((((X)&0xffULL)<<56) | \
(((X)&0xff00ULL)<<40) | \
(((X)&0xff0000ULL)<<24) | \
(((X)&0xff000000ULL)<<8) | \
(((X)&0xff00000000ULL)>>8) | \
(((X)&0xff0000000000ULL)>>24) | \
(((X)&0xff000000000000ULL)>>40) | \
(((X)&0xff00000000000000ULL)>>56)))
/* Endianess macros. */
((X&0xF0) >> 4) | \
((X&0xF00) << 4) | \
((X&0xF000) >> 4))
/*32 bit nibble swap. example 0x12345678 -> 0x21436587 */
#define HRD_NIBBLE_SWAP_32BIT(X) (((X&0xF) << 4) | \
((X&0xF0) >> 4) | \
((X&0xF00) << 4) | \
((X&0xF000) >> 4) | \
((X&0xF0000) << 4) | \
((X&0xF00000) >> 4) | \
((X&0xF000000) << 4) | \
((X&0xF0000000) >> 4))
/* 16 bit byte swap. example 0x1234->0x3412 */
#define HRD_BYTE_SWAP_16BIT(X) ((((X)&0xFF)<<8) | (((X)&0xFF00)>>8))
/* 32 bit byte swap. example 0x12345678->0x78563412 */
#define HRD_BYTE_SWAP_32BIT(X) ((((X)&0xFF)<<24) | \
(((X)&0xFF00)<<8) | \
(((X)&0xFF0000)>>8) | \
(((X)&0xFF000000)>>24))
/* 64 bit byte swap. example 0x11223344.55667788 -> 0x88776655.44332211 */
#define HRD_BYTE_SWAP_64BIT(X) ((l64) ((((X)&0xFFULL)<<56) | \
(((X)&0xFF00ULL)<<40) | \
(((X)&0xFF0000ULL)<<24) | \
(((X)&0xFF000000ULL)<<8) | \
(((X)&0xFF00000000ULL)>>8) | \
(((X)&0xFF0000000000ULL)>>24) | \
(((X)&0xFF000000000000ULL)>>40) | \
(((X)&0xFF00000000000000ULL)>>56)))
/* -- Endianess macros. */
#ifdef HRD_ENDNESS_BIGEND
#define HRD_16BIT_LE(X) HRD_BYTE_SWAP_16BIT(X)
#define HRD_32BIT_LE(X) HRD_BYTE_SWAP_32BIT(X)
......
drivers/mtd/hisilicon/sfc/hrd_sfc_driver.c
浏览文件 @ 24c1d66a
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 Hisilicon Limited, All Rights Reserved.
*
......@@ -29,6 +29,8 @@
#include "hrd_sflash_driver.h"
#include "hrd_sflash_hal.h"
#define SFC_DRIVER_VERSION "1.7.8.0"
static const char *sflashMtdList[] = { "sflash", NULL };
static unsigned int hrd_flash_info_fill(struct maps_init_info *maps,
......@@ -37,8 +39,7 @@ static unsigned int hrd_flash_info_fill(struct maps_init_info *maps,
{
u32 i;
/* clear the whole array */
memset((void *)maps, 0x0, sizeof(maps));
memset((void *)maps, 0x0, sizeof(struct maps_init_info)*MTD_MAX_FLASH_NUMBER);
for (i = 0; i < MTD_MAX_FLASH_NUMBER; i++) {
maps[i].mtdDrv = sflashMtdList;
......@@ -46,18 +47,18 @@ static unsigned int hrd_flash_info_fill(struct maps_init_info *maps,
maps[i].mapInfo.phys = flash_iores->start;
maps[i].mapInfo.size = resource_size(flash_iores);
maps[i].mapInfo.bankwidth = 8;
DB(pr_info("i is 0x%x, phys 0x%llx,size 0x%lx\n",
DB(pr_info("[SFC] i is 0x%x, phys 0x%llx,size 0x%lx\n",
(u32) i, maps[i].mapInfo.phys,
maps[i].mapInfo.size));
DB(pr_info("\nINFO: Found %s %d - base 0x%08x, size 0x%x",
DB(pr_info("[SFC] INFO: Found %s %d - base 0x%08x, size 0x%x\n",
maps[i].mapInfo.name, i,
(unsigned int)maps[i].mapInfo.phys,
(unsigned int)maps[i].mapInfo.size));
}
DB(pr_info("\nINFO: %s - Found %d Flash Devices", __func__, i));
DB(pr_info("[SFC] INFO: %s - Found %d Flash Devices\n", __func__, i));
return i;
}
......@@ -68,26 +69,24 @@ static int __init hrd_flashProbe(const char **mtdDrv, struct map_info *map,
if ((mtdDrv == NULL)
|| (map == NULL)
|| (mtd == NULL)) {
pr_err("\nERROR: NULL pointer parameter at %s entry", __func__);
pr_err("[SFC] ERROR: NULL pointer parameter at %s entry\n", __func__);
return -EINVAL;
}
/* remap the physical address to a virtual address */
map->virt = ioremap(map->phys, map->size);
if (!map->virt) {
pr_err("\nFailed ioremap Flash device at base 0x%x.",
pr_err("[SFC] Failed ioremap Flash device at base 0x%x.\n",
(unsigned int)map->phys);
return -EIO;
}
DB(pr_info
("\nIo remapped ok.phy addr:0x%llx, virt addr:0x%llx",
("[SFC] Io remapped ok.phy addr:0x%llx, virt addr:0x%llx\n",
(u64) map->phys, (u64) map->virt));
/* Skip bankwidths that are not supported */
if (!map_bankwidth_supported(map->bankwidth)) {
pr_err("\nERROR: bankwidth %d not supported.",
pr_err("[SFC] ERROR: bankwidth %d not supported.\n",
(unsigned int)map->bankwidth);
iounmap((void *)map->virt);
return -EIO;
......@@ -97,20 +96,19 @@ static int __init hrd_flashProbe(const char **mtdDrv, struct map_info *map,
for (; (!(*mtd) && *mtdDrv); mtdDrv++) {
DB(pr_info
("\nUsing %s probe %s at addr 0x%llx,size 0x%x, width %dm",
("[SFC] Using %s probe %s at addr 0x%llx,size 0x%x, width %dm\n",
*mtdDrv, map->name, (u64) map->phys,
(unsigned int)map->size, map->bankwidth));
*mtd = sflash_probe(map, sfc_regres);
if (*mtd) {
DB(pr_info(" - detected OK"));
/*map->size = (*mtd)->size; */
DB(pr_info(" - detected OK\n"));
(*mtd)->owner = THIS_MODULE;
if (mtd_device_register(*mtd, NULL, 0)) {
pr_err
("\nERROR: %s - Failed to add the mtd device",
("[SFC] ERROR: %s - Failed to add the mtd device\n",
__func__);
iounmap((void *)map->virt);
map->virt = 0;
......@@ -119,13 +117,13 @@ static int __init hrd_flashProbe(const char **mtdDrv, struct map_info *map,
return 0;
} else {
DB(pr_info(" - Not detected"));
DB(pr_info("[SFC] - Not detected\n"));
}
}
iounmap((void *)map->virt);
map->virt = 0;
pr_err("\nERROR: %s - probe failed", __func__);
pr_err("[SFC] ERROR: %s - probe failed\n", __func__);
return -ENXIO;
}
......@@ -139,43 +137,43 @@ static unsigned int flash_map_init(struct platform_device *pdev)
struct resource *flash_iores;
struct sfc_host *host;
pr_info("SFC Driver V0.11");
pr_info("SFC Driver\n");
host = devm_kzalloc(dev, sizeof(struct sfc_host), GFP_KERNEL);
if (!host)
if (!host) {
pr_err("[SFC] ERROR: %s devm_kzalloc failed\n", __func__);
return -ENOMEM;
}
sfc_regres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
flash_iores = platform_get_resource(pdev, IORESOURCE_MEM, 1);
if (sfc_regres->end <= sfc_regres->start) {
pr_info("\nERROR: %s - sfc register error\r\n", __func__);
pr_err("ERROR: sfc register error\n");
return -EFAULT;
}
if (flash_iores->end <= flash_iores->start) {
pr_info("\nERROR: %s - sflash addr error\r\n", __func__);
pr_err("[SFC] ERROR: flash addr error\n");
return -EFAULT;
}
mapsNum = hrd_flash_info_fill(host->maps, flash_iores, pdev);
DB(pr_info
("\nINFO: hrd_flash_info_fill - DEtected %d devices\n", mapsNum));
("[SFC] INFO: DEtected %d devices\n", mapsNum));
for (i = 0; i < mapsNum; i++) {
DB(pr_info
("MTD: Initialize the %s device at address 0x%08x\n",
("[SFC] MTD: Initialize the %s device at address 0x%08x\n",
host->maps[i].mapInfo.name,
(unsigned int)host->maps[i].mapInfo.phys));
if (hrd_flashProbe
(host->maps[i].mtdDrv, &host->maps[i].mapInfo, sfc_regres,
&host->maps[i].mtdInfo) == 0) {
DB(pr_info(" - OK.\n"));
DB(pr_info("[SFC]- OK.\n"));
} else {
host->maps[i].mtdInfo = NULL;
DB(pr_err(" - FAILED!\n"));
DB(pr_err(" [SFC]- FAILED!\n"));
}
}
......@@ -203,8 +201,10 @@ static void __exit flash_map_exit(struct platform_device *pdev)
host->maps[i].mapInfo.virt = 0;
}
if (host->maps[i].mtdInfo) {
sflash_destroy(host->maps[i].mtdInfo);
}
}
}
......@@ -243,4 +243,4 @@ module_platform_driver(hisi_sfc_driver);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
MODULE_DESCRIPTION("Hi16xx SFC driver");
MODULE_VERSION("1.07");
MODULE_VERSION(SFC_DRIVER_VERSION);
drivers/mtd/hisilicon/sfc/hrd_sflash_driver.c
浏览文件 @ 24c1d66a
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 Hisilicon Limited, All Rights Reserved.
*
......@@ -78,23 +78,16 @@ struct mtd_info *sflash_probe(struct map_info *map, struct resource *sfc_regres)
struct SFC_SFLASH_INFO *sflash;
unsigned long flags = 0, sflash_in_irq = 0;
DB_LOCAL(pr_info("\nINFO: entering %s", __func__));
DB_LOCAL(pr_info("[SFC] INFO: entering %s\n", __func__));
mtd = kmalloc(sizeof(*mtd), GFP_KERNEL);
if (!mtd) {
pr_err(KERN_NOTICE
"\nERROR: %s - Failed to allocate memory for mtd structure",
__func__);
pr_err("ERROR: %s - Failed to allocate memory for mtd structure\n", __func__);
return NULL;
}
sflash = kmalloc(sizeof(struct SFC_SFLASH_INFO), GFP_KERNEL);
if (!sflash) {
pr_err(KERN_NOTICE
"\nERROR: %s - Failed to allocate memory for sflash structure",
__func__);
pr_err("[SFC] ERROR: %s - Failed to allocate memory for sflash structure\n", __func__);
kfree(mtd);
return NULL;
}
......@@ -103,13 +96,10 @@ struct mtd_info *sflash_probe(struct map_info *map, struct resource *sfc_regres)
memset(sflash, 0, sizeof(*sflash));
DB_LOCAL(pr_info
("\nINFO: %s - Base address %llx\n", __func__, map->phys));
("[SFC] INFO: %s - Base address %llx\n", __func__, map->phys));
sflash->baseAddr = (u64) ioremap(map->phys, map->size);
if (!sflash->baseAddr) {
pr_err(KERN_NOTICE
"\nERROR: %s - map flash error\r\n", __func__);
pr_err("[SFC] ERROR: %s - map flash error\n", __func__);
goto exit0;
}
......@@ -117,27 +107,22 @@ struct mtd_info *sflash_probe(struct map_info *map, struct resource *sfc_regres)
(u64) ioremap_nocache(sfc_regres->start, resource_size(sfc_regres));
if (!sflash->sfc_reg_base) {
pr_err(KERN_NOTICE
"\nERROR: %s - map register error\r\n", __func__);
pr_err("[SFC] ERROR: %s - map register error\n", __func__);
goto exit1;
}
mutex_init(&sflash->lock);
sflash->index = INVALID_DEVICE_NUMBER; /* will be detected in init */
sflash->index = INVALID_DEVICE_NUMBER;
sflash_disable_irqs(flags, sflash_in_irq);
if (hrd_sflash_init(sflash) != HRD_OK) {
sflash_enable_irqs(flags, sflash_in_irq);
pr_err(KERN_NOTICE
"ERROR: %s - Failed to initialize the SFlash.",
__func__);
pr_err("[SFC] ERROR: %s - Failed to initialize the SFlash.\n", __func__);
goto exit2;
}
sflash_enable_irqs(flags, sflash_in_irq);
mtd->erasesize = sflash->sectorSize;
mtd->size = (u64) sflash->sectorSize * (u64) sflash->sectorNumber;
mtd->priv = map;
......@@ -160,21 +145,21 @@ struct mtd_info *sflash_probe(struct map_info *map, struct resource *sfc_regres)
map->fldrv_priv = sflash;
DB_LOCAL(pr_info
("\nINFO: %s - Detected SFlash device (size 0x%llx)", __func__,
("[SFC] INFO: %s - Detected SFlash device (size 0x%llx)\n", __func__,
mtd->size));
DB_LOCAL(pr_info
("\n Base Address : 0x%llx", sflash->baseAddr));
("[SFC] Base Address : 0x%llx\n", sflash->baseAddr));
DB_LOCAL(pr_info
("\n Manufacturer ID : 0x%02x",
("[SFC] Manufacturer ID : 0x%02x\n",
sflash->manufacturerId));
DB_LOCAL(pr_info
("\n Device ID : 0x%04x", sflash->deviceId));
("[SFC] Device ID : 0x%04x\n", sflash->deviceId));
DB_LOCAL(pr_info
("\n Sector Size : 0x%x", sflash->sectorSize));
("[SFC] Sector Size : 0x%x\n", sflash->sectorSize));
DB_LOCAL(pr_info
("\n Sector Number : %d", sflash->sectorNumber));
("[SFC] Sector Number : %d\n", sflash->sectorNumber));
pr_info("SPI Serial flash detected @ 0x%08llx, %dKB (%dsec x %dKB)\n",
pr_info("[SFC] detected @ 0x%08llx, %dKB (%dsec x %dKB)\n",
sflash->baseAddr,
((sflash->sectorNumber * sflash->sectorSize) / 1024),
sflash->sectorNumber, (sflash->sectorSize / 1024));
......@@ -204,7 +189,7 @@ void sflash_destroy(struct mtd_info *mtd)
struct map_info *map = mtd->priv;
struct SFC_SFLASH_INFO *sflash = map->fldrv_priv;
DB_LOCAL(pr_info("\nINFO: %s called", __func__));
DB_LOCAL(pr_info("[SFC] INFO: %s called\n", __func__));
if (sflash->baseAddr != 0)
iounmap((void *)sflash->baseAddr);
......@@ -227,7 +212,7 @@ static int sflash_read(struct mtd_info *mtd, loff_t from, size_t len,
*retlen = 0;
DB_LOCAL(pr_info
("\nINFO: %s - offset %08x, len %d", __func__, offset,
("[SFC] INFO: %s - offset %08x, len %d\n", __func__, offset,
(int)len));
mutex_lock(&sflash->lock);
......@@ -237,12 +222,8 @@ static int sflash_read(struct mtd_info *mtd, loff_t from, size_t len,
ret = SFC_RegModeRead(sflash, offset, (u8 *) buf, (u32) len);
break;
case SFC_BUS_RW_MODE:
ret = SFC_BusModeRead(sflash, offset, (u8 *) buf, (u32) len);
break;
default:
pr_err(KERN_NOTICE "\nERROR: %s - rw mode error", __func__);
pr_err("[SFC] ERROR: %s - rw mode error\n", __func__);
ret = -1;
}
......@@ -250,16 +231,14 @@ static int sflash_read(struct mtd_info *mtd, loff_t from, size_t len,
if (ret != HRD_OK) {
mutex_unlock(&sflash->lock);
pr_err(KERN_NOTICE "\nERROR: %s - Failed to read block",
__func__);
pr_err("[SFC] ERROR: %s - Failed to read block\n", __func__);
return -1;
}
mutex_unlock(&sflash->lock);
*retlen = len;
DB_LOCAL(pr_info(" - OK"));
DB_LOCAL(pr_info(" [SFC] - OK\n"));
return 0;
}
......@@ -273,7 +252,7 @@ static int sflash_write(struct mtd_info *mtd, loff_t to, size_t len,
*retlen = 0;
DB_LOCAL(pr_info("\nINFO: %s-offset %08x, len %d",
DB_LOCAL(pr_info("[SFC] INFO: %s-offset %08x, len %d\n",
__func__, offset, (u32) len));
mutex_lock(&sflash->lock);
......@@ -282,20 +261,15 @@ static int sflash_write(struct mtd_info *mtd, loff_t to, size_t len,
case SFC_REGISTER_RW_MODE:
ret = SFC_RegModeWrite(sflash, offset, buf, (u32) len);
break;
case SFC_BUS_RW_MODE:
ret = SFC_BusModeWrite(sflash, offset, buf, (u32) len);
break;
default:
pr_err(KERN_NOTICE "\nERROR: %s - rw mode error", __func__);
pr_err("[SFC] ERROR: %s - rw mode error\n", __func__);
ret = -1;
}
if (ret != HRD_OK) {
mutex_unlock(&sflash->lock);
pr_err(KERN_NOTICE "\nERROR: %s - Failed to write block",
pr_err("[SFC] ERROR: %s - Failed to write block\n",
__func__);
return -1;
}
......@@ -304,7 +278,7 @@ static int sflash_write(struct mtd_info *mtd, loff_t to, size_t len,
*retlen = len;
DB_LOCAL(pr_info(" - OK"));
DB_LOCAL(pr_info("[SFC] - OK"));
return 0;
}
......@@ -319,37 +293,31 @@ static int sflash_erase(struct mtd_info *mtd, struct erase_info *instr)
u64 i;
DB_LOCAL(pr_info
("\nINFO: %s - Addr %08llx, len %lld", __func__, instr->addr,
("[SFC] INFO: %s - Addr %08llx, len %lld\n", __func__, instr->addr,
instr->len));
if (!sflash) {
pr_err("\nError: sflash is NULL");
pr_err("[SFC] Error: sflash is NULL\n");
return -EINVAL;
}
if (instr->addr & (mtd->erasesize - 1)) {
pr_err("\nError: %s - Erase address not sector alligned",
pr_err("[SFC] Error: %s - Erase address not sector alligned\n",
__func__);
return -EINVAL;
}
if (instr->len & (mtd->erasesize - 1)) {
pr_err("\nError: %s - Erase length is not sector alligned",
pr_err("[SFC] Error: %s - Erase length is not sector alligned\n",
__func__);
return -EINVAL;
}
if (instr->len + instr->addr > mtd->size) {
pr_err("\nError: %s - Erase exceeded flash size", __func__);
pr_err("[SFC] Error: %s - Erase exceeded flash size\n", __func__);
return -EINVAL;
}
if (0 != SFC_ControllerAddrModeSet(sflash)) {
pr_err("\nError: %s - SFC_ControllerAddrModeSet %d failed",
__func__, sflash->addr_mode);
return -1;
}
{
fsec = instr->addr;
do_div(fsec, 4 * 1024);
......@@ -357,10 +325,12 @@ static int sflash_erase(struct mtd_info *mtd, struct erase_info *instr)
do_div(lsec, 4 * 1024);
if (fsec < lsec) {
pr_info("\nINFO: %s - for 4K from sector %lld to %lld",
pr_info("[SFC] INFO: %s - for 4K from sector %lld to %lld\n",
__func__, fsec, lsec - 1);
mutex_lock(&sflash->lock);
SFC_CheckErr(sflash);
for (i = fsec; i < lsec; i++) {
if (SFC_BlockErase
(sflash, ((u32) i) * 0x1000,
......@@ -368,7 +338,7 @@ static int sflash_erase(struct mtd_info *mtd, struct erase_info *instr)
mutex_unlock(&sflash->lock);
pr_err
("\nError: %s - mvSFlashSectorErase on sector %lld",
("[SFC] Error: %s - mvSFlashSectorErase on sector %lld\n",
__func__, i);
return -1;
}
......@@ -384,7 +354,7 @@ static int sflash_erase(struct mtd_info *mtd, struct erase_info *instr)
do_div(lsec, mtd->erasesize);
lsec = (fsec + lsec);
DB_LOCAL(pr_info("\nINFO: %s - from sector %u to %u", __func__, fsec,
DB_LOCAL(pr_info("[SFC] INFO: %s - from sector %u to %u\n", __func__, fsec,
lsec - 1));
mutex_lock(&sflash->lock);
......@@ -395,7 +365,7 @@ static int sflash_erase(struct mtd_info *mtd, struct erase_info *instr)
mutex_unlock(&sflash->lock);
pr_err
("\nError: %s - mvSFlashSectorErase on sector %lld",
("[SFC] Error: %s - mvSFlashSectorErase on sector %lld\n",
__func__, i);
#if LINUX_VERSION_CODE > KERNEL_VERSION(4, 16, 0)
instr->fail_addr = ((u32) i) * mtd->erasesize;
......@@ -421,7 +391,7 @@ static int sflash_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
struct map_info *map = mtd->priv;
struct SFC_SFLASH_INFO *sflash = map->fldrv_priv;
DB_LOCAL(pr_info("\nINFO: %s called", __func__));
DB_LOCAL(pr_info("[SFC] INFO: %s called\n", __func__));
mutex_lock(&sflash->lock);
ret = SFC_WPSet(sflash, 1);
......@@ -436,7 +406,7 @@ static int sflash_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
struct map_info *map = mtd->priv;
struct SFC_SFLASH_INFO *sflash = map->fldrv_priv;
pr_info("\nINFO: %s called", __func__);
pr_info("[SFC] INFO: %s called\n", __func__);
mutex_lock(&sflash->lock);
ret = SFC_WPSet(sflash, 0);
......@@ -447,28 +417,28 @@ static int sflash_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
static void sflash_sync(struct mtd_info *mtd)
{
DB_LOCAL(pr_info("\nINFO: %s called - DUMMY", __func__));
DB_LOCAL(pr_info("[SFC] INFO: %s called - DUMMY\n", __func__));
}
static int sflash_suspend(struct mtd_info *mtd)
{
DB_LOCAL(pr_info("\nINFO: %s called - DUMMY()", __func__));
DB_LOCAL(pr_info("[SFC] INFO: %s called - DUMMY()\n", __func__));
return 0;
}
static void sflash_resume(struct mtd_info *mtd)
{
DB_LOCAL(pr_info("\nINFO: %s called - DUMMY", __func__));
DB_LOCAL(pr_info("[SFC] INFO: %s called - DUMMY\n", __func__));
}
static int sflash_block_isbad(struct mtd_info *mtd, loff_t ofs)
{
DB_LOCAL(pr_info("\nINFO: %s called - DUMMY", __func__));
DB_LOCAL(pr_info("[SFC] INFO: %s called - DUMMY\n", __func__));
return 0;
}
static int sflash_block_markbad(struct mtd_info *mtd, loff_t ofs)
{
DB_LOCAL(pr_info("\nINFO: %s called - DUMMY", __func__));
DB_LOCAL(pr_info("[SFC] INFO: %s called - DUMMY\n", __func__));
return 0;
}
drivers/mtd/hisilicon/sfc/hrd_sflash_hal.c
浏览文件 @ 24c1d66a
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 Hisilicon Limited, All Rights Reserved.
*
......@@ -33,7 +33,6 @@
#include "hrd_sflash_driver.h"
#include "hrd_sflash_hal.h"
#include "hrd_sflash_spec.h"
#include "lbc.h"
#define CPLD_WP_REG (0x13)
#define BIT0 (1<<0)
......@@ -46,619 +45,619 @@
struct SPI_FLASH_DEVICE_PARAMS g_stSPIFlashDevTable[] = {
/* NUMONYX N25Q128 SPI flash, 16MB, 256 sectors of 64K each */
{
MV_N25Q_WREN_CMND_OPCD,
MV_N25Q_WRDI_CMND_OPCD,
MV_N25Q_RDID_CMND_OPCD,
MV_N25Q_RDSR_CMND_OPCD,
MV_N25Q_WRSR_CMND_OPCD,
MV_N25Q_READ_CMND_OPCD,
MV_N25Q_FAST_RD_CMND_OPCD,
MV_N25Q_PP_CMND_OPCD,
MV_N25Q_SSE_CMND_OPCD,
MV_N25Q_SE_CMND_OPCD,
MV_N25Q_BE_CMND_OPCD,
MV_SFLASH_NO_SPECIFIC_OPCD,
MV_SFLASH_NO_SPECIFIC_OPCD,
MV_N25Q_RDVECR_CMND_OPCD,
MV_N25Q_WRVECR_CMND_OPCD,
MV_N25Q_EN4BADDR_CMND_OPCD,
MV_N25Q_EX4BADDR_CMND_OPCD,
MV_N25Q_BUSY_FLAG_BIT,
HISI_N25Q_WREN_CMND_OPCD,
HISI_N25Q_WRDI_CMND_OPCD,
HISI_N25Q_RDID_CMND_OPCD,
HISI_N25Q_RDSR_CMND_OPCD,
HISI_N25Q_WRSR_CMND_OPCD,
HISI_N25Q_READ_CMND_OPCD,
HISI_N25Q_FAST_RD_CMND_OPCD,
HISI_N25Q_PP_CMND_OPCD,
HISI_N25Q_SSE_CMND_OPCD,
HISI_N25Q_SE_CMND_OPCD,
HISI_N25Q_BE_CMND_OPCD,
HISI_SFLASH_NO_SPECIFIC_OPCD,
HISI_SFLASH_NO_SPECIFIC_OPCD,
HISI_N25Q_RDVECR_CMND_OPCD,
HISI_N25Q_WRVECR_CMND_OPCD,
HISI_N25Q_EN4BADDR_CMND_OPCD,
HISI_N25Q_EX4BADDR_CMND_OPCD,
HISI_N25Q_BUSY_FLAG_BIT,
0,
0,
MV_N25Q128_PAGE_SIZE,
MV_N25Q128_SECTOR_NUMBER,
MV_N25Q128_SECTOR_SIZE,
HISI_N25Q128_PAGE_SIZE,
HISI_N25Q128_SECTOR_NUMBER,
HISI_N25Q128_SECTOR_SIZE,
"NUMONYX N25Q128",
MV_N25Q128_MANF_ID,
MV_N25Q128_DEVICE_ID,
HISI_N25Q128_MANF_ID,
HISI_N25Q128_DEVICE_ID,
0xff,
0xff,
0xff,
MV_N25Q128_MAX_SPI_FREQ,
MV_N25Q128_MAX_FAST_SPI_FREQ,
MV_N25Q128_FAST_READ_DUMMY_BYTES,
HISI_N25Q128_MAX_SPI_FREQ,
HISI_N25Q128_MAX_FAST_SPI_FREQ,
HISI_N25Q128_FAST_READ_DUMMY_BYTES,
SPI_FLASH_3BYTE_ADDR,
STANDARD_SPI_IF},
/* NUMONYX N25Q128B SPI flash, 16MB, 256 sectors of 64K each */
{
MV_N25Q_WREN_CMND_OPCD,
MV_N25Q_WRDI_CMND_OPCD,
MV_N25Q_RDID_CMND_OPCD,
MV_N25Q_RDSR_CMND_OPCD,
MV_N25Q_WRSR_CMND_OPCD,
MV_N25Q_READ_CMND_OPCD,
MV_N25Q_FAST_RD_CMND_OPCD,
MV_N25Q_PP_CMND_OPCD,
MV_N25Q_SSE_CMND_OPCD,
MV_N25Q_SE_CMND_OPCD,
MV_N25Q_BE_CMND_OPCD,
MV_SFLASH_NO_SPECIFIC_OPCD,
MV_SFLASH_NO_SPECIFIC_OPCD,
MV_N25Q_RDVECR_CMND_OPCD,
MV_N25Q_WRVECR_CMND_OPCD,
MV_N25Q_EN4BADDR_CMND_OPCD,
MV_N25Q_EX4BADDR_CMND_OPCD,
MV_N25Q_BUSY_FLAG_BIT,
HISI_N25Q_WREN_CMND_OPCD,
HISI_N25Q_WRDI_CMND_OPCD,
HISI_N25Q_RDID_CMND_OPCD,
HISI_N25Q_RDSR_CMND_OPCD,
HISI_N25Q_WRSR_CMND_OPCD,
HISI_N25Q_READ_CMND_OPCD,
HISI_N25Q_FAST_RD_CMND_OPCD,
HISI_N25Q_PP_CMND_OPCD,
HISI_N25Q_SSE_CMND_OPCD,
HISI_N25Q_SE_CMND_OPCD,
HISI_N25Q_BE_CMND_OPCD,
HISI_SFLASH_NO_SPECIFIC_OPCD,
HISI_SFLASH_NO_SPECIFIC_OPCD,
HISI_N25Q_RDVECR_CMND_OPCD,
HISI_N25Q_WRVECR_CMND_OPCD,
HISI_N25Q_EN4BADDR_CMND_OPCD,
HISI_N25Q_EX4BADDR_CMND_OPCD,
HISI_N25Q_BUSY_FLAG_BIT,
0,
0,
MV_N25Q128_PAGE_SIZE,
MV_N25Q128_SECTOR_NUMBER,
MV_N25Q128_SECTOR_SIZE,
HISI_N25Q128_PAGE_SIZE,
HISI_N25Q128_SECTOR_NUMBER,
HISI_N25Q128_SECTOR_SIZE,
"NUMONYX N25Q128",
MV_N25Q128B_MANF_ID,
MV_N25Q128B_DEVICE_ID,
HISI_N25Q128B_MANF_ID,
HISI_N25Q128B_DEVICE_ID,
0xff,
0xff,
0xff,
MV_N25Q128_MAX_SPI_FREQ,
MV_N25Q128_MAX_FAST_SPI_FREQ,
MV_N25Q128_FAST_READ_DUMMY_BYTES,
HISI_N25Q128_MAX_SPI_FREQ,
HISI_N25Q128_MAX_FAST_SPI_FREQ,
HISI_N25Q128_FAST_READ_DUMMY_BYTES,
SPI_FLASH_3BYTE_ADDR,
STANDARD_SPI_IF},
/* NUMONYX N25Q256 SPI flash, 32MB, 256 sectors of 64K each */
{
MV_N25Q_WREN_CMND_OPCD,
MV_N25Q_WRDI_CMND_OPCD,
MV_N25Q_RDID_CMND_OPCD,
MV_N25Q_RDSR_CMND_OPCD,
MV_N25Q_WRSR_CMND_OPCD,
MV_N25Q_READ_CMND_OPCD,
MV_N25Q_FAST_RD_CMND_OPCD,
MV_N25Q_PP_CMND_OPCD,
MV_N25Q_SSE_CMND_OPCD,
MV_N25Q_SE_CMND_OPCD,
MV_N25Q_BE_CMND_OPCD,
MV_SFLASH_NO_SPECIFIC_OPCD,
MV_SFLASH_NO_SPECIFIC_OPCD,
MV_N25Q_RDVECR_CMND_OPCD,
MV_N25Q_WRVECR_CMND_OPCD,
MV_N25Q_EN4BADDR_CMND_OPCD,
MV_N25Q_EX4BADDR_CMND_OPCD,
MV_N25Q_BUSY_FLAG_BIT,
HISI_N25Q_WREN_CMND_OPCD,
HISI_N25Q_WRDI_CMND_OPCD,
HISI_N25Q_RDID_CMND_OPCD,
HISI_N25Q_RDSR_CMND_OPCD,
HISI_N25Q_WRSR_CMND_OPCD,
HISI_N25Q_READ_CMND_OPCD,
HISI_N25Q_FAST_RD_CMND_OPCD,
HISI_N25Q_PP_CMND_OPCD,
HISI_N25Q_SSE_CMND_OPCD,
HISI_N25Q_SE_CMND_OPCD,
HISI_N25Q_BE_CMND_OPCD,
HISI_SFLASH_NO_SPECIFIC_OPCD,
HISI_SFLASH_NO_SPECIFIC_OPCD,
HISI_N25Q_RDVECR_CMND_OPCD,
HISI_N25Q_WRVECR_CMND_OPCD,
HISI_N25Q_EN4BADDR_CMND_OPCD,
HISI_N25Q_EX4BADDR_CMND_OPCD,
HISI_N25Q_BUSY_FLAG_BIT,
0,
0,
MV_N25Q256_PAGE_SIZE,
MV_N25Q256_SECTOR_NUMBER,
MV_N25Q256_SECTOR_SIZE,
HISI_N25Q256_PAGE_SIZE,
HISI_N25Q256_SECTOR_NUMBER,
HISI_N25Q256_SECTOR_SIZE,
"NUMONYX N25Q256",
MV_N25Q256_MANF_ID,
MV_N25Q256_DEVICE_ID,
HISI_N25Q256_MANF_ID,
HISI_N25Q256_DEVICE_ID,
0xff,
0xff,
0xff,
MV_N25Q256_MAX_SPI_FREQ,
MV_N25Q256_MAX_FAST_SPI_FREQ,
MV_N25Q256_FAST_READ_DUMMY_BYTES,
HISI_N25Q256_MAX_SPI_FREQ,
HISI_N25Q256_MAX_FAST_SPI_FREQ,
HISI_N25Q256_FAST_READ_DUMMY_BYTES,
SPI_FLASH_3BYTE_ADDR,
STANDARD_SPI_IF},
/* ST M25P80 SPI flash, 1MB, 16 sectors of 64K each */
{
MV_M25P_WREN_CMND_OPCD,
MV_M25P_WRDI_CMND_OPCD,
MV_M25P_RDID_CMND_OPCD,
MV_M25P_RDSR_CMND_OPCD,
MV_M25P_WRSR_CMND_OPCD,
MV_M25P_READ_CMND_OPCD,
MV_M25P_FAST_RD_CMND_OPCD,
MV_M25P_PP_CMND_OPCD,
MV_M25P_SSE_CMND_OPCD,
MV_M25P_SE_CMND_OPCD,
MV_M25P_BE_CMND_OPCD,
MV_M25P_RES_CMND_OPCD,
MV_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */
MV_SFLASH_UNKOWN_OPCD, /* next code need see datasheet */
MV_SFLASH_UNKOWN_OPCD,
MV_SFLASH_UNKOWN_OPCD,
MV_SFLASH_UNKOWN_OPCD,
MV_SFLASH_UNKOWN_OPCD,
HISI_M25P_WREN_CMND_OPCD,
HISI_M25P_WRDI_CMND_OPCD,
HISI_M25P_RDID_CMND_OPCD,
HISI_M25P_RDSR_CMND_OPCD,
HISI_M25P_WRSR_CMND_OPCD,
HISI_M25P_READ_CMND_OPCD,
HISI_M25P_FAST_RD_CMND_OPCD,
HISI_M25P_PP_CMND_OPCD,
HISI_M25P_SSE_CMND_OPCD,
HISI_M25P_SE_CMND_OPCD,
HISI_M25P_BE_CMND_OPCD,
HISI_M25P_RES_CMND_OPCD,
HISI_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */
HISI_SFLASH_UNKOWN_OPCD, /* next code need see datasheet */
HISI_SFLASH_UNKOWN_OPCD,
HISI_SFLASH_UNKOWN_OPCD,
HISI_SFLASH_UNKOWN_OPCD,
HISI_SFLASH_UNKOWN_OPCD,
0,
0,
MV_M25P_PAGE_SIZE,
MV_M25P80_SECTOR_NUMBER,
MV_M25P80_SECTOR_SIZE,
HISI_M25P_PAGE_SIZE,
HISI_M25P80_SECTOR_NUMBER,
HISI_M25P80_SECTOR_SIZE,
"ST M25P80",
MV_M25PXXX_ST_MANF_ID,
MV_M25P80_DEVICE_ID,
HISI_M25PXXX_ST_MANF_ID,
HISI_M25P80_DEVICE_ID,
0xff,
0xff,
0xff,
MV_M25P80_MAX_SPI_FREQ,
MV_M25P80_MAX_FAST_SPI_FREQ,
MV_M25P80_FAST_READ_DUMMY_BYTES,
HISI_M25P80_MAX_SPI_FREQ,
HISI_M25P80_MAX_FAST_SPI_FREQ,
HISI_M25P80_FAST_READ_DUMMY_BYTES,
SPI_FLASH_3BYTE_ADDR,
STANDARD_SPI_IF},
/* ST M25P32 SPI flash, 4MB, 64 sectors of 64K each */
{
MV_M25P_WREN_CMND_OPCD,
MV_M25P_WRDI_CMND_OPCD,
MV_M25P_RDID_CMND_OPCD,
MV_M25P_RDSR_CMND_OPCD,
MV_M25P_WRSR_CMND_OPCD,
MV_M25P_READ_CMND_OPCD,
MV_M25P_FAST_RD_CMND_OPCD,
MV_M25P_PP_CMND_OPCD,
MV_M25P_SSE_CMND_OPCD,
MV_M25P_SE_CMND_OPCD,
MV_M25P_BE_CMND_OPCD,
MV_M25P_RES_CMND_OPCD,
MV_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */
MV_SFLASH_UNKOWN_OPCD, /* next code need see datasheet */
MV_SFLASH_UNKOWN_OPCD,
MV_SFLASH_UNKOWN_OPCD,
MV_SFLASH_UNKOWN_OPCD,
MV_SFLASH_UNKOWN_OPCD,
HISI_M25P_WREN_CMND_OPCD,
HISI_M25P_WRDI_CMND_OPCD,
HISI_M25P_RDID_CMND_OPCD,
HISI_M25P_RDSR_CMND_OPCD,
HISI_M25P_WRSR_CMND_OPCD,
HISI_M25P_READ_CMND_OPCD,
HISI_M25P_FAST_RD_CMND_OPCD,
HISI_M25P_PP_CMND_OPCD,
HISI_M25P_SSE_CMND_OPCD,
HISI_M25P_SE_CMND_OPCD,
HISI_M25P_BE_CMND_OPCD,
HISI_M25P_RES_CMND_OPCD,
HISI_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */
HISI_SFLASH_UNKOWN_OPCD, /* next code need see datasheet */
HISI_SFLASH_UNKOWN_OPCD,
HISI_SFLASH_UNKOWN_OPCD,
HISI_SFLASH_UNKOWN_OPCD,
HISI_SFLASH_UNKOWN_OPCD,
0,
0,
MV_M25P_PAGE_SIZE,
MV_M25P32_SECTOR_NUMBER,
MV_M25P32_SECTOR_SIZE,
HISI_M25P_PAGE_SIZE,
HISI_M25P32_SECTOR_NUMBER,
HISI_M25P32_SECTOR_SIZE,
"ST M25P32",
MV_M25PXXX_ST_MANF_ID,
MV_M25P32_DEVICE_ID,
HISI_M25PXXX_ST_MANF_ID,
HISI_M25P32_DEVICE_ID,
0xff,
0xff,
0xff,
MV_M25P32_MAX_SPI_FREQ,
MV_M25P32_MAX_FAST_SPI_FREQ,
MV_M25P32_FAST_READ_DUMMY_BYTES,
HISI_M25P32_MAX_SPI_FREQ,
HISI_M25P32_MAX_FAST_SPI_FREQ,
HISI_M25P32_FAST_READ_DUMMY_BYTES,
SPI_FLASH_3BYTE_ADDR,
STANDARD_SPI_IF},
/* ST M25P64 SPI flash, 8MB, 128 sectors of 64K each */
{
MV_M25P_WREN_CMND_OPCD,
MV_M25P_WRDI_CMND_OPCD,
MV_M25P_RDID_CMND_OPCD,
MV_M25P_RDSR_CMND_OPCD,
MV_M25P_WRSR_CMND_OPCD,
MV_M25P_READ_CMND_OPCD,
MV_M25P_FAST_RD_CMND_OPCD,
MV_M25P_PP_CMND_OPCD,
MV_M25P_SSE_CMND_OPCD,
MV_M25P_SE_CMND_OPCD,
MV_M25P_BE_CMND_OPCD,
MV_M25P_RES_CMND_OPCD,
MV_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */
MV_SFLASH_UNKOWN_OPCD, /* next code need see datasheet */
MV_SFLASH_UNKOWN_OPCD,
MV_SFLASH_UNKOWN_OPCD,
MV_SFLASH_UNKOWN_OPCD,
MV_SFLASH_UNKOWN_OPCD,
HISI_M25P_WREN_CMND_OPCD,
HISI_M25P_WRDI_CMND_OPCD,
HISI_M25P_RDID_CMND_OPCD,
HISI_M25P_RDSR_CMND_OPCD,
HISI_M25P_WRSR_CMND_OPCD,
HISI_M25P_READ_CMND_OPCD,
HISI_M25P_FAST_RD_CMND_OPCD,
HISI_M25P_PP_CMND_OPCD,
HISI_M25P_SSE_CMND_OPCD,
HISI_M25P_SE_CMND_OPCD,
HISI_M25P_BE_CMND_OPCD,
HISI_M25P_RES_CMND_OPCD,
HISI_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */
HISI_SFLASH_UNKOWN_OPCD, /* next code need see datasheet */
HISI_SFLASH_UNKOWN_OPCD,
HISI_SFLASH_UNKOWN_OPCD,
HISI_SFLASH_UNKOWN_OPCD,
HISI_SFLASH_UNKOWN_OPCD,
0,
0,
MV_M25P_PAGE_SIZE,
MV_M25P64_SECTOR_NUMBER,
MV_M25P64_SECTOR_SIZE,
HISI_M25P_PAGE_SIZE,
HISI_M25P64_SECTOR_NUMBER,
HISI_M25P64_SECTOR_SIZE,
"ST M25P64",
MV_M25PXXX_ST_MANF_ID,
MV_M25P64_DEVICE_ID,
HISI_M25PXXX_ST_MANF_ID,
HISI_M25P64_DEVICE_ID,
0xff,
0xff,
0xff,
MV_M25P64_MAX_SPI_FREQ,
MV_M25P64_MAX_FAST_SPI_FREQ,
MV_M25P64_FAST_READ_DUMMY_BYTES,
HISI_M25P64_MAX_SPI_FREQ,
HISI_M25P64_MAX_FAST_SPI_FREQ,
HISI_M25P64_FAST_READ_DUMMY_BYTES,
SPI_FLASH_3BYTE_ADDR,
STANDARD_SPI_IF},
/* ST M25P128 SPI flash, 16MB, 64 sectors of 256K each */
{
MV_M25P_WREN_CMND_OPCD,
MV_M25P_WRDI_CMND_OPCD,
MV_M25P_RDID_CMND_OPCD,
MV_M25P_RDSR_CMND_OPCD,
MV_M25P_WRSR_CMND_OPCD,
MV_M25P_READ_CMND_OPCD,
MV_M25P_FAST_RD_CMND_OPCD,
MV_M25P_PP_CMND_OPCD,
MV_M25P_SSE_CMND_OPCD,
MV_M25P_SE_CMND_OPCD,
MV_M25P_BE_CMND_OPCD,
MV_M25P_RES_CMND_OPCD,
MV_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */
MV_SFLASH_UNKOWN_OPCD, /* next code need see datasheet */
MV_SFLASH_UNKOWN_OPCD,
MV_SFLASH_UNKOWN_OPCD,
MV_SFLASH_UNKOWN_OPCD,
MV_SFLASH_UNKOWN_OPCD,
HISI_M25P_WREN_CMND_OPCD,
HISI_M25P_WRDI_CMND_OPCD,
HISI_M25P_RDID_CMND_OPCD,
HISI_M25P_RDSR_CMND_OPCD,
HISI_M25P_WRSR_CMND_OPCD,
HISI_M25P_READ_CMND_OPCD,
HISI_M25P_FAST_RD_CMND_OPCD,
HISI_M25P_PP_CMND_OPCD,
HISI_M25P_SSE_CMND_OPCD,
HISI_M25P_SE_CMND_OPCD,
HISI_M25P_BE_CMND_OPCD,
HISI_M25P_RES_CMND_OPCD,
HISI_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */
HISI_SFLASH_UNKOWN_OPCD, /* next code need see datasheet */
HISI_SFLASH_UNKOWN_OPCD,
HISI_SFLASH_UNKOWN_OPCD,
HISI_SFLASH_UNKOWN_OPCD,
HISI_SFLASH_UNKOWN_OPCD,
0,
0,
MV_M25P_PAGE_SIZE,
MV_M25P128_SECTOR_NUMBER,
MV_M25P128_SECTOR_SIZE,
HISI_M25P_PAGE_SIZE,
HISI_M25P128_SECTOR_NUMBER,
HISI_M25P128_SECTOR_SIZE,
"ST M25P128",
MV_M25PXXX_ST_MANF_ID,
MV_M25P128_DEVICE_ID,
HISI_M25PXXX_ST_MANF_ID,
HISI_M25P128_DEVICE_ID,
0xff,
0xff,
0xff,
MV_M25P128_MAX_SPI_FREQ,
MV_M25P128_MAX_FAST_SPI_FREQ,
MV_M25P128_FAST_READ_DUMMY_BYTES,
HISI_M25P128_MAX_SPI_FREQ,
HISI_M25P128_MAX_FAST_SPI_FREQ,
HISI_M25P128_FAST_READ_DUMMY_BYTES,
SPI_FLASH_3BYTE_ADDR,
STANDARD_SPI_IF},
/* Macronix MXIC MX25L6405 SPI flash, 8MB, 128 sectors of 64K each */
{
MV_MX25L_WREN_CMND_OPCD,
MV_MX25L_WRDI_CMND_OPCD,
MV_MX25L_RDID_CMND_OPCD,
MV_MX25L_RDSR_CMND_OPCD,
MV_MX25L_WRSR_CMND_OPCD,
MV_MX25L_READ_CMND_OPCD,
MV_MX25L_FAST_RD_CMND_OPCD,
MV_MX25L_PP_CMND_OPCD,
MV_MX25L_SSE_CMND_OPCD,
MV_MX25L_SE_CMND_OPCD,
MV_MX25L_BE_CMND_OPCD,
MV_MX25L_RES_CMND_OPCD,
MV_MX25L_DP_CMND_OPCD,
MV_SFLASH_UNKOWN_OPCD, /* next code need see datasheet */
MV_SFLASH_UNKOWN_OPCD,
MV_SFLASH_UNKOWN_OPCD,
MV_SFLASH_UNKOWN_OPCD,
MV_SFLASH_UNKOWN_OPCD,
HISI_MX25L_WREN_CMND_OPCD,
HISI_MX25L_WRDI_CMND_OPCD,
HISI_MX25L_RDID_CMND_OPCD,
HISI_MX25L_RDSR_CMND_OPCD,
HISI_MX25L_WRSR_CMND_OPCD,
HISI_MX25L_READ_CMND_OPCD,
HISI_MX25L_FAST_RD_CMND_OPCD,
HISI_MX25L_PP_CMND_OPCD,
HISI_MX25L_SSE_CMND_OPCD,
HISI_MX25L_SE_CMND_OPCD,
HISI_MX25L_BE_CMND_OPCD,
HISI_MX25L_RES_CMND_OPCD,
HISI_MX25L_DP_CMND_OPCD,
HISI_SFLASH_UNKOWN_OPCD, /* next code need see datasheet */
HISI_SFLASH_UNKOWN_OPCD,
HISI_SFLASH_UNKOWN_OPCD,
HISI_SFLASH_UNKOWN_OPCD,
HISI_SFLASH_UNKOWN_OPCD,
0,
0,
MV_MXIC_PAGE_SIZE,
MV_MX25L6405_SECTOR_NUMBER,
MV_MX25L6405_SECTOR_SIZE,
HISI_MXIC_PAGE_SIZE,
HISI_MX25L6405_SECTOR_NUMBER,
HISI_MX25L6405_SECTOR_SIZE,
"MXIC MX25L6405",
MV_MXIC_MANF_ID,
MV_MX25L6405_DEVICE_ID,
HISI_MXIC_MANF_ID,
HISI_MX25L6405_DEVICE_ID,
0xff,
0xff,
0xff,
MV_MX25L6405_MAX_SPI_FREQ,
MV_MX25L6405_MAX_FAST_SPI_FREQ,
MV_MX25L6405_FAST_READ_DUMMY_BYTES,
HISI_MX25L6405_MAX_SPI_FREQ,
HISI_MX25L6405_MAX_FAST_SPI_FREQ,
HISI_MX25L6405_FAST_READ_DUMMY_BYTES,
SPI_FLASH_3BYTE_ADDR,
STANDARD_SPI_IF},
/* Macronix MXIC MX25L1606E SPI flash, 2MB, 32 sectors of 64K each */
{
MV_MX25L_WREN_CMND_OPCD,
MV_MX25L_WRDI_CMND_OPCD,
MV_MX25L_RDID_CMND_OPCD,
MV_MX25L_RDSR_CMND_OPCD,
MV_MX25L_WRSR_CMND_OPCD,
MV_MX25L_READ_CMND_OPCD,
MV_MX25L_FAST_RD_CMND_OPCD,
MV_MX25L_PP_CMND_OPCD,
MV_MX25L_SSE_CMND_OPCD,
MV_MX25L_SE_CMND_OPCD,
MV_MX25L_BE_CMND_OPCD,
MV_MX25L_RES_CMND_OPCD,
MV_MX25L_DP_CMND_OPCD,
MV_SFLASH_NO_SPECIFIC_OPCD, /* can't support next 5 code */
MV_SFLASH_NO_SPECIFIC_OPCD,
MV_SFLASH_NO_SPECIFIC_OPCD,
MV_SFLASH_NO_SPECIFIC_OPCD,
MV_SFLASH_NO_SPECIFIC_OPCD,
HISI_MX25L_WREN_CMND_OPCD,
HISI_MX25L_WRDI_CMND_OPCD,
HISI_MX25L_RDID_CMND_OPCD,
HISI_MX25L_RDSR_CMND_OPCD,
HISI_MX25L_WRSR_CMND_OPCD,
HISI_MX25L_READ_CMND_OPCD,
HISI_MX25L_FAST_RD_CMND_OPCD,
HISI_MX25L_PP_CMND_OPCD,
HISI_MX25L_SSE_CMND_OPCD,
HISI_MX25L_SE_CMND_OPCD,
HISI_MX25L_BE_CMND_OPCD,
HISI_MX25L_RES_CMND_OPCD,
HISI_MX25L_DP_CMND_OPCD,
HISI_SFLASH_NO_SPECIFIC_OPCD, /* can't support next 5 code */
HISI_SFLASH_NO_SPECIFIC_OPCD,
HISI_SFLASH_NO_SPECIFIC_OPCD,
HISI_SFLASH_NO_SPECIFIC_OPCD,
HISI_SFLASH_NO_SPECIFIC_OPCD,
0,
0,
MV_MXIC_PAGE_SIZE,
MV_MX25L1606E_SECTOR_NUMBER,
MV_MX25L1606E_SECTOR_SIZE,
HISI_MXIC_PAGE_SIZE,
HISI_MX25L1606E_SECTOR_NUMBER,
HISI_MX25L1606E_SECTOR_SIZE,
"MXIC MX25L1606E",
MV_MXIC_MANF_ID,
MV_MX25L1606E_DEVICE_ID,
HISI_MXIC_MANF_ID,
HISI_MX25L1606E_DEVICE_ID,
0xff,
0xff,
0xff,
MV_MX25L1606E_MAX_SPI_FREQ,
MV_MX25L1606E_MAX_FAST_SPI_FREQ,
MV_MX25L1606E_FAST_READ_DUMMY_BYTES,
HISI_MX25L1606E_MAX_SPI_FREQ,
HISI_MX25L1606E_MAX_FAST_SPI_FREQ,
HISI_MX25L1606E_FAST_READ_DUMMY_BYTES,
SPI_FLASH_3BYTE_ADDR,
STANDARD_SPI_IF},
/* Macronix MXIC MX25U12835F SPI flash, 16MB, 255 sectors of 64K each */
{
MV_MX25U12835F_WREN_CMND_OPCD,
MV_MX25U12835F_WRDI_CMND_OPCD,
MV_MX25U12835F_RDID_CMND_OPCD,
MV_MX25U12835F_RDSR_CMND_OPCD,
MV_MX25U12835F_WRSR_CMND_OPCD,
MV_MX25U12835F_READ_CMND_OPCD,
MV_MX25U12835F_FAST_RD_CMND_OPCD,
MV_MX25U12835F_PP_CMND_OPCD,
MV_MX25U12835F_SSE_CMND_OPCD,
MV_MX25U12835F_SE_CMND_OPCD,
MV_MX25U12835F_BE_CMND_OPCD,
MV_MX25U12835F_RES_CMND_OPCD,
MV_MX25U12835F_DP_CMND_OPCD,
MV_SFLASH_NO_SPECIFIC_OPCD, /* can't support next 5 code */
MV_SFLASH_NO_SPECIFIC_OPCD,
MV_SFLASH_NO_SPECIFIC_OPCD,
MV_SFLASH_NO_SPECIFIC_OPCD,
MV_SFLASH_NO_SPECIFIC_OPCD,
HISI_MX25U12835F_WREN_CMND_OPCD,
HISI_MX25U12835F_WRDI_CMND_OPCD,
HISI_MX25U12835F_RDID_CMND_OPCD,
HISI_MX25U12835F_RDSR_CMND_OPCD,
HISI_MX25U12835F_WRSR_CMND_OPCD,
HISI_MX25U12835F_READ_CMND_OPCD,
HISI_MX25U12835F_FAST_RD_CMND_OPCD,
HISI_MX25U12835F_PP_CMND_OPCD,
HISI_MX25U12835F_SSE_CMND_OPCD,
HISI_MX25U12835F_SE_CMND_OPCD,
HISI_MX25U12835F_BE_CMND_OPCD,
HISI_MX25U12835F_RES_CMND_OPCD,
HISI_MX25U12835F_DP_CMND_OPCD,
HISI_SFLASH_NO_SPECIFIC_OPCD, /* can't support next 5 code */
HISI_SFLASH_NO_SPECIFIC_OPCD,
HISI_SFLASH_NO_SPECIFIC_OPCD,
HISI_SFLASH_NO_SPECIFIC_OPCD,
HISI_SFLASH_NO_SPECIFIC_OPCD,
0,
0,
MV_MX25U12835F_PAGE_SIZE,
MV_MX25U12835F_SECTOR_NUMBER,
MV_MX25U12835F_SECTOR_SIZE,
HISI_MX25U12835F_PAGE_SIZE,
HISI_MX25U12835F_SECTOR_NUMBER,
HISI_MX25U12835F_SECTOR_SIZE,
"MXIC MX25U12835F",
MV_MX25U12835F_MANF_ID,
MV_MX25U12835F_DEVICE_ID,
HISI_MX25U12835F_MANF_ID,
HISI_MX25U12835F_DEVICE_ID,
0xff,
0xff,
0xff,
MV_MX25U12835F_MAX_SPI_FREQ,
MV_MX25U12835F_MAX_FAST_SPI_FREQ,
MV_MX25U12835F_FAST_READ_DUMMY_BYTES,
HISI_MX25U12835F_MAX_SPI_FREQ,
HISI_MX25U12835F_MAX_FAST_SPI_FREQ,
HISI_MX25U12835F_FAST_READ_DUMMY_BYTES,
SPI_FLASH_3BYTE_ADDR,
STANDARD_SPI_IF},
/* SPANSION S25FL128P SPI flash, 16MB, 64 sectors of 256K each */
{
MV_S25FL_WREN_CMND_OPCD,
MV_S25FL_WRDI_CMND_OPCD,
MV_S25FL_RDID_CMND_OPCD,
MV_S25FL_RDSR_CMND_OPCD,
MV_S25FL_WRSR_CMND_OPCD,
MV_S25FL_READ_CMND_OPCD,
MV_S25FL_FAST_RD_CMND_OPCD,
MV_S25FL_PP_CMND_OPCD,
MV_S25FL_SSE_CMND_OPCD,
MV_S25FL_SE_CMND_OPCD,
MV_S25FL_BE_CMND_OPCD,
MV_S25FL_RES_CMND_OPCD,
MV_S25FL_DP_CMND_OPCD,
MV_SFLASH_UNKOWN_OPCD, /* next code need see datasheet */
MV_SFLASH_UNKOWN_OPCD,
MV_SFLASH_UNKOWN_OPCD,
MV_SFLASH_UNKOWN_OPCD,
MV_SFLASH_UNKOWN_OPCD,
HISI_S25FL_WREN_CMND_OPCD,
HISI_S25FL_WRDI_CMND_OPCD,
HISI_S25FL_RDID_CMND_OPCD,
HISI_S25FL_RDSR_CMND_OPCD,
HISI_S25FL_WRSR_CMND_OPCD,
HISI_S25FL_READ_CMND_OPCD,
HISI_S25FL_FAST_RD_CMND_OPCD,
HISI_S25FL_PP_CMND_OPCD,
HISI_S25FL_SSE_CMND_OPCD,
HISI_S25FL_SE_CMND_OPCD,
HISI_S25FL_BE_CMND_OPCD,
HISI_S25FL_RES_CMND_OPCD,
HISI_S25FL_DP_CMND_OPCD,
HISI_SFLASH_UNKOWN_OPCD, /* next code need see datasheet */
HISI_SFLASH_UNKOWN_OPCD,
HISI_SFLASH_UNKOWN_OPCD,
HISI_SFLASH_UNKOWN_OPCD,
HISI_SFLASH_UNKOWN_OPCD,
0,
0,
MV_S25FL_PAGE_SIZE,
MV_S25FL128_SECTOR_NUMBER,
MV_S25FL128_SECTOR_SIZE,
HISI_S25FL_PAGE_SIZE,
HISI_S25FL128_SECTOR_NUMBER,
HISI_S25FL128_SECTOR_SIZE,
"SPANSION S25FL128",
MV_SPANSION_MANF_ID,
MV_S25FL128_DEVICE_ID,
HISI_SPANSION_MANF_ID,
HISI_S25FL128_DEVICE_ID,
0xff,
0xff,
0x80,
MV_S25FL128_MAX_SPI_FREQ,
MV_M25P128_MAX_FAST_SPI_FREQ,
MV_M25P128_FAST_READ_DUMMY_BYTES,
HISI_S25FL128_MAX_SPI_FREQ,
HISI_M25P128_MAX_FAST_SPI_FREQ,
HISI_M25P128_FAST_READ_DUMMY_BYTES,
SPI_FLASH_3BYTE_ADDR,
STANDARD_SPI_IF},
/* SPANSION S25FS128S SPI flash, 16MB, 255 sectors of 64K each + */
{
MV_S25FL_WREN_CMND_OPCD,
MV_S25FL_WRDI_CMND_OPCD,
MV_S25FL_RDID_CMND_OPCD,
MV_S25FL_RDSR_CMND_OPCD,
MV_S25FL_WRSR_CMND_OPCD,
MV_S25FL_READ_CMND_OPCD,
MV_S25FL_FAST_RD_CMND_OPCD,
MV_S25FL_PP_CMND_OPCD,
MV_S25FL_SSE_CMND_OPCD,
MV_S25FL_SE_CMND_OPCD,
MV_S25FL_BE_CMND_OPCD,
MV_S25FL_RES_CMND_OPCD,
MV_S25FL_DP_CMND_OPCD,
MV_SFLASH_UNKOWN_OPCD, /* next code need see datasheet */
MV_SFLASH_UNKOWN_OPCD,
MV_SFLASH_UNKOWN_OPCD,
MV_SFLASH_UNKOWN_OPCD,
MV_SFLASH_UNKOWN_OPCD,
HISI_S25FL_WREN_CMND_OPCD,
HISI_S25FL_WRDI_CMND_OPCD,
HISI_S25FL_RDID_CMND_OPCD,
HISI_S25FL_RDSR_CMND_OPCD,
HISI_S25FL_WRSR_CMND_OPCD,
HISI_S25FL_READ_CMND_OPCD,
HISI_S25FL_FAST_RD_CMND_OPCD,
HISI_S25FL_PP_CMND_OPCD,
HISI_S25FL_SSE_CMND_OPCD,
HISI_S25FL_SE_CMND_OPCD,
HISI_S25FL_BE_CMND_OPCD,
HISI_S25FL_RES_CMND_OPCD,
HISI_S25FL_DP_CMND_OPCD,
HISI_SFLASH_UNKOWN_OPCD, /* next code need see datasheet */
HISI_SFLASH_UNKOWN_OPCD,
HISI_SFLASH_UNKOWN_OPCD,
HISI_SFLASH_UNKOWN_OPCD,
HISI_SFLASH_UNKOWN_OPCD,
0,
0,
MV_S25FL_PAGE_SIZE,
MV_S25FL128_SECTOR_NUMBER,
MV_S25FL128_SECTOR_SIZE,
HISI_S25FL_PAGE_SIZE,
HISI_S25FL128_SECTOR_NUMBER,
HISI_S25FL128_SECTOR_SIZE,
"SPANSION S25FS128",
MV_SPANSION_MANF_ID,
MV_S25FL128_DEVICE_ID,
HISI_SPANSION_MANF_ID,
HISI_S25FL128_DEVICE_ID,
0xff,
0xff,
0x81,
MV_S25FL128_MAX_SPI_FREQ,
MV_M25P128_MAX_FAST_SPI_FREQ,
MV_M25P128_FAST_READ_DUMMY_BYTES,
HISI_S25FL128_MAX_SPI_FREQ,
HISI_M25P128_MAX_FAST_SPI_FREQ,
HISI_M25P128_FAST_READ_DUMMY_BYTES,
SPI_FLASH_3BYTE_ADDR,
STANDARD_SPI_IF},
/* ATMEL AT25DF641 SPI flash, 8MB, 128 sectors of 64K each */
{
MV_AT25DF_WREN_CMND_OPCD,
MV_AT25DF_WRDI_CMND_OPCD,
MV_AT25DF_RDID_CMND_OPCD,
MV_AT25DF_RDSR_CMND_OPCD,
MV_AT25DF_WRSR_CMND_OPCD,
MV_AT25DF_READ_CMND_OPCD,
MV_AT25DF_FAST_RD_CMND_OPCD,
MV_AT25DF_PP_CMND_OPCD,
MV_AT25DF_SSE_CMND_OPCD,
MV_AT25DF_SE_CMND_OPCD,
MV_AT25DF_BE_CMND_OPCD,
MV_AT25DF_RES_CMND_OPCD,
MV_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */
MV_SFLASH_UNKOWN_OPCD, /* next code need see datasheet */
MV_SFLASH_UNKOWN_OPCD,
MV_SFLASH_UNKOWN_OPCD,
MV_SFLASH_UNKOWN_OPCD,
MV_SFLASH_UNKOWN_OPCD,
HISI_AT25DF_WREN_CMND_OPCD,
HISI_AT25DF_WRDI_CMND_OPCD,
HISI_AT25DF_RDID_CMND_OPCD,
HISI_AT25DF_RDSR_CMND_OPCD,
HISI_AT25DF_WRSR_CMND_OPCD,
HISI_AT25DF_READ_CMND_OPCD,
HISI_AT25DF_FAST_RD_CMND_OPCD,
HISI_AT25DF_PP_CMND_OPCD,
HISI_AT25DF_SSE_CMND_OPCD,
HISI_AT25DF_SE_CMND_OPCD,
HISI_AT25DF_BE_CMND_OPCD,
HISI_AT25DF_RES_CMND_OPCD,
HISI_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */
HISI_SFLASH_UNKOWN_OPCD, /* next code need see datasheet */
HISI_SFLASH_UNKOWN_OPCD,
HISI_SFLASH_UNKOWN_OPCD,
HISI_SFLASH_UNKOWN_OPCD,
HISI_SFLASH_UNKOWN_OPCD,
0,
0,
MV_AT25DF_PAGE_SIZE,
MV_AT25DF641_SECTOR_NUMBER,
MV_AT25DF641_SECTOR_SIZE,
HISI_AT25DF_PAGE_SIZE,
HISI_AT25DF641_SECTOR_NUMBER,
HISI_AT25DF641_SECTOR_SIZE,
"AT 25DF641",
MV_AT25DFXXX_AT_MANF_ID,
MV_AT25DF641_DEVICE_ID,
HISI_AT25DFXXX_AT_MANF_ID,
HISI_AT25DF641_DEVICE_ID,
0xff,
0xff,
0xff,
MV_AT25DF641_MAX_SPI_FREQ,
MV_AT25DF641_MAX_FAST_SPI_FREQ,
MV_AT25DF641_FAST_READ_DUMMY_BYTES,
HISI_AT25DF641_MAX_SPI_FREQ,
HISI_AT25DF641_MAX_FAST_SPI_FREQ,
HISI_AT25DF641_FAST_READ_DUMMY_BYTES,
SPI_FLASH_3BYTE_ADDR,
STANDARD_SPI_IF},
/* new add , M25P */
{
MV_M25P_WREN_CMND_OPCD,
MV_M25P_WRDI_CMND_OPCD,
MV_M25P_RDID_CMND_OPCD,
MV_M25P_RDSR_CMND_OPCD,
MV_M25P_WRSR_CMND_OPCD,
MV_M25P_READ_CMND_OPCD,
MV_M25P_FAST_RD_CMND_OPCD,
MV_M25P_PP_CMND_OPCD,
MV_M25P_SSE_CMND_OPCD,
MV_M25P_SE_CMND_OPCD,
MV_M25P_BE_CMND_OPCD,
MV_M25P_RES_CMND_OPCD,
MV_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */
MV_SFLASH_UNKOWN_OPCD, /* next code need see datasheet */
MV_SFLASH_UNKOWN_OPCD,
MV_SFLASH_UNKOWN_OPCD,
MV_SFLASH_UNKOWN_OPCD,
MV_SFLASH_UNKOWN_OPCD,
HISI_M25P_WREN_CMND_OPCD,
HISI_M25P_WRDI_CMND_OPCD,
HISI_M25P_RDID_CMND_OPCD,
HISI_M25P_RDSR_CMND_OPCD,
HISI_M25P_WRSR_CMND_OPCD,
HISI_M25P_READ_CMND_OPCD,
HISI_M25P_FAST_RD_CMND_OPCD,
HISI_M25P_PP_CMND_OPCD,
HISI_M25P_SSE_CMND_OPCD,
HISI_M25P_SE_CMND_OPCD,
HISI_M25P_BE_CMND_OPCD,
HISI_M25P_RES_CMND_OPCD,
HISI_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */
HISI_SFLASH_UNKOWN_OPCD, /* next code need see datasheet */
HISI_SFLASH_UNKOWN_OPCD,
HISI_SFLASH_UNKOWN_OPCD,
HISI_SFLASH_UNKOWN_OPCD,
HISI_SFLASH_UNKOWN_OPCD,
0,
0,
MV_M25P_PAGE_SIZE,
MV_M25P32_SECTOR_NUMBER,
MV_M25P32_SECTOR_SIZE,
HISI_M25P_PAGE_SIZE,
HISI_M25P32_SECTOR_NUMBER,
HISI_M25P32_SECTOR_SIZE,
"ST_M25PXXX",
MV_M25PXXX_ST_MANF_ID,
HISI_M25PXXX_ST_MANF_ID,
0xffff,
0xff,
0xff,
0xff,
MV_M25P32_MAX_SPI_FREQ,
MV_M25P32_MAX_FAST_SPI_FREQ,
MV_M25P32_FAST_READ_DUMMY_BYTES,
HISI_M25P32_MAX_SPI_FREQ,
HISI_M25P32_MAX_FAST_SPI_FREQ,
HISI_M25P32_FAST_READ_DUMMY_BYTES,
SPI_FLASH_3BYTE_ADDR,
STANDARD_SPI_IF},
/* new add , M25L */
{
MV_MX25L_WREN_CMND_OPCD,
MV_MX25L_WRDI_CMND_OPCD,
MV_MX25L_RDID_CMND_OPCD,
MV_MX25L_RDSR_CMND_OPCD,
MV_MX25L_WRSR_CMND_OPCD,
MV_MX25L_READ_CMND_OPCD,
MV_MX25L_FAST_RD_CMND_OPCD,
MV_MX25L_PP_CMND_OPCD,
MV_MX25L_SSE_CMND_OPCD,
MV_MX25L_SE_CMND_OPCD,
MV_MX25L_BE_CMND_OPCD,
MV_MX25L_RES_CMND_OPCD,
MV_MX25L_DP_CMND_OPCD,
MV_SFLASH_UNKOWN_OPCD, /* next code need see datasheet */
MV_SFLASH_UNKOWN_OPCD,
MV_SFLASH_UNKOWN_OPCD,
MV_SFLASH_UNKOWN_OPCD,
MV_SFLASH_UNKOWN_OPCD,
HISI_MX25L_WREN_CMND_OPCD,
HISI_MX25L_WRDI_CMND_OPCD,
HISI_MX25L_RDID_CMND_OPCD,
HISI_MX25L_RDSR_CMND_OPCD,
HISI_MX25L_WRSR_CMND_OPCD,
HISI_MX25L_READ_CMND_OPCD,
HISI_MX25L_FAST_RD_CMND_OPCD,
HISI_MX25L_PP_CMND_OPCD,
HISI_MX25L_SSE_CMND_OPCD,
HISI_MX25L_SE_CMND_OPCD,
HISI_MX25L_BE_CMND_OPCD,
HISI_MX25L_RES_CMND_OPCD,
HISI_MX25L_DP_CMND_OPCD,
HISI_SFLASH_UNKOWN_OPCD, /* next code need see datasheet */
HISI_SFLASH_UNKOWN_OPCD,
HISI_SFLASH_UNKOWN_OPCD,
HISI_SFLASH_UNKOWN_OPCD,
HISI_SFLASH_UNKOWN_OPCD,
0,
0,
MV_MXIC_PAGE_SIZE,
MV_MX25L6405_SECTOR_NUMBER,
MV_MX25L6405_SECTOR_SIZE,
HISI_MXIC_PAGE_SIZE,
HISI_MX25L6405_SECTOR_NUMBER,
HISI_MX25L6405_SECTOR_SIZE,
"MXIC MX25LXXX",
MV_MXIC_MANF_ID,
HISI_MXIC_MANF_ID,
0xffff,
0xff,
0xff,
0xff,
MV_MX25L6405_MAX_SPI_FREQ,
MV_MX25L6405_MAX_FAST_SPI_FREQ,
MV_MX25L6405_FAST_READ_DUMMY_BYTES,
HISI_MX25L6405_MAX_SPI_FREQ,
HISI_MX25L6405_MAX_FAST_SPI_FREQ,
HISI_MX25L6405_FAST_READ_DUMMY_BYTES,
SPI_FLASH_3BYTE_ADDR,
STANDARD_SPI_IF},
/* new add , M25FL */
{
MV_S25FL_WREN_CMND_OPCD,
MV_S25FL_WRDI_CMND_OPCD,
MV_S25FL_RDID_CMND_OPCD,
MV_S25FL_RDSR_CMND_OPCD,
MV_S25FL_WRSR_CMND_OPCD,
MV_S25FL_READ_CMND_OPCD,
MV_S25FL_FAST_RD_CMND_OPCD,
MV_S25FL_PP_CMND_OPCD,
MV_S25FL_SSE_CMND_OPCD,
MV_S25FL_SE_CMND_OPCD,
MV_S25FL_BE_CMND_OPCD,
MV_S25FL_RES_CMND_OPCD,
MV_S25FL_DP_CMND_OPCD,
MV_SFLASH_UNKOWN_OPCD, /* next code need see datasheet */
MV_SFLASH_UNKOWN_OPCD,
MV_SFLASH_UNKOWN_OPCD,
MV_SFLASH_UNKOWN_OPCD,
MV_SFLASH_UNKOWN_OPCD,
HISI_S25FL_WREN_CMND_OPCD,
HISI_S25FL_WRDI_CMND_OPCD,
HISI_S25FL_RDID_CMND_OPCD,
HISI_S25FL_RDSR_CMND_OPCD,
HISI_S25FL_WRSR_CMND_OPCD,
HISI_S25FL_READ_CMND_OPCD,
HISI_S25FL_FAST_RD_CMND_OPCD,
HISI_S25FL_PP_CMND_OPCD,
HISI_S25FL_SSE_CMND_OPCD,
HISI_S25FL_SE_CMND_OPCD,
HISI_S25FL_BE_CMND_OPCD,
HISI_S25FL_RES_CMND_OPCD,
HISI_S25FL_DP_CMND_OPCD,
HISI_SFLASH_UNKOWN_OPCD, /* next code need see datasheet */
HISI_SFLASH_UNKOWN_OPCD,
HISI_SFLASH_UNKOWN_OPCD,
HISI_SFLASH_UNKOWN_OPCD,
HISI_SFLASH_UNKOWN_OPCD,
0,
0,
MV_S25FL_PAGE_SIZE,
MV_S25FL128_SECTOR_NUMBER,
MV_S25FL128_SECTOR_SIZE,
HISI_S25FL_PAGE_SIZE,
HISI_S25FL128_SECTOR_NUMBER,
HISI_S25FL128_SECTOR_SIZE,
"SPANSION S25FLXXX",
MV_SPANSION_MANF_ID,
HISI_SPANSION_MANF_ID,
0xffff,
0xff,
0xff,
0xff,
MV_S25FL128_MAX_SPI_FREQ,
MV_M25P128_MAX_FAST_SPI_FREQ,
MV_M25P128_FAST_READ_DUMMY_BYTES,
HISI_S25FL128_MAX_SPI_FREQ,
HISI_M25P128_MAX_FAST_SPI_FREQ,
HISI_M25P128_FAST_READ_DUMMY_BYTES,
SPI_FLASH_3BYTE_ADDR,
STANDARD_SPI_IF},
/* new add , ATMEL */
{
MV_AT25DF_WREN_CMND_OPCD,
MV_AT25DF_WRDI_CMND_OPCD,
MV_AT25DF_RDID_CMND_OPCD,
MV_AT25DF_RDSR_CMND_OPCD,
MV_AT25DF_WRSR_CMND_OPCD,
MV_AT25DF_READ_CMND_OPCD,
MV_AT25DF_FAST_RD_CMND_OPCD,
MV_AT25DF_PP_CMND_OPCD,
MV_AT25DF_SSE_CMND_OPCD,
MV_AT25DF_SE_CMND_OPCD,
MV_AT25DF_BE_CMND_OPCD,
MV_AT25DF_RES_CMND_OPCD,
MV_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */
MV_SFLASH_UNKOWN_OPCD, /* next code need see datasheet */
MV_SFLASH_UNKOWN_OPCD,
MV_SFLASH_UNKOWN_OPCD,
MV_SFLASH_UNKOWN_OPCD,
MV_SFLASH_UNKOWN_OPCD,
HISI_AT25DF_WREN_CMND_OPCD,
HISI_AT25DF_WRDI_CMND_OPCD,
HISI_AT25DF_RDID_CMND_OPCD,
HISI_AT25DF_RDSR_CMND_OPCD,
HISI_AT25DF_WRSR_CMND_OPCD,
HISI_AT25DF_READ_CMND_OPCD,
HISI_AT25DF_FAST_RD_CMND_OPCD,
HISI_AT25DF_PP_CMND_OPCD,
HISI_AT25DF_SSE_CMND_OPCD,
HISI_AT25DF_SE_CMND_OPCD,
HISI_AT25DF_BE_CMND_OPCD,
HISI_AT25DF_RES_CMND_OPCD,
HISI_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */
HISI_SFLASH_UNKOWN_OPCD, /* next code need see datasheet */
HISI_SFLASH_UNKOWN_OPCD,
HISI_SFLASH_UNKOWN_OPCD,
HISI_SFLASH_UNKOWN_OPCD,
HISI_SFLASH_UNKOWN_OPCD,
0,
0,
MV_AT25DF_PAGE_SIZE,
MV_AT25DF641_SECTOR_NUMBER,
MV_AT25DF641_SECTOR_SIZE,
HISI_AT25DF_PAGE_SIZE,
HISI_AT25DF641_SECTOR_NUMBER,
HISI_AT25DF641_SECTOR_SIZE,
"AT 25DFXX",
MV_AT25DFXXX_AT_MANF_ID,
HISI_AT25DFXXX_AT_MANF_ID,
0xffff,
0xff,
0xff,
0xff,
MV_AT25DF641_MAX_SPI_FREQ,
MV_AT25DF641_MAX_FAST_SPI_FREQ,
MV_AT25DF641_FAST_READ_DUMMY_BYTES,
HISI_AT25DF641_MAX_SPI_FREQ,
HISI_AT25DF641_MAX_FAST_SPI_FREQ,
HISI_AT25DF641_FAST_READ_DUMMY_BYTES,
SPI_FLASH_3BYTE_ADDR,
STANDARD_SPI_IF}
};
......@@ -683,7 +682,7 @@ s32 SFC_ClearInt(u64 reg_addr)
IntStatus = SFC_RegisterRead(reg_addr + (u32) INTRAWSTATUS);
if ((0 != (IntStatus & INT_MASK))) {
pr_err("[%s %d]: Int status=%u not cleared, clear\r\n",
pr_err("[SFC] [%s %d]: Int status=%x not cleared, clear\r\n",
__func__, __LINE__, IntStatus);
SFC_RegisterWrite(reg_addr + INTCLEAR, INT_MASK);
}
......@@ -708,7 +707,7 @@ s32 SFC_WaitInt(u64 reg_addr)
}
if (ulCount >= WAIT_MAX_COUNT) {
pr_err("[%s %d]: time out\n", __func__, __LINE__);
pr_err("[SFC] [%s %d]: time out\n", __func__, __LINE__);
return WAIT_TIME_OUT;
}
......@@ -803,7 +802,7 @@ s32 SFC_CheckBusy(struct SFC_SFLASH_INFO *sflash, u32 ulTimeOut)
ulRegValue = SFC_ReadStatus(sflash);
if (WAIT_TIME_OUT == ulRegValue) {
pr_err("[%s %d]: SFC_ReadStatus time out\n", __func__,
pr_err("[SFC] [%s %d]: SFC_ReadStatus time out\n", __func__,
__LINE__);
return HRD_ERR;
}
......@@ -815,15 +814,15 @@ s32 SFC_CheckBusy(struct SFC_SFLASH_INFO *sflash, u32 ulTimeOut)
ulRegValue = SFC_ReadStatus(sflash);
if (WAIT_TIME_OUT == ulRegValue) {
pr_err("[%s %d]: SFC_ReadStatus time out\n",
pr_err("[SFC] [%s %d]: SFC_ReadStatus time out\n",
__func__, __LINE__);
return HRD_ERR;
}
if ((sflash->manufacturerId == MV_SPANSION_MANF_ID)
if ((sflash->manufacturerId == HISI_SPANSION_MANF_ID)
&& (ulRegValue & (STATUS_REG_P_ERR | STATUS_REG_E_ERR))) {
pr_err
("[%s %d]: program err or erase err, status = %08x\n",
("[SFC] [%s %d]: program err or erase err, status = %08x\n",
__func__, __LINE__, ulRegValue);
return HRD_ERR;
}
......@@ -836,7 +835,7 @@ s32 SFC_CheckBusy(struct SFC_SFLASH_INFO *sflash, u32 ulTimeOut)
}
if (ulWaitCount >= ulTimeOut) {
pr_err("[%s %d]: SFC_CheckBusy time out\n", __func__, __LINE__);
pr_err("[SFC] [%s %d]: CheckBusy time out\n", __func__, __LINE__);
return WAIT_TIME_OUT;
}
......@@ -850,7 +849,7 @@ s32 SFC_ClearStatus(struct SFC_SFLASH_INFO *sflash)
(void)SFC_ClearInt(sflash->sfc_reg_base);
if (sflash->manufacturerId == MV_SPANSION_MANF_ID) {
if (sflash->manufacturerId == HISI_SPANSION_MANF_ID) {
/* 30 for spansion , clear status */
SFC_RegisterWrite(sflash->sfc_reg_base + CMD_INS, 0x30);
......@@ -885,12 +884,12 @@ s32 SFC_CheckErr(struct SFC_SFLASH_INFO *sflash)
{
u32 ulRegValue = 0;
if (sflash->manufacturerId == MV_SPANSION_MANF_ID) {
if (sflash->manufacturerId == HISI_SPANSION_MANF_ID) {
ulRegValue = SFC_ReadStatus(sflash);
if (WAIT_TIME_OUT == ulRegValue) {
pr_err("[%s %d]: SFC_ReadStatus time out\n", __func__,
pr_err("[SFC] [%s %d]: SFC_ReadStatus time out\n", __func__,
__LINE__);
return HRD_ERR;
}
......@@ -899,11 +898,11 @@ s32 SFC_CheckErr(struct SFC_SFLASH_INFO *sflash)
if (ulRegValue & (STATUS_REG_P_ERR | STATUS_REG_E_ERR)) {
pr_err
("[%s %d]: program err or erase err, status = %08x\n",
("[SFC] [%s %d]: program err or erase err, status = %08x\n",
__func__, __LINE__, ulRegValue);
if (HRD_OK != SFC_ClearStatus(sflash)) {
pr_err("[%s %d]: clear status failed\r\n",
pr_err("[SFC] [%s %d]: clear status failed\r\n",
__func__, __LINE__);
return HRD_ERR;
} else {
......@@ -917,37 +916,12 @@ s32 SFC_CheckErr(struct SFC_SFLASH_INFO *sflash)
return HRD_OK;
}
s32 SFC_ControllerAddrModeSet(struct SFC_SFLASH_INFO *sflash)
{
u32 ulTemp;
ulTemp = SFC_RegisterRead(sflash->sfc_reg_base + GLOBAL_CONFIG);
if (SPI_FLASH_3BYTE_ADDR == sflash->addr_mode) {
/* set 3Byte addr mode */
ulTemp &= ~(1 << API_ADDR_MODE);
} else if (SPI_FLASH_4BYTE_ADDR == sflash->addr_mode) {
/* set 4Byte addr mode */
ulTemp |= (1 << API_ADDR_MODE);
} else {
pr_err("[%s %d]: ulMode(%d) is invalid\n", __func__,
__LINE__, sflash->addr_mode);
return HRD_COMMON_ERR_INPUT_INVALID;
}
SFC_RegisterWrite(sflash->sfc_reg_base + GLOBAL_CONFIG, ulTemp);
return HRD_OK;
}
s32 SFC_BlockErase(struct SFC_SFLASH_INFO *sflash, u32 ulAddr, u32 ErCmd)
{
u32 ulRegValue;
s32 ulRet;
SFC_CheckErr(sflash);
ulRet = SFC_WriteEnable(sflash);
if (HRD_OK != ulRet) {
pr_err("[%s %d]: SFC_WriteEnable fail\n", __func__, __LINE__);
goto rel;
......@@ -969,14 +943,14 @@ s32 SFC_BlockErase(struct SFC_SFLASH_INFO *sflash, u32 ulAddr, u32 ErCmd)
ulRet = SFC_WaitInt(sflash->sfc_reg_base);
if (HRD_OK != ulRet) {
pr_err("[%s %d]: SFC_WaitInt fail\n", __func__, __LINE__);
pr_err("[SFC] [%s %d]: SFC_WaitInt fail\n", __func__, __LINE__);
goto rel;
}
ulRet = SFC_CheckBusy(sflash, WAIT_MAX_COUNT);
if (HRD_OK != ulRet) {
pr_err("[%s %d]: SFC_WaitInt fail\n", __func__, __LINE__);
pr_err("[SFC] [%s %d]: SFC_WaitInt fail\n", __func__, __LINE__);
goto rel;
}
......@@ -986,14 +960,21 @@ s32 SFC_BlockErase(struct SFC_SFLASH_INFO *sflash, u32 ulAddr, u32 ErCmd)
}
s32 SFC_RegWordRead(struct SFC_SFLASH_INFO *sflash,
u32 ulOffsetAddr, u32 *pulData)
static s32 SFC_RegWordAlignRead(struct SFC_SFLASH_INFO *sflash,
u32 ulOffsetAddr, u32 *pulData, u32 ulReadLen)
{
u32 i;
u32 ulDataCnt;
u32 ulRegValue;
s32 ulRet;
if (!ulReadLen || ulReadLen > SFC_HARD_BUF_LEN || (ulReadLen&0x3)) {
pr_err("[SFC] [%s %d]: len=%u err \n", __func__, __LINE__, ulReadLen);
return HRD_ERR;
}
ulDataCnt = ulReadLen>>2;
(void)SFC_ClearInt(sflash->sfc_reg_base);
SFC_CheckErr(sflash);
/* configure INS reg,send RDDATA operate */
SFC_RegisterWrite(sflash->sfc_reg_base + CMD_INS,
......@@ -1004,7 +985,7 @@ s32 SFC_RegWordRead(struct SFC_SFLASH_INFO *sflash,
ulRegValue = SFC_RegisterRead(sflash->sfc_reg_base + CMD_CONFIG);
ulRegValue &= (~(0xff << DATA_CNT) & (~(1 << SEL_CS)));
ulRegValue |=
(3 << DATA_CNT) | (1 << ADDR_EN) | (1 << DATA_EN) | (1 << RW_DATA)
((ulReadLen-1) << DATA_CNT) | (1 << ADDR_EN) | (1 << DATA_EN) | (1 << RW_DATA)
| (SFC_CHIP_CS << SEL_CS) | (0x1 << START);
wmb();
......@@ -1013,24 +994,25 @@ s32 SFC_RegWordRead(struct SFC_SFLASH_INFO *sflash,
ulRet = SFC_WaitInt(sflash->sfc_reg_base);
if (HRD_OK != ulRet) {
pr_err("[%s %d]: SFC_WaitInt fail\n", __func__, __LINE__);
pr_err("[SFC] [%s %d]: SFC_WaitInt fail\n", __func__, __LINE__);
return ulRet;
}
*pulData = SFC_RegisterRead(sflash->sfc_reg_base + DATABUFFER1);
for (i = 0; i < ulDataCnt; i++) {
pulData[i] = SFC_RegisterRead(sflash->sfc_reg_base + DATABUFFER1 + 4*i);
}
return ulRet;
}
s32 SFC_RegByteRead(struct SFC_SFLASH_INFO *sflash,
static s32 SFC_RegByteRead(struct SFC_SFLASH_INFO *sflash,
u32 ulOffsetAddr, u8 *pucData)
{
u32 ulRegValue;
s32 ulRet;
(void)SFC_ClearInt(sflash->sfc_reg_base);
SFC_CheckErr(sflash);
/* configure INS reg,send RDDATA operate */
SFC_RegisterWrite(sflash->sfc_reg_base + CMD_INS,
......@@ -1050,7 +1032,7 @@ s32 SFC_RegByteRead(struct SFC_SFLASH_INFO *sflash,
ulRet = SFC_WaitInt(sflash->sfc_reg_base);
if (HRD_OK != ulRet) {
pr_err("[%s %d]: SFC_WaitInt fail\n", __func__, __LINE__);
pr_err("[SFC] [%s %d]: SFC_WaitInt fail\n", __func__, __LINE__);
return ulRet;
}
......@@ -1059,32 +1041,43 @@ s32 SFC_RegByteRead(struct SFC_SFLASH_INFO *sflash,
return ulRet;
}
s32 SFC_RegWordWrite(struct SFC_SFLASH_INFO *sflash,
u32 ulData, u32 ulOffsetAddr)
/* 4bytes align, ulDataLen <=256 */
static s32 SFC_RegWordAlignWrite(struct SFC_SFLASH_INFO *sflash,
const u32 *ulData, u32 ulOffsetAddr, u32 ulWriteLen)
{
u32 i;
u32 ulDataCnt;
u32 ulRegValue;
s32 ulRet = HRD_OK;
/* u32 i = 0; */
SFC_CheckErr(sflash);
ulRet = SFC_WriteEnable(sflash);
if (!ulWriteLen || ulWriteLen > SFC_HARD_BUF_LEN || (ulWriteLen&0x3)) {
pr_err("[SFC] [%s %d]: len=%u err \n", __func__, __LINE__, ulWriteLen);
ulRet = HRD_ERR;
goto rel;
}
if (HRD_OK != ulRet) {
pr_err("[%s %d]: SFC_WriteEnable fail\n", __func__, __LINE__);
pr_err("[SFC] [%s %d]: SFC_WriteEnable fail\n", __func__, __LINE__);
goto rel;
}
SFC_RegisterWrite(sflash->sfc_reg_base + CMD_INS,
sflash->sflash_dev_params.ucOpcodePP);
SFC_RegisterWrite(sflash->sfc_reg_base + DATABUFFER1, ulData);
ulDataCnt = ulWriteLen>>2;
for (i = 0; i < ulDataCnt; i++) {
SFC_RegisterWrite(sflash->sfc_reg_base + DATABUFFER1+4*i, ulData[i]);
}
SFC_RegisterWrite(sflash->sfc_reg_base + CMD_ADDR, ulOffsetAddr);
/* set configure reg and startup */
ulRegValue = SFC_RegisterRead(sflash->sfc_reg_base + CMD_CONFIG);
ulRegValue &=
(~(0xff << DATA_CNT)) & (~(1 << RW_DATA) & (~(1 << SEL_CS)));
ulRegValue |= (3 << DATA_CNT) | (1 << ADDR_EN) | (1 << DATA_EN)
ulRegValue |= ((ulWriteLen-1) << DATA_CNT) | (1 << ADDR_EN) | (1 << DATA_EN)
| (SFC_CHIP_CS << SEL_CS) | (0x1 << START);
wmb();
......@@ -1093,7 +1086,7 @@ s32 SFC_RegWordWrite(struct SFC_SFLASH_INFO *sflash,
ulRet = SFC_WaitInt(sflash->sfc_reg_base);
if (HRD_OK != ulRet) {
pr_err("[%s %d]: SFC_WaitInt fail\n", __func__, __LINE__);
pr_err("[SFC] [%s %d]: SFC_WaitInt fail\n", __func__, __LINE__);
goto rel;
}
......@@ -1104,21 +1097,21 @@ s32 SFC_RegWordWrite(struct SFC_SFLASH_INFO *sflash,
rel:
SFC_FlashUnlock(sflash);
return ulRet;
}
s32 SFC_RegByteWrite(struct SFC_SFLASH_INFO *sflash,
static s32 SFC_RegByteWrite(struct SFC_SFLASH_INFO *sflash,
u8 ucData, u32 ulOffsetAddr)
{
u32 ulRegValue;
s32 ulRet = HRD_OK;
SFC_CheckErr(sflash);
ulRet = SFC_WriteEnable(sflash);
if (HRD_OK != ulRet) {
pr_err("[%s %d]: SFC_WriteEnable failed\r\n", __func__,
pr_err("[SFC] [%s %d]: SFC_WriteEnable failed\r\n", __func__,
__LINE__);
goto rel;
}
......@@ -1141,7 +1134,7 @@ s32 SFC_RegByteWrite(struct SFC_SFLASH_INFO *sflash,
ulRet = SFC_WaitInt(sflash->sfc_reg_base);
if (HRD_OK != ulRet) {
pr_err("[%s %d]: wait int failed\r\n", __func__, __LINE__);
pr_err("[SFC] [%s %d]: wait int failed\r\n", __func__, __LINE__);
goto rel;
}
......@@ -1165,39 +1158,28 @@ s32 SFC_RegModeWrite(struct SFC_SFLASH_INFO *sflash,
u32 ulRemain;
u32 ulAlignLen;
/* pr_info("SFC_RegModeWrite call\n"); */
if (!pucSrc) {
pr_err("[%s %d]: Pointer is null\n", __func__, __LINE__);
pr_err("[SFC] [%s %d]: Pointer is null\n", __func__, __LINE__);
return HRD_COMMON_ERR_NULL_POINTER;
}
if (ulWriteLen > sflash->space_size) {
pr_err("[%s %d]: ulReadLen is invalid\n", __func__, __LINE__);
pr_err("[SFC] [%s %d]: ulReadLen is invalid\n", __func__, __LINE__);
return HRD_COMMON_ERR_INPUT_INVALID;
}
/* reset controller adde mode, make sure different cs can work well */
ulRet = SFC_ControllerAddrModeSet(sflash);
if (HRD_OK != ulRet) {
pr_err("[%s %d]: SFC_ControllerAddrModeSet fail\n",
__func__, __LINE__);
return HRD_ERR;
}
ulRemain = ulWriteLen % 4;
SFC_CheckErr(sflash);
ulRemain = ulWriteLen % SFC_HARD_BUF_LEN;
ulAlignLen = ulWriteLen - ulRemain;
for (i = 0; i < ulAlignLen; i += 4) {
for (i = 0; i < ulAlignLen; i += SFC_HARD_BUF_LEN) {
ulRet =
SFC_RegWordWrite(sflash,
*(const u32 *)(pucSrc + i), offset + i);
SFC_RegWordAlignWrite(sflash,
(const u32 *)(pucSrc + i), offset + i, SFC_HARD_BUF_LEN);
if (HRD_OK != ulRet) {
pr_err
("[%s %d]: SFC_RegWordWrite fail\n",
("[SFC] [%s %d]: SFC_RegWordWrite fail\n",
__func__, __LINE__);
return ulRet;
}
......@@ -1207,6 +1189,18 @@ s32 SFC_RegModeWrite(struct SFC_SFLASH_INFO *sflash,
}
}
if (ulRemain >= 4) {
ulRet = SFC_RegWordAlignWrite(sflash, (const u32 *)(pucSrc + i), offset + i, ulRemain&(~0x3));
if (HRD_OK != ulRet) {
pr_err
("[SFC] [%s %d]: SFC_RegWordAlignWrite fail\n",
__func__, __LINE__);
return ulRet;
}
i += ulRemain&(~0x3);
}
for (; i < ulWriteLen; i++) {
ulRet =
SFC_RegByteWrite(sflash,
......@@ -1214,7 +1208,7 @@ s32 SFC_RegModeWrite(struct SFC_SFLASH_INFO *sflash,
if (HRD_OK != ulRet) {
pr_err
("[%s %d]: SFC_RegByteWrite fail\n",
("[SFC] [%s %d]: SFC_RegByteWrite fail\n",
__func__, __LINE__);
return ulRet;
}
......@@ -1223,132 +1217,47 @@ s32 SFC_RegModeWrite(struct SFC_SFLASH_INFO *sflash,
return HRD_OK;
}
s32 SFC_BusModeWrite(struct SFC_SFLASH_INFO *sflash,
u32 offset, const u8 *pucSrc, u32 ulWriteLen)
{
s32 ulRet;
u32 ulRemain;
u32 ulAlignLen;
u32 i;
/* pr_info("SFC_BusModeWrite call\n"); */
if (!sflash || !pucSrc) {
pr_err("[%s %d]: Pointer is null\n", __func__, __LINE__);
return HRD_COMMON_ERR_NULL_POINTER;
}
if (ulWriteLen > sflash->space_size) {
pr_err("[%s %d]: ulReadLen is invalid\n", __func__, __LINE__);
return HRD_COMMON_ERR_INPUT_INVALID;
}
/* reset controller adde mode, make sure different cs can work well */
ulRet = SFC_ControllerAddrModeSet(sflash);
ulRemain = ulWriteLen % 4;
ulAlignLen = ulWriteLen - ulRemain;
for (i = 0; i < ulAlignLen; i += 4) {
*(__iomem u32 *) (sflash->baseAddr + offset +
i) = *(const u32 *)(pucSrc + i);
if ((i > 0) && (i % 65536 == 0)) {
msleep(1);
continue;
}
}
for (; i < ulWriteLen; i++) {
*(__iomem u8 *) (sflash->baseAddr + offset +
i) = *(const u8 *)(pucSrc + i);
}
return ulRet;
}
s32 SFC_RegModeRead(struct SFC_SFLASH_INFO *sflash,
u32 offset, u8 *pucDest, u32 ulReadLen)
{
u32 i;
s32 ulRet;
u32 ulRemain;
u32 ulAlignLen;
/* pr_info("SFC_RegModeRead call\n"); */
if (!sflash || !pucDest) {
pr_err("[%s %d]: Pointer is null\n", __func__, __LINE__);
pr_err("[SFC] [%s %d]: Pointer is null\n", __func__, __LINE__);
return HRD_COMMON_ERR_NULL_POINTER;
}
if (ulReadLen > sflash->space_size) {
pr_err("[%s %d]: ulReadLen is invalid\n", __func__, __LINE__);
pr_err("[SFC] [%s %d]: ulReadLen is invalid\n", __func__, __LINE__);
return HRD_COMMON_ERR_INPUT_INVALID;
}
/* reset controller adde mode, make sure different cs can work well */
ulRet = SFC_ControllerAddrModeSet(sflash);
if (HRD_OK != ulRet) {
pr_err("[%s %d]: SFC_ControllerAddrModeSet fail\n",
__func__, __LINE__);
return HRD_ERR;
}
ulRemain = ulReadLen % 4;
SFC_CheckErr(sflash);
ulRemain = ulReadLen % SFC_HARD_BUF_LEN;
ulAlignLen = ulReadLen - ulRemain;
for (i = 0; i < ulAlignLen; i += 4) {
(void)SFC_RegWordRead(sflash, offset + i,
(u32 *) (pucDest + i));
}
for (; i < ulReadLen; i++) {
(void)SFC_RegByteRead(sflash, offset + i, pucDest + i);
}
return HRD_OK;
}
s32 SFC_BusModeRead(struct SFC_SFLASH_INFO *sflash,
u32 offset, u8 *pucDest, u32 ulReadLen)
{
s32 ulRet;
u32 i;
u32 ulRemain;
u32 ulAlignLen;
/* pr_info("SFC_BusModeRead call\n"); */
if (!sflash || !pucDest) {
pr_err("[%s %d]: Pointer is null\n", __func__, __LINE__);
return HRD_COMMON_ERR_NULL_POINTER;
}
if (ulReadLen > sflash->space_size) {
pr_err("[%s %d]: ulReadLen is invalid\n", __func__, __LINE__);
return HRD_COMMON_ERR_INPUT_INVALID;
for (i = 0; i < ulAlignLen; i += SFC_HARD_BUF_LEN) {
(void)SFC_RegWordAlignRead(sflash, offset + i,
(u32 *) (pucDest + i), SFC_HARD_BUF_LEN);
}
/* reset controller adde mode, make sure different cs can work well */
ulRet = SFC_ControllerAddrModeSet(sflash);
ulRemain = ulReadLen % 4;
if (ulRemain >= 4) {
ulAlignLen = ulReadLen - ulRemain;
for (i = 0; i < ulAlignLen; i += 4) {
*(u32 *) (pucDest + i) =
*(__iomem u32 *) (sflash->baseAddr + offset + i);
(void)SFC_RegWordAlignRead(sflash, offset + i,
(u32 *) (pucDest + i), ulRemain&(~0x3));
i += ulRemain&(~0x3);
}
for (; i < ulReadLen; i++) {
*(u8 *) (pucDest + i) =
*(__iomem u8 *) (sflash->baseAddr + offset + i);
(void)SFC_RegByteRead(sflash, offset + i, pucDest + i);
}
return ulRet;
return HRD_OK;
}
s32 SFC_CheckCmdExcStatus(struct SFC_SFLASH_INFO *sflash)
......@@ -1363,7 +1272,7 @@ s32 SFC_CheckCmdExcStatus(struct SFC_SFLASH_INFO *sflash)
timeout--;
if (0 == timeout) {
pr_err("%s (%d):Check cmd execute status time out!\n",
pr_err("[SFC] %s (%d):Check cmd execute status time out!\n",
__func__, __LINE__);
return HRD_ERR;
}
......@@ -1384,7 +1293,7 @@ s32 SFC_SPIFlashIdGet(struct SFC_SFLASH_INFO *pFlinfo,
u32 readid_cmd;
if (!pulManuId || !pulDevId) {
pr_err("[%s %d]: input params is invalid\n", __func__,
pr_err("[SFC] [%s %d]: input params is invalid\n", __func__,
__LINE__);
return HRD_COMMON_ERR_NULL_POINTER;
}
......@@ -1412,14 +1321,14 @@ s32 SFC_SPIFlashIdGet(struct SFC_SFLASH_INFO *pFlinfo,
ulRet = SFC_WaitInt(pFlinfo->sfc_reg_base);
if (HRD_OK != ulRet) {
pr_err("[%s %d]: wait int failed\r\n", __func__, __LINE__);
pr_err("[SFC] [%s %d]: wait int failed\r\n", __func__, __LINE__);
return WAIT_TIME_OUT;
}
ulRet = SFC_CheckCmdExcStatus(pFlinfo);
if (ulRet) {
pr_err("[%s %d]: cmd execute timeout\r\n", __func__, __LINE__);
pr_err("[SFC] [%s %d]: cmd execute timeout\r\n", __func__, __LINE__);
return WAIT_TIME_OUT;
}
......@@ -1438,36 +1347,13 @@ s32 SFC_SPIFlashIdGet(struct SFC_SFLASH_INFO *pFlinfo,
*pfid = (ulRegValue >> 8) & 0xff;
pr_info
("[%s %d]:ulManuId=0x%x, ulDevId=0x%x cfi_len=0x%x, sec_arch=0x%x, fid=0x%x\n",
("[SFC] [%s %d]:ulManuId=0x%x, ulDevId=0x%x cfi_len=0x%x, sec_arch=0x%x, fid=0x%x\n",
__func__, __LINE__, *pulManuId, *pulDevId, *pcfi_len, *psec_arch,
*pfid);
return HRD_OK;
}
void CPLD_WPSet(u32 val)
{
int ret;
u8 value;
u32 RegAddr = CPLD_WP_REG;
ret = lbc_read8(1, RegAddr, &value);
if (0 != ret) {
pr_err("[%s %d]: lbc_read8 fail\r\n", __func__, __LINE__);
return;
}
if (val) {
value &= (~BIT0);
} else {
value |= BIT0;
}
(void)lbc_write8(1, RegAddr, value);
return;
}
int SFC_WaitFlashIdle(struct SFC_SFLASH_INFO *sflash)
{
union UN_SFC_CMD_CONFIG temp;
......@@ -1493,7 +1379,7 @@ int SFC_WaitFlashIdle(struct SFC_SFLASH_INFO *sflash)
ret = SFC_CheckCmdExcStatus(sflash);
if (HRD_OK != ret) {
pr_err("[%s %d]: cmd execute timeout\r\n", __func__,
pr_err("[SFC] [%s %d]: cmd execute timeout\r\n", __func__,
__LINE__);
return ret;
}
......@@ -1508,7 +1394,7 @@ int SFC_WaitFlashIdle(struct SFC_SFLASH_INFO *sflash)
udelay((unsigned long)20);
} while (timeout--);
pr_err("[%s %d]: Write in progress!\r\n", __func__, __LINE__);
pr_err("[SFC] [%s %d]: Write in progress!\r\n", __func__, __LINE__);
return HRD_ERR;
}
......@@ -1538,31 +1424,16 @@ int SFC_GetDeviceId(struct SFC_SFLASH_INFO *sflash, u32 *id)
ret = SFC_CheckCmdExcStatus(sflash);
if (HRD_OK != ret) {
pr_err("%s %d\n", __func__, __LINE__);
pr_err("[SFC] %s %d\n", __func__, __LINE__);
return ret;
}
*id = SFC_RegisterRead(sflash->sfc_reg_base + DATABUFFER1);
pr_info("%s(%d):get_device_id: 0x%x !\n", __func__, __LINE__, *id);
pr_info("[SFC] %s(%d):get_device_id: 0x%x !\n", __func__, __LINE__, *id);
return ret;
}
static void SFC_SetBusMode(struct SFC_SFLASH_INFO *sflash, BOOL val)
{
/*shuwdown the bus mode */
if (!val) {
SFC_RegisterWrite(sflash->sfc_reg_base + BUS_CONFIG1,
0x00800300);
} else {
SFC_RegisterWrite(sflash->sfc_reg_base + BUS_CONFIG1,
0x80800300);
}
}
static int MirconWPSet(struct SFC_SFLASH_INFO *sflash, BOOL val)
{
int ret = HRD_OK;
......@@ -1574,7 +1445,7 @@ static int MirconWPSet(struct SFC_SFLASH_INFO *sflash, BOOL val)
ret = SFC_WriteEnable(sflash);
if (HRD_OK != ret) {
pr_err("[%s %d]: SFC_WriteEnable fail\n", __func__,
pr_err("[SFC] [%s %d]: SFC_WriteEnable fail\n", __func__,
__LINE__);
return ret;
}
......@@ -1607,7 +1478,7 @@ static int SpansionWPSet(struct SFC_SFLASH_INFO *sflash, BOOL val)
ret = SFC_CheckCmdExcStatus(sflash);
if (HRD_OK != ret) {
pr_err("[%s %d]: SFC_CheckCmdExcStatus fail\n",
pr_err("[SFC] [%s %d]: SFC_CheckCmdExcStatus fail\n",
__func__, __LINE__);
return ret;
}
......@@ -1617,7 +1488,7 @@ static int SpansionWPSet(struct SFC_SFLASH_INFO *sflash, BOOL val)
ret = SFC_WaitFlashIdle(sflash);
if (HRD_OK != ret) {
pr_err("[%s %d]: SFC_WaitFlashIdle fail\n", __func__,
pr_err("[SFC] [%s %d]: SFC_WaitFlashIdle fail\n", __func__,
__LINE__);
return ret;
}
......@@ -1626,7 +1497,7 @@ static int SpansionWPSet(struct SFC_SFLASH_INFO *sflash, BOOL val)
ret = SFC_WriteEnable(sflash);
if (HRD_OK != ret) {
pr_err("[%s %d]: SFC_WriteEnable fail\n", __func__,
pr_err("[SFC] [%s %d]: SFC_WriteEnable fail\n", __func__,
__LINE__);
return ret;
}
......@@ -1652,14 +1523,14 @@ static int MxicWPSet(struct SFC_SFLASH_INFO *sflash, BOOL val)
if (WAIT_TIME_OUT == status) {
ret = HRD_ERR;
pr_err("[%s %d]: SFC_ReadStatus time out\n", __func__,
pr_err("[SFC] [%s %d]: SFC_ReadStatus time out\n", __func__,
__LINE__);
return ret;
}
if (((status >> 1) & 0x1) != 1) {
ret = HRD_ERR;
pr_err("[%s %d]: Write enable fail\n", __func__, __LINE__);
pr_err("[SFC] [%s %d]: Write enable fail\n", __func__, __LINE__);
return ret;
}
......@@ -1685,7 +1556,7 @@ static int MxicWPSet(struct SFC_SFLASH_INFO *sflash, BOOL val)
if (WAIT_TIME_OUT == status) {
ret = HRD_ERR;
pr_err("[%s %d]: SFC_ReadStatus time out\n", __func__,
pr_err("[SFC] [%s %d]: SFC_ReadStatus time out\n", __func__,
__LINE__);
return ret;
}
......@@ -1693,7 +1564,7 @@ static int MxicWPSet(struct SFC_SFLASH_INFO *sflash, BOOL val)
/* check status register data */
if (((status >> 1) & 0x1) == 1) {
ret = HRD_ERR;
pr_err("[%s %d]: Value of write enable latch bit error\n",
pr_err("[SFC] [%s %d]: Value of write enable latch bit error\n",
__func__, __LINE__);
return ret;
}
......@@ -1701,7 +1572,7 @@ static int MxicWPSet(struct SFC_SFLASH_INFO *sflash, BOOL val)
if (val) {
if (((status >> 2) & 0xF) != 0xF) {
ret = HRD_ERR;
pr_err("[%s %d]: Set to protect all blocks failed\n",
pr_err("[SFC] [%s %d]: Set to protect all blocks failed\n",
__func__, __LINE__);
return ret;
}
......@@ -1709,7 +1580,7 @@ static int MxicWPSet(struct SFC_SFLASH_INFO *sflash, BOOL val)
if (((status >> 2) & 0xF) != 0x0) {
ret = HRD_ERR;
pr_err
("[%s %d]: Set to not protect any blocks failed\n",
("[SFC] [%s %d]: Set to not protect any blocks failed\n",
__func__, __LINE__);
return ret;
}
......@@ -1731,26 +1602,18 @@ int SFC_WPSet(struct SFC_SFLASH_INFO *sflash, BOOL val)
int ret;
bool isFlashLock = false;
SFC_SetBusMode(sflash, val);
udelay((unsigned long)1000);
(void)SFC_ClearInt(sflash->sfc_reg_base);
(void)SFC_CheckErr(sflash);
/* First try to read the Manufacturer and Device IDs */
ret = SFC_GetDeviceId(sflash, &device_id);
retval_if_fail(ret, "Failed to get the SFlash ID!\n");
udelay((unsigned long)100);
CPLD_WPSet((unsigned int)0);
udelay((unsigned long)20);
retval_if_fail(ret, "[SFC] Failed to get the SFlash ID!\n");
ret = SFC_WaitFlashIdle(sflash);
if (HRD_OK != ret) {
pr_err("[%s %d]: SFC_WaitFlashIdle fail\n", __func__, __LINE__);
pr_err("[SFC][%s %d]: SFC_WaitFlashIdle fail\n", __func__, __LINE__);
goto error;
}
......@@ -1758,30 +1621,30 @@ int SFC_WPSet(struct SFC_SFLASH_INFO *sflash, BOOL val)
isFlashLock = true;
if (HRD_OK != ret) {
pr_err("[%s %d]: SFC_WriteEnable fail\n", __func__, __LINE__);
pr_err("[SFC] [%s %d]: SFC_WriteEnable fail\n", __func__, __LINE__);
goto error;
}
if (MV_M25PXXX_ST_MANF_ID == (u8) (device_id)) {
if (HISI_M25PXXX_ST_MANF_ID == (u8) (device_id)) {
ret = MirconWPSet(sflash, val);
if (HRD_OK != ret) {
goto error;
}
} else if (MV_SPANSION_MANF_ID == (u8) (device_id)) {
} else if (HISI_SPANSION_MANF_ID == (u8) (device_id)) {
ret = SpansionWPSet(sflash, val);
if (HRD_OK != ret) {
goto error;
}
} else if (MV_MX25U12835F_MANF_ID == (u8) (device_id)) {
} else if (HISI_MX25U12835F_MANF_ID == (u8) (device_id)) {
ret = MxicWPSet(sflash, val);
if (HRD_OK != ret) {
goto error;
}
} else {
pr_err("[%s %d]: not support devid=0x%08x\n", __func__,
pr_err("[SFC] [%s %d]: not support devid=0x%08x\n", __func__,
__LINE__, device_id);
ret = HRD_ERR;
goto error;
......@@ -1792,7 +1655,7 @@ int SFC_WPSet(struct SFC_SFLASH_INFO *sflash, BOOL val)
ret = SFC_CheckCmdExcStatus(sflash);
if (HRD_OK != ret) {
pr_err("[%s %d]: SFC_CheckCmdExcStatus fail\n", __func__,
pr_err("[SFC] [%s %d]: SFC_CheckCmdExcStatus fail\n", __func__,
__LINE__);
goto error;
}
......@@ -1800,23 +1663,16 @@ int SFC_WPSet(struct SFC_SFLASH_INFO *sflash, BOOL val)
ret = SFC_WaitFlashIdle(sflash);
if (HRD_OK != ret) {
pr_err("[%s %d]: SFC_WaitFlashIdle fail\n", __func__, __LINE__);
pr_err("[SFC] [%s %d]: SFC_WaitFlashIdle fail\n", __func__, __LINE__);
goto error;
}
if (TRUE == val) {
CPLD_WPSet(val);
}
SFC_FlashUnlock(sflash);
return ret;
error:
CPLD_WPSet(TRUE);
/*enable bus mode write */
SFC_SetBusMode(sflash, 1);
if (isFlashLock) {
SFC_FlashUnlock(sflash);
}
......@@ -1824,24 +1680,6 @@ int SFC_WPSet(struct SFC_SFLASH_INFO *sflash, BOOL val)
return ret;
}
u32 SFC_ControllerInit(u64 sfc_reg_base)
{
u32 ulRegValue;
/* use default 128Mbit SPI FLASH large */
u32 ulSFlashSizeIndex = 0x09;
ulRegValue = SFC_RegisterRead(sfc_reg_base + (u32) BUS_FLASH_SIZE);
ulRegValue &= (~((u32) 0xf << FLASH_SIZE_CS_BIT(SFC_CHIP_CS)));
ulRegValue |= (ulSFlashSizeIndex << FLASH_SIZE_CS_BIT(SFC_CHIP_CS));
SFC_RegisterWrite(sfc_reg_base + (u32) BUS_FLASH_SIZE, ulRegValue);
ulRegValue = SFC_RegisterRead(sfc_reg_base + BUS_CONFIG1);
ulRegValue &= ~(1 << WR_ENABLE);
SFC_RegisterWrite(sfc_reg_base + BUS_CONFIG1, ulRegValue);
return HRD_OK;
}
#define CMPEXTERNID(indx, cfi_len, sec_arch, fid) \
(((g_stSPIFlashDevTable[indx].ulIdCFILen != 0xff) ? (g_stSPIFlashDevTable[indx].ulIdCFILen == cfi_len) : 1) && \
((g_stSPIFlashDevTable[indx].ulPhySecArch != 0xff) ? (g_stSPIFlashDevTable[indx].ulPhySecArch == sec_arch) : 1) && \
......@@ -1860,7 +1698,7 @@ int hrd_sflash_init(struct SFC_SFLASH_INFO *pFlinfo)
/* check for NULL pointer */
if (pFlinfo == NULL) {
pr_err("%s HRD_ERR: Null pointer parameter!\n", __func__);
pr_err("[SFC] %s HRD_ERR: Null pointer parameter!\n", __func__);
return HRD_COMMON_ERR_INPUT_INVALID;
}
......@@ -1869,7 +1707,7 @@ int hrd_sflash_init(struct SFC_SFLASH_INFO *pFlinfo)
SFC_SPIFlashIdGet(pFlinfo, &manf, &dev, &cfi_len, &sec_arch, &fid);
if (ret != HRD_OK) {
pr_err("%s HRD_ERR: Failed to get the SFlash ID!\n", __func__);
pr_err("[SFC] %s HRD_ERR: Failed to get the SFlash ID!\n", __func__);
return ret;
}
......@@ -1893,14 +1731,11 @@ int hrd_sflash_init(struct SFC_SFLASH_INFO *pFlinfo)
if (!detectFlag) {
pr_err
("%s HRD_ERR: manf:0x%x, dev:0x%x, Unknown SPI flash device!\n",
("[SFC] %s HRD_ERR: manf:0x%x, dev:0x%x, Unknown SPI flash device!\n",
__func__, manf, dev);
return HRD_ERR;
}
/* init SPI FLASH Controller */
(void)SFC_ControllerInit(pFlinfo->sfc_reg_base);
/* fill the info based on the model detected */
pFlinfo->sectorSize = g_stSPIFlashDevTable[pFlinfo->index].ulBlockSize;
pFlinfo->sectorNumber =
......@@ -1910,7 +1745,7 @@ int hrd_sflash_init(struct SFC_SFLASH_INFO *pFlinfo)
memcpy(&pFlinfo->sflash_dev_params,
&g_stSPIFlashDevTable[pFlinfo->index],
sizeof(struct SPI_FLASH_DEVICE_PARAMS));
DB(pr_info("%s rw_mode %d\n", __func__, pFlinfo->rw_mode));
DB(pr_debug("[SFC] %s rw_mode %d\n", __func__, pFlinfo->rw_mode));
return ret;
}
drivers/mtd/hisilicon/sfc/hrd_sflash_hal.h
浏览文件 @ 24c1d66a
......@@ -131,7 +131,7 @@
#define DATABUFFER6 CMD_DATABUF(6)
#define DATABUFFER7 CMD_DATABUF(7)
#define DATABUFFER8 CMD_DATABUF(8)
#define SFC_HARD_BUF_LEN (64)
#define SFC_HARD_BUF_LEN (256)
/* GLOBAL_CONFIG */
#define RD_DELAY 3
......@@ -201,19 +201,14 @@ union UN_SFC_CMD_CONFIG {
unsigned int u32;
};
extern u32 SFC_ControllerInit(u64 sfc_reg_base);
extern s32 SFC_CheckErr(struct SFC_SFLASH_INFO *sflash);
extern s32 SFC_RegModeRead(struct SFC_SFLASH_INFO *sflash, u32 offset,
u8 *pucDest, u32 ulReadLen);
extern s32 SFC_BusModeRead(struct SFC_SFLASH_INFO *sflash, u32 offset,
u8 *pucDest, u32 ulReadLen);
extern s32 SFC_RegModeWrite(struct SFC_SFLASH_INFO *sflash, u32 offset,
const u8 *pucSrc, u32 ulWriteLen);
extern s32 SFC_BusModeWrite(struct SFC_SFLASH_INFO *sflash, u32 offset,
const u8 *pucSrc, u32 ulWriteLen);
extern s32 SFC_SPIFlashIdGet(struct SFC_SFLASH_INFO *pFlinfo,
u8 *pulManuId, u16 *pulDevId, u8 *pcfi_len,
u8 *psec_arch, u8 *pfid);
extern s32 SFC_ControllerAddrModeSet(struct SFC_SFLASH_INFO *pFlinfo);
extern s32 SFC_BlockErase(struct SFC_SFLASH_INFO *sflash, u32 ulAddr,
u32 ErCmd);
extern int hrd_sflash_init(struct SFC_SFLASH_INFO *pFlinfo);
......
drivers/mtd/hisilicon/sfc/hrd_sflash_spec.h
浏览文件 @ 24c1d66a
......@@ -23,361 +23,361 @@
#define SFLASH_DEFAULT_WREN_OPCD 0x06 /* Default Write Enable */
/* Constants */
#define MV_SFLASH_READ_CMND_LENGTH 4 /* 1B opcode + 3B address */
#define MV_SFLASH_SE_CMND_LENGTH 4 /* 1B opcode + 3B address */
#define MV_SFLASH_BE_CMND_LENGTH 1 /* 1B opcode */
#define MV_SFLASH_PP_CMND_LENGTH 4 /* 1B opcode + 3B address */
#define MV_SFLASH_WREN_CMND_LENGTH 1 /* 1B opcode */
#define MV_SFLASH_WRDI_CMND_LENGTH 1 /* 1B opcode */
#define MV_SFLASH_RDID_CMND_LENGTH 1 /* 1B opcode */
#define HISI_SFLASH_READ_CMND_LENGTH 4 /* 1B opcode + 3B address */
#define HISI_SFLASH_SE_CMND_LENGTH 4 /* 1B opcode + 3B address */
#define HISI_SFLASH_BE_CMND_LENGTH 1 /* 1B opcode */
#define HISI_SFLASH_PP_CMND_LENGTH 4 /* 1B opcode + 3B address */
#define HISI_SFLASH_WREN_CMND_LENGTH 1 /* 1B opcode */
#define HISI_SFLASH_WRDI_CMND_LENGTH 1 /* 1B opcode */
#define HISI_SFLASH_RDID_CMND_LENGTH 1 /* 1B opcode */
/* 1B manf ID and 2B device ID */
#define MV_SFLASH_RDID_REPLY_LENGTH 3
#define MV_SFLASH_RDSR_CMND_LENGTH 1 /* 1B opcode */
#define MV_SFLASH_RDSR_REPLY_LENGTH 1 /* 1B status */
#define HISI_SFLASH_RDID_REPLY_LENGTH 3
#define HISI_SFLASH_RDSR_CMND_LENGTH 1 /* 1B opcode */
#define HISI_SFLASH_RDSR_REPLY_LENGTH 1 /* 1B status */
/* 1B opcode + 1B status value */
#define MV_SFLASH_WRSR_CMND_LENGTH 2
#define MV_SFLASH_DP_CMND_LENGTH 1 /* 1B opcode */
#define MV_SFLASH_RES_CMND_LENGTH 1 /* 1B opcode */
#define HISI_SFLASH_WRSR_CMND_LENGTH 2
#define HISI_SFLASH_DP_CMND_LENGTH 1 /* 1B opcode */
#define HISI_SFLASH_RES_CMND_LENGTH 1 /* 1B opcode */
/* Status Register Bit Masks */
/* bit 0; write in progress */
#define MV_SFLASH_STATUS_REG_WIP_OFFSET 0
#define HISI_SFLASH_STATUS_REG_WIP_OFFSET 0
/* bit 2-4; write protect option */
#define MV_SFLASH_STATUS_REG_WP_OFFSET 2
#define HISI_SFLASH_STATUS_REG_WP_OFFSET 2
/* bit 7; lock status register write */
#define MV_SFLASH_STATUS_REG_SRWD_OFFSET 7
#define MV_SFLASH_STATUS_REG_WIP_MASK \
(0x1 << MV_SFLASH_STATUS_REG_WIP_OFFSET)
#define MV_SFLASH_STATUS_REG_SRWD_MASK \
(0x1 << MV_SFLASH_STATUS_REG_SRWD_OFFSET)
#define HISI_SFLASH_STATUS_REG_SRWD_OFFSET 7
#define HISI_SFLASH_STATUS_REG_WIP_MASK \
(0x1 << HISI_SFLASH_STATUS_REG_WIP_OFFSET)
#define HISI_SFLASH_STATUS_REG_SRWD_MASK \
(0x1 << HISI_SFLASH_STATUS_REG_SRWD_OFFSET)
#define MV_SFLASH_MAX_WAIT_LOOP 1000000
#define MV_SFLASH_CHIP_ERASE_MAX_WAIT_LOOP 0x50000000
#define HISI_SFLASH_MAX_WAIT_LOOP 1000000
#define HISI_SFLASH_CHIP_ERASE_MAX_WAIT_LOOP 0x50000000
#define MV_SFLASH_DEFAULT_RDID_OPCD 0x9F /* Default Read ID */
#define MV_SFLASH_DEFAULT_WREN_OPCD 0x06 /* Default Write Enable */
#define MV_SFLASH_NO_SPECIFIC_OPCD 0x00
#define MV_SFLASH_UNKOWN_OPCD 0xFF
#define HISI_SFLASH_DEFAULT_RDID_OPCD 0x9F /* Default Read ID */
#define HISI_SFLASH_DEFAULT_WREN_OPCD 0x06 /* Default Write Enable */
#define HISI_SFLASH_NO_SPECIFIC_OPCD 0x00
#define HISI_SFLASH_UNKOWN_OPCD 0xFF
/********************************/
/* ST M25Pxxx Device Specific */
/********************************/
/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */
#define MV_M25PXXX_ST_MANF_ID 0x20
#define MV_M25P80_DEVICE_ID 0x2014
#define MV_M25P80_MAX_SPI_FREQ 20000000 /* 20MHz */
#define MV_M25P80_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */
#define MV_M25P80_FAST_READ_DUMMY_BYTES 1
#define MV_M25P32_DEVICE_ID 0x2016
#define MV_M25P32_MAX_SPI_FREQ 20000000 /* 20MHz */
#define MV_M25P32_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */
#define MV_M25P32_FAST_READ_DUMMY_BYTES 1
#define MV_M25P64_DEVICE_ID 0x2017
#define MV_M25P64_MAX_SPI_FREQ 20000000 /* 20MHz */
#define MV_M25P64_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */
#define MV_M25P64_FAST_READ_DUMMY_BYTES 1
#define MV_M25P128_DEVICE_ID 0x2018
#define MV_M25P128_MAX_SPI_FREQ 20000000 /* 20MHz */
#define MV_M25P128_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */
#define MV_M25P128_FAST_READ_DUMMY_BYTES 1
#define HISI_M25PXXX_ST_MANF_ID 0x20
#define HISI_M25P80_DEVICE_ID 0x2014
#define HISI_M25P80_MAX_SPI_FREQ 20000000 /* 20MHz */
#define HISI_M25P80_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */
#define HISI_M25P80_FAST_READ_DUMMY_BYTES 1
#define HISI_M25P32_DEVICE_ID 0x2016
#define HISI_M25P32_MAX_SPI_FREQ 20000000 /* 20MHz */
#define HISI_M25P32_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */
#define HISI_M25P32_FAST_READ_DUMMY_BYTES 1
#define HISI_M25P64_DEVICE_ID 0x2017
#define HISI_M25P64_MAX_SPI_FREQ 20000000 /* 20MHz */
#define HISI_M25P64_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */
#define HISI_M25P64_FAST_READ_DUMMY_BYTES 1
#define HISI_M25P128_DEVICE_ID 0x2018
#define HISI_M25P128_MAX_SPI_FREQ 20000000 /* 20MHz */
#define HISI_M25P128_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */
#define HISI_M25P128_FAST_READ_DUMMY_BYTES 1
/* Sector Sizes and population per device model*/
#define MV_M25P80_SECTOR_SIZE 0x10000 /* 64K */
#define MV_M25P32_SECTOR_SIZE 0x10000 /* 64K */
#define MV_M25P64_SECTOR_SIZE 0x10000 /* 64K */
#define MV_M25P128_SECTOR_SIZE 0x40000 /* 256K */
#define MV_M25P80_SECTOR_NUMBER 16
#define MV_M25P32_SECTOR_NUMBER 64
#define MV_M25P64_SECTOR_NUMBER 128
#define MV_M25P128_SECTOR_NUMBER 64
#define MV_M25P_PAGE_SIZE 0x100 /* 256 byte */
#define MV_M25P_WREN_CMND_OPCD 0x06 /* Write Enable */
#define MV_M25P_WRDI_CMND_OPCD 0x04 /* Write Disable */
#define MV_M25P_RDID_CMND_OPCD 0x9F /* Read ID */
#define HISI_M25P80_SECTOR_SIZE 0x10000 /* 64K */
#define HISI_M25P32_SECTOR_SIZE 0x10000 /* 64K */
#define HISI_M25P64_SECTOR_SIZE 0x10000 /* 64K */
#define HISI_M25P128_SECTOR_SIZE 0x40000 /* 256K */
#define HISI_M25P80_SECTOR_NUMBER 16
#define HISI_M25P32_SECTOR_NUMBER 64
#define HISI_M25P64_SECTOR_NUMBER 128
#define HISI_M25P128_SECTOR_NUMBER 64
#define HISI_M25P_PAGE_SIZE 0x100 /* 256 byte */
#define HISI_M25P_WREN_CMND_OPCD 0x06 /* Write Enable */
#define HISI_M25P_WRDI_CMND_OPCD 0x04 /* Write Disable */
#define HISI_M25P_RDID_CMND_OPCD 0x9F /* Read ID */
/* Read Status Register */
#define MV_M25P_RDSR_CMND_OPCD 0x05
#define HISI_M25P_RDSR_CMND_OPCD 0x05
/* Write Status Register */
#define MV_M25P_WRSR_CMND_OPCD 0x01
#define MV_M25P_READ_CMND_OPCD 0x03 /* Sequential Read */
#define MV_M25P_FAST_RD_CMND_OPCD 0x0B /* Fast Read */
#define MV_M25P_PP_CMND_OPCD 0x02 /* Page Program */
#define MV_M25P_SSE_CMND_OPCD 0x20 /* SubSectorErase */
#define MV_M25P_SE_CMND_OPCD 0xD8 /* Sector Erase */
#define MV_M25P_BE_CMND_OPCD 0xC7 /* Bulk Erase */
#define HISI_M25P_WRSR_CMND_OPCD 0x01
#define HISI_M25P_READ_CMND_OPCD 0x03 /* Sequential Read */
#define HISI_M25P_FAST_RD_CMND_OPCD 0x0B /* Fast Read */
#define HISI_M25P_PP_CMND_OPCD 0x02 /* Page Program */
#define HISI_M25P_SSE_CMND_OPCD 0x20 /* SubSectorErase */
#define HISI_M25P_SE_CMND_OPCD 0xD8 /* Sector Erase */
#define HISI_M25P_BE_CMND_OPCD 0xC7 /* Bulk Erase */
/* Read Electronic Signature */
#define MV_M25P_RES_CMND_OPCD 0xAB
#define HISI_M25P_RES_CMND_OPCD 0xAB
/* Status Register Write Protect Bit Masks - 3bits */
#define MV_M25P_STATUS_REG_WP_MASK (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define MV_M25P_STATUS_BP_NONE (0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define MV_M25P_STATUS_BP_1_OF_64 (0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define MV_M25P_STATUS_BP_1_OF_32 (0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define MV_M25P_STATUS_BP_1_OF_16 (0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define MV_M25P_STATUS_BP_1_OF_8 (0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define MV_M25P_STATUS_BP_1_OF_4 (0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define MV_M25P_STATUS_BP_1_OF_2 (0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define MV_M25P_STATUS_BP_ALL (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define HISI_M25P_STATUS_REG_WP_MASK (0x07 << HISI_SFLASH_STATUS_REG_WP_OFFSET)
#define HISI_M25P_STATUS_BP_NONE (0x00 << HISI_SFLASH_STATUS_REG_WP_OFFSET)
#define HISI_M25P_STATUS_BP_1_OF_64 (0x01 << HISI_SFLASH_STATUS_REG_WP_OFFSET)
#define HISI_M25P_STATUS_BP_1_OF_32 (0x02 << HISI_SFLASH_STATUS_REG_WP_OFFSET)
#define HISI_M25P_STATUS_BP_1_OF_16 (0x03 << HISI_SFLASH_STATUS_REG_WP_OFFSET)
#define HISI_M25P_STATUS_BP_1_OF_8 (0x04 << HISI_SFLASH_STATUS_REG_WP_OFFSET)
#define HISI_M25P_STATUS_BP_1_OF_4 (0x05 << HISI_SFLASH_STATUS_REG_WP_OFFSET)
#define HISI_M25P_STATUS_BP_1_OF_2 (0x06 << HISI_SFLASH_STATUS_REG_WP_OFFSET)
#define HISI_M25P_STATUS_BP_ALL (0x07 << HISI_SFLASH_STATUS_REG_WP_OFFSET)
/************************************/
/* MXIC MX25L6405 Device Specific */
/************************************/
/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */
#define MV_MXIC_MANF_ID 0xC2
#define MV_MX25L6405_DEVICE_ID 0x2017
#define MV_MX25L6405_MAX_SPI_FREQ 20000000 /* 20MHz */
#define MV_MX25L6405_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */
#define MV_MX25L6405_FAST_READ_DUMMY_BYTES 1
#define MV_MXIC_DP_EXIT_DELAY 30 /* 30 ms */
#define HISI_MXIC_MANF_ID 0xC2
#define HISI_MX25L6405_DEVICE_ID 0x2017
#define HISI_MX25L6405_MAX_SPI_FREQ 20000000 /* 20MHz */
#define HISI_MX25L6405_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */
#define HISI_MX25L6405_FAST_READ_DUMMY_BYTES 1
#define HISI_MXIC_DP_EXIT_DELAY 30 /* 30 ms */
/* Sector Sizes and population per device model*/
#define MV_MX25L6405_SECTOR_SIZE 0x10000 /* 64K */
#define MV_MX25L6405_SECTOR_NUMBER 128
#define MV_MXIC_PAGE_SIZE 0x100 /* 256 byte */
#define HISI_MX25L6405_SECTOR_SIZE 0x10000 /* 64K */
#define HISI_MX25L6405_SECTOR_NUMBER 128
#define HISI_MXIC_PAGE_SIZE 0x100 /* 256 byte */
#define MV_MX25L_WREN_CMND_OPCD 0x06 /* Write Enable */
#define MV_MX25L_WRDI_CMND_OPCD 0x04 /* Write Disable */
#define MV_MX25L_RDID_CMND_OPCD 0x9F /* Read ID */
#define HISI_MX25L_WREN_CMND_OPCD 0x06 /* Write Enable */
#define HISI_MX25L_WRDI_CMND_OPCD 0x04 /* Write Disable */
#define HISI_MX25L_RDID_CMND_OPCD 0x9F /* Read ID */
/* Read Status Register */
#define MV_MX25L_RDSR_CMND_OPCD 0x05
#define HISI_MX25L_RDSR_CMND_OPCD 0x05
/* Write Status Register */
#define MV_MX25L_WRSR_CMND_OPCD 0x01
#define MV_MX25L_READ_CMND_OPCD 0x03 /* Sequential Read */
#define MV_MX25L_FAST_RD_CMND_OPCD 0x0B /* Fast Read */
#define MV_MX25L_PP_CMND_OPCD 0x02 /* Page Program */
#define MV_MX25L_SSE_CMND_OPCD 0x20 /* SubSector Erase */
#define MV_MX25L_SE_CMND_OPCD 0xD8 /* Sector Erase */
#define MV_MX25L_BE_CMND_OPCD 0xC7 /* Bulk Erase */
#define MV_MX25L_DP_CMND_OPCD 0xB9 /* Deep Power Down */
#define HISI_MX25L_WRSR_CMND_OPCD 0x01
#define HISI_MX25L_READ_CMND_OPCD 0x03 /* Sequential Read */
#define HISI_MX25L_FAST_RD_CMND_OPCD 0x0B /* Fast Read */
#define HISI_MX25L_PP_CMND_OPCD 0x02 /* Page Program */
#define HISI_MX25L_SSE_CMND_OPCD 0x20 /* SubSector Erase */
#define HISI_MX25L_SE_CMND_OPCD 0xD8 /* Sector Erase */
#define HISI_MX25L_BE_CMND_OPCD 0xC7 /* Bulk Erase */
#define HISI_MX25L_DP_CMND_OPCD 0xB9 /* Deep Power Down */
/* Read Electronic Signature */
#define MV_MX25L_RES_CMND_OPCD 0xAB
#define HISI_MX25L_RES_CMND_OPCD 0xAB
/* Status Register Write Protect Bit Masks - 4bits */
#define MV_MX25L_STATUS_REG_WP_MASK (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define MV_MX25L_STATUS_BP_NONE (0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define MV_MX25L_STATUS_BP_1_OF_128 (0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define MV_MX25L_STATUS_BP_1_OF_64 (0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define MV_MX25L_STATUS_BP_1_OF_32 (0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define MV_MX25L_STATUS_BP_1_OF_16 (0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define MV_MX25L_STATUS_BP_1_OF_8 (0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define MV_MX25L_STATUS_BP_1_OF_4 (0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define MV_MX25L_STATUS_BP_1_OF_2 (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define MV_MX25L_STATUS_BP_ALL (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define HISI_MX25L_STATUS_REG_WP_MASK (0x0F << HISI_SFLASH_STATUS_REG_WP_OFFSET)
#define HISI_MX25L_STATUS_BP_NONE (0x00 << HISI_SFLASH_STATUS_REG_WP_OFFSET)
#define HISI_MX25L_STATUS_BP_1_OF_128 (0x01 << HISI_SFLASH_STATUS_REG_WP_OFFSET)
#define HISI_MX25L_STATUS_BP_1_OF_64 (0x02 << HISI_SFLASH_STATUS_REG_WP_OFFSET)
#define HISI_MX25L_STATUS_BP_1_OF_32 (0x03 << HISI_SFLASH_STATUS_REG_WP_OFFSET)
#define HISI_MX25L_STATUS_BP_1_OF_16 (0x04 << HISI_SFLASH_STATUS_REG_WP_OFFSET)
#define HISI_MX25L_STATUS_BP_1_OF_8 (0x05 << HISI_SFLASH_STATUS_REG_WP_OFFSET)
#define HISI_MX25L_STATUS_BP_1_OF_4 (0x06 << HISI_SFLASH_STATUS_REG_WP_OFFSET)
#define HISI_MX25L_STATUS_BP_1_OF_2 (0x07 << HISI_SFLASH_STATUS_REG_WP_OFFSET)
#define HISI_MX25L_STATUS_BP_ALL (0x0F << HISI_SFLASH_STATUS_REG_WP_OFFSET)
/************************************/
/* MXIC MX25LU12835F Device Specific */
/************************************/
/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */
#define MV_MX25U12835F_MANF_ID 0xC2
#define MV_MX25U12835F_DEVICE_ID 0x2538
#define MV_MX25U12835F_MAX_SPI_FREQ 20000000 /* 20MHz */
#define MV_MX25U12835F_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */
#define MV_MX25U12835F_FAST_READ_DUMMY_BYTES 1
#define MV_MX25U12835F_DP_EXIT_DELAY 30 /* 30 ms */
#define HISI_MX25U12835F_MANF_ID 0xC2
#define HISI_MX25U12835F_DEVICE_ID 0x2538
#define HISI_MX25U12835F_MAX_SPI_FREQ 20000000 /* 20MHz */
#define HISI_MX25U12835F_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */
#define HISI_MX25U12835F_FAST_READ_DUMMY_BYTES 1
#define HISI_MX25U12835F_DP_EXIT_DELAY 30 /* 30 ms */
/* Sector Sizes and population per device model*/
#define MV_MX25U12835F_SECTOR_SIZE 0x10000 /* 64K */
#define MV_MX25U12835F_SECTOR_NUMBER 256
#define MV_MX25U12835F_PAGE_SIZE 0x1000 /* 4KB */
#define HISI_MX25U12835F_SECTOR_SIZE 0x10000 /* 64K */
#define HISI_MX25U12835F_SECTOR_NUMBER 256
#define HISI_MX25U12835F_PAGE_SIZE 0x1000 /* 4KB */
#define MV_MX25U12835F_WREN_CMND_OPCD 0x06 /* Write Enable */
#define MV_MX25U12835F_WRDI_CMND_OPCD 0x04 /* Write Disable */
#define MV_MX25U12835F_RDID_CMND_OPCD 0x9F /* Read ID */
#define HISI_MX25U12835F_WREN_CMND_OPCD 0x06 /* Write Enable */
#define HISI_MX25U12835F_WRDI_CMND_OPCD 0x04 /* Write Disable */
#define HISI_MX25U12835F_RDID_CMND_OPCD 0x9F /* Read ID */
/* Read Status Register */
#define MV_MX25U12835F_RDSR_CMND_OPCD 0x05
#define HISI_MX25U12835F_RDSR_CMND_OPCD 0x05
/* Write Status Register */
#define MV_MX25U12835F_WRSR_CMND_OPCD 0x01
#define MV_MX25U12835F_READ_CMND_OPCD 0x03 /* Sequential Read */
#define MV_MX25U12835F_FAST_RD_CMND_OPCD 0x0B /* Fast Read */
#define MV_MX25U12835F_PP_CMND_OPCD 0x02 /* Page Program */
#define MV_MX25U12835F_SSE_CMND_OPCD 0x20 /* SubSector Erase */
#define MV_MX25U12835F_SE_CMND_OPCD 0xD8 /* Sector Erase */
#define MV_MX25U12835F_BE_CMND_OPCD 0xC7 /* Bulk Erase */
#define MV_MX25U12835F_DP_CMND_OPCD 0xB9 /* Deep Power Down */
#define HISI_MX25U12835F_WRSR_CMND_OPCD 0x01
#define HISI_MX25U12835F_READ_CMND_OPCD 0x03 /* Sequential Read */
#define HISI_MX25U12835F_FAST_RD_CMND_OPCD 0x0B /* Fast Read */
#define HISI_MX25U12835F_PP_CMND_OPCD 0x02 /* Page Program */
#define HISI_MX25U12835F_SSE_CMND_OPCD 0x20 /* SubSector Erase */
#define HISI_MX25U12835F_SE_CMND_OPCD 0xD8 /* Sector Erase */
#define HISI_MX25U12835F_BE_CMND_OPCD 0xC7 /* Bulk Erase */
#define HISI_MX25U12835F_DP_CMND_OPCD 0xB9 /* Deep Power Down */
/* Read Electronic Signature */
#define MV_MX25U12835F_RES_CMND_OPCD 0xAB
#define HISI_MX25U12835F_RES_CMND_OPCD 0xAB
/* Status Register Write Protect Bit Masks - 4bits */
#define MV_MX25U12835F_STATUS_REG_WP_MASK (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define MV_MX25U12835F_STATUS_BP_NONE (0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define MV_MX25U12835F_STATUS_BP_1_OF_128 (0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define MV_MX25U12835F_STATUS_BP_1_OF_64 (0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define MV_MX25U12835F_STATUS_BP_1_OF_32 (0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define MV_MX25U12835F_STATUS_BP_1_OF_16 (0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define MV_MX25U12835F_STATUS_BP_1_OF_8 (0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define MV_MX25U12835F_STATUS_BP_1_OF_4 (0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define MV_MX25U12835F_STATUS_BP_1_OF_2 (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define MV_MX25U12835F_STATUS_BP_ALL (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define HISI_MX25U12835F_STATUS_REG_WP_MASK (0x0F << HISI_SFLASH_STATUS_REG_WP_OFFSET)
#define HISI_MX25U12835F_STATUS_BP_NONE (0x00 << HISI_SFLASH_STATUS_REG_WP_OFFSET)
#define HISI_MX25U12835F_STATUS_BP_1_OF_128 (0x01 << HISI_SFLASH_STATUS_REG_WP_OFFSET)
#define HISI_MX25U12835F_STATUS_BP_1_OF_64 (0x02 << HISI_SFLASH_STATUS_REG_WP_OFFSET)
#define HISI_MX25U12835F_STATUS_BP_1_OF_32 (0x03 << HISI_SFLASH_STATUS_REG_WP_OFFSET)
#define HISI_MX25U12835F_STATUS_BP_1_OF_16 (0x04 << HISI_SFLASH_STATUS_REG_WP_OFFSET)
#define HISI_MX25U12835F_STATUS_BP_1_OF_8 (0x05 << HISI_SFLASH_STATUS_REG_WP_OFFSET)
#define HISI_MX25U12835F_STATUS_BP_1_OF_4 (0x06 << HISI_SFLASH_STATUS_REG_WP_OFFSET)
#define HISI_MX25U12835F_STATUS_BP_1_OF_2 (0x07 << HISI_SFLASH_STATUS_REG_WP_OFFSET)
#define HISI_MX25U12835F_STATUS_BP_ALL (0x0F << HISI_SFLASH_STATUS_REG_WP_OFFSET)
/************************************/
/* MXIC MX25L1606E Device Specific */
/************************************/
/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */
#define MV_MX25L1606E_DEVICE_ID 0x2015
#define MV_MX25L1606E_MAX_SPI_FREQ 33000000 /* 33MHz */
#define MV_MX25L1606E_MAX_FAST_SPI_FREQ 86000000 /* 86MHz */
#define MV_MX25L1606E_FAST_READ_DUMMY_BYTES 1
#define HISI_MX25L1606E_DEVICE_ID 0x2015
#define HISI_MX25L1606E_MAX_SPI_FREQ 33000000 /* 33MHz */
#define HISI_MX25L1606E_MAX_FAST_SPI_FREQ 86000000 /* 86MHz */
#define HISI_MX25L1606E_FAST_READ_DUMMY_BYTES 1
#define MV_MX25L1606E_PAGE_SIZE 0x1000 /* 4K */
#define MV_MX25L1606E_SECTOR_SIZE 0x10000 /* 64K */
#define MV_MX25L1606E_SECTOR_NUMBER 32
#define HISI_MX25L1606E_PAGE_SIZE 0x1000 /* 4K */
#define HISI_MX25L1606E_SECTOR_SIZE 0x10000 /* 64K */
#define HISI_MX25L1606E_SECTOR_NUMBER 32
/************************************/
/* SPANSION S25Fx128 Device Specific */
/************************************/
/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */
#define MV_SPANSION_MANF_ID 0x01
#define MV_S25FL128_DEVICE_ID 0x2018
#define MV_S25FL128_MAX_SPI_FREQ 33000000 /* 33MHz */
#define MV_S25FL128_MAX_FAST_SPI_FREQ 104000000 /* 104MHz */
#define MV_S25FL128_FAST_READ_DUMMY_BYTES 1
#define HISI_SPANSION_MANF_ID 0x01
#define HISI_S25FL128_DEVICE_ID 0x2018
#define HISI_S25FL128_MAX_SPI_FREQ 33000000 /* 33MHz */
#define HISI_S25FL128_MAX_FAST_SPI_FREQ 104000000 /* 104MHz */
#define HISI_S25FL128_FAST_READ_DUMMY_BYTES 1
/* Sector Sizes and population per device model*/
#define MV_S25FL128_SECTOR_SIZE 0x10000 /* 64K */
#define MV_S25FL128_SECTOR_NUMBER 256
#define MV_S25FL_PAGE_SIZE 0x100 /* 256 byte */
#define HISI_S25FL128_SECTOR_SIZE 0x10000 /* 64K */
#define HISI_S25FL128_SECTOR_NUMBER 256
#define HISI_S25FL_PAGE_SIZE 0x100 /* 256 byte */
#define MV_S25FL_WREN_CMND_OPCD 0x06 /* Write Enable */
#define MV_S25FL_WRDI_CMND_OPCD 0x04 /* Write Disable */
#define MV_S25FL_RDID_CMND_OPCD 0x9F /* Read ID */
#define HISI_S25FL_WREN_CMND_OPCD 0x06 /* Write Enable */
#define HISI_S25FL_WRDI_CMND_OPCD 0x04 /* Write Disable */
#define HISI_S25FL_RDID_CMND_OPCD 0x9F /* Read ID */
/* Read Status Register */
#define MV_S25FL_RDSR_CMND_OPCD 0x05
#define HISI_S25FL_RDSR_CMND_OPCD 0x05
/* Write Status Register */
#define MV_S25FL_WRSR_CMND_OPCD 0x01
#define MV_S25FL_READ_CMND_OPCD 0x03 /* Sequential Read */
#define MV_S25FL_FAST_RD_CMND_OPCD 0x0B /* Fast Read */
#define MV_S25FL_PP_CMND_OPCD 0x02 /* Page Program */
#define MV_S25FL_SSE_CMND_OPCD 0x20 /* SubSector Erase */
#define MV_S25FL_SE_CMND_OPCD 0xD8 /* Sector Erase */
#define MV_S25FL_BE_CMND_OPCD 0xC7 /* Bulk Erase */
#define MV_S25FL_DP_CMND_OPCD 0xB9 /* Deep Power Down */
#define HISI_S25FL_WRSR_CMND_OPCD 0x01
#define HISI_S25FL_READ_CMND_OPCD 0x03 /* Sequential Read */
#define HISI_S25FL_FAST_RD_CMND_OPCD 0x0B /* Fast Read */
#define HISI_S25FL_PP_CMND_OPCD 0x02 /* Page Program */
#define HISI_S25FL_SSE_CMND_OPCD 0x20 /* SubSector Erase */
#define HISI_S25FL_SE_CMND_OPCD 0xD8 /* Sector Erase */
#define HISI_S25FL_BE_CMND_OPCD 0xC7 /* Bulk Erase */
#define HISI_S25FL_DP_CMND_OPCD 0xB9 /* Deep Power Down */
/* Read Electronic Signature */
#define MV_S25FL_RES_CMND_OPCD 0xAB
#define HISI_S25FL_RES_CMND_OPCD 0xAB
/* Status Register Write Protect Bit Masks - 4bits */
#define MV_S25FL_STATUS_REG_WP_MASK \
(0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define MV_S25FL_STATUS_BP_NONE \
(0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define MV_S25FL_STATUS_BP_1_OF_128 \
(0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define MV_S25FL_STATUS_BP_1_OF_64 \
(0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define MV_S25FL_STATUS_BP_1_OF_32 \
(0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define MV_S25FL_STATUS_BP_1_OF_16 \
(0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define MV_S25FL_STATUS_BP_1_OF_8 \
(0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define MV_S25FL_STATUS_BP_1_OF_4 \
(0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define MV_S25FL_STATUS_BP_1_OF_2 \
(0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define MV_S25FL_STATUS_BP_ALL \
(0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define HISI_S25FL_STATUS_REG_WP_MASK \
(0x0F << HISI_SFLASH_STATUS_REG_WP_OFFSET)
#define HISI_S25FL_STATUS_BP_NONE \
(0x00 << HISI_SFLASH_STATUS_REG_WP_OFFSET)
#define HISI_S25FL_STATUS_BP_1_OF_128 \
(0x01 << HISI_SFLASH_STATUS_REG_WP_OFFSET)
#define HISI_S25FL_STATUS_BP_1_OF_64 \
(0x02 << HISI_SFLASH_STATUS_REG_WP_OFFSET)
#define HISI_S25FL_STATUS_BP_1_OF_32 \
(0x03 << HISI_SFLASH_STATUS_REG_WP_OFFSET)
#define HISI_S25FL_STATUS_BP_1_OF_16 \
(0x04 << HISI_SFLASH_STATUS_REG_WP_OFFSET)
#define HISI_S25FL_STATUS_BP_1_OF_8 \
(0x05 << HISI_SFLASH_STATUS_REG_WP_OFFSET)
#define HISI_S25FL_STATUS_BP_1_OF_4 \
(0x06 << HISI_SFLASH_STATUS_REG_WP_OFFSET)
#define HISI_S25FL_STATUS_BP_1_OF_2 \
(0x07 << HISI_SFLASH_STATUS_REG_WP_OFFSET)
#define HISI_S25FL_STATUS_BP_ALL \
(0x0F << HISI_SFLASH_STATUS_REG_WP_OFFSET)
/********************************/
/* ATMEL ATxx Device Specific */
/********************************/
/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */
#define MV_AT25DFXXX_AT_MANF_ID 0x1F
#define MV_AT25DF641_DEVICE_ID 0x4800
#define MV_AT25DF641_MAX_SPI_FREQ 20000000 /* 20MHz */
#define MV_AT25DF641_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */
#define MV_AT25DF641_FAST_READ_DUMMY_BYTES 1
#define HISI_AT25DFXXX_AT_MANF_ID 0x1F
#define HISI_AT25DF641_DEVICE_ID 0x4800
#define HISI_AT25DF641_MAX_SPI_FREQ 20000000 /* 20MHz */
#define HISI_AT25DF641_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */
#define HISI_AT25DF641_FAST_READ_DUMMY_BYTES 1
/* Sector Sizes and population per device model*/
#define MV_AT25DF641_SECTOR_SIZE 0x10000 /* 64K */
#define MV_AT25DF641_SECTOR_NUMBER 128
#define MV_AT25DF_PAGE_SIZE 0x100 /* 256 byte */
#define MV_AT25DF_WREN_CMND_OPCD 0x06 /* Write Enable */
#define MV_AT25DF_WRDI_CMND_OPCD 0x04 /* Write Disable */
#define MV_AT25DF_RDID_CMND_OPCD 0x9F /* Read ID */
#define MV_AT25DF_RDSR_CMND_OPCD 0x05 /* Read Status Register */
#define MV_AT25DF_WRSR_CMND_OPCD 0x01 /* Write Status Register */
#define MV_AT25DF_READ_CMND_OPCD 0x03 /* Sequential Read */
#define MV_AT25DF_FAST_RD_CMND_OPCD 0x0B /* Fast Read */
#define MV_AT25DF_PP_CMND_OPCD 0x02 /* Page Program */
#define MV_AT25DF_SSE_CMND_OPCD 0x20 /* SubSector Erase */
#define MV_AT25DF_SE_CMND_OPCD 0xD8 /* Sector Erase */
#define MV_AT25DF_BE_CMND_OPCD 0xC7 /* Bulk Erase */
#define MV_AT25DF_RES_CMND_OPCD 0xAB /* Read Electronic Signature */
#define HISI_AT25DF641_SECTOR_SIZE 0x10000 /* 64K */
#define HISI_AT25DF641_SECTOR_NUMBER 128
#define HISI_AT25DF_PAGE_SIZE 0x100 /* 256 byte */
#define HISI_AT25DF_WREN_CMND_OPCD 0x06 /* Write Enable */
#define HISI_AT25DF_WRDI_CMND_OPCD 0x04 /* Write Disable */
#define HISI_AT25DF_RDID_CMND_OPCD 0x9F /* Read ID */
#define HISI_AT25DF_RDSR_CMND_OPCD 0x05 /* Read Status Register */
#define HISI_AT25DF_WRSR_CMND_OPCD 0x01 /* Write Status Register */
#define HISI_AT25DF_READ_CMND_OPCD 0x03 /* Sequential Read */
#define HISI_AT25DF_FAST_RD_CMND_OPCD 0x0B /* Fast Read */
#define HISI_AT25DF_PP_CMND_OPCD 0x02 /* Page Program */
#define HISI_AT25DF_SSE_CMND_OPCD 0x20 /* SubSector Erase */
#define HISI_AT25DF_SE_CMND_OPCD 0xD8 /* Sector Erase */
#define HISI_AT25DF_BE_CMND_OPCD 0xC7 /* Bulk Erase */
#define HISI_AT25DF_RES_CMND_OPCD 0xAB /* Read Electronic Signature */
/* Status Register Write Protect Bit Masks - 4bits */
#define MV_AT25DF_STATUS_REG_WP_MASK \
(0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define MV_AT25DF_STATUS_BP_NONE \
(0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define HISI_AT25DF_STATUS_REG_WP_MASK \
(0x0F << HISI_SFLASH_STATUS_REG_WP_OFFSET)
#define HISI_AT25DF_STATUS_BP_NONE \
(0x00 << HISI_SFLASH_STATUS_REG_WP_OFFSET)
#define MV_AT25DF_STATUS_BP_WP_NONE (0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define MV_AT25DF_STATUS_BP_SOME (0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define MV_AT25DF_STATUS_BP_ALL (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define HISI_AT25DF_STATUS_BP_WP_NONE (0x04 << HISI_SFLASH_STATUS_REG_WP_OFFSET)
#define HISI_AT25DF_STATUS_BP_SOME (0x05 << HISI_SFLASH_STATUS_REG_WP_OFFSET)
#define HISI_AT25DF_STATUS_BP_ALL (0x07 << HISI_SFLASH_STATUS_REG_WP_OFFSET)
/********************************/
/* NUMONYX N25Q Device Specific */
/********************************/
#define MV_N25Q_WREN_CMND_OPCD 0x06 /* Write Enable */
#define MV_N25Q_WRDI_CMND_OPCD 0x04 /* Write Disable */
#define MV_N25Q_RDID_CMND_OPCD 0x9F /* Read ID */
#define HISI_N25Q_WREN_CMND_OPCD 0x06 /* Write Enable */
#define HISI_N25Q_WRDI_CMND_OPCD 0x04 /* Write Disable */
#define HISI_N25Q_RDID_CMND_OPCD 0x9F /* Read ID */
/* Read Status Register */
#define MV_N25Q_RDSR_CMND_OPCD 0x05
#define HISI_N25Q_RDSR_CMND_OPCD 0x05
/* Write Status Register */
#define MV_N25Q_WRSR_CMND_OPCD 0x01
#define MV_N25Q_READ_CMND_OPCD 0x03 /* Sequential Read */
#define MV_N25Q_FAST_RD_CMND_OPCD 0x0B /* Fast Read */
#define MV_N25Q_PP_CMND_OPCD 0x02 /* Page Program */
#define MV_N25Q_SSE_CMND_OPCD 0x20 /* SubSectorErase */
#define MV_N25Q_SE_CMND_OPCD 0xD8 /* Sector Erase */
#define MV_N25Q_BE_CMND_OPCD 0xC7 /* Bulk Erase */
#define HISI_N25Q_WRSR_CMND_OPCD 0x01
#define HISI_N25Q_READ_CMND_OPCD 0x03 /* Sequential Read */
#define HISI_N25Q_FAST_RD_CMND_OPCD 0x0B /* Fast Read */
#define HISI_N25Q_PP_CMND_OPCD 0x02 /* Page Program */
#define HISI_N25Q_SSE_CMND_OPCD 0x20 /* SubSectorErase */
#define HISI_N25Q_SE_CMND_OPCD 0xD8 /* Sector Erase */
#define HISI_N25Q_BE_CMND_OPCD 0xC7 /* Bulk Erase */
/* Read Volatile Enhanced Configuration Register */
#define MV_N25Q_RDVECR_CMND_OPCD 0x65
#define HISI_N25Q_RDVECR_CMND_OPCD 0x65
/* Write Volatile Enhanced Configuration Register */
#define MV_N25Q_WRVECR_CMND_OPCD 0x61
#define HISI_N25Q_WRVECR_CMND_OPCD 0x61
/* Enter 4-byte address mode */
#define MV_N25Q_EN4BADDR_CMND_OPCD 0xB7
#define HISI_N25Q_EN4BADDR_CMND_OPCD 0xB7
/* Exit 4-byte address mode */
#define MV_N25Q_EX4BADDR_CMND_OPCD 0xE9
#define HISI_N25Q_EX4BADDR_CMND_OPCD 0xE9
/* STATUS REGISTER BUSY BIT */
#define MV_N25Q_BUSY_FLAG_BIT 0xC7
#define HISI_N25Q_BUSY_FLAG_BIT 0xC7
#define MV_N25Q256_MANF_ID 0x20
#define MV_N25Q256_DEVICE_ID 0xBA19
#define MV_N25Q256_MAX_SPI_FREQ 108000000 /* 108MHz */
#define MV_N25Q256_MAX_FAST_SPI_FREQ 432000000 /* 432MHz */
#define MV_N25Q256_FAST_READ_DUMMY_BYTES 8
#define HISI_N25Q256_MANF_ID 0x20
#define HISI_N25Q256_DEVICE_ID 0xBA19
#define HISI_N25Q256_MAX_SPI_FREQ 108000000 /* 108MHz */
#define HISI_N25Q256_MAX_FAST_SPI_FREQ 432000000 /* 432MHz */
#define HISI_N25Q256_FAST_READ_DUMMY_BYTES 8
#define MV_N25Q256_SECTOR_SIZE 0x10000 /* 64K */
#define MV_N25Q256_SECTOR_NUMBER 512
#define MV_N25Q256_PAGE_SIZE 0x1000 /* 4K */
#define HISI_N25Q256_SECTOR_SIZE 0x10000 /* 64K */
#define HISI_N25Q256_SECTOR_NUMBER 512
#define HISI_N25Q256_PAGE_SIZE 0x1000 /* 4K */
/* support 3byte and 4byte addr */
#define MV_N25Q256_3B_4B_SUPPORT 0x3
#define HISI_N25Q256_3B_4B_SUPPORT 0x3
/* support ESPI, FULL DIO, FULL QIO mode */
#define MV_N25Q256_IF_TYPE_SUPPORT 0x89
#define HISI_N25Q256_IF_TYPE_SUPPORT 0x89
#define MV_N25Q128_MANF_ID 0x20
#define MV_N25Q128_DEVICE_ID 0xBA18
#define MV_N25Q128_MAX_SPI_FREQ 108000000 /* 108MHz */
#define MV_N25Q128_MAX_FAST_SPI_FREQ 432000000 /* 432MHz */
#define MV_N25Q128_FAST_READ_DUMMY_BYTES 8
#define HISI_N25Q128_MANF_ID 0x20
#define HISI_N25Q128_DEVICE_ID 0xBA18
#define HISI_N25Q128_MAX_SPI_FREQ 108000000 /* 108MHz */
#define HISI_N25Q128_MAX_FAST_SPI_FREQ 432000000 /* 432MHz */
#define HISI_N25Q128_FAST_READ_DUMMY_BYTES 8
#define MV_N25Q128_SECTOR_SIZE 0x10000 /* 64K */
#define MV_N25Q128_SECTOR_NUMBER 256
#define MV_N25Q128_PAGE_SIZE 0x1000 /* 4K */
#define HISI_N25Q128_SECTOR_SIZE 0x10000 /* 64K */
#define HISI_N25Q128_SECTOR_NUMBER 256
#define HISI_N25Q128_PAGE_SIZE 0x1000 /* 4K */
/* NUMONYX N25Q128B SPI flash */
#define MV_N25Q128B_MANF_ID 0x20
#define MV_N25Q128B_DEVICE_ID 0xBB18
#define HISI_N25Q128B_MANF_ID 0x20
#define HISI_N25Q128B_DEVICE_ID 0xBB18
/* support 3byte and 4byte addr */
#define MV_N25Q128_3B_4B_SUPPORT 0x3
#define HISI_N25Q128_3B_4B_SUPPORT 0x3
/* support ESPI, FULL DIO, FULL QIO mode */
#define MV_N25Q128_IF_TYPE_SUPPORT 0x89
#define HISI_N25Q128_IF_TYPE_SUPPORT 0x89
#endif
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