crypto/hisilicon/qm: backport qm/zip from mainline

driver inclusion
category: bugfix
bugzilla: NA
CVE: NA

Some changes accepted by mainline but not merged into CI should backport,
No major changes.

Feature or Bugfix:Bugfix
Signed-off-by: NZhou Wang <wangzhou1@hisilicon.com>
Signed-off-by: Ntanshukun (A) <tanshukun1@huawei.com>
Reviewed-by: NLing Mingqiang <lingmingqiang@huawei.com>
Reviewed-by: NYang Yingliang <yangyingliang@huawei.com>
Signed-off-by: NYang Yingliang <yangyingliang@huawei.com>

drivers/crypto/hisilicon/hpre/hpre_main.c

@@ -232,7 +232,7 @@ static int pf_q_num_set(const char *val, const struct kernel_param *kp)
 			q_num);
 	} else {
 		rev_id = pdev->revision;
-		if (rev_id == QM_HW_VER2_ID)
+		if (rev_id == QM_HW_V2)
 			q_num = HPRE_QUEUE_NUM_V2;
 		else
 			return -EINVAL;
@@ -432,7 +432,7 @@ static void hpre_cnt_regs_clear(struct hisi_qm *qm)
 	/* clear rdclr_en */
 	writel(0x0, qm->io_base + HPRE_CTRL_CNT_CLR_CE);
 
-	hisi_qm_cnt_regs_clear(qm);
+	hisi_qm_debug_regs_clear(qm);
 }
 
 static void hpre_hw_error_set_state(struct hpre *hpre, bool state)

drivers/crypto/hisilicon/qm.c

@@ -146,7 +146,7 @@
 
 #define POLL_PERIOD			10
 #define POLL_TIMEOUT			1000
-#define TEMPBUFFER_LEN			20
+#define TEMPBUFFER_LEN			22
 
 #define QM_DB_TIMEOUT_TYPE_SHIFT	6
 #define QM_FIFO_OVERFLOW_TYPE_SHIFT	6
@@ -1193,7 +1193,7 @@ static struct hisi_qp *hisi_qm_create_qp_nolock(struct hisi_qm *qm,
 			goto err_clear_bit;
 		}
 
-		dev_dbg(dev, "allocate qp dma buf(va=%pK, dma=%pad, size=%lx)\n",
+		dev_dbg(dev, "allocate qp dma buf(va=%pK, dma=%pad, size=%zx)\n",
 			qp->qdma.va, &qp->qdma.dma, qp->qdma.size);
 	}
 
@@ -1890,6 +1890,19 @@ static int qm_register_uacce(struct hisi_qm *qm)
 
 	return uacce_register(uacce);
 }
+
+static int qm_unregister_uacce(struct hisi_qm *qm)
+{
+	int ret;
+
+	ret = uacce_unregister(&qm->uacce);
+	if (ret)
+		return ret;
+
+	memset(&qm->uacce, 0, sizeof(qm->uacce));
+
+	return 0;
+}
 #endif
 
 /**
@@ -1930,7 +1943,7 @@ int hisi_qm_init(struct hisi_qm *qm)
 	ret = pci_enable_device_mem(pdev);
 	if (ret < 0) {
 		dev_err(&pdev->dev, "Failed to enable device mem!\n");
-		return ret;
+		goto err_unregister_uacce;
 	}
 
 	ret = pci_request_mem_regions(pdev, qm->dev_name);
@@ -1987,6 +2000,11 @@ int hisi_qm_init(struct hisi_qm *qm)
 	pci_release_mem_regions(pdev);
 err_disable_pcidev:
 	pci_disable_device(pdev);
+err_unregister_uacce:
+#ifdef CONFIG_CRYPTO_QM_UACCE
+	if (qm->use_uacce)
+		qm_unregister_uacce(qm);
+#endif
 
 	return ret;
 }
@@ -2428,7 +2446,7 @@ int hisi_qm_start(struct hisi_qm *qm)
 		qm->qdma.va = dma_alloc_coherent(dev, qm->qdma.size,
 						 &qm->qdma.dma,
 						 GFP_ATOMIC | __GFP_ZERO);
-		dev_dbg(dev, "allocate qm dma buf(va=%pK, dma=%pad, size=%lx)\n",
+		dev_dbg(dev, "allocate qm dma buf(va=%pK, dma=%pad, size=%zx)\n",
 			qm->qdma.va, &qm->qdma.dma, qm->qdma.size);
 		if (!qm->qdma.va) {
 			ret = -ENOMEM;
@@ -2524,10 +2542,10 @@ int hisi_qm_stop(struct hisi_qm *qm, enum qm_stop_reason r)
 EXPORT_SYMBOL_GPL(hisi_qm_stop);
 
 /**
- * hisi_qm_cnt_regs_clear() - clear qm cnt regs.
- * @qm: The qm for which we want to clear
+ * hisi_qm_debug_regs_clear() - clear qm debug related registers.
+ * @qm: The qm for which we want to clear.
  */
-void hisi_qm_cnt_regs_clear(struct hisi_qm *qm)
+void hisi_qm_debug_regs_clear(struct hisi_qm *qm)
 {
 	struct qm_dfx_registers *regs;
 	int i;
@@ -2549,7 +2567,7 @@ void hisi_qm_cnt_regs_clear(struct hisi_qm *qm)
 	/* clear clear_enable */
 	writel(0x0, qm->io_base + QM_DFX_CNT_CLR_CE);
 }
-EXPORT_SYMBOL_GPL(hisi_qm_cnt_regs_clear);
+EXPORT_SYMBOL_GPL(hisi_qm_debug_regs_clear);
 
 /**
  * hisi_qm_debug_init() - Initialize qm related debugfs files.
@@ -2674,10 +2692,9 @@ EXPORT_SYMBOL_GPL(hisi_qm_clear_queues);
 enum qm_hw_ver hisi_qm_get_hw_version(struct pci_dev *pdev)
 {
 	switch (pdev->revision) {
-	case QM_HW_VER1_ID:
-		return QM_HW_V1;
-	case QM_HW_VER2_ID:
-		return QM_HW_V2;
+	case QM_HW_V1:
+	case QM_HW_V2:
+		return pdev->revision;
 	default:
 		return QM_HW_UNKNOWN;
 	}

drivers/crypto/hisilicon/qm.h

@@ -79,8 +79,6 @@
 			 QM_ACC_GET_TASK_TIMEOUT | QM_DB_TIMEOUT | \
 			 QM_OF_FIFO_OF)
 #define QM_BASE_CE			QM_ECC_1BIT
-#define QM_HW_VER1_ID			0x20
-#define QM_HW_VER2_ID			0x21
 
 #define QM_DFX_QN_SHIFT			16
 #define QM_VF_CNT_MASK			0xffffffc0
@@ -108,8 +106,8 @@ enum qp_state {
 
 enum qm_hw_ver {
 	QM_HW_UNKNOWN = -1,
-	QM_HW_V1 = 1,
-	QM_HW_V2,
+	QM_HW_V1 = 0x20,
+	QM_HW_V2 = 0x21,
 };
 
 enum qm_fun_type {
@@ -343,7 +341,7 @@ int hisi_qp_wait(struct hisi_qp *qp);
 int hisi_qm_get_free_qp_num(struct hisi_qm *qm);
 int hisi_qm_get_vft(struct hisi_qm *qm, u32 *base, u32 *number);
 int hisi_qm_set_vft(struct hisi_qm *qm, u32 fun_num, u32 base, u32 number);
-void hisi_qm_cnt_regs_clear(struct hisi_qm *qm);
+void hisi_qm_debug_regs_clear(struct hisi_qm *qm);
 int hisi_qm_debug_init(struct hisi_qm *qm);
 void hisi_qm_hw_error_init(struct hisi_qm *qm, u32 ce, u32 nfe, u32 fe,
 			   u32 msi);

drivers/crypto/hisilicon/rde/rde_main.c

@@ -222,10 +222,10 @@ static int pf_q_num_set(const char *val, const struct kernel_param *kp)
 	} else {
 		rev_id = pdev->revision;
 		switch (rev_id) {
-		case QM_HW_VER1_ID:
+		case QM_HW_V1:
 			q_num = HRDE_QUEUE_NUM_V1;
 			break;
-		case QM_HW_VER2_ID:
+		case QM_HW_V2:
 			q_num = HRDE_QUEUE_NUM_V2;
 			break;
 		default:

drivers/crypto/hisilicon/sec2/sec_main.c

@@ -269,10 +269,10 @@ static int pf_q_num_set(const char *val, const struct kernel_param *kp)
 	} else {
 		rev_id = pdev->revision;
 		switch (rev_id) {
-		case QM_HW_VER1_ID:
+		case QM_HW_V1:
 			q_num = HSEC_QUEUE_NUM_V1;
 			break;
-		case QM_HW_VER2_ID:
+		case QM_HW_V2:
 			q_num = HSEC_QUEUE_NUM_V2;
 			break;
 		default:

drivers/crypto/hisilicon/zip/zip_crypto.c

@@ -31,7 +31,6 @@
 
 #define HZIP_ZLIB_HEAD_SIZE			2
 #define HZIP_GZIP_HEAD_SIZE			10
-#define HZIP_CTX_Q_NUM				2
 #define HZIP_ALG_PRIORITY			300
 
 #define HZIP_BD_STATUS_M			GENMASK(7, 0)
@@ -52,6 +51,12 @@ static const u8 gzip_head[HZIP_GZIP_HEAD_SIZE] = {0x1f, 0x8b, 0x08, 0x0, 0x0,
 	(((req_type) == HZIP_ALG_TYPE_ZLIB) ? zlib_head :		\
 	 ((req_type) == HZIP_ALG_TYPE_GZIP) ? gzip_head : NULL)		\
 
+enum {
+	HZIP_QPC_COMP,
+	HZIP_QPC_DECOMP,
+	HZIP_CTX_Q_NUM
+};
+
 struct hisi_zip_buffer {
 	u8 *input;
 	dma_addr_t input_dma;
@@ -66,8 +71,6 @@ struct hisi_zip_qp_ctx {
 };
 
 struct hisi_zip_ctx {
-#define QPC_COMP	0
-#define QPC_DECOMP	1
 	struct hisi_zip_qp_ctx qp_ctx[HZIP_CTX_Q_NUM];
 };
 
@@ -284,7 +287,7 @@ static int hisi_zip_compress(struct crypto_tfm *tfm, const u8 *src,
 			     unsigned int slen, u8 *dst, unsigned int *dlen)
 {
 	struct hisi_zip_ctx *hisi_zip_ctx = crypto_tfm_ctx(tfm);
-	struct hisi_zip_qp_ctx *qp_ctx = &hisi_zip_ctx->qp_ctx[QPC_COMP];
+	struct hisi_zip_qp_ctx *qp_ctx = &hisi_zip_ctx->qp_ctx[HZIP_QPC_COMP];
 	struct hisi_qp *qp = qp_ctx->qp;
 	struct hisi_zip_sqe *zip_sqe = &qp_ctx->zip_sqe;
 	int ret;
@@ -382,7 +385,7 @@ static int hisi_zip_decompress(struct crypto_tfm *tfm, const u8 *src,
 			       unsigned int slen, u8 *dst, unsigned int *dlen)
 {
 	struct hisi_zip_ctx *hisi_zip_ctx = crypto_tfm_ctx(tfm);
-	struct hisi_zip_qp_ctx *qp_ctx = &hisi_zip_ctx->qp_ctx[QPC_DECOMP];
+	struct hisi_zip_qp_ctx *qp_ctx = &hisi_zip_ctx->qp_ctx[HZIP_QPC_DECOMP];
 	struct hisi_qp *qp = qp_ctx->qp;
 	struct hisi_zip_sqe *zip_sqe = &qp_ctx->zip_sqe;
 	u16 size;

drivers/crypto/hisilicon/zip/zip_main.c

@@ -89,7 +89,7 @@
 #define HZIP_MSE_ENABLE			1
 #define HZIP_MSE_DISABLE		0
 #define HZIP_NUMA_DISTANCE		100
-#define HZIP_BUF_SIZE			20
+#define HZIP_BUF_SIZE			22
 #define FORMAT_DECIMAL			10
 #define HZIP_REG_RD_INTVRL_US		10
 #define HZIP_REG_RD_TMOUT_US		1000
@@ -278,17 +278,17 @@ static int pf_q_num_set(const char *val, const struct kernel_param *kp)
 	if (!val)
 		return -EINVAL;
 
-	if (unlikely(!pdev)) {
+	if (!pdev) {
 		q_num = min_t(u32, HZIP_QUEUE_NUM_V1, HZIP_QUEUE_NUM_V2);
 		pr_info("No device found currently, suppose queue number is %d\n",
 			q_num);
 	} else {
 		rev_id = pdev->revision;
 		switch (rev_id) {
-		case QM_HW_VER1_ID:
+		case QM_HW_V1:
 			q_num = HZIP_QUEUE_NUM_V1;
 			break;
-		case QM_HW_VER2_ID:
+		case QM_HW_V2:
 			q_num = HZIP_QUEUE_NUM_V2;
 			break;
 		default:
@@ -412,9 +412,11 @@ static void hisi_zip_set_user_domain_and_cache(struct hisi_zip *hisi_zip)
 	       hisi_zip->qm.io_base + QM_CACHE_CTL);
 }
 
-/* hisi_zip_cnt_regs_clear() - clear the zip cnt regs */
-static void hisi_zip_cnt_regs_clear(struct hisi_qm *qm)
+/* hisi_zip_debug_regs_clear() - clear the zip debug regs */
+static void hisi_zip_debug_regs_clear(struct hisi_zip *hisi_zip)
 {
+	struct hisi_qm *qm = &hisi_zip->qm;
+
 	/* clear current_qm */
 	writel(0x0, qm->io_base + QM_DFX_MB_CNT_VF);
 	writel(0x0, qm->io_base + QM_DFX_DB_CNT_VF);
@@ -422,7 +424,7 @@ static void hisi_zip_cnt_regs_clear(struct hisi_qm *qm)
 	/* clear rdclr_en */
 	writel(0x0, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE);
 
-	hisi_qm_cnt_regs_clear(qm);
+	hisi_qm_debug_regs_clear(qm);
 }
 
 
@@ -702,6 +704,11 @@ static void hisi_zip_debugfs_exit(struct hisi_zip *hisi_zip)
 	struct hisi_qm *qm = &hisi_zip->qm;
 
 	debugfs_remove_recursive(qm->debug.debug_root);
+
+	if (qm->fun_type == QM_HW_PF) {
+		hisi_zip_debug_regs_clear(hisi_zip);
+		qm->debug.curr_qm_qp_num = 0;
+	}
 }
 
 static void hisi_zip_hw_error_init(struct hisi_zip *hisi_zip)
@@ -739,6 +746,7 @@ static int hisi_zip_pf_probe_init(struct hisi_zip *hisi_zip)
 
 	hisi_zip_set_user_domain_and_cache(hisi_zip);
 	hisi_zip_hw_error_init(hisi_zip);
+	hisi_zip_debug_regs_clear(hisi_zip);
 
 	return 0;
 }
@@ -804,7 +812,6 @@ static int hisi_zip_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 	}
 
 	if (qm->fun_type == QM_HW_PF) {
-		hisi_zip_cnt_regs_clear(qm);
 		ret = hisi_zip_pf_probe_init(hisi_zip);
 		if (ret)
 			goto err_remove_from_list;
@@ -965,10 +972,6 @@ static void hisi_zip_remove(struct pci_dev *pdev)
 	if (qm->fun_type == QM_HW_PF && hisi_zip->ctrl->num_vfs != 0)
 		hisi_zip_sriov_disable(pdev);
 
-	if (qm->fun_type == QM_HW_PF) {
-		hisi_zip_cnt_regs_clear(qm);
-		qm->debug.curr_qm_qp_num = 0;
-	}
 	hisi_zip_debugfs_exit(hisi_zip);
 	hisi_qm_stop(qm, QM_NORMAL);
 
@@ -1036,10 +1039,8 @@ static pci_ers_result_t hisi_zip_process_hw_error(struct pci_dev *pdev)
 		return PCI_ERS_RESULT_NONE;
 	}
 
-	/* log qm error */
 	qm_ret = hisi_qm_hw_error_handle(&hisi_zip->qm);
 
-	/* log zip error */
 	zip_ret = hisi_zip_hw_error_handle(hisi_zip);
 
 	return (qm_ret == PCI_ERS_RESULT_NEED_RESET ||
@@ -1302,7 +1303,6 @@ static pci_ers_result_t hisi_zip_slot_reset(struct pci_dev *pdev)
 
 	pci_cleanup_aer_uncorrect_error_status(pdev);
 
-	/* reset zip controller */
 	ret = hisi_zip_controller_reset(hisi_zip);
 	if (ret) {
 		dev_err(&pdev->dev, "hisi_zip controller reset failed (%d)\n",