From 0cdad7e88a23910a911a3339ff2d70f8f952d7b8 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Tue, 14 Oct 2008 17:19:38 -0700 Subject: [PATCH] i915: Use non-reserved status page index for breadcrumb Dwords 0 through 0x1f are reserved for use by the hardware. Move the GEM breadcrumb from 0x10 to 0x20 to keep out of this area. Signed-off-by: Keith Packard Signed-off-by: Eric Anholt Signed-off-by: Dave Airlie --- drivers/gpu/drm/i915/i915_drv.h | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 74011235f2cc..da7c0072ad4c 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -597,16 +597,18 @@ extern void opregion_enable_asle(struct drm_device *dev); * MI_STORE_DATA_IMM. * * The following dwords have a reserved meaning: - * 0: ISR copy, updated when an ISR bit not set in the HWSTAM changes. - * 4: ring 0 head pointer - * 5: ring 1 head pointer (915-class) - * 6: ring 2 head pointer (915-class) + * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. + * 0x04: ring 0 head pointer + * 0x05: ring 1 head pointer (915-class) + * 0x06: ring 2 head pointer (915-class) + * 0x10-0x1b: Context status DWords (GM45) + * 0x1f: Last written status offset. (GM45) * - * The area from dword 0x10 to 0x3ff is available for driver usage. + * The area from dword 0x20 to 0x3ff is available for driver usage. */ #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg]) #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, 5) -#define I915_GEM_HWS_INDEX 0x10 +#define I915_GEM_HWS_INDEX 0x20 extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); -- GitLab