From 0a616c6ae40fc5ed5ca95354329df7ee3915f267 Mon Sep 17 00:00:00 2001 From: Guangbin Huang Date: Thu, 20 Feb 2020 16:54:52 +0800 Subject: [PATCH] net: hns3: modify timing of reading register in hclge_reset_wait() driver inclusion category: bugfix bugzilla: NA CVE: NA In order to get register status earlier, this patch modifies the code timing to read register firstly and then go to sleep to wait. Signed-off-by: Guangbin Huang Reviewed-by: Peng Li Reviewed-by: Zhong Zhaohui Signed-off-by: Yang Yingliang --- drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c index 2e1fbcc5818f..33f7045ca460 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c @@ -3304,11 +3304,12 @@ static int hclge_reset_wait(struct hclge_dev *hdev) return -EINVAL; } - do { + val = hclge_read_dev(&hdev->hw, reg); + while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) { msleep(HCLGE_RESET_WATI_MS); val = hclge_read_dev(&hdev->hw, reg); cnt++; - } while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT); + } if (cnt >= HCLGE_RESET_WAIT_CNT) { dev_warn(&hdev->pdev->dev, -- GitLab